From d3a818ce28e5b9010ca30839178804faf954401f Mon Sep 17 00:00:00 2001 From: Shashank-Vijay Date: Tue, 29 Jun 2021 21:39:26 -0700 Subject: [PATCH 01/12] OP local changes --- piton/tools/src/proto/block.list | 2 +- piton/tools/src/proto/common/blackparrot.tcl | 1300 +++++++++++------ .../env/manycore/devices_blackparrot.xml | 2 +- piton/verif/env/manycore/pc_cmp.v.pyv | 4 +- 4 files changed, 850 insertions(+), 458 deletions(-) diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 04a332390..4ef553af9 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -25,7 +25,7 @@ # Format: # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 -system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768 +system . vc707,60,1024;genesys2,25,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768 chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 diff --git a/piton/tools/src/proto/common/blackparrot.tcl b/piton/tools/src/proto/common/blackparrot.tcl index 075f8fe36..648efe31b 100644 --- a/piton/tools/src/proto/common/blackparrot.tcl +++ b/piton/tools/src/proto/common/blackparrot.tcl @@ -1,165 +1,78 @@ set obj [get_filesets sources_1] set BLACKPARROT_RTL_IMPL_FILES [list \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_links.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_defines.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_cin.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf_ctrl.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nor2.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_csr_defines.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_defines.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_pkg.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_bypass.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_me_if.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_fe_be_if.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_defines.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_pkg.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_defines.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_pkg.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_internal_if_defines.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_ctl_defines.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_mem_defines.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_pkg.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_calculator_top.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cfg_link_pkg.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_csr.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_wbuf_entry.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_pkt.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_pkg.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_pipeline.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_decoder.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_detector.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_director.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_instr_decoder.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_int_alu.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_ctrl.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_fp.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_int.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_long.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mem.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mul.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_sys.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_ptw.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_regfile.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_scheduler.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_top.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_me_cce_mem_if.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_me_pkg.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_cce_inst.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_cce_pkg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_pce_l15_if.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_pce_pkg.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_pkg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_complex.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_alu.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_arbitrate.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_branch.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_lru_extract.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_segment.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_tag_checker.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_fsm.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_gad.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_decode.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_predecode.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_ram.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_stall.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/test/common/bp_cce_mmio_cfg_loader.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_msg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_pending_bits.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_reg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_spec_bits.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_src_sel.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_wrapper.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cfg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_clint_slice.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_mem_defines.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_defines.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_pkg.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_complex.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_pkg.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_minimal.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_bht.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_btb.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_icache.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_instr_scan.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_mem.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_pc_gen.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_top.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_req.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_cmd.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_pce.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_io_cce.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_complex.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_link_to_lce.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile_node.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_addr_to_cce_id.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cache_dma_to_cce.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cache_slice.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_id_to_cord.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cce_to_cache.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cce_to_cache_dma.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_mem_wormhole.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_client.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_master.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cord_to_id.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_lce_id_to_cord.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_mem_complex.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_nd_socket.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_pma.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_multicore.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_unicore.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_complex.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile_node.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_piton_top.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_tlb.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_arb_fixed.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_one_hot.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_concentrate_static.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_reverse.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/include/bp_top_pkg.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_async_fifo.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bsg_async_noc_link.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_launch_sync_sync.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_async_ptr_gray.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_decode.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_dma.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_miss.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf_queue.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_rx.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_tx.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_in.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_out.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged_fifo.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_large.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1rw_large.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_tracker.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_flow_counter.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_one_fifo.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_passthrough.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_1_to_n.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_2_to_2.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_n_to_1.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_full.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_passthrough.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_shift_reg.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_two_fifo.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_replacement.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_sync.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_tag_array.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_one_hot.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_synth.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_synth.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync_synth.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync_synth.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_cin.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_one_hot.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_ripple_carry.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_arb_fixed.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_concentrate_static.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf_ctrl.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_circular_ptr.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_clkgate_optional.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_concentrate_static.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up_one_hot.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_set_down.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_set_en.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_overflow_en.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_up_down.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_crossbar_o_by_i.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_cycle_counter.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_decode.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_decode_with_v.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff.v" \ @@ -170,65 +83,41 @@ set BLACKPARROT_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_set_clear.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dlatch.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_edge_detect.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_encode_one_hot.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_expand_bitmask.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_fifo_1r1w_rolly.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_hardened.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_tracker.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_flow_counter.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_hash_bank.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_hash_bank_reverse.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative_controller.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_launch_sync_sync.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lfsr.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_decode.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_encode.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_one_hot.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_mesh_stitch.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_bitwise.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_butterfly.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_one_hot.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_segmented.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_muxi2_gatestack.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nand.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nor2.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nor3.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_one_fifo.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nand.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_priority_encode.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_priority_encode_one_hot_out.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_reduce.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_reduce_segmented.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_rotate_left.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_rotate_right.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_1_to_n.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_n_to_1.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_scan.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_full.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_shift_reg.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_strobe.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_swap.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_thermometer_count.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_transpose.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_two_fifo.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_unconcentrate_static.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_xnor.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_mesh_stitch.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_repeater_node.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_in.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_out.v" \ @@ -239,7 +128,179 @@ set BLACKPARROT_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_decoder_dor.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_input_control.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_output_control.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_xnor.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/addRecFN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/compareRecFN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/divSqrtRecFN_small.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/fNToRecFN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_primitives.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_consts.vi" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_rawFN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/iNToRecFN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/isSigNaNRecFN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/mulAddRecFN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/mulRecFN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToFN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToIN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToRecFN.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/RISCV/HardFloat_specialize.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/RISCV/HardFloat_specialize.vi" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_fifo_1r1w_rolly.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_bus_pack.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_pma.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_mmu.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_tlb.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_top.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_calculator_top.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_csr.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_int.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_long.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mem.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_sys.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_aux.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_ctl.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_fma.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_fp_to_rec.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_ptw.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_rec_to_fp.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_cmd_queue.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_detector.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_director.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_instr_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_issue_queue.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_regfile.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_scheduler.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_scoreboard.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_wbuf.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_bht.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_btb.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_icache.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_instr_scan.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_pc_gen.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_top.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_req.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_cmd.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cce_to_cache.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_alu.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_arbitrate.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_branch.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_lru_extract.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_segment.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_tag_checker.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_fsm.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_gad.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_decode.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_predecode.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_ram.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_stall.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/test/common/bp_cce_mmio_cfg_loader.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_msg.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_pending_bits.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_pma.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_reg.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_spec_bits.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_src_sel.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_io_cce.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_uce.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_pce.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_addr_to_cce_id.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_id_to_cord.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_bidir.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_client.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_master.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cord_to_id.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_lce_id_to_cord.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_lite_to_stream.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_stream_to_lite.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_lite_to_burst.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_burst_to_lite.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_loopback.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_nd_socket.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_vdp.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_tile.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_tile_node.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_complex.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_vdp.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_tile.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_tile_node.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_complex.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cfg.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_minimal.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_complex.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_clint_slice.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_l2e_tile.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_l2e_tile_node.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_complex.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_link_to_lce.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile_node.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_mem_complex.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_multicore.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_unicore.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile_node.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_piton_top.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_async_noc_link.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_cache_dma_to_wormhole.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_dff_reset_half.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_wormhole_to_cache_dma_fanout.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.vh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_links.vh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_defines.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_instr_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_core_if.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_core_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_log_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_csr_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_bedrock_if.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_bedrock_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cache_engine_if.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cache_engine_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cfg_bus_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cfg_bus_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_addr_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_addr_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_ctl_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_pce_l15_if.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_inst_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_inst_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_wormhole_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/include/bp_top_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_pkg.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_decompress.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_defines.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_reverse.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_rx.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_tx.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_clkgate_optional.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dlatch.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v" \ ] add_files -norecurse -fileset $obj $BLACKPARROT_RTL_IMPL_FILES @@ -261,1172 +322,1503 @@ set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj set_property -name "is_global_include" -value "1" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_csr_defines.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_pkg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_defines.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_pkg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_pkg.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_pkg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_bypass.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_pkg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_me_if.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/include/bp_top_pkg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_fe_be_if.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_async_fifo.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_defines.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_launch_sync_sync.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_pkg.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_async_ptr_gray.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_defines.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_decode.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_dma.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_miss.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf_queue.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_in.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_out.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged_fifo.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged.v" -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_pkg.vh" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_large.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1rw_large.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_tracker.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_internal_if_defines.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_flow_counter.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_one_fifo.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_passthrough.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_1_to_n.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_2_to_2.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_n_to_1.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_full.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_passthrough.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_shift_reg.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_two_fifo.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_replacement.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_sync.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_tag_array.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_one_hot.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_synth.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +#set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" +# +#set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +#set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +#set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v" +# +#set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +#set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_synth.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync_synth.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync_synth.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_cin.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_one_hot.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_ripple_carry.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_arb_fixed.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_concentrate_static.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf_ctrl.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_circular_ptr.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_concentrate_static.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up_one_hot.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_set_down.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_set_en.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_overflow_en.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_up_down.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_crossbar_o_by_i.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_ctl_defines.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_cycle_counter.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_mem_defines.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_decode.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_pkg.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_decode_with_v.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_calculator_top.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cfg_link_pkg.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_chain.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_csr.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_en.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_wbuf_entry.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_en_bypass.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_pkt.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en_bypass.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_pkg.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_pipeline.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_set_clear.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_decoder.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_edge_detect.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_encode_one_hot.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_expand_bitmask.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_detector.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_hash_bank.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_director.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_hash_bank_reverse.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_instr_decoder.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_int_alu.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative_controller.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_ctrl.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lfsr.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_fp.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_decode.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_int.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_encode.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_long.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mem.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_bitwise.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mul.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_butterfly.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_sys.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_one_hot.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_mem/bp_be_ptw.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_segmented.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_regfile.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_muxi2_gatestack.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_scheduler.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nor2.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_top.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nand.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_me_cce_mem_if.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nor3.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_me_pkg.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_priority_encode.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_cce_inst.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_priority_encode_one_hot_out.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_cce_pkg.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_reduce.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_pce_l15_if.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_reduce_segmented.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_pce_pkg.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_rotate_left.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_pkg.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_rotate_right.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_complex.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_scan.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_strobe.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_alu.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_swap.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_arbitrate.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_transpose.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_branch.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_thermometer_count.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_unconcentrate_static.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_lru_extract.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_xnor.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_segment.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_mesh_stitch.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_tag_checker.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_repeater_node.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_fsm.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_gad.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_in.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_decode.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_out.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_predecode.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_ram.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_stall.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_in.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/test/common/bp_cce_mmio_cfg_loader.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_out.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_msg.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_decoder_dor.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_pending_bits.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_input_control.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_reg.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_output_control.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_spec_bits.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/addRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_src_sel.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/compareRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_wrapper.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/divSqrtRecFN_small.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cfg.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/fNToRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_clint_slice.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_primitives.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_mem_defines.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_consts.vi" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_defines.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_rawFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/iNToRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "Verilog Header" -objects $file_obj +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_pkg.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/isSigNaNRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/mulAddRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_complex.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/mulRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_pkg.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_minimal.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToIN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_bht.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_btb.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/RISCV/HardFloat_specialize.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_icache.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/RISCV/HardFloat_specialize.vi" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_instr_scan.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_mem.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_pc_gen.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_instr_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_top.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_core_if.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_req.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_core_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_cmd.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_pce.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_log_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_io_cce.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_csr_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_complex.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_bedrock_if.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_link_to_lce.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_bedrock_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cache_engine_if.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile_node.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cache_engine_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_addr_to_cce_id.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cfg_bus_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cfg_bus_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cache_dma_to_cce.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_addr_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cache_slice.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_addr_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_id_to_cord.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_ctl_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cce_to_cache.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cce_to_cache_dma.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/v/bp_mem_wormhole.vh" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/include/bp_top_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_client.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_top.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_master.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_calculator_top.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cord_to_id.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_csr.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_lce_id_to_cord.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_fp_to_rec.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_rec_to_fp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_int.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_aux.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_ctl.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_fma.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_mem_complex.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_long.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_nd_socket.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mem.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_pma.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_sys.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_multicore.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_ptw.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_unicore.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_cmd_queue.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_complex.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_detector.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_director.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile_node.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_instr_decoder.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_piton_top.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_issue_queue.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_tlb.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_regfile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_arb_fixed.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_scheduler.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_one_hot.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_scoreboard.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_concentrate_static.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_reverse.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_decoder.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_async_fifo.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_wbuf.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bsg_async_noc_link.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_pce_l15_if.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_async_ptr_gray.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_inst_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_inst_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_decode.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_dma.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_wormhole_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_miss.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_pkg.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf_queue.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_alu.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_rx.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_arbitrate.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_tx.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_branch.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_replacement.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_lru_extract.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_sync.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_segment.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_tag_array.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_tag_checker.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_circular_ptr.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_fsm.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_clkgate_optional.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_gad.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_concentrate_static.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_decode.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_predecode.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_set_down.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_ram.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_set_en.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_stall.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_up_down.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/test/common/bp_cce_mmio_cfg_loader.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_msg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_crossbar_o_by_i.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_pending_bits.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_decode.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_pma.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_decode_with_v.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_reg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_spec_bits.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_chain.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_src_sel.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_en.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_io_cce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_en_bypass.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_wrapper.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en_bypass.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_decompress.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_set_clear.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_pkgdef.svh" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "Verilog Header" -objects $file_obj + +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_bht.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dlatch.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_btb.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_edge_detect.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_icache.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_encode_one_hot.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_instr_scan.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_expand_bitmask.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_pc_gen.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_fifo_1r1w_rolly.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_top.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_hardened.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_req.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_cmd.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_tracker.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_uce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_flow_counter.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_pce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_hash_bank.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cce_to_cache.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_addr_to_cce_id.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative_controller.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_id_to_cord.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_launch_sync_sync.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_bidir.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_decode.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_client.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_encode.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_master.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cord_to_id.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_one_hot.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_lce_id_to_cord.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_synth.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_lite_to_stream.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_stream_to_lite.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_synth.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_lite_to_burst.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_burst_to_lite.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync_synth.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_loopback.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_mesh_stitch.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_nd_socket.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_vdp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_bitwise.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_tile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_butterfly.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_tile_node.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_one_hot.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_complex.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_segmented.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_vdp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_muxi2_gatestack.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_tile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nand.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_tile_node.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nor3.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_complex.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_one_fifo.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cfg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_minimal.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_priority_encode.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_complex.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_priority_encode_one_hot_out.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_clint_slice.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_reduce.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_l2e_tile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_reduce_segmented.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_l2e_tile_node.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_rotate_left.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_complex.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_rotate_right.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_link_to_lce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_1_to_n.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile_node.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_n_to_1.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_scan.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_mem_complex.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_multicore.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_unicore.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_full.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_shift_reg.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile_node.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_strobe.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_piton_top.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_swap.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_fifo_1r1w_rolly.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_transpose.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_bus_pack.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_two_fifo.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_mmu.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_unconcentrate_static.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_pma.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_tlb.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_in.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_reverse.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_out.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_async_noc_link.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_cache_dma_to_wormhole.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_dff_reset_half.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_in.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_wormhole_to_cache_dma_fanout.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_out.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_decoder_dor.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_rx.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_input_control.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_tx.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_output_control.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_clkgate_optional.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_xnor.v" +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dlatch.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + diff --git a/piton/verif/env/manycore/devices_blackparrot.xml b/piton/verif/env/manycore/devices_blackparrot.xml index 82fdd3bff..914ce5a05 100644 --- a/piton/verif/env/manycore/devices_blackparrot.xml +++ b/piton/verif/env/manycore/devices_blackparrot.xml @@ -23,7 +23,7 @@ Description: Peripheral address map for OpenPiton+BlackParrot configurations. mem 0x80000000 - 0x40000000 + 0x08000000 iob diff --git a/piton/verif/env/manycore/pc_cmp.v.pyv b/piton/verif/env/manycore/pc_cmp.v.pyv index c393673cb..3154792e9 100644 --- a/piton/verif/env/manycore/pc_cmp.v.pyv +++ b/piton/verif/env/manycore/pc_cmp.v.pyv @@ -258,8 +258,8 @@ endtask // get_thread_status end always @(posedge clk) begin - spc0_inst_done <= `BLACKPARROT_CORE0.core.be.calculator.commit_pkt.instret; - spc0_phy_pc_w <= 48'($signed(48'(`BLACKPARROT_CORE0.core.be.calculator.commit_pkt.pc))); + spc0_inst_done <= `BLACKPARROT_CORE0.be.calculator.commit_pkt_cast_o.instret; + spc0_phy_pc_w <= 48'($signed(48'(`BLACKPARROT_CORE0.be.calculator.commit_pkt_cast_o.pc))); end `else `ifdef RTL_PICO0 From c4d8f32ae4280c441768af9819cf3afaef3af535 Mon Sep 17 00:00:00 2001 From: Shashank-Vijay Date: Tue, 29 Jun 2021 21:40:04 -0700 Subject: [PATCH 02/12] Bumping BP submodule --- piton/design/chip/tile/blackparrot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/tile/blackparrot b/piton/design/chip/tile/blackparrot index 3d6aac661..58ed5cb76 160000 --- a/piton/design/chip/tile/blackparrot +++ b/piton/design/chip/tile/blackparrot @@ -1 +1 @@ -Subproject commit 3d6aac66133b9da8c8e5294e09fac9550529c381 +Subproject commit 58ed5cb761565715dc2d32ea7b6c12c2906a1ef2 From a509765a9a7e292164f13a5da882d73b0aa321df Mon Sep 17 00:00:00 2001 From: Shashank-Vijay Date: Thu, 8 Jul 2021 17:06:41 -0700 Subject: [PATCH 03/12] More changes --- piton/design/xilinx/genesys2/constraints.xdc | 3 +++ piton/tools/bin/rv64_img | 1 + piton/tools/src/sims/sims,2.0 | 4 ++++ 3 files changed, 8 insertions(+) diff --git a/piton/design/xilinx/genesys2/constraints.xdc b/piton/design/xilinx/genesys2/constraints.xdc index f3ad24085..110a5cf21 100644 --- a/piton/design/xilinx/genesys2/constraints.xdc +++ b/piton/design/xilinx/genesys2/constraints.xdc @@ -58,6 +58,9 @@ set_false_path -from [get_ports trst_ni] set_max_delay -datapath_only -from [get_clocks -include_generated_clocks chipset_clk_clk_mmcm] -to [get_clocks tck_i] 15.000 set_max_delay -datapath_only -from [get_clocks tck_i] -to [get_clocks -include_generated_clocks chipset_clk_clk_mmcm] 15.000 +# Retiming +set_property BLOCK_SYNTH.RETIMING 1 [get_cells -hierarchical *pipe_fma*] + set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVCMOS33} [get_ports trst_ni] set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVCMOS33} [get_ports tck_i] set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVCMOS33} [get_ports td_i] diff --git a/piton/tools/bin/rv64_img b/piton/tools/bin/rv64_img index 6ed284e23..cfeb9d140 100755 --- a/piton/tools/bin/rv64_img +++ b/piton/tools/bin/rv64_img @@ -27,6 +27,7 @@ # create mem.image #riscv64-unknown-elf-objcopy --reverse-bytes 4 -I elf32-littleriscv -O binary diag.exe diag.o ${RV64_TARGET_TRIPLE}-objcopy -I elf64-littleriscv -O binary diag.exe diag.o +cp diag.exe prog.elf # pad with zero to 128byte boundary du diag.o -b | awk '{print(128 - ($1 % 128));}' | xargs -t -ISIZE truncate diag.o -s +SIZE printf "\n@0000000080000000\t// Section '.RED_SEC', segment 'text'\n" >mem.image diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index 44af72751..5418db4ce 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -2676,6 +2676,7 @@ sub parse_args 'gui!', 'log_all!', 'debug_all!', + 'debug_pp!', 'ibm!', 'ed_enable!', 'ed_sync_method=s', @@ -2900,6 +2901,9 @@ sub parse_args # push (@{$opt{sim_run_args}}, "-gui") if ($opt{gui}) ; push (@{$opt{vcs_build_args}}, "-debug_all") if ($opt{debug_all}) ; + push (@{$opt{vcs_build_args}}, "-debug_pp") if ($opt{debug_pp}) ; + push (@{$opt{vcs_build_args}}, "-CFLAGS \"-I/mnt/users/ssd1/homes/svijay97/BlackParrot/black-parrot-sdk/include -std=c++14\"") ; + push (@{$opt{vcs_build_args}}, "/mnt/users/ssd1/homes/svijay97/BlackParrot/black-parrot-sdk/lib/libdromajo_cosim.a") ; # Push optional execution drafting enable push (@{$opt{midas_args}}, "-DED_ENABLE") if ($opt{ed_enable}); From 9ded7e8142940c3e63043be7cb946d78c44330b5 Mon Sep 17 00:00:00 2001 From: Shashank-Vijay Date: Thu, 8 Jul 2021 22:46:55 -0700 Subject: [PATCH 04/12] Minor changes --- piton/design/chipset/rtl/chipset_impl.v.pyv | 10 ++++++---- piton/design/chipset/rtl/packet_filter.v.pyv | 11 +---------- piton/design/chipset/rtl/storage_addr_trans.v.pyv | 6 +++--- .../chipset/rtl/storage_addr_trans_unified.v.pyv | 6 +++--- 4 files changed, 13 insertions(+), 20 deletions(-) diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 0735e45fe..eadf890df 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -946,8 +946,8 @@ uart_top uart_top ( `endif // PITONSYS_NO_MC // Uncomment to connect to the switch - // .uart_timeout_en(uart_timeout_en), - .uart_timeout_en ( 1'b1 ), + .uart_timeout_en(uart_timeout_en), + // .uart_timeout_en ( 1'b1 ), .test_start ( test_start ), .test_good_end ( test_good_end ), @@ -1066,8 +1066,10 @@ ciop_fake_iob ciop_fake_iob( <% text = r''' - .spc0_inst_done (`PITON_CORE0_INST_DONE), - .pc_w0 (`PITON_CORE0_PC_W0), + `ifndef DISABLE_ALL_MONITORS + .spc0_inst_done (`PITON_CORE0_INST_DONE), + .pc_w0 (`PITON_CORE0_PC_W0), + `endif ''' for i in range (PITON_NUM_TILES): diff --git a/piton/design/chipset/rtl/packet_filter.v.pyv b/piton/design/chipset/rtl/packet_filter.v.pyv index de8bff17a..4cbe4f842 100644 --- a/piton/design/chipset/rtl/packet_filter.v.pyv +++ b/piton/design/chipset/rtl/packet_filter.v.pyv @@ -325,14 +325,6 @@ for i in range(1, len(devices)): outputstr = """ else begin -`ifdef PITON_FPGA_SYNTH - // route everything else to the memory when uart_boot_en is asserted - if (%s (uart_boot_en)) begin - readdressed_flit0[`MSG_DST_X] = `NOC_X_WIDTH'h%x; - end else begin - invalid_access = 1'b1; - end -`else // PITON_FPGA_SYNTH `ifdef MONITOR_INVALID_ACCESSES // route everything else to the memory when uart_boot_en is asserted if (%s (uart_boot_en)) begin @@ -344,9 +336,8 @@ outputstr = """ // route everything else to the memory in simulation readdressed_flit0[`MSG_DST_X] = `NOC_X_WIDTH'h%x; `endif // MONITOR_INVALID_ACCESSES -`endif // PITON_FPGA_SYNTH end -""" % (mem_addr_range, mem_port, mem_addr_range, mem_port, mem_port) +""" % (mem_addr_range, mem_port, mem_port) print(outputstr) %> end diff --git a/piton/design/chipset/rtl/storage_addr_trans.v.pyv b/piton/design/chipset/rtl/storage_addr_trans.v.pyv index 872f9dd49..10236dc47 100644 --- a/piton/design/chipset/rtl/storage_addr_trans.v.pyv +++ b/piton/design/chipset/rtl/storage_addr_trans.v.pyv @@ -33,7 +33,7 @@ import pyhplib import os from pyhplib import * -if PITON_ARIANE: +if PITON_BLACKPARROT: devices = pyhplib.ReadDevicesXMLFile() %> @@ -46,7 +46,7 @@ module storage_addr_trans #(parameter MEM_ADDR_WIDTH=64, VA_ADDR_WIDTH=40, STORA output hit_any_section ); -`ifdef PITON_ARIANE +`ifdef PITON_BLACKPARROT wire [63:0] storage_addr; @@ -56,7 +56,7 @@ wire in_section_0; // align physical address, and use correct memory offsets as specified in platform config <% -if PITON_ARIANE: +if PITON_BLACKPARROT: for i in range(len(devices)): if devices[i]["name"] == "mem": memBegin = devices[i]["base"] diff --git a/piton/design/chipset/rtl/storage_addr_trans_unified.v.pyv b/piton/design/chipset/rtl/storage_addr_trans_unified.v.pyv index 2df01f06b..9eff12162 100644 --- a/piton/design/chipset/rtl/storage_addr_trans_unified.v.pyv +++ b/piton/design/chipset/rtl/storage_addr_trans_unified.v.pyv @@ -33,7 +33,7 @@ import pyhplib import os from pyhplib import * -if PITON_ARIANE: +if PITON_BLACKPARROT: devices = pyhplib.ReadDevicesXMLFile() %> @@ -46,7 +46,7 @@ module storage_addr_trans_unified #(parameter MEM_ADDR_WIDTH=64, VA_ADDR_WIDTH=4 output hit_any_section ); -`ifdef PITON_ARIANE +`ifdef PITON_BLACKPARROT wire [63:0] storage_addr; @@ -56,7 +56,7 @@ wire in_section_0; // align physical address, and use correct memory offsets as specified in platform config <% -if PITON_ARIANE: +if PITON_BLACKPARROT: for i in range(len(devices)): if devices[i]["name"] == "mem": memBegin = devices[i]["base"] From c4c6e5f189034ae493a28264da3d518867102683 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Mon, 12 Jul 2021 14:51:55 -0700 Subject: [PATCH 05/12] Update sims,2.0 --- piton/tools/src/sims/sims,2.0 | 2 ++ 1 file changed, 2 insertions(+) diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index 5418db4ce..842161aed 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -2832,6 +2832,7 @@ sub parse_args $ENV{BP_ME_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/bp_me"; $ENV{BP_BE_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/bp_be"; $ENV{BP_TOP_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/bp_top"; + $ENV{HARDFLOAT_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/external/HardFloat"; push (@{$opt{config_rtl}}, "PITON_OST1") if ($opt{ost1}); push (@{$opt{config_rtl}}, "PITON_PICO") if ($opt{pico}); push (@{$opt{config_rtl}}, "PITON_PICO") if ($opt{pico_het}); @@ -2900,6 +2901,7 @@ sub parse_args # push (@{$opt{sim_run_args}}, "-gui") if ($opt{gui}) ; + push (@{$opt{vcs_build_args}}, "-assert svaext") ; push (@{$opt{vcs_build_args}}, "-debug_all") if ($opt{debug_all}) ; push (@{$opt{vcs_build_args}}, "-debug_pp") if ($opt{debug_pp}) ; push (@{$opt{vcs_build_args}}, "-CFLAGS \"-I/mnt/users/ssd1/homes/svijay97/BlackParrot/black-parrot-sdk/include -std=c++14\"") ; From da77c232425ba9d016e22fabeff99e8ec0476edb Mon Sep 17 00:00:00 2001 From: Shashank-Vijay Date: Fri, 16 Jul 2021 11:21:33 -0700 Subject: [PATCH 06/12] Cosim module addition --- piton/verif/env/manycore/manycore_top.v.pyv | 42 +++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/piton/verif/env/manycore/manycore_top.v.pyv b/piton/verif/env/manycore/manycore_top.v.pyv index 364109d04..a0a1649fe 100644 --- a/piton/verif/env/manycore/manycore_top.v.pyv +++ b/piton/verif/env/manycore/manycore_top.v.pyv @@ -570,6 +570,48 @@ system system( $display("UART: TX changed to %d at", tx, $time); end*/ +`ifdef ENABLE_COSIM + // Bind cosim module + bind bp_be_top + bp_nonsynth_cosim + #(.bp_params_p(bp_params_p)) + cosim + (.clk_i(clk_i) + ,.reset_i(~cmp_top.sys_rst_n) + ,.freeze_i(calculator.pipe_sys.csr.cfg_bus_cast_i.freeze) + + // We want to pass these values as parameters, but cannot in Verilator 4.025 + // Parameter-resolved constants must not use dotted references + ,.cosim_en_i(1'b1) + ,.trace_en_i(1'b1) + ,.checkpoint_i(1'b0) + ,.num_core_i(1) + ,.mhartid_i(calculator.pipe_sys.csr.cfg_bus_cast_i.core_id) + ,.config_file_i("prog.cfg") + ,.instr_cap_i(0) + ,.memsize_i(256) + ,.amo_en_i(1) + + ,.decode_i(calculator.reservation_n.decode) + + ,.is_debug_mode_i(calculator.pipe_sys.csr.is_debug_mode) + ,.commit_pkt_i(calculator.commit_pkt_cast_o) + + ,.priv_mode_i(calculator.pipe_sys.csr.priv_mode_r) + ,.mstatus_i(calculator.pipe_sys.csr.mstatus_lo) + ,.mcause_i(calculator.pipe_sys.csr.mcause_lo) + ,.scause_i(calculator.pipe_sys.csr.scause_lo) + + ,.ird_w_v_i(scheduler.iwb_pkt_cast_i.ird_w_v) + ,.ird_addr_i(scheduler.iwb_pkt_cast_i.rd_addr) + ,.ird_data_i(scheduler.iwb_pkt_cast_i.rd_data) + + ,.frd_w_v_i(scheduler.fwb_pkt_cast_i.frd_w_v) + ,.frd_addr_i(scheduler.fwb_pkt_cast_i.rd_addr) + ,.frd_data_i(scheduler.fwb_pkt_cast_i.rd_data) + ); +`endif // ENABLE_COSIM + endmodule // cmp_top `endif From 274a5174a69892c5b333be361acd5938716ccd5e Mon Sep 17 00:00:00 2001 From: Jonathan Balkind Date: Fri, 24 Jul 2020 12:22:23 -0400 Subject: [PATCH 07/12] Working cacheable-only $readmemh memory for simulation Base and size configurable with parameters (using defaults for now) Compile with -config_rtl=PITON_SIM_MEMORY Use by taking compiled diag.o and running: xxd -g 8 -c 64 diag.o | awk '{printf("%s%s%s%s%s%s%s%s\n", $9, $8, $7, $6, $5, $4, $3, $2);}' > sim_memory.memh sim_memory.memh should be put in the same location that mem.image would normally live --- piton/verif/env/common/fake_mem_ctrl.v | 106 ++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 1 deletion(-) diff --git a/piton/verif/env/common/fake_mem_ctrl.v b/piton/verif/env/common/fake_mem_ctrl.v index 652850a80..3eab290d9 100644 --- a/piton/verif/env/common/fake_mem_ctrl.v +++ b/piton/verif/env/common/fake_mem_ctrl.v @@ -43,7 +43,12 @@ `define MEM_ADDR_WIDTH 64 -module fake_mem_ctrl( +module fake_mem_ctrl #( +`ifdef PITON_SIM_MEMORY + parameter [63:0] MEM_BASE = 64'h0000000080000000, + parameter [63:0] SIZE_BYTES = 64'h0000000040000000 +`endif +) ( input wire clk, input wire rst_n, @@ -73,6 +78,15 @@ reg [`MSG_LENGTH_WIDTH-1:0] buf_in_counter_next; reg [3:0] buf_in_wr_ptr_f; reg [3:0] buf_in_wr_ptr_next; +`ifdef PITON_SIM_MEMORY +reg sim_memory_write; +reg [511:0] sim_memory_wr_data; +reg [63:0] sim_memory_wr_addr; +reg [63:0] sim_memory_rd_addr; +reg [511:0] sim_memory [SIZE_BYTES/(64*8)-1:0]; +// reg [SIZE_BYTES-1:0] sim_memory; +`endif + always @ * begin noc_ready_in = (buf_in_counter_f == 0) || (buf_in_counter_f < (buf_in_mem_f[0][`MSG_LENGTH]+1)); @@ -243,6 +257,7 @@ begin end +`ifndef PITON_SIM_MEMORY always @ * begin // initialize to get rid of msim warnings @@ -564,6 +579,95 @@ begin end end +`else // ifndef PITON_SIM_MEMORY + +always @ * +begin + mem_temp = `NOC_DATA_WIDTH'h0; + sim_memory_write = 1'b0; + sim_memory_rd_addr = 64'b0; + if (mem_valid_in) + begin + case (msg_type) + `MSG_TYPE_LOAD_MEM: + begin + sim_memory_rd_addr = {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b000000} - MEM_BASE; + $display("fake_mem_ctrl.v: true read addr: %h", sim_memory_rd_addr); + msg_send_data[0] = sim_memory[sim_memory_rd_addr[63:6]][9'b000000000+:64]; + msg_send_data[1] = sim_memory[sim_memory_rd_addr[63:6]][9'b001000000+:64]; + msg_send_data[2] = sim_memory[sim_memory_rd_addr[63:6]][9'b010000000+:64]; + msg_send_data[3] = sim_memory[sim_memory_rd_addr[63:6]][9'b011000000+:64]; + msg_send_data[4] = sim_memory[sim_memory_rd_addr[63:6]][9'b100000000+:64]; + msg_send_data[5] = sim_memory[sim_memory_rd_addr[63:6]][9'b101000000+:64]; + msg_send_data[6] = sim_memory[sim_memory_rd_addr[63:6]][9'b110000000+:64]; + msg_send_data[7] = sim_memory[sim_memory_rd_addr[63:6]][9'b111000000+:64]; +`ifndef MINIMAL_MONITORING + $display("MemRead: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b000000}, msg_send_data[0]); + $display("MemRead: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b001000}, msg_send_data[1]); + $display("MemRead: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b010000}, msg_send_data[2]); + $display("MemRead: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b011000}, msg_send_data[3]); + $display("MemRead: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b100000}, msg_send_data[4]); + $display("MemRead: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b101000}, msg_send_data[5]); + $display("MemRead: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b110000}, msg_send_data[6]); + $display("MemRead: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b111000}, msg_send_data[7]); +`endif + msg_send_type = `MSG_TYPE_LOAD_MEM_ACK; + msg_send_length = 8'd8; + end + `MSG_TYPE_STORE_MEM: + begin + sim_memory_write = 1'b1; + sim_memory_wr_addr = {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b000000} - MEM_BASE; + $display("fake_mem_ctrl.v: true write addr: %h", sim_memory_wr_addr); + sim_memory_wr_data = {buf_in_mem_f[10], buf_in_mem_f[9], buf_in_mem_f[8], buf_in_mem_f[7], buf_in_mem_f[6], buf_in_mem_f[5], buf_in_mem_f[4], buf_in_mem_f[3]}; +`ifndef MINIMAL_MONITORING + $display("MemWrite: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b000000}, buf_in_mem_f[3]); + $display("MemWrite: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b001000}, buf_in_mem_f[4]); + $display("MemWrite: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b010000}, buf_in_mem_f[5]); + $display("MemWrite: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b011000}, buf_in_mem_f[6]); + $display("MemWrite: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b100000}, buf_in_mem_f[7]); + $display("MemWrite: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b101000}, buf_in_mem_f[8]); + $display("MemWrite: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b110000}, buf_in_mem_f[9]); + $display("MemWrite: %h : %h", {{(`MEM_ADDR_WIDTH-`PHY_ADDR_WIDTH){1'b0}}, msg_addr[`L2_TAG],msg_addr[`L2_TAG_INDEX],6'b111000}, buf_in_mem_f[10]); +`endif + msg_send_type = `MSG_TYPE_STORE_MEM_ACK; + msg_send_length = 8'd0; + end + default: + begin + msg_send_type = `MSG_TYPE_ERROR; + msg_send_length = 8'd0; + end + endcase + end +end + +//generate for (int i = 0; i < (SIZE_BYTES/64; i = i + 1) begin : gen_sim_memory +//always @(posedge clk) begin +// //if (~rst_n) begin +// // sim_memory[i] <= 512'b0; +// //end else +// if (sim_memory_write & (sim_memory_wr_addr[63:6] == i) begin +// sim_memory[i] <= sim_memory_wr_data; +// end +//end +//end + +always @(posedge clk) begin + if (sim_memory_write) begin + sim_memory[sim_memory_wr_addr[63:6]] <= sim_memory_wr_data; + end +end + +initial begin + for (integer i = 0; i < SIZE_BYTES/(64*8); i = i + 1) begin + sim_memory[i] = 512'b0; + end + $readmemh("sim_memory.memh", sim_memory); +end + +`endif // ifndef PITON_SIM_MEMORY + l2_encoder encoder( .msg_dst_chipid (msg_src_chipid), .msg_dst_x (msg_src_x), From 204f3e87358a28a35bc776402fb3b7b5a48f1160 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Sun, 3 Oct 2021 16:46:51 -0700 Subject: [PATCH 08/12] Various updates needed to run OP --- piton/ariane_build_tools.sh | 48 +- .../ip_cores/afifo_w3_d16/afifo_w3_d16.xci | 149 +- .../ip_cores/afifo_w64_d16/afifo_w64_d16.xci | 149 +- .../ip_cores/fifo_w3_d16/fifo_w3_d16.xci | 149 +- .../ip_cores/fifo_w64_d16/fifo_w64_d16.xci | 149 +- piton/design/chip/tile/ariane | 2 +- piton/design/chip/tile/blackparrot | 2 +- .../ip_cores/atg_uart_init/atg_uart_init.xci | 443 ++++- .../bram_16384x512/bram_16384x512.xci | 127 +- .../ip_cores/bram_256x512/bram_256x512.xci | 127 +- .../ip_cores/mig_7series_0/mig_7series_0.xci | 1468 ++++++++++++++++- .../ip_cores/sd_cache_bram/sd_cache_bram.xci | 127 +- .../ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci | 149 +- .../ip_cores/sd_data_fifo/sd_data_fifo.xci | 149 +- .../afifo_w64_d128_std/afifo_w64_d128_std.xci | 149 +- .../mac_eth_axi_lite/mac_eth_axi_lite.xci | 70 +- piton/piton_settings.bash | 9 +- piton/tools/src/proto/block.list | 3 +- piton/tools/src/sims/sims,2.0 | 6 +- 19 files changed, 3379 insertions(+), 96 deletions(-) diff --git a/piton/ariane_build_tools.sh b/piton/ariane_build_tools.sh index aa4d3c559..55d6cf0bd 100755 --- a/piton/ariane_build_tools.sh +++ b/piton/ariane_build_tools.sh @@ -62,38 +62,38 @@ else # not all tools are required at the moment ci/make-tmp.sh ci/build-riscv-gcc.sh - ci/install-fesvr.sh + # ci/install-fesvr.sh # ci/build-riscv-tests.sh # ci/install-dtc.sh - ci/install-spike.sh + # ci/install-spike.sh # ci/get-torture.sh - ci/install-verilator.sh + # ci/install-verilator.sh - # build the RISCV tests if necessary - VERSION="7cc76ea83b4f827596158c8ba0763e93da65de8f" - cd tmp + # # build the RISCV tests if necessary + # VERSION="7cc76ea83b4f827596158c8ba0763e93da65de8f" + # cd tmp - [ -d riscv-tests ] || git clone https://github.com/riscv/riscv-tests.git - cd riscv-tests - git checkout $VERSION - git submodule update --init --recursive - autoconf - mkdir -p build + # [ -d riscv-tests ] || git clone https://github.com/riscv/riscv-tests.git + # cd riscv-tests + # git checkout $VERSION + # git submodule update --init --recursive + # autoconf + # mkdir -p build - # link in adapted syscalls.c such that the benchmarks can be used in the OpenPiton TB - cd benchmarks/common/ - rm syscalls.c util.h - ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/syscalls.c - ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/util.h - cd - + # # link in adapted syscalls.c such that the benchmarks can be used in the OpenPiton TB + # cd benchmarks/common/ + # rm syscalls.c util.h + # ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/syscalls.c + # ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/util.h + # cd - - cd build - ../configure --prefix=$ROOT/tmp/riscv-tests/build + # cd build + # ../configure --prefix=$ROOT/tmp/riscv-tests/build - make clean - make isa -j${NUM_JOBS} > /dev/null - make benchmarks -j${NUM_JOBS} > /dev/null - make install + # make clean + # make isa -j${NUM_JOBS} > /dev/null + # make benchmarks -j${NUM_JOBS} > /dev/null + # make install cd ${PITON_ROOT} echo diff --git a/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/afifo_w3_d16/afifo_w3_d16.xci b/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/afifo_w3_d16/afifo_w3_d16.xci index 812e757de..126969813 100644 --- a/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/afifo_w3_d16/afifo_w3_d16.xci +++ b/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/afifo_w3_d16/afifo_w3_d16.xci @@ -7,13 +7,124 @@ afifo_w3_d16 - + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 0 0 0 @@ -385,28 +496,58 @@ FIFO FIFO kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 4 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/afifo_w64_d16/afifo_w64_d16.xci b/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/afifo_w64_d16/afifo_w64_d16.xci index 1369d021c..7d54beded 100644 --- a/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/afifo_w64_d16/afifo_w64_d16.xci +++ b/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/afifo_w64_d16/afifo_w64_d16.xci @@ -7,13 +7,124 @@ afifo_w64_d16 - + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 0 0 0 @@ -385,28 +496,58 @@ FIFO FIFO kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 4 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/fifo_w3_d16/fifo_w3_d16.xci b/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/fifo_w3_d16/fifo_w3_d16.xci index dcf0a212e..c053c340b 100644 --- a/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/fifo_w3_d16/fifo_w3_d16.xci +++ b/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/fifo_w3_d16/fifo_w3_d16.xci @@ -7,13 +7,124 @@ fifo_w3_d16 - + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 0 0 0 @@ -385,28 +496,58 @@ FIFO FIFO kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 4 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/fifo_w64_d16/fifo_w64_d16.xci b/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/fifo_w64_d16/fifo_w64_d16.xci index 60856392e..6a1d0a0a6 100644 --- a/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/fifo_w64_d16/fifo_w64_d16.xci +++ b/piton/design/chip/chip_bridge/xilinx/genesys2/ip_cores/fifo_w64_d16/fifo_w64_d16.xci @@ -7,13 +7,124 @@ fifo_w64_d16 - + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 0 0 0 @@ -385,28 +496,58 @@ FIFO FIFO kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 4 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index cbbcf3565..18e24507f 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit cbbcf3565c3829b40288848e2a6a49be689e7922 +Subproject commit 18e24507f2116bd8c412654859c478e6e8f4224a diff --git a/piton/design/chip/tile/blackparrot b/piton/design/chip/tile/blackparrot index 58ed5cb76..5181ccacc 160000 --- a/piton/design/chip/tile/blackparrot +++ b/piton/design/chip/tile/blackparrot @@ -1 +1 @@ -Subproject commit 58ed5cb761565715dc2d32ea7b6c12c2906a1ef2 +Subproject commit 5181ccacc6657912eb00eaf653b2bbaa51358da2 diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci index c39a5b875..1b4fc7f89 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci @@ -7,10 +7,282 @@ atg_uart_init - + 65536 + 100000000 + 0 + 0.000 + 1 + 1 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + WRITE_ONLY + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 0 0 0 4 @@ -23,15 +295,16 @@ 1 0 16 - 0x0000000013A00FFF + 0x0000000013A00000 0x0000000013A00FFF 3 0 - 0x0000000013A00FFF - 0x0000000013A00FFF + 0x0000000012A00000 + 0x0000000012A00FFF 3 0 16 + no_mem_file_loaded 0 1 0 @@ -47,10 +320,10 @@ 0x00000400 256 1 - atg_uart_init_addr.mif - atg_uart_init_ctrl.mif - atg_uart_init_data.mif - atg_uart_init_mask.mif + atg_uart_init_addr.mem + atg_uart_init_ctrl.mem + atg_uart_init_data.mem + atg_uart_init_mask.mem "00000000000000000000000000000001" 0 5000 @@ -74,25 +347,29 @@ 32 1 0 - atg_uart_init_default_addrram.mif - atg_uart_init_default_cmdram.mif + atg_uart_init_default_addrram.mem + atg_uart_init_default_cmdram.mem NONE NONE NONE - atg_uart_init_default_prmram.mif - atg_uart_init_default_mstram.mif + atg_uart_init_default_prmram.mem + atg_uart_init_default_mstram.mem + 0 254 0xABCD 8 8 32 1 + 0 1 + Seed_Based 100 Read_Write 16 16 Custom + no_mem_file_loaded 0x5A5A 0x7C9B 16 @@ -197,25 +474,161 @@ 8 1080 kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 12 + 5 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci index 84904252b..1e2e7ff24 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci @@ -7,9 +7,88 @@ bram_16384x512 - + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 14 14 1 @@ -60,6 +139,8 @@ 1 16384 16384 + 1 + 1 512 512 0 @@ -126,6 +207,8 @@ 8kx2 false false + 1 + 1 512 512 false @@ -154,28 +237,64 @@ false Stand_Alone kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 5 + 3 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci index 124a0ffde..632ae8f1a 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci @@ -7,9 +7,88 @@ bram_256x512 - + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 8 8 1 @@ -60,6 +139,8 @@ 1 256 256 + 1 + 1 512 512 0 @@ -126,6 +207,8 @@ 8kx2 false false + 1 + 1 512 512 false @@ -154,28 +237,64 @@ false Stand_Alone kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 5 + 3 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci b/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci index 506fc8d7c..ea2418ffe 100644 --- a/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci +++ b/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci @@ -7,8 +7,1151 @@ mig_7series_0 - + + 0 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 32 32 32 @@ -1162,28 +2305,345 @@ Custom mig_a.prj kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 2 + 1 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci index e46abc50c..b05164ed0 100644 --- a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci +++ b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci @@ -7,9 +7,88 @@ sd_cache_bram - + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 9 9 1 @@ -60,6 +139,8 @@ 1 512 512 + 1 + 1 64 64 0 @@ -126,6 +207,8 @@ 8kx2 false false + 1 + 1 64 64 false @@ -154,28 +237,64 @@ false Stand_Alone kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 5 + 3 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci index 2a58d39f4..f28a882ba 100644 --- a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci +++ b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci @@ -7,13 +7,124 @@ sd_ctrl_fifo - + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 0 0 0 @@ -385,28 +496,58 @@ FIFO FIFO kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 4 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci index eeae03d3d..5a7d19d2e 100644 --- a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci +++ b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci @@ -7,13 +7,124 @@ sd_data_fifo - + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 0 0 0 @@ -385,28 +496,58 @@ FIFO FIFO kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 4 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci index 454104a47..9523c8d69 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci @@ -7,13 +7,124 @@ afifo_w64_d128_std - + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 0 0 0 @@ -385,28 +496,58 @@ FIFO FIFO kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 4 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci index 8ec9fc732..46fc0917d 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci @@ -9,6 +9,44 @@ mac_eth_axi_lite + 1 + false + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 0 1 kintex7 1 @@ -37,25 +75,51 @@ Custom false kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 9 + 17 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/piton_settings.bash b/piton/piton_settings.bash index 79754ada4..e7f47a5f3 100644 --- a/piton/piton_settings.bash +++ b/piton/piton_settings.bash @@ -36,7 +36,7 @@ fi # Please define VCS_HOME only if you have VCS, otherwise comment it out. -#export VCS_HOME= +export VCS_HOME=/gro/cad/synopsys/vcs/L-2016.06-SP2-15 # Please define NCV_HOME only if you have NC-Verilog, otherwise comment it out. @@ -57,7 +57,7 @@ fi #export SYNP_HOME= -#export LM_LICENSE_FILE= +export LM_LICENSE_FILE=27020@kk9.cs.washington.edu:1717@persephone.engr.washington.edu # define vivado version if it deviates from the default #export VIVADO_BIN="vivado" @@ -129,7 +129,9 @@ then NEWPATH=$NEWPATH:$CC_BIN fi -export PATH="$NEWPATH:$PATH" +export PATH="$PATH:$NEWPATH" +#Path for BP external/bin +export PATH=$PATH:~/scratch/sdk/install/bin # Set a path for MacOS OS=`uname -s` @@ -144,3 +146,4 @@ export M4PATH=$DV_ROOT/tools/$OS/$CPU/lib/m4 # Set library path for the new goldfinger export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DV_ROOT/tools/src/goldfinger/lib + diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 4ef553af9..87748d0f0 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -24,8 +24,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # Format: # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) -piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 -system . vc707,60,1024;genesys2,25,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768 +system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048; chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index 842161aed..fa857a8bf 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -2226,7 +2226,7 @@ sub assemble_diag } if ($opt{blackparrot} and $opt{precompiled}) { - push @{$opt{asm_diag_root}}, "$ENV{DV_ROOT}/design/chip/tile/blackparrot/bp_common/test/mem/"; + push @{$opt{asm_diag_root}}, "$ENV{HOME}/scratch/sdk/prog/riscv-tests" } # find diagnostic @@ -2904,8 +2904,8 @@ sub parse_args push (@{$opt{vcs_build_args}}, "-assert svaext") ; push (@{$opt{vcs_build_args}}, "-debug_all") if ($opt{debug_all}) ; push (@{$opt{vcs_build_args}}, "-debug_pp") if ($opt{debug_pp}) ; - push (@{$opt{vcs_build_args}}, "-CFLAGS \"-I/mnt/users/ssd1/homes/svijay97/BlackParrot/black-parrot-sdk/include -std=c++14\"") ; - push (@{$opt{vcs_build_args}}, "/mnt/users/ssd1/homes/svijay97/BlackParrot/black-parrot-sdk/lib/libdromajo_cosim.a") ; + push (@{$opt{vcs_build_args}}, "-CFLAGS \"-I/mnt/users/ssd0/homes/petrisko/scratch/black-parrot/tools/install/include -std=c++14\"") ; + push (@{$opt{vcs_build_args}}, "/mnt/users/ssd0/homes/petrisko/scratch/black-parrot/tools/install/lib/libdromajo_cosim.a") ; # Push optional execution drafting enable push (@{$opt{midas_args}}, "-DED_ENABLE") if ($opt{ed_enable}); From 5943677303d1807da1bfe9d6ef643adb5d4bee17 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Mon, 4 Oct 2021 00:45:57 -0700 Subject: [PATCH 09/12] Updating tcl scripts --- .../ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci | 136 +++++++++++--- .../ip_cores/uart_16550/uart_16550.xci | 64 ++++++- .../genesys2/ip_cores/clk_mmcm/clk_mmcm.xci | 166 +++++++++++++++--- .../genesys2/ip_cores/afifo_w64/afifo_w64.xci | 149 +++++++++++++++- .../genesys2/ip_cores/afifo_w3/afifo_w3.xci | 149 +++++++++++++++- piton/tools/src/proto/common/blackparrot.tcl | 93 +++++----- 6 files changed, 645 insertions(+), 112 deletions(-) diff --git a/piton/design/chip/xilinx/genesys2/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci b/piton/design/chip/xilinx/genesys2/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci index 36a28754f..175b4c1de 100644 --- a/piton/design/chip/xilinx/genesys2/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci +++ b/piton/design/chip/xilinx/genesys2/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci @@ -7,13 +7,73 @@ clk_mmcm_chip - + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 MMCM cddcdone cddcreq 0000 - 7800 + 0000 clkfb_in_n clkfb_in clkfb_in_p @@ -24,11 +84,11 @@ clkfb_stopped 50.0 100.0 - 11c7 - 5c00 + 0000 + 0000 60.000 - 1041 - 00c0 + 0000 + 0000 100.000 BUFG 50.0 @@ -39,8 +99,8 @@ 60.000 0.000 1 - 1041 - 00c0 + 0000 + 0000 100.000 BUFG 50.000 @@ -52,8 +112,8 @@ 0.000 1 0 - 1041 - 00c0 + 0000 + 0000 100.000 BUFG 50.000 @@ -65,8 +125,8 @@ 0.000 1 0 - 1041 - 00c0 + 0000 + 0000 100.000 BUFG 50.000 @@ -78,8 +138,8 @@ 0.000 1 0 - 1041 - 14c0 + 0000 + 0000 100.000 BUFG 50.000 @@ -91,8 +151,8 @@ 0.000 1 0 - 1041 - 38c0 + 0000 + 0000 100.000 BUFG 50.000 @@ -129,7 +189,7 @@ dclk den din - 0145 + 0000 1 0.6 0.6 @@ -149,8 +209,8 @@ 0 0 FDBK_AUTO - 0800 - 9090 + 0000 + 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_________200.000____________0.010 @@ -160,9 +220,9 @@ Units_MHz No_Jitter locked - 00fa - 7c01 - 7fe9 + 0000 + 0000 + 0000 false false false @@ -175,7 +235,7 @@ 49.875 0.000 FALSE - 5.0 + 5.000 10.0 16.625 0.500 @@ -260,7 +320,7 @@ No notes 0.010 power_down - FFFF + 0000 1 clk_in1 MMCM @@ -448,7 +508,7 @@ 49.875 0.000 false - 5.0 + 5.000 10.0 16.625 0.500 @@ -572,13 +632,15 @@ false false kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE @@ -588,12 +650,31 @@ . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + @@ -615,6 +696,7 @@ + diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci index e9e2c882b..684b2eb05 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci @@ -9,6 +9,43 @@ uart_16550 + + 100000000 + 0 + 0.000 + 0 + 1 + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 25000000 kintex7 0 @@ -29,28 +66,49 @@ Custom false kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 13 + 21 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci index 5cb30b834..32017076e 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci @@ -7,13 +7,109 @@ clk_mmcm - + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 MMCM cddcdone cddcreq 0000 - 0080 + 0000 clkfb_in_n clkfb_in clkfb_in_p @@ -24,11 +120,11 @@ clkfb_stopped 50.0 100.0 - 1105 - 0080 + 0000 + 0000 66.667 - 1042 - 0080 + 0000 + 0000 200.000 BUFG 50.0 @@ -39,7 +135,7 @@ 66.666 0.000 1 - 1186 + 0000 0000 50.000 BUFG @@ -52,7 +148,7 @@ 0.000 1 1 - 10c3 + 0000 0000 100.000 BUFG @@ -65,8 +161,8 @@ 0.000 1 1 - 10c3 - 0003 + 0000 + 0000 100.000 BUFG 50.0 @@ -78,7 +174,7 @@ 0.000 1 1 - 130c + 0000 0000 25.000 BUFG @@ -91,8 +187,8 @@ 180.000 1 1 - 10c3 - 0080 + 0000 + 0000 100.000 BUFG 50.0 @@ -129,7 +225,7 @@ dclk den din - 1041 + 0000 1 0.33332999999999996 1.3333199999999998 @@ -149,8 +245,8 @@ 0 0 FDBK_AUTO - 0800 - 9990 + 0000 + 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_________200.000____________0.010 @@ -160,9 +256,9 @@ Units_MHz No_Jitter locked - 03e8 - 2001 - 23e9 + 0000 + 0000 + 0000 false false false @@ -260,7 +356,7 @@ No notes 0.010 power_down - FFFF + 0000 1 clk_in1 MMCM @@ -572,13 +668,15 @@ false false kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE @@ -588,12 +686,30 @@ . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + @@ -618,15 +734,21 @@ + + + + + + diff --git a/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci b/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci index 947f56ca8..47305f13d 100644 --- a/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci +++ b/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci @@ -7,13 +7,124 @@ afifo_w64 - + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 0 0 0 @@ -385,29 +496,59 @@ FIFO FIFO kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 4 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci b/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci index 57d7873d8..b8f2c2ceb 100644 --- a/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci +++ b/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci @@ -7,13 +7,124 @@ afifo_w3 - + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 0 0 0 @@ -385,29 +496,59 @@ FIFO FIFO kintex7 - + + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 4 TRUE . . - 2016.4 + 2019.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/tools/src/proto/common/blackparrot.tcl b/piton/tools/src/proto/common/blackparrot.tcl index 648efe31b..8264e51f7 100644 --- a/piton/tools/src/proto/common/blackparrot.tcl +++ b/piton/tools/src/proto/common/blackparrot.tcl @@ -182,7 +182,8 @@ set BLACKPARROT_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_req.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_cmd.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cce_to_cache.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_cce_to_cache.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_bedrock_register.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_alu.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_arbitrate.sv" \ @@ -208,23 +209,19 @@ set BLACKPARROT_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_wrapper.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_uce.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_pce.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_addr_to_cce_id.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_id_to_cord.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_bidir.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_client.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_master.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cord_to_id.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_lce_id_to_cord.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_lite_to_stream.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_stream_to_lite.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_lite_to_burst.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_burst_to_lite.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_loopback.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_addr_to_cce_id.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_id_to_cord.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_bidir.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_recv.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_send.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cord_to_id.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_lce_id_to_cord.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_cmd.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_req.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_resp.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_cmd.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_resp.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_loopback.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_nd_socket.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_vdp.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_tile.sv" \ @@ -234,11 +231,11 @@ set BLACKPARROT_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_tile.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_tile_node.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_complex.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cfg.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_cfg.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_minimal.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_complex.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_clint_slice.sv" \ + "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_clint_slice.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_l2e_tile.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_l2e_tile_node.sv" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_complex.sv" \ @@ -258,6 +255,7 @@ set BLACKPARROT_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.vh" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_links.vh" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_defines.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache.vh" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_pkgdef.svh" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_instr_defines.svh" \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_pkgdef.svh" \ @@ -294,6 +292,7 @@ set BLACKPARROT_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_pkgdef.svh" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_reverse.v" \ + "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mul_add_unsigned.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_rx.v" \ "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_tx.v" \ @@ -1522,92 +1521,77 @@ set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_pce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cache/bp_me_cce_to_cache.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_cce_to_cache.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_addr_to_cce_id.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_bedrock_register.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_id_to_cord.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_addr_to_cce_id.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_bidir.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_id_to_cord.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_client.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_bidir.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_master.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_recv.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_cord_to_id.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_send.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_lce_id_to_cord.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cord_to_id.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_lce_id_to_cord.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_cmd.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_req.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_resp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_cmd.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_lite_to_stream.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_resp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_stream_to_lite.sv" - -set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj - -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_lite_to_burst.sv" - -set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj - -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/wormhole/bp_burst_to_lite.sv" - -set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] -set_property -name "file_type" -value "SystemVerilog" -objects $file_obj - -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_loopback.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_loopback.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj @@ -1657,7 +1641,7 @@ set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_complex.s set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cfg.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_cfg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj @@ -1677,7 +1661,7 @@ set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_complex.s set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_clint_slice.sv" +set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_clint_slice.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj @@ -1777,6 +1761,11 @@ set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj +set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mul_add_unsigned.v" + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] +set_property -name "file_type" -value "SystemVerilog" -objects $file_obj + set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_async_noc_link.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] From 5a2de3b62804b58ded31b8357bc732e667ba3fb9 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Mon, 4 Oct 2021 00:56:05 -0700 Subject: [PATCH 10/12] Moving blackparrot submodule --- .gitmodules | 2 +- piton/design/chip/tile/{blackparrot => black-parrot} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename piton/design/chip/tile/{blackparrot => black-parrot} (100%) diff --git a/.gitmodules b/.gitmodules index 2b02535cc..877f5f24d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -5,6 +5,6 @@ path = piton/design/aws url = https://github.com/PrincetonUniversity/openpiton-aws.git [submodule "piton/design/chip/tile/blackparrot"] - path = piton/design/chip/tile/blackparrot + path = piton/design/chip/tile/black-parrot url = https://github.com/black-parrot/black-parrot.git branch = parrotpiton diff --git a/piton/design/chip/tile/blackparrot b/piton/design/chip/tile/black-parrot similarity index 100% rename from piton/design/chip/tile/blackparrot rename to piton/design/chip/tile/black-parrot From c48a5ddc8d9fcaad4db6ec154d756d39a7d751de Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Mon, 4 Oct 2021 01:02:30 -0700 Subject: [PATCH 11/12] Moving black-parrot submodule --- .gitmodules | 2 +- piton/tools/src/proto/common/blackparrot.tcl | 1202 +++++++++--------- piton/tools/src/sims/manycore.config | 2 +- piton/tools/src/sims/sims,2.0 | 14 +- 4 files changed, 610 insertions(+), 610 deletions(-) diff --git a/.gitmodules b/.gitmodules index 877f5f24d..a1d7c5067 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,7 +4,7 @@ [submodule "aws"] path = piton/design/aws url = https://github.com/PrincetonUniversity/openpiton-aws.git -[submodule "piton/design/chip/tile/blackparrot"] +[submodule "piton/design/chip/tile/black-parrot"] path = piton/design/chip/tile/black-parrot url = https://github.com/black-parrot/black-parrot.git branch = parrotpiton diff --git a/piton/tools/src/proto/common/blackparrot.tcl b/piton/tools/src/proto/common/blackparrot.tcl index 8264e51f7..980da513b 100644 --- a/piton/tools/src/proto/common/blackparrot.tcl +++ b/piton/tools/src/proto/common/blackparrot.tcl @@ -1,1812 +1,1812 @@ set obj [get_filesets sources_1] set BLACKPARROT_RTL_IMPL_FILES [list \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/include/bp_top_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_async_fifo.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_launch_sync_sync.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_async_ptr_gray.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_decode.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_dma.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_miss.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf_queue.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_in.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_out.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged_fifo.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_large.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1rw_large.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_tracker.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_flow_counter.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_one_fifo.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_passthrough.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_1_to_n.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_2_to_2.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_n_to_1.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_full.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_passthrough.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_shift_reg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_two_fifo.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_replacement.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_sync.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_tag_array.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_one_hot.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync_synth.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_cin.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_one_hot.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_ripple_carry.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_arb_fixed.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_concentrate_static.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf_ctrl.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_circular_ptr.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_concentrate_static.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up_one_hot.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_set_down.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_set_en.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_overflow_en.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_up_down.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_crossbar_o_by_i.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_cycle_counter.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_decode.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_decode_with_v.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_chain.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_en.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_en_bypass.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en_bypass.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_set_clear.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_edge_detect.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_encode_one_hot.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_expand_bitmask.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_hash_bank.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_hash_bank_reverse.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative_controller.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lfsr.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_decode.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_encode.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_bitwise.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_butterfly.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_one_hot.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_segmented.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_muxi2_gatestack.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nor2.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nor3.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nand.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_priority_encode.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_priority_encode_one_hot_out.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_reduce.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_reduce_segmented.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_rotate_left.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_rotate_right.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_scan.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_strobe.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_swap.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_thermometer_count.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_transpose.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_unconcentrate_static.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_xnor.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_mesh_stitch.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_repeater_node.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_in.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_out.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_in.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_out.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_decoder_dor.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_input_control.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_output_control.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/addRecFN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/compareRecFN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/divSqrtRecFN_small.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/fNToRecFN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_primitives.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_consts.vi" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_rawFN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/iNToRecFN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/isSigNaNRecFN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/mulAddRecFN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/mulRecFN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToFN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToIN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToRecFN.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/RISCV/HardFloat_specialize.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/RISCV/HardFloat_specialize.vi" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_fifo_1r1w_rolly.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_bus_pack.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_pma.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_mmu.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_tlb.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_top.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_calculator_top.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_csr.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_int.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_long.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mem.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_sys.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_aux.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_ctl.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_fma.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_fp_to_rec.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_ptw.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_rec_to_fp.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_cmd_queue.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_detector.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_director.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_instr_decoder.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_issue_queue.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_regfile.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_scheduler.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_scoreboard.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_decoder.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_wbuf.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_bht.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_btb.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_icache.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_instr_scan.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_pc_gen.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_top.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_req.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_cmd.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_cce_to_cache.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_bedrock_register.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_alu.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_arbitrate.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_branch.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_lru_extract.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_segment.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_tag_checker.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_fsm.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_gad.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_decode.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_predecode.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_ram.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_stall.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/test/common/bp_cce_mmio_cfg_loader.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_msg.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_pending_bits.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_pma.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_reg.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_spec_bits.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_src_sel.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_io_cce.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_wrapper.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_uce.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_pce.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_addr_to_cce_id.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_id_to_cord.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_bidir.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_recv.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_send.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cord_to_id.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_lce_id_to_cord.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_cmd.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_req.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_resp.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_cmd.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_resp.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_loopback.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_nd_socket.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_vdp.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_tile.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_tile_node.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_complex.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_vdp.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_tile.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_tile_node.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_complex.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_cfg.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_minimal.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_complex.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_clint_slice.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_l2e_tile.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_l2e_tile_node.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_complex.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_link_to_lce.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile_node.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_mem_complex.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_multicore.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_unicore.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile_node.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_piton_top.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_async_noc_link.sv" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_cache_dma_to_wormhole.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_dff_reset_half.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_wormhole_to_cache_dma_fanout.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_links.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_defines.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache.vh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_instr_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_core_if.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_core_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_log_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_csr_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_bedrock_if.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_bedrock_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cache_engine_if.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cache_engine_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cfg_bus_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cfg_bus_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_addr_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_addr_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_ctl_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_pce_l15_if.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_inst_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_inst_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_wormhole_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/include/bp_top_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_pkg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_decompress.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_defines.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_pkgdef.svh" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_reverse.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mul_add_unsigned.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_rx.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_tx.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_clkgate_optional.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dlatch.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small.v" \ - "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/include/bp_fe_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/include/bp_be_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/include/bp_top_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_async/bsg_async_fifo.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_async/bsg_launch_sync_sync.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_async/bsg_async_ptr_gray.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_decode.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_dma.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_miss.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf_queue.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_in.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_out.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged_fifo.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_large.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1rw_large.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_tracker.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_flow_counter.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_one_fifo.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_passthrough.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_1_to_n.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_2_to_2.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_n_to_1.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_full.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_passthrough.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_shift_reg.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_two_fifo.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_replacement.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_sync.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_tag_array.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_one_hot.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_synth.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_synth.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync_synth.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync_synth.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_adder_cin.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_adder_one_hot.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_adder_ripple_carry.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_arb_fixed.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_array_concentrate_static.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_buf.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_buf_ctrl.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_circular_ptr.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_concentrate_static.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up_one_hot.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_set_down.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_set_en.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_overflow_en.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_up_down.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_crossbar_o_by_i.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_cycle_counter.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_decode.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_decode_with_v.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_chain.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_en.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_en_bypass.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en_bypass.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset_set_clear.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_edge_detect.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_encode_one_hot.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_expand_bitmask.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_hash_bank.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_hash_bank_reverse.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative_controller.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_lfsr.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_decode.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_encode.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mux.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mux_bitwise.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mux_butterfly.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mux_one_hot.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mux_segmented.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_muxi2_gatestack.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_nor2.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_nor3.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_nand.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_priority_encode.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_priority_encode_one_hot_out.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_reduce.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_reduce_segmented.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_rotate_left.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_rotate_right.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_scan.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_strobe.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_swap.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_thermometer_count.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_transpose.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_unconcentrate_static.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_xnor.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_mesh_stitch.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_noc_repeater_node.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_in.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_out.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_in.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_out.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_decoder_dor.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_input_control.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_output_control.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/addRecFN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/compareRecFN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/divSqrtRecFN_small.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/fNToRecFN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/HardFloat_primitives.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/HardFloat_consts.vi" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/HardFloat_rawFN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/iNToRecFN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/isSigNaNRecFN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/mulAddRecFN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/mulRecFN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/recFNToFN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/recFNToIN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/recFNToRecFN.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/RISCV/HardFloat_specialize.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/RISCV/HardFloat_specialize.vi" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_fifo_1r1w_rolly.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_bus_pack.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bp_pma.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bp_mmu.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bp_tlb.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_top.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_calculator_top.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_csr.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_int.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_long.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mem.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_sys.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_aux.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_ctl.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_fma.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_fp_to_rec.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_ptw.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_rec_to_fp.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_cmd_queue.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_detector.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_director.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_instr_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_issue_queue.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_regfile.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_scheduler.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_scoreboard.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_dcache/bp_be_dcache.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_wbuf.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_bht.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_btb.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_icache.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_instr_scan.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_pc_gen.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_top.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/lce/bp_lce.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/lce/bp_lce_req.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/lce/bp_lce_cmd.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/dev/bp_me_cce_to_cache.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/dev/bp_me_bedrock_register.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_alu.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_arbitrate.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_branch.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_dir.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_dir_lru_extract.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_dir_segment.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_dir_tag_checker.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_fsm.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_gad.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_inst_decode.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_inst_predecode.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_inst_ram.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_inst_stall.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/test/common/bp_cce_mmio_cfg_loader.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_msg.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_pending_bits.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_pma.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_reg.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_spec_bits.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_src_sel.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_io_cce.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_uce.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_pce.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_addr_to_cce_id.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_cce_id_to_cord.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_cce_to_mem_link_bidir.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_cce_to_mem_link_recv.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_cce_to_mem_link_send.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_cord_to_id.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_lce_id_to_cord.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_cmd.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_req.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_resp.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_cmd.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_resp.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/dev/bp_me_loopback.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_nd_socket.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_cacc_vdp.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_cacc_tile.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_cacc_tile_node.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_cacc_complex.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_sacc_vdp.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_sacc_tile.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_sacc_tile_node.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_sacc_complex.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/dev/bp_me_cfg.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_core.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_core_minimal.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_core_complex.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/dev/bp_me_clint_slice.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_l2e_tile.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_l2e_tile_node.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_io_complex.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_io_link_to_lce.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_io_tile.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_io_tile_node.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_mem_complex.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_multicore.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_unicore.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_tile.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_tile_node.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_piton_top.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_async_noc_link.sv" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_cache_dma_to_wormhole.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_dff_reset_half.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_wormhole_to_cache_dma_fanout.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.vh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_noc_links.vh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_defines.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache.vh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_aviary_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_rv64_instr_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_rv64_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_core_if.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_core_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_log_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_rv64_csr_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_bedrock_if.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_bedrock_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_cache_engine_if.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_cache_engine_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_cfg_bus_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_cfg_bus_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_addr_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_addr_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_aviary_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/include/bp_be_ctl_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/include/bp_be_dcache_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/include/bp_be_dcache_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/include/bp_be_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_pce_l15_if.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_cce_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_cce_inst_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_cce_inst_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_wormhole_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/include/bp_top_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_noc_pkg.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/include/bp_fe_decompress.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/include/bp_fe_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/include/bp_fe_icache_defines.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/include/bp_fe_icache_pkgdef.svh" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_array_reverse.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mul_add_unsigned.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_rx.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_tx.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_clkgate_optional.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dlatch.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small.v" \ + "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v" \ ] add_files -norecurse -fileset $obj $BLACKPARROT_RTL_IMPL_FILES -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.vh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.vh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj set_property -name "is_global_include" -value "1" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_links.vh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_noc_links.vh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj set_property -name "is_global_include" -value "1" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_defines.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_defines.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj set_property -name "is_global_include" -value "1" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_pkg.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_pkg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_pkg.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/include/bp_fe_pkg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_pkg.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/include/bp_be_pkg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_pkg.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_pkg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/include/bp_top_pkg.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/include/bp_top_pkg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_async_fifo.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_async/bsg_async_fifo.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_launch_sync_sync.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_async/bsg_launch_sync_sync.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_async/bsg_async_ptr_gray.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_async/bsg_async_ptr_gray.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_decode.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_decode.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_dma.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_dma.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_miss.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_miss.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf_queue.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf_queue.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_in.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_in.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_out.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_out.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged_fifo.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged_fifo.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_large.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_large.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1rw_large.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1rw_large.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_fifo_tracker.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_tracker.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_flow_counter.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_flow_counter.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_one_fifo.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_one_fifo.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_passthrough.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_passthrough.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_1_to_n.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_1_to_n.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_2_to_2.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_2_to_2.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_n_to_1.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_n_to_1.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_full.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_full.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_passthrough.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_passthrough.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_shift_reg.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_shift_reg.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_dataflow/bsg_two_fifo.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_dataflow/bsg_two_fifo.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_replacement.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_replacement.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_sync.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_sync.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_tag_array.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_tag_array.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_one_hot.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_one_hot.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_synth.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_synth.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -#set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" +#set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" # #set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] #set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -#set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v" +#set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v" # #set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] #set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_synth.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_synth.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync_synth.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync_synth.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync_synth.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync_synth.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_cin.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_adder_cin.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_one_hot.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_adder_one_hot.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_adder_ripple_carry.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_adder_ripple_carry.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_arb_fixed.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_arb_fixed.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_concentrate_static.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_array_concentrate_static.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_buf.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_buf_ctrl.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_buf_ctrl.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_circular_ptr.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_circular_ptr.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_concentrate_static.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_concentrate_static.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up_one_hot.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up_one_hot.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_set_down.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_set_down.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_set_en.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_set_en.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_overflow_en.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_overflow_en.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_up_down.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_up_down.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_crossbar_o_by_i.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_crossbar_o_by_i.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_cycle_counter.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_cycle_counter.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_decode.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_decode.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_decode_with_v.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_decode_with_v.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_chain.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_chain.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_en.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_en.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_en_bypass.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_en_bypass.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en_bypass.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en_bypass.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dff_reset_set_clear.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset_set_clear.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_edge_detect.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_edge_detect.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_encode_one_hot.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_encode_one_hot.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_expand_bitmask.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_expand_bitmask.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_hash_bank.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_hash_bank.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_hash_bank_reverse.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_hash_bank_reverse.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative_controller.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative_controller.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lfsr.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_lfsr.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_decode.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_decode.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_encode.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_encode.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mux.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_bitwise.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mux_bitwise.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_butterfly.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mux_butterfly.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_one_hot.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mux_one_hot.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mux_segmented.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mux_segmented.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_muxi2_gatestack.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_muxi2_gatestack.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nor2.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_nor2.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nand.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_nand.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_nor3.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_nor3.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_priority_encode.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_priority_encode.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_priority_encode_one_hot_out.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_priority_encode_one_hot_out.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_reduce.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_reduce.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_reduce_segmented.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_reduce_segmented.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_rotate_left.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_rotate_left.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_rotate_right.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_rotate_right.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_scan.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_scan.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_strobe.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_strobe.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_swap.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_swap.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_transpose.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_transpose.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_thermometer_count.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_thermometer_count.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_unconcentrate_static.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_unconcentrate_static.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_xnor.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_xnor.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_mesh_stitch.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_mesh_stitch.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_repeater_node.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_noc_repeater_node.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_in.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_in.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_out.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_out.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_in.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_in.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_out.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_out.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_decoder_dor.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_decoder_dor.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_input_control.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_input_control.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_output_control.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_output_control.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/addRecFN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/addRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/compareRecFN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/compareRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/divSqrtRecFN_small.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/divSqrtRecFN_small.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/fNToRecFN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/fNToRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_primitives.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/HardFloat_primitives.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_consts.vi" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/HardFloat_consts.vi" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/HardFloat_rawFN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/HardFloat_rawFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/iNToRecFN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/iNToRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/isSigNaNRecFN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/isSigNaNRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/mulAddRecFN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/mulAddRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/mulRecFN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/mulRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToFN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/recFNToFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToIN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/recFNToIN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/recFNToRecFN.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/recFNToRecFN.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/RISCV/HardFloat_specialize.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/RISCV/HardFloat_specialize.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/HardFloat/source/RISCV/HardFloat_specialize.vi" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/HardFloat/source/RISCV/HardFloat_specialize.vi" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_aviary_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_aviary_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_aviary_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_instr_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_rv64_instr_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_rv64_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_core_if.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_core_if.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_core_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_core_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_log_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_log_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_rv64_csr_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_rv64_csr_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_bedrock_if.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_bedrock_if.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_bedrock_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_bedrock_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cache_engine_if.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_cache_engine_if.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cache_engine_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_cache_engine_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cfg_bus_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_cfg_bus_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_cfg_bus_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_cfg_bus_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_addr_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_addr_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/include/bp_common_addr_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/include/bp_common_addr_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_ctl_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/include/bp_be_ctl_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/include/bp_be_dcache_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_dcache_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/include/bp_be_dcache_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/include/bp_be_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/include/bp_be_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/include/bp_top_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/include/bp_top_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_top.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_top.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_calculator_top.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_calculator_top.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_csr.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_csr.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_fp_to_rec.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_fp_to_rec.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_rec_to_fp.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_rec_to_fp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_int.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_int.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_aux.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_aux.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_ctl.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_ctl.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_fma.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_fma.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_long.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_long.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mem.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mem.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_sys.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_sys.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_ptw.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_calculator/bp_be_ptw.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_cmd_queue.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_cmd_queue.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_detector.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_detector.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_director.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_director.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_instr_decoder.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_instr_decoder.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_issue_queue.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_issue_queue.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_regfile.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_regfile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_scheduler.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_scheduler.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_checker/bp_be_scoreboard.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_checker/bp_be_scoreboard.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_dcache/bp_be_dcache.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_decoder.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_decoder.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_wbuf.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_be/src/v/bp_be_dcache/bp_be_dcache_wbuf.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_pce_l15_if.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_pce_l15_if.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_cce_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_inst_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_cce_inst_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_cce_inst_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_cce_inst_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/include/bp_me_wormhole_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/include/bp_me_wormhole_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_noc_pkg.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_noc_pkg.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_alu.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_alu.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_arbitrate.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_arbitrate.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_branch.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_branch.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_dir.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_lru_extract.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_dir_lru_extract.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_segment.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_dir_segment.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_dir_tag_checker.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_dir_tag_checker.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_fsm.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_fsm.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_gad.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_gad.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_decode.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_inst_decode.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_predecode.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_inst_predecode.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_ram.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_inst_ram.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_inst_stall.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_inst_stall.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/test/common/bp_cce_mmio_cfg_loader.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/test/common/bp_cce_mmio_cfg_loader.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_msg.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_msg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_pending_bits.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_pending_bits.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_pma.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_pma.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_reg.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_reg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_spec_bits.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_spec_bits.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_src_sel.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_src_sel.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_io_cce.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_io_cce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_cce_wrapper.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_cce_wrapper.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_decompress.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/include/bp_fe_decompress.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/include/bp_fe_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_defines.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/include/bp_fe_icache_defines.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/include/bp_fe_icache_pkgdef.svh" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/include/bp_fe_icache_pkgdef.svh" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "Verilog Header" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_bht.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_bht.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_btb.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_btb.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_icache.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_icache.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_instr_scan.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_instr_scan.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_pc_gen.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_pc_gen.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_fe/src/v/bp_fe_top.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_fe/src/v/bp_fe_top.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/lce/bp_lce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_req.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/lce/bp_lce_req.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/lce/bp_lce_cmd.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/lce/bp_lce_cmd.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_uce.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_uce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/cce/bp_pce.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/cce/bp_pce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_cce_to_cache.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/dev/bp_me_cce_to_cache.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_bedrock_register.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/dev/bp_me_bedrock_register.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_addr_to_cce_id.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_addr_to_cce_id.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_id_to_cord.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_cce_id_to_cord.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_bidir.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_cce_to_mem_link_bidir.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_recv.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_cce_to_mem_link_recv.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cce_to_mem_link_send.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_cce_to_mem_link_send.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_cord_to_id.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_cord_to_id.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_lce_id_to_cord.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_lce_id_to_cord.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_cmd.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_cmd.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_req.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_req.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_resp.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_lce_resp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_cmd.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_cmd.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_resp.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/network/bp_me_wormhole_packet_encode_mem_resp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_loopback.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/dev/bp_me_loopback.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_nd_socket.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_nd_socket.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_vdp.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_cacc_vdp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_tile.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_cacc_tile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_tile_node.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_cacc_tile_node.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_cacc_complex.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_cacc_complex.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_vdp.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_sacc_vdp.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_tile.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_sacc_tile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_tile_node.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_sacc_tile_node.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_sacc_complex.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_sacc_complex.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_cfg.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/dev/bp_me_cfg.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_core.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_minimal.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_core_minimal.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_core_complex.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_core_complex.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_me/src/v/dev/bp_me_clint_slice.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_me/src/v/dev/bp_me_clint_slice.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_l2e_tile.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_l2e_tile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_l2e_tile_node.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_l2e_tile_node.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_complex.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_io_complex.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_link_to_lce.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_io_link_to_lce.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_io_tile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_io_tile_node.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_io_tile_node.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_mem_complex.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_mem_complex.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_multicore.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_multicore.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_unicore.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_unicore.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_tile.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_tile_node.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_tile_node.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_top/src/v/bp_piton_top.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_top/src/v/bp_piton_top.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_fifo_1r1w_rolly.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_fifo_1r1w_rolly.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_bus_pack.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_bus_pack.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_mmu.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bp_mmu.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_pma.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bp_pma.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bp_tlb.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bp_tlb.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_array_reverse.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_array_reverse.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_mul_add_unsigned.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_mul_add_unsigned.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_async_noc_link.sv" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_async_noc_link.sv" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_cache_dma_to_wormhole.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_cache_dma_to_wormhole.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_dff_reset_half.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_dff_reset_half.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/bp_common/src/v/bsg_wormhole_to_cache_dma_fanout.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/bp_common/src/v/bsg_wormhole_to_cache_dma_fanout.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_rx.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_rx.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_tx.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_tx.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_clkgate_optional.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_clkgate_optional.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj -set file "${DV_ROOT}/design/chip/tile/blackparrot/external/basejump_stl/bsg_misc/bsg_dlatch.v" +set file "${DV_ROOT}/design/chip/tile/black-parrot/external/basejump_stl/bsg_misc/bsg_dlatch.v" set file_obj [get_files -of_objects [get_filesets sources_1] [list "$file"]] set_property -name "file_type" -value "SystemVerilog" -objects $file_obj diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index ffbbd1d31..7cc31b494 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -25,7 +25,7 @@ -model=manycore -toplevel=cmp_top #ifdef FLIST_BLACKPARROT - -flist=$DV_ROOT/design/chip/tile/blackparrot/bp_top/syn/flist.vcs + -flist=$DV_ROOT/design/chip/tile/black-parrot/bp_top/syn/flist.vcs // Including Ariane Flist for the CLINT and PLIC -flist=$DV_ROOT/design/chip/tile/ariane/Flist.ariane #endif diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index fa857a8bf..1947e1b89 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -2826,13 +2826,13 @@ sub parse_args $ENV{PITON_ARIANE} = $opt{ariane}; $ENV{PITON_BLACKPARROT} = $opt{blackparrot}; $ENV{PITON_RV64_PLATFORM} = $opt{rv64_platform}; - $ENV{BASEJUMP_STL_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/external/basejump_stl"; - $ENV{BP_COMMON_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/bp_common"; - $ENV{BP_FE_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/bp_fe"; - $ENV{BP_ME_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/bp_me"; - $ENV{BP_BE_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/bp_be"; - $ENV{BP_TOP_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/bp_top"; - $ENV{HARDFLOAT_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/blackparrot/external/HardFloat"; + $ENV{BASEJUMP_STL_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/black-parrot/external/basejump_stl"; + $ENV{BP_COMMON_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/black-parrot/bp_common"; + $ENV{BP_FE_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/black-parrot/bp_fe"; + $ENV{BP_ME_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/black-parrot/bp_me"; + $ENV{BP_BE_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/black-parrot/bp_be"; + $ENV{BP_TOP_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/black-parrot/bp_top"; + $ENV{HARDFLOAT_DIR} = $ENV{DV_ROOT} . "/design/chip/tile/black-parrot/external/HardFloat"; push (@{$opt{config_rtl}}, "PITON_OST1") if ($opt{ost1}); push (@{$opt{config_rtl}}, "PITON_PICO") if ($opt{pico}); push (@{$opt{config_rtl}}, "PITON_PICO") if ($opt{pico_het}); From 85f552fe7d9160ffdbb96280206049c549c8eeb1 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Mon, 4 Oct 2021 02:02:36 -0700 Subject: [PATCH 12/12] Use sdk environment variable --- piton/tools/src/sims/sims,2.0 | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index 1947e1b89..1a0e63723 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -2226,7 +2226,7 @@ sub assemble_diag } if ($opt{blackparrot} and $opt{precompiled}) { - push @{$opt{asm_diag_root}}, "$ENV{HOME}/scratch/sdk/prog/riscv-tests" + push @{$opt{asm_diag_root}}, "$BLACKPARROT_SDK/prog/riscv-tests" } # find diagnostic @@ -2904,8 +2904,8 @@ sub parse_args push (@{$opt{vcs_build_args}}, "-assert svaext") ; push (@{$opt{vcs_build_args}}, "-debug_all") if ($opt{debug_all}) ; push (@{$opt{vcs_build_args}}, "-debug_pp") if ($opt{debug_pp}) ; - push (@{$opt{vcs_build_args}}, "-CFLAGS \"-I/mnt/users/ssd0/homes/petrisko/scratch/black-parrot/tools/install/include -std=c++14\"") ; - push (@{$opt{vcs_build_args}}, "/mnt/users/ssd0/homes/petrisko/scratch/black-parrot/tools/install/lib/libdromajo_cosim.a") ; + push (@{$opt{vcs_build_args}}, "-CFLAGS \"-I{BLACKPARROT_ROOT}/tools/install/include -std=c++14\"") ; + push (@{$opt{vcs_build_args}}, "${BLACKPARROT_ROOT}/tools/install/lib/libdromajo_cosim.a") ; # Push optional execution drafting enable push (@{$opt{midas_args}}, "-DED_ENABLE") if ($opt{ed_enable});