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I've only looked at the top.route file a little bit and it does seem to have a lot of the information that we would need from the netlist. We would need to write an entirely new design query interface for the file, and it would be a lot more work than our Vivado and RapidWright interfaces as there are a lot of built-in commands that make getting the information we need much easier. Jackson and I would need to do more research into the F4PGA flow in order to figure out what kind of design querying support it has, so an interface for this file would likely be a future project.
My suggestion would be to probably look at the FPGA Interchange format which has a Python API library and integration with RapidWright and Vivado already. The F4PGA tools are slowly moving to producing and consuming this file format.
The top.route file from an F4PGA build folder may work in replacement of a Vivado DCP file.
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