-
Notifications
You must be signed in to change notification settings - Fork 22
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Getting recursion error when parsing a netlist #213
Comments
Hi @arun-chaubey, are you able to share the netlist you're trying to parse so I can try it out myself and see what's going wrong? |
@jacobdbrown4 , thanks for your prompt response. Unfortunately the netlist is a key IP so wouldn't be able to share :( |
That's okay. It looks like line 742 in the verilog parser is being called over and over again. This happens when it parses multiple wire declarations on one line, like the following:
parse_cable_declaration() parses a wire declaration and if it sees that there is a comma instead of a semicolon, it will call itself again to parse the next wire. The problem with this is that it is implemented in a recursive fashion, not iterative. My guess is that there is a large amount of wires declared in a single line, so parse_cable_declaration() calls itself over and over until the max recursion depth is reached. I will work on fixing this. In the meantime, you can try looking at the netlist and breaking up the wire declarations into a multiple lines to see if that helps. |
I went ahead and made my own dummy netlist to test my theory and I got the same error (max recursion depth exceeded from line 742). Fixing it was simple, and the fix can be found on the next_release branch. I'm not sure when it will be merged into the master branch. |
Awesome, thanks @jacobdbrown4 |
Btw @jacobdbrown4 if you can provide the fix so I can put it in locally to proceed in the meantime, would be very helpful. Thanks |
You should be able to access the 'next_release' branch. The fix is found here (line 718 to 753). I think the easiest way to start using the fix is to clone the repo, switch to the next_release branch, and install spydrnet from there. |
Hi,
When trying to load up a verilog gate netlist written out of Synopsys synthesis tool, I am getting
RecursionError: maximum recursion depth exceeded in comparison
Below is the code and detailed error trace:
Has anyone else seen this issue before or can please let me know if I might be missing something on my end ?
Thanks & Regards,
Arun
The text was updated successfully, but these errors were encountered: