From 097f1dfe4e7453ca320efd51cea1000b8b57ef03 Mon Sep 17 00:00:00 2001 From: Ethan Uppal <113849268+ethanuppal@users.noreply.github.com> Date: Wed, 20 Nov 2024 20:26:57 -0500 Subject: [PATCH 01/12] [docs] Fix images in docs for `calyx-pass-explorer` (#2361) Closes #2344 since I think it's a relative paths issue. --- docs/compiler.md | 9 ++++++++- docs/dev/calyx-pass-explorer.md | 7 ++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/docs/compiler.md b/docs/compiler.md index 088646d417..64b35aaac8 100644 --- a/docs/compiler.md +++ b/docs/compiler.md @@ -33,6 +33,7 @@ For example, the alias `all` is an ordered sequence of default passes executed when the compiler is run from the command-line. The command-line provides two options to control the execution of passes: + - `-p, --pass`: Execute this pass or alias. Overrides default alias. - `-d, --disable-pass`: Disable this pass or alias. Takes priority over `-p`. @@ -43,6 +44,10 @@ the default execution alias `all`: cargo run -- examples/futil/simple.futil -p all -d static-timing ``` +If you want to work with passes interactively (for instance, you only care about +a pass far into the `all` sequence, and it is impractical to pass 20 `-p` +options), you can [visualize them](./dev/calyx-pass-explorer.md) with the `calyx-pass-explorer` tool. + ## Providing Pass Options Some passes take options to control their behavior. The `--list-passes` command prints out the options for each pass. For example, the `tdcc` pass has the following options: @@ -53,23 +58,25 @@ tdcc: ``` The option allows us to change the behavior of the pass. To provide a pass-specific option, we use the `-x` switch: + ``` cargo run -- examples/futil/simple.futil -p tdcc -x tdcc:dump-fsm ``` Note that we specify the option of `tdcc` by prefixing it with the pass name and a colon. - ## Specifying Primitives Library The compiler implementation uses a standard library of components to compile programs. The only standard library for the compiler is located in: + ``` /primitives ``` Specify the location of the library using the `-l` flag: + ``` cargo run -- -l ./primitives ``` diff --git a/docs/dev/calyx-pass-explorer.md b/docs/dev/calyx-pass-explorer.md index 8ff04e6016..a71112858f 100644 --- a/docs/dev/calyx-pass-explorer.md +++ b/docs/dev/calyx-pass-explorer.md @@ -9,6 +9,7 @@ is just to run it on code and see what happens. Enter [`calyx-pass-explorer`](https://github.com/calyxir/calyx/tree/main/tools/calyx-pass-explorer). It's a command line tool that provides an interactive interface for visualizing how different passes affect the source code. +It's been used to debug and develop new compiler passes as well as implement new features in the compiler, so I hope you can find it useful too! > ![Example running of the tool](https://raw.githubusercontent.com/calyxir/calyx/main/tools/calyx-pass-explorer/example_v0.0.0.png) > _The above image depicts the tool's interface in v0.0.0. @@ -67,11 +68,11 @@ tool to help develop it! We'll first run `calyx-pass-explorer example0.futil`. You should get something horrific like -![Lots of random text output that doesn't make sense](./assets/horrific-interface.png) +![Lots of random text output that doesn't make sense](assets/horrific-interface.png) > [!TIP] > If you get this message: -> ![Calyx executable could not be found](./assets/calyx-missing.png) +> ![Calyx executable could not be found](assets/calyx-missing.png) > You should setup `fud` or pass the path explicitly with `-e`, as suggested. > However, we're going to update this later to look at `fud2` as well because > `fud` is now officially deprecated. @@ -82,7 +83,7 @@ What we really want is to focus on what happens to, _e.g._, the `main` component To do that, we just pass `-c main` (or `--component main`) as a flag: ![Running the tool and visualizing how the well-formed pass affects the main -component](./assets/well-formed.png) +component](assets/well-formed.png) That's a lot better, but it's still quite a bit of information. Let's break it down. From cc24c34b5d52ca75b44d2c01b2308ccfa8a1ed9a Mon Sep 17 00:00:00 2001 From: Ethan Uppal <113849268+ethanuppal@users.noreply.github.com> Date: Wed, 20 Nov 2024 20:55:08 -0500 Subject: [PATCH 02/12] [docs] Fix images in docs for `calyx-pass-explorer` (#2362) Actually closes #2344; see #2361 for the failed previous attempt. --- .gitignore | 2 ++ docs/dev/assets/calyx-missing.png | Bin 0 -> 94736 bytes docs/dev/assets/horrific-interface.png | Bin 0 -> 484472 bytes docs/dev/assets/well-formed.png | Bin 0 -> 355189 bytes 4 files changed, 2 insertions(+) create mode 100644 docs/dev/assets/calyx-missing.png create mode 100644 docs/dev/assets/horrific-interface.png create mode 100644 docs/dev/assets/well-formed.png diff --git a/.gitignore b/.gitignore index 5c6840dac6..17a3384a44 100644 --- a/.gitignore +++ b/.gitignore @@ -75,3 +75,5 @@ frontends/queues/tests/**/*.expect # emacs *~ + +!docs/dev/assets/*.png diff --git a/docs/dev/assets/calyx-missing.png b/docs/dev/assets/calyx-missing.png new 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zYOyY%5hHn|Vyr+%(9ww@yp=1e`*sX*8*cj1Xw@kM`__N>3-6oIw!queTrn>=9|VT| ztDoS+ox~&!J}VD)`q3(7RD(1bE;MYo2%WT;xC|5}Ngr0OFMz`GuL}9Kof%eX7o%`ED+F^*a}U9h3Tv9pRzJ!+Gb7?rcS%I$tn+5!ExRTb zF<`@T-eujixVDc)czl3SQJ=*oV8~Gd|BJ*SQ7Vkj3fdhP0U*b`-bS*qgL@#yyC-4) zS$P}~39f<|21}zQsTS+YJ-$2!#IK8{-334*vncd7%?Y5LDrx@)>xu>2QqYqIjfuR+ zJfI4%IP7SyV;sJ%k0EX!0a~nFg#*|5+@P{8!>?Q?j8Qw_L)G*RIPxo4i&j62m+i2| zn1Cn%v%af%2yjg0+t9bk;$-ZRc!e=1}`_e>$KHOqYQ!2FP^v4Hzp_;J1!I3Hiy*c43^@ z748W%AovGS-u*NPQXE{pM~vIIkP_@)v8LM!o_qYbIkE{= zT6pC&KwJ0u;OFJ!$Ukdyb zjj^lCUs+A)DNmDLFvQ~`wmkF) z8U(t%dtV9`2v9{s{i5Bh!{?=fhusF{f-ayQ`^_JQdQ1PCu}cV@!ieaq&Sak}G6MMv z$ZwZ+cn#L8z0M{Y1i_lG--^dpx%6zsVR0>Kn~rO|r@tX(iT>D5mE*oxIrcfXSUEo8 zD-woy5v37yQjTN&=b)nRv%xBxM#Iqiy!k;&VW5I(xf4=m;Yxkcgy|m!{e-)4S Zx)Xk{)f;c Date: Fri, 29 Nov 2024 17:58:44 -0500 Subject: [PATCH 03/12] Parser (#2353) Created a parser to process the path we've described such as: ".-0-1-b" --- interp/src/debugger/commands/core.rs | 31 +++++ interp/src/debugger/commands/mod.rs | 1 + interp/src/debugger/commands/path_parser.pest | 13 ++ interp/src/debugger/commands/path_parser.rs | 116 ++++++++++++++++++ 4 files changed, 161 insertions(+) create mode 100644 interp/src/debugger/commands/path_parser.pest create mode 100644 interp/src/debugger/commands/path_parser.rs diff --git a/interp/src/debugger/commands/core.rs b/interp/src/debugger/commands/core.rs index 37148ef8a0..5d5e9689af 100644 --- a/interp/src/debugger/commands/core.rs +++ b/interp/src/debugger/commands/core.rs @@ -299,6 +299,37 @@ impl From<(Vec, Option, PrintMode)> for PrintTuple { } } +/// ParseNodes enum is used to represent what child to traverse with respect to +/// the current ControlIdx. +/// Body defines that we should go into the body of a while or repeat. +/// Offset defines which child to go to. +/// If defines whether we should go to the true or false branch next +#[derive(Debug, PartialEq, Clone)] +pub enum ParseNodes { + Body, + Offset(u32), + If(bool), +} +pub struct ParsePath { + nodes: Vec, +} + +impl ParsePath { + pub fn new(nodes: Vec) -> ParsePath { + ParsePath { nodes } + } + + pub fn get_path(&self) -> Vec { + self.nodes.clone() + } +} + +impl FromIterator for ParsePath { + fn from_iter>(iter: I) -> Self { + ParsePath::new(iter.into_iter().collect()) + } +} + // Different types of printing commands pub enum PrintCommand { Normal, diff --git a/interp/src/debugger/commands/mod.rs b/interp/src/debugger/commands/mod.rs index 452108f4ea..19f20de743 100644 --- a/interp/src/debugger/commands/mod.rs +++ b/interp/src/debugger/commands/mod.rs @@ -1,6 +1,7 @@ //! This module contains the structures for the debugger commands pub(crate) mod command_parser; pub mod core; +mod path_parser; pub use command_parser::parse_command; pub use core::Command; diff --git a/interp/src/debugger/commands/path_parser.pest b/interp/src/debugger/commands/path_parser.pest new file mode 100644 index 0000000000..f95eaff145 --- /dev/null +++ b/interp/src/debugger/commands/path_parser.pest @@ -0,0 +1,13 @@ +root = { "." } + +separator = { "-" } + +body = { "b" } + +num = { ASCII_DIGIT+ } + +branch = {"t" | "f"} + +clause = { separator ~ (body | num | branch) } + +path = { SOI ~ root ~ clause* ~ EOI } diff --git a/interp/src/debugger/commands/path_parser.rs b/interp/src/debugger/commands/path_parser.rs new file mode 100644 index 0000000000..5739da65b9 --- /dev/null +++ b/interp/src/debugger/commands/path_parser.rs @@ -0,0 +1,116 @@ +use super::{core::ParseNodes, ParsePath}; + +use pest_consume::{match_nodes, Error, Parser}; + +type ParseResult = std::result::Result>; +type Node<'i> = pest_consume::Node<'i, Rule, ()>; + +// include the grammar file so that Cargo knows to rebuild this file on grammar changes +const _GRAMMAR: &str = include_str!("path_parser.pest"); + +#[derive(Parser)] +#[grammar = "debugger/commands/path_parser.pest"] + +pub struct PathParser; + +#[pest_consume::parser] +impl PathParser { + fn EOI(_input: Node) -> ParseResult<()> { + Ok(()) + } + + fn root(_input: Node) -> ParseResult<()> { + Ok(()) + } + + fn body(_input: Node) -> ParseResult<()> { + Ok(()) + } + + fn separator(_input: Node) -> ParseResult<()> { + Ok(()) + } + + fn num(input: Node) -> ParseResult { + input + .as_str() + .parse::() + .map_err(|_| input.error("Expected non-negative number")) + } + + fn branch(input: Node) -> ParseResult { + let b = input.as_str(); + let result = b != "f"; + Ok(result) + } + + fn clause(input: Node) -> ParseResult { + Ok(match_nodes!(input.into_children(); + [separator(_), num(n)] => ParseNodes::Offset(n), + [separator(_), body(_)] => ParseNodes::Body, + [separator(_), branch(b)] => ParseNodes::If(b) + )) + } + + fn path(input: Node) -> ParseResult { + Ok(match_nodes!(input.into_children(); + [root(_), clause(c).., EOI(_)] => ParsePath::from_iter(c), + )) + } +} + +// Parse the path +#[allow(dead_code)] +pub fn parse_path(input_str: &str) -> Result>> { + let entries = PathParser::parse(Rule::path, input_str)?; + let entry = entries.single()?; + + PathParser::path(entry).map_err(Box::new) +} + +#[cfg(test)] +#[test] +fn root() { + let path = parse_path(".").unwrap(); + dbg!(path.get_path()); + assert_eq!(path.get_path(), Vec::new()) +} + +#[test] +fn body() { + let path = parse_path(".-b").unwrap(); + dbg!(path.get_path()); + assert_eq!(path.get_path(), vec![ParseNodes::Body]) +} + +#[test] +fn branch() { + let path = parse_path(".-f").unwrap(); + dbg!(path.get_path()); + assert_eq!(path.get_path(), vec![ParseNodes::If(false)]) +} + +#[test] +fn offset() { + let path = parse_path(".-0-1").unwrap(); + dbg!(path.get_path()); + assert_eq!( + path.get_path(), + vec![ParseNodes::Offset(0), ParseNodes::Offset(1)] + ) +} + +#[test] +fn multiple() { + let path = parse_path(".-0-1-b-t").unwrap(); + dbg!(path.get_path()); + assert_eq!( + path.get_path(), + vec![ + ParseNodes::Offset(0), + ParseNodes::Offset(1), + ParseNodes::Body, + ParseNodes::If(true) + ] + ) +} From 8b17e752eedea60c4a4d7dc29befa160a812046d Mon Sep 17 00:00:00 2001 From: Akash Dhiraj Date: Tue, 3 Dec 2024 20:46:40 -0500 Subject: [PATCH 04/12] Queues: add instructions for converting tests to Calyx (#2364) What is says on the tin (as discussed on this [slack thread](https://cucapra.slack.com/archives/C06CV424G94/p1727223025447109)) Due to a new [release](https://releases.rs/docs/1.83.0/) for rust, CI catches a few errors (unrelated to this PR). For now, we simply pin to an older version: - remove toolchain argument for `setup-rust-toolchain@v1` in `rust.yml` - add `rust-toolchain.toml` --- .github/workflows/rust.yml | 2 -- frontends/queues/README.md | 27 +++++++++++++++++++++++++-- rust-toolchain.toml | 2 ++ 3 files changed, 27 insertions(+), 4 deletions(-) create mode 100644 rust-toolchain.toml diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml index 1a9f9f5963..f796428231 100644 --- a/.github/workflows/rust.yml +++ b/.github/workflows/rust.yml @@ -20,8 +20,6 @@ jobs: uses: actions/checkout@v4 - name: Install Rust stable uses: actions-rust-lang/setup-rust-toolchain@v1 - with: - toolchain: stable - name: Build calyx dev run: cargo build - name: Check calyx build diff --git a/frontends/queues/README.md b/frontends/queues/README.md index 139e974843..882359c905 100644 --- a/frontends/queues/README.md +++ b/frontends/queues/README.md @@ -1,12 +1,35 @@ # Queues Library -See the [docs](https://docs.calyxir.org/frontends/queues.html) for more details. +See the [docs][docs] for more details. ## Installation To use our queues: -1. Install [flit](https://flit.readthedocs.io/en/latest/#install) +1. Install [flit][flit] 2. Install the `queues` package: ``` $ cd frontends/queues/ $ flit install --symlink +``` + +## Converting Tests to Calyx + +To convert any of our [randomized tests][testing-harness] to a single Calyx file and their associated data and expect files: + +0. Follow the [installation instructions](#installation) +1. Choose a test by picking a `.py` file in [`tests/`][tests-dir] +2. Convert the test to Calyx: +``` +python3 _test.py 20000 --keepgoing > _test.futil ``` +3. Run the script [`gen_test_data.sh`][gen_test_data.sh] to generate data and expect files: +``` +./gen_test_data.sh +``` + +The files `_test.py`, `_test.data`, and `_test.expect` contain the Calyx program, input data, and expected outputs for the test. + +[docs]: https://docs.calyxir.org/frontends/queues.html +[flit]: https://flit.readthedocs.io/en/latest/#install +[testing-harness]: https://docs.calyxir.org/frontends/queues.html#shared-testing-harness +[tests-dir]: ./tests/ +[gen_test_data.sh]: ./test_data_gen/gen_test_data.sh \ No newline at end of file diff --git a/rust-toolchain.toml b/rust-toolchain.toml new file mode 100644 index 0000000000..2e2b8c8521 --- /dev/null +++ b/rust-toolchain.toml @@ -0,0 +1,2 @@ +[toolchain] +channel = "1.82.0" From 23d78cdf2c2253c368eca1aca473dc206b1d7029 Mon Sep 17 00:00:00 2001 From: Angelica-Schell <47483301+Angelica-Schell@users.noreply.github.com> Date: Tue, 3 Dec 2024 23:39:57 -0500 Subject: [PATCH 05/12] Ieee special values (#2367) Adding functions to check if values are special IEEE values (Nan, infinity, denormalized) --- .../data-conversion/src/float_special_values | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 tools/data-conversion/src/float_special_values diff --git a/tools/data-conversion/src/float_special_values b/tools/data-conversion/src/float_special_values new file mode 100644 index 0000000000..96aadf84ef --- /dev/null +++ b/tools/data-conversion/src/float_special_values @@ -0,0 +1,32 @@ +use num_bigint::BigUint; +use std::str::FromStr; + +pub struct IntermediateRepresentation { + pub sign: bool, + pub mantissa: BigUint, + pub exponent: i64, // Arbitrary precision exponent +} + +impl IntermediateRepresentation { + // Function to check if the value is NaN + pub fn is_nan(&self, bit_width: usize) -> bool { + let max_exponent_value = (1 << (bit_width - 1)) - 1; // Max exponent for NaN + self.exponent == max_exponent_value as i64 && !self.mantissa.is_zero() + } + + // Function to check if the value is infinity + pub fn is_infinity(&self, bit_width: usize) -> bool { + let max_exponent_value = (1 << (bit_width - 1)) - 1; // Max exponent for infinity + self.exponent == max_exponent_value as i64 && self.mantissa.is_zero() + } + + // Function to check if the value is denormalized + pub fn is_denormalized(&self) -> bool { + self.exponent == 0 && !self.mantissa.is_zero() + } + + // Function to check if the value is zero + pub fn is_zero(&self) -> bool { + self.exponent == 0 && self.mantissa.is_zero() + } +} From 53e9d299a84166bccbdd231bb422f08d16f3a3f0 Mon Sep 17 00:00:00 2001 From: Ethan Uppal <113849268+ethanuppal@users.noreply.github.com> Date: Wed, 4 Dec 2024 01:27:17 -0500 Subject: [PATCH 06/12] Fix failing tests on `main` due to new Rust version (#2365) Uses interior mutability with a `RwLock` and `lazy_static!`. --- Cargo.lock | 1 + calyx-frontend/src/parser.rs | 14 +++++--- calyx-utils/Cargo.toml | 1 + calyx-utils/src/errors.rs | 2 +- calyx-utils/src/position.rs | 63 ++++++++++++++++++++---------------- 5 files changed, 49 insertions(+), 32 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 7eba776379..78ac90b395 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -429,6 +429,7 @@ version = "0.7.1" dependencies = [ "atty", "itertools 0.11.0", + "lazy_static", "petgraph", "serde", "serde_json", diff --git a/calyx-frontend/src/parser.rs b/calyx-frontend/src/parser.rs index ce1044e934..47938508dc 100644 --- a/calyx-frontend/src/parser.rs +++ b/calyx-frontend/src/parser.rs @@ -60,10 +60,13 @@ impl CalyxParser { let file = GlobalPositionTable::as_mut() .add_file(path.to_string_lossy().to_string(), string_content); let user_data = UserData { file }; - let content = GlobalPositionTable::as_ref().get_source(file); + let gpos_ref = GlobalPositionTable::as_ref(); + let content = gpos_ref.get_source(file).to_owned(); + drop(gpos_ref); + // Parse the file let inputs = - CalyxParser::parse_with_userdata(Rule::file, content, user_data) + CalyxParser::parse_with_userdata(Rule::file, &content, user_data) .map_err(|e| e.with_path(&path.to_string_lossy())) .map_err(|e| { calyx_utils::Error::parse_error(e.variant.message()) @@ -96,10 +99,13 @@ impl CalyxParser { let file = GlobalPositionTable::as_mut().add_file("".to_string(), buf); let user_data = UserData { file }; - let contents = GlobalPositionTable::as_ref().get_source(file); + let gpos_ref = GlobalPositionTable::as_ref(); + let content = gpos_ref.get_source(file).to_owned(); + drop(gpos_ref); + // Parse the input let inputs = - CalyxParser::parse_with_userdata(Rule::file, contents, user_data) + CalyxParser::parse_with_userdata(Rule::file, &content, user_data) .map_err(|e| { calyx_utils::Error::parse_error(e.variant.message()) .with_pos(&Self::error_span(&e, file)) diff --git a/calyx-utils/Cargo.toml b/calyx-utils/Cargo.toml index da438c0d4c..6d3dc94693 100644 --- a/calyx-utils/Cargo.toml +++ b/calyx-utils/Cargo.toml @@ -23,3 +23,4 @@ string-interner.workspace = true itertools.workspace = true petgraph.workspace = true symbol_table = { version = "0.3", features = ["global"] } +lazy_static.workspace = true diff --git a/calyx-utils/src/errors.rs b/calyx-utils/src/errors.rs index b087d017aa..b560fdeec0 100644 --- a/calyx-utils/src/errors.rs +++ b/calyx-utils/src/errors.rs @@ -179,7 +179,7 @@ impl Error { post_msg: None, } } - pub fn location(&self) -> (&str, usize, usize) { + pub fn location(&self) -> (String, usize, usize) { self.pos.get_location() } pub fn message(&self) -> String { diff --git a/calyx-utils/src/position.rs b/calyx-utils/src/position.rs index 2b74e99a24..fb5333897f 100644 --- a/calyx-utils/src/position.rs +++ b/calyx-utils/src/position.rs @@ -1,7 +1,12 @@ //! Definitions for tracking source position information of Calyx programs use itertools::Itertools; -use std::{cmp, fmt::Write, mem, sync}; +use lazy_static::lazy_static; +use std::{ + cmp, + fmt::Write, + sync::{RwLock, RwLockReadGuard, RwLockWriteGuard}, +}; #[derive(Clone, Copy, PartialEq, Eq, Debug)] /// Handle to a position in a [PositionTable] @@ -99,28 +104,28 @@ impl PositionTable { /// The global position table pub struct GlobalPositionTable; +lazy_static! { + static ref GPOS_TABLE: RwLock = + RwLock::new(PositionTable::default()); +} + impl GlobalPositionTable { - /// Return reference to a global [PositionTable] - pub fn as_mut() -> &'static mut PositionTable { - static mut SINGLETON: mem::MaybeUninit = - mem::MaybeUninit::uninit(); - static ONCE: sync::Once = sync::Once::new(); - - // SAFETY: - // - writing to the singleton is OK because we only do it one time - // - the ONCE guarantees that SINGLETON is init'ed before assume_init_ref - unsafe { - ONCE.call_once(|| { - SINGLETON.write(PositionTable::new()); - assert!(PositionTable::UNKNOWN == GPosIdx::UNKNOWN.0) - }); - SINGLETON.assume_init_mut() - } + /// Return reference to a global [PositionTable]. + /// + /// # Safety + /// + /// You may not call this function after any call to [`Self::as_ref`]. + pub fn as_mut() -> RwLockWriteGuard<'static, PositionTable> { + GPOS_TABLE + .try_write() + .expect("failed to get write lock for global position table") } /// Return an immutable reference to the global position table - pub fn as_ref() -> &'static PositionTable { - Self::as_mut() + pub fn as_ref() -> RwLockReadGuard<'static, PositionTable> { + GPOS_TABLE + .try_read() + .expect("failed to get read lock for global position table") } } @@ -152,7 +157,7 @@ impl GPosIdx { /// 1. lines associated with this span /// 2. start position of the first line in span /// 3. line number of the span - fn get_lines(&self) -> (Vec<&str>, usize, usize) { + fn get_lines(&self) -> (Vec, usize, usize) { let table = GlobalPositionTable::as_ref(); let pos_d = table.get_pos(self.0); let file = &table.get_file_data(pos_d.file).source; @@ -181,16 +186,20 @@ impl GPosIdx { pos = next_pos + 1; linum += 1; } - (buf, out_idx, out_line) + ( + buf.into_iter().map(|str| str.to_owned()).collect(), + out_idx, + out_line, + ) } /// returns: /// 1. the name of the file the span is in /// 2. the (inclusive) range of lines within the span - pub fn get_line_num(&self) -> (&String, (usize, usize)) { + pub fn get_line_num(&self) -> (String, (usize, usize)) { let table = GlobalPositionTable::as_ref(); let pos_data = table.get_pos(self.0); - let file_name = &table.get_file_data(pos_data.file).name; + let file_name = table.get_file_data(pos_data.file).name.clone(); let (buf, _, line_num) = self.get_lines(); //reformat to return the range (inclusive) let rng = (line_num, line_num + buf.len() - 1); @@ -205,7 +214,7 @@ impl GPosIdx { let (lines, pos, linum) = self.get_lines(); let mut buf = String::new(); - let l = lines[0]; + let l = lines[0].as_str(); let linum_text = format!("{} ", linum); let linum_space: String = " ".repeat(linum_text.len()); let mark: String = "^".repeat(cmp::min( @@ -238,17 +247,17 @@ impl GPosIdx { buf } - pub fn get_location(&self) -> (&str, usize, usize) { + pub fn get_location(&self) -> (String, usize, usize) { let table = GlobalPositionTable::as_ref(); let pos_d = table.get_pos(self.0); - let name = &table.get_file_data(pos_d.file).name; + let name = table.get_file_data(pos_d.file).name.clone(); (name, pos_d.start, pos_d.end) } /// Visualizes the span without any message or marking pub fn show(&self) -> String { let (lines, _, linum) = self.get_lines(); - let l = lines[0]; + let l = lines[0].as_str(); let linum_text = format!("{} ", linum); format!("{}|{}\n", linum_text, l) } From 445e1740aa36743897bfe3d163dd4f3c32c7a6b5 Mon Sep 17 00:00:00 2001 From: Griffin Berlstein Date: Wed, 4 Dec 2024 19:58:41 +0000 Subject: [PATCH 07/12] [Cider] Clock propagation (#2368) This somewhat chunky PR includes the logic needed to propagate clocks through combinational logic and amends the read checks to defer until the value is used in a non-combinational context. The continuous assignments now run under a single thread which is never synchronized, so attempts to write a register in continuous logic will always result in a race when used outside continuous logic. There's some additional refactoring and minor changes to the primitive interface. Additionally, a single step can now advance past multiple control nodes, which should reduce some of the repetition when using the debugger --- Cargo.lock | 1 - interp/Cargo.toml | 1 - interp/src/as_raw.rs | 4 +- interp/src/debugger/commands/core.rs | 35 +- .../src/debugger/debugging_context/context.rs | 12 +- interp/src/errors.rs | 21 +- interp/src/flatten/flat_ir/base.rs | 107 +- .../src/flatten/flat_ir/control/translator.rs | 9 +- interp/src/flatten/flat_ir/flatten_trait.rs | 2 +- .../src/flatten/primitives/combinational.rs | 35 +- interp/src/flatten/primitives/macros.rs | 70 +- interp/src/flatten/primitives/prim_trait.rs | 35 +- .../src/flatten/primitives/stateful/math.rs | 101 +- .../flatten/primitives/stateful/memories.rs | 144 +- .../structures/environment/assignments.rs | 73 +- .../flatten/structures/environment/clock.rs | 144 +- .../src/flatten/structures/environment/env.rs | 1212 +++++++++++------ .../structures/environment/program_counter.rs | 64 +- interp/src/flatten/structures/index_trait.rs | 66 +- interp/src/flatten/structures/indexed_map.rs | 13 +- interp/src/flatten/structures/thread.rs | 11 +- interp/tests/data-race/conflict.expect | 4 + interp/tests/data-race/conflict.futil | 66 + interp/tests/data-race/continuous-race.expect | 4 + interp/tests/data-race/continuous-race.futil | 28 + interp/tests/data-race/guard-conflict.expect | 2 +- .../tests/data-race/par-conflict-cmem.expect | 2 +- interp/tests/data-race/par-conflict.expect | 2 +- interp/tests/data-race/strange_mult.expect | 4 + interp/tests/data-race/strange_mult.futil | 50 + 30 files changed, 1638 insertions(+), 684 deletions(-) create mode 100644 interp/tests/data-race/conflict.expect create mode 100644 interp/tests/data-race/conflict.futil create mode 100644 interp/tests/data-race/continuous-race.expect create mode 100644 interp/tests/data-race/continuous-race.futil create mode 100644 interp/tests/data-race/strange_mult.expect create mode 100644 interp/tests/data-race/strange_mult.futil diff --git a/Cargo.lock b/Cargo.lock index 78ac90b395..e5db4631e3 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1463,7 +1463,6 @@ dependencies = [ "fraction", "fst-writer", "itertools 0.11.0", - "lazy_static", "num-bigint", "num-traits", "once_cell", diff --git a/interp/Cargo.toml b/interp/Cargo.toml index 8d99d1a848..49926126aa 100644 --- a/interp/Cargo.toml +++ b/interp/Cargo.toml @@ -16,7 +16,6 @@ path = "src/main.rs" [dependencies] smallvec = { workspace = true, features = ["union", "const_generics"] } serde = { workspace = true, features = ["derive", "rc"] } -lazy_static.workspace = true itertools.workspace = true pest.workspace = true pest_derive.workspace = true diff --git a/interp/src/as_raw.rs b/interp/src/as_raw.rs index dada77d2df..a14ac7d812 100644 --- a/interp/src/as_raw.rs +++ b/interp/src/as_raw.rs @@ -17,12 +17,12 @@ impl AsRaw for *const T { } } -impl<'a, T> AsRaw for &Ref<'a, T> { +impl AsRaw for &Ref<'_, T> { fn as_raw(&self) -> *const T { self as &T as *const T } } -impl<'a, T> AsRaw for Ref<'a, T> { +impl AsRaw for Ref<'_, T> { fn as_raw(&self) -> *const T { self as &T as *const T } diff --git a/interp/src/debugger/commands/core.rs b/interp/src/debugger/commands/core.rs index 5d5e9689af..f9267c5a13 100644 --- a/interp/src/debugger/commands/core.rs +++ b/interp/src/debugger/commands/core.rs @@ -1,7 +1,6 @@ //! This module contains the core data structures and commands used by the debugger use itertools::{self, Itertools}; -use lazy_static::lazy_static; use owo_colors::OwoColorize; use std::{ fmt::{Display, Write}, @@ -403,7 +402,7 @@ impl Command { invocation: names, description: message, .. - } in COMMAND_INFO.iter() + } in get_command_info().iter() { writeln!(out, " {: <30}{}", names.join(", "), message.green()) .unwrap(); @@ -419,7 +418,9 @@ impl Command { invocation, description, usage_example, - } in COMMAND_INFO.iter().filter(|x| !x.usage_example.is_empty()) + } in get_command_info() + .iter() + .filter(|x| !x.usage_example.is_empty()) { writeln!(out).unwrap(); writeln!(out, "{}", invocation.join(", ")).unwrap(); @@ -438,11 +439,16 @@ impl Command { // I wouldn't recommend looking at this -lazy_static! { - /// A (lazy) static list of [CommandInfo] objects used for the help and - /// explain messages - static ref COMMAND_INFO: Vec = { - vec![ +use std::sync::OnceLock; +/// A (lazy) static list of [CommandInfo] objects used for the help and +/// explain messages. Access via [get_command_info] +static COMMAND_INFO: OnceLock> = OnceLock::new(); + +/// Returns the list of [CommandInfo] objects used for the help and explain +/// messages +fn get_command_info() -> &'static [CommandInfo] { + COMMAND_INFO.get_or_init(|| { + [ // step CIBuilder::new().invocation("step") .invocation("s") @@ -522,7 +528,6 @@ lazy_static! { .description("Disable target watchpoint") .usage("> disable-watch 4") .usage("> disable-watch do_mult").build(), - // explain CIBuilder::new().invocation("explain") .description("Show examples of commands which take arguments").build(), @@ -532,15 +537,15 @@ lazy_static! { CIBuilder::new().invocation("exit") .invocation("quit") .description("Exit the debugger").build(), - ] - }; + ].into() + }) } #[derive(Clone, Debug)] struct CommandInfo { - invocation: Vec, + invocation: Box<[CommandName]>, description: Description, - usage_example: Vec, + usage_example: Box<[UsageExample]>, } // type shenanigans @@ -627,9 +632,9 @@ where impl CommandInfoBuilder { fn build(self) -> CommandInfo { CommandInfo { - invocation: self.invocation, + invocation: self.invocation.into(), description: self.description.unwrap(), - usage_example: self.usage_example, + usage_example: self.usage_example.into(), } } } diff --git a/interp/src/debugger/debugging_context/context.rs b/interp/src/debugger/debugging_context/context.rs index 7f317d3aaa..6856f5ae05 100644 --- a/interp/src/debugger/debugging_context/context.rs +++ b/interp/src/debugger/debugging_context/context.rs @@ -648,10 +648,8 @@ impl DebuggingContext { let watchpoint_indicies = self.watchpoints.get_by_group(x).unwrap(); match watchpoint_indicies { - WatchPointIndices::Before(x) => return x.iter(), - WatchPointIndices::Both { before, .. } => { - return before.iter() - } + WatchPointIndices::Before(x) => x.iter(), + WatchPointIndices::Both { before, .. } => before.iter(), // this is stupid but works _ => [].iter(), } @@ -665,10 +663,8 @@ impl DebuggingContext { let watchpoint_indicies = self.watchpoints.get_by_group(x).unwrap(); match watchpoint_indicies { - WatchPointIndices::After(x) => return x.iter(), - WatchPointIndices::Both { after, .. } => { - return after.iter() - } + WatchPointIndices::After(x) => x.iter(), + WatchPointIndices::Both { after, .. } => after.iter(), // this is stupid but works _ => [].iter(), } diff --git a/interp/src/errors.rs b/interp/src/errors.rs index 43b1e2c775..192ef33443 100644 --- a/interp/src/errors.rs +++ b/interp/src/errors.rs @@ -225,7 +225,7 @@ pub enum RuntimeError { OverflowError, #[error(transparent)] - ConflictingAssignments(ConflictingAssignments), + ConflictingAssignments(Box), } // this is silly but needed to make the program print something sensible when returning @@ -299,7 +299,8 @@ impl RuntimeError { } match self { - RuntimeError::ConflictingAssignments(ConflictingAssignments { target, a1, a2 }) => { + RuntimeError::ConflictingAssignments(boxed_err) => { + let ConflictingAssignments { target, a1, a2 } = *boxed_err; let (a1_str, a1_source) = assign_to_string(&a1, env); let (a2_str, a2_source) = assign_to_string(&a2, env); @@ -323,8 +324,20 @@ impl RuntimeError { RuntimeError::UndefinedReadAddr(c) => CiderError::GenericError(format!("Attempted to read from an undefined memory address from memory named \"{}\"", env.get_full_name(c))), RuntimeError::ClockError(clk) => { match clk { - ClockError::ReadWrite(c) => CiderError::GenericError(format!("Concurrent read & write to the same register/memory {}", env.get_full_name(c).underline())), - ClockError::WriteWrite(c) => CiderError::GenericError(format!("Concurrent writes to the same register/memory {}", env.get_full_name(c).underline())), + ClockError::ReadWrite(c, num) => { + if let Some(entry_number) = num { + CiderError::GenericError(format!("Concurrent read & write to the same memory {} in slot {}", env.get_full_name(c).underline(), entry_number)) + } else { + CiderError::GenericError(format!("Concurrent read & write to the same register {}", env.get_full_name(c).underline())) + } + }, + ClockError::WriteWrite(c, num) => { + if let Some(entry_number) = num { + CiderError::GenericError(format!("Concurrent writes to the same memory {} in slot {}", env.get_full_name(c).underline(), entry_number)) + } else { + CiderError::GenericError(format!("Concurrent writes to the same register {}", env.get_full_name(c).underline())) + } + }, c => CiderError::GenericError(format!("Unexpected clock error: {c:?}")), } } diff --git a/interp/src/flatten/flat_ir/base.rs b/interp/src/flatten/flat_ir/base.rs index 93b8c100cc..e92d08fc45 100644 --- a/interp/src/flatten/flat_ir/base.rs +++ b/interp/src/flatten/flat_ir/base.rs @@ -13,6 +13,7 @@ use crate::{ serialization::PrintCode, }; use baa::{BitVecOps, BitVecValue}; +use std::collections::HashSet; // making these all u32 for now, can give the macro an optional type as the // second arg to contract or expand as needed @@ -428,12 +429,24 @@ impl From<(GlobalCellIdx, AssignmentIdx)> for AssignmentWinner { /// A struct representing a value that has been assigned to a port. It wraps a /// concrete value and the "winner" which assigned it. -#[derive(Clone, PartialEq)] +#[derive(Clone)] pub struct AssignedValue { val: BitVecValue, winner: AssignmentWinner, thread: Option, clocks: Option, + propagate_clocks: bool, + transitive_clocks: Option>, +} + +impl AssignedValue { + pub fn eq_no_transitive_clocks(&self, other: &Self) -> bool { + self.val == other.val + && self.winner == other.winner + && self.thread == other.thread + && self.clocks == other.clocks + && self.propagate_clocks == other.propagate_clocks + } } impl std::fmt::Debug for AssignedValue { @@ -442,6 +455,8 @@ impl std::fmt::Debug for AssignedValue { .field("val", &self.val.to_bit_str()) .field("winner", &self.winner) .field("thread", &self.thread) + .field("clocks", &self.clocks) + .field("propagate_clocks", &self.propagate_clocks) .finish() } } @@ -461,9 +476,37 @@ impl AssignedValue { winner: winner.into(), thread: None, clocks: None, + propagate_clocks: false, + transitive_clocks: None, } } + /// Adds a clock to the set of transitive reads associated with this value + pub fn add_transitive_clock(&mut self, clock_pair: ClockPair) { + self.transitive_clocks + .get_or_insert_with(Default::default) + .insert(clock_pair); + } + + pub fn add_transitive_clocks>( + &mut self, + clocks: I, + ) { + self.transitive_clocks + .get_or_insert_with(Default::default) + .extend(clocks); + } + + pub fn iter_transitive_clocks( + &self, + ) -> impl Iterator + '_ { + self.transitive_clocks + .as_ref() + .map(|set| set.iter().copied()) + .into_iter() + .flatten() + } + pub fn with_thread(mut self, thread: ThreadIdx) -> Self { self.thread = Some(thread); self @@ -479,6 +522,31 @@ impl AssignedValue { self } + pub fn with_clocks_optional( + mut self, + clock_pair: Option, + ) -> Self { + self.clocks = clock_pair; + self + } + + pub fn with_transitive_clocks_opt( + mut self, + clocks: Option>, + ) -> Self { + self.transitive_clocks = clocks; + self + } + + pub fn with_propagate_clocks(mut self) -> Self { + self.propagate_clocks = true; + self + } + + pub fn set_propagate_clocks(&mut self, propagate_clocks: bool) { + self.propagate_clocks = propagate_clocks; + } + /// Returns true if the two AssignedValues do not have the same winner pub fn has_conflict_with(&self, other: &Self) -> bool { self.winner != other.winner @@ -497,36 +565,21 @@ impl AssignedValue { /// A utility constructor which returns a new implicitly assigned value with /// a one bit high value pub fn implicit_bit_high() -> Self { - Self { - val: BitVecValue::tru(), - winner: AssignmentWinner::Implicit, - thread: None, - clocks: None, - } + Self::new(BitVecValue::tru(), AssignmentWinner::Implicit) } /// A utility constructor which returns an [`AssignedValue`] with the given /// value and a [`AssignmentWinner::Cell`] as the winner #[inline] pub fn cell_value(val: BitVecValue) -> Self { - Self { - val, - winner: AssignmentWinner::Cell, - thread: None, - clocks: None, - } + Self::new(val, AssignmentWinner::Cell) } /// A utility constructor which returns an [`AssignedValue`] with the given /// value and a [`AssignmentWinner::Implicit`] as the winner #[inline] pub fn implicit_value(val: BitVecValue) -> Self { - Self { - val, - winner: AssignmentWinner::Implicit, - thread: None, - clocks: None, - } + Self::new(val, AssignmentWinner::Implicit) } /// A utility constructor which returns an [`AssignedValue`] with a one bit @@ -549,6 +602,14 @@ impl AssignedValue { pub fn clocks(&self) -> Option<&ClockPair> { self.clocks.as_ref() } + + pub fn transitive_clocks(&self) -> Option<&HashSet> { + self.transitive_clocks.as_ref() + } + + pub fn propagate_clocks(&self) -> bool { + self.propagate_clocks + } } #[derive(Debug, Clone, Default)] @@ -595,6 +656,14 @@ impl PortValue { self } + pub fn transitive_clocks(&self) -> Option<&HashSet> { + self.0.as_ref().and_then(|x| x.transitive_clocks()) + } + + pub fn as_option_mut(&mut self) -> Option<&mut AssignedValue> { + self.0.as_mut() + } + /// If the value is defined, returns the value cast to a boolean. Otherwise /// returns `None`. It will panic if the given value is not one bit wide. pub fn as_bool(&self) -> Option { diff --git a/interp/src/flatten/flat_ir/control/translator.rs b/interp/src/flatten/flat_ir/control/translator.rs index 5efa5d284c..193af5bf13 100644 --- a/interp/src/flatten/flat_ir/control/translator.rs +++ b/interp/src/flatten/flat_ir/control/translator.rs @@ -290,8 +290,13 @@ fn translate_component( .collect_vec(); // Will need to rethink this at some point - if go_ports.len() != 1 || done_ports.len() != 1 { - todo!("handle multiple go and done ports"); + if go_ports.len() > 1 || done_ports.len() > 1 { + todo!( + "handle multiple go and done ports. On component: {}", + comp.name + ); + } else if comp.is_comb { + todo!("handle comb components. On component: {}", comp.name); } let go_port = &go_ports[0]; let done_port = &done_ports[0]; diff --git a/interp/src/flatten/flat_ir/flatten_trait.rs b/interp/src/flatten/flat_ir/flatten_trait.rs index 41d0cf0b33..4aa500c567 100644 --- a/interp/src/flatten/flat_ir/flatten_trait.rs +++ b/interp/src/flatten/flat_ir/flatten_trait.rs @@ -74,7 +74,7 @@ where handle: &'a mut VecHandle<'outer, In, Idx, Out>, } -impl<'a, 'outer, In, Idx, Out> SingleHandle<'a, 'outer, In, Idx, Out> +impl<'outer, In, Idx, Out> SingleHandle<'_, 'outer, In, Idx, Out> where Idx: IndexRef, { diff --git a/interp/src/flatten/primitives/combinational.rs b/interp/src/flatten/primitives/combinational.rs index 8df70e4352..3da8b99194 100644 --- a/interp/src/flatten/primitives/combinational.rs +++ b/interp/src/flatten/primitives/combinational.rs @@ -4,7 +4,10 @@ use crate::flatten::{ all_defined, comb_primitive, declare_ports, ports, prim_trait::UpdateStatus, utils::floored_division, Primitive, }, - structures::environment::PortMap, + structures::{ + environment::PortMap, + index_trait::{IndexRef, SplitIndexRange}, + }, }; use baa::{BitVecOps, BitVecValue}; @@ -34,18 +37,18 @@ impl Primitive for StdConst { }) } - fn exec_cycle(&mut self, _port_map: &mut PortMap) -> UpdateResult { - Ok(UpdateStatus::Unchanged) - } - - fn has_comb(&self) -> bool { + fn has_comb_path(&self) -> bool { true } - fn has_stateful(&self) -> bool { + fn has_stateful_path(&self) -> bool { false } + fn get_ports(&self) -> SplitIndexRange { + SplitIndexRange::new(self.out, self.out, (self.out.index() + 1).into()) + } + fn clone_boxed(&self) -> Box { Box::new(self.clone()) } @@ -53,19 +56,19 @@ impl Primitive for StdConst { #[derive(Clone)] pub struct StdMux { - base: GlobalPortIdx, + base_port: GlobalPortIdx, } impl StdMux { - declare_ports![ COND: 0, TRU: 1, FAL:2, OUT: 3]; + declare_ports![ COND: 0, TRU: 1 | FAL:2, OUT: 3 ]; pub fn new(base: GlobalPortIdx) -> Self { - Self { base } + Self { base_port: base } } } impl Primitive for StdMux { fn exec_comb(&self, port_map: &mut PortMap) -> UpdateResult { - ports![&self.base; cond: Self::COND, tru: Self::TRU, fal: Self::FAL, out: Self::OUT]; + ports![&self.base_port; cond: Self::COND, tru: Self::TRU, fal: Self::FAL, out: Self::OUT]; let winning_idx = port_map[cond].as_bool().map(|c| if c { tru } else { fal }); @@ -83,10 +86,14 @@ impl Primitive for StdMux { } } - fn has_stateful(&self) -> bool { + fn has_stateful_path(&self) -> bool { false } + fn get_ports(&self) -> SplitIndexRange { + self.get_signature() + } + fn clone_boxed(&self) -> Box { Box::new(self.clone()) } @@ -300,6 +307,10 @@ impl Primitive for StdUndef { Ok(UpdateStatus::Unchanged) } + fn get_ports(&self) -> SplitIndexRange { + SplitIndexRange::new(self.0, self.0, (self.0.index() + 1).into()) + } + fn clone_boxed(&self) -> Box { Box::new(self.clone()) } diff --git a/interp/src/flatten/primitives/macros.rs b/interp/src/flatten/primitives/macros.rs index bf75c6f1b4..21084c770e 100644 --- a/interp/src/flatten/primitives/macros.rs +++ b/interp/src/flatten/primitives/macros.rs @@ -1,12 +1,70 @@ +// taken from https://veykril.github.io/tlborm/decl-macros/building-blocks/counting.html +macro_rules! replace_expr { + ($_t:tt $sub:expr) => { + $sub + }; +} + +macro_rules! count_tts { + ($($tts:tt)*) => {0usize $(+ $crate::flatten::primitives::macros::replace_expr!($tts 1usize))*}; +} +// -- https://veykril.github.io/tlborm/decl-macros/building-blocks/counting.html + +pub(crate) use count_tts; +pub(crate) use replace_expr; + macro_rules! ports { ($base:expr; $( $port:ident : $offset:expr ),+ ) => { $(let $port: $crate::flatten::flat_ir::prelude::GlobalPortIdx = ($crate::flatten::structures::index_trait::IndexRef::index($base) + $offset).into();)+ } } +/// Declare a list of ports for the primitive with their offsets given relative +/// to the cell's base port.A vertical bar is used to separate the input and +/// output ports +/// +/// ## NOTE: These must be given in ascending order. And the base port of the struct must be named `base_port` +/// +/// ```ignore +/// // Example +/// // declare COND, TRU, FAL as input ports +/// // declare OUT as output port +/// declare_ports![ COND: 0, TRU: 1, FAL:2 | OUT: 3]; +/// ``` macro_rules! declare_ports { - ($( $port:ident : $offset:expr ),+ $(,)? ) => { + ($( $input_port:ident : $input_offset:literal ),+ $(,)? | $( $output_port:ident : $output_offset:literal ),+ $(,)? ) => { + + $( + #[allow(non_upper_case_globals)] + const $input_port: usize = $input_offset; // this is a usize because it encodes the position of the port! + )+ + + $( + #[allow(non_upper_case_globals)] + const $output_port: usize = $output_offset; // this is a usize because it encodes the position of the port! + )+ + // determine the offset of the first and last output ports + const SPLIT_IDX: usize = [$($output_offset),+][0]; + const END_IDX: usize = ([$($output_offset),+][$crate::flatten::primitives::macros::count_tts!($($output_offset)+) - 1]) + 1; + + #[inline] + pub fn get_signature(&self) -> $crate::flatten::structures::index_trait::SplitIndexRange<$crate::flatten::flat_ir::prelude::GlobalPortIdx> { + use $crate::flatten::structures::index_trait::IndexRef; + + $crate::flatten::structures::index_trait::SplitIndexRange::new(self.base_port, + $crate::flatten::flat_ir::prelude::GlobalPortIdx::new(self.base_port.index() + Self::SPLIT_IDX), + $crate::flatten::flat_ir::prelude::GlobalPortIdx::new(self.base_port.index() + Self::END_IDX), + ) + } + } +} + +/// Declare a list of ports for the primitive with their offsets given relative +/// to the cell's base port. Unlike `declare_ports` this does not generate a +/// `get_signature` function or distinguish between input and output ports. +macro_rules! declare_ports_no_signature { + ($( $port:ident : $offset:literal ),+ $(,)? ) => { $( #[allow(non_upper_case_globals)] const $port: usize = $offset; // this is a usize because it encodes the position of the port! @@ -27,6 +85,7 @@ macro_rules! make_getters { } pub(crate) use declare_ports; +pub(crate) use declare_ports_no_signature; pub(crate) use make_getters; pub(crate) use ports; @@ -46,8 +105,7 @@ macro_rules! comb_primitive { impl $name { - $crate::flatten::primitives::macros::declare_ports![$($port: $port_idx),+]; - $crate::flatten::primitives::macros::declare_ports![$out_port: $out_port_idx,]; + $crate::flatten::primitives::macros::declare_ports![$($port: $port_idx),+ | $out_port: $out_port_idx]; #[allow(non_snake_case)] pub fn new( @@ -98,10 +156,14 @@ macro_rules! comb_primitive { } } - fn has_stateful(&self) -> bool { + fn has_stateful_path(&self) -> bool { false } + fn get_ports(&self) -> $crate::flatten::structures::index_trait::SplitIndexRange<$crate::flatten::flat_ir::prelude::GlobalPortIdx> { + self.get_signature() + } + fn clone_boxed(&self) -> Box { Box::new(Self { base_port: self.base_port, diff --git a/interp/src/flatten/primitives/prim_trait.rs b/interp/src/flatten/primitives/prim_trait.rs index 199adce455..4a94324485 100644 --- a/interp/src/flatten/primitives/prim_trait.rs +++ b/interp/src/flatten/primitives/prim_trait.rs @@ -4,6 +4,7 @@ use crate::{ flat_ir::base::GlobalPortIdx, structures::{ environment::{clock::ClockMap, PortMap}, + index_trait::SplitIndexRange, thread::ThreadMap, }, }, @@ -109,15 +110,15 @@ pub trait Primitive { Ok(UpdateStatus::Unchanged) } - fn exec_cycle(&mut self, _port_map: &mut PortMap) -> UpdateResult { - Ok(UpdateStatus::Unchanged) + fn exec_cycle(&mut self, _port_map: &mut PortMap) -> RuntimeResult<()> { + Ok(()) } - fn has_comb(&self) -> bool { + fn has_comb_path(&self) -> bool { true } - fn has_stateful(&self) -> bool { + fn has_stateful_path(&self) -> bool { true } @@ -135,6 +136,13 @@ pub trait Primitive { None } + fn get_ports(&self) -> SplitIndexRange; + + /// Returns `true` if this primitive only has a combinational part + fn is_combinational(&self) -> bool { + self.has_comb_path() && !self.has_stateful_path() + } + fn clone_boxed(&self) -> Box; } @@ -153,7 +161,7 @@ pub trait RaceDetectionPrimitive: Primitive { port_map: &mut PortMap, _clock_map: &mut ClockMap, _thread_map: &ThreadMap, - ) -> UpdateResult { + ) -> RuntimeResult<()> { self.exec_cycle(port_map) } @@ -163,20 +171,3 @@ pub trait RaceDetectionPrimitive: Primitive { fn clone_boxed_rd(&self) -> Box; } - -/// An empty primitive implementation used for testing. It does not do anything -/// and has no ports of any kind -#[derive(Clone, Copy)] -pub struct DummyPrimitive; - -impl DummyPrimitive { - pub fn new_dyn() -> Box { - Box::new(Self) - } -} - -impl Primitive for DummyPrimitive { - fn clone_boxed(&self) -> Box { - Box::new(*self) - } -} diff --git a/interp/src/flatten/primitives/stateful/math.rs b/interp/src/flatten/primitives/stateful/math.rs index c8fb091e48..1d47fadf5d 100644 --- a/interp/src/flatten/primitives/stateful/math.rs +++ b/interp/src/flatten/primitives/stateful/math.rs @@ -1,11 +1,14 @@ -use crate::flatten::{ - flat_ir::prelude::*, - primitives::{ - declare_ports, ports, - prim_trait::*, - utils::{floored_division, int_sqrt, ShiftBuffer}, +use crate::{ + errors::RuntimeResult, + flatten::{ + flat_ir::prelude::*, + primitives::{ + declare_ports, ports, + prim_trait::*, + utils::{floored_division, int_sqrt, ShiftBuffer}, + }, + structures::{environment::PortMap, index_trait::SplitIndexRange}, }, - structures::environment::PortMap, }; use baa::{BitVecOps, BitVecValue, WidthInt}; use num_traits::Euclid; @@ -20,7 +23,7 @@ pub struct StdMultPipe { } impl StdMultPipe { - declare_ports![_CLK: 0, RESET: 1, GO: 2, LEFT: 3, RIGHT: 4, OUT: 5, DONE: 6]; + declare_ports![_CLK: 0, RESET: 1, GO: 2, LEFT: 3, RIGHT: 4, | OUT: 5, DONE: 6]; pub fn new(base_port: GlobalPortIdx, width: u32) -> Self { Self { base_port, @@ -55,7 +58,7 @@ impl Primitive for StdMultPipe { Ok(out_changed | done_signal) } - fn exec_cycle(&mut self, port_map: &mut PortMap) -> UpdateResult { + fn exec_cycle(&mut self, port_map: &mut PortMap) -> RuntimeResult<()> { ports![&self.base_port; left: Self::LEFT, right: Self::RIGHT, @@ -95,7 +98,7 @@ impl Primitive for StdMultPipe { self.done_is_high = false; } - let done_signal = port_map.insert_val_general( + port_map.insert_val_general( done, AssignedValue::cell_value(if self.done_is_high { BitVecValue::tru() @@ -104,10 +107,13 @@ impl Primitive for StdMultPipe { }), )?; - Ok( - port_map.write_exact_unchecked(out, self.current_output.clone()) - | done_signal, - ) + port_map.write_exact_unchecked(out, self.current_output.clone()); + + Ok(()) + } + + fn get_ports(&self) -> SplitIndexRange { + self.get_signature() } } @@ -122,7 +128,7 @@ pub struct StdDivPipe { } impl StdDivPipe { - declare_ports![_CLK: 0, RESET: 1, GO: 2, LEFT: 3, RIGHT: 4, OUT_QUOTIENT: 5, OUT_REMAINDER: 6, DONE: 7]; + declare_ports![_CLK: 0, RESET: 1, GO: 2, LEFT: 3, RIGHT: 4, | OUT_QUOTIENT: 5, OUT_REMAINDER: 6, DONE: 7]; pub fn new(base_port: GlobalPortIdx, width: u32) -> Self { Self { base_port, @@ -158,7 +164,7 @@ impl Primitive Ok(quot_changed | rem_changed | done_signal) } - fn exec_cycle(&mut self, port_map: &mut PortMap) -> UpdateResult { + fn exec_cycle(&mut self, port_map: &mut PortMap) -> RuntimeResult<()> { ports![&self.base_port; left: Self::LEFT, right: Self::RIGHT, @@ -226,13 +232,15 @@ impl Primitive self.done_is_high = false; } - let done_signal = port_map.set_done(done, self.done_is_high)?; - let quot_changed = port_map - .write_exact_unchecked(out_quot, self.output_quotient.clone()); - let rem_changed = port_map - .write_exact_unchecked(out_rem, self.output_remainder.clone()); + port_map.set_done(done, self.done_is_high)?; + port_map.write_exact_unchecked(out_quot, self.output_quotient.clone()); + port_map.write_exact_unchecked(out_rem, self.output_remainder.clone()); - Ok(quot_changed | rem_changed | done_signal) + Ok(()) + } + + fn get_ports(&self) -> SplitIndexRange { + self.get_signature() } } @@ -246,7 +254,7 @@ pub struct Sqrt { } impl Sqrt { - declare_ports!(_CLK: 0, RESET: 1, GO: 2, IN: 3, OUT: 4, DONE: 5); + declare_ports!(_CLK: 0, RESET: 1, GO: 2, IN: 3, | OUT: 4, DONE: 5); pub fn new( base_port: GlobalPortIdx, width: u32, @@ -277,7 +285,7 @@ impl Primitive for Sqrt { Ok(out_changed | done_changed) } - fn exec_cycle(&mut self, port_map: &mut PortMap) -> UpdateResult { + fn exec_cycle(&mut self, port_map: &mut PortMap) -> RuntimeResult<()> { ports![&self.base_port; reset: Self::RESET, go: Self::GO, @@ -315,11 +323,14 @@ impl Primitive for Sqrt { self.done_is_high = false; } - let done_signal = port_map.set_done(done, self.done_is_high)?; - let out_changed = - port_map.write_exact_unchecked(out, self.output.clone()); + port_map.set_done(done, self.done_is_high)?; + port_map.write_exact_unchecked(out, self.output.clone()); - Ok(out_changed | done_signal) + Ok(()) + } + + fn get_ports(&self) -> SplitIndexRange { + self.get_signature() } } @@ -334,7 +345,7 @@ pub struct FxpMultPipe { } impl FxpMultPipe { - declare_ports![_CLK: 0, RESET: 1, GO: 2, LEFT: 3, RIGHT: 4, OUT: 5, DONE: 6]; + declare_ports![_CLK: 0, RESET: 1, GO: 2, LEFT: 3, RIGHT: 4, | OUT: 5, DONE: 6]; pub fn new( base_port: GlobalPortIdx, int_width: u32, @@ -376,7 +387,7 @@ impl Primitive for FxpMultPipe { Ok(out_changed | done_signal) } - fn exec_cycle(&mut self, port_map: &mut PortMap) -> UpdateResult { + fn exec_cycle(&mut self, port_map: &mut PortMap) -> RuntimeResult<()> { ports![&self.base_port; left: Self::LEFT, right: Self::RIGHT, @@ -425,7 +436,7 @@ impl Primitive for FxpMultPipe { self.done_is_high = false; } - let done_signal = port_map.insert_val_general( + port_map.insert_val_general( done, AssignedValue::cell_value(if self.done_is_high { BitVecValue::tru() @@ -433,11 +444,13 @@ impl Primitive for FxpMultPipe { BitVecValue::fals() }), )?; + port_map.write_exact_unchecked(out, self.current_output.clone()); - Ok( - port_map.write_exact_unchecked(out, self.current_output.clone()) - | done_signal, - ) + Ok(()) + } + + fn get_ports(&self) -> SplitIndexRange { + self.get_signature() } } @@ -453,7 +466,7 @@ pub struct FxpDivPipe { } impl FxpDivPipe { - declare_ports![_CLK: 0, RESET: 1, GO: 2, LEFT: 3, RIGHT: 4, OUT_REMAINDER: 5, OUT_QUOTIENT: 6, DONE: 7]; + declare_ports![_CLK: 0, RESET: 1, GO: 2, LEFT: 3, RIGHT: 4, | OUT_REMAINDER: 5, OUT_QUOTIENT: 6, DONE: 7]; pub fn new( base_port: GlobalPortIdx, int_width: u32, @@ -500,7 +513,7 @@ impl Primitive Ok(quot_changed | rem_changed | done_signal) } - fn exec_cycle(&mut self, port_map: &mut PortMap) -> UpdateResult { + fn exec_cycle(&mut self, port_map: &mut PortMap) -> RuntimeResult<()> { ports![&self.base_port; left: Self::LEFT, right: Self::RIGHT, @@ -570,12 +583,14 @@ impl Primitive self.done_is_high = false; } - let done_signal = port_map.set_done(done, self.done_is_high)?; - let quot_changed = port_map - .write_exact_unchecked(out_quot, self.output_quotient.clone()); - let rem_changed = port_map - .write_exact_unchecked(out_rem, self.output_remainder.clone()); + port_map.set_done(done, self.done_is_high)?; + port_map.write_exact_unchecked(out_quot, self.output_quotient.clone()); + port_map.write_exact_unchecked(out_rem, self.output_remainder.clone()); - Ok(quot_changed | rem_changed | done_signal) + Ok(()) + } + + fn get_ports(&self) -> SplitIndexRange { + self.get_signature() } } diff --git a/interp/src/flatten/primitives/stateful/memories.rs b/interp/src/flatten/primitives/stateful/memories.rs index 8365907f26..9ef3a1a51b 100644 --- a/interp/src/flatten/primitives/stateful/memories.rs +++ b/interp/src/flatten/primitives/stateful/memories.rs @@ -8,17 +8,17 @@ use crate::{ prelude::{AssignedValue, GlobalPortIdx, PortValue}, }, primitives::{ - declare_ports, make_getters, ports, + declare_ports, declare_ports_no_signature, make_getters, ports, prim_trait::{RaceDetectionPrimitive, UpdateResult, UpdateStatus}, utils::infer_thread_id, Primitive, }, structures::{ environment::{ - clock::{new_clock, ClockMap, ValueWithClock}, + clock::{new_clock_pair, ClockMap, ValueWithClock}, PortMap, }, - index_trait::IndexRef, + index_trait::{IndexRef, SplitIndexRange}, thread::{ThreadIdx, ThreadMap}, }, }, @@ -36,7 +36,7 @@ pub struct StdReg { } impl StdReg { - declare_ports![IN: 0, WRITE_EN: 1, _CLK: 2, RESET: 3, OUT: 4, DONE: 5]; + declare_ports![IN: 0, WRITE_EN: 1, _CLK: 2, RESET: 3, | OUT: 4, DONE: 5]; pub fn new( base_port: GlobalPortIdx, @@ -44,8 +44,10 @@ impl StdReg { width: u32, clocks: &mut Option<&mut ClockMap>, ) -> Self { - let internal_state = - ValueWithClock::zero(width, new_clock(clocks), new_clock(clocks)); + let internal_state = ValueWithClock::zero( + width, + new_clock_pair(clocks, global_idx, None), + ); Self { base_port, global_idx, @@ -60,7 +62,7 @@ impl Primitive for StdReg { Box::new(self.clone()) } - fn exec_cycle(&mut self, port_map: &mut PortMap) -> UpdateResult { + fn exec_cycle(&mut self, port_map: &mut PortMap) -> RuntimeResult<()> { ports![&self.base_port; input: Self::IN, write_en: Self::WRITE_EN, @@ -69,7 +71,7 @@ impl Primitive for StdReg { done: Self::DONE ]; - let done_port = if port_map[reset].as_bool().unwrap_or_default() { + if port_map[reset].as_bool().unwrap_or_default() { self.internal_state.value = BitVecValue::zero(self.internal_state.value.width()); port_map.insert_val_general( @@ -97,12 +99,12 @@ impl Primitive for StdReg { )? }; - Ok(done_port - | port_map.insert_val_general( - out_idx, - AssignedValue::cell_value(self.internal_state.value.clone()) - .with_clocks(self.internal_state.clocks), - )?) + port_map.insert_val_general( + out_idx, + AssignedValue::cell_value(self.internal_state.value.clone()) + .with_clocks(self.internal_state.clocks), + )?; + Ok(()) } fn exec_comb(&self, port_map: &mut PortMap) -> UpdateResult { @@ -141,6 +143,10 @@ impl Primitive for StdReg { fn dump_memory_state(&self) -> Option> { Some(self.internal_state.value.clone().to_bytes_le()) } + + fn get_ports(&self) -> SplitIndexRange { + self.get_signature() + } } impl RaceDetectionPrimitive for StdReg { @@ -157,7 +163,7 @@ impl RaceDetectionPrimitive for StdReg { port_map: &mut PortMap, clock_map: &mut ClockMap, thread_map: &ThreadMap, - ) -> UpdateResult { + ) -> RuntimeResult<()> { ports![&self.base_port; input: Self::IN, write_en: Self::WRITE_EN, @@ -178,7 +184,7 @@ impl RaceDetectionPrimitive for StdReg { self.internal_state .clocks .check_write(current_clock_idx, clock_map) - .map_err(|e| e.add_cell_info(self.global_idx))?; + .map_err(|e| e.add_cell_info(self.global_idx, None))?; } self.exec_cycle(port_map) @@ -200,7 +206,7 @@ impl MemDx { } } - declare_ports![ + declare_ports_no_signature![ SEQ_ADDR0: 2, COMB_ADDR0: 0, SEQ_ADDR1: 3, COMB_ADDR1: 1, SEQ_ADDR2: 4, COMB_ADDR2: 2, @@ -412,7 +418,7 @@ pub struct CombMem { global_idx: GlobalCellIdx, } impl CombMem { - declare_ports![ + declare_ports_no_signature![ WRITE_DATA:0, WRITE_EN: 1, _CLK: 2, @@ -442,11 +448,10 @@ impl CombMem { { let shape = size.into(); let mut internal_state = Vec::with_capacity(shape.size()); - for _ in 0..shape.size() { + for i in 0_usize..shape.size() { internal_state.push(ValueWithClock::zero( width, - new_clock(clocks), - new_clock(clocks), + new_clock_pair(clocks, global_idx, Some(i.try_into().unwrap())), )); } @@ -479,8 +484,16 @@ impl CombMem { let internal_state = data .chunks_exact(byte_count as usize) .map(|x| BitVecValue::from_bytes_le(x, width)) - .map(|x| { - ValueWithClock::new(x, new_clock(clocks), new_clock(clocks)) + .enumerate() + .map(|(i, x)| { + ValueWithClock::new( + x, + new_clock_pair( + clocks, + global_idx, + Some(i.try_into().unwrap()), + ), + ) }) .collect_vec(); @@ -561,7 +574,7 @@ impl Primitive for CombMem { Ok(done_signal | read) } - fn exec_cycle(&mut self, port_map: &mut PortMap) -> UpdateResult { + fn exec_cycle(&mut self, port_map: &mut PortMap) -> RuntimeResult<()> { // These two behave like false when undefined let reset = port_map[self.reset_port()].as_bool().unwrap_or_default(); let write_en = port_map[self.write_en()].as_bool().unwrap_or_default(); @@ -573,7 +586,7 @@ impl Primitive for CombMem { )?; let (read_data, done) = (self.read_data(), self.done()); - let done = if write_en && !reset { + if write_en && !reset { let addr = addr.ok_or(RuntimeError::UndefinedWriteAddr(self.global_idx))?; @@ -589,17 +602,17 @@ impl Primitive for CombMem { }; if let Some(addr) = addr { - Ok(port_map.insert_val_general( + port_map.insert_val_general( read_data, AssignedValue::cell_value( self.internal_state[addr].value.clone(), ) .with_clocks(self.internal_state[addr].clocks), - )? | done) + )?; } else { port_map.write_undef(read_data)?; - Ok(done) } + Ok(()) } fn serialize(&self, code: Option) -> Serializable { @@ -621,6 +634,14 @@ impl Primitive for CombMem { fn dump_memory_state(&self) -> Option> { Some(self.dump_data()) } + + fn get_ports(&self) -> SplitIndexRange { + SplitIndexRange::new( + self.base_port, + self.read_data(), + (self.done().index() + 1).into(), + ) + } } impl RaceDetectionPrimitive for CombMem { @@ -661,7 +682,7 @@ impl RaceDetectionPrimitive for CombMem { port_map: &mut PortMap, clock_map: &mut ClockMap, thread_map: &ThreadMap, - ) -> UpdateResult { + ) -> RuntimeResult<()> { let thread = self.infer_thread(port_map); if let Some(addr) = self.addresser.calculate_addr( port_map, @@ -677,7 +698,12 @@ impl RaceDetectionPrimitive for CombMem { if port_map[self.write_en()].as_bool().unwrap_or_default() { val.clocks .check_write(thread_clock, clock_map) - .map_err(|e| e.add_cell_info(self.global_idx))?; + .map_err(|e| { + e.add_cell_info( + self.global_idx, + Some(addr.try_into().unwrap()), + ) + })?; } } else if addr != 0 || port_map[self.write_en()].as_bool().unwrap_or_default() @@ -718,11 +744,10 @@ impl SeqMem { ) -> Self { let shape = size.into(); let mut internal_state = Vec::with_capacity(shape.size()); - for _ in 0..shape.size() { + for i in 0_usize..shape.size() { internal_state.push(ValueWithClock::zero( width, - new_clock(clocks), - new_clock(clocks), + new_clock_pair(clocks, global_idx, Some(i.try_into().unwrap())), )); } @@ -756,8 +781,16 @@ impl SeqMem { let internal_state = data .chunks_exact(byte_count as usize) .map(|x| BitVecValue::from_bytes_le(x, width)) - .map(|x| { - ValueWithClock::new(x, new_clock(clocks), new_clock(clocks)) + .enumerate() + .map(|(i, x)| { + ValueWithClock::new( + x, + new_clock_pair( + clocks, + global_idx, + Some(i.try_into().unwrap()), + ), + ) }) .collect_vec(); @@ -779,14 +812,14 @@ impl SeqMem { } } - declare_ports![ + declare_ports_no_signature![ _CLK: 0, RESET: 1, ]; // these port offsets are placed after the address ports and so need the end // of the address base to work correctly. - declare_ports![ + declare_ports_no_signature![ CONTENT_ENABLE: 0, WRITE_ENABLE: 1, WRITE_DATA: 2, @@ -860,7 +893,7 @@ impl Primitive for SeqMem { Ok(done_signal | out_signal) } - fn exec_cycle(&mut self, port_map: &mut PortMap) -> UpdateResult { + fn exec_cycle(&mut self, port_map: &mut PortMap) -> RuntimeResult<()> { let reset = port_map[self.reset()].as_bool().unwrap_or_default(); let write_en = port_map[self.write_enable()].as_bool().unwrap_or_default(); @@ -896,7 +929,7 @@ impl Primitive for SeqMem { self.done_is_high = false; } - let done_changed = port_map.insert_val_general( + port_map.insert_val_general( self.done(), AssignedValue::cell_value(if self.done_is_high { BitVecValue::tru() @@ -904,16 +937,15 @@ impl Primitive for SeqMem { BitVecValue::fals() }), )?; - Ok(done_changed - | port_map - .write_exact_unchecked(self.read_data(), self.read_out.clone())) + port_map.write_exact_unchecked(self.read_data(), self.read_out.clone()); + Ok(()) } - fn has_comb(&self) -> bool { + fn has_comb_path(&self) -> bool { false } - fn has_stateful(&self) -> bool { + fn has_stateful_path(&self) -> bool { true } @@ -936,6 +968,14 @@ impl Primitive for SeqMem { fn dump_memory_state(&self) -> Option> { Some(self.dump_data()) } + + fn get_ports(&self) -> SplitIndexRange { + SplitIndexRange::new( + self.base_port, + self.read_data(), + (self.done().index() + 1).into(), + ) + } } impl RaceDetectionPrimitive for SeqMem { @@ -961,7 +1001,7 @@ impl RaceDetectionPrimitive for SeqMem { port_map: &mut PortMap, clock_map: &mut ClockMap, thread_map: &ThreadMap, - ) -> UpdateResult { + ) -> RuntimeResult<()> { let thread = self.infer_thread(port_map); if let Some(addr) = self.addresser.calculate_addr( port_map, @@ -986,7 +1026,12 @@ impl RaceDetectionPrimitive for SeqMem { ), clock_map, ) - .map_err(|e| e.add_cell_info(self.global_idx))?; + .map_err(|e| { + e.add_cell_info( + self.global_idx, + Some(addr.try_into().unwrap()), + ) + })?; } else if port_map[self.content_enable()] .as_bool() .unwrap_or_default() @@ -1001,7 +1046,12 @@ impl RaceDetectionPrimitive for SeqMem { ), clock_map, ) - .map_err(|e| e.add_cell_info(self.global_idx))?; + .map_err(|e| { + e.add_cell_info( + self.global_idx, + Some(addr.try_into().unwrap()), + ) + })?; } } } diff --git a/interp/src/flatten/structures/environment/assignments.rs b/interp/src/flatten/structures/environment/assignments.rs index 1fdb672111..2306404b1e 100644 --- a/interp/src/flatten/structures/environment/assignments.rs +++ b/interp/src/flatten/structures/environment/assignments.rs @@ -1,6 +1,6 @@ use crate::flatten::{ flat_ir::prelude::{GlobalCellIdx, LocalPortOffset}, - structures::thread::ThreadIdx, + structures::thread::{ThreadIdx, ThreadMap}, }; use super::env::AssignmentRange; @@ -11,6 +11,43 @@ pub struct GroupInterfacePorts { pub done: LocalPortOffset, } +/// An enum describing the source of a set of assignments +#[derive(Debug, Clone, Copy)] +pub enum AssignType { + /// Assignments come from a comb group + Combinational, + /// Assignments are continuous + Continuous, + /// Assignments come from a group or invoke + Control, +} + +impl AssignType { + /// Returns `true` if the assign source is [`Combinational`]. + /// + /// [`Combinational`]: AssignType::Combinational + #[must_use] + pub fn is_combinational(&self) -> bool { + matches!(self, Self::Combinational) + } + + /// Returns `true` if the assign source is [`Continuous`]. + /// + /// [`Continuous`]: AssignType::Continuous + #[must_use] + pub fn is_continuous(&self) -> bool { + matches!(self, Self::Continuous) + } + + /// Returns `true` if the assign type is [`Control`]. + /// + /// [`Control`]: AssignType::Control + #[must_use] + pub fn is_control(&self) -> bool { + matches!(self, Self::Control) + } +} + /// A group of assignments that is scheduled to be evaluated #[derive(Debug)] pub struct ScheduledAssignments { @@ -18,23 +55,49 @@ pub struct ScheduledAssignments { pub assignments: AssignmentRange, pub interface_ports: Option, pub thread: Option, - pub is_cont: bool, + pub assign_type: AssignType, } impl ScheduledAssignments { - pub fn new( + pub fn new_control( active_cell: GlobalCellIdx, assignments: AssignmentRange, interface_ports: Option, thread: Option, - is_comb: bool, ) -> Self { Self { active_cell, assignments, interface_ports, thread, - is_cont: is_comb, + assign_type: AssignType::Control, + } + } + + pub fn new_combinational( + active_cell: GlobalCellIdx, + assignments: AssignmentRange, + ) -> Self { + Self { + active_cell, + assignments, + interface_ports: None, + thread: None, + assign_type: AssignType::Combinational, + } + } + + pub fn new_continuous( + active_cell: GlobalCellIdx, + assignments: AssignmentRange, + ) -> Self { + Self { + active_cell, + assignments, + interface_ports: None, + // all continuous assignments are executed under a single control thread + thread: Some(ThreadMap::continuous_thread()), + assign_type: AssignType::Continuous, } } } diff --git a/interp/src/flatten/structures/environment/clock.rs b/interp/src/flatten/structures/environment/clock.rs index 9d30eabc24..1ba27735da 100644 --- a/interp/src/flatten/structures/environment/clock.rs +++ b/interp/src/flatten/structures/environment/clock.rs @@ -3,18 +3,18 @@ use std::{ collections::HashMap, hash::Hash, num::NonZeroU32, + ops::{Index, IndexMut}, }; use crate::flatten::{ flat_ir::base::GlobalCellIdx, structures::{ - index_trait::{impl_index_nonzero, IndexRef}, - indexed_map::IndexedMap, + index_trait::impl_index_nonzero, indexed_map::IndexedMap, thread::ThreadIdx, }, }; -#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] pub struct ClockIdx(NonZeroU32); impl_index_nonzero!(ClockIdx); @@ -22,18 +22,74 @@ use baa::BitVecValue; use itertools::Itertools; use thiserror::Error; -pub type ClockMap = IndexedMap>; pub type ThreadClockPair = (ThreadIdx, ClockIdx); +#[derive(Debug, Clone)] +pub struct ClockPairInfo { + /// The cell that this clock pair was generated for + pub attached_cell: GlobalCellIdx, + /// An optional entry number within the given cell. This is used for + /// memories but not for registers + pub entry_number: Option, +} + +#[derive(Debug, Default, Clone)] +pub struct ClockMap { + clocks: IndexedMap>, + reverse_map: HashMap, +} + impl ClockMap { + pub fn new() -> Self { + Self::default() + } + /// pushes a new clock into the map and returns its index pub fn new_clock(&mut self) -> ClockIdx { - self.push(VectorClock::new()) + self.clocks.push(VectorClock::new()) + } + + pub fn new_clock_pair(&mut self) -> ClockPair { + let read = self.new_clock(); + let write = self.new_clock(); + ClockPair::new(read, write) + } + + pub fn insert_reverse_entry( + &mut self, + pair: ClockPair, + cell: GlobalCellIdx, + entry_number: Option, + ) { + self.reverse_map.insert( + pair, + ClockPairInfo { + attached_cell: cell, + entry_number, + }, + ); + } + + pub fn lookup_cell(&self, pair: ClockPair) -> Option<&ClockPairInfo> { + self.reverse_map.get(&pair) } /// Returns a new clock that is the clone of the given clock pub fn fork_clock(&mut self, parent: ClockIdx) -> ClockIdx { - self.push(self[parent].clone()) + self.clocks.push(self.clocks[parent].clone()) + } +} + +impl Index for ClockMap { + type Output = VectorClock; + fn index(&self, index: ClockIdx) -> &Self::Output { + &self.clocks[index] + } +} + +impl IndexMut for ClockMap { + fn index_mut(&mut self, index: ClockIdx) -> &mut Self::Output { + &mut self.clocks[index] } } @@ -86,11 +142,18 @@ impl Counter for u128 { /// If the clock map is provided, use it to create a new clock. Otherwise, /// return the 0th clock idx. -pub fn new_clock(clock_map: &mut Option<&mut ClockMap>) -> ClockIdx { - clock_map - .as_mut() - .map(|c| c.new_clock()) - .unwrap_or(ClockIdx::new(0)) +pub fn new_clock_pair( + clock_map: &mut Option<&mut ClockMap>, + cell: GlobalCellIdx, + entry_number: Option, +) -> ClockPair { + if let Some(map) = clock_map { + let pair = map.new_clock_pair(); + map.insert_reverse_entry(pair, cell, entry_number); + pair + } else { + ClockPair::zero() + } } /// A simple vector clock implementation. @@ -294,38 +357,40 @@ pub struct ValueWithClock { } impl ValueWithClock { - pub fn zero( - width: u32, - reading_clock: ClockIdx, - writing_clock: ClockIdx, - ) -> Self { + pub fn zero(width: u32, clocks: ClockPair) -> Self { Self { value: BitVecValue::zero(width), - clocks: ClockPair::new(reading_clock, writing_clock), + clocks, } } - pub fn new( - value: BitVecValue, - write_clock: ClockIdx, - read_clock: ClockIdx, - ) -> Self { + pub fn new(value: BitVecValue, clock_pair: ClockPair) -> Self { Self { value, - clocks: ClockPair::new(read_clock, write_clock), + clocks: clock_pair, } } } /// A struct containing the read and write clocks for a value. This is small /// enough to be copied around easily -#[derive(Debug, Clone, PartialEq, Copy)] +#[derive(Debug, Clone, PartialEq, Eq, Copy, Hash)] pub struct ClockPair { pub read_clock: ClockIdx, pub write_clock: ClockIdx, } impl ClockPair { + /// Returns a new clock pair where both indices point to the zero clock. + /// This should only be used as a placeholder entry for when clocks are not + /// actually being tracked. + pub fn zero() -> Self { + Self { + read_clock: ClockIdx::from(0), + write_clock: ClockIdx::from(0), + } + } + pub fn new(read_clock: ClockIdx, write_clock: ClockIdx) -> Self { Self { read_clock, @@ -356,6 +421,18 @@ impl ClockPair { } } + /// A wrapper method which checks the read and adds cell info on an error + pub fn check_read_w_cell( + &self, + (thread, reading_clock): ThreadClockPair, + clock_map: &mut ClockMap, + cell: GlobalCellIdx, + entry_number: Option, + ) -> Result<(), ClockError> { + self.check_read((thread, reading_clock), clock_map) + .map_err(|e| e.add_cell_info(cell, entry_number)) + } + pub fn check_write( &self, writing_clock: ClockIdx, @@ -371,6 +448,7 @@ impl ClockPair { .partial_cmp(&clock_map[self.read_clock]) .is_none() { + // dbg!(&clock_map[writing_clock], &clock_map[self.read_clock]); Err(ClockError::ReadWriteUnhelpful) } else if clock_map[writing_clock] .partial_cmp(&clock_map[self.write_clock]) @@ -394,16 +472,24 @@ pub enum ClockError { #[error("Concurrent writes to the same register/memory")] WriteWriteUnhelpful, #[error("Concurrent read & write to the same register/memory {0:?}")] - ReadWrite(GlobalCellIdx), + ReadWrite(GlobalCellIdx, Option), #[error("Concurrent writes to the same register/memory {0:?}")] - WriteWrite(GlobalCellIdx), + WriteWrite(GlobalCellIdx, Option), } impl ClockError { - pub fn add_cell_info(self, cell: GlobalCellIdx) -> Self { + pub fn add_cell_info( + self, + cell: GlobalCellIdx, + entry_number: Option, + ) -> Self { match self { - ClockError::ReadWriteUnhelpful => ClockError::ReadWrite(cell), - ClockError::WriteWriteUnhelpful => ClockError::WriteWrite(cell), + ClockError::ReadWriteUnhelpful => { + ClockError::ReadWrite(cell, entry_number) + } + ClockError::WriteWriteUnhelpful => { + ClockError::WriteWrite(cell, entry_number) + } _ => self, } } diff --git a/interp/src/flatten/structures/environment/env.rs b/interp/src/flatten/structures/environment/env.rs index 7b7360a57b..d8f3f13925 100644 --- a/interp/src/flatten/structures/environment/env.rs +++ b/interp/src/flatten/structures/environment/env.rs @@ -3,13 +3,17 @@ use super::{ context::Context, index_trait::IndexRange, indexed_map::IndexedMap, }, assignments::{GroupInterfacePorts, ScheduledAssignments}, - clock::{ClockMap, VectorClock}, - program_counter::{ControlTuple, PcMaps, ProgramCounter, WithEntry}, + clock::ClockMap, + program_counter::{ + ControlTuple, ParEntry, PcMaps, ProgramCounter, WithEntry, + }, traverser::{Path, TraversalError}, }; use crate::{ configuration::{LoggingConfig, RuntimeConfig}, - errors::{BoxedCiderError, CiderResult, ConflictingAssignments}, + errors::{ + BoxedCiderError, BoxedRuntimeError, CiderResult, ConflictingAssignments, + }, flatten::{ flat_ir::{ base::{ @@ -49,8 +53,8 @@ use itertools::Itertools; use owo_colors::OwoColorize; use slog::{info, warn, Logger}; -use std::fmt::Debug; use std::fmt::Write; +use std::{convert::Into, fmt::Debug}; pub type PortMap = IndexedMap; @@ -74,7 +78,11 @@ impl PortMap { val: PortValue, ) -> UpdateStatus { if self[target].is_undef() && val.is_undef() - || self[target].as_option() == val.as_option() + || self[target] + .as_option() + .zip(val.as_option()) + .map(|(a, b)| a.eq_no_transitive_clocks(b)) + .unwrap_or_default() { UpdateStatus::Unchanged } else { @@ -94,10 +102,12 @@ impl PortMap { &mut self, target: GlobalPortIdx, val: AssignedValue, - ) -> Result { + ) -> Result> { match self[target].as_option() { // unchanged - Some(t) if *t == val => Ok(UpdateStatus::Unchanged), + Some(t) if t.eq_no_transitive_clocks(&val) => { + Ok(UpdateStatus::Unchanged) + } // conflict // TODO: Fix to make the error more helpful Some(t) @@ -110,7 +120,8 @@ impl PortMap { target, a1: t.clone(), a2: val, - }) + } + .into()) } // changed Some(_) | None => { @@ -429,8 +440,9 @@ impl + Clone> Environment { let root = ctx.as_ref().entry_point; let aux = &ctx.as_ref().secondary[root]; - let mut clocks = IndexedMap::new(); - let root_clock = clocks.push(VectorClock::new()); + let mut clocks = ClockMap::new(); + let root_clock = clocks.new_clock(); + let continuous_clock = clocks.new_clock(); let mut env = Self { ports: PortMap::with_capacity(aux.port_offset_map.count()), @@ -443,7 +455,7 @@ impl + Clone> Environment { ), pc: ProgramCounter::new_empty(), clocks, - thread_map: ThreadMap::new(root_clock), + thread_map: ThreadMap::new(root_clock, continuous_clock), ctx, memory_header: None, pinned_ports: PinnedPorts::new(), @@ -462,6 +474,7 @@ impl + Clone> Environment { let root_thread = ThreadMap::root_thread(); env.clocks[root_clock].increment(&root_thread); + env.clocks[continuous_clock].increment(&ThreadMap::continuous_thread()); // Initialize program counter // TODO griffin: Maybe refactor into a separate function @@ -572,6 +585,24 @@ impl + Clone> Environment { self.control_ports.insert(done, 1); } + // ref cells and ports are initialized to None + for (ref_cell, def_idx) in comp_aux.ref_cell_offset_map.iter() { + let info = &self.ctx.as_ref().secondary[*def_idx]; + + for port_idx in info.ports.iter() { + let port_actual = self.ref_ports.push(None); + debug_assert_eq!( + &self.cells[comp].as_comp().unwrap().index_bases + port_idx, + port_actual + ); + } + let cell_actual = self.ref_cells.push(None); + debug_assert_eq!( + &self.cells[comp].as_comp().unwrap().index_bases + ref_cell, + cell_actual + ) + } + for (cell_off, def_idx) in comp_aux.cell_offset_map.iter() { let info = &self.ctx.as_ref().secondary[*def_idx]; if !info.prototype.is_component() { @@ -634,23 +665,6 @@ impl + Clone> Environment { } } } - - // ref cells and ports are initialized to None - for (ref_cell, def_idx) in comp_aux.ref_cell_offset_map.iter() { - let info = &self.ctx.as_ref().secondary[*def_idx]; - for port_idx in info.ports.iter() { - let port_actual = self.ref_ports.push(None); - debug_assert_eq!( - &self.cells[comp].as_comp().unwrap().index_bases + port_idx, - port_actual - ) - } - let cell_actual = self.ref_cells.push(None); - debug_assert_eq!( - &self.cells[comp].as_comp().unwrap().index_bases + ref_cell, - cell_actual - ) - } } pub fn get_comp_go(&self, comp: GlobalCellIdx) -> GlobalPortIdx { @@ -827,10 +841,17 @@ impl + Clone> Environment { let node = &ctx.primary[point.control_node_idx]; match node { ControlNode::Enable(x) => { + let go = &self.cells[point.comp].unwrap_comp().index_bases + + self.ctx().primary[x.group()].go; println!( - "{}::{}", + "{}::{}{}", self.get_full_name(point.comp), - ctx.lookup_name(x.group()).underline() + ctx.lookup_name(x.group()).underline(), + if self.ports[go].as_bool().unwrap_or_default() { + "" + } else { + " [done]" + } ); } ControlNode::Invoke(x) => { @@ -889,7 +910,7 @@ impl + Clone> Environment { /// Attempt to find the parent cell for a port. If no such cell exists (i.e. /// it is a hole port, then it returns None) - fn get_parent_cell_from_port( + fn _get_parent_cell_from_port( &self, port: PortRef, comp: GlobalCellIdx, @@ -1320,6 +1341,17 @@ impl + Clone> Environment { } } +enum ControlNodeEval { + Reprocess, + Stop { retain_node: bool }, +} + +impl ControlNodeEval { + fn stop(retain_node: bool) -> Self { + ControlNodeEval::Stop { retain_node } + } +} + /// The core functionality of a simulator. Clonable. #[derive(Clone)] pub struct BaseSimulator + Clone> { @@ -1633,7 +1665,7 @@ impl + Clone> BaseSimulator { ControlNode::Enable(e) => { let group = &self.ctx().primary[e.group()]; - Some(ScheduledAssignments::new( + Some(ScheduledAssignments::new_control( node.comp, group.assignments, Some(GroupInterfacePorts { @@ -1641,17 +1673,17 @@ impl + Clone> BaseSimulator { done: group.done, }), *thread, - false, )) } - ControlNode::Invoke(i) => Some(ScheduledAssignments::new( - node.comp, - i.assignments, - None, - *thread, - false, - )), + ControlNode::Invoke(i) => { + Some(ScheduledAssignments::new_control( + node.comp, + i.assignments, + None, + *thread, + )) + } ControlNode::Empty(_) => None, // non-leaf nodes @@ -1663,25 +1695,20 @@ impl + Clone> BaseSimulator { } }) .chain(self.env.pc.continuous_assigns().iter().map(|x| { - ScheduledAssignments::new(x.comp, x.assigns, None, None, true) + ScheduledAssignments::new_continuous(x.comp, x.assigns) })) .chain(self.env.pc.with_map().iter().map( |(ctrl_pt, with_entry)| { - let assigns = - self.ctx().primary[with_entry.group].assignments; - ScheduledAssignments::new( + ScheduledAssignments::new_combinational( ctrl_pt.comp, - assigns, - None, - with_entry.thread, - false, + self.ctx().primary[with_entry.group].assignments, ) }, )) .collect() } - /// A helper function which inserts indicies for the ref cells and ports + /// A helper function which inserts indices for the ref cells and ports /// used in the invoke statement fn initialize_ref_cells( &mut self, @@ -1851,7 +1878,7 @@ impl + Clone> BaseSimulator { { with_map.insert( node.clone(), - WithEntry::new(invoke.comb_group.unwrap(), thread), + WithEntry::new(invoke.comb_group.unwrap()), ); } @@ -1877,7 +1904,7 @@ impl + Clone> BaseSimulator { { with_map.insert( node.clone(), - WithEntry::new(i.cond_group().unwrap(), thread), + WithEntry::new(i.cond_group().unwrap()), ); } } @@ -1886,7 +1913,7 @@ impl + Clone> BaseSimulator { { with_map.insert( node.clone(), - WithEntry::new(w.cond_group().unwrap(), thread), + WithEntry::new(w.cond_group().unwrap()), ); } } @@ -1911,34 +1938,71 @@ impl + Clone> BaseSimulator { pub fn step(&mut self) -> CiderResult<()> { self.converge()?; - let out: Result<(), BoxedCiderError> = { - let mut result = Ok(()); - for cell in self.env.cells.values_mut() { - match cell { - CellLedger::Primitive { cell_dyn } => { - let res = cell_dyn.exec_cycle(&mut self.env.ports); - if res.is_err() { - result = Err(res.unwrap_err()); - break; + if self.conf.check_data_race { + let mut clock_map = std::mem::take(&mut self.env.clocks); + for cell in self.env.cells.values() { + if !matches!(&cell, CellLedger::Component(_)) { + let dyn_prim = match cell { + CellLedger::Primitive { cell_dyn } => &**cell_dyn, + CellLedger::RaceDetectionPrimitive { cell_dyn } => { + cell_dyn.as_primitive() } - } + CellLedger::Component(_) => { + unreachable!() + } + }; - CellLedger::RaceDetectionPrimitive { cell_dyn } => { - let res = cell_dyn.exec_cycle_checked( - &mut self.env.ports, - &mut self.env.clocks, - &self.env.thread_map, - ); - if res.is_err() { - result = Err(res.unwrap_err()); - break; + if !dyn_prim.is_combinational() { + let sig = dyn_prim.get_ports(); + for port in sig.iter_first() { + if let Some(val) = self.env.ports[port].as_option() + { + if val.propagate_clocks() + && (val.transitive_clocks().is_some()) + { + // For non-combinational cells with + // transitive reads, we will check them at + // the cycle boundary and attribute the read + // to the continuous thread + self.check_read( + ThreadMap::continuous_thread(), + port, + &mut clock_map, + ) + .map_err(|e| { + e.prettify_message(&self.env) + })? + } + } } } - CellLedger::Component(_) => {} } } - result.map_err(|e| e.prettify_message(&self.env).into()) - }; + + self.env.clocks = clock_map; + } + + let out: Result<(), BoxedRuntimeError> = self + .env + .cells + .values_mut() + .filter_map(|cell| match cell { + CellLedger::Primitive { cell_dyn } => { + Some(cell_dyn.exec_cycle(&mut self.env.ports)) + } + + CellLedger::RaceDetectionPrimitive { cell_dyn } => { + Some(cell_dyn.exec_cycle_checked( + &mut self.env.ports, + &mut self.env.clocks, + &self.env.thread_map, + )) + } + CellLedger::Component(_) => None, + }) + .collect(); + + out.map_err(|e| e.prettify_message(&self.env))?; self.env.pc.clear_finished_comps(); @@ -1948,7 +2012,10 @@ impl + Clone> BaseSimulator { let mut removed = vec![]; - for (i, node) in vecs.iter_mut().enumerate() { + let mut i = 0; + + while i < vecs.len() { + let node = &mut vecs[i]; let keep_node = self .evaluate_control_node( node, @@ -1956,8 +2023,16 @@ impl + Clone> BaseSimulator { (&mut par_map, &mut with_map, &mut repeat_map), ) .map_err(|e| e.prettify_message(&self.env))?; - if !keep_node { - removed.push(i); + match keep_node { + ControlNodeEval::Reprocess => { + continue; + } + ControlNodeEval::Stop { retain_node } => { + if !retain_node { + removed.push(i); + } + i += 1; + } } } @@ -1972,7 +2047,7 @@ impl + Clone> BaseSimulator { // insert all the new nodes from the par into the program counter self.env.pc.vec_mut().extend(new_nodes); - out + Ok(()) } fn evaluate_control_node( @@ -1980,7 +2055,7 @@ impl + Clone> BaseSimulator { node: &mut ControlTuple, new_nodes: &mut Vec, maps: PcMaps, - ) -> RuntimeResult { + ) -> RuntimeResult { let (node_thread, node) = node; let (par_map, with_map, repeat_map) = maps; let comp_go = self.env.get_comp_go(node.comp); @@ -1999,173 +2074,41 @@ impl + Clone> BaseSimulator { { // if the go port is low or the done port is high, we skip the // node without doing anything - return Ok(true); + return Ok(ControlNodeEval::stop(true)); } // just considering a single node case for the moment let retain_bool = match &ctx.primary[node.control_node_idx] { - ControlNode::Seq(seq) => { - if !seq.is_empty() { - let next = seq.stms()[0]; - *node = node.new_retain_comp(next); - true - } else { - node.mutate_into_next(self.env.ctx.as_ref()) - } - } - ControlNode::Par(par) => { - if par_map.contains_key(node) { - let count = par_map.get_mut(node).unwrap(); - *count -= 1; - - if *count == 0 { - par_map.remove(node); - if self.conf.check_data_race { - let thread = - thread.expect("par nodes should have a thread"); - - let child_clock_idx = - self.env.thread_map.unwrap_clock_id(thread); - let parent = - self.env.thread_map[thread].parent().unwrap(); - let parent_clock = - self.env.thread_map.unwrap_clock_id(parent); - let child_clock = std::mem::take( - &mut self.env.clocks[child_clock_idx], - ); - self.env.clocks[parent_clock].sync(&child_clock); - self.env.clocks[child_clock_idx] = child_clock; - assert!(self.env.thread_map[thread] - .parent() - .is_some()); - *node_thread = Some(parent); - self.env.clocks[parent_clock].increment(&parent); - } - node.mutate_into_next(self.env.ctx.as_ref()) - } else { - false - } - } else { - par_map.insert( - node.clone(), - par.stms().len().try_into().expect( - "More than (2^16 - 1 threads) in a par block. Are you sure this is a good idea?", - ), - ); - new_nodes.extend(par.stms().iter().map(|x| { - let thread = if self.conf.check_data_race { - let thread = - thread.expect("par nodes should have a thread"); - - let new_thread_idx: ThreadIdx = *(self - .env - .pc - .lookup_thread(node.comp, thread, *x) - .or_insert_with(|| { - let new_clock_idx = - self.env.clocks.new_clock(); - - self.env - .thread_map - .spawn(thread, new_clock_idx) - })); - - let new_clock_idx = self - .env - .thread_map - .unwrap_clock_id(new_thread_idx); - - self.env.clocks[new_clock_idx] = self.env.clocks - [self.env.thread_map.unwrap_clock_id(thread)] - .clone(); - - self.env.clocks[new_clock_idx] - .increment(&new_thread_idx); - - Some(new_thread_idx) - } else { - None - }; - - (thread, node.new_retain_comp(*x)) - })); - - if self.conf.check_data_race { - let thread = - thread.expect("par nodes should have a thread"); - let clock = self.env.thread_map.unwrap_clock_id(thread); - self.env.clocks[clock].increment(&thread); - } - - false - } - } + ControlNode::Seq(seq) => self.handle_seq(seq, node), + ControlNode::Par(par) => self.handle_par( + par_map, + node, + thread, + node_thread, + par, + new_nodes, + ), ControlNode::If(i) => self.handle_if(with_map, node, thread, i)?, ControlNode::While(w) => { self.handle_while(w, with_map, node, thread)? } ControlNode::Repeat(rep) => { - if let Some(count) = repeat_map.get_mut(node) { - *count -= 1; - if *count == 0 { - repeat_map.remove(node); - node.mutate_into_next(self.env.ctx.as_ref()) - } else { - *node = node.new_retain_comp(rep.body); - true - } - } else { - repeat_map.insert(node.clone(), rep.num_repeats); - *node = node.new_retain_comp(rep.body); - true - } + self.handle_repeat(repeat_map, node, rep) } // ===== leaf nodes ===== ControlNode::Empty(_) => { node.mutate_into_next(self.env.ctx.as_ref()) } - ControlNode::Enable(e) => { - let done_local = self.env.ctx.as_ref().primary[e.group()].done; - let done_idx = - &self.env.cells[node.comp].as_comp().unwrap().index_bases - + done_local; - if !self.env.ports[done_idx].as_bool().unwrap_or_default() { - true - } else { - // This group has finished running and may be removed - // this is somewhat dubious at the moment since it - // relies on the fact that the group done port will - // still be high since convergence hasn't propagated the - // low done signal yet. - node.mutate_into_next(self.env.ctx.as_ref()) - } - } - ControlNode::Invoke(i) => { - let done = self.get_global_port_idx(&i.done, node.comp); - - if i.comb_group.is_some() && !with_map.contains_key(node) { - with_map.insert( - node.clone(), - WithEntry::new(i.comb_group.unwrap(), thread), - ); - } - - if !self.env.ports[done].as_bool().unwrap_or_default() { - true - } else { - self.cleanup_ref_cells(node.comp, i); - - if i.comb_group.is_some() { - with_map.remove(node); - } - - node.mutate_into_next(self.env.ctx.as_ref()) - } - } + ControlNode::Enable(e) => self.handle_enable(e, node), + ControlNode::Invoke(i) => self.handle_invoke(i, node, with_map)?, }; + if retain_bool && node.should_reprocess(ctx) { + return Ok(ControlNodeEval::Reprocess); + } + if !retain_bool && ControlPoint::get_next(node, self.env.ctx.as_ref()).is_none() && // either we are not a par node, or we are the last par node (!matches!(&self.env.ctx.as_ref().primary[node.control_node_idx], ControlNode::Par(_)) || !par_map.contains_key(node)) @@ -2184,9 +2127,185 @@ impl + Clone> BaseSimulator { .control .unwrap(), ); - Ok(true) + Ok(ControlNodeEval::stop(true)) + } else { + Ok(ControlNodeEval::stop(retain_bool)) + } + } + + fn handle_seq(&mut self, seq: &Seq, node: &mut ControlPoint) -> bool { + if !seq.is_empty() { + let next = seq.stms()[0]; + *node = node.new_retain_comp(next); + true + } else { + node.mutate_into_next(self.env.ctx.as_ref()) + } + } + + fn handle_repeat( + &mut self, + repeat_map: &mut HashMap, + node: &mut ControlPoint, + rep: &Repeat, + ) -> bool { + if let Some(count) = repeat_map.get_mut(node) { + *count -= 1; + if *count == 0 { + repeat_map.remove(node); + node.mutate_into_next(self.env.ctx.as_ref()) + } else { + *node = node.new_retain_comp(rep.body); + true + } + } else { + repeat_map.insert(node.clone(), rep.num_repeats); + *node = node.new_retain_comp(rep.body); + true + } + } + + fn handle_enable(&mut self, e: &Enable, node: &mut ControlPoint) -> bool { + let done_local = self.env.ctx.as_ref().primary[e.group()].done; + let done_idx = + &self.env.cells[node.comp].as_comp().unwrap().index_bases + + done_local; + + if !self.env.ports[done_idx].as_bool().unwrap_or_default() { + true } else { - Ok(retain_bool) + // This group has finished running and may be removed + // this is somewhat dubious at the moment since it + // relies on the fact that the group done port will + // still be high since convergence hasn't propagated the + // low done signal yet. + node.mutate_into_next(self.env.ctx.as_ref()) + } + } + + fn handle_invoke( + &mut self, + i: &Invoke, + node: &mut ControlPoint, + with_map: &mut HashMap, + ) -> Result { + let done = self.get_global_port_idx(&i.done, node.comp); + if i.comb_group.is_some() && !with_map.contains_key(node) { + with_map + .insert(node.clone(), WithEntry::new(i.comb_group.unwrap())); + } + Ok(if !self.env.ports[done].as_bool().unwrap_or_default() { + true + } else { + self.cleanup_ref_cells(node.comp, i); + + if i.comb_group.is_some() { + with_map.remove(node); + } + + node.mutate_into_next(self.env.ctx.as_ref()) + }) + } + + fn handle_par( + &mut self, + par_map: &mut HashMap, + node: &mut ControlPoint, + thread: Option, + node_thread: &mut Option, + par: &Par, + new_nodes: &mut Vec<(Option, ControlPoint)>, + ) -> bool { + if par_map.contains_key(node) { + let par_entry = par_map.get_mut(node).unwrap(); + *par_entry.child_count_mut() -= 1; + + if self.conf.check_data_race { + par_entry.add_finished_thread( + thread.expect("par nodes should have a thread"), + ); + } + + if par_entry.child_count() == 0 { + let par_entry = par_map.remove(node).unwrap(); + if self.conf.check_data_race { + assert!(par_entry + .iter_finished_threads() + .map(|thread| { + self.env.thread_map[thread].parent().unwrap() + }) + .all_equal()); + let parent = + self.env.thread_map[thread.unwrap()].parent().unwrap(); + let parent_clock = + self.env.thread_map.unwrap_clock_id(parent); + + for child_thread in par_entry.iter_finished_threads() { + let child_clock_idx = + self.env.thread_map.unwrap_clock_id(child_thread); + + let child_clock = std::mem::take( + &mut self.env.clocks[child_clock_idx], + ); + + self.env.clocks[parent_clock].sync(&child_clock); + + self.env.clocks[child_clock_idx] = child_clock; + } + + *node_thread = Some(parent); + self.env.clocks[parent_clock].increment(&parent); + } + node.mutate_into_next(self.env.ctx.as_ref()) + } else { + false + } + } else { + par_map.insert( + node.clone(), + par.stms().len().try_into().expect( + "More than (2^16 - 1 threads) in a par block. Are you sure this is a good idea?", + ), + ); + new_nodes.extend(par.stms().iter().map(|x| { + let thread = if self.conf.check_data_race { + let thread = + thread.expect("par nodes should have a thread"); + + let new_thread_idx: ThreadIdx = *(self + .env + .pc + .lookup_thread(node.comp, thread, *x) + .or_insert_with(|| { + let new_clock_idx = self.env.clocks.new_clock(); + + self.env.thread_map.spawn(thread, new_clock_idx) + })); + + let new_clock_idx = + self.env.thread_map.unwrap_clock_id(new_thread_idx); + + self.env.clocks[new_clock_idx] = self.env.clocks + [self.env.thread_map.unwrap_clock_id(thread)] + .clone(); + + self.env.clocks[new_clock_idx].increment(&new_thread_idx); + + Some(new_thread_idx) + } else { + None + }; + + (thread, node.new_retain_comp(*x)) + })); + + if self.conf.check_data_race { + let thread = thread.expect("par nodes should have a thread"); + let clock = self.env.thread_map.unwrap_clock_id(thread); + self.env.clocks[clock].increment(&thread); + } + + false } } @@ -2207,27 +2326,20 @@ impl + Clone> BaseSimulator { GlobalPortRef::Ref(r) => self.env.ref_ports[r] .expect("While condition (ref) is undefined"), }; + if self.conf.check_data_race { - if let Some(clocks) = self.env.ports[idx].clocks() { - let read_clock = - self.env.thread_map.unwrap_clock_id(thread.unwrap()); - clocks - .check_read( - (thread.unwrap(), read_clock), - &mut self.env.clocks, - ) - .map_err(|e| { - e.add_cell_info( - self.env - .get_parent_cell_from_port( - w.cond_port(), - node.comp, - ) - .unwrap(), - ) - })?; - } + let mut clock_map = std::mem::take(&mut self.env.clocks); + + self.check_read_relative( + thread.unwrap(), + w.cond_port(), + node.comp, + &mut clock_map, + )?; + + self.env.clocks = clock_map; } + let result = self.env.ports[idx] .as_bool() .expect("While condition is undefined"); @@ -2271,25 +2383,11 @@ impl + Clone> BaseSimulator { }; if self.conf.check_data_race { - if let Some(clocks) = self.env.ports[idx].clocks() { - let read_clock = - self.env.thread_map.unwrap_clock_id(thread.unwrap()); - clocks - .check_read( - (thread.unwrap(), read_clock), - &mut self.env.clocks, - ) - .map_err(|e| { - e.add_cell_info( - self.env - .get_parent_cell_from_port( - i.cond_port(), - node.comp, - ) - .unwrap(), - ) - })?; - } + let mut clock_map = std::mem::take(&mut self.env.clocks); + + self.check_read(thread.unwrap(), idx, &mut clock_map)?; + + self.env.clocks = clock_map; } let result = self.env.ports[idx] @@ -2401,7 +2499,7 @@ impl + Clone> BaseSimulator { assignments, interface_ports, thread, - is_cont, + assign_type, } in assigns_bundle.iter() { let ledger = self.env.cells[*active_cell].as_comp().unwrap(); @@ -2429,7 +2527,7 @@ impl + Clone> BaseSimulator { .unwrap_or_else(|| { // if there is no go signal, then we want to run the // continuous assignments but not comb group assignments - if *is_cont { + if assign_type.is_continuous() { true } else { self.env.ports[comp_go] @@ -2453,55 +2551,14 @@ impl + Clone> BaseSimulator { let val = &self.env.ports[port]; if self.conf.debug_logging { - info!( - self.env.logger, - "Assignment fired in {}: {}\n wrote {}", - self.env.get_full_name(active_cell), - self.ctx() - .printer() - .print_assignment( - ledger.comp_id, - assign_idx - ) - .yellow(), - val.bold() + self.log_assignment( + active_cell, + ledger, + assign_idx, + val, ); } - if self.conf.check_data_race { - if let Some(clocks) = val.clocks() { - // skip checking clocks for continuous assignments - if !is_cont { - if let Some(thread) = thread { - let thread_clock = self - .env - .thread_map - .unwrap_clock_id(thread); - - clocks - .check_read( - (thread, thread_clock), - &mut self.env.clocks, - ) - .map_err(|e| { - // TODO griffin: find a less hacky way to - // do this - e.add_cell_info( - self.env - .get_parent_cell_from_port( - assign.src, - *active_cell, - ) - .unwrap(), - ) - })?; - } else { - panic!("cannot determine thread for non-continuous assignment that touches a checked port"); - } - } - } - } - let dest = self .get_global_port_idx(&assign.dst, *active_cell); @@ -2518,13 +2575,36 @@ impl + Clone> BaseSimulator { } if let Some(v) = val.as_option() { + let mut assigned_value = AssignedValue::new( + v.val().clone(), + (assign_idx, *active_cell), + ); + + // if this assignment is in a combinational + // context we want to propagate any clocks which + // are present. Since clocks aren't present + // when not running with `check_data_race`, this + // won't happen when the flag is not set + if (val.clocks().is_some() + || val.transitive_clocks().is_some()) + && (assign_type.is_combinational() + || assign_type.is_continuous()) + { + assigned_value = assigned_value + .with_transitive_clocks_opt( + val.transitive_clocks().cloned(), + ) + .with_propagate_clocks(); + // direct clock becomes a transitive clock + // on assignment + if let Some(c) = val.clocks() { + assigned_value.add_transitive_clock(c); + } + } + let result = self.env.ports.insert_val( dest, - AssignedValue::new( - v.val().clone(), - (assign_idx, *active_cell), - ) - .with_thread_optional(thread), + assigned_value.with_thread_optional(thread), ); let changed = match result { @@ -2566,79 +2646,15 @@ impl + Clone> BaseSimulator { todo!("Raise an error here since this assignment is undefining things: {}. Port currently has value: {}", self.env.ctx.as_ref().printer().print_assignment(ledger.comp_id, assign_idx), &self.env.ports[dest]) } } - - if self.conf.check_data_race { - if let Some(read_ports) = self - .env - .ctx - .as_ref() - .primary - .guard_read_map - .get(assign.guard) - { - for port in read_ports { - let port_idx = self.get_global_port_idx( - port, - *active_cell, - ); - if let Some(clocks) = - self.env.ports[port_idx].clocks() - { - let thread = thread - .expect("cannot determine thread"); - let thread_clock = self - .env - .thread_map - .unwrap_clock_id(thread); - clocks - .check_read( - (thread, thread_clock), - &mut self.env.clocks, - ) - .map_err(|e| { - // TODO griffin: find a less hacky way to - // do this - e.add_cell_info( - self.env - .get_parent_cell_from_port( - *port, - *active_cell, - ) - .unwrap(), - ) - })?; - } - } - } - } } } } - // Run all the primitives - let changed: bool = self - .env - .cells - .range() - .iter() - .filter_map(|x| match &mut self.env.cells[x] { - CellLedger::Primitive { cell_dyn } => { - Some(cell_dyn.exec_comb(&mut self.env.ports)) - } - CellLedger::RaceDetectionPrimitive { cell_dyn } => { - Some(cell_dyn.exec_comb_checked( - &mut self.env.ports, - &mut self.env.clocks, - &self.env.thread_map, - )) - } + if self.conf.check_data_race { + self.propagate_comb_reads(assigns_bundle)?; + } - CellLedger::Component(_) => None, - }) - .fold_ok(UpdateStatus::Unchanged, |has_changed, update| { - has_changed | update - })? - .as_bool(); + let changed = self.run_primitive_comb_path()?; has_changed |= changed; @@ -2666,70 +2682,394 @@ impl + Clone> BaseSimulator { } } + // check reads needs to happen before zeroing the go ports. If this is + // not observed then some read checks will be accidentally skipped + if self.conf.check_data_race { + self.handle_reads(assigns_bundle)?; + } + if self.conf.undef_guard_check { - let mut error_v = vec![]; - for bundle in assigns_bundle.iter() { - let ledger = - self.env.cells[bundle.active_cell].as_comp().unwrap(); - let go = bundle - .interface_ports - .as_ref() - .map(|x| &ledger.index_bases + x.go); - let done = bundle - .interface_ports - .as_ref() - .map(|x| &ledger.index_bases + x.done); + self.check_undefined_guards(assigns_bundle)?; + } + + // This should be the last update that occurs during convergence + self.zero_done_groups_go(assigns_bundle); - if !done - .and_then(|done| self.env.ports[done].as_bool()) + if self.conf.debug_logging { + info!(self.env.logger, "Finished combinational convergence"); + } + + Ok(()) + } + + /// For all groups in the given assignments, set the go port to zero if the + /// done port is high + fn zero_done_groups_go(&mut self, assigns_bundle: &[ScheduledAssignments]) { + for ScheduledAssignments { + active_cell, + interface_ports, + .. + } in assigns_bundle.iter() + { + if let Some(interface_ports) = interface_ports { + let ledger = self.env.cells[*active_cell].as_comp().unwrap(); + let go = &ledger.index_bases + interface_ports.go; + let done = &ledger.index_bases + interface_ports.done; + if self.env.ports[done].as_bool().unwrap_or_default() { + self.env.ports[go] = + PortValue::new_implicit(BitVecValue::zero(1)); + } + } + } + } + + /// A final pass meant to be run after convergence which does the following: + /// + /// 1. For successful assignments, check reads from the source port if applicable + /// 2. For non-continuous/combinational contexts, check all reads performed + /// by the guard regardless of whether the assignment fired or not + /// 3. For continuous/combinational contexts, update the transitive reads of + /// the value in the destination with the reads done by the guard, + /// regardless of success + fn handle_reads( + &mut self, + assigns_bundle: &[ScheduledAssignments], + ) -> Result<(), BoxedRuntimeError> { + // needed for mutability reasons + let mut clock_map = std::mem::take(&mut self.env.clocks); + + for ScheduledAssignments { + active_cell, + assignments, + interface_ports, + thread, + assign_type, + } in assigns_bundle.iter() + { + let ledger = self.env.cells[*active_cell].as_comp().unwrap(); + let go = + interface_ports.as_ref().map(|x| &ledger.index_bases + x.go); + + let comp_go = self.env.get_comp_go(*active_cell); + + let thread = self.compute_thread(comp_go, thread, go); + + // check for direct reads + if assign_type.is_control() + && go + .as_ref() + .map(|g| { + self.env.ports[*g].as_bool().unwrap_or_default() + && self.env.ports[comp_go] + .as_bool() + .unwrap_or_default() + }) .unwrap_or_default() - && go - .and_then(|go| self.env.ports[go].as_bool()) - .unwrap_or(true) - { - for assign in bundle.assignments.iter() { - let guard_idx = self.ctx().primary[assign].guard; - if self - .evaluate_guard(guard_idx, bundle.active_cell) - .is_none() - { - let inner_v = self - .ctx() - .primary - .guard_read_map - .get(guard_idx) + { + for assign_idx in assignments.iter() { + let assign = &self.env.ctx.as_ref().primary[assign_idx]; + + // read source + if self + .evaluate_guard(assign.guard, *active_cell) + .unwrap_or_default() + { + self.check_read_relative( + thread.unwrap(), + assign.src, + *active_cell, + &mut clock_map, + )?; + } + + // guard reads, assignment firing does not matter + if let Some(read_ports) = self + .env + .ctx + .as_ref() + .primary + .guard_read_map + .get(assign.guard) + { + for port in read_ports { + self.check_read_relative( + thread.unwrap(), + *port, + *active_cell, + &mut clock_map, + )?; + } + } + } + } + } + self.env.clocks = clock_map; + + Ok(()) + } + + /// For continuous/combinational contexts, update the transitive reads of + /// the value in the destination with the reads done by the guard, + /// regardless of success + fn propagate_comb_reads( + &mut self, + assigns_bundle: &[ScheduledAssignments], + ) -> Result<(), BoxedRuntimeError> { + for ScheduledAssignments { + active_cell, + assignments, + assign_type, + .. + } in assigns_bundle.iter() + { + let comp_go = self.env.get_comp_go(*active_cell); + + if (assign_type.is_combinational() + && self.env.ports[comp_go].as_bool().unwrap_or_default()) + || assign_type.is_continuous() + { + for assign_idx in assignments.iter() { + let assign = &self.env.ctx.as_ref().primary[assign_idx]; + let dest = + self.get_global_port_idx(&assign.dst, *active_cell); + + if let Some(read_ports) = self + .env + .ctx + .as_ref() + .primary + .guard_read_map + .get(assign.guard) + { + if self.env.ports[dest].is_def() { + let mut set_extension = HashSet::new(); + + for port in read_ports { + let port = self + .get_global_port_idx(port, *active_cell); + if let Some(clock) = + self.env.ports[port].clocks() + { + set_extension.insert(clock); + } + if let Some(clocks) = + self.env.ports[port].transitive_clocks() + { + set_extension + .extend(clocks.iter().copied()); + } + } + + self.env.ports[dest] + .as_option_mut() .unwrap() - .iter() - .filter_map(|p| { - let p = self.get_global_port_idx( - p, - bundle.active_cell, - ); - if self.env.ports[p].is_undef() { - Some(p) - } else { - None - } - }) - .collect_vec(); + .add_transitive_clocks(set_extension); - error_v.push((bundle.active_cell, assign, inner_v)) + // this is necessary for ports which were implicitly + // assigned zero and is redundant for other ports + // which will already have propagate_clocks set + self.env.ports[dest] + .as_option_mut() + .unwrap() + .set_propagate_clocks(true); } } } } - if !error_v.is_empty() { - return Err(RuntimeError::UndefinedGuardError(error_v).into()); + } + + Ok(()) + } + + /// Check for undefined guards and raise an error if any are found + fn check_undefined_guards( + &mut self, + assigns_bundle: &[ScheduledAssignments], + ) -> Result<(), BoxedRuntimeError> { + let mut error_v = vec![]; + for bundle in assigns_bundle.iter() { + let ledger = self.env.cells[bundle.active_cell].as_comp().unwrap(); + let go = bundle + .interface_ports + .as_ref() + .map(|x| &ledger.index_bases + x.go); + let done = bundle + .interface_ports + .as_ref() + .map(|x| &ledger.index_bases + x.done); + + if !done + .and_then(|done| self.env.ports[done].as_bool()) + .unwrap_or_default() + && go + .and_then(|go| self.env.ports[go].as_bool()) + .unwrap_or(true) + { + for assign in bundle.assignments.iter() { + let guard_idx = self.ctx().primary[assign].guard; + if self + .evaluate_guard(guard_idx, bundle.active_cell) + .is_none() + { + let inner_v = self + .ctx() + .primary + .guard_read_map + .get(guard_idx) + .unwrap() + .iter() + .filter_map(|p| { + let p = self + .get_global_port_idx(p, bundle.active_cell); + if self.env.ports[p].is_undef() { + Some(p) + } else { + None + } + }) + .collect_vec(); + + error_v.push((bundle.active_cell, assign, inner_v)) + } + } } } + if !error_v.is_empty() { + Err(RuntimeError::UndefinedGuardError(error_v).into()) + } else { + Ok(()) + } + } - if self.conf.debug_logging { - info!(self.env.logger, "Finished combinational convergence"); + fn run_primitive_comb_path(&mut self) -> Result { + let changed: bool = self + .env + .cells + .values_mut() + .filter_map(|x| match x { + CellLedger::Primitive { cell_dyn } => { + let result = cell_dyn.exec_comb(&mut self.env.ports); + + if result.is_ok() + && self.conf.check_data_race + && cell_dyn.is_combinational() + { + let mut working_set = vec![]; + let signature = cell_dyn.get_ports(); + + for port in signature.iter_first() { + let val = &self.env.ports[port]; + if let Some(val) = val.as_option() { + if val.propagate_clocks() + && (val.clocks().is_some() + || val.transitive_clocks().is_some()) + { + if let Some(clocks) = val.clocks() { + working_set.push(*clocks); + } + working_set + .extend(val.iter_transitive_clocks()); + } + } + } + + if signature.iter_second().len() == 1 { + let port = signature.iter_second().next().unwrap(); + let val = &mut self.env.ports[port]; + if let Some(val) = val.as_option_mut() { + val.add_transitive_clocks(working_set); + } + } else { + todo!("comb primitive with multiple outputs") + } + } + Some(result) + } + CellLedger::RaceDetectionPrimitive { cell_dyn } => { + Some(cell_dyn.exec_comb_checked( + &mut self.env.ports, + &mut self.env.clocks, + &self.env.thread_map, + )) + } + + CellLedger::Component(_) => None, + }) + .fold_ok(UpdateStatus::Unchanged, |has_changed, update| { + has_changed | update + })? + .as_bool(); + Ok(changed) + } + + /// A wrapper function for [check_read] which takes in a [PortRef] and the + /// active component cell and calls [check_read] with the appropriate [GlobalPortIdx] + fn check_read_relative( + &self, + thread: ThreadIdx, + port: PortRef, + active_cell: GlobalCellIdx, + clock_map: &mut ClockMap, + ) -> Result<(), BoxedRuntimeError> { + let global_port = self.get_global_port_idx(&port, active_cell); + self.check_read(thread, global_port, clock_map) + } + + fn check_read( + &self, + thread: ThreadIdx, + global_port: GlobalPortIdx, + clock_map: &mut ClockMap, + ) -> Result<(), BoxedRuntimeError> { + let val = &self.env.ports[global_port]; + let thread_clock = self.env.thread_map.unwrap_clock_id(thread); + + if val.clocks().is_some() && val.transitive_clocks().is_some() { + // TODO griffin: Sort this out + panic!("Value has both direct clock and transitive clock. This shouldn't happen?") + } else if let Some(clocks) = val.clocks() { + let info = clock_map.lookup_cell(clocks).expect("Clock pair without cell. This should never happen, please report this bug"); + clocks.check_read_w_cell( + (thread, thread_clock), + clock_map, + info.attached_cell, + info.entry_number, + )? + } else if let Some(transitive_clocks) = val.transitive_clocks() { + for clock_pair in transitive_clocks { + let info = clock_map.lookup_cell(*clock_pair).expect("Clock pair without cell. This should never happen, please report this bug"); + + clock_pair.check_read_w_cell( + (thread, thread_clock), + clock_map, + info.attached_cell, + info.entry_number, + )? + } } Ok(()) } + fn log_assignment( + &self, + active_cell: &GlobalCellIdx, + ledger: &ComponentLedger, + assign_idx: AssignmentIdx, + val: &PortValue, + ) { + info!( + self.env.logger, + "Assignment fired in {}: {}\n wrote {}", + self.env.get_full_name(active_cell), + self.ctx() + .printer() + .print_assignment(ledger.comp_id, assign_idx) + .yellow(), + val.bold() + ); + } + /// Attempts to compute the thread id for the given group/component. /// /// If the given thread is `None`, then the thread id is computed from the diff --git a/interp/src/flatten/structures/environment/program_counter.rs b/interp/src/flatten/structures/environment/program_counter.rs index 918303141e..698a4a0dab 100644 --- a/interp/src/flatten/structures/environment/program_counter.rs +++ b/interp/src/flatten/structures/environment/program_counter.rs @@ -1,6 +1,7 @@ use std::{collections::hash_map::Entry, num::NonZeroU32}; use ahash::{HashMap, HashMapExt}; +use smallvec::SmallVec; use super::super::context::Context; use crate::flatten::{ @@ -60,6 +61,19 @@ impl ControlPoint { } } + pub(super) fn should_reprocess(&self, ctx: &Context) -> bool { + match &ctx.primary.control[self.control_node_idx] { + ControlNode::Repeat(_) + | ControlNode::Empty(_) + | ControlNode::Seq(_) + | ControlNode::Par(_) => true, + ControlNode::Enable(_) + | ControlNode::If(_) + | ControlNode::While(_) + | ControlNode::Invoke(_) => false, + } + } + /// Returns a string showing the path from the root node to input node. This /// path is displayed in the minimal metadata path syntax. pub fn string_path(&self, ctx: &Context) -> String { @@ -417,14 +431,12 @@ pub struct WithEntry { pub group: CombGroupIdx, /// Whether or not a body has been executed. Only used by if statements pub entered: bool, - pub thread: Option, } impl WithEntry { - pub fn new(group: CombGroupIdx, thread: Option) -> Self { + pub fn new(group: CombGroupIdx) -> Self { Self { group, - thread, entered: false, } } @@ -434,12 +446,48 @@ impl WithEntry { } } +#[derive(Debug, Clone)] +pub struct ParEntry { + child_count: ChildCount, + finished_threads: SmallVec<[ThreadIdx; 4]>, +} + +impl ParEntry { + pub fn child_count_mut(&mut self) -> &mut ChildCount { + &mut self.child_count + } + + pub fn child_count(&self) -> u16 { + self.child_count + } + pub fn add_finished_thread(&mut self, thread: ThreadIdx) { + self.finished_threads.push(thread); + } + + pub fn iter_finished_threads( + &self, + ) -> impl Iterator + '_ { + self.finished_threads.iter().copied() + } +} + +impl TryFrom for ParEntry { + type Error = std::num::TryFromIntError; + + fn try_from(value: usize) -> Result { + Ok(ParEntry { + child_count: value.try_into()?, + finished_threads: SmallVec::new(), + }) + } +} + /// The program counter for the whole program execution. Wraps over a vector of /// the active leaf statements for each component instance. #[derive(Debug, Default, Clone)] pub(crate) struct ProgramCounter { vec: Vec, - par_map: HashMap, + par_map: HashMap, continuous_assigns: Vec, with_map: HashMap, repeat_map: HashMap, @@ -452,13 +500,13 @@ pub type ControlTuple = (Option, ControlPoint); pub type PcFields = ( Vec, - HashMap, + HashMap, HashMap, HashMap, ); pub type PcMaps<'a> = ( - &'a mut HashMap, + &'a mut HashMap, &'a mut HashMap, &'a mut HashMap, ); @@ -488,11 +536,11 @@ impl ProgramCounter { &mut self.vec } - pub fn _par_map_mut(&mut self) -> &mut HashMap { + pub fn _par_map_mut(&mut self) -> &mut HashMap { &mut self.par_map } - pub fn _par_map(&self) -> &HashMap { + pub fn _par_map(&self) -> &HashMap { &self.par_map } diff --git a/interp/src/flatten/structures/index_trait.rs b/interp/src/flatten/structures/index_trait.rs index 09f2588538..816f4c9dc0 100644 --- a/interp/src/flatten/structures/index_trait.rs +++ b/interp/src/flatten/structures/index_trait.rs @@ -164,6 +164,46 @@ where } } +/// A continuous range of indices that is split into two parts. +/// +/// Represents the ranges +/// `[start, split)` and `[split, end)` +#[derive(Debug, Clone)] +pub struct SplitIndexRange { + start: I, + split: I, + end: I, +} + +impl SplitIndexRange { + /// Create a new split index range. + /// + /// The `start` must be less than or equal to + /// the `split`, and the `split` must be less than or equal to the `end`. It will + /// panic if these conditions are not met. + pub fn new(start: I, split: I, end: I) -> Self { + assert!(start <= split); + assert!(split <= end); + + Self { start, split, end } + } + + /// Returns an iterator over the first segment of the range, i.e `[start, split)`. + pub fn iter_first(&self) -> OwnedIndexRangeIterator { + OwnedIndexRangeIterator::new(IndexRange::new(self.start, self.split)) + } + + /// Returns an iterator over the second segment of the range, i.e `[split, end)`. + pub fn iter_second(&self) -> OwnedIndexRangeIterator { + OwnedIndexRangeIterator::new(IndexRange::new(self.split, self.end)) + } + + /// Returns an iterator over the entire range. + pub fn iter_all(&self) -> OwnedIndexRangeIterator { + OwnedIndexRangeIterator::new(IndexRange::new(self.start, self.end)) + } +} + impl IntoIterator for IndexRange where I: IndexRef + PartialOrd, @@ -199,7 +239,7 @@ where current: I, } -impl<'a, I> ExactSizeIterator for IndexRangeIterator<'a, I> where +impl ExactSizeIterator for IndexRangeIterator<'_, I> where I: IndexRef + PartialOrd { } @@ -216,7 +256,7 @@ where } } -impl<'a, I> Iterator for IndexRangeIterator<'a, I> +impl Iterator for IndexRangeIterator<'_, I> where I: IndexRef + PartialOrd, { @@ -242,10 +282,10 @@ where (size, Some(size)) } } -/// An iterator over a range of indices but without +/// An iterator over a range of indices that owns the range, rather than borrowing it. /// /// Because I really played myself by making the [IndexRangeIterator] have a -/// lifetime attached to it. This one doesn't do that. As with it's sibling, the +/// lifetime attached to it. This one doesn't do that. As with its sibling, the /// range is half open, meaning that the start is inclusive, but the end is /// exclusive. pub struct OwnedIndexRangeIterator @@ -253,7 +293,6 @@ where I: IndexRef + PartialOrd, { range: IndexRange, - current: I, } impl OwnedIndexRangeIterator @@ -261,10 +300,7 @@ where I: IndexRef + PartialOrd, { pub fn new(range: IndexRange) -> Self { - Self { - range, - current: range.start, - } + Self { range } } } @@ -275,18 +311,18 @@ where type Item = I; fn next(&mut self) -> Option { - if self.current < self.range.end { - let current = self.current; - self.current = I::new(self.current.index() + 1); - Some(current) + if self.range.start < self.range.end { + let out = self.range.start; + self.range.start = I::new(self.range.start.index() + 1); + Some(out) } else { None } } fn size_hint(&self) -> (usize, Option) { - let size = if self.range.end.index() > self.current.index() { - self.range.end.index() - self.current.index() + let size = if self.range.end > self.range.start { + self.range.end.index() - self.range.start.index() } else { 0 }; diff --git a/interp/src/flatten/structures/indexed_map.rs b/interp/src/flatten/structures/indexed_map.rs index e3f24c3150..58b1e7a135 100644 --- a/interp/src/flatten/structures/indexed_map.rs +++ b/interp/src/flatten/structures/indexed_map.rs @@ -121,6 +121,10 @@ where self.data.iter_mut() } + pub fn values(&self) -> impl Iterator { + self.data.iter() + } + pub fn keys(&self) -> impl Iterator + '_ { // TODO (griffin): Make this an actual struct instead self.data.iter().enumerate().map(|(i, _)| K::new(i)) @@ -153,15 +157,12 @@ where data: &'data IndexedMap, } -impl<'range, 'data, K, D> ExactSizeIterator - for IndexedMapRangeIterator<'range, 'data, K, D> -where - K: IndexRef + PartialOrd, +impl ExactSizeIterator for IndexedMapRangeIterator<'_, '_, K, D> where + K: IndexRef + PartialOrd { } -impl<'range, 'data, K, D> Iterator - for IndexedMapRangeIterator<'range, 'data, K, D> +impl<'data, K, D> Iterator for IndexedMapRangeIterator<'_, 'data, K, D> where K: IndexRef + PartialOrd, { diff --git a/interp/src/flatten/structures/thread.rs b/interp/src/flatten/structures/thread.rs index 8ca8a5bc9e..85a70fb5fe 100644 --- a/interp/src/flatten/structures/thread.rs +++ b/interp/src/flatten/structures/thread.rs @@ -31,18 +31,27 @@ pub struct ThreadMap { } impl ThreadMap { - pub fn new(root_clock: ClockIdx) -> Self { + pub fn new(root_clock: ClockIdx, continuous_clock: ClockIdx) -> Self { let mut map = IndexedMap::new(); map.push(ThreadInfo { parent: None, clock_id: root_clock, }); + map.push(ThreadInfo { + parent: None, + clock_id: continuous_clock, + }); Self { map } } pub fn root_thread() -> ThreadIdx { ThreadIdx::from(0) } + + pub fn continuous_thread() -> ThreadIdx { + ThreadIdx::from(1) + } + /// Lookup the clock associated with the given thread id. Returns `None` if /// the thread id is invalid. pub fn get_clock_id(&self, thread_id: &ThreadIdx) -> Option { diff --git a/interp/tests/data-race/conflict.expect b/interp/tests/data-race/conflict.expect new file mode 100644 index 0000000000..fdf4dca079 --- /dev/null +++ b/interp/tests/data-race/conflict.expect @@ -0,0 +1,4 @@ +---CODE--- +1 +---STDERR--- +Error: Concurrent read & write to the same register main.count diff --git a/interp/tests/data-race/conflict.futil b/interp/tests/data-race/conflict.futil new file mode 100644 index 0000000000..335ac9bc35 --- /dev/null +++ b/interp/tests/data-race/conflict.futil @@ -0,0 +1,66 @@ +import "primitives/core.futil"; +import "primitives/memories/comb.futil"; +import "primitives/binary_operators.futil"; + +component main() -> (out: 32) { + cells { + pow = std_reg(32); + count = std_reg(4); + mul = std_mult_pipe(32); + lt = std_lt(4); + incr = std_add(4); + const0 = std_const(4, 3); + base = std_reg(32); + exp = std_reg(4); + my_wire = std_wire(1); + useless_wire = std_wire(1); + } + wires { + group init<"static"=1> { + pow.in = 32'd1; + pow.write_en = 1'd1; + count.in = 4'd0; + count.write_en = 1'd1; + + base.in = 32'd10; + base.write_en = 1'd1; + + exp.in = 4'd3; + exp.write_en = 1'd1; + + + init[done] = pow.done & count.done ? 1'd1; + } + group do_mul { + mul.left = base.out; + mul.right = pow.out; + mul.go = !mul.done ? 1'd1; + pow.in = mul.out; + pow.write_en = mul.done; + useless_wire.in = my_wire.out; + do_mul[done] = pow.done; + } + group incr_count<"static"=1> { + incr.left = 4'd1; + incr.right = count.out; + count.in = incr.out; + count.write_en = 1'd1; + incr_count[done] = count.done; + } + comb group cond { + lt.right = exp.out; + lt.left = count.out; + my_wire.in = !lt.out & 1'd0 ? 1'd1; + } + + out = pow.out; + } + control { + seq { + init; + while lt.out with cond { + par { do_mul; incr_count; } + } + } + } +} diff --git a/interp/tests/data-race/continuous-race.expect b/interp/tests/data-race/continuous-race.expect new file mode 100644 index 0000000000..d6eeceb5f8 --- /dev/null +++ b/interp/tests/data-race/continuous-race.expect @@ -0,0 +1,4 @@ +---CODE--- +1 +---STDERR--- +Error: Concurrent read & write to the same register main.val diff --git a/interp/tests/data-race/continuous-race.futil b/interp/tests/data-race/continuous-race.futil new file mode 100644 index 0000000000..03fcc56bf4 --- /dev/null +++ b/interp/tests/data-race/continuous-race.futil @@ -0,0 +1,28 @@ +import "primitives/core.futil"; +import "primitives/memories/comb.futil"; + +component main() -> () { + cells { + @external mem = comb_mem_d1(32, 20, 32); + val = std_reg(32); + add = std_add(32); + } + wires { + add.right = 32'b1; + add.left = val.out; + val.write_en = 1'b1; + val.in = add.out; + + group store { + mem.addr0 = val.out; + mem.write_data = val.out; + mem.write_en = 1'b1; + store[done] = mem.done; + } + } + control { + repeat 19 { + store; + } + } +} diff --git a/interp/tests/data-race/guard-conflict.expect b/interp/tests/data-race/guard-conflict.expect index d3f49ee6dd..cc56d3b526 100644 --- a/interp/tests/data-race/guard-conflict.expect +++ b/interp/tests/data-race/guard-conflict.expect @@ -1,4 +1,4 @@ ---CODE--- 1 ---STDERR--- -Error: Concurrent read & write to the same register/memory main.cond_reg +Error: Concurrent read & write to the same register main.cond_reg diff --git a/interp/tests/data-race/par-conflict-cmem.expect b/interp/tests/data-race/par-conflict-cmem.expect index 59aad0e0bd..ed1403c818 100644 --- a/interp/tests/data-race/par-conflict-cmem.expect +++ b/interp/tests/data-race/par-conflict-cmem.expect @@ -1,4 +1,4 @@ ---CODE--- 1 ---STDERR--- -Error: Concurrent read & write to the same register/memory main.cond_mem +Error: Concurrent read & write to the same memory main.cond_mem in slot 0 diff --git a/interp/tests/data-race/par-conflict.expect b/interp/tests/data-race/par-conflict.expect index d3f49ee6dd..cc56d3b526 100644 --- a/interp/tests/data-race/par-conflict.expect +++ b/interp/tests/data-race/par-conflict.expect @@ -1,4 +1,4 @@ ---CODE--- 1 ---STDERR--- -Error: Concurrent read & write to the same register/memory main.cond_reg +Error: Concurrent read & write to the same register main.cond_reg diff --git a/interp/tests/data-race/strange_mult.expect b/interp/tests/data-race/strange_mult.expect new file mode 100644 index 0000000000..f96745bfa8 --- /dev/null +++ b/interp/tests/data-race/strange_mult.expect @@ -0,0 +1,4 @@ +---CODE--- +1 +---STDERR--- +Error: Concurrent read & write to the same register main.first_reg diff --git a/interp/tests/data-race/strange_mult.futil b/interp/tests/data-race/strange_mult.futil new file mode 100644 index 0000000000..8d3c43f4dd --- /dev/null +++ b/interp/tests/data-race/strange_mult.futil @@ -0,0 +1,50 @@ +import "primitives/core.futil"; +import "primitives/memories/comb.futil"; +import "primitives/binary_operators.futil"; + +component main() -> (out: 32) { + cells { + first_reg = std_reg(32); + mult = std_mult_pipe(32); + second_reg = std_reg(32); + adder = std_add(32); + adder2 = std_add(32); + } + wires { + group init { + first_reg.in = 32'd10; + first_reg.write_en = 1'd1; + second_reg.in = 32'd20; + second_reg.write_en = 1'd1; + init[done] = first_reg.done; + } + + group incr_first_reg { + adder.left = first_reg.out; + adder.right = 32'd1; + first_reg.in = adder.out; + first_reg.write_en = 1'd1; + incr_first_reg[done] = first_reg.done; + } + + group incr_second_reg { + adder2.left = second_reg.out; + adder2.right = 32'd1; + second_reg.in = adder2.out; + second_reg.write_en = 1'd1; + incr_second_reg[done] = second_reg.done; + } + + mult.left = first_reg.out; + mult.right = second_reg.out; + } + control { + seq { + init; + par { + incr_first_reg; + incr_second_reg; + } + } + } +} From d9df2643c6d4685929a4b4681dbe18a05a070e20 Mon Sep 17 00:00:00 2001 From: Ayaka Yorihiro <36107281+ayakayorihiro@users.noreply.github.com> Date: Mon, 9 Dec 2024 08:30:35 -0800 Subject: [PATCH 08/12] [Profiler] Profiling support for parallel programs (#2370) This PR contains: - The `profiler-instrumentation` pass is now updated to contain four types of probes in order to capture call site information. - `group_probe`: A probe that is high when a group is active. - `primitive_probe`: A probe that is high when a primitive cell is active. - `se_probe`: A probe that is high when a group that structurally enables another group is active. - `cell_probe`: A probe that is high when a group that invokes a non-primitive cell is active. - `profiler-process.py`: an updated VCD postprocessing script that generates `.folded` and `.dot` files: - A "flattened" flame graph, where each parallel arm gets its own "cycle". So, if arm A and arm B were executing on a single cycle, the flame graph would account for a cycle in arm A and a cycle in arm B. - A scaled flame graph, where a cycle is divided between the parallel arms in execution. So, if arm A and arm B were executing on a single cycle, the flame graph would account for 0.5 cycles in arm A and 0.5 cycles in arm B. - `aggregate.dot`: A tree summary of the execution of the program. Nodes (groups and cells) are labeled with the number of times the node was a leaf, and edges are labeled with the number of cycles that edge was activated. - `rank{i}.dot`: A tree representation of the `i`th most active stack picture. `rankings.csv` lists the specific cycles that each ranked tree was active for. - Updated fud2 support (`fud2/scripts/profiler.rhai`) - Utility scripts to help convert generated `.folded` and `.dot` files into visualizations (`svg` and `png` files respectively) - Updated tests/cleanup of old tests that relied on scripts that no longer exist As usual, I'd really appreciate any suggestions or thoughts!! --- .../src/passes/profiler_instrumentation.rs | 243 +++++++- docs/running-calyx/profiler.md | 37 ++ fud2/scripts/profiler.rhai | 18 +- fud2/src/cli_pyenv.rs | 7 + .../snapshots/tests__test@plan_profiler.snap | 13 +- runt.toml | 10 +- .../profiler_instrumentation/cond.expect | 35 ++ .../profiler_instrumentation/cond.futil} | 21 +- .../profiler_instrumentation/cond.futil.data} | 0 .../profiler_instrumentation.expect | 50 ++ .../profiler_instrumentation.futil | 2 +- .../triple-multi-component.expect | 65 ++ .../triple-multi-component.futil | 72 +++ tests/profiler/par.expect | 69 --- tests/profiler/par.futil | 41 -- tests/profiler/par.futil.data | 32 - tests/profiler/simple-par.expect | 47 -- tests/profiler/simple-seq.expect | 36 -- tests/profiler/simple-seq.futil | 23 - tests/profiler/simple-seq.futil.data | 12 - tests/profiler/while-never-true.expect | 60 -- tests/profiler/while-never-true.futil | 46 -- tests/profiler/while-never-true.futil.data | 10 - tools/profiler/adjust-scaled-flame-svg.py | 31 + tools/profiler/create-visuals.py | 404 ------------- tools/profiler/create-visuals.sh | 30 + tools/profiler/parse-vcd.py | 392 ------------ tools/profiler/profiler-process.py | 561 ++++++++++++++++++ tools/profiler/run-up-to-tdcc.sh | 12 +- 29 files changed, 1144 insertions(+), 1235 deletions(-) create mode 100644 docs/running-calyx/profiler.md create mode 100644 tests/passes/profiler_instrumentation/cond.expect rename tests/{profiler/simple-par.futil => passes/profiler_instrumentation/cond.futil} (51%) rename tests/{profiler/simple-par.futil.data => passes/profiler_instrumentation/cond.futil.data} (100%) create mode 100644 tests/passes/profiler_instrumentation/profiler_instrumentation.expect rename tests/passes/{ => profiler_instrumentation}/profiler_instrumentation.futil (96%) create mode 100644 tests/passes/profiler_instrumentation/triple-multi-component.expect create mode 100644 tests/passes/profiler_instrumentation/triple-multi-component.futil delete mode 100644 tests/profiler/par.expect delete mode 100644 tests/profiler/par.futil delete mode 100644 tests/profiler/par.futil.data delete mode 100644 tests/profiler/simple-par.expect delete mode 100644 tests/profiler/simple-seq.expect delete mode 100644 tests/profiler/simple-seq.futil delete mode 100644 tests/profiler/simple-seq.futil.data delete mode 100644 tests/profiler/while-never-true.expect delete mode 100644 tests/profiler/while-never-true.futil delete mode 100644 tests/profiler/while-never-true.futil.data create mode 100644 tools/profiler/adjust-scaled-flame-svg.py delete mode 100644 tools/profiler/create-visuals.py create mode 100644 tools/profiler/create-visuals.sh delete mode 100644 tools/profiler/parse-vcd.py create mode 100644 tools/profiler/profiler-process.py diff --git a/calyx-opt/src/passes/profiler_instrumentation.rs b/calyx-opt/src/passes/profiler_instrumentation.rs index 631cdb3eb3..1e23aad8e6 100644 --- a/calyx-opt/src/passes/profiler_instrumentation.rs +++ b/calyx-opt/src/passes/profiler_instrumentation.rs @@ -1,5 +1,7 @@ +use std::collections::HashMap; + use crate::traversal::{Action, ConstructVisitor, Named, VisResult, Visitor}; -use calyx_ir::{self as ir, build_assignments, BoolAttr}; +use calyx_ir::{self as ir, BoolAttr, Guard, Id, Nothing, NumAttr}; use calyx_utils::CalyxResult; /// Adds probe wires to each group to detect when a group is active. @@ -38,39 +40,236 @@ impl Visitor for ProfilerInstrumentation { sigs: &ir::LibrarySignatures, _comps: &[ir::Component], ) -> VisResult { - // collect names of all groups (to construct group-specific cells) + let delimiter = "___"; + let mut acc = 0; + let comp_name = comp.name; + let mut structural_enable_map: HashMap< + Id, + Vec<(Id, ir::Guard)>, + > = HashMap::new(); + // groups to cells (from non-primitive components) that they invoked + let mut cell_invoke_map: HashMap> = HashMap::new(); + // groups to primitives that they invoked + let mut primitive_invoke_map: HashMap< + Id, + Vec<(Id, ir::Guard)>, + > = HashMap::new(); + // child_group --> [(parent_group, Guard)] let group_names = comp .groups .iter() .map(|group| group.borrow().name()) .collect::>(); - let comp_name = comp.name; - // for each group, construct a instrumentation cell and instrumentation assignment - let mut asgn_and_cell = Vec::with_capacity(group_names.len()); + // iterate and check for structural enables and for cell invokes + for group_ref in comp.groups.iter() { + let group = &group_ref.borrow(); + let mut primitive_vec: Vec<(Id, ir::Guard)> = Vec::new(); + for assigment_ref in group.assignments.iter() { + let dst_borrow = assigment_ref.dst.borrow(); + if let ir::PortParent::Group(parent_group_ref) = + &dst_borrow.parent + { + if dst_borrow.name == "go" { + // found an invocation of go + let invoked_group_name = + parent_group_ref.upgrade().borrow().name(); + let guard = *(assigment_ref.guard.clone()); + match structural_enable_map.get_mut(&invoked_group_name) + { + Some(vec_ref) => { + vec_ref.push((group.name(), guard)) + } + None => { + structural_enable_map.insert( + invoked_group_name, + vec![(group.name(), guard)], + ); + } + } + acc += 1; // really sad hack + } + } + if let ir::PortParent::Cell(cell_ref) = &dst_borrow.parent { + match cell_ref.upgrade().borrow().prototype.clone() { + calyx_ir::CellType::Primitive { + name: _, + param_binding: _, + is_comb, + latency: _, + } => { + let cell_name = cell_ref.upgrade().borrow().name(); + // don't need to profile for combinational primitives, and if the port isn't a go port. + if !is_comb & dst_borrow.has_attribute(NumAttr::Go) + { + let guard = Guard::and( + *(assigment_ref.guard.clone()), + Guard::port(ir::rrc( + assigment_ref.src.borrow().clone(), + )), + ); + primitive_vec.push((cell_name, guard)); + } + } + calyx_ir::CellType::Component { name: _ } => { + if dst_borrow.name == "go" { + let cell_name = + cell_ref.upgrade().borrow().name(); + match cell_invoke_map.get_mut(&group.name()) { + Some(vec_ref) => { + vec_ref.push(cell_name); + } + None => { + cell_invoke_map.insert( + group.name(), + vec![cell_name], + ); + } + } + } + } + _ => (), + } + } + } + primitive_invoke_map + .insert(group_ref.borrow().name(), primitive_vec); + } + // build probe and assignments for every group + all structural invokes + let mut builder = ir::Builder::new(comp, sigs); + let one = builder.add_constant(1, 1); + let mut group_name_assign_and_cell = Vec::with_capacity(acc); { - let mut builder = ir::Builder::new(comp, sigs); - let one = builder.add_constant(1, 1); + // probe and assignments for group (this group is currently active) for group_name in group_names.into_iter() { // store group and component name (differentiate between groups of the same name under different components) - let name = format!("{}__{}_probe", group_name, comp_name); - let inst_cell = builder.add_primitive(name, "std_wire", &[1]); - let asgn: [ir::Assignment; 1] = build_assignments!( - builder; - inst_cell["in"] = ? one["out"]; + let name = format!( + "{}{}{}_group_probe", + group_name, delimiter, comp_name ); + let probe_cell = builder.add_primitive(name, "std_wire", &[1]); + let probe_asgn: ir::Assignment = builder + .build_assignment( + probe_cell.borrow().get("in"), + one.borrow().get("out"), + Guard::True, + ); // the probes should be @control because they should have value 0 whenever the corresponding group is not active. - inst_cell.borrow_mut().add_attribute(BoolAttr::Control, 1); - inst_cell.borrow_mut().add_attribute(BoolAttr::Protected, 1); - asgn_and_cell.push((asgn[0].clone(), inst_cell)); + probe_cell.borrow_mut().add_attribute(BoolAttr::Control, 1); + probe_cell + .borrow_mut() + .add_attribute(BoolAttr::Protected, 1); + group_name_assign_and_cell + .push((group_name, probe_asgn, probe_cell)); + } + // probe and assignments for primitive invocations (this group is activating a primitive) + for (group, primitive_invs) in primitive_invoke_map.iter() { + for (primitive_cell_name, guard) in primitive_invs.iter() { + let probe_cell_name = format!( + "{}{}{}{}{}_primitive_probe", + primitive_cell_name, + delimiter, + group, + delimiter, + comp_name + ); + let probe_cell = builder.add_primitive( + probe_cell_name, + "std_wire", + &[1], + ); + probe_cell.borrow_mut().add_attribute(BoolAttr::Control, 1); + probe_cell + .borrow_mut() + .add_attribute(BoolAttr::Protected, 1); + let probe_asgn: ir::Assignment = builder + .build_assignment( + probe_cell.borrow().get("in"), + one.borrow().get("out"), + guard.clone(), + ); + group_name_assign_and_cell + .push((*group, probe_asgn, probe_cell)); + } + } + // probe and assignments for structural enables (this group is structurally enabling a child group) + for (invoked_group_name, parent_groups) in + structural_enable_map.iter() + { + for (parent_group, guard) in parent_groups.iter() { + let probe_cell_name = format!( + "{}{}{}{}{}_se_probe", + invoked_group_name, + delimiter, + parent_group, + delimiter, + comp_name + ); + let probe_cell = builder.add_primitive( + probe_cell_name, + "std_wire", + &[1], + ); + probe_cell.borrow_mut().add_attribute(BoolAttr::Control, 1); + probe_cell + .borrow_mut() + .add_attribute(BoolAttr::Protected, 1); + let probe_asgn: ir::Assignment = builder + .build_assignment( + probe_cell.borrow().get("in"), + one.borrow().get("out"), + guard.clone(), + ); + group_name_assign_and_cell.push(( + *parent_group, + probe_asgn, + probe_cell, + )); + } + } + // probe cell and assignments for structural cell invocations (the group is structurally invoking a cell.) + for (invoker_group, invoked_cells) in cell_invoke_map.iter() { + for invoked_cell in invoked_cells { + let probe_cell_name = format!( + "{}{}{}{}{}_cell_probe", + invoked_cell, + delimiter, + invoker_group, + delimiter, + comp_name + ); + let probe_cell = builder.add_primitive( + probe_cell_name, + "std_wire", + &[1], + ); + probe_cell.borrow_mut().add_attribute(BoolAttr::Control, 1); + probe_cell + .borrow_mut() + .add_attribute(BoolAttr::Protected, 1); + // NOTE: this probe is active for the duration of the whole group. Hence, it may be active even when the cell itself is inactive. + let probe_asgn: ir::Assignment = builder + .build_assignment( + probe_cell.borrow().get("in"), + one.borrow().get("out"), + Guard::True, + ); + group_name_assign_and_cell.push(( + *invoker_group, + probe_asgn, + probe_cell, + )); + } } } - // add cells and assignments - for (group, (asgn, inst_cell)) in - comp.groups.iter().zip(asgn_and_cell.into_iter()) - { - group.borrow_mut().assignments.push(asgn); - comp.cells.add(inst_cell); + // ugh so ugly + for group in comp.groups.iter() { + for (group_name, asgn, cell) in group_name_assign_and_cell.iter() { + if group.borrow().name() == group_name { + group.borrow_mut().assignments.push(asgn.clone()); + comp.cells.add(cell.to_owned()); + } + } } - Ok(Action::Stop) + Ok(Action::Continue) } } diff --git a/docs/running-calyx/profiler.md b/docs/running-calyx/profiler.md new file mode 100644 index 0000000000..d1c64d9c0e --- /dev/null +++ b/docs/running-calyx/profiler.md @@ -0,0 +1,37 @@ +# Calyx Profiler + +*Note: The profiler is still in development. If you have any suggestions, thoughts, or feedback, please let us know!* + +Profilers can help you analyze performance information to find places you can optimize in your code. Currently, the Calyx profiler prouduces timing information in terms of cycle counts. + +## Setup + +In order to run the profiler, you need: +- [fud2][] +- The Python [`vcdvcd` library](https://github.com/cirosantilli/vcdvcd). Running `fud2 env init` should install this for you. +- A clone of Brendan Gregg's Flamegraph repository: [https://github.com/brendangregg/FlameGraph](https://github.com/brendangregg/FlameGraph) + +Then, you need to edit your fud2 configuration file to specify the location of `flamegraph.pl` within the `Flamegraph` repository: + +ex) +``` +[flamegraph] +script = "/home/ayaka/projects/FlameGraph/flamegraph.pl" +``` + +## Basic Use + +To obtain a flame graph, run fud2 with an SVG output file: + +ex) +``` +fud2 tests/correctness/pow.futil -o pow.svg -s sim.data=tests/correctness/pow.futil.data +``` + +The produced flame graph is "flattened", which means that each parallel arm gets its own "cycle". So, if arm A and arm B were executing on a single cycle, the flame graph would account for a cycle in arm A and a cycle in arm B. You can view and interact with the flame graph using your favorite web browser. + +If you retain the fud2 build directory with the `--keep` option or the `--dir` option, you will find additional profiler output files in `/profiler-out`: + + - `scaled-flame.svg`: A scaled flame graph, where a cycle is divided between the parallel arms in execution. So, if arm A and arm B were executing on a single cycle, the flame graph would account for 0.5 cycles in arm A and 0.5 cycles in arm B. + - `aggregate.dot.png`: A tree summary of the execution of the program. Nodes (groups and cells) are labeled with the number of times the node was a leaf, and edges are labeled with the number of cycles that edge was activated. + - `rank{i}.dot.png`: A tree representation of the `i`th most active stack picture. `rankings.csv` lists the specific cycles that each ranked tree was active for. diff --git a/fud2/scripts/profiler.rhai b/fud2/scripts/profiler.rhai index 7fe78e7dee..0a678efa35 100644 --- a/fud2/scripts/profiler.rhai +++ b/fud2/scripts/profiler.rhai @@ -21,16 +21,13 @@ fn profiling_setup(e) { // rules for postprocessing - // script to process vcd and attribute active cycles to every group/cell - e.var_("parse-vcd-script", "$calyx-base/tools/profiler/parse-vcd.py"); - e.rule("parse-vcd", "python3 $parse-vcd-script $in $tdcc-json $cells summary.csv $out"); - - // script to produce trace and visuals - e.var_("create-visuals-script", "$calyx-base/tools/profiler/create-visuals.py"); - e.rule("create-visuals", "python3 $create-visuals-script $in $cells timeline.json fsm-timeline.json $out fsm-flame.folded frequency.folded components.folded fsm-components.folded"); + // script to process vcd and produce folded representation of flame graph + e.var_("parse-vcd-script", "$calyx-base/tools/profiler/profiler-process.py"); + e.rule("parse-vcd", "python3 $parse-vcd-script $in $cells profiler-out $out"); e.config_var("flamegraph-script", "flamegraph.script"); - e.rule("produce-flame-graph", "$flamegraph-script $in > $out"); + e.var_("create-visuals-script", "$calyx-base/tools/profiler/create-visuals.sh"); + e.rule("create-visuals", "bash $create-visuals-script $flamegraph-script profiler-out $in $out"); // Standalone Verilog testbench. copied from testbench e.rsrc("tb.sv"); @@ -72,9 +69,8 @@ fn calyx_to_flamegraph(e, input, output) { // vcd --> flamegraph let elems_profiled_json = "elems-profiled.json"; let flamegraph_folded = "flamegraph.folded"; - e.build_cmd([elems_profiled_json], "parse-vcd", [instrumented_vcd], []); - e.build_cmd([flamegraph_folded], "create-visuals", [elems_profiled_json], ["$cells"]); - e.build_cmd([output], "produce-flame-graph", [flamegraph_folded], []); + e.build_cmd([flamegraph_folded], "parse-vcd", [instrumented_vcd], ["$cells"]); + e.build_cmd([output], "create-visuals", [flamegraph_folded], []); } op( diff --git a/fud2/src/cli_pyenv.rs b/fud2/src/cli_pyenv.rs index f5d01e9821..e01f15c659 100644 --- a/fud2/src/cli_pyenv.rs +++ b/fud2/src/cli_pyenv.rs @@ -46,6 +46,13 @@ impl PyenvCommand { .stdout(std::io::stdout()) .output()?; + // install vcdvcd (for Profiler) + Command::new(pyenv.join("bin").join("pip")) + .arg("install") + .arg("vcdvcd") + .stdout(std::io::stdout()) + .output()?; + // install flit Command::new(pyenv.join("bin").join("pip")) .arg("install") diff --git a/fud2/tests/snapshots/tests__test@plan_profiler.snap b/fud2/tests/snapshots/tests__test@plan_profiler.snap index c1b862f538..1e8c101447 100644 --- a/fud2/tests/snapshots/tests__test@plan_profiler.snap +++ b/fud2/tests/snapshots/tests__test@plan_profiler.snap @@ -1,6 +1,7 @@ --- source: fud2/tests/tests.rs description: "emit plan: profiler" +snapshot_kind: text --- build-tool = fud2 rule get-rsrc @@ -24,12 +25,9 @@ passes = all component_cells = $calyx-base/target/debug/component_cells rule component-cells command = $component_cells -l $calyx-base $in > $out -parse-vcd-script = $calyx-base/tools/profiler/parse-vcd.py +parse-vcd-script = $calyx-base/tools/profiler/profiler-process.py rule parse-vcd - command = python3 $parse-vcd-script $in $tdcc-json $cells summary.csv $out -create-visuals-script = $calyx-base/tools/profiler/create-visuals.py -rule create-visuals - command = python3 $create-visuals-script $in $cells timeline.json fsm-timeline.json $out fsm-flame.folded frequency.folded components.folded fsm-components.folded + command = python3 $parse-vcd-script $in $cells profiler-out $out verilator = verilator cycle-limit = 500000000 @@ -63,8 +61,7 @@ build instrumented.exe: cp verilator-out/Vtoplevel build sim.log instrumented.vcd: sim-run instrumented.exe $datadir bin = instrumented.exe args = +NOTRACE=0 +OUT=instrumented.vcd -build elems-profiled.json: parse-vcd instrumented.vcd -build flamegraph.folded: create-visuals elems-profiled.json | $cells -build /output.ext: produce-flame-graph flamegraph.folded +build flamegraph.folded: parse-vcd instrumented.vcd | $cells +build /output.ext: create-visuals flamegraph.folded default /output.ext diff --git a/runt.toml b/runt.toml index c5b421b234..66d4a8cae9 100644 --- a/runt.toml +++ b/runt.toml @@ -681,12 +681,4 @@ make --silent -B TEST_PATH={} COCOTB_LOG_LEVEL=CRITICAL |\ make clean && \ rm -f results.xml -""" - -### Profiler tests -[[tests]] -name = "profiler" -paths = ["tests/profiler/*.futil"] -cmd = """ -bash tools/profiler/get-profile-counts-info.sh {} {}.data STDOUT -d -""" +""" \ No newline at end of file diff --git a/tests/passes/profiler_instrumentation/cond.expect b/tests/passes/profiler_instrumentation/cond.expect new file mode 100644 index 0000000000..186dcc56f9 --- /dev/null +++ b/tests/passes/profiler_instrumentation/cond.expect @@ -0,0 +1,35 @@ +import "primitives/core.futil"; +import "primitives/memories/comb.futil"; +component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) { + cells { + @external a = comb_mem_d1(32, 1, 1); + lt = std_lt(32); + @control @generated @protected wr_a___main_group_probe = std_wire(1); + @control @generated @protected a___wr_a___main_primitive_probe = std_wire(1); + @control @generated @protected wr_b___main_group_probe = std_wire(1); + @control @generated @protected wr_a___wr_b___main_se_probe = std_wire(1); + } + wires { + group wr_a { + a.addr0 = 1'd0; + a.write_en = 1'd1; + a.write_data = 32'd1; + wr_a[done] = a.done; + wr_a___main_group_probe.in = 1'd1; + a___wr_a___main_primitive_probe.in = 1'd1; + } + group wr_b { + wr_a[go] = lt.out ? 1'd1; + wr_b[done] = wr_a[done]; + wr_b___main_group_probe.in = 1'd1; + wr_a___wr_b___main_se_probe.in = lt.out ? 1'd1; + } + comb group cond { + lt.left = 32'd5; + lt.right = 32'd9; + } + } + control { + wr_b; + } +} diff --git a/tests/profiler/simple-par.futil b/tests/passes/profiler_instrumentation/cond.futil similarity index 51% rename from tests/profiler/simple-par.futil rename to tests/passes/profiler_instrumentation/cond.futil index a66b7ab5e7..a0d5d50943 100644 --- a/tests/profiler/simple-par.futil +++ b/tests/passes/profiler_instrumentation/cond.futil @@ -1,23 +1,34 @@ +// -p profiler-instrumentation + import "primitives/core.futil"; import "primitives/memories/comb.futil"; component main() -> () { cells { @external(1) a = comb_mem_d1(32, 1, 1); + lt = std_lt(32); } wires { - group write { + comb group cond { + lt.left = 32'd5; + lt.right = 32'd9; + } + + group wr_a { a.addr0 = 1'b0; a.write_en = 1'b1; a.write_data = 32'd1; - write[done] = a.done; + wr_a[done] = a.done; + } + + group wr_b { + wr_a[go] = lt.out ? 1'b1; + wr_b[done] = wr_a[done]; } } control { - par { - write; - } + wr_b; } } diff --git a/tests/profiler/simple-par.futil.data b/tests/passes/profiler_instrumentation/cond.futil.data similarity index 100% rename from tests/profiler/simple-par.futil.data rename to tests/passes/profiler_instrumentation/cond.futil.data diff --git a/tests/passes/profiler_instrumentation/profiler_instrumentation.expect b/tests/passes/profiler_instrumentation/profiler_instrumentation.expect new file mode 100644 index 0000000000..62eb8c93ed --- /dev/null +++ b/tests/passes/profiler_instrumentation/profiler_instrumentation.expect @@ -0,0 +1,50 @@ +import "primitives/core.futil"; +import "primitives/memories/comb.futil"; +component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) { + cells { + @external i = comb_mem_d1(32, 1, 1); + lt = std_lt(32); + lt_reg = std_reg(1); + add = std_add(32); + @control @generated @protected cond___main_group_probe = std_wire(1); + @control @generated @protected lt_reg___cond___main_primitive_probe = std_wire(1); + @control @generated @protected incr___main_group_probe = std_wire(1); + @control @generated @protected i___incr___main_primitive_probe = std_wire(1); + } + wires { + group cond { + i.addr0 = 1'd0; + lt.left = i.read_data; + lt.right = 32'd8; + lt_reg.in = lt.out; + lt_reg.write_en = 1'd1; + cond[done] = lt_reg.done; + cond___main_group_probe.in = 1'd1; + lt_reg___cond___main_primitive_probe.in = 1'd1; + } + group incr<"static"=1> { + add.right = i.read_data; + add.left = 32'd1; + i.write_data = add.out; + i.addr0 = 1'd0; + i.write_en = 1'd1; + incr[done] = i.done; + incr___main_group_probe.in = 1'd1; + i___incr___main_primitive_probe.in = 1'd1; + } + } + control { + seq { + cond; + while lt_reg.out { + seq { + incr; + incr; + cond; + } + } + } + } +} +---STDERR--- +[WARN calyx_frontend::attribute] The attribute @static is deprecated and will be ignored by the compiler. diff --git a/tests/passes/profiler_instrumentation.futil b/tests/passes/profiler_instrumentation/profiler_instrumentation.futil similarity index 96% rename from tests/passes/profiler_instrumentation.futil rename to tests/passes/profiler_instrumentation/profiler_instrumentation.futil index 5ed5727dad..98578f073f 100644 --- a/tests/passes/profiler_instrumentation.futil +++ b/tests/passes/profiler_instrumentation/profiler_instrumentation.futil @@ -1,4 +1,4 @@ -//-p profiler-instrumentation +// -p profiler-instrumentation import "primitives/core.futil"; import "primitives/memories/comb.futil"; diff --git a/tests/passes/profiler_instrumentation/triple-multi-component.expect b/tests/passes/profiler_instrumentation/triple-multi-component.expect new file mode 100644 index 0000000000..8bf55e4a35 --- /dev/null +++ b/tests/passes/profiler_instrumentation/triple-multi-component.expect @@ -0,0 +1,65 @@ +import "primitives/core.futil"; +import "primitives/memories/comb.futil"; +component identity(in: 32, @go go: 1, @clk clk: 1, @reset reset: 1) -> (out: 32, @done done: 1) { + cells { + r = std_reg(32); + @control @generated @protected save___identity_group_probe = std_wire(1); + @control @generated @protected r___save___identity_primitive_probe = std_wire(1); + } + wires { + group save { + r.in = in; + r.write_en = 1'd1; + save[done] = r.done; + save___identity_group_probe.in = 1'd1; + r___save___identity_primitive_probe.in = 1'd1; + } + out = r.out; + } + control { + save; + } +} +component middle(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) { + cells { + id = identity(); + current_value = std_reg(32); + @control @generated @protected run_id___middle_group_probe = std_wire(1); + @control @generated @protected id___run_id___middle_cell_probe = std_wire(1); + @control @generated @protected use_id___middle_group_probe = std_wire(1); + @control @generated @protected current_value___use_id___middle_primitive_probe = std_wire(1); + } + wires { + group run_id { + id.in = 32'd10; + id.go = 1'd1; + run_id[done] = id.done; + run_id___middle_group_probe.in = 1'd1; + id___run_id___middle_cell_probe.in = 1'd1; + } + group use_id { + current_value.in = id.out; + current_value.write_en = 1'd1; + use_id[done] = current_value.done; + use_id___middle_group_probe.in = 1'd1; + current_value___use_id___middle_primitive_probe.in = 1'd1; + } + } + control { + seq { + run_id; + use_id; + } + } +} +component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) { + cells { + mid = middle(); + } + wires {} + control { + seq { + invoke mid()(); + } + } +} diff --git a/tests/passes/profiler_instrumentation/triple-multi-component.futil b/tests/passes/profiler_instrumentation/triple-multi-component.futil new file mode 100644 index 0000000000..91dd7ca06a --- /dev/null +++ b/tests/passes/profiler_instrumentation/triple-multi-component.futil @@ -0,0 +1,72 @@ +// -p profiler-instrumentation + +import "primitives/core.futil"; +import "primitives/memories/comb.futil"; + +//// ANCHOR: component +component identity(in: 32) -> (out: 32) { + cells { + r = std_reg(32); + } + wires { + group save { + r.in = in; + r.write_en = 1'd1; + save[done] = r.done; + } + + //// ANCHOR: wires + // This component always outputs the current value in r + out = r.out; + //// ANCHOR_END: wires + } + control { + save; + } +} +//// ANCHOR_END: component + +//// ANCHOR: main +component middle() -> () { + cells { + // Instantiate the identity element + id = identity(); + current_value = std_reg(32); + } + wires { + group run_id { + // We want to "save" the value 10 inside the identity group. + id.in = 32'd10; + // All components have a magic "go" and "done" port added to them. + // Execute the component. + id.go = 1'd1; + run_id[done] = id.done; + } + group use_id { + // We want to "observe" the current value saved in id. + // The out port on the `id` component always shows the last saved + // element. We don't need to set the `go` because we're not executing + // and control. + current_value.in = id.out; + current_value.write_en = 1'd1; + use_id[done] = current_value.done; + } + } + control { + seq { run_id; use_id; } + } +} + +component main() -> () { + cells { + mid = middle(); + } + wires { + + } + control { + seq { invoke mid()(); } + } +} + +//// ANCHOR_END: main diff --git a/tests/profiler/par.expect b/tests/profiler/par.expect deleted file mode 100644 index bf4f603070..0000000000 --- a/tests/profiler/par.expect +++ /dev/null @@ -1,69 +0,0 @@ -[get-profile-counts-info.sh] Obtaining FSM info from TDCC -[get-profile-counts-info.sh] Obtaining cell information from component-cells backend -[get-profile-counts-info.sh] Obtaining VCD file via simulation -[get-profile-counts-info.sh] Using FSM info and VCD file to obtain cycle level counts -Total clock cycles: 3 -=====SUMMARY===== - -[FSM] Group TOP.toplevel.main.par0 Summary: - Total cycles: 3 - # of times active: 1 - Avg runtime: 3.0 - -[GT] Group TOP.toplevel.main.par0 Summary: - Total cycles: 2 - # of times active: 1 - Avg runtime: 2.0 - -[GT] Group TOP.toplevel.main.wr_a Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -[GT] Group TOP.toplevel.main.wr_b Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -[GT] Group TOP.toplevel.main.wr_c Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -=====DUMP===== - -[FSM] Group TOP.toplevel.main.par0: - FSM name: TOP.toplevel.main.fsm - FSM state ids: [0] - Total cycles: 3 - # of times active: 1 - Segments: [0, 3) - -[GT] Group TOP.toplevel.main.par0: - Total cycles: 2 - # of times active: 1 - Segments: [0, 2) - -[GT] Group TOP.toplevel.main.wr_a: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -[GT] Group TOP.toplevel.main.wr_b: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -[GT] Group TOP.toplevel.main.wr_c: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -name,total-cycles,times-active,avg -TOP.toplevel.main.par0[FSM],3,1,3.0 -TOP.toplevel.main.par0,2,1,2.0 -TOP.toplevel.main.wr_a,1,1,1.0 -TOP.toplevel.main.wr_b,1,1,1.0 -TOP.toplevel.main.wr_c,1,1,1.0 -TOTAL,3,-,- -[get-profile-counts-info.sh] Writing visualization diff --git a/tests/profiler/par.futil b/tests/profiler/par.futil deleted file mode 100644 index 1f71a5e152..0000000000 --- a/tests/profiler/par.futil +++ /dev/null @@ -1,41 +0,0 @@ -import "primitives/core.futil"; -import "primitives/memories/comb.futil"; - -component main() -> () { - cells { - @external(1) a = comb_mem_d1(32, 1, 1); - @external(1) b = comb_mem_d1(32, 1, 1); - @external(1) c = comb_mem_d1(32, 1, 1); - } - - wires { - group wr_a { - a.addr0 = 1'b0; - a.write_en = 1'b1; - a.write_data = 32'd1; - wr_a[done] = a.done; - } - - group wr_b { - b.addr0 = 1'b0; - b.write_en = 1'b1; - b.write_data = 32'd1; - wr_b[done] = b.done; - } - - group wr_c { - c.addr0 = 1'b0; - c.write_en = 1'b1; - c.write_data = 32'd1; - wr_c[done] = c.done; - } - } - - control { - par { - wr_a; - wr_b; - wr_c; - } - } -} diff --git a/tests/profiler/par.futil.data b/tests/profiler/par.futil.data deleted file mode 100644 index 4862df80f9..0000000000 --- a/tests/profiler/par.futil.data +++ /dev/null @@ -1,32 +0,0 @@ -{ - "a": { - "data": [ - 0 - ], - "format": { - "numeric_type": "bitnum", - "is_signed": true, - "width": 32 - } - }, - "b": { - "data": [ - 0 - ], - "format": { - "numeric_type": "bitnum", - "is_signed": false, - "width": 32 - } - }, - "c": { - "data": [ - 0 - ], - "format": { - "numeric_type": "bitnum", - "is_signed": false, - "width": 32 - } - } -} diff --git a/tests/profiler/simple-par.expect b/tests/profiler/simple-par.expect deleted file mode 100644 index 213fd30020..0000000000 --- a/tests/profiler/simple-par.expect +++ /dev/null @@ -1,47 +0,0 @@ -[get-profile-counts-info.sh] Obtaining FSM info from TDCC -[get-profile-counts-info.sh] Obtaining cell information from component-cells backend -[get-profile-counts-info.sh] Obtaining VCD file via simulation -[get-profile-counts-info.sh] Using FSM info and VCD file to obtain cycle level counts -Total clock cycles: 3 -=====SUMMARY===== - -[FSM] Group TOP.toplevel.main.par0 Summary: - Total cycles: 3 - # of times active: 1 - Avg runtime: 3.0 - -[GT] Group TOP.toplevel.main.par0 Summary: - Total cycles: 2 - # of times active: 1 - Avg runtime: 2.0 - -[GT] Group TOP.toplevel.main.write Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -=====DUMP===== - -[FSM] Group TOP.toplevel.main.par0: - FSM name: TOP.toplevel.main.fsm - FSM state ids: [0] - Total cycles: 3 - # of times active: 1 - Segments: [0, 3) - -[GT] Group TOP.toplevel.main.par0: - Total cycles: 2 - # of times active: 1 - Segments: [0, 2) - -[GT] Group TOP.toplevel.main.write: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -name,total-cycles,times-active,avg -TOP.toplevel.main.par0[FSM],3,1,3.0 -TOP.toplevel.main.par0,2,1,2.0 -TOP.toplevel.main.write,1,1,1.0 -TOTAL,3,-,- -[get-profile-counts-info.sh] Writing visualization diff --git a/tests/profiler/simple-seq.expect b/tests/profiler/simple-seq.expect deleted file mode 100644 index 35bff072bf..0000000000 --- a/tests/profiler/simple-seq.expect +++ /dev/null @@ -1,36 +0,0 @@ -[get-profile-counts-info.sh] Obtaining FSM info from TDCC -[get-profile-counts-info.sh] Obtaining cell information from component-cells backend -[get-profile-counts-info.sh] Obtaining VCD file via simulation -[get-profile-counts-info.sh] Using FSM info and VCD file to obtain cycle level counts -Total clock cycles: 2 -=====SUMMARY===== - -[FSM] Group TOP.toplevel.main.write Summary: - Total cycles: 2 - # of times active: 1 - Avg runtime: 2.0 - -[GT] Group TOP.toplevel.main.write Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -=====DUMP===== - -[FSM] Group TOP.toplevel.main.write: - FSM name: TOP.toplevel.main.fsm - FSM state ids: [0] - Total cycles: 2 - # of times active: 1 - Segments: [0, 2) - -[GT] Group TOP.toplevel.main.write: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -name,total-cycles,times-active,avg -TOP.toplevel.main.write[FSM],2,1,2.0 -TOP.toplevel.main.write,1,1,1.0 -TOTAL,2,-,- -[get-profile-counts-info.sh] Writing visualization diff --git a/tests/profiler/simple-seq.futil b/tests/profiler/simple-seq.futil deleted file mode 100644 index 9bf79820a1..0000000000 --- a/tests/profiler/simple-seq.futil +++ /dev/null @@ -1,23 +0,0 @@ -import "primitives/core.futil"; -import "primitives/memories/comb.futil"; - -component main() -> () { - cells { - @external(1) a = comb_mem_d1(32, 1, 1); - } - - wires { - group write { - a.addr0 = 1'b0; - a.write_en = 1'b1; - a.write_data = 32'd1; - write[done] = a.done; - } - } - - control { - seq { - write; - } - } -} diff --git a/tests/profiler/simple-seq.futil.data b/tests/profiler/simple-seq.futil.data deleted file mode 100644 index cad4ef0e4a..0000000000 --- a/tests/profiler/simple-seq.futil.data +++ /dev/null @@ -1,12 +0,0 @@ -{ - "a": { - "data": [ - 0 - ], - "format": { - "numeric_type": "bitnum", - "is_signed": true, - "width": 32 - } - } -} diff --git a/tests/profiler/while-never-true.expect b/tests/profiler/while-never-true.expect deleted file mode 100644 index 04bf0a1c9f..0000000000 --- a/tests/profiler/while-never-true.expect +++ /dev/null @@ -1,60 +0,0 @@ -[get-profile-counts-info.sh] Obtaining FSM info from TDCC -[get-profile-counts-info.sh] Obtaining cell information from component-cells backend -[get-profile-counts-info.sh] Obtaining VCD file via simulation -[get-profile-counts-info.sh] Using FSM info and VCD file to obtain cycle level counts -Total clock cycles: 2 -=====SUMMARY===== - -[FSM] Group TOP.toplevel.main.cond Summary: - Total cycles: 2 - # of times active: 1 - Avg runtime: 2.0 - -[GT] Group TOP.toplevel.main.cond Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -[FSM] Group TOP.toplevel.main.incr Summary: - Total cycles: 0 - # of times active: 0 - Avg runtime: 0 - -[GT] Group TOP.toplevel.main.incr Summary: - Total cycles: 0 - # of times active: 0 - Avg runtime: 0 - -=====DUMP===== - -[FSM] Group TOP.toplevel.main.cond: - FSM name: TOP.toplevel.main.fsm - FSM state ids: [0, 3] - Total cycles: 2 - # of times active: 1 - Segments: [0, 2) - -[GT] Group TOP.toplevel.main.cond: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -[FSM] Group TOP.toplevel.main.incr: - FSM name: TOP.toplevel.main.fsm - FSM state ids: [2, 1] - Total cycles: 0 - # of times active: 0 - Segments: - -[GT] Group TOP.toplevel.main.incr: - Total cycles: 0 - # of times active: 0 - Segments: - -name,total-cycles,times-active,avg -TOP.toplevel.main.cond[FSM],2,1,2.0 -TOP.toplevel.main.cond,1,1,1.0 -TOP.toplevel.main.incr[FSM],0,0,0 -TOP.toplevel.main.incr,0,0,0 -TOTAL,2,-,- -[get-profile-counts-info.sh] Writing visualization diff --git a/tests/profiler/while-never-true.futil b/tests/profiler/while-never-true.futil deleted file mode 100644 index 97805bd8f6..0000000000 --- a/tests/profiler/while-never-true.futil +++ /dev/null @@ -1,46 +0,0 @@ -import "primitives/core.futil"; -import "primitives/memories/comb.futil"; - -component main() -> () { - cells { - @external(1) i = comb_mem_d1(32, 1, 1); - lt = std_lt(32); - lt_reg = std_reg(1); - add = std_add(32); - } - - wires { - group cond { - i.addr0 = 1'd0; - lt.left = i.read_data; - lt.right = 32'd0; - lt_reg.in = lt.out; - lt_reg.write_en = 1'b1; - cond[done] = lt_reg.done; - } - - group incr { - add.right = i.read_data; - add.left = 32'd1; - - i.write_data = add.out; - i.addr0 = 1'd0; - i.write_en = 1'b1; - - incr[done] = i.done; - } - } - - control { - seq { - cond; - while lt_reg.out { - seq { - incr; - incr; - cond; - } - } - } - } -} diff --git a/tests/profiler/while-never-true.futil.data b/tests/profiler/while-never-true.futil.data deleted file mode 100644 index a2b95ef52d..0000000000 --- a/tests/profiler/while-never-true.futil.data +++ /dev/null @@ -1,10 +0,0 @@ -{ - "i": { - "data": [0], - "format": { - "numeric_type": "bitnum", - "is_signed": false, - "width": 32 - } - } -} diff --git a/tools/profiler/adjust-scaled-flame-svg.py b/tools/profiler/adjust-scaled-flame-svg.py new file mode 100644 index 0000000000..f3845a2cbe --- /dev/null +++ b/tools/profiler/adjust-scaled-flame-svg.py @@ -0,0 +1,31 @@ +import os +import sys + +# Takes in a flame graph svg that is scaled by 1000 and prints a version with fixed cycles. +def main(svg_in): + oin = open(svg_in, "r") + + for line in oin: + if line.startswith(""): + line_split = line.strip().split(" ") + target_idx = 0 + for i in range(len(line_split)): + if line_split[i] == "cycles,": + target_idx = i-1 + new_number = int(line_split[target_idx].split("(")[1].replace(",", "")) / 1000 + print(" ".join(line_split[0:target_idx]) + " (" + "{:,}".format(new_number) + " " + " ".join(line_split[target_idx+1:])) + else: + print(line.strip()) + + +if __name__ == "__main__": + if len(sys.argv) > 1: + svg_filename = sys.argv[1] + main(svg_filename) + else: + args_desc = [ + "INPUT_SVG" + ] + print(f"Usage: {sys.argv[0]} {' '.join(args_desc)}") + print("CELLS_JSON: Run the `component_cells` tool") + sys.exit(-1) \ No newline at end of file diff --git a/tools/profiler/create-visuals.py b/tools/profiler/create-visuals.py deleted file mode 100644 index 1c279380d4..0000000000 --- a/tools/profiler/create-visuals.py +++ /dev/null @@ -1,404 +0,0 @@ -""" -Takes in a dump file created by parse-vcd.py and creates files for visualization: -- *.folded files for producing flame graphs -- *.json files displaying the timeline (to be read by Perfetto UI) -""" -import json -import sys - -class CallStackElement: - """ - A component on the stack that is active at a given snapshot in time. Contains cell name and any active groups. - (The element may not have any active groups when control is taking extra cycles for FSMs, etc.) - starting_group is the first group that shows up. When starting_group is None, the stack simply contains the cell. - """ - def __init__(self, component, starting_group): - self.component = component - if starting_group is None: - self.active_groups = [] - else: - self.active_groups = [starting_group] - self.cell_fullname = ".".join(starting_group.split(".")[:-1]) # remove group name - self.cell_id = None - - def __repr__(self): - return f"([{self.component}] Active groups: {self.active_groups})" - - """ - Registers a new group active on the stack. - """ - def add_group(self, group_name): - if group_name not in self.active_groups: - self.active_groups.append(group_name) - - """ - Returns the active group if the component is sequential (has only one active group), or None if the cell has no active groups. - Throws exception if there are multiple groups active at the same time, since we are assuming sequential programs right now. - """ - def get_active_group(self): - if len(self.active_groups) == 0: - return None - elif len(self.active_groups) == 1: - return self.active_groups[0] - else: - # concatenate all parallel active groups - sorted_active_groups = list(sorted(self.active_groups)) - acc = sorted_active_groups[0] - for group in sorted_active_groups[1:]: - suffix = group.split(".")[-1] - acc += "/" + suffix - return acc - - """ - Returns the identifier of this stack: either the full name of the active group, or the full name of the cell if no groups are active. - """ - def get_fullname(self): - active_group = self.get_active_group() - if active_group is None: - return self.cell_fullname - else: - return active_group - - """ - Returns the representation of the current stack for *.folded flame graph files. - """ - def flame_stack_string(self, main_component): - main_shortname = main_component.split("TOP.toplevel.")[1] - if self.component == main_shortname: - prefix = main_component - else: - prefix = self.cell_id - - active_group = self.get_active_group() - if active_group is not None: - return prefix + ";" + active_group.split(".")[-1] - else: - return prefix - - """ - Returns the name of the stack's component. - """ - def component_flame_stack_string(self, main_component): - main_shortname = main_component.split("TOP.toplevel.")[1] - if self.component == main_shortname: - return main_component - else: - return self.component - - # other utility functions - - def get_stack_depth(self): - return self.get_fullname().count(".") - - def add_flame_cell_name(self, parent_component, cell_name): - self.cell_id = f"{self.component}[{parent_component}.{cell_name}]" - self.parent_component = parent_component - self.cell_name = cell_name - - def get_active_groups(self): - return self.active_groups - - def add_cell_fullname(self, cell_fullname): - self.cell_fullname = cell_fullname - -""" -Computes which groups were tracked by FSMs. -""" -def get_fsm_groups(profiled_info): - fsm_groups = set() - all_groups = set() - for group_info in profiled_info: - if group_info["name"] == "TOTAL" or group_info["component"] is None: - continue - all_groups.add(group_info["name"]) - if group_info["fsm_name"] is not None: - fsm_groups.add(group_info["name"]) - return fsm_groups, all_groups - -""" -Adds a new CallStackElement object for `component` to `timeline_map` -""" -def add_elem_to_callstack(timeline_map, component, name, is_cell): - if component not in timeline_map: - if is_cell: - timeline_map[component] = CallStackElement(component, None) - timeline_map[component].add_cell_fullname(name) - else: - timeline_map[component] = CallStackElement(component, name) - else: - timeline_map[component].add_group(name) - -""" -Returns the stack element that is deepest in the simultaneously running sets of components -""" -def get_deepest_stack_element(stack_elems): - elems_sorted = sorted(stack_elems, key=lambda k : stack_elems[k].get_stack_depth(), reverse=True) - # NOTE: assuming sequential for now, which means (with n as the "deepest stack size"): - # (1) There is only one element with stack depth n (this should be a group) - # (2) There are two elements with stack depth n (a group and a cell). We want to return the cell in this case. - if len(elems_sorted) == 1 or stack_elems[elems_sorted[0]].get_stack_depth() > stack_elems[elems_sorted[1]].get_stack_depth(): - return elems_sorted[0] - elif stack_elems[elems_sorted[0]].get_active_groups() is None: # 0th element is a cell - return elems_sorted[0] - else: # 1th element has to be a cell, assuming sequential programs. - return elems_sorted[1] - -""" -Helper method to put trace stack elements in calling order -""" -def order_trace(main_component, cells_map, timeline): - main_shortname = main_component.split("TOP.toplevel.")[1] - # timeline_map has an *unordered* - processed_trace = {} - for i in timeline: - if main_shortname not in timeline[i]: - continue - stack = [timeline[i][main_shortname]] - # get the element that is deepest within the stack, then reconstruct from there - component = get_deepest_stack_element(timeline[i]) - if component != main_shortname: - cell_full_name = timeline[i][component].cell_fullname - after_main = cell_full_name.split(f"{main_component}.")[1] - after_main_split = after_main.split(".") - prev_component = main_shortname - for cell_name in after_main_split: - cell_component = cells_map[prev_component][cell_name] - timeline[i][cell_component].add_flame_cell_name(prev_component, cell_name) - stack.append(timeline[i][cell_component]) - prev_component = cell_component - processed_trace[i] = stack - return processed_trace - -""" -Constructs traces: for every cycle, what was the stack of active cells/groups? -""" -def create_trace(profiled_info, main_component, cells_map, fsm_groups, all_groups): - summary = list(filter(lambda x : x["name"] == "TOTAL", profiled_info))[0] - total_cycles = summary["total_cycles"] - only_gt_groups = all_groups.difference(fsm_groups) - timeline_map = {i : {} for i in range(total_cycles)} - fsm_timeline_map = {i : {} for i in range(total_cycles)} - group_to_gt_segments = {} # we need segment info for frequency checking - # first iterate through all of the cells - for cell_info in filter(lambda x : "is_cell" in x and x["is_cell"], profiled_info): - for segment in cell_info["closed_segments"]: - for i in range(segment["start"], segment["end"]): - add_elem_to_callstack(fsm_timeline_map[i], cell_info["component"], cell_info["name"], True) - add_elem_to_callstack(timeline_map[i], cell_info["component"], cell_info["name"], True) - # next iterate through everything else - for group_info in profiled_info: - group_name = group_info["name"] - if group_name == "TOTAL" or group_info["is_cell"]: # only care about actual groups - continue - group_component = group_info["component"] - for segment in group_info["closed_segments"]: - if group_info["fsm_name"] is None: - if group_name not in group_to_gt_segments: - group_to_gt_segments[group_name] = {} # segment start cycle to segment end cycle - group_to_gt_segments[group_name][segment["start"]] = segment["end"] - for i in range(segment["start"], segment["end"]): # really janky, I wonder if there's a better way to do this? - if group_info["fsm_name"] is not None: # FSM version - add_elem_to_callstack(fsm_timeline_map[i], group_component, group_name, False) - elif group_name in only_gt_groups: # A group that isn't managed by an FSM. In which case it has to be in both FSM and GT - add_elem_to_callstack(fsm_timeline_map[i], group_component, group_name, False) - add_elem_to_callstack(timeline_map[i], group_component, group_name, False) - else: # The ground truth info about a group managed by an FSM. - add_elem_to_callstack(timeline_map[i], group_component, group_name, False) - - trace = order_trace(main_component, cells_map, timeline_map) - fsm_trace = order_trace(main_component, cells_map, fsm_timeline_map) - - return trace, fsm_trace, len(timeline_map) - -""" -Writes a flame graph counting the number of times a group was active to `frequency_flame_out`. -""" -def create_frequency_flame_graph(main_component, trace, total_cycles, frequency_flame_out): - frequency_stacks = {} - stack_last_cycle = "" - for i in range(total_cycles): - current_stack = "" - if i in trace and len(trace[i]) != 0: - current_stack = ";".join(map(lambda x : x.flame_stack_string(main_component), trace[i])) - if stack_last_cycle != current_stack and stack_last_cycle.count(";") <= current_stack.count(";"): # We activated a different group, or invoked a different component! - if current_stack not in frequency_stacks: - frequency_stacks[current_stack] = 0 - frequency_stacks[current_stack] += 1 - stack_last_cycle = current_stack - - write_flame_graph(frequency_flame_out, frequency_stacks) - -""" -Returns a representation of how many cycles each stack combination was active for. -""" -def compute_flame_stacks(trace, main_component, total_cycles): - stacks = {} - component_stacks = {} - for i in trace: - stack = ";".join(map(lambda x : x.flame_stack_string(main_component), trace[i])) - # FIXME: really should separate out component stack - component_stack = ";".join(map(lambda x : x.component_flame_stack_string(main_component), trace[i])) - if stack not in stacks: - stacks[stack] = 0 - if component_stack not in component_stacks: - component_stacks[component_stack] = 0 - stacks[stack] += 1 - component_stacks[component_stack] += 1 - component_stacks[main_component] = total_cycles - len(trace) - return stacks, component_stacks - -""" -Constructs and writes flame graphs. -""" -def create_flame_graph(main_component, trace, fsm_trace, num_cycles, flame_out, fsm_flame_out, component_out, fsm_component_out): - stacks, component_stacks = compute_flame_stacks(trace, main_component, num_cycles) - write_flame_graph(flame_out, stacks) - write_flame_graph(component_out, component_stacks) - fsm_stacks, fsm_component_stacks = compute_flame_stacks(fsm_trace, main_component, num_cycles) - write_flame_graph(fsm_flame_out, fsm_stacks) - write_flame_graph(fsm_component_out, fsm_component_stacks) - -""" -Creates the JSON timeline representation. -""" -def create_timeline_stacks(trace, main_component): - events = [] - currently_active = {} # group name to beginning traceEvent entry (so end event can copy) - ts_multiplier = 100 # some arbitrary number to multiply by so that it's easier to see in the viewer - cell_to_stackframe_info = {main_component : (2, 1)} # (stack_number, parent_stack_number) - stack_number_acc = 3 # To guarantee that we get unique stack numbers when we need a new one - - cell_to_stackframe_info["MAIN"] = (1, None) - cell_to_stackframe_info["TOP.toplevel"] = (2, 1) - - for i in trace: - active_this_cycle = set() - # Start from the bottom up. Parent is the previous stack! - parent = "MAIN" - for elem in trace[i]: - # we want an entry for the cell and the group, if the stack entry has a group in it. - # cell - cell_name = elem.cell_fullname - active_this_cycle.add(cell_name) - if cell_name not in currently_active: # first cycle of the cell. - # get the stackframe - if cell_name not in cell_to_stackframe_info: - (parent_stackframe, _) = cell_to_stackframe_info[parent] # the parent better have been registered by now - cell_to_stackframe_info[cell_name] = (stack_number_acc, parent_stackframe) - stack_number_acc += 1 - (cell_stackframe, _) = cell_to_stackframe_info[cell_name] - # add start event of this cell - start_event = {"name": cell_name.split(".")[-1], "cat": "cell", "ph": "B", "pid" : 1, "tid": 1, "ts": i * ts_multiplier, "sf" : cell_stackframe} - events.append(start_event) - currently_active[cell_name] = start_event - # add a group if one is active - group_name = elem.get_active_group() - if group_name is not None: - active_this_cycle.add(group_name) - if group_name not in currently_active: - # get the stackframe - if group_name not in cell_to_stackframe_info: - cell_to_stackframe_info[group_name] = (stack_number_acc, cell_stackframe) # parent of the group is the cell - stack_number_acc += 1 - (group_stackframe, _) = cell_to_stackframe_info[group_name] - # add start event of this group - start_event = {"name": group_name.split(".")[-1], "cat": "group", "ph": "B", "pid" : 1, "tid": 1, "ts": i * ts_multiplier, "sf" : group_stackframe} - events.append(start_event) - currently_active[group_name] = start_event - parent = group_name # the next cell's parent will be this group. - # Any element that was previously active but not active this cycle need to end - for non_active_group in set(currently_active.keys()).difference(active_this_cycle): - end_event = currently_active[non_active_group].copy() - del currently_active[non_active_group] - end_event["ts"] = (i) * ts_multiplier - 1 - end_event["ph"] = "E" - events.append(end_event) - # postprocess - add end events for all events still active by the end - for event in currently_active: - end_event = currently_active[event].copy() - end_event["ts"] = (len(trace)) * ts_multiplier - 1 # only difference w the above - end_event["ph"] = "E" - events.append(end_event) - - # "stackFrames" field of the Trace Format JSON - stacks = {} - stack_category = "C" - for cell in cell_to_stackframe_info: - stack_id, parent_stack_id = cell_to_stackframe_info[cell] - if parent_stack_id is None: - stacks[stack_id] = {"name" : "MAIN", "category": stack_category} - else: - stacks[stack_id] = {"name" : cell, "parent": parent_stack_id, "category" : stack_category} - - return { "traceEvents": events, "stackFrames": stacks } - -""" -Wrapper function for constructing and writing a timeline representation -""" -def create_timeline_json(trace, fsm_trace, main_component, timeline_out, fsm_timeline_out): - timeline_json_data = create_timeline_stacks(trace, main_component) - with open(timeline_out, "w", encoding="utf-8") as timeline_file: - timeline_file.write(json.dumps(timeline_json_data, indent=4)) - fsm_timeline_json_data = create_timeline_stacks(fsm_trace, main_component) - with open(fsm_timeline_out, "w", encoding="utf-8") as fsm_timeline_file: - fsm_timeline_file.write(json.dumps(fsm_timeline_json_data, indent=4)) - -""" -Helper function to output the *.folded file for flame graphs. -""" -def write_flame_graph(flame_out, stacks): - with open(flame_out, "w") as f: - for stack in sorted(stacks, key=lambda k : len(k)): # main needs to come first for flame graph script to not make two boxes for main? - f.write(f"{stack} {stacks[stack]}\n") - -""" -Helper function to process the cells_json input. -""" -def build_cells_map(json_file): - cell_json = json.load(open(json_file)) - cells_map = {} - for component_entry in cell_json: - inner_cells_map = {} - for cell_entry in component_entry["cell_info"]: - inner_cells_map[cell_entry["cell_name"]] = cell_entry["component_name"] - cells_map[component_entry["component"]] = inner_cells_map - return cells_map - -def main(profiler_dump_file, cells_json, timeline_out, fsm_timeline_out, flame_out, fsm_flame_out, frequency_flame_out, component_out, fsm_component_out): - profiled_info = json.load(open(profiler_dump_file, "r")) - fsm_groups, all_groups = get_fsm_groups(profiled_info) - # This cells_map is different from the one in parse-vcd.py - cells_map = build_cells_map(cells_json) - summary = list(filter(lambda x : x["name"] == "TOTAL", profiled_info))[0] - main_component = summary["main_full_path"] - trace, fsm_trace, num_cycles = create_trace(profiled_info, main_component, cells_map, fsm_groups, all_groups) - create_flame_graph(main_component, trace, fsm_trace, num_cycles, flame_out, fsm_flame_out, component_out, fsm_component_out) - create_timeline_json(trace, fsm_trace, main_component, timeline_out, fsm_timeline_out) - create_frequency_flame_graph(main_component, trace, num_cycles, frequency_flame_out) - -if __name__ == "__main__": - if len(sys.argv) > 9: - profiler_dump_json = sys.argv[1] - cells_json = sys.argv[2] - timeline_out = sys.argv[3] - fsm_timeline_out = sys.argv[4] - flame_out = sys.argv[5] - fsm_flame_out = sys.argv[6] - frequency_flame_out = sys.argv[7] - component_flame_out = sys.argv[8] - fsm_component_flame_out = sys.argv[9] - main(profiler_dump_json, cells_json, timeline_out, fsm_timeline_out, flame_out, fsm_flame_out, frequency_flame_out, component_flame_out, fsm_component_flame_out) - else: - args_desc = [ - "PROFILER_JSON", - "CELLS_JSON", - "TIMELINE_VIEW_JSON", - "FSM_TIMELINE_VIEW_JSON", - "FLAME_GRAPH_FOLDED", - "FSM_FLAME_GRAPH_FOLDED", - "FREQUENCY_FLAME_GRAPH_FOLDED", - "COMPONENT_FOLDED", - "FSM_COMPONENT_FOLDED" - ] - print(f"Usage: {sys.argv[0]} {' '.join(args_desc)}") - sys.exit(-1) diff --git a/tools/profiler/create-visuals.sh b/tools/profiler/create-visuals.sh new file mode 100644 index 0000000000..61e36559d6 --- /dev/null +++ b/tools/profiler/create-visuals.sh @@ -0,0 +1,30 @@ +# Utility script for fud2 to produce flame graphs from produced .folded files + +if [ $# -lt 4 ]; then + echo "USAGE: bash $0 FLAME_GRAPH_SCRIPT DATA_DIR REPR_IN REPR_OUT" # the last two arguments are mainly for fud2's need for a defined input and output. + exit +fi + +SCRIPT_DIR=$( cd $( dirname $0 ) && pwd ) + +FLAME_GRAPH_SCRIPT=$1 +DATA_DIR=$2 +REPR_IN=$3 +REPR_OUT=$4 + +TREES_PDF_DIR=${DATA_DIR}-png +for f in $( ls ${DATA_DIR} | grep dot$ ); do + dot -Tpng ${DATA_DIR}/${f} > ${DATA_DIR}/${f}.png +done + +for folded in $( ls ${DATA_DIR}/*.folded ); do + base_name=$( echo "${folded}" | rev | cut -d. -f2- | rev ) + if [[ "${base_name}" == *"scaled"* ]]; then + ${FLAME_GRAPH_SCRIPT} --countname="cycles" ${folded} > ${base_name}-original.svg + python3 ${SCRIPT_DIR}/adjust-scaled-flame-svg.py ${base_name}-original.svg > ${base_name}.svg + else + ${FLAME_GRAPH_SCRIPT} --countname="cycles" ${folded} > ${base_name}.svg + fi +done + +${FLAME_GRAPH_SCRIPT} ${REPR_IN} > ${REPR_OUT} diff --git a/tools/profiler/parse-vcd.py b/tools/profiler/parse-vcd.py deleted file mode 100644 index 8c2d79d7a2..0000000000 --- a/tools/profiler/parse-vcd.py +++ /dev/null @@ -1,392 +0,0 @@ -import csv -import sys -import json -import vcdvcd - -def remove_size_from_name(name: str) -> str: - """ changes e.g. "state[2:0]" to "state" """ - return name.split('[')[0] - -class ProfilingInfo: - def __init__(self, name, component, fsm_name=None, fsm_values=None, tdcc_group_name=None, is_cell=False): - self.name = name - self.fsm_name = fsm_name - self.fsm_values = list(sorted(fsm_values)) if fsm_values is not None else None - self.total_cycles = 0 - self.closed_segments = [] # Segments will be (start_time, end_time) - self.current_segment = None - self.tdcc_group = tdcc_group_name - self.component = component - self.is_cell = is_cell - - def __repr__ (self): - segments_str = "" - for segment in self.closed_segments: - if (segments_str != ""): - segments_str += ", " - segments_str += f"[{segment['start']}, {segment['end']})" - if self.fsm_name is not None: - header = (f"[FSM] Group {self.name}:\n" + - f"\tFSM name: {self.fsm_name}\n" + - f"\tFSM state ids: {self.fsm_values}\n" - ) - elif self.component is None: - header = f"[CMP] Group {self.name}:\n" - else: - header = f"[GT] Group {self.name}:\n" - - return (header + - f"\tTotal cycles: {self.total_cycles}\n" + - f"\t# of times active: {len(self.closed_segments)}\n" + - f"\tSegments: {segments_str}\n" - ) - - def is_active(self): - return self.current_segment is not None - - def start_clock_cycle(self): - if self.current_segment is None: - return -1 - else: - return self.current_segment["start"] - - def compute_average_cycles(self): - if len(self.closed_segments) == 0: - return 0 - else: - return round(self.total_cycles / len(self.closed_segments), 2) - - def emit_csv_data(self): - name = self.name - if self.fsm_name is not None: - name += "[FSM]" - if self.component is None: - name += "[CMP]" - return {"name": name, - "total-cycles" : self.total_cycles, - "times-active" : len(self.closed_segments), - "avg" : self.compute_average_cycles()} - - def summary(self): - if self.fsm_name is None: - header = "[GT] " - else: - header = "[FSM]" - return (f"{header} Group {self.name} Summary:\n" + - f"\tTotal cycles: {self.total_cycles}\n" + - f"\t# of times active: {len(self.closed_segments)}\n" + - f"\tAvg runtime: {self.compute_average_cycles()}\n" - ) - - def start_new_segment(self, curr_clock_cycle): - if self.current_segment is None: - self.current_segment = {"start": curr_clock_cycle, "end": -1} - else: - print(f"Error! The group {self.name} is starting a new segment while the current segment is not closed.") - print(f"Current segment: {self.current_segment}") - sys.exit(1) - - def end_current_segment(self, curr_clock_cycle): - if self.current_segment is not None and self.current_segment["end"] == -1: # ignore cases where done is high forever - self.current_segment["end"] = curr_clock_cycle - self.closed_segments.append(self.current_segment) - self.total_cycles += curr_clock_cycle - self.current_segment["start"] - self.current_segment = None # Reset current segment - -class VCDConverter(vcdvcd.StreamParserCallbacks): - - def __init__(self, fsms, tdcc_groups, fsm_group_maps, main_component, cells): - super().__init__() - self.main_component = main_component - self.fsms = fsms - self.single_enable_names = set() - # Recording the first cycle when the TDCC group became active - self.tdcc_group_active_cycle = {tdcc_group_name : -1 for tdcc_group_name in tdcc_groups} - # Map from a TDCC group to all FSMs that depend on it. maybe a 1:1 mapping - self.tdcc_group_to_dep_fsms = tdcc_groups - # Group name --> ProfilingInfo object - self.profiling_info = {} - for group in fsm_group_maps: - # Differentiate FSM versions from ground truth versions - self.profiling_info[f"{group}FSM"] = ProfilingInfo(group, fsm_group_maps[group]["component"], fsm_group_maps[group]["fsm"], fsm_group_maps[group]["ids"], fsm_group_maps[group]["tdcc-group-name"]) - self.cells = set(cells.keys()) - for cell in cells: - self.profiling_info[cell] = ProfilingInfo(cell, cells[cell], is_cell=True) - # Map from timestamps [ns] to value change events that happened on that timestamp - self.timestamps_to_events = {} - - def enddefinitions(self, vcd, signals, cur_sig_vals): - # convert references to list and sort by name - refs = [(k, v) for k, v in vcd.references_to_ids.items()] - refs = sorted(refs, key=lambda e: e[0]) - names = [remove_size_from_name(e[0]) for e in refs] - signal_id_dict = {sid : [] for sid in vcd.references_to_ids.values()} # one id can map to multiple signal names since wires are connected - - clock_name = f"{self.main_component}.clk" - if clock_name not in names: - print("Can't find the clock? Exiting...") - sys.exit(1) - signal_id_dict[vcd.references_to_ids[clock_name]] = [clock_name] - - # get go and done for cells (the signals are exactly {cell}.go and {cell}.done) - for cell in self.cells: - cell_go = cell + ".go" - cell_done = cell + ".done" - if cell_go not in vcd.references_to_ids: - print(f"Not accounting for cell {cell} (probably combinational)") - continue - signal_id_dict[vcd.references_to_ids[cell_go]].append(cell_go) - signal_id_dict[vcd.references_to_ids[cell_done]].append(cell_done) - - for name, sid in refs: - # FIXME: We may want to optimize these nested for loops - for tdcc_group in self.tdcc_group_to_dep_fsms: - if name.startswith(f"{tdcc_group}_go.out["): - signal_id_dict[sid].append(name) - for fsm in self.fsms: - if name.startswith(f"{fsm}.out["): - signal_id_dict[sid].append(name) - if "_probe_out" in name: # instrumentation probes are "<group>__<component>_probe" - group_component_split = name.split("_probe_out")[0].split("__") - group_name = group_component_split[0] - self.single_enable_names.add(group_name) - self.profiling_info[group_name] = ProfilingInfo(group_name, group_component_split[1]) - signal_id_dict[sid].append(name) - - # don't need to check for signal ids that don't pertain to signals we're interested in - self.signal_id_to_names = {k:v for k,v in signal_id_dict.items() if len(v) > 0} - - # Stream processes the events recorded in the VCD and stores them in self.timestamps_to_events - # NOTE: Stream processing doesn't work because value changes that happen in the same timestamp - # are not processed at the same time. - # NOTE: when we reimplement this script, we probably want to separate this part from the - # clock cycle processing - def value( - self, - vcd, - time, - value, - identifier_code, - cur_sig_vals, - ): - # ignore all signals we don't care about - if identifier_code not in self.signal_id_to_names: - return - - signal_names = self.signal_id_to_names[identifier_code] - int_value = int(value, 2) - - if time not in self.timestamps_to_events: - self.timestamps_to_events[time] = [] - - for signal_name in signal_names: - event = {"signal": signal_name, "value": int_value} - self.timestamps_to_events[time].append(event) - - # Postprocess data mapping timestamps to events (signal changes) - # We have to postprocess instead of processing signals in a stream because - # signal changes that happen at the same time as a clock tick might be recorded - # *before* or *after* the clock change on the VCD file (hence why we can't process - # everything within a stream if we wanted to be precise) - def postprocess(self): - clock_name = f"{self.main_component}.clk" - clock_cycles = -1 - fsm_to_active_group = {fsm : None for fsm in self.fsms} - # current values of FSM registers. This is different from fsm_to_active_group since the TDCC group for the FSM - # may not be active (which means that no group managed by the FSM is active) - fsm_to_curr_value = {fsm: -1 for fsm in self.fsms} - started = False - for ts in self.timestamps_to_events: - events = self.timestamps_to_events[ts] - started = started or [x for x in events if x["signal"] == f"{self.main_component}.go" and x["value"] == 1] - if not started: - # Update fsm_to_curr_value for any FSM signals that got updated. We will start the events corresponding - # to those values once the TDCC group for the FSM starts. - # Realistically this will most likely only happen on the 0th cycle just to set the FSM value to 0, - # but trying to be extra safe here. - for event in filter(lambda e : "fsm" in e["signal"], events): - fsm = ".".join(event["signal"].split(".")[0:-1]) - if event["value"] in self.fsms[fsm]: - fsm_to_curr_value[fsm] = event["value"] - continue - # checking whether the timestamp has a rising edge (hacky) - if {"signal": clock_name, "value": 1} in events: - clock_cycles += 1 - # TDCC groups need to be recorded (before FSMs) for tracking FSM values - # (ex. if the FSM has value 0 but the TDCC group isn't active, then the group represented by the - # FSM's 0 value should not be considered as active) - for tdcc_event in filter(lambda e : "tdcc" in e["signal"] and "go" in e["signal"], events): - tdcc_group = "_".join(tdcc_event["signal"].split("_")[0:-1]) - if self.tdcc_group_active_cycle[tdcc_group] == -1 and tdcc_event["value"] == 1: # value changed to 1 - self.tdcc_group_active_cycle[tdcc_group] = clock_cycles - for fsm in self.tdcc_group_to_dep_fsms[tdcc_group]: - value = fsm_to_curr_value[fsm] - if value != -1: - if value not in self.fsms[fsm]: - continue - next_group = f"{self.fsms[fsm][value]}FSM" - fsm_to_active_group[fsm] = next_group - self.profiling_info[next_group].start_new_segment(clock_cycles) - elif self.tdcc_group_active_cycle[tdcc_group] > -1 and tdcc_event["value"] == 0: # tdcc group that was active's signal turned to 0 - self.tdcc_group_active_cycle[tdcc_group] = -1 - for event in events: - signal_name = event["signal"] - value = event["value"] - if "tdcc" in signal_name and "go" in signal_name: # skip all tdcc events since we've already processed them - continue - if signal_name.endswith(".go") and value == 1: # cells have .go and .done - cell = signal_name.split(".go")[0] - self.profiling_info[cell].start_new_segment(clock_cycles) - if signal_name.endswith(".done") and value == 1: # cells have .go and .done - cell = signal_name.split(".done")[0] - self.profiling_info[cell].end_current_segment(clock_cycles) - if "_probe_out" in signal_name and value == 1: # instrumented group started being active - group = signal_name.split("_probe_out")[0].split("__")[0] - self.profiling_info[group].start_new_segment(clock_cycles) - elif "_probe_out" in signal_name and value == 0: # instrumented group stopped being active - group = signal_name.split("_probe_out")[0].split("__")[0] - self.profiling_info[group].end_current_segment(clock_cycles) - elif "fsm" in signal_name: - fsm = ".".join(signal_name.split(".")[0:-1]) - fsm_to_curr_value[fsm] = value - # Workarounds because the value 0 may not correspond to a group - if fsm_to_active_group[fsm] is not None: - prev_group = fsm_to_active_group[fsm] # getting the "FSM" variant of the group - self.profiling_info[prev_group].end_current_segment(clock_cycles) - if value in self.fsms[fsm]: - next_group = f"{self.fsms[fsm][value]}FSM" # getting the "FSM" variant of the group - tdcc_group_active_cycle = self.tdcc_group_active_cycle[self.profiling_info[next_group].tdcc_group] - if tdcc_group_active_cycle == -1: # If the TDCC group is not active, then no segments should start - continue - fsm_to_active_group[fsm] = next_group - self.profiling_info[next_group].start_new_segment(clock_cycles) - - self.clock_cycles = clock_cycles - -# Generates a list of all of the components to potential cell names -# `prefix` is the cell's "path" (ex. for a cell "my_cell" defined in "main", the prefix would be "TOP.toplevel.main") -# The initial value of curr_component should be the top level/main component -def build_components_to_cells(prefix, curr_component, cells_to_components, components_to_cells): - for (cell, cell_component) in cells_to_components[curr_component].items(): - if cell_component not in components_to_cells: - components_to_cells[cell_component] = [f"{prefix}.{cell}"] - else: - components_to_cells[cell_component].append(f"{prefix}.{cell}") - build_components_to_cells(prefix + f".{cell}", cell_component, cells_to_components, components_to_cells) - -# Reads json generated by component-cells backend to produce a mapping from all components -# to cell names they could have. -def read_component_cell_names_json(json_file): - cell_json = json.load(open(json_file)) - # For each component, contains a map from each cell name to its corresponding component - # component name --> { cell name --> component name} - cells_to_components = {} - main_component = "" - for curr_component_entry in cell_json: - cell_map = {} # mapping cell names to component names for all cells in the current component - if curr_component_entry["is_main_component"]: - main_component = curr_component_entry["component"] - for cell_info in curr_component_entry["cell_info"]: - cell_map[cell_info["cell_name"]] = cell_info["component_name"] - cells_to_components[curr_component_entry["component"]] = cell_map - full_main_component = f"TOP.toplevel.{main_component}" - components_to_cells = {main_component : [full_main_component]} # come up with a better name for this - build_components_to_cells(full_main_component, main_component, cells_to_components, components_to_cells) - return full_main_component, components_to_cells - -# Reads json generated by TDCC (via dump-fsm-json option) to produce initial group information -def remap_tdcc_json(tdcc_json_file, components_to_cells): - profiling_infos = json.load(open(tdcc_json_file)) - cells_to_components = {} # go and done info are needed for cells. cell --> component name - tdcc_groups = {} # TDCC-generated groups that manage control flow using FSMs. maps to all fsms that map to the tdcc group - fsm_group_maps = {} # fsm-managed groups info (fsm register, TDCC group that manages fsm, id of group within fsm) - fsms = {} # Remapping of JSON data for easy access - for profiling_info in profiling_infos: - if "Fsm" in profiling_info: - fsm = profiling_info["Fsm"] - # create entries for all possible cells of component - for cell in components_to_cells[fsm["component"]]: - fsm_name = cell + "." + fsm["fsm"] - fsms[fsm_name] = {} - for state in fsm["states"]: - group_name = cell + "." + state["group"] - fsms[fsm_name][state["id"]] = group_name - tdcc_group = cell + "." + fsm["group"] - if group_name not in fsm_group_maps: - fsm_group_maps[group_name] = {"fsm": fsm_name, "tdcc-group-name": tdcc_group, "ids": [state["id"]], "component": fsm["component"]} - if tdcc_group not in tdcc_groups: # Keep track of the TDCC group to figure out when first group starts - tdcc_groups[tdcc_group] = set() - tdcc_groups[tdcc_group].add(fsm_name) - else: - fsm_group_maps[group_name]["ids"].append(state["id"]) - for component in components_to_cells: - for cell in components_to_cells[component]: - cells_to_components[cell] = component - - return fsms, tdcc_groups, fsm_group_maps, cells_to_components - -def output_result(out_csv, dump_out_json, converter): - print(f"Total clock cycles: {converter.clock_cycles}") - print("=====SUMMARY=====") - print() - groups_to_emit = list(filter(lambda group : not group.name.startswith("tdcc") and not group.name.endswith("END"), converter.profiling_info.values())) - groups_to_emit.sort(key=lambda x : x.name) # to preserve stability - groups_to_emit.sort(key=lambda x : x.total_cycles, reverse=True) - csv_acc = [] - dump_json_acc = [] - for group_info in groups_to_emit: - csv_acc.append(group_info.emit_csv_data()) - dump_json_acc.append(group_info.__dict__) - print(group_info.summary()) - print("=====DUMP=====") - print() - for group_info in groups_to_emit: - print(group_info) - # Add total cycles for visualizer script (probably want to do this in a neater fashion in the future) - dump_json_acc.append({"name": "TOTAL", "total_cycles": converter.clock_cycles, "main_full_path": converter.main_component}) - # emit a json for visualizer script - print(f"Writing dump JSON to {dump_out_json}") - with open(dump_out_json, "w", encoding="utf-8") as dump_file: - dump_file.write(json.dumps(dump_json_acc, indent=4)) - # emitting a CSV file for easier eyeballing - print(f"Writing summary to {out_csv}") - csv_keys = ["name", "total-cycles", "times-active", "avg"] - csv_acc.append({ "name": "TOTAL", "total-cycles": converter.clock_cycles, "times-active": "-", "avg": "-"}) - if (out_csv == "STDOUT"): - writer = csv.DictWriter(sys.stdout, csv_keys, lineterminator="\n") - else: - writer = csv.DictWriter(open(out_csv, "w"), csv_keys, lineterminator="\n") - writer.writeheader() - writer.writerows(csv_acc) - -def main(vcd_filename, tdcc_json_file, cells_json_file, out_csv, dump_out_json): - main_component, components_to_cells = read_component_cell_names_json(cells_json_file) - fsms, tdcc_group_names, fsm_group_maps, cells = remap_tdcc_json(tdcc_json_file, components_to_cells) - converter = VCDConverter(fsms, tdcc_group_names, fsm_group_maps, main_component, cells) - vcdvcd.VCDVCD(vcd_filename, callbacks=converter, store_tvs=False) - converter.postprocess() - output_result(out_csv, dump_out_json, converter) - -if __name__ == "__main__": - if len(sys.argv) > 5: - vcd_filename = sys.argv[1] - fsm_json = sys.argv[2] - cells_json = sys.argv[3] - out_csv = sys.argv[4] - dump_out_json = sys.argv[5] - main(vcd_filename, fsm_json, cells_json, out_csv, dump_out_json) - else: - args_desc = [ - "VCD_FILE", - "TDCC_JSON", - "CELLS_JSON", - "SUMMARY_OUT_CSV", - "DUMP_OUT_JSON" - ] - print(f"Usage: {sys.argv[0]} {' '.join(args_desc)}") - print("TDCC_JSON: Run Calyx with `tdcc:dump-fsm-json` option") - print("CELLS_JSON: Run the `component_cells` tool") - print("GROUPS_JSON: Run the `component_groups` tool") - print("If SUMMARY_OUT_CSV is STDOUT, then summary CSV will be printed to stdout") - print("DUMP_OUT_JSON: output json file for group-specific") - sys.exit(-1) diff --git a/tools/profiler/profiler-process.py b/tools/profiler/profiler-process.py new file mode 100644 index 0000000000..1554aa5019 --- /dev/null +++ b/tools/profiler/profiler-process.py @@ -0,0 +1,561 @@ +import copy +from datetime import datetime +import json +import os +import sys +import vcdvcd + +DELIMITER = "___" +INVISIBLE = "gray" +ACTIVE_PRIMITIVE_COLOR="lemonchiffon" +TREE_PICTURE_LIMIT=300 +SCALED_FLAME_MULTIPLIER=1000 + +def remove_size_from_name(name: str) -> str: + """ changes e.g. "state[2:0]" to "state" """ + return name.split('[')[0] + +def create_cycle_trace(info_this_cycle, cells_to_components, main_component, include_primitives): + stacks_this_cycle = [] + parents = set() # keeping track of entities that are parents of other entities + i_mapping = {} # each unique group inv mapping to its stack. the "group" should be the last item on each stack + i_mapping[main_component] = [main_component.split(".")[-1]] + cell_worklist = [main_component] + while len(cell_worklist) > 0: + current_cell = cell_worklist.pop() + covered_units_in_component = set() # collect all of the units we've covered. + # catch all active units that are groups in this component. + units_to_cover = info_this_cycle["group-active"][current_cell] if current_cell in info_this_cycle["group-active"] else set() + structural_enables = info_this_cycle["structural-enable"][current_cell] if current_cell in info_this_cycle["structural-enable"] else set() + primitive_enables = info_this_cycle["primitive-enable"][current_cell] if current_cell in info_this_cycle["primitive-enable"] else set() + cell_invokes = info_this_cycle["cell-invoke"][current_cell] if current_cell in info_this_cycle["cell-invoke"] else set() + # find all enables from control. these are all units that either (1) don't have any maps in call_stack_probes_info, or (2) have no active parent calls in call_stack_probes_info + for active_unit in units_to_cover: + shortname = active_unit.split(".")[-1] + if active_unit not in structural_enables: + i_mapping[active_unit] = i_mapping[current_cell] + [shortname] + parents.add(current_cell) + covered_units_in_component.add(active_unit) + # get all of the other active units + while len(covered_units_in_component) < len(units_to_cover): + # loop through all other elements to figure out parent child info + for active_unit in units_to_cover: + shortname = active_unit.split(".")[-1] + if active_unit in i_mapping: + continue + for parent_group in structural_enables[active_unit]: + parent = f"{current_cell}.{parent_group}" + if parent in i_mapping: + i_mapping[active_unit] = i_mapping[parent] + [shortname] + covered_units_in_component.add(active_unit) + parents.add(parent) + # get primitives if requested. + if include_primitives: + for primitive_parent_group in primitive_enables: + for primitive_name in primitive_enables[primitive_parent_group]: + primitive_parent = f"{current_cell}.{primitive_parent_group}" + primitive_shortname = primitive_name.split(".")[-1] + i_mapping[primitive_name] = i_mapping[primitive_parent] + [f"{primitive_shortname} (primitive)"] + parents.add(primitive_parent) + # by this point, we should have covered all groups in the same component... + # now we need to construct stacks for any cells that are called from a group in the current component. + for cell_invoker_group in cell_invokes: + for invoked_cell in cell_invokes[cell_invoker_group]: + if invoked_cell in info_this_cycle["cell-active"]: + cell_shortname = invoked_cell.split(".")[-1] + cell_worklist.append(invoked_cell) + cell_component = cells_to_components[invoked_cell] + parent = f"{current_cell}.{cell_invoker_group}" + i_mapping[invoked_cell] = i_mapping[parent] + [f"{cell_shortname} [{cell_component}]"] + parents.add(parent) + # Only retain paths that lead to leaf nodes. + for elem in i_mapping: + if elem not in parents: + stacks_this_cycle.append(i_mapping[elem]) + + return stacks_this_cycle + + +class VCDConverter(vcdvcd.StreamParserCallbacks): + def __init__(self, main_component, cells_to_components): + super().__init__() + self.main_component = main_component + self.cells_to_components = cells_to_components + # Documenting other fields for reference + # signal_id_to_names + self.timestamps_to_events = {} + + def enddefinitions(self, vcd, signals, cur_sig_vals): + # convert references to list and sort by name + refs = [(k, v) for k, v in vcd.references_to_ids.items()] + refs = sorted(refs, key=lambda e: e[0]) + names = [remove_size_from_name(e[0]) for e in refs] + signal_id_dict = {sid : [] for sid in vcd.references_to_ids.values()} # one id can map to multiple signal names since wires are connected + + clock_name = f"{self.main_component}.clk" + if clock_name not in names: + print("Can't find the clock? Exiting...") + sys.exit(1) + signal_id_dict[vcd.references_to_ids[clock_name]] = [clock_name] + + # get go and done for cells (the signals are exactly {cell}.go and {cell}.done) + for cell in self.cells_to_components.keys(): + cell_go = cell + ".go" + cell_done = cell + ".done" + if cell_go not in vcd.references_to_ids: + print(f"Not accounting for cell {cell} (probably combinational)") + continue + signal_id_dict[vcd.references_to_ids[cell_go]].append(cell_go) + signal_id_dict[vcd.references_to_ids[cell_done]].append(cell_done) + + for name, sid in refs: + if "probe_out" in name: + signal_id_dict[sid].append(name) + + # don't need to check for signal ids that don't pertain to signals we're interested in + self.signal_id_to_names = {k:v for k,v in signal_id_dict.items() if len(v) > 0} + + def value(self, vcd, time, value, identifier_code, cur_sig_vals): + # ignore all signals we don't care about + if identifier_code not in self.signal_id_to_names: + return + + signal_names = self.signal_id_to_names[identifier_code] + int_value = int(value, 2) + + for signal_name in signal_names: + if signal_name == f"{self.main_component}.clk" and int_value == 0: # ignore falling edges + continue + event = {"signal": signal_name, "value": int_value} + if time not in self.timestamps_to_events: + self.timestamps_to_events[time] = [event] + else: + self.timestamps_to_events[time].append(event) + + # Postprocess data mapping timestamps to events (signal changes) + # We have to postprocess instead of processing signals in a stream because + # signal changes that happen at the same time as a clock tick might be recorded + # *before* or *after* the clock change on the VCD file (hence why we can't process + # everything within a stream if we wanted to be precise) + def postprocess(self): + clock_name = f"{self.main_component}.clk" + clock_cycles = -1 # will be 0 on the 0th cycle + started = False + cell_active = set() + group_active = set() + structural_enable_active = set() + cell_enable_active = set() + primitive_enable = set() + + probe_labels_to_sets = {"group_probe_out": group_active, "se_probe_out": structural_enable_active, "cell_probe_out": cell_enable_active, "primitive_probe_out" : primitive_enable} + + self.trace = {} # cycle number --> set of stacks + + for ts in self.timestamps_to_events: + events = self.timestamps_to_events[ts] + started = started or [x for x in events if x["signal"] == f"{self.main_component}.go" and x["value"] == 1] + if not started: # only start counting when main component is on. + continue + # checking whether the timestamp has a rising edge + if {"signal": clock_name, "value": 1} in events: + clock_cycles += 1 + # Recording the data organization for every kind of probe so I don't forget. () is a set. + # groups-active: cell --> (active groups) + # cell-active: (cells) + # structural-enable: cell --> { child --> (parents) } + # cell-invoke: parent_cell --> { parent --> (cells) } # FIXME: subject to change. + # primitive-enable: cell --> { parent --> (primitives) } + info_this_cycle = {"group-active" : {}, "cell-active": set(), "structural-enable": {}, "cell-invoke": {}, "primitive-enable": {}} + for event in events: + # check probe and cell signals to update currently active entities. + signal_name = event["signal"] + value = event["value"] + if signal_name.endswith(".go") and value == 1: # cells have .go and .done + cell = signal_name.split(".go")[0] + cell_active.add(cell) + if signal_name.endswith(".done") and value == 1: + cell = signal_name.split(".done")[0] + cell_active.remove(cell) + # process all probes. + for probe_label in probe_labels_to_sets: + cutoff = f"_{probe_label}" + if cutoff in signal_name: + # record cell name instead of component name. + split = signal_name.split(cutoff)[0].split(DELIMITER)[:-1] + cell_name = ".".join(signal_name.split(cutoff)[0].split(".")[:-1]) + split.append(cell_name) + probe_info = tuple(split) + if value == 1: + probe_labels_to_sets[probe_label].add(probe_info) + elif value == 0: + probe_labels_to_sets[probe_label].remove(probe_info) + # add all probe information + info_this_cycle["cell-active"] = cell_active.copy() + for (group, cell_name) in group_active: + if cell_name in info_this_cycle["group-active"]: + info_this_cycle["group-active"][cell_name].add(group) + else: + info_this_cycle["group-active"][cell_name] = {group} + for (child_group, parent_group, cell_name) in structural_enable_active: + if cell_name not in info_this_cycle["structural-enable"]: + info_this_cycle["structural-enable"][cell_name] = {child_group: {parent_group}} + elif child_group not in info_this_cycle["structural-enable"][cell_name]: + info_this_cycle["structural-enable"][cell_name][child_group] = {parent_group} + else: + info_this_cycle["structural-enable"][cell_name][child_group].add(parent_group) + for (cell_name, parent_group, parent_cell_name) in cell_enable_active: + if parent_cell_name not in info_this_cycle["cell-invoke"]: + info_this_cycle["cell-invoke"][parent_cell_name] = {parent_group : {cell_name}} + elif parent_group not in info_this_cycle["cell-invoke"][parent_cell_name]: + info_this_cycle["cell-invoke"][parent_cell_name][parent_group] = {cell_name} + else: + info_this_cycle["cell-invoke"][parent_cell_name][parent_group].add(cell_name) + for (primitive_name, parent_group, cell_name) in primitive_enable: + if cell_name not in info_this_cycle["primitive-enable"]: + info_this_cycle["primitive-enable"][cell_name] = {parent_group: {primitive_name}} + elif parent_group not in info_this_cycle["primitive-enable"][cell_name]: + info_this_cycle["primitive-enable"][cell_name][parent_group] = {primitive_name} + else: + info_this_cycle["primitive-enable"][cell_name][parent_group].add(primitive_name) + self.trace[clock_cycles] = create_cycle_trace(info_this_cycle, self.cells_to_components, self.main_component, True) # True to track primitives + + self.clock_cycles = clock_cycles + +# Generates a list of all of the components to potential cell names +# `prefix` is the cell's "path" (ex. for a cell "my_cell" defined in "main", the prefix would be "TOP.toplevel.main") +# The initial value of curr_component should be the top level/main component +def build_components_to_cells(prefix, curr_component, cells_to_components, components_to_cells): + for (cell, cell_component) in cells_to_components[curr_component].items(): + if cell_component not in components_to_cells: + components_to_cells[cell_component] = [f"{prefix}.{cell}"] + else: + components_to_cells[cell_component].append(f"{prefix}.{cell}") + build_components_to_cells(prefix + f".{cell}", cell_component, cells_to_components, components_to_cells) + +# Reads json generated by component-cells backend to produce a mapping from all components +# to cell names they could have. +def read_component_cell_names_json(json_file): + cell_json = json.load(open(json_file)) + # For each component, contains a map from each cell name to its corresponding component + # component name --> { cell name --> component name } + cells_to_components = {} + main_component = "" + for curr_component_entry in cell_json: + cell_map = {} # mapping cell names to component names for all cells in the current component + if curr_component_entry["is_main_component"]: + main_component = curr_component_entry["component"] + for cell_info in curr_component_entry["cell_info"]: + cell_map[cell_info["cell_name"]] = cell_info["component_name"] + cells_to_components[curr_component_entry["component"]] = cell_map + full_main_component = f"TOP.toplevel.{main_component}" + components_to_cells = {main_component : [full_main_component]} # come up with a better name for this + build_components_to_cells(full_main_component, main_component, cells_to_components, components_to_cells) + full_cell_names_to_components = {} + for component in components_to_cells: + for cell in components_to_cells[component]: + full_cell_names_to_components[cell] = component + + return full_main_component, full_cell_names_to_components + +""" +Creates a tree that encapsulates all stacks that occur within the program. +""" +def create_tree(timeline_map): + node_id_acc = 0 + tree_dict = {} # node id --> node name + path_dict = {} # stack list string --> list of node ids + path_prefixes_dict = {} # stack list string --> list of node ids + stack_list = [] + # collect all of the stacks from the list. (i.e. "flatten" the timeline map values.) + for sl in timeline_map.values(): + for s in sl: + if s not in stack_list: + stack_list.append(s) + stack_list.sort(key=len) + for stack in stack_list: + stack_len = len(stack) + id_path_list = [] + prefix = "" + # obtain the longest prefix of the current stack. Everything after the prefix is a new stack element. + for i in range(1, stack_len+1): + attempted_prefix = ";".join(stack[0:stack_len-i]) + if attempted_prefix in path_prefixes_dict: + prefix = attempted_prefix + id_path_list = list(path_prefixes_dict[prefix]) + break + # create nodes + if prefix != "": + new_nodes = stack[stack_len - i:] + new_prefix = prefix + else: + new_nodes = stack + new_prefix = "" + for elem in new_nodes: + if new_prefix == "": + new_prefix = elem + else: + new_prefix += f";{elem}" + tree_dict[node_id_acc] = elem + id_path_list.append(node_id_acc) + path_prefixes_dict[new_prefix] = list(id_path_list) + node_id_acc += 1 + path_dict[new_prefix] = id_path_list + + return tree_dict, path_dict + +def create_tree_rankings(trace, tree_dict, path_dict, path_to_edges, all_edges, dot_out_dir): + stack_list_str_to_used_nodes = {} + stack_list_str_to_used_edges = {} + stack_list_str_to_cycles = {} + all_nodes = set(tree_dict.keys()) + + # accumulating counts + for i in trace: + stack_list_str = str(trace[i]) + if stack_list_str in stack_list_str_to_cycles: + stack_list_str_to_cycles[stack_list_str].append(i) + continue + stack_list_str_to_cycles[stack_list_str] = [i] + used_nodes = set() + used_edges = set() + + for stack in trace[i]: + stack_id = ";".join(stack) + for node_id in path_dict[stack_id]: + used_nodes.add(node_id) + for edge in path_to_edges[stack_id]: + used_edges.add(edge) + stack_list_str_to_used_nodes[stack_list_str] = used_nodes + stack_list_str_to_used_edges[stack_list_str] = used_edges + + sorted_stack_list_items = sorted(stack_list_str_to_cycles.items(), key=(lambda item : len(item[1])), reverse=True) + acc = 0 + rankings_out = open(os.path.join(dot_out_dir, "rankings.csv"), "w") + rankings_out.write("Rank,#Cycles,Cycles-list\n") + for (stack_list_str, cycles) in sorted_stack_list_items: + if acc == 5: + break + acc += 1 + # draw the tree + fpath = os.path.join(dot_out_dir, f"rank{acc}.dot") + with open(fpath, "w") as f: + f.write("digraph rank" + str(acc) + " {\n") + # declare nodes. + for node in all_nodes: + if node in stack_list_str_to_used_nodes[stack_list_str]: + f.write(f'\t{node} [label="{tree_dict[node]}"];\n') + else: + f.write(f'\t{node} [label="{tree_dict[node]}",color="{INVISIBLE}",fontcolor="{INVISIBLE}"];\n') + # write all edges. + for edge in all_edges: + if edge in stack_list_str_to_used_edges[stack_list_str]: + f.write(f'\t{edge} ; \n') + else: + f.write(f'\t{edge} [color="{INVISIBLE}"]; \n') + f.write("}") + + # should write to a txt file what + rankings_out.write(f"{acc},{len(cycles)},{';'.join(str(c) for c in cycles)}\n") + + +# one tree to summarize the entire execution. +def create_aggregate_tree(timeline_map, out_dir, tree_dict, path_dict): + path_to_edges, all_edges = create_edge_dict(path_dict) + + leaf_nodes_dict = {node_id: 0 for node_id in tree_dict} # how many times was this node a leaf? + edges_dict = {} # how many times was this edge active? + + for stack_list in timeline_map.values(): + edges_this_cycle = set() + leaves_this_cycle = set() + for stack in stack_list: + stack_id = ";".join(stack) + # record the leaf node. ignore all primitives as I think we care more about the group that called the primitive (up to debate) + leaf_node = path_dict[stack_id][-1] + if "primitive" in tree_dict[leaf_node]: + leaf_node = path_dict[stack_id][-2] + if leaf_node not in leaves_this_cycle: + leaf_nodes_dict[leaf_node] += 1 + leaves_this_cycle.add(leaf_node) + for edge in path_to_edges[stack_id]: + if edge not in edges_this_cycle: + if edge not in edges_dict: + edges_dict[edge] = 1 + else: + edges_dict[edge] += 1 + edges_this_cycle.add(edge) + + # write the tree + if not os.path.exists(out_dir): + os.mkdir(out_dir) + with open(os.path.join(out_dir, "aggregate.dot"), "w") as f: + f.write("digraph aggregate {\n") + # declare nodes + for node in leaf_nodes_dict: + if "primitive" in tree_dict[node]: + f.write(f'\t{node} [label="{tree_dict[node]}"];\n') + else: + f.write(f'\t{node} [label="{tree_dict[node]} ({leaf_nodes_dict[node]})"];\n') + # write edges with labels + for edge in edges_dict: + f.write(f'\t{edge} [label="{edges_dict[edge]}"]; \n') + f.write("}") + +def create_path_dot_str_dict(path_dict): + path_to_dot_str = {} # stack list string --> stack path representation on dot file. + + for path_id in path_dict: + path = path_dict[path_id] + path_acc = "" + for node_id in path[0:-1]: + path_acc += f'{node_id} -> ' + path_acc += f'{path[-1]}' + path_to_dot_str[path_id] = path_acc + + return path_to_dot_str + +def create_edge_dict(path_dict): + path_to_edges = {} # stack list string --> [edge string representation] + all_edges = set() + + for path_id in path_dict: + path = path_dict[path_id] + edge_set = [] + for i in range(len(path)-1): + edge = f"{path[i]} -> {path[i+1]}" + edge_set.append(edge) + all_edges.add(edge) + path_to_edges[path_id] = edge_set + + return path_to_edges, list(sorted(all_edges)) + +# create a tree where we divide cycles via par arms +def compute_scaled_flame(timeline_map): + stacks = {} + for i in timeline_map: + num_stacks = len(timeline_map[i]) + cycle_slice = round(1 / num_stacks, 3) + last_cycle_slice = 1 - (cycle_slice * (num_stacks - 1)) + acc = 0 + for stack_list in timeline_map[i]: + stack_id = ";".join(stack_list) + slice_to_add = cycle_slice if acc < num_stacks - 1 else last_cycle_slice + if stack_id not in stacks: + stacks[stack_id] = slice_to_add * SCALED_FLAME_MULTIPLIER + else: + stacks[stack_id] += slice_to_add * SCALED_FLAME_MULTIPLIER + acc += 1 + + return stacks + +def create_flame_groups(timeline_map, flame_out_file, flames_out_dir): + if not os.path.exists(flames_out_dir): + os.mkdir(flames_out_dir) + + # make flame graph folded file + stacks = {} # stack to number of cycles + for i in timeline_map: + for stack_list in timeline_map[i]: + stack_id = ";".join(stack_list) + if stack_id not in stacks: + stacks[stack_id] = 1 + else: + stacks[stack_id] += 1 + + with open(flame_out_file, "w") as flame_out: + for stack in stacks: + flame_out.write(f"{stack} {stacks[stack]}\n") + + scaled_stacks = compute_scaled_flame(timeline_map) + with open(os.path.join(flames_out_dir, "scaled-flame.folded"), "w") as div_flame_out: + for stack in scaled_stacks: + div_flame_out.write(f"{stack} {scaled_stacks[stack]}\n") + +def create_slideshow_dot(timeline_map, dot_out_dir, flame_out_file, flames_out_dir): + + if not os.path.exists(dot_out_dir): + os.mkdir(dot_out_dir) + + # probably wise to not have a billion dot files. + if len(timeline_map) > TREE_PICTURE_LIMIT: + print(f"Simulation exceeds {TREE_PICTURE_LIMIT} cycles, skipping trees...") + return + tree_dict, path_dict = create_tree(timeline_map) + path_to_edges, all_edges = create_edge_dict(path_dict) + + for i in timeline_map: + used_edges = {} + used_paths = set() + used_nodes = set() + all_nodes = set(tree_dict.keys()) + # figure out what nodes are used and what nodes aren't used + for stack in timeline_map[i]: + stack_id = ";".join(stack) + used_paths.add(stack_id) + for node_id in path_dict[stack_id]: + used_nodes.add(node_id) + for edge in path_to_edges[stack_id]: + if edge not in used_edges: + used_edges[edge] = 1 + else: + used_edges[edge] += 1 + + fpath = os.path.join(dot_out_dir, f"cycle{i}.dot") + with open(fpath, "w") as f: + f.write("digraph cycle" + str(i) + " {\n") + # declare nodes. + for node in all_nodes: + if node in used_nodes: + f.write(f'\t{node} [label="{tree_dict[node]}"];\n') + else: + f.write(f'\t{node} [label="{tree_dict[node]}",color="{INVISIBLE}",fontcolor="{INVISIBLE}"];\n') + # write all edges. + for edge in all_edges: + if edge in used_edges.keys(): + f.write(f'\t{edge} ; \n') + else: + f.write(f'\t{edge} [color="{INVISIBLE}"]; \n') + f.write("}") + +def main(vcd_filename, cells_json_file, out_dir, flame_out): + print(f"Start time: {datetime.now()}") + main_component, cells_to_components = read_component_cell_names_json(cells_json_file) + print(f"Start reading VCD: {datetime.now()}") + converter = VCDConverter(main_component, cells_to_components) + vcdvcd.VCDVCD(vcd_filename, callbacks=converter) + print(f"Start Postprocessing VCD: {datetime.now()}") + converter.postprocess() + print(f"End Postprocessing VCD: {datetime.now()}") + print(f"End reading VCD: {datetime.now()}") + + if len(converter.trace) < 100: + for i in converter.trace: + print(i) + for stack in converter.trace[i]: + print(f"\t{stack}") + + tree_dict, path_dict = create_tree(converter.trace) + path_to_edges, all_edges = create_edge_dict(path_dict) + + create_aggregate_tree(converter.trace, out_dir, tree_dict, path_dict) + create_tree_rankings(converter.trace, tree_dict, path_dict, path_to_edges, all_edges, out_dir) + create_flame_groups(converter.trace, flame_out, out_dir) + print(f"End time: {datetime.now()}") + +if __name__ == "__main__": + if len(sys.argv) > 4: + vcd_filename = sys.argv[1] + cells_json = sys.argv[2] + out_dir = sys.argv[3] + flame_out = sys.argv[4] + main(vcd_filename, cells_json, out_dir, flame_out) + else: + args_desc = [ + "VCD_FILE", + "CELLS_JSON", + "OUT_DIR", + "FLATTENED_FLAME_OUT" + ] + print(f"Usage: {sys.argv[0]} {' '.join(args_desc)}") + print("CELLS_JSON: Run the `component_cells` tool") + sys.exit(-1) diff --git a/tools/profiler/run-up-to-tdcc.sh b/tools/profiler/run-up-to-tdcc.sh index 2ae2f7055b..44373c1661 100644 --- a/tools/profiler/run-up-to-tdcc.sh +++ b/tools/profiler/run-up-to-tdcc.sh @@ -9,16 +9,14 @@ fi SCRIPT_DIR=$( cd $( dirname $0 ) && pwd ) CALYX_DIR=$( dirname $( dirname ${SCRIPT_DIR} ) ) -if [ "$2" == "-o" ]; then -( +if [ "$2" == "-no" ]; then + ( cd ${CALYX_DIR} - cargo run $1 -p compile-repeat -p well-formed -p papercut -p canonicalize -p infer-data-path -p collapse-control -p compile-sync-without-sync-reg -p group2seq -p dead-assign-removal -p group2invoke -p infer-share -p inline -p comb-prop -p dead-cell-removal -p cell-share -p simplify-with-control -p compile-invoke -p static-inference -p static-promotion -p compile-repeat -p dead-group-removal -p collapse-control -p static-inline -p merge-assigns -p dead-group-removal -p simplify-static-guards -p add-guard -p static-fsm-opts -p compile-static -p dead-group-removal -p tdcc -) + cargo run $1 -p compile-repeat -p well-formed -p papercut -p canonicalize -p compile-sync -p simplify-with-control -p compile-invoke -p static-inline -p merge-assigns -p dead-group-removal -p simplify-static-guards -p add-guard -p static-fsm-opts -p compile-static -p dead-group-removal -p tdcc + ) else - ( cd ${CALYX_DIR} - cargo run $1 -p compile-repeat -p well-formed -p papercut -p canonicalize -p compile-sync -p simplify-with-control -p compile-invoke -p static-inline -p merge-assigns -p dead-group-removal -p simplify-static-guards -p add-guard -p static-fsm-opts -p compile-static -p dead-group-removal -p tdcc + cargo run $1 -p compile-repeat -p well-formed -p papercut -p canonicalize -p infer-data-path -p collapse-control -p compile-sync-without-sync-reg -p group2seq -p dead-assign-removal -p group2invoke -p infer-share -p inline -p comb-prop -p dead-cell-removal -p cell-share -p simplify-with-control -p compile-invoke -p static-inference -p static-promotion -p compile-repeat -p dead-group-removal -p collapse-control -p static-inline -p merge-assigns -p dead-group-removal -p simplify-static-guards -p add-guard -p static-fsm-opts -p compile-static -p dead-group-removal # -p tdcc ) - fi From 124da612c56b3f2e38ef217222ff5707ae893301 Mon Sep 17 00:00:00 2001 From: Ayaka Yorihiro <36107281+ayakayorihiro@users.noreply.github.com> Date: Mon, 9 Dec 2024 10:54:00 -0800 Subject: [PATCH 09/12] Fix Profiler documentation (#2371) --- docs/SUMMARY.md | 1 + docs/running-calyx/profiler.md | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/SUMMARY.md b/docs/SUMMARY.md index fd7f126fdc..508f69b253 100644 --- a/docs/SUMMARY.md +++ b/docs/SUMMARY.md @@ -26,6 +26,7 @@ - [Scripting](./running-calyx/fud2/scripts.md) - [Interfacing with Calyx RTL](./running-calyx/interfacing.md) - [The Calyx Interpreter](./running-calyx/interpreter.md) +- [The Calyx Profiler](./running-calyx/profiler.md) - [FIRRTL Backend](./running-calyx/firrtl.md) # Compiler Development Guide diff --git a/docs/running-calyx/profiler.md b/docs/running-calyx/profiler.md index d1c64d9c0e..bc0307b591 100644 --- a/docs/running-calyx/profiler.md +++ b/docs/running-calyx/profiler.md @@ -1,4 +1,4 @@ -# Calyx Profiler +# The Calyx Profiler *Note: The profiler is still in development. If you have any suggestions, thoughts, or feedback, please let us know!* @@ -7,7 +7,7 @@ Profilers can help you analyze performance information to find places you can op ## Setup In order to run the profiler, you need: -- [fud2][] +- [fud2](./fud2/index.html) - The Python [`vcdvcd` library](https://github.com/cirosantilli/vcdvcd). Running `fud2 env init` should install this for you. - A clone of Brendan Gregg's Flamegraph repository: [https://github.com/brendangregg/FlameGraph](https://github.com/brendangregg/FlameGraph) From 84dab52608b91a1f2a42a97467a881f5f255ce5a Mon Sep 17 00:00:00 2001 From: Griffin Berlstein <griffin@berlste.in> Date: Mon, 9 Dec 2024 19:42:42 +0000 Subject: [PATCH 10/12] [Cider] Combinational Component support (#2372) Small PR which adds support for combinational components and makes some minor adjustments in a few other places. The notable difference for the convergence algorithm is that we now sort the program counter by containment, before iterating over it. This means we will visit parents before children during convergence and is necessary for race detection in the presence of invoke chains. While it is unnecessary when not doing race detection, I've currently elected to do it unconditionally for simplicity and consistency's sake, but if it becomes necessary we can move it behind the race detection flag. --- interp/src/flatten/flat_ir/base.rs | 16 ++- interp/src/flatten/flat_ir/component.rs | 106 ++++++++++++++++- .../src/flatten/flat_ir/control/translator.rs | 50 +++++--- .../flatten/primitives/stateful/memories.rs | 59 +++++++--- interp/src/flatten/structures/context.rs | 6 +- .../src/flatten/structures/environment/env.rs | 107 ++++++++++++------ .../structures/environment/program_counter.rs | 2 +- interp/src/flatten/structures/printer.rs | 7 +- interp/tests/unit/comb-comp-incr.expect | 14 +++ interp/tests/unit/comb-comp-incr.futil | 71 ++++++++++++ 10 files changed, 355 insertions(+), 83 deletions(-) create mode 100644 interp/tests/unit/comb-comp-incr.expect create mode 100644 interp/tests/unit/comb-comp-incr.futil diff --git a/interp/src/flatten/flat_ir/base.rs b/interp/src/flatten/flat_ir/base.rs index e92d08fc45..bb2f4a0156 100644 --- a/interp/src/flatten/flat_ir/base.rs +++ b/interp/src/flatten/flat_ir/base.rs @@ -642,6 +642,18 @@ impl PortValue { self.0.as_ref() } + /// Returns a mutable reference to the underlying [`AssignedValue`] if it is + /// defined. Otherwise returns `None`. + pub fn as_option_mut(&mut self) -> Option<&mut AssignedValue> { + self.0.as_mut() + } + + /// Returns the underlying [`AssignedValue`] if it is defined. Otherwise + /// returns `None`. + pub fn into_option(self) -> Option<AssignedValue> { + self.0 + } + pub fn with_thread(mut self, thread: ThreadIdx) -> Self { if let Some(val) = self.0.as_mut() { val.thread = Some(thread); @@ -660,10 +672,6 @@ impl PortValue { self.0.as_ref().and_then(|x| x.transitive_clocks()) } - pub fn as_option_mut(&mut self) -> Option<&mut AssignedValue> { - self.0.as_mut() - } - /// If the value is defined, returns the value cast to a boolean. Otherwise /// returns `None`. It will panic if the given value is not one bit wide. pub fn as_bool(&self) -> Option<bool> { diff --git a/interp/src/flatten/flat_ir/component.rs b/interp/src/flatten/flat_ir/component.rs index 3999a7f83e..40a97e282c 100644 --- a/interp/src/flatten/flat_ir/component.rs +++ b/interp/src/flatten/flat_ir/component.rs @@ -79,21 +79,119 @@ impl Default for DefinitionRanges { } /// A structure which contains the basic information about a component -/// definition needed during simulation. +/// definition needed during simulation. This is for standard (non-combinational) +/// components #[derive(Debug)] pub struct ComponentCore { /// The control program for this component. pub control: Option<ControlIdx>, /// The set of assignments that are always active. pub continuous_assignments: IndexRange<AssignmentIdx>, - /// True iff component is combinational - pub is_comb: bool, /// The go port for this component pub go: LocalPortOffset, /// The done port for this component pub done: LocalPortOffset, } +#[derive(Debug)] +pub struct CombComponentCore { + /// The set of assignments that are always active. + pub continuous_assignments: IndexRange<AssignmentIdx>, +} + +impl CombComponentCore { + pub fn contains_assignment( + &self, + assign: AssignmentIdx, + ) -> Option<AssignmentDefinitionLocation> { + self.continuous_assignments + .contains(assign) + .then_some(AssignmentDefinitionLocation::ContinuousAssignment) + } +} + +#[derive(Debug)] +pub enum PrimaryComponentInfo { + Comb(CombComponentCore), + Standard(ComponentCore), +} + +impl PrimaryComponentInfo { + pub fn contains_assignment( + &self, + ctx: &Context, + assign: AssignmentIdx, + ) -> Option<AssignmentDefinitionLocation> { + match self { + PrimaryComponentInfo::Comb(info) => { + info.contains_assignment(assign) + } + PrimaryComponentInfo::Standard(info) => { + info.contains_assignment(ctx, assign) + } + } + } + + #[must_use] + pub fn as_standard(&self) -> Option<&ComponentCore> { + if let Self::Standard(v) = self { + Some(v) + } else { + None + } + } + + pub fn unwrap_standard(&self) -> &ComponentCore { + match self { + PrimaryComponentInfo::Standard(v) => v, + _ => panic!("Expected a standard component"), + } + } + + #[must_use] + pub fn as_comb(&self) -> Option<&CombComponentCore> { + if let Self::Comb(v) = self { + Some(v) + } else { + None + } + } + + /// Returns `true` if the primary component info is [`Comb`]. + /// + /// [`Comb`]: PrimaryComponentInfo::Comb + #[must_use] + pub fn is_comb(&self) -> bool { + matches!(self, Self::Comb(..)) + } + + pub fn continuous_assignments(&self) -> IndexRange<AssignmentIdx> { + match self { + PrimaryComponentInfo::Comb(info) => info.continuous_assignments, + PrimaryComponentInfo::Standard(info) => info.continuous_assignments, + } + } + + pub fn control(&self) -> Option<ControlIdx> { + match self { + PrimaryComponentInfo::Comb(_) => None, + PrimaryComponentInfo::Standard(info) => info.control, + } + } +} + +impl From<ComponentCore> for PrimaryComponentInfo { + fn from(v: ComponentCore) -> Self { + Self::Standard(v) + } +} + +impl From<CombComponentCore> for PrimaryComponentInfo { + fn from(v: CombComponentCore) -> Self { + Self::Comb(v) + } +} + pub enum AssignmentDefinitionLocation { /// The assignment is contained in a comb group CombGroup(CombGroupIdx), @@ -389,4 +487,4 @@ impl IdxSkipSizes { } } -pub type ComponentMap = IndexedMap<ComponentIdx, ComponentCore>; +pub type ComponentMap = IndexedMap<ComponentIdx, PrimaryComponentInfo>; diff --git a/interp/src/flatten/flat_ir/control/translator.rs b/interp/src/flatten/flat_ir/control/translator.rs index 193af5bf13..408f89e1c5 100644 --- a/interp/src/flatten/flat_ir/control/translator.rs +++ b/interp/src/flatten/flat_ir/control/translator.rs @@ -9,7 +9,10 @@ use crate::{ flatten::{ flat_ir::{ cell_prototype::{CellPrototype, ConstantType}, - component::{AuxiliaryComponentInfo, ComponentCore}, + component::{ + AuxiliaryComponentInfo, CombComponentCore, ComponentCore, + PrimaryComponentInfo, + }, flatten_trait::{flatten_tree, FlattenTree, SingleHandle}, prelude::{ Assignment, AssignmentIdx, CellRef, CombGroup, CombGroupIdx, @@ -289,27 +292,38 @@ fn translate_component( .find_all_with_attr(NumAttr::Done) .collect_vec(); - // Will need to rethink this at some point - if go_ports.len() > 1 || done_ports.len() > 1 { - todo!( - "handle multiple go and done ports. On component: {}", + let comp_info: PrimaryComponentInfo = if comp.is_comb { + assert!( + go_ports.is_empty() && done_ports.is_empty(), + "malformed comb component: {}", comp.name ); - } else if comp.is_comb { - todo!("handle comb components. On component: {}", comp.name); - } - let go_port = &go_ports[0]; - let done_port = &done_ports[0]; - - let comp_core = ComponentCore { - control, - continuous_assignments, - is_comb: comp.is_comb, - go: *layout.port_map[&go_port.as_raw()].unwrap_local(), - done: *layout.port_map[&done_port.as_raw()].unwrap_local(), + + PrimaryComponentInfo::Comb(CombComponentCore { + continuous_assignments, + }) + } else { + let go_port = &go_ports[0]; + let done_port = &done_ports[0]; + + // Will need to rethink this at some point + if go_ports.len() > 1 || done_ports.len() > 1 { + todo!( + "handle multiple go and done ports. On component: {}", + comp.name + ); + } + + let comp_core = ComponentCore { + control, + continuous_assignments, + go: *layout.port_map[&go_port.as_raw()].unwrap_local(), + done: *layout.port_map[&done_port.as_raw()].unwrap_local(), + }; + comp_core.into() }; - let ctrl_ref = ctx.primary.components.push(comp_core); + let ctrl_ref = ctx.primary.components.push(comp_info); ctx.secondary .comp_aux_info .insert(ctrl_ref, auxiliary_component_info); diff --git a/interp/src/flatten/primitives/stateful/memories.rs b/interp/src/flatten/primitives/stateful/memories.rs index 9ef3a1a51b..9bf02fb3a0 100644 --- a/interp/src/flatten/primitives/stateful/memories.rs +++ b/interp/src/flatten/primitives/stateful/memories.rs @@ -719,6 +719,37 @@ impl RaceDetectionPrimitive for CombMem { } } +#[derive(Copy, Clone, Debug)] +enum MemOut { + /// Points to a valid address in the memory + Valid(usize), + /// Output is zero, but not a memory address + Zero, + /// Output is undefined + Undef, +} + +impl MemOut { + fn is_def(&self) -> bool { + match self { + MemOut::Valid(_) | MemOut::Zero => true, + MemOut::Undef => false, + } + } + + fn get_value(&self, data: &[ValueWithClock]) -> PortValue { + match self { + MemOut::Valid(addr) => { + PortValue::new_cell(data[*addr].value.clone()) + } + MemOut::Zero => { + PortValue::new_cell(BitVecValue::zero(data[0].value.width())) + } + MemOut::Undef => PortValue::new_undef(), + } + } +} + #[derive(Clone)] pub struct SeqMem { base_port: GlobalPortIdx, @@ -727,10 +758,10 @@ pub struct SeqMem { // TODO griffin: This bool is unused in the actual struct and should either // be removed or _allow_invalid_access: bool, - width: u32, addresser: MemDx<true>, done_is_high: bool, - read_out: PortValue, + // memory index which is currently latched + read_out: MemOut, } impl SeqMem { @@ -755,10 +786,9 @@ impl SeqMem { base_port: base, internal_state, _allow_invalid_access: allow_invalid, - width, addresser: MemDx::new(shape), done_is_high: false, - read_out: PortValue::new_undef(), + read_out: MemOut::Undef, global_idx, } } @@ -804,10 +834,9 @@ impl SeqMem { base_port, internal_state, _allow_invalid_access: allow_invalid, - width, addresser: MemDx::new(size), done_is_high: false, - read_out: PortValue::new_undef(), + read_out: MemOut::Undef, global_idx, } } @@ -884,7 +913,10 @@ impl Primitive for SeqMem { { port_map.insert_val_general( self.read_data(), - self.read_out.as_option().unwrap().clone(), + self.read_out + .get_value(&self.internal_state) + .into_option() + .unwrap(), )? } else { UpdateStatus::Unchanged @@ -908,10 +940,10 @@ impl Primitive for SeqMem { if reset { self.done_is_high = false; - self.read_out = PortValue::new_cell(BitVecValue::zero(self.width)); + self.read_out = MemOut::Zero; } else if content_en && write_en { self.done_is_high = true; - self.read_out = PortValue::new_undef(); + self.read_out = MemOut::Undef; let addr_actual = addr.ok_or(RuntimeError::UndefinedWriteAddr(self.global_idx))?; let write_data = port_map[self.write_data()] @@ -922,9 +954,7 @@ impl Primitive for SeqMem { self.done_is_high = true; let addr_actual = addr.ok_or(RuntimeError::UndefinedReadAddr(self.global_idx))?; - self.read_out = PortValue::new_cell( - self.internal_state[addr_actual].value.clone(), - ); + self.read_out = MemOut::Valid(addr_actual); } else { self.done_is_high = false; } @@ -937,7 +967,10 @@ impl Primitive for SeqMem { BitVecValue::fals() }), )?; - port_map.write_exact_unchecked(self.read_data(), self.read_out.clone()); + port_map.write_exact_unchecked( + self.read_data(), + self.read_out.get_value(&self.internal_state), + ); Ok(()) } diff --git a/interp/src/flatten/structures/context.rs b/interp/src/flatten/structures/context.rs index 87960482a0..eaa2dde318 100644 --- a/interp/src/flatten/structures/context.rs +++ b/interp/src/flatten/structures/context.rs @@ -5,8 +5,8 @@ use calyx_ir::Direction; use crate::flatten::flat_ir::{ cell_prototype::CellPrototype, component::{ - AssignmentDefinitionLocation, AuxiliaryComponentInfo, ComponentCore, - ComponentMap, + AssignmentDefinitionLocation, AuxiliaryComponentInfo, ComponentMap, + PrimaryComponentInfo, }, identifier::IdMap, prelude::{ @@ -53,7 +53,7 @@ pub struct InterpretationContext { } impl Index<ComponentIdx> for InterpretationContext { - type Output = ComponentCore; + type Output = PrimaryComponentInfo; fn index(&self, index: ComponentIdx) -> &Self::Output { &self.components[index] diff --git a/interp/src/flatten/structures/environment/env.rs b/interp/src/flatten/structures/environment/env.rs index d8f3f13925..2eb4d2ec4a 100644 --- a/interp/src/flatten/structures/environment/env.rs +++ b/interp/src/flatten/structures/environment/env.rs @@ -480,20 +480,22 @@ impl<C: AsRef<Context> + Clone> Environment<C> { // TODO griffin: Maybe refactor into a separate function for (idx, ledger) in env.cells.iter() { if let CellLedger::Component(comp) = ledger { - if let Some(ctrl) = - &env.ctx.as_ref().primary[comp.comp_id].control - { - env.pc.vec_mut().push(( - if comp.comp_id == root { - Some(root_thread) - } else { - None - }, - ControlPoint { - comp: idx, - control_node_idx: *ctrl, - }, - )) + let comp_info = &env.ctx.as_ref().primary[comp.comp_id]; + if !comp_info.is_comb() { + if let Some(ctrl) = comp_info.as_standard().unwrap().control + { + env.pc.vec_mut().push(( + if comp.comp_id == root { + Some(root_thread) + } else { + None + }, + ControlPoint { + comp: idx, + control_node_idx: ctrl, + }, + )) + } } } } @@ -534,7 +536,7 @@ impl<C: AsRef<Context> + Clone> Environment<C> { // Insert the component's continuous assignments into the program counter, if non-empty let cont_assigns = - self.ctx.as_ref().primary[*comp_id].continuous_assignments; + self.ctx.as_ref().primary[*comp_id].continuous_assignments(); if !cont_assigns.is_empty() { self.pc.push_continuous_assigns(comp, cont_assigns); } @@ -667,25 +669,40 @@ impl<C: AsRef<Context> + Clone> Environment<C> { } } - pub fn get_comp_go(&self, comp: GlobalCellIdx) -> GlobalPortIdx { + pub fn get_comp_go(&self, comp: GlobalCellIdx) -> Option<GlobalPortIdx> { let ledger = self.cells[comp] .as_comp() .expect("Called get_comp_go with a non-component cell."); - &ledger.index_bases + self.ctx.as_ref().primary[ledger.comp_id].go + let go_port = self.ctx.as_ref().primary[ledger.comp_id] + .as_standard() + .map(|x| x.go); + + go_port.map(|go| &ledger.index_bases + go) } - pub fn get_comp_done(&self, comp: GlobalCellIdx) -> GlobalPortIdx { + pub fn unwrap_comp_go(&self, comp: GlobalCellIdx) -> GlobalPortIdx { + self.get_comp_go(comp).unwrap() + } + + pub fn get_comp_done(&self, comp: GlobalCellIdx) -> Option<GlobalPortIdx> { let ledger = self.cells[comp] .as_comp() .expect("Called get_comp_done with a non-component cell."); - &ledger.index_bases + self.ctx.as_ref().primary[ledger.comp_id].done + let done_port = self.ctx.as_ref().primary[ledger.comp_id] + .as_standard() + .map(|x| x.done); + done_port.map(|done| &ledger.index_bases + done) + } + + pub fn unwrap_comp_done(&self, comp: GlobalCellIdx) -> GlobalPortIdx { + self.get_comp_done(comp).unwrap() } #[inline] pub fn get_root_done(&self) -> GlobalPortIdx { - self.get_comp_done(Self::get_root()) + self.get_comp_done(Self::get_root()).unwrap() } #[inline] @@ -704,7 +721,7 @@ impl<C: AsRef<Context> + Clone> Environment<C> { let node = &self.ctx.as_ref().primary[point.control_node_idx]; match node { ControlNode::Enable(x) => { - let comp_go = self.get_comp_go(point.comp); + let comp_go = self.get_comp_go(point.comp).unwrap(); if self.ports[comp_go].as_bool().unwrap_or_default() { Some(x.group()) } else { @@ -827,7 +844,7 @@ impl<C: AsRef<Context> + Clone> Environment<C> { let node = &self.ctx.as_ref().primary[point.control_node_idx]; match node { ControlNode::Enable(_) | ControlNode::Invoke(_) => { - let comp_go = self.get_comp_go(point.comp); + let comp_go = self.unwrap_comp_go(point.comp); self.ports[comp_go].as_bool().unwrap_or_default() } @@ -1284,7 +1301,7 @@ impl<C: AsRef<Context> + Clone> Environment<C> { pub fn pin_value<S: AsRef<str>>(&mut self, port: S, val: BitVecValue) { let port = self.get_root_input_port(port); - let go = self.get_comp_go(Self::get_root()); + let go = self.unwrap_comp_go(Self::get_root()); assert!(port != go, "Cannot pin the go port"); self.pinned_ports.insert(port, val); @@ -1648,7 +1665,9 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { fn set_root_go_high(&mut self) { let ledger = self.get_root_component(); let go = &ledger.index_bases - + self.env.ctx.as_ref().primary[ledger.comp_id].go; + + self.env.ctx.as_ref().primary[ledger.comp_id] + .unwrap_standard() + .go; self.env.ports[go] = PortValue::new_implicit(BitVecValue::tru()); } @@ -1828,7 +1847,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { } for (comp, id) in self.env.pc.finished_comps() { - let done_port = self.env.get_comp_done(*comp); + let done_port = self.env.unwrap_comp_done(*comp); let v = PortValue::new_implicit(BitVecValue::tru()); self.env.ports[done_port] = if self.conf.check_data_race { v.with_thread(id.expect("finished comps should have a thread")) @@ -1837,17 +1856,26 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { } } - let (vecs, par_map, mut with_map, repeat_map) = + let (mut vecs, par_map, mut with_map, repeat_map) = self.env.pc.take_fields(); + // For thread propagation during race detection we need to iterate in + // containment order. This probably isn't necessary for normal execution + // and could be guarded by the `check_data_race` flag. Will leave it for + // the moment though and see if we need to change it down the line. In + // expectation, the program counter should almost always be already + // sorted as the only thing which causes nodes to be added or removed + // are par nodes + vecs.sort_by_key(|x| x.1.comp); + // for mutability reasons, this should be a cheap clone, either an RC in // the owned case or a simple reference clone let ctx = self.env.ctx.clone(); let ctx_ref = ctx.as_ref(); for (thread, node) in vecs.iter() { - let comp_done = self.env.get_comp_done(node.comp); - let comp_go = self.env.get_comp_go(node.comp); + let comp_done = self.env.unwrap_comp_done(node.comp); + let comp_go = self.env.unwrap_comp_go(node.comp); let thread = thread.or_else(|| { self.env.ports[comp_go].as_option().and_then(|t| t.thread()) }); @@ -1887,7 +1915,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { PortValue::new_implicit(BitVecValue::tru()) .with_thread_optional( if self.conf.check_data_race { - assert!(thread.is_some()); + assert!(thread.is_some(), "Invoke is running but has no thread. This shouldn't happen. In {}", node.comp.get_full_name(&self.env)); thread } else { None @@ -2058,8 +2086,8 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { ) -> RuntimeResult<ControlNodeEval> { let (node_thread, node) = node; let (par_map, with_map, repeat_map) = maps; - let comp_go = self.env.get_comp_go(node.comp); - let comp_done = self.env.get_comp_done(node.comp); + let comp_go = self.env.unwrap_comp_go(node.comp); + let comp_done = self.env.unwrap_comp_done(node.comp); let thread = node_thread.or_else(|| { self.env.ports[comp_go].as_option().and_then(|x| x.thread()) @@ -2124,6 +2152,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { let comp_ledger = self.env.cells[node.comp].unwrap_comp(); *node = node.new_retain_comp( self.env.ctx.as_ref().primary[comp_ledger.comp_id] + .unwrap_standard() .control .unwrap(), ); @@ -2520,7 +2549,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { // signal of the component must also be high .map(|g| { self.env.ports[*g].as_bool().unwrap_or_default() - && self.env.ports[comp_go] + && self.env.ports[comp_go.unwrap()] .as_bool() .unwrap_or_default() }) @@ -2530,7 +2559,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { if assign_type.is_continuous() { true } else { - self.env.ports[comp_go] + self.env.ports[comp_go.unwrap()] .as_bool() .unwrap_or_default() } @@ -2760,7 +2789,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { .as_ref() .map(|g| { self.env.ports[*g].as_bool().unwrap_or_default() - && self.env.ports[comp_go] + && self.env.ports[comp_go.unwrap()] .as_bool() .unwrap_or_default() }) @@ -2825,7 +2854,9 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { let comp_go = self.env.get_comp_go(*active_cell); if (assign_type.is_combinational() - && self.env.ports[comp_go].as_bool().unwrap_or_default()) + && comp_go + .and_then(|comp_go| self.env.ports[comp_go].as_bool()) + .unwrap_or_default()) || assign_type.is_continuous() { for assign_idx in assignments.iter() { @@ -3078,7 +3109,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { /// none of these succeed then `None` is returned. fn compute_thread( &self, - comp_go: GlobalPortIdx, + comp_go: Option<GlobalPortIdx>, thread: &Option<ThreadIdx>, go: Option<GlobalPortIdx>, ) -> Option<ThreadIdx> { @@ -3090,7 +3121,9 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> { return Some(go_thread); } } - self.env.ports[comp_go].as_option().and_then(|x| x.thread()) + comp_go.and_then(|comp_go| { + self.env.ports[comp_go].as_option().and_then(|x| x.thread()) + }) }) } diff --git a/interp/src/flatten/structures/environment/program_counter.rs b/interp/src/flatten/structures/environment/program_counter.rs index 698a4a0dab..3c312ed483 100644 --- a/interp/src/flatten/structures/environment/program_counter.rs +++ b/interp/src/flatten/structures/environment/program_counter.rs @@ -402,7 +402,7 @@ impl SearchPath { .components .iter() .fold_while(ControlIdx::new(0), |current_root, (_, comp_info)| { - if let Some(index) = comp_info.control { + if let Some(index) = comp_info.control() { if index >= current_root && index < target { FoldWhile::Continue(index) } else { diff --git a/interp/src/flatten/structures/printer.rs b/interp/src/flatten/structures/printer.rs index 7d42a2bb71..952c65ee3d 100644 --- a/interp/src/flatten/structures/printer.rs +++ b/interp/src/flatten/structures/printer.rs @@ -76,9 +76,10 @@ impl<'a> Printer<'a> { for x in self.ctx.secondary[idx].definitions.comb_groups() { self.print_comb_group(x, idx) } - if !self.ctx.primary[idx].continuous_assignments.is_empty() { + if !self.ctx.primary[idx].continuous_assignments().is_empty() { println!("{}", text_utils::indent("Continuous Assignments:", 1)); - for assign in self.ctx.primary[idx].continuous_assignments.iter() { + for assign in self.ctx.primary[idx].continuous_assignments().iter() + { println!( "{}", text_utils::indent(self.print_assignment(idx, assign), 2) @@ -87,7 +88,7 @@ impl<'a> Printer<'a> { } println!(); println!("{}", text_utils::indent("Control:", 1)); - if let Some(ctrl) = self.ctx.primary[idx].control { + if let Some(ctrl) = self.ctx.primary[idx].control() { println!("{}", self.format_control(idx, ctrl, 2)); } } diff --git a/interp/tests/unit/comb-comp-incr.expect b/interp/tests/unit/comb-comp-incr.expect new file mode 100644 index 0000000000..84a055204b --- /dev/null +++ b/interp/tests/unit/comb-comp-incr.expect @@ -0,0 +1,14 @@ +{ + "r": [ + 14 + ], + "r_t0": [ + 10 + ], + "r_t1": [ + 11 + ], + "r_t2": [ + 13 + ] +} diff --git a/interp/tests/unit/comb-comp-incr.futil b/interp/tests/unit/comb-comp-incr.futil new file mode 100644 index 0000000000..645ea6a34b --- /dev/null +++ b/interp/tests/unit/comb-comp-incr.futil @@ -0,0 +1,71 @@ +import "primitives/core.futil"; +import "primitives/binary_operators.futil"; + + +comb component incr(in: 32) -> (out: 32) { + cells { + add = std_add(32); + } + wires { + add.left = in; + add.right = 32'd1; + out = add.out; + } +} + +component copy() -> () { + cells { + ref source = std_reg(32); + ref dest = std_reg(32); + } + wires { + group copy { + dest.in = source.out; + dest.write_en = 1'd1; + copy[done] = dest.done; + } + } + control { + seq { + copy; + } + } +} + +component main() -> () { + cells { + inc = incr(32); + r = std_reg(32); + r_t0 = std_reg(32); + r_t1 = std_reg(32); + r_t2 = std_reg(32); + copy = copy(); + } + + wires { + group init { + r.in = 32'd10; + r.write_en = 1'd1; + init[done] = r.done; + } + group incr { + inc.in = r.out; + r.in = inc.out; + r.write_en = 1'd1; + incr[done] = r.done; + } + } + + control { + seq { + init; + invoke copy[source=r, dest=r_t0]()(); + incr; + invoke copy[source=r, dest=r_t1]()(); + incr; + incr; + invoke copy[source=r, dest=r_t2]()(); + incr; + } + } +} From 7e2e9133fe7e5a79d42eb49587b0089ee33563ed Mon Sep 17 00:00:00 2001 From: Ayaka Yorihiro <36107281+ayakayorihiro@users.noreply.github.com> Date: Tue, 10 Dec 2024 10:12:08 -0800 Subject: [PATCH 11/12] Remove par-to-seq from profiler passes (#2373) Forgot to remove `par-to-seq` from profiler passes after implementing profiling for parallel programs!!! --- fud2/scripts/profiler.rhai | 2 +- fud2/tests/snapshots/tests__test@plan_profiler.snap | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/fud2/scripts/profiler.rhai b/fud2/scripts/profiler.rhai index 0a678efa35..b798d2ccb1 100644 --- a/fud2/scripts/profiler.rhai +++ b/fud2/scripts/profiler.rhai @@ -40,7 +40,7 @@ fn calyx_to_flamegraph(e, input, output) { e.build_cmd(["$cells"], "component-cells", [input], []); e.build_cmd([instrumented_verilog], "calyx", [input], []); e.arg("backend", "verilog"); - e.arg("args", " -p static-inline -p compile-static -p compile-repeat -p par-to-seq -p compile-invoke -p profiler-instrumentation -p $passes -x tdcc:dump-fsm-json=fsm.json"); + e.arg("args", " -p static-inline -p compile-static -p compile-repeat -p compile-invoke -p profiler-instrumentation -p $passes -x tdcc:dump-fsm-json=fsm.json"); let instrumented_sim = "instrumented.exe"; // verilog --> sim; adapted from verilator::verilator_build() diff --git a/fud2/tests/snapshots/tests__test@plan_profiler.snap b/fud2/tests/snapshots/tests__test@plan_profiler.snap index 1e8c101447..b917f06f2f 100644 --- a/fud2/tests/snapshots/tests__test@plan_profiler.snap +++ b/fud2/tests/snapshots/tests__test@plan_profiler.snap @@ -54,7 +54,7 @@ cycle-limit = 500000000 build $cells: component-cells /input.ext build instrumented.sv: calyx /input.ext backend = verilog - args = -p static-inline -p compile-static -p compile-repeat -p par-to-seq -p compile-invoke -p profiler-instrumentation -p $passes -x tdcc:dump-fsm-json=fsm.json + args = -p static-inline -p compile-static -p compile-repeat -p compile-invoke -p profiler-instrumentation -p $passes -x tdcc:dump-fsm-json=fsm.json build verilator-out/Vtoplevel: verilator-compile-standalone-tb instrumented.sv | tb.sv out-dir = verilator-out build instrumented.exe: cp verilator-out/Vtoplevel From 260d2f1df2e472cbd3fc2dd12951c54c11a7768f Mon Sep 17 00:00:00 2001 From: Griffin Berlstein <griffin@berlste.in> Date: Tue, 10 Dec 2024 20:14:21 +0000 Subject: [PATCH 12/12] [CI] Standardize a single rust toolchain for all of CI (#2374) Supersedes #2369. `rust-toolchain.toml` now determines the version of rust used for every aspect of the CI, rather than having it change on its own or be set separately. As it turns out, the version of rust used for the clippy lints was also pinned separately, so I also had to address all those lints. As a result, I had to make minor changes to a bunch of code, the vast majority of which were either docstring indents or places where people manually implemented `ToString` instead of using `Display`. I don't anticipate any of these changes messing with things but if I did break something, do let me know. Assuming I've done things correctly, it should be the case that the rust version will not change on its own anymore, and we can update the version used by all of Ci by editing the toolchain file --- .github/workflows/docs.yml | 4 +- .github/workflows/format.yml | 4 +- .github/workflows/playground.yml | 2 - calyx-backend/src/backend_opt.rs | 6 +-- calyx-backend/src/verilog.rs | 2 +- calyx-ir/src/guard.rs | 16 ++++---- calyx-ir/src/printer.rs | 4 +- .../domination_analysis/dominator_map.rs | 41 ++++++++++--------- calyx-opt/src/analysis/graph.rs | 8 ++-- calyx-opt/src/analysis/graph_coloring.rs | 7 ++-- calyx-opt/src/analysis/inference_analysis.rs | 3 +- calyx-opt/src/analysis/static_tree.rs | 13 +++--- calyx-opt/src/analysis/variable_detection.rs | 1 + calyx-opt/src/passes/cell_share.rs | 10 ++--- calyx-opt/src/passes/collapse_control.rs | 1 - calyx-opt/src/passes/group_to_invoke.rs | 4 +- calyx-opt/src/passes/lower_guards.rs | 6 +-- calyx-opt/src/passes/static_promotion.rs | 8 ++-- calyx-opt/src/passes/well_formed.rs | 4 +- .../sync/compile_sync_without_sync_reg.rs | 2 +- calyx-opt/src/traversal/construct.rs | 2 +- calyx-utils/src/out_file.rs | 19 +++++---- calyx-utils/src/pos_string.rs | 8 ++-- calyx-utils/src/weight_graph.rs | 11 +++-- rust-toolchain.toml | 2 + src/cmdline.rs | 2 +- tools/data-conversion/src/main.rs | 25 +++++------ 27 files changed, 106 insertions(+), 109 deletions(-) diff --git a/.github/workflows/docs.yml b/.github/workflows/docs.yml index c31a656d1a..e689a741d3 100644 --- a/.github/workflows/docs.yml +++ b/.github/workflows/docs.yml @@ -23,10 +23,8 @@ jobs: - name: mdbook run: mdbook build - name: Install Rust stable - uses: actions-rs/toolchain@v1 + uses: actions-rust-lang/setup-rust-toolchain@v1 with: - toolchain: 1.66.0 - override: true components: rustfmt, clippy - name: Build source documentation uses: actions-rs/cargo@v1 diff --git a/.github/workflows/format.yml b/.github/workflows/format.yml index 33263866cf..a5077b678f 100644 --- a/.github/workflows/format.yml +++ b/.github/workflows/format.yml @@ -13,10 +13,8 @@ jobs: - name: Checkout uses: actions/checkout@v4 - name: Install stable - uses: actions-rs/toolchain@v1 + uses: actions-rust-lang/setup-rust-toolchain@v1 with: - toolchain: 1.76.0 - override: true components: rustfmt, clippy - name: Check formatting uses: actions-rs/cargo@v1 diff --git a/.github/workflows/playground.yml b/.github/workflows/playground.yml index a569ddd371..da58255702 100644 --- a/.github/workflows/playground.yml +++ b/.github/workflows/playground.yml @@ -14,8 +14,6 @@ jobs: - uses: actions/setup-node@v4 - name: Install Rust stable uses: actions-rust-lang/setup-rust-toolchain@v1 - with: - toolchain: stable - name: Install wasm-pack and wasm-bindgen-cli uses: taiki-e/install-action@wasm-pack with: diff --git a/calyx-backend/src/backend_opt.rs b/calyx-backend/src/backend_opt.rs index 000e368d78..f28bedbb68 100644 --- a/calyx-backend/src/backend_opt.rs +++ b/calyx-backend/src/backend_opt.rs @@ -62,8 +62,8 @@ impl FromStr for BackendOpt { } /// Convert `BackendOpt` to a string -impl ToString for BackendOpt { - fn to_string(&self) -> String { +impl std::fmt::Display for BackendOpt { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { match self { Self::Mlir => "mlir", Self::Resources => "resources", @@ -76,6 +76,6 @@ impl ToString for BackendOpt { Self::PrimitiveUses => "primitive-uses", Self::None => "none", } - .to_string() + .fmt(f) } } diff --git a/calyx-backend/src/verilog.rs b/calyx-backend/src/verilog.rs index dda26a31b4..0f0371af53 100644 --- a/calyx-backend/src/verilog.rs +++ b/calyx-backend/src/verilog.rs @@ -419,7 +419,7 @@ fn cell_instance(cell: &ir::Cell) -> Option<v::Instance> { ); } else { param_binding.iter().for_each(|(name, value)| { - if *value > (std::i32::MAX as u64) { + if *value > (i32::MAX as u64) { panic!( "Parameter value {} for `{}` cannot be represented using 32 bits", value, diff --git a/calyx-ir/src/guard.rs b/calyx-ir/src/guard.rs index 287adbd229..9b1edad4b7 100644 --- a/calyx-ir/src/guard.rs +++ b/calyx-ir/src/guard.rs @@ -2,7 +2,7 @@ use crate::Printer; use super::{NumAttr, Port, RRC}; use calyx_utils::Error; -use std::fmt::Debug; +use std::fmt::{Debug, Display}; use std::mem; use std::ops::{BitAnd, BitAndAssign, BitOr, BitOrAssign, Not}; use std::{cmp::Ordering, hash::Hash, rc::Rc}; @@ -11,9 +11,9 @@ use std::{cmp::Ordering, hash::Hash, rc::Rc}; #[cfg_attr(feature = "serialize", derive(serde::Serialize))] pub struct Nothing; -impl ToString for Nothing { - fn to_string(&self) -> String { - "".to_string() +impl Display for Nothing { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + write!(f, "") } } @@ -62,12 +62,12 @@ pub struct StaticTiming { interval: (u64, u64), } -impl ToString for StaticTiming { - fn to_string(&self) -> String { +impl Display for StaticTiming { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { if self.interval.0 + 1 == self.interval.1 { - format!("%{}", self.interval.0) + write!(f, "%{}", self.interval.0) } else { - format!("%[{}:{}]", self.interval.0, self.interval.1) + write!(f, "%[{}:{}]", self.interval.0, self.interval.1) } } } diff --git a/calyx-ir/src/printer.rs b/calyx-ir/src/printer.rs index f8da0fc4c8..e7388481ef 100644 --- a/calyx-ir/src/printer.rs +++ b/calyx-ir/src/printer.rs @@ -759,9 +759,9 @@ impl Printer { } /// Generate a String-based representation for a guard. - pub fn guard_str<T: ToString>(guard: &ir::Guard<T>) -> String + pub fn guard_str<T>(guard: &ir::Guard<T>) -> String where - T: Eq, + T: Eq + ToString, { match &guard { ir::Guard::And(l, r) | ir::Guard::Or(l, r) => { diff --git a/calyx-opt/src/analysis/domination_analysis/dominator_map.rs b/calyx-opt/src/analysis/domination_analysis/dominator_map.rs index 89d2354fea..5ee5c58cb5 100644 --- a/calyx-opt/src/analysis/domination_analysis/dominator_map.rs +++ b/calyx-opt/src/analysis/domination_analysis/dominator_map.rs @@ -23,21 +23,22 @@ const END_ID: ir::Attribute = ir::Attribute::Internal(ir::InternalAttr::END_ID); /// - While Guards /// - If Guards /// - "End" If nodes, representing the place we're at in the program after the if -/// statement has just finished. This doesn't correspond to any actual Calyx code, but is -/// just a conceptualization we use to reason about domination. +/// statement has just finished. This doesn't correspond to any actual Calyx code, but is +/// just a conceptualization we use to reason about domination. +/// /// Note that seqs and pars will *not* be included in the domination map. /// /// Here is the algorithm we use to build the domination map. /// - Start with an emtpy map. /// - Visit each node n in the control program, and set: /// - dom(n) = {U dom(p) for each predecessor p of n} U {n}. In other words, take the -/// dominators of each predecessor of n, and union them together. Then add n to -/// this set, and set this set as the dominators of n. +/// dominators of each predecessor of n, and union them together. Then add n to +/// this set, and set this set as the dominators of n. /// - (Another clarification): by "predecessors" of node n we mean the set of nodes -/// that could be the most recent node executed when n begins to execute. +/// that could be the most recent node executed when n begins to execute. /// - If we visit every node of the control program and the map has not changed, -/// then we are done. If it has changed, then we visit each node again to repeat -/// the process. +/// then we are done. If it has changed, then we visit each node again to repeat +/// the process. /// /// The reason why we can take the union (rather than intersection) of the /// dominators of each predecessor is because we know each predecessor of each @@ -46,19 +47,19 @@ const END_ID: ir::Attribute = ir::Attribute::Internal(ir::InternalAttr::END_ID); /// our algorithm to deal with them. /// /// 1) The While Guard -/// The last node(s) in the while body are predecessor(s) of the while guard but -/// are not guaranteed to be executed. So, we can think of the while guard's -/// predecessors as being split in two groups: the "body predecessors" that are not guaranteed to -/// be executed before the while guard and the "outside predecessors" that are -/// outside the body of the while loop and are guaranteed to be executed before -/// the while loop guard. -/// Here we take: -/// dom(while guard) = U(dom(outside preds)) U {while guard} +/// The last node(s) in the while body are predecessor(s) of the while guard but +/// are not guaranteed to be executed. So, we can think of the while guard's +/// predecessors as being split in two groups: the "body predecessors" that are not guaranteed to +/// be executed before the while guard and the "outside predecessors" that are +/// outside the body of the while loop and are guaranteed to be executed before +/// the while loop guard. +/// Here we take: +/// dom(while guard) = U(dom(outside preds)) U {while guard} /// /// Justification: /// dom(while guard) is a subset of U(dom(outside preds)) U {while guard} /// Suppose n dominates the while guard. Every path to the while guard must end in -/// 1) outside pred -> while guard OR 2) body pred -> while guard. But for choice 2) +/// (1) outside pred -> while guard OR (2) body pred -> while guard. But for choice 2) /// we know the path was really something like outside pred -> while guard -> body /// -> while guard... body -> while guard. Since n dominates the while guard /// we know that it *cannot* be in the while body. Therefore, since every path to the @@ -72,10 +73,10 @@ const END_ID: ir::Attribute = ir::Attribute::Internal(ir::InternalAttr::END_ID); /// n dominates the while guard. /// /// 2) "End Node" of If Statements -/// In this case, *neither* of the predecessor sets (the set in the tbranch or -/// the set in the fbranch) are guaranteed to be executed. -/// Here we take: -/// dom(end node) = dom(if guard) U {end node}. +/// In this case, *neither* of the predecessor sets (the set in the tbranch or +/// the set in the fbranch) are guaranteed to be executed. +/// Here we take: +/// dom(end node) = dom(if guard) U {end node}. /// /// Justification: /// dom(end node) is a subset of dom(if guard) U {end node}. diff --git a/calyx-opt/src/analysis/graph.rs b/calyx-opt/src/analysis/graph.rs index 72c2dacdf5..0c9d9b3225 100644 --- a/calyx-opt/src/analysis/graph.rs +++ b/calyx-opt/src/analysis/graph.rs @@ -5,7 +5,7 @@ use petgraph::{ visit::EdgeRef, Direction::{Incoming, Outgoing}, }; -use std::fmt::Write; +use std::fmt::{Display, Write}; use std::{collections::HashMap, rc::Rc}; type Node = RRC<ir::Port>; @@ -271,8 +271,8 @@ impl GraphAnalysis { } } -impl ToString for GraphAnalysis { - fn to_string(&self) -> String { +impl Display for GraphAnalysis { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { let mut out = String::new(); for idx in self.graph.node_indices() { let src_port = self.graph[idx].borrow(); @@ -293,6 +293,6 @@ impl ToString for GraphAnalysis { ) .expect("Failed to write to ScheduleConflicts string"); } - out + out.fmt(f) } } diff --git a/calyx-opt/src/analysis/graph_coloring.rs b/calyx-opt/src/analysis/graph_coloring.rs index cd36af4027..5ceea831be 100644 --- a/calyx-opt/src/analysis/graph_coloring.rs +++ b/calyx-opt/src/analysis/graph_coloring.rs @@ -3,6 +3,7 @@ use itertools::Itertools; use petgraph::algo; use std::{ collections::{BTreeMap, HashMap}, + fmt::Display, hash::Hash, }; @@ -216,8 +217,8 @@ where } } -impl<T: Eq + Hash + ToString + Clone + Ord> ToString for GraphColoring<T> { - fn to_string(&self) -> String { - self.graph.to_string() +impl<T: Eq + Hash + ToString + Clone + Ord> Display for GraphColoring<T> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + self.graph.to_string().fmt(f) } } diff --git a/calyx-opt/src/analysis/inference_analysis.rs b/calyx-opt/src/analysis/inference_analysis.rs index a2f2b209c2..ddd612f221 100644 --- a/calyx-opt/src/analysis/inference_analysis.rs +++ b/calyx-opt/src/analysis/inference_analysis.rs @@ -535,10 +535,11 @@ impl InferenceAnalysis { /// "Fixes Up" the component. In particular: /// 1. Removes @promotable annotations for any groups that write to any - /// `updated_components`. + /// `updated_components`. /// 2. Try to re-infer groups' latencies. /// 3. Removes all @promotable annotation from the control program. /// 4. Re-infers the @promotable annotations for any groups or control. + /// /// Note that this only fixes up the component's ``internals''. /// It does *not* fix the component's signature. pub fn fixup_timing(&self, comp: &mut ir::Component) { diff --git a/calyx-opt/src/analysis/static_tree.rs b/calyx-opt/src/analysis/static_tree.rs index 0c7d3b7b11..e89a3f05ca 100644 --- a/calyx-opt/src/analysis/static_tree.rs +++ b/calyx-opt/src/analysis/static_tree.rs @@ -367,13 +367,13 @@ impl SingleNode { /// Therefore we take in a bunch of data structures to keep track of coloring: /// - `coloring` that maps group names -> colors, /// - `colors_to_max_values` which maps colors -> (max latency, max_num_repeats) - /// (we need to make sure that when we instantiate a color, - /// we give enough bits to support the maximum latency/num_repeats that will be - /// used for that color) + /// (we need to make sure that when we instantiate a color, + /// we give enough bits to support the maximum latency/num_repeats that will be + /// used for that color) /// - `colors_to_fsm` - /// which maps colors to (fsm_register, iter_count_register): fsm_register counts - /// up for a single iteration, iter_count_register counts the number of iterations - /// that have passed. + /// which maps colors to (fsm_register, iter_count_register): fsm_register counts + /// up for a single iteration, iter_count_register counts the number of iterations + /// that have passed. /// /// Note that it is not always necessary to instantiate one or both registers (e.g., /// if num_repeats == 1 then you don't need an iter_count_register). @@ -1279,6 +1279,7 @@ impl SingleNode { /// - if `global_view` is true, then you have to include the iteration /// count register in the assignment's guard. /// - if `global_view` is false, then you dont' have to include it + /// /// `ignore_timing`: remove static timing guards instead of transforming them /// into an FSM query. Note that in order to do this, the timing guard must /// equal %[0:1], otherwise we will throw an error. This option is here diff --git a/calyx-opt/src/analysis/variable_detection.rs b/calyx-opt/src/analysis/variable_detection.rs index 3cc112b6fa..97c21decfb 100644 --- a/calyx-opt/src/analysis/variable_detection.rs +++ b/calyx-opt/src/analysis/variable_detection.rs @@ -10,6 +10,7 @@ impl VariableDetection { /// - among write to state_shareable components, there is only one write /// - has `@go` port equal to `1'd1` /// - has `g[done] = cell.done` + /// /// Returns the name of the cell if such a group is detected, /// otherwise returns `None`. pub fn variable_like( diff --git a/calyx-opt/src/passes/cell_share.rs b/calyx-opt/src/passes/cell_share.rs index fe85667807..dc163be240 100644 --- a/calyx-opt/src/passes/cell_share.rs +++ b/calyx-opt/src/passes/cell_share.rs @@ -282,12 +282,12 @@ impl CellShare { /// - use [ScheduleConflicts] to find groups/invokes that run in parallel with each other /// - for each tuple combination of cells that return true on cell_filter(), c1 and c2 /// - first determine if their live ranges overlap. If so, then insert a conflict between -/// c1 and c2 +/// c1 and c2 /// - if c1 and c2 don't have overlapping live ranges, check if c1 and c2 are ever -/// live at within the same par block, and they are live at different children -/// of the par block. If the parent par is not static, then add a conflict. -/// If the parent par is static, then we can use the static_par_timing analysis -/// to check whether the cells' liveness actually overlaps. +/// live at within the same par block, and they are live at different children +/// of the par block. If the parent par is not static, then add a conflict. +/// If the parent par is static, then we can use the static_par_timing analysis +/// to check whether the cells' liveness actually overlaps. /// - perform graph coloring using `self.ordering` to define the order of the greedy coloring /// - use coloring to rewrite group assignments, continuous assignments, and conditional ports. impl Visitor for CellShare { diff --git a/calyx-opt/src/passes/collapse_control.rs b/calyx-opt/src/passes/collapse_control.rs index 71c7f73a61..3a5190274b 100644 --- a/calyx-opt/src/passes/collapse_control.rs +++ b/calyx-opt/src/passes/collapse_control.rs @@ -36,7 +36,6 @@ use calyx_ir::{self as ir, GetAttributes, LibrarySignatures}; /// 3. Collapses nested `static seq` in the same way as 1 /// 4. Collapses nested `static par` in the same way as 2 /// 5. Collapses `static repeat`: -/// Collapse /// ``` /// static repeat 0 { ** body ** } /// ``` diff --git a/calyx-opt/src/passes/group_to_invoke.rs b/calyx-opt/src/passes/group_to_invoke.rs index 4acdb50020..33fb9269ea 100644 --- a/calyx-opt/src/passes/group_to_invoke.rs +++ b/calyx-opt/src/passes/group_to_invoke.rs @@ -13,9 +13,9 @@ use std::rc::Rc; /// /// For a group to meet the requirements of this pass, it must /// 1. Only write to one non-combinational component (all other writes must be -/// to combinational primitives) +/// to combinational primitives) /// 2. That component is *not* a ref cell, nor does it have the external attribute, -/// nor is it This Component +/// nor is it This Component /// 3. Assign component.go = 1'd1 /// 4. Assign group[done] = component.done pub struct GroupToInvoke { diff --git a/calyx-opt/src/passes/lower_guards.rs b/calyx-opt/src/passes/lower_guards.rs index fccb9ebad3..3748cbec9f 100644 --- a/calyx-opt/src/passes/lower_guards.rs +++ b/calyx-opt/src/passes/lower_guards.rs @@ -145,12 +145,11 @@ impl Visitor for LowerGuards { .component .get_groups_mut() .drain() - .map(|group| { + .inspect(|group| { let assigns = group.borrow_mut().assignments.drain(..).collect(); let new_assigns = lower_assigns(assigns, &mut builder); group.borrow_mut().assignments = new_assigns; - group }) .into(); builder.component.set_groups(groups); @@ -174,12 +173,11 @@ impl Visitor for LowerGuards { .component .comb_groups .drain() - .map(|group| { + .inspect(|group| { let assigns = group.borrow_mut().assignments.drain(..).collect(); let new_assigns = lower_assigns(assigns, &mut builder); group.borrow_mut().assignments = new_assigns; - group }) .into(); builder.component.comb_groups = comb_groups; diff --git a/calyx-opt/src/passes/static_promotion.rs b/calyx-opt/src/passes/static_promotion.rs index 00a64c323c..637475f69c 100644 --- a/calyx-opt/src/passes/static_promotion.rs +++ b/calyx-opt/src/passes/static_promotion.rs @@ -21,12 +21,12 @@ const APPROX_WHILE_REPEAT_SIZE: u64 = 3; /// /// Promotion occurs the following policies: /// 1. ``Threshold'': How large the island must be. We have three const -/// defined as heuristics to measure approximately how big each control program -/// is. It must be larger than that threshold. +/// defined as heuristics to measure approximately how big each control program +/// is. It must be larger than that threshold. /// 2. ``Cycle limit": The maximum number of cycles the island can be when we -/// promote it. +/// promote it. /// 3. ``If Diff Limit": The maximum difference in latency between if statments -/// that we can tolerate to promote it. +/// that we can tolerate to promote it. /// pub struct StaticPromotion { /// An InferenceAnalysis object so that we can re-infer the latencies of diff --git a/calyx-opt/src/passes/well_formed.rs b/calyx-opt/src/passes/well_formed.rs index 32d14bb63d..a5634a278b 100644 --- a/calyx-opt/src/passes/well_formed.rs +++ b/calyx-opt/src/passes/well_formed.rs @@ -541,13 +541,13 @@ impl Visitor for WellFormed { { Err(Error::malformed_structure(format!( "Static Timing Guard has improper interval: `{}`", - static_timing.to_string() + static_timing )) .with_pos(&assign.attributes)) } else if static_timing.get_interval().1 > group_latency { Err(Error::malformed_structure(format!( "Static Timing Guard has interval `{}`, which is out of bounds since its static group has latency {}", - static_timing.to_string(), + static_timing, group_latency )) .with_pos(&assign.attributes)) diff --git a/calyx-opt/src/passes_experimental/sync/compile_sync_without_sync_reg.rs b/calyx-opt/src/passes_experimental/sync/compile_sync_without_sync_reg.rs index cb175fde38..d99ed5ac7c 100644 --- a/calyx-opt/src/passes_experimental/sync/compile_sync_without_sync_reg.rs +++ b/calyx-opt/src/passes_experimental/sync/compile_sync_without_sync_reg.rs @@ -64,7 +64,7 @@ impl BarrierMap { } fn insert_shared_wire(&mut self, builder: &mut ir::Builder, idx: &u64) { - if self.0.get(idx).is_none() { + if !self.0.contains_key(idx) { structure!(builder; let s = prim std_wire(1); ); diff --git a/calyx-opt/src/traversal/construct.rs b/calyx-opt/src/traversal/construct.rs index 65042598a2..8e88a36297 100644 --- a/calyx-opt/src/traversal/construct.rs +++ b/calyx-opt/src/traversal/construct.rs @@ -106,7 +106,7 @@ impl std::fmt::Display for ParseVal { } write!(f, "]") } - ParseVal::OutStream(o) => write!(f, "{}", o.to_string()), + ParseVal::OutStream(o) => write!(f, "{}", o), } } } diff --git a/calyx-utils/src/out_file.rs b/calyx-utils/src/out_file.rs index 16ac5ff654..c3edac848c 100644 --- a/calyx-utils/src/out_file.rs +++ b/calyx-utils/src/out_file.rs @@ -1,4 +1,5 @@ use std::{ + fmt::Display, io::{self, BufWriter}, path::PathBuf, str::FromStr, @@ -48,14 +49,16 @@ impl FromStr for OutputFile { } } -impl ToString for OutputFile { - fn to_string(&self) -> String { - match self { - OutputFile::Stdout => "-".to_string(), - OutputFile::Stderr => "<err>".to_string(), - OutputFile::Null => "<null>".to_string(), - OutputFile::File { path, .. } => path.to_str().unwrap().to_string(), - } +impl Display for OutputFile { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let string = match self { + OutputFile::Stdout => "-", + OutputFile::Stderr => "<err>", + OutputFile::Null => "<null>", + OutputFile::File { path, .. } => path.to_str().unwrap(), + }; + + string.fmt(f) } } diff --git a/calyx-utils/src/pos_string.rs b/calyx-utils/src/pos_string.rs index 90c0b96913..d5cc617dac 100644 --- a/calyx-utils/src/pos_string.rs +++ b/calyx-utils/src/pos_string.rs @@ -1,4 +1,4 @@ -use std::path::PathBuf; +use std::{fmt::Display, path::PathBuf}; use crate::{GPosIdx, WithPos}; @@ -30,9 +30,9 @@ impl From<PosString> for PathBuf { } } -impl ToString for PosString { - fn to_string(&self) -> String { - self.data.to_string() +impl Display for PosString { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + self.data.fmt(f) } } diff --git a/calyx-utils/src/weight_graph.rs b/calyx-utils/src/weight_graph.rs index e6ca364453..b5e72d5a59 100644 --- a/calyx-utils/src/weight_graph.rs +++ b/calyx-utils/src/weight_graph.rs @@ -1,7 +1,7 @@ use itertools::Itertools; use petgraph::matrix_graph::{MatrixGraph, NodeIndex, UnMatrix, Zero}; use petgraph::visit::IntoEdgeReferences; -use std::{collections::HashMap, hash::Hash}; +use std::{collections::HashMap, fmt::Display, hash::Hash}; /// Index into a [WeightGraph] pub type Idx = NodeIndex; @@ -126,14 +126,13 @@ where } } -impl<T: Eq + Hash + ToString + Clone + Ord> ToString for WeightGraph<T> { - fn to_string(&self) -> String { +impl<T: Eq + Hash + ToString + Clone + Ord> Display for WeightGraph<T> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { let rev_map = self.reverse_index(); let keys: Vec<_> = self.index_map.keys().collect(); let nodes = keys .iter() - .enumerate() - .map(|(_idx, key)| { + .map(|key| { format!( " {} [label=\"{}\"];", key.to_string(), @@ -154,6 +153,6 @@ impl<T: Eq + Hash + ToString + Clone + Ord> ToString for WeightGraph<T> { }) .collect::<Vec<_>>() .join("\n"); - format!("graph {{ \n{}\n{}\n }}", nodes, edges) + write!(f, "graph {{ \n{}\n{}\n }}", nodes, edges) } } diff --git a/rust-toolchain.toml b/rust-toolchain.toml index 2e2b8c8521..22efd9b707 100644 --- a/rust-toolchain.toml +++ b/rust-toolchain.toml @@ -1,2 +1,4 @@ +# This file is used by github actions for the CI checks. + [toolchain] channel = "1.82.0" diff --git a/src/cmdline.rs b/src/cmdline.rs index f03eb0b365..5568a4e148 100644 --- a/src/cmdline.rs +++ b/src/cmdline.rs @@ -200,7 +200,7 @@ impl Opts { { return Err(Error::misc(format!( "--compile-mode=file is only valid with -b calyx. `-b {}` requires --compile-mode=project", - opts.backend.to_string() + opts.backend ))); } diff --git a/tools/data-conversion/src/main.rs b/tools/data-conversion/src/main.rs index f41315a257..8f4663723c 100644 --- a/tools/data-conversion/src/main.rs +++ b/tools/data-conversion/src/main.rs @@ -1,12 +1,12 @@ //use std::env; use argh::FromArgs; -use std::error::Error; use std::fmt; use std::fs::read_to_string; use std::fs::File; use std::io::stdout; use std::io::{self, Write}; use std::str::FromStr; +use std::{error::Error, fmt::Display}; //cargo run -- --from $PATH1 --to $PATH2 --ftype "from" --totype "to" @@ -29,14 +29,15 @@ enum NumType { Fixed, } -impl ToString for NumType { - fn to_string(&self) -> String { +impl Display for NumType { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { match self { - NumType::Binary => "binary".to_string(), - NumType::Float => "float".to_string(), - NumType::Hex => "hex".to_string(), - NumType::Fixed => "fixed".to_string(), + NumType::Binary => "binary", + NumType::Float => "float", + NumType::Hex => "hex", + NumType::Fixed => "fixed", } + .fmt(f) } } @@ -171,22 +172,18 @@ fn convert( } _ => panic!( "Conversion from {} to {} is not supported", - convert_from.to_string(), - convert_to.to_string() + convert_from, convert_to ), } if let Some(filepath) = filepath_send { eprintln!( "Successfully converted from {} to {} in {}", - convert_from.to_string(), - convert_to.to_string(), - filepath + convert_from, convert_to, filepath ); } else { eprintln!( "Successfully converted from {} to {}", - convert_from.to_string(), - convert_to.to_string(), + convert_from, convert_to, ); } }

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