From 470506d032fccec587823885852d0d000d6aa07e Mon Sep 17 00:00:00 2001
From: Parth Sarkar <ps679@cornell.edu>
Date: Tue, 17 Dec 2024 13:11:45 -0500
Subject: [PATCH] fixed bug where compiler generates OR guards instead of AND

---
 calyx-backend/src/verilog.rs | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/calyx-backend/src/verilog.rs b/calyx-backend/src/verilog.rs
index 71df8d668..3c88e1cd2 100644
--- a/calyx-backend/src/verilog.rs
+++ b/calyx-backend/src/verilog.rs
@@ -880,13 +880,20 @@ impl<'a> std::fmt::Display for VerilogPortRef<'a> {
 
 fn unflattened_guard(guard: &ir::Guard<Nothing>) -> String {
     match guard {
-        Guard::Or(left, right) | Guard::And(left, right) => {
+        Guard::Or(left, right) => {
             format!(
                 "({}) | ({})",
                 unflattened_guard(left),
                 unflattened_guard(right)
             )
         }
+        Guard::And(left, right) => {
+            format!(
+                "({}) & ({})",
+                unflattened_guard(left),
+                unflattened_guard(right)
+            )
+        }
         Guard::CompOp(comp, left, right) => {
             let op = match comp {
                 ir::PortComp::Eq => "==",