From 5c6d93eddaa1a0780ea5cc778f1d21fb447eb02e Mon Sep 17 00:00:00 2001
From: Jiahan Xie <jx353@cornell.edu>
Date: Tue, 17 Dec 2024 18:01:21 -0500
Subject: [PATCH] change while line to for line due to format checking

---
 calyx-backend/src/verilog.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/calyx-backend/src/verilog.rs b/calyx-backend/src/verilog.rs
index 8646b38fe..5ddec38e9 100644
--- a/calyx-backend/src/verilog.rs
+++ b/calyx-backend/src/verilog.rs
@@ -235,10 +235,10 @@ impl Backend for VerilogBackend {
             if cmd.status.success() {
                 // Post-process morty output
                 let stdout = String::from_utf8_lossy(&cmd.stdout);
-                let mut lines = stdout.lines();
+                let lines = stdout.lines();
                 let mut skip_next_line = false;
 
-                while let Some(line) = lines.next() {
+                for line in lines {
                     if skip_next_line {
                         skip_next_line = false;
                         continue;