From 8549f52a600d47fcb13fb3837831c5d10a8f1654 Mon Sep 17 00:00:00 2001 From: Ayaka Yorihiro Date: Wed, 4 Dec 2024 16:13:09 -0500 Subject: [PATCH] removing old profiler tests --- tests/profiler/par.expect | 69 ---------------------- tests/profiler/par.futil | 41 ------------- tests/profiler/par.futil.data | 32 ---------- tests/profiler/simple-par.expect | 47 --------------- tests/profiler/simple-par.futil | 23 -------- tests/profiler/simple-par.futil.data | 12 ---- tests/profiler/simple-seq.expect | 36 ----------- tests/profiler/simple-seq.futil | 23 -------- tests/profiler/simple-seq.futil.data | 12 ---- tests/profiler/while-never-true.expect | 60 ------------------- tests/profiler/while-never-true.futil | 46 --------------- tests/profiler/while-never-true.futil.data | 10 ---- 12 files changed, 411 deletions(-) delete mode 100644 tests/profiler/par.expect delete mode 100644 tests/profiler/par.futil delete mode 100644 tests/profiler/par.futil.data delete mode 100644 tests/profiler/simple-par.expect delete mode 100644 tests/profiler/simple-par.futil delete mode 100644 tests/profiler/simple-par.futil.data delete mode 100644 tests/profiler/simple-seq.expect delete mode 100644 tests/profiler/simple-seq.futil delete mode 100644 tests/profiler/simple-seq.futil.data delete mode 100644 tests/profiler/while-never-true.expect delete mode 100644 tests/profiler/while-never-true.futil delete mode 100644 tests/profiler/while-never-true.futil.data diff --git a/tests/profiler/par.expect b/tests/profiler/par.expect deleted file mode 100644 index bf4f603070..0000000000 --- a/tests/profiler/par.expect +++ /dev/null @@ -1,69 +0,0 @@ -[get-profile-counts-info.sh] Obtaining FSM info from TDCC -[get-profile-counts-info.sh] Obtaining cell information from component-cells backend -[get-profile-counts-info.sh] Obtaining VCD file via simulation -[get-profile-counts-info.sh] Using FSM info and VCD file to obtain cycle level counts -Total clock cycles: 3 -=====SUMMARY===== - -[FSM] Group TOP.toplevel.main.par0 Summary: - Total cycles: 3 - # of times active: 1 - Avg runtime: 3.0 - -[GT] Group TOP.toplevel.main.par0 Summary: - Total cycles: 2 - # of times active: 1 - Avg runtime: 2.0 - -[GT] Group TOP.toplevel.main.wr_a Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -[GT] Group TOP.toplevel.main.wr_b Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -[GT] Group TOP.toplevel.main.wr_c Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -=====DUMP===== - -[FSM] Group TOP.toplevel.main.par0: - FSM name: TOP.toplevel.main.fsm - FSM state ids: [0] - Total cycles: 3 - # of times active: 1 - Segments: [0, 3) - -[GT] Group TOP.toplevel.main.par0: - Total cycles: 2 - # of times active: 1 - Segments: [0, 2) - -[GT] Group TOP.toplevel.main.wr_a: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -[GT] Group TOP.toplevel.main.wr_b: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -[GT] Group TOP.toplevel.main.wr_c: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -name,total-cycles,times-active,avg -TOP.toplevel.main.par0[FSM],3,1,3.0 -TOP.toplevel.main.par0,2,1,2.0 -TOP.toplevel.main.wr_a,1,1,1.0 -TOP.toplevel.main.wr_b,1,1,1.0 -TOP.toplevel.main.wr_c,1,1,1.0 -TOTAL,3,-,- -[get-profile-counts-info.sh] Writing visualization diff --git a/tests/profiler/par.futil b/tests/profiler/par.futil deleted file mode 100644 index 1f71a5e152..0000000000 --- a/tests/profiler/par.futil +++ /dev/null @@ -1,41 +0,0 @@ -import "primitives/core.futil"; -import "primitives/memories/comb.futil"; - -component main() -> () { - cells { - @external(1) a = comb_mem_d1(32, 1, 1); - @external(1) b = comb_mem_d1(32, 1, 1); - @external(1) c = comb_mem_d1(32, 1, 1); - } - - wires { - group wr_a { - a.addr0 = 1'b0; - a.write_en = 1'b1; - a.write_data = 32'd1; - wr_a[done] = a.done; - } - - group wr_b { - b.addr0 = 1'b0; - b.write_en = 1'b1; - b.write_data = 32'd1; - wr_b[done] = b.done; - } - - group wr_c { - c.addr0 = 1'b0; - c.write_en = 1'b1; - c.write_data = 32'd1; - wr_c[done] = c.done; - } - } - - control { - par { - wr_a; - wr_b; - wr_c; - } - } -} diff --git a/tests/profiler/par.futil.data b/tests/profiler/par.futil.data deleted file mode 100644 index 4862df80f9..0000000000 --- a/tests/profiler/par.futil.data +++ /dev/null @@ -1,32 +0,0 @@ -{ - "a": { - "data": [ - 0 - ], - "format": { - "numeric_type": "bitnum", - "is_signed": true, - "width": 32 - } - }, - "b": { - "data": [ - 0 - ], - "format": { - "numeric_type": "bitnum", - "is_signed": false, - "width": 32 - } - }, - "c": { - "data": [ - 0 - ], - "format": { - "numeric_type": "bitnum", - "is_signed": false, - "width": 32 - } - } -} diff --git a/tests/profiler/simple-par.expect b/tests/profiler/simple-par.expect deleted file mode 100644 index 213fd30020..0000000000 --- a/tests/profiler/simple-par.expect +++ /dev/null @@ -1,47 +0,0 @@ -[get-profile-counts-info.sh] Obtaining FSM info from TDCC -[get-profile-counts-info.sh] Obtaining cell information from component-cells backend -[get-profile-counts-info.sh] Obtaining VCD file via simulation -[get-profile-counts-info.sh] Using FSM info and VCD file to obtain cycle level counts -Total clock cycles: 3 -=====SUMMARY===== - -[FSM] Group TOP.toplevel.main.par0 Summary: - Total cycles: 3 - # of times active: 1 - Avg runtime: 3.0 - -[GT] Group TOP.toplevel.main.par0 Summary: - Total cycles: 2 - # of times active: 1 - Avg runtime: 2.0 - -[GT] Group TOP.toplevel.main.write Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -=====DUMP===== - -[FSM] Group TOP.toplevel.main.par0: - FSM name: TOP.toplevel.main.fsm - FSM state ids: [0] - Total cycles: 3 - # of times active: 1 - Segments: [0, 3) - -[GT] Group TOP.toplevel.main.par0: - Total cycles: 2 - # of times active: 1 - Segments: [0, 2) - -[GT] Group TOP.toplevel.main.write: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -name,total-cycles,times-active,avg -TOP.toplevel.main.par0[FSM],3,1,3.0 -TOP.toplevel.main.par0,2,1,2.0 -TOP.toplevel.main.write,1,1,1.0 -TOTAL,3,-,- -[get-profile-counts-info.sh] Writing visualization diff --git a/tests/profiler/simple-par.futil b/tests/profiler/simple-par.futil deleted file mode 100644 index a66b7ab5e7..0000000000 --- a/tests/profiler/simple-par.futil +++ /dev/null @@ -1,23 +0,0 @@ -import "primitives/core.futil"; -import "primitives/memories/comb.futil"; - -component main() -> () { - cells { - @external(1) a = comb_mem_d1(32, 1, 1); - } - - wires { - group write { - a.addr0 = 1'b0; - a.write_en = 1'b1; - a.write_data = 32'd1; - write[done] = a.done; - } - } - - control { - par { - write; - } - } -} diff --git a/tests/profiler/simple-par.futil.data b/tests/profiler/simple-par.futil.data deleted file mode 100644 index cad4ef0e4a..0000000000 --- a/tests/profiler/simple-par.futil.data +++ /dev/null @@ -1,12 +0,0 @@ -{ - "a": { - "data": [ - 0 - ], - "format": { - "numeric_type": "bitnum", - "is_signed": true, - "width": 32 - } - } -} diff --git a/tests/profiler/simple-seq.expect b/tests/profiler/simple-seq.expect deleted file mode 100644 index 35bff072bf..0000000000 --- a/tests/profiler/simple-seq.expect +++ /dev/null @@ -1,36 +0,0 @@ -[get-profile-counts-info.sh] Obtaining FSM info from TDCC -[get-profile-counts-info.sh] Obtaining cell information from component-cells backend -[get-profile-counts-info.sh] Obtaining VCD file via simulation -[get-profile-counts-info.sh] Using FSM info and VCD file to obtain cycle level counts -Total clock cycles: 2 -=====SUMMARY===== - -[FSM] Group TOP.toplevel.main.write Summary: - Total cycles: 2 - # of times active: 1 - Avg runtime: 2.0 - -[GT] Group TOP.toplevel.main.write Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -=====DUMP===== - -[FSM] Group TOP.toplevel.main.write: - FSM name: TOP.toplevel.main.fsm - FSM state ids: [0] - Total cycles: 2 - # of times active: 1 - Segments: [0, 2) - -[GT] Group TOP.toplevel.main.write: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -name,total-cycles,times-active,avg -TOP.toplevel.main.write[FSM],2,1,2.0 -TOP.toplevel.main.write,1,1,1.0 -TOTAL,2,-,- -[get-profile-counts-info.sh] Writing visualization diff --git a/tests/profiler/simple-seq.futil b/tests/profiler/simple-seq.futil deleted file mode 100644 index 9bf79820a1..0000000000 --- a/tests/profiler/simple-seq.futil +++ /dev/null @@ -1,23 +0,0 @@ -import "primitives/core.futil"; -import "primitives/memories/comb.futil"; - -component main() -> () { - cells { - @external(1) a = comb_mem_d1(32, 1, 1); - } - - wires { - group write { - a.addr0 = 1'b0; - a.write_en = 1'b1; - a.write_data = 32'd1; - write[done] = a.done; - } - } - - control { - seq { - write; - } - } -} diff --git a/tests/profiler/simple-seq.futil.data b/tests/profiler/simple-seq.futil.data deleted file mode 100644 index cad4ef0e4a..0000000000 --- a/tests/profiler/simple-seq.futil.data +++ /dev/null @@ -1,12 +0,0 @@ -{ - "a": { - "data": [ - 0 - ], - "format": { - "numeric_type": "bitnum", - "is_signed": true, - "width": 32 - } - } -} diff --git a/tests/profiler/while-never-true.expect b/tests/profiler/while-never-true.expect deleted file mode 100644 index 04bf0a1c9f..0000000000 --- a/tests/profiler/while-never-true.expect +++ /dev/null @@ -1,60 +0,0 @@ -[get-profile-counts-info.sh] Obtaining FSM info from TDCC -[get-profile-counts-info.sh] Obtaining cell information from component-cells backend -[get-profile-counts-info.sh] Obtaining VCD file via simulation -[get-profile-counts-info.sh] Using FSM info and VCD file to obtain cycle level counts -Total clock cycles: 2 -=====SUMMARY===== - -[FSM] Group TOP.toplevel.main.cond Summary: - Total cycles: 2 - # of times active: 1 - Avg runtime: 2.0 - -[GT] Group TOP.toplevel.main.cond Summary: - Total cycles: 1 - # of times active: 1 - Avg runtime: 1.0 - -[FSM] Group TOP.toplevel.main.incr Summary: - Total cycles: 0 - # of times active: 0 - Avg runtime: 0 - -[GT] Group TOP.toplevel.main.incr Summary: - Total cycles: 0 - # of times active: 0 - Avg runtime: 0 - -=====DUMP===== - -[FSM] Group TOP.toplevel.main.cond: - FSM name: TOP.toplevel.main.fsm - FSM state ids: [0, 3] - Total cycles: 2 - # of times active: 1 - Segments: [0, 2) - -[GT] Group TOP.toplevel.main.cond: - Total cycles: 1 - # of times active: 1 - Segments: [0, 1) - -[FSM] Group TOP.toplevel.main.incr: - FSM name: TOP.toplevel.main.fsm - FSM state ids: [2, 1] - Total cycles: 0 - # of times active: 0 - Segments: - -[GT] Group TOP.toplevel.main.incr: - Total cycles: 0 - # of times active: 0 - Segments: - -name,total-cycles,times-active,avg -TOP.toplevel.main.cond[FSM],2,1,2.0 -TOP.toplevel.main.cond,1,1,1.0 -TOP.toplevel.main.incr[FSM],0,0,0 -TOP.toplevel.main.incr,0,0,0 -TOTAL,2,-,- -[get-profile-counts-info.sh] Writing visualization diff --git a/tests/profiler/while-never-true.futil b/tests/profiler/while-never-true.futil deleted file mode 100644 index 97805bd8f6..0000000000 --- a/tests/profiler/while-never-true.futil +++ /dev/null @@ -1,46 +0,0 @@ -import "primitives/core.futil"; -import "primitives/memories/comb.futil"; - -component main() -> () { - cells { - @external(1) i = comb_mem_d1(32, 1, 1); - lt = std_lt(32); - lt_reg = std_reg(1); - add = std_add(32); - } - - wires { - group cond { - i.addr0 = 1'd0; - lt.left = i.read_data; - lt.right = 32'd0; - lt_reg.in = lt.out; - lt_reg.write_en = 1'b1; - cond[done] = lt_reg.done; - } - - group incr { - add.right = i.read_data; - add.left = 32'd1; - - i.write_data = add.out; - i.addr0 = 1'd0; - i.write_en = 1'b1; - - incr[done] = i.done; - } - } - - control { - seq { - cond; - while lt_reg.out { - seq { - incr; - incr; - cond; - } - } - } - } -} diff --git a/tests/profiler/while-never-true.futil.data b/tests/profiler/while-never-true.futil.data deleted file mode 100644 index a2b95ef52d..0000000000 --- a/tests/profiler/while-never-true.futil.data +++ /dev/null @@ -1,10 +0,0 @@ -{ - "i": { - "data": [0], - "format": { - "numeric_type": "bitnum", - "is_signed": false, - "width": 32 - } - } -}