From a7534503c136d461f626c6749836de39cc8aaa2d Mon Sep 17 00:00:00 2001
From: Rachit Nigam <rachit.nigam12@gmail.com>
Date: Sun, 3 Nov 2024 16:56:55 -0500
Subject: [PATCH] Remove use of `always_comb`

---
 primitives/binary_operators.sv                |  2 +-
 .../seq-mem-vec-add-axi-wrapped.expect        |  2 +-
 .../seq-mem-vec-add-verilog.expect            | 55 +------------------
 3 files changed, 4 insertions(+), 55 deletions(-)

diff --git a/primitives/binary_operators.sv b/primitives/binary_operators.sv
index 1cfe5beabe..7ba413f0d8 100644
--- a/primitives/binary_operators.sv
+++ b/primitives/binary_operators.sv
@@ -146,7 +146,7 @@ module std_fp_div_pipe #(
         running <= running;
     end
 
-    always_comb begin
+    always @* begin
       if (acc >= {1'b0, right}) begin
         acc_next = acc - right;
         {acc_next, quotient_next} = {acc_next[WIDTH-1:0], quotient, 1'b1};
diff --git a/yxi/tests/axi/read-compute-write/seq-mem-vec-add-axi-wrapped.expect b/yxi/tests/axi/read-compute-write/seq-mem-vec-add-axi-wrapped.expect
index bf390e5738..ac69b673cc 100644
--- a/yxi/tests/axi/read-compute-write/seq-mem-vec-add-axi-wrapped.expect
+++ b/yxi/tests/axi/read-compute-write/seq-mem-vec-add-axi-wrapped.expect
@@ -327,7 +327,7 @@ module std_fp_div_pipe #(
         running <= running;
     end
 
-    always_comb begin
+    always @* begin
       if (acc >= {1'b0, right}) begin
         acc_next = acc - right;
         {acc_next, quotient_next} = {acc_next[WIDTH-1:0], quotient, 1'b1};
diff --git a/yxi/tests/axi/read-compute-write/seq-mem-vec-add-verilog.expect b/yxi/tests/axi/read-compute-write/seq-mem-vec-add-verilog.expect
index 15594bdd32..6503598b09 100644
--- a/yxi/tests/axi/read-compute-write/seq-mem-vec-add-verilog.expect
+++ b/yxi/tests/axi/read-compute-write/seq-mem-vec-add-verilog.expect
@@ -1,53 +1,2 @@
-{
-  "A0": {
-    "data": [
-      1,
-      3,
-      7,
-      15,
-      31,
-      63,
-      127,
-      255
-    ],
-    "format": {
-      "numeric_type": "bitnum",
-      "is_signed": false,
-      "width": 32
-    }
-  },
-  "B0": {
-    "data": [
-      1,
-      1,
-      1,
-      1,
-      1,
-      1,
-      1,
-      1
-    ],
-    "format": {
-      "numeric_type": "bitnum",
-      "is_signed": false,
-      "width": 32
-    }
-  },
-  "Sum0": {
-    "data": [
-      2,
-      4,
-      8,
-      16,
-      32,
-      64,
-      128,
-      256
-    ],
-    "format": {
-      "numeric_type": "bitnum",
-      "is_signed": false,
-      "width": 32
-    }
-  }
-}
+---CODE---
+1