From e7b1fbbac8acdca13f7834a61b17b282bfa24054 Mon Sep 17 00:00:00 2001
From: Ayaka Yorihiro <36107281+ayakayorihiro@users.noreply.github.com>
Date: Wed, 7 Feb 2024 13:45:17 -0500
Subject: [PATCH] [Calyx-FIRRTL] Debugged FIRRTL implementations of primitives
 (#1907)

* Debug std_reg FIRRTL implementation

* Fix std_const template typo

* Fix std_lsh FIRRTL primitive

* Fixed std_reg bug that was causing  to fail
---
 .../firrtl/generate-firrtl-with-primitives.py |  6 +++++-
 tools/firrtl/templates/std_const.fir          |  2 +-
 tools/firrtl/templates/std_lsh.fir            |  2 +-
 tools/firrtl/templates/std_reg.fir            | 20 +++++++++++--------
 4 files changed, 19 insertions(+), 11 deletions(-)

diff --git a/tools/firrtl/generate-firrtl-with-primitives.py b/tools/firrtl/generate-firrtl-with-primitives.py
index b6d2163936..b1f8be6700 100644
--- a/tools/firrtl/generate-firrtl-with-primitives.py
+++ b/tools/firrtl/generate-firrtl-with-primitives.py
@@ -1,4 +1,5 @@
 import json
+import math
 import os
 import sys
 
@@ -13,6 +14,9 @@ def generate_replacement_map(inst):
         replacement_map["DIFF"] = replacement_map["OUT_WIDTH"] - replacement_map["IN_WIDTH"]
     elif inst["name"] == "std_slice":
         replacement_map["DIFF"] = replacement_map["IN_WIDTH"] - replacement_map["OUT_WIDTH"]
+    elif inst["name"] == "std_lsh":
+        width = replacement_map["WIDTH"]
+        replacement_map["BITS"] = math.ceil(math.log(width, 2)) + 1
 
     return replacement_map
 
@@ -62,4 +66,4 @@ def main():
     generate(sys.argv[1], sys.argv[2])
 
 if __name__ == '__main__':
-        main()
\ No newline at end of file
+        main()
diff --git a/tools/firrtl/templates/std_const.fir b/tools/firrtl/templates/std_const.fir
index 27a66a93df..9c0fc5473c 100644
--- a/tools/firrtl/templates/std_const.fir
+++ b/tools/firrtl/templates/std_const.fir
@@ -1,3 +1,3 @@
-    module std_const_WIDTH_VAL :
+    module std_const_WIDTH_VALUE :
         output out : UInt<WIDTH>
         out <= UInt(VALUE)
diff --git a/tools/firrtl/templates/std_lsh.fir b/tools/firrtl/templates/std_lsh.fir
index 934883c083..adae3394e7 100644
--- a/tools/firrtl/templates/std_lsh.fir
+++ b/tools/firrtl/templates/std_lsh.fir
@@ -3,4 +3,4 @@
         input right : UInt<WIDTH>
         output out : UInt<WIDTH>
 
-        out <= dshl(left, right)
+        out <= dshl(left, bits(right, BITS, 0))
diff --git a/tools/firrtl/templates/std_reg.fir b/tools/firrtl/templates/std_reg.fir
index fe9a4192f4..1ecc93cc25 100644
--- a/tools/firrtl/templates/std_reg.fir
+++ b/tools/firrtl/templates/std_reg.fir
@@ -7,13 +7,17 @@
         output done : UInt<1>
 
         reg internal_reg : UInt<WIDTH>, clk
-        out <= UInt(0)
-        when eq(write_en, UInt(1)):
-            out <= in
-            done <= UInt(1)
+        reg done_reg : UInt<1>, clk
+
+        when eq(reset, UInt(1)):
+            internal_reg <= UInt(0)
+            done_reg <= UInt(0)
         else:
-            when eq(reset, UInt(1)):
-                done <= UInt(0)
-                out <= UInt(0)
+            when eq(write_en, UInt(1)):
+                internal_reg <= in
+                done_reg <= UInt(1)
             else:
-                done <= UInt(0)
+                done_reg <= UInt(0)
+
+        out <= internal_reg
+        done <= done_reg