diff --git a/fud/fud/stages/vivado/extract.py b/fud/fud/stages/vivado/extract.py
index 964e95ee24..437ba83480 100644
--- a/fud/fud/stages/vivado/extract.py
+++ b/fud/fud/stages/vivado/extract.py
@@ -79,22 +79,35 @@ def place_and_route_extract(
     try:
         if util_file.exists():
             impl_parser = rpt.RPTParser(util_file)
-            slice_logic = impl_parser.get_table(re.compile(r"1\. CLB Logic"), 2)
-            dsp_table = impl_parser.get_table(re.compile(r"4\. ARITHMETIC"), 2)
-
-            clb_lut = to_int(find_row(slice_logic, "Site Type", "CLB LUTs")["Used"])
-            clb_reg = to_int(
-                find_row(slice_logic, "Site Type", "CLB Registers")["Used"]
-            )
-            carry8 = to_int(find_row(slice_logic, "Site Type", "CARRY8")["Used"])
-            f7_muxes = to_int(find_row(slice_logic, "Site Type", "F7 Muxes")["Used"])
-            f8_muxes = to_int(find_row(slice_logic, "Site Type", "F8 Muxes")["Used"])
-            f9_muxes = to_int(find_row(slice_logic, "Site Type", "F9 Muxes")["Used"])
+            try:
+                slice_logic = impl_parser.get_table(re.compile(r"1\. CLB Logic"), 2)
+                dsp_table = impl_parser.get_table(re.compile(r"4\. ARITHMETIC"), 2)
+
+                clb_lut = to_int(find_row(slice_logic, "Site Type", "CLB LUTs")["Used"])
+                clb_reg = to_int(
+                    find_row(slice_logic, "Site Type", "CLB Registers")["Used"]
+                )
+                carry8 = to_int(find_row(slice_logic, "Site Type", "CARRY8")["Used"])
+                f7_muxes = to_int(find_row(slice_logic, "Site Type", "F7 Muxes")["Used"])
+                f8_muxes = to_int(find_row(slice_logic, "Site Type", "F8 Muxes")["Used"])
+                f9_muxes = to_int(find_row(slice_logic, "Site Type", "F9 Muxes")["Used"])
+            except:
+                # Older FPGAs use a different table format
+                slice_logic = impl_parser.get_table(re.compile(r"1\. Slice Logic"), 2)
+                dsp_table = impl_parser.get_table(re.compile(r"4\. DSP"), 2)
+                clb_lut = to_int(find_row(slice_logic, "Site Type", "Slice LUTs")["Used"])
+                clb_reg = to_int(
+                    find_row(slice_logic, "Site Type", "Slice Registers")["Used"]
+                )
+                carry8 = -1
+                f7_muxes = to_int(find_row(slice_logic, "Site Type", "F7 Muxes")["Used"])
+                f8_muxes = to_int(find_row(slice_logic, "Site Type", "F8 Muxes")["Used"])
+                f9_muxes = -1
+
+                
             resource_info.update(
                 {
-                    "lut": to_int(
-                        find_row(slice_logic, "Site Type", "CLB LUTs")["Used"]
-                    ),
+                    "lut": clb_lut,
                     "dsp": to_int(find_row(dsp_table, "Site Type", "DSPs")["Used"]),
                     "registers": rtl_component_extract(synth_file, "Registers"),
                     "muxes": rtl_component_extract(synth_file, "Muxes"),