From 509ae13431db52bb84fe576f84465726bc131269 Mon Sep 17 00:00:00 2001 From: wargio Date: Tue, 27 Aug 2024 22:50:05 +0800 Subject: [PATCH] Add MCRegisterClass_getRegister --- MCRegisterInfo.c | 4 + MCRegisterInfo.h | 2 + arch/Mips/MipsDisassembler.c | 210 +++++++++++++++++++---------------- arch/Mips/MipsModule.c | 1 + 4 files changed, 119 insertions(+), 98 deletions(-) diff --git a/MCRegisterInfo.c b/MCRegisterInfo.c index ce9a237a476..e8007fae675 100644 --- a/MCRegisterInfo.c +++ b/MCRegisterInfo.c @@ -149,3 +149,7 @@ bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg) return (c->RegSet[Byte] & (1 << InByte)) != 0; } + +unsigned MCRegisterClass_getRegister(const MCRegisterClass *c, unsigned RegNo) { + return c->RegsBegin[RegNo]; +} diff --git a/MCRegisterInfo.h b/MCRegisterInfo.h index 471a04a9dd8..8432e5e2c52 100644 --- a/MCRegisterInfo.h +++ b/MCRegisterInfo.h @@ -113,4 +113,6 @@ const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsi bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg); +unsigned MCRegisterClass_getRegister(const MCRegisterClass *c, unsigned i); + #endif diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c index 1a3f5d99859..d25801da369 100644 --- a/arch/Mips/MipsDisassembler.c +++ b/arch/Mips/MipsDisassembler.c @@ -33,6 +33,7 @@ #include "../../MathExtras.h" #include "../../MCInstPrinter.h" #include "../../MCDisassembler.h" +#include "../../MCRegisterInfo.h" #include "../../MCFixedLenDisassembler.h" #include "../../cs_priv.h" #include "../../utils.h" @@ -550,7 +551,20 @@ static DecodeStatus DecodeFIXMEInstruction(MCInst *Inst, unsigned Insn, const void *Decoder); #include "MipsGenDisassemblerTables.inc" -#define getReg(Decoder, Rc, RegNo) (RegNo) + +static unsigned getReg(const MCInst *Inst, unsigned RC, unsigned RegNo) +{ + if (!Inst->MRI) { + return MIPS_REG_INVALID; + } + + const MCRegisterClass* c = MCRegisterInfo_getRegClass(Inst->MRI, RC); + if (!MCRegisterClass_contains(c, RegNo)) { + return MIPS_REG_INVALID; + } + + return MCRegisterClass_getRegister(c, RegNo); +} typedef DecodeStatus (*DecodeFN)(MCInst *Inst, unsigned Insn, uint64_t Address, @@ -604,8 +618,8 @@ static DecodeStatus DecodeDAHIDATI(MCInst *MI, uint32_t insn, uint64_t Address, { uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); uint32_t Imm = fieldFromInstruction_4(insn, 0, 16); - MCOperand_CreateReg0(MI, (Rs)); - MCOperand_CreateReg0(MI, (Rs)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; @@ -641,9 +655,9 @@ static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, uint32_t insn, if (HasRs) MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, (Rt)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; @@ -660,25 +674,25 @@ static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, uint32_t insn, if (Rs >= Rt) { MCInst_setOpcode(MI, (Mips_BOVC_MMR6)); MCOperand_CreateReg0( - MI, (Rt)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 2 + 4; } else if (Rs != 0 && Rs < Rt) { MCInst_setOpcode(MI, (Mips_BEQC_MMR6)); MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); MCOperand_CreateReg0( - MI, (Rt)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; } else { MCInst_setOpcode(MI, (Mips_BEQZALC_MMR6)); MCOperand_CreateReg0( - MI, (Rt)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 2 + 4; @@ -720,9 +734,9 @@ static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, uint32_t insn, if (HasRs) MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, (Rt)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; @@ -739,25 +753,25 @@ static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, uint32_t insn, if (Rs >= Rt) { MCInst_setOpcode(MI, (Mips_BNVC_MMR6)); MCOperand_CreateReg0( - MI, (Rt)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 2 + 4; } else if (Rs != 0 && Rs < Rt) { MCInst_setOpcode(MI, (Mips_BNEC_MMR6)); MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); MCOperand_CreateReg0( - MI, (Rt)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; } else { MCInst_setOpcode(MI, (Mips_BNEZALC_MMR6)); MCOperand_CreateReg0( - MI, (Rt)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 2 + 4; @@ -798,9 +812,9 @@ static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, uint32_t insn, if (HasRs) MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, (Rt)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateImm0(MI, (Imm)); @@ -837,9 +851,9 @@ static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, uint32_t insn, if (HasRs) MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, (Rt)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateImm0(MI, (Imm)); @@ -880,9 +894,9 @@ static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, uint32_t insn, if (HasRs) MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, (Rt)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateImm0(MI, (Imm)); @@ -924,9 +938,9 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, uint32_t insn, if (HasRs) MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, (Rt)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateImm0(MI, (Imm)); @@ -971,11 +985,11 @@ static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, uint32_t insn, if (HasRs) MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); if (HasRt) MCOperand_CreateReg0( - MI, (Rt)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateImm0(MI, (Imm)); @@ -1015,8 +1029,8 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, uint32_t insn, if (HasRs) MCOperand_CreateReg0( - MI, (Rs)); - MCOperand_CreateReg0(MI, (Rt)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateImm0(MI, (Imm)); @@ -1055,8 +1069,8 @@ static DecodeStatus DecodeDEXT(MCInst *MI, uint32_t Insn, uint64_t Address, uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); - MCOperand_CreateReg0(MI, (Rt)); - MCOperand_CreateReg0(MI, (Rs)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rt))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); MCOperand_CreateImm0(MI, (Pos)); MCOperand_CreateImm0(MI, (Size)); @@ -1096,8 +1110,8 @@ static DecodeStatus DecodeDINS(MCInst *MI, uint32_t Insn, uint64_t Address, uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); MCInst_setOpcode(MI, (Mips_DINS)); - MCOperand_CreateReg0(MI, (Rt)); - MCOperand_CreateReg0(MI, (Rs)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rt))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); MCOperand_CreateImm0(MI, (Pos)); MCOperand_CreateImm0(MI, (Size)); @@ -1110,9 +1124,9 @@ static DecodeStatus DecodeCRC(MCInst *MI, uint32_t Insn, uint64_t Address, { uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); - MCOperand_CreateReg0(MI, (Rt)); - MCOperand_CreateReg0(MI, (Rs)); - MCOperand_CreateReg0(MI, (Rt)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); return MCDisassembler_Success; } @@ -1361,7 +1375,7 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_GPR64RegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -1372,7 +1386,7 @@ static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, { if (RegNo > 7) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_GPRMM16RegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -1383,7 +1397,7 @@ static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, { if (RegNo > 7) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_GPRMM16ZeroRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -1395,7 +1409,7 @@ static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, { if (RegNo > 7) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_GPRMM16MovePRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -1406,7 +1420,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, { if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_GPR32RegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -1435,7 +1449,7 @@ static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_FGR64RegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -1447,7 +1461,7 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_FGR32RegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -1458,7 +1472,7 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, { if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_CCRRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -1469,7 +1483,7 @@ static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, { if (RegNo > 7) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_FCCRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -1481,7 +1495,7 @@ static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_FGRCCRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -1493,8 +1507,8 @@ static DecodeStatus DecodeMem(MCInst *Inst, unsigned Insn, uint64_t Address, unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); if (MCInst_getOpcode(Inst) == Mips_SC || MCInst_getOpcode(Inst) == Mips_SCD) @@ -1514,8 +1528,8 @@ static DecodeStatus DecodeMemEVA(MCInst *Inst, unsigned Insn, uint64_t Address, unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); if (MCInst_getOpcode(Inst) == Mips_SCE) MCOperand_CreateReg0(Inst, (Reg)); @@ -1534,8 +1548,8 @@ static DecodeStatus DecodeLoadByte15(MCInst *Inst, unsigned Insn, unsigned Base = fieldFromInstruction_4(Insn, 16, 5); unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); - Base = Base; - Reg = Reg; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Base)); @@ -1551,7 +1565,7 @@ static DecodeStatus DecodeCacheOp(MCInst *Inst, unsigned Insn, uint64_t Address, unsigned Hint = fieldFromInstruction_4(Insn, 16, 5); unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Base = Base; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Base)); MCOperand_CreateImm0(Inst, (Offset)); @@ -1567,7 +1581,7 @@ static DecodeStatus DecodeCacheOpMM(MCInst *Inst, unsigned Insn, unsigned Base = fieldFromInstruction_4(Insn, 16, 5); unsigned Hint = fieldFromInstruction_4(Insn, 21, 5); - Base = Base; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Base)); MCOperand_CreateImm0(Inst, (Offset)); @@ -1583,7 +1597,7 @@ static DecodeStatus DecodePrefeOpMM(MCInst *Inst, unsigned Insn, unsigned Base = fieldFromInstruction_4(Insn, 16, 5); unsigned Hint = fieldFromInstruction_4(Insn, 21, 5); - Base = Base; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Base)); MCOperand_CreateImm0(Inst, (Offset)); @@ -1600,7 +1614,7 @@ static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, unsigned Insn, unsigned Hint = fieldFromInstruction_4(Insn, 16, 5); unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Base = Base; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Base)); MCOperand_CreateImm0(Inst, (Offset)); @@ -1615,7 +1629,7 @@ static DecodeStatus DecodeSyncI(MCInst *Inst, unsigned Insn, uint64_t Address, int Offset = SignExtend32((Insn & 0xffff), 16); unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Base = Base; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Base)); MCOperand_CreateImm0(Inst, (Offset)); @@ -1629,7 +1643,7 @@ static DecodeStatus DecodeSyncI_MM(MCInst *Inst, unsigned Insn, int Offset = SignExtend32((Insn & 0xffff), 16); unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Base = Base; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Base)); MCOperand_CreateImm0(Inst, (Offset)); @@ -1643,7 +1657,7 @@ static DecodeStatus DecodeSynciR6(MCInst *Inst, unsigned Insn, uint64_t Address, int Immediate = SignExtend32((Insn & 0xffff), 16); unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Base = Base; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Base)); MCOperand_CreateImm0(Inst, (Immediate)); @@ -1658,8 +1672,8 @@ static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, unsigned Reg = fieldFromInstruction_4(Insn, 6, 5); unsigned Base = fieldFromInstruction_4(Insn, 11, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_MSA128BRegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Base)); @@ -1760,7 +1774,7 @@ static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, unsigned Insn, unsigned Offset = Insn & 0x1F; unsigned Reg = fieldFromInstruction_4(Insn, 5, 5); - Reg = Reg; + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Mips_SP)); @@ -1775,7 +1789,7 @@ static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, unsigned Insn, unsigned Offset = Insn & 0x7F; unsigned Reg = fieldFromInstruction_4(Insn, 7, 3); - Reg = Reg; + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Mips_GP)); @@ -1816,8 +1830,8 @@ static DecodeStatus DecodeMemMMImm9(MCInst *Inst, unsigned Insn, unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); if (MCInst_getOpcode(Inst) == Mips_SCE_MM || MCInst_getOpcode(Inst) == Mips_SC_MMR6) @@ -1837,8 +1851,8 @@ static DecodeStatus DecodeMemMMImm12(MCInst *Inst, unsigned Insn, unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); switch (MCInst_getOpcode(Inst)) { case Mips_SWM32_MM: @@ -1872,8 +1886,8 @@ static DecodeStatus DecodeMemMMImm16(MCInst *Inst, unsigned Insn, unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Base)); @@ -1889,8 +1903,8 @@ static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, uint64_t Address, unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_FGR64RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Base)); @@ -1908,8 +1922,8 @@ static DecodeStatus DecodeFMemMMR2(MCInst *Inst, unsigned Insn, unsigned Base = fieldFromInstruction_4(Insn, 16, 5); unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_FGR64RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Base)); @@ -1925,8 +1939,8 @@ static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, uint64_t Address, unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_COP2RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Base)); @@ -1942,8 +1956,8 @@ static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, uint64_t Address, unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_COP3RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Base)); @@ -1959,8 +1973,8 @@ static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); unsigned Base = fieldFromInstruction_4(Insn, 11, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_COP2RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Base)); @@ -1976,8 +1990,8 @@ static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, unsigned Insn, unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Reg = Reg; - Base = Base; + Reg = getReg(Inst, Mips_COP2RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, (Reg)); MCOperand_CreateReg0(Inst, (Base)); @@ -1993,8 +2007,8 @@ static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, unsigned Insn, unsigned Rt = fieldFromInstruction_4(Insn, 16, 5); unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Rt = Rt; - Base = Base; + Rt = getReg(Inst, Mips_GPR32RegClassID, Rt); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); if (MCInst_getOpcode(Inst) == Mips_SC_R6 || MCInst_getOpcode(Inst) == Mips_SCD_R6) { @@ -2026,7 +2040,7 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 30 || RegNo % 2) return MCDisassembler_Fail; - unsigned Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo / 2); + unsigned Reg = getReg(Inst, Mips_AFGR64RegClassID, RegNo / 2); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2038,7 +2052,7 @@ static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo >= 4) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_ACC64DSPRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2050,7 +2064,7 @@ static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo >= 4) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_HI32DSPRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2062,7 +2076,7 @@ static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo >= 4) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_LO32DSPRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2074,7 +2088,7 @@ static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_MSA128BRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2086,7 +2100,7 @@ static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_MSA128HRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2098,7 +2112,7 @@ static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_MSA128WRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2110,7 +2124,7 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_MSA128DRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2122,7 +2136,7 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 7) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_MSACtrlRegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2134,7 +2148,7 @@ static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_COP0RegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2146,7 +2160,7 @@ static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler_Fail; - unsigned Reg = RegNo; + unsigned Reg = getReg(Inst, Mips_COP2RegClassID, RegNo); MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -2554,11 +2568,11 @@ static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, uint32_t insn, if (HasRs) MCOperand_CreateReg0( - MI, (Rs)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); if (HasRt) MCOperand_CreateReg0( - MI, (Rt)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateImm0(MI, (Imm)); @@ -2603,8 +2617,8 @@ static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, uint32_t insn, if (HasRs) MCOperand_CreateReg0( - MI, (Rs)); - MCOperand_CreateReg0(MI, (Rt)); + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); MCOperand_CreateImm0(MI, (Imm)); diff --git a/arch/Mips/MipsModule.c b/arch/Mips/MipsModule.c index 81f0d73efc4..c5dcb73e6ee 100644 --- a/arch/Mips/MipsModule.c +++ b/arch/Mips/MipsModule.c @@ -19,6 +19,7 @@ cs_err Mips_global_init(cs_struct *ud) ud->printer = Mips_printer; ud->printer_info = mri; + ud->getinsn_info = mri; ud->reg_name = Mips_reg_name; ud->insn_id = Mips_get_insn_id; ud->insn_name = Mips_insn_name;