diff --git a/.cargo/config.toml b/.cargo/config.toml index 7f591900..1de4da1a 100644 --- a/.cargo/config.toml +++ b/.cargo/config.toml @@ -10,19 +10,13 @@ rustflags = [ "-C", "link-arg=-nostartfiles", "-C", "link-arg=-Wl,-Tlinkall.x", "-C", "link-arg=-Trom_functions.x", +] - # tell the core library have atomics even though it's not specified in the target definition - "--cfg", "target_has_atomic_load_store", - "--cfg", 'target_has_atomic_load_store="8"', - "--cfg", 'target_has_atomic_load_store="16"', - "--cfg", 'target_has_atomic_load_store="32"', - "--cfg", 'target_has_atomic_load_store="ptr"', - # enable cas - "--cfg", "target_has_atomic", - "--cfg", 'target_has_atomic="8"', - "--cfg", 'target_has_atomic="16"', - "--cfg", 'target_has_atomic="32"', - "--cfg", 'target_has_atomic="ptr"', +[target.riscv32imac-unknown-none-elf] +rustflags = [ + "-C", "force-frame-pointers", + "-C", "link-arg=-Tlinkall.x", + "-C", "link-arg=-Trom_functions.x", ] [alias] diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 4152fba2..5337a288 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -21,7 +21,7 @@ jobs: build-fw: strategy: matrix: - version: ["v4"] + version: ["v4", "v6c6", "v6s3"] runs-on: ubuntu-latest diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml index c9d322ad..eb321af0 100644 --- a/.github/workflows/check.yml +++ b/.github/workflows/check.yml @@ -15,7 +15,11 @@ concurrency: group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }} jobs: - test: + check: + strategy: + matrix: + version: ["v4", "v6c6", "v6s3"] + runs-on: ubuntu-latest steps: @@ -31,7 +35,18 @@ jobs: run: cargo fmt --check - name: check - run: cargo xcheck + run: cargo xcheck ${{ matrix.version }} + + test: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + - uses: esp-rs/xtensa-toolchain@v1.5 + with: + default: true + buildtargets: esp32s3 + ldproxy: false + - uses: Swatinem/rust-cache@v2 - name: test run: cargo xtask test diff --git a/.github/workflows/merge.yml b/.github/workflows/merge.yml index c83b1128..4bd244a7 100644 --- a/.github/workflows/merge.yml +++ b/.github/workflows/merge.yml @@ -8,7 +8,11 @@ env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} jobs: - test: + build: + strategy: + matrix: + version: ["v4", "v6c6", "v6s3"] + runs-on: ubuntu-latest steps: @@ -24,11 +28,20 @@ jobs: - name: setup espflash run: cargo binstall --no-confirm --force cargo-espflash - - name: check - run: cargo xcheck + - name: build + run: cargo xbuild ${{ matrix.version }} + + test: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + - uses: esp-rs/xtensa-toolchain@v1.5 + with: + default: true + buildtargets: esp32s3 + ldproxy: false + - uses: Swatinem/rust-cache@v2 - name: test run: cargo xtask test - - - name: build - run: cargo xbuild + \ No newline at end of file diff --git a/.gitignore b/.gitignore index 5005086c..defc4869 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,4 @@ Cargo.lock .vscode/esp32s3.base.svd .vscode/launch.json .vscode/.cortex-debug.peripherals.state.json +cfg.toml \ No newline at end of file diff --git a/.vscode/esp32c6.base.svd b/.vscode/esp32c6.base.svd new file mode 100644 index 00000000..06d13e85 --- /dev/null +++ b/.vscode/esp32c6.base.svd @@ -0,0 +1,69036 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-C6 + ESP32 C-Series + 9 + 32-bit RISC-V MCU & 2.4 GHz Wi-Fi 6 & Bluetooth 5 (LE) & IEEE 802.15.4 + Copyright 2023 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + RV32IMAC + r0p0 + little + false + false + 0 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x60088000 + + 0x0 + 0xBC + registers + + + AES + 73 + + + + KEY_0 + Key material key_0 configure register + 0x0 + 0x20 + + + KEY_0 + This bits stores key_0 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_1 + Key material key_1 configure register + 0x4 + 0x20 + + + KEY_1 + This bits stores key_1 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_2 + Key material key_2 configure register + 0x8 + 0x20 + + + KEY_2 + This bits stores key_2 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_3 + Key material key_3 configure register + 0xC + 0x20 + + + KEY_3 + This bits stores key_3 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_4 + Key material key_4 configure register + 0x10 + 0x20 + + + KEY_4 + This bits stores key_4 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_5 + Key material key_5 configure register + 0x14 + 0x20 + + + KEY_5 + This bits stores key_5 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_6 + Key material key_6 configure register + 0x18 + 0x20 + + + KEY_6 + This bits stores key_6 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_7 + Key material key_7 configure register + 0x1C + 0x20 + + + KEY_7 + This bits stores key_7 that is a part of key material. + 0 + 32 + read-write + + + + + TEXT_IN_0 + source text material text_in_0 configure register + 0x20 + 0x20 + + + TEXT_IN_0 + This bits stores text_in_0 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_1 + source text material text_in_1 configure register + 0x24 + 0x20 + + + TEXT_IN_1 + This bits stores text_in_1 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_2 + source text material text_in_2 configure register + 0x28 + 0x20 + + + TEXT_IN_2 + This bits stores text_in_2 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_3 + source text material text_in_3 configure register + 0x2C + 0x20 + + + TEXT_IN_3 + This bits stores text_in_3 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_OUT_0 + result text material text_out_0 configure register + 0x30 + 0x20 + + + TEXT_OUT_0 + This bits stores text_out_0 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_1 + result text material text_out_1 configure register + 0x34 + 0x20 + + + TEXT_OUT_1 + This bits stores text_out_1 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_2 + result text material text_out_2 configure register + 0x38 + 0x20 + + + TEXT_OUT_2 + This bits stores text_out_2 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_3 + result text material text_out_3 configure register + 0x3C + 0x20 + + + TEXT_OUT_3 + This bits stores text_out_3 that is a part of result text material. + 0 + 32 + read-write + + + + + MODE + AES Mode register + 0x40 + 0x20 + + + MODE + This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + 0 + 3 + read-write + + + + + ENDIAN + AES Endian configure register + 0x44 + 0x20 + + + ENDIAN + endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian + 0 + 6 + read-write + + + + + TRIGGER + AES trigger register + 0x48 + 0x20 + + + TRIGGER + Set this bit to start AES calculation. + 0 + 1 + write-only + + + + + STATE + AES state register + 0x4C + 0x20 + + + STATE + Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. + 0 + 2 + read-only + + + + + 16 + 0x1 + IV_MEM[%s] + The memory that stores initialization vector + 0x50 + 0x8 + + + 16 + 0x1 + H_MEM[%s] + The memory that stores GCM hash subkey + 0x60 + 0x8 + + + 16 + 0x1 + J0_MEM[%s] + The memory that stores J0 + 0x70 + 0x8 + + + 16 + 0x1 + T0_MEM[%s] + The memory that stores T0 + 0x80 + 0x8 + + + DMA_ENABLE + DMA-AES working mode register + 0x90 + 0x20 + + + DMA_ENABLE + 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + 0 + 1 + read-write + + + + + BLOCK_MODE + AES cipher block mode register + 0x94 + 0x20 + + + BLOCK_MODE + Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + 0 + 3 + read-write + + + + + BLOCK_NUM + AES block number register + 0x98 + 0x20 + + + BLOCK_NUM + Those bits stores the number of Plaintext/ciphertext block. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function configure register + 0x9C + 0x20 + + + INC_SEL + This bit decides the standard incrementing function. 0: INC32. 1: INC128. + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + Additional Authential Data block number register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Those bits stores the number of AAD block. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + AES remainder bit number register + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Those bits stores the number of remainder bit. + 0 + 7 + read-write + + + + + CONTINUE + AES continue register + 0xA8 + 0x20 + + + CONTINUE + Set this bit to continue GCM operation. + 0 + 1 + write-only + + + + + INT_CLEAR + AES Interrupt clear register + 0xAC + 0x20 + + + INT_CLEAR + Set this bit to clear the AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + AES Interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + 0 + 1 + read-write + + + + + DATE + AES version control register + 0xB4 + 0x20 + 0x20191210 + + + DATE + This bits stores the version information of AES. + 0 + 30 + read-write + + + + + DMA_EXIT + AES-DMA exit config + 0xB8 + 0x20 + + + DMA_EXIT + Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer. + 0 + 1 + write-only + + + + + + + APB_SARADC + SAR (Successive Approximation Register) Analog-to-Digital Converter + APB_SARADC + 0x6000E000 + + 0x0 + 0x70 + registers + + + APB_SARADC + 60 + + + + CTRL + digital saradc configure register + 0x0 + 0x20 + 0x40038240 + + + SARADC_START_FORCE + select software enable saradc sample + 0 + 1 + read-write + + + SARADC_START + software enable saradc sample + 1 + 1 + read-write + + + SARADC_SAR_CLK_GATED + SAR clock gated + 6 + 1 + read-write + + + SARADC_SAR_CLK_DIV + SAR clock divider + 7 + 8 + read-write + + + SARADC_SAR_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 15 + 3 + read-write + + + SARADC_SAR_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 23 + 1 + read-write + + + SARADC_XPD_SAR_FORCE + force option to xpd sar blocks + 27 + 2 + read-write + + + SARADC2_PWDET_DRV + enable saradc2 power detect driven func. + 29 + 1 + read-write + + + SARADC_WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + digital saradc configure register + 0x4 + 0x20 + 0x0000A1FE + + + SARADC_MEAS_NUM_LIMIT + enable max meas num + 0 + 1 + read-write + + + SARADC_MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SARADC_SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SARADC_SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + SARADC_TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + SARADC_TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + digital saradc configure register + 0x8 + 0x20 + + + APB_SARADC_FILTER_FACTOR1 + Factor of saradc filter1 + 26 + 3 + read-write + + + APB_SARADC_FILTER_FACTOR0 + Factor of saradc filter0 + 29 + 3 + read-write + + + + + FSM_WAIT + digital saradc configure register + 0xC + 0x20 + 0x00FF0808 + + + SARADC_XPD_WAIT + saradc_xpd_wait + 0 + 8 + read-write + + + SARADC_RSTB_WAIT + saradc_rstb_wait + 8 + 8 + read-write + + + SARADC_STANDBY_WAIT + saradc_standby_wait + 16 + 8 + read-write + + + + + SAR1_STATUS + digital saradc configure register + 0x10 + 0x20 + 0x20000000 + + + SARADC_SAR1_STATUS + saradc1 status about data and channel + 0 + 32 + read-only + + + + + SAR2_STATUS + digital saradc configure register + 0x14 + 0x20 + 0x20000000 + + + SARADC_SAR2_STATUS + saradc2 status about data and channel + 0 + 32 + read-only + + + + + SAR_PATT_TAB1 + digital saradc configure register + 0x18 + 0x20 + 0x00FFFFFF + + + SARADC_SAR_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR_PATT_TAB2 + digital saradc configure register + 0x1C + 0x20 + 0x00FFFFFF + + + SARADC_SAR_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + ONETIME_SAMPLE + digital saradc configure register + 0x20 + 0x20 + 0x1A000000 + + + SARADC_ONETIME_ATTEN + configure onetime atten + 23 + 2 + read-write + + + SARADC_ONETIME_CHANNEL + configure onetime channel + 25 + 4 + read-write + + + SARADC_ONETIME_START + trigger adc onetime sample + 29 + 1 + read-write + + + SARADC2_ONETIME_SAMPLE + enable adc2 onetime sample + 30 + 1 + read-write + + + SARADC1_ONETIME_SAMPLE + enable adc1 onetime sample + 31 + 1 + read-write + + + + + ARB_CTRL + digital saradc configure register + 0x24 + 0x20 + 0x00000900 + + + ADC_ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ADC_ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ADC_ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ADC_ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ADC_ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ADC_ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ADC_ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ADC_ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + digital saradc configure register + 0x28 + 0x20 + 0x03740000 + + + APB_SARADC_FILTER_CHANNEL1 + configure filter1 to adc channel + 18 + 4 + read-write + + + APB_SARADC_FILTER_CHANNEL0 + configure filter0 to adc channel + 22 + 4 + read-write + + + APB_SARADC_FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + SAR1DATA_STATUS + digital saradc configure register + 0x2C + 0x20 + + + APB_SARADC1_DATA + saradc1 data + 0 + 17 + read-only + + + + + SAR2DATA_STATUS + digital saradc configure register + 0x30 + 0x20 + + + APB_SARADC2_DATA + saradc2 data + 0 + 17 + read-only + + + + + THRES0_CTRL + digital saradc configure register + 0x34 + 0x20 + 0x0003FFED + + + APB_SARADC_THRES0_CHANNEL + configure thres0 to adc channel + 0 + 4 + read-write + + + APB_SARADC_THRES0_HIGH + saradc thres0 monitor thres + 5 + 13 + read-write + + + APB_SARADC_THRES0_LOW + saradc thres0 monitor thres + 18 + 13 + read-write + + + + + THRES1_CTRL + digital saradc configure register + 0x38 + 0x20 + 0x0003FFED + + + APB_SARADC_THRES1_CHANNEL + configure thres1 to adc channel + 0 + 4 + read-write + + + APB_SARADC_THRES1_HIGH + saradc thres1 monitor thres + 5 + 13 + read-write + + + APB_SARADC_THRES1_LOW + saradc thres1 monitor thres + 18 + 13 + read-write + + + + + THRES_CTRL + digital saradc configure register + 0x3C + 0x20 + + + APB_SARADC_THRES_ALL_EN + enable thres to all channel + 27 + 1 + read-write + + + APB_SARADC_THRES1_EN + enable thres1 + 30 + 1 + read-write + + + APB_SARADC_THRES0_EN + enable thres0 + 31 + 1 + read-write + + + + + INT_ENA + digital saradc int register + 0x40 + 0x20 + + + APB_SARADC_TSENS_INT_ENA + tsens low interrupt enable + 25 + 1 + read-write + + + APB_SARADC_THRES1_LOW_INT_ENA + saradc thres1 low interrupt enable + 26 + 1 + read-write + + + APB_SARADC_THRES0_LOW_INT_ENA + saradc thres0 low interrupt enable + 27 + 1 + read-write + + + APB_SARADC_THRES1_HIGH_INT_ENA + saradc thres1 high interrupt enable + 28 + 1 + read-write + + + APB_SARADC_THRES0_HIGH_INT_ENA + saradc thres0 high interrupt enable + 29 + 1 + read-write + + + APB_SARADC2_DONE_INT_ENA + saradc2 done interrupt enable + 30 + 1 + read-write + + + APB_SARADC1_DONE_INT_ENA + saradc1 done interrupt enable + 31 + 1 + read-write + + + + + INT_RAW + digital saradc int register + 0x44 + 0x20 + + + APB_SARADC_TSENS_INT_RAW + saradc tsens interrupt raw + 25 + 1 + read-write + + + APB_SARADC_THRES1_LOW_INT_RAW + saradc thres1 low interrupt raw + 26 + 1 + read-write + + + APB_SARADC_THRES0_LOW_INT_RAW + saradc thres0 low interrupt raw + 27 + 1 + read-write + + + APB_SARADC_THRES1_HIGH_INT_RAW + saradc thres1 high interrupt raw + 28 + 1 + read-write + + + APB_SARADC_THRES0_HIGH_INT_RAW + saradc thres0 high interrupt raw + 29 + 1 + read-write + + + APB_SARADC2_DONE_INT_RAW + saradc2 done interrupt raw + 30 + 1 + read-write + + + APB_SARADC1_DONE_INT_RAW + saradc1 done interrupt raw + 31 + 1 + read-write + + + + + INT_ST + digital saradc int register + 0x48 + 0x20 + + + APB_SARADC_TSENS_INT_ST + saradc tsens interrupt state + 25 + 1 + read-only + + + APB_SARADC_THRES1_LOW_INT_ST + saradc thres1 low interrupt state + 26 + 1 + read-only + + + APB_SARADC_THRES0_LOW_INT_ST + saradc thres0 low interrupt state + 27 + 1 + read-only + + + APB_SARADC_THRES1_HIGH_INT_ST + saradc thres1 high interrupt state + 28 + 1 + read-only + + + APB_SARADC_THRES0_HIGH_INT_ST + saradc thres0 high interrupt state + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + saradc2 done interrupt state + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + saradc1 done interrupt state + 31 + 1 + read-only + + + + + INT_CLR + digital saradc int register + 0x4C + 0x20 + + + APB_SARADC_TSENS_INT_CLR + saradc tsens interrupt clear + 25 + 1 + write-only + + + APB_SARADC_THRES1_LOW_INT_CLR + saradc thres1 low interrupt clear + 26 + 1 + write-only + + + APB_SARADC_THRES0_LOW_INT_CLR + saradc thres0 low interrupt clear + 27 + 1 + write-only + + + APB_SARADC_THRES1_HIGH_INT_CLR + saradc thres1 high interrupt clear + 28 + 1 + write-only + + + APB_SARADC_THRES0_HIGH_INT_CLR + saradc thres0 high interrupt clear + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + saradc2 done interrupt clear + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + saradc1 done interrupt clear + 31 + 1 + write-only + + + + + DMA_CONF + digital saradc configure register + 0x50 + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + CLKM_CONF + digital saradc configure register + 0x54 + 0x20 + 0x00000004 + + + CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + CLKM_DIV_B + Fractional clock divider numerator value + 8 + 6 + read-write + + + CLKM_DIV_A + Fractional clock divider denominator value + 14 + 6 + read-write + + + CLK_EN + reg clk en + 20 + 1 + read-write + + + CLK_SEL + Set this bit to enable clk_apll + 21 + 2 + read-write + + + + + APB_TSENS_CTRL + digital tsens configure register + 0x58 + 0x20 + 0x00018080 + + + TSENS_OUT + temperature sensor data out + 0 + 8 + read-only + + + TSENS_IN_INV + invert temperature sensor data + 13 + 1 + read-write + + + TSENS_CLK_DIV + temperature sensor clock divider + 14 + 8 + read-write + + + TSENS_PU + temperature sensor power up + 22 + 1 + read-write + + + + + TSENS_CTRL2 + digital tsens configure register + 0x5C + 0x20 + 0x00004002 + + + TSENS_XPD_WAIT + the time that power up tsens need wait + 0 + 12 + read-write + + + TSENS_XPD_FORCE + force power up tsens + 12 + 2 + read-write + + + TSENS_CLK_INV + inv tsens clk + 14 + 1 + read-write + + + TSENS_CLK_SEL + tsens clk select + 15 + 1 + read-write + + + + + CALI + digital saradc configure register + 0x60 + 0x20 + 0x00008000 + + + APB_SARADC_CALI_CFG + saradc cali factor + 0 + 17 + read-write + + + + + APB_TSENS_WAKE + digital tsens configure register + 0x64 + 0x20 + 0x0000FF00 + + + WAKEUP_TH_LOW + reg_wakeup_th_low + 0 + 8 + read-write + + + WAKEUP_TH_HIGH + reg_wakeup_th_high + 8 + 8 + read-write + + + WAKEUP_OVER_UPPER_TH + reg_wakeup_over_upper_th + 16 + 1 + read-only + + + WAKEUP_MODE + reg_wakeup_mode + 17 + 1 + read-write + + + WAKEUP_EN + reg_wakeup_en + 18 + 1 + read-write + + + + + APB_TSENS_SAMPLE + digital tsens configure register + 0x68 + 0x20 + 0x00000014 + + + TSENS_SAMPLE_RATE + HW sample rate + 0 + 16 + read-write + + + TSENS_SAMPLE_EN + HW sample en + 16 + 1 + read-write + + + + + CTRL_DATE + version + 0x3FC + 0x20 + 0x02206240 + + + DATE + version + 0 + 32 + read-write + + + + + + + ASSIST_DEBUG + Debug Assist + ASSIST_DEBUG + 0x600C2000 + + 0x0 + 0x80 + registers + + + ASSIST_DEBUG + 26 + + + + CORE_0_MONTR_ENA + core0 monitor enable configuration register + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + Core0 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + Core0 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_ENA + Core0 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_ENA + Core0 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_ENA + Core0 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_ENA + Core0 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_ENA + Core0 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_ENA + Core0 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_ENA + Core0 stackpoint underflow monitor enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_ENA + Core0 stackpoint overflow monitor enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_RAW + core0 monitor interrupt status register + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + Core0 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + Core0 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_RD_RAW + Core0 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_WR_RAW + Core0 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_0_AREA_PIF_0_RD_RAW + Core0 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_0_AREA_PIF_0_WR_RAW + Core0 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_0_AREA_PIF_1_RD_RAW + Core0 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_0_AREA_PIF_1_WR_RAW + Core0 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_0_SP_SPILL_MIN_RAW + Core0 stackpoint underflow monitor interrupt status + 8 + 1 + read-only + + + CORE_0_SP_SPILL_MAX_RAW + Core0 stackpoint overflow monitor interrupt status + 9 + 1 + read-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_0_INTR_ENA + core0 monitor interrupt enable register + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_INTR_ENA + Core0 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_INTR_ENA + Core0 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_INTR_ENA + Core0 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_INTR_ENA + Core0 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_INTR_ENA + Core0 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_INTR_ENA + Core0 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_INTR_ENA + Core0 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_INTR_ENA + Core0 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_INTR_ENA + Core0 stackpoint underflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_INTR_ENA + Core0 stackpoint overflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_CLR + core0 monitor interrupt clr register + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + Core0 dram0 area0 read monitor interrupt clr + 0 + 1 + write-only + + + CORE_0_AREA_DRAM0_0_WR_CLR + Core0 dram0 area0 write monitor interrupt clr + 1 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_RD_CLR + Core0 dram0 area1 read monitor interrupt clr + 2 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_WR_CLR + Core0 dram0 area1 write monitor interrupt clr + 3 + 1 + write-only + + + CORE_0_AREA_PIF_0_RD_CLR + Core0 PIF area0 read monitor interrupt clr + 4 + 1 + write-only + + + CORE_0_AREA_PIF_0_WR_CLR + Core0 PIF area0 write monitor interrupt clr + 5 + 1 + write-only + + + CORE_0_AREA_PIF_1_RD_CLR + Core0 PIF area1 read monitor interrupt clr + 6 + 1 + write-only + + + CORE_0_AREA_PIF_1_WR_CLR + Core0 PIF area1 write monitor interrupt clr + 7 + 1 + write-only + + + CORE_0_SP_SPILL_MIN_CLR + Core0 stackpoint underflow monitor interrupt clr + 8 + 1 + write-only + + + CORE_0_SP_SPILL_MAX_CLR + Core0 stackpoint overflow monitor interrupt clr + 9 + 1 + write-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + write-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + write-only + + + + + CORE_0_AREA_DRAM0_0_MIN + core0 dram0 region0 addr configuration register + 0x10 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_0_MIN + Core0 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_0_MAX + core0 dram0 region0 addr configuration register + 0x14 + 0x20 + + + CORE_0_AREA_DRAM0_0_MAX + Core0 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MIN + core0 dram0 region1 addr configuration register + 0x18 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_1_MIN + Core0 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MAX + core0 dram0 region1 addr configuration register + 0x1C + 0x20 + + + CORE_0_AREA_DRAM0_1_MAX + Core0 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MIN + core0 PIF region0 addr configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_0_MIN + Core0 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MAX + core0 PIF region0 addr configuration register + 0x24 + 0x20 + + + CORE_0_AREA_PIF_0_MAX + Core0 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MIN + core0 PIF region1 addr configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_1_MIN + Core0 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MAX + core0 PIF region1 addr configuration register + 0x2C + 0x20 + + + CORE_0_AREA_PIF_1_MAX + Core0 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PC + core0 area pc status register + 0x30 + 0x20 + + + CORE_0_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_AREA_SP + core0 area sp status register + 0x34 + 0x20 + + + CORE_0_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_SP_MIN + stack min value + 0x38 + 0x20 + + + CORE_0_SP_MIN + core0 sp region configuration regsiter + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + stack max value + 0x3C + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + core0 sp pc status register + 0 + 32 + read-write + + + + + CORE_0_SP_PC + stack monitor pc status register + 0x40 + 0x20 + + + CORE_0_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only + + + + + CORE_0_RCD_EN + record enable configuration register + 0x44 + 0x20 + + + CORE_0_RCD_RECORDEN + Set 1 to enable record PC + 0 + 1 + read-write + + + CORE_0_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGPC + record status regsiter + 0x48 + 0x20 + + + CORE_0_RCD_PDEBUGPC + recorded PC + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSP + record status regsiter + 0x4C + 0x20 + + + CORE_0_RCD_PDEBUGSP + recorded sp + 0 + 32 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 + 0x50 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_0 + reg_core_0_iram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + reg_core_0_iram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + reg_core_0_iram0_recording_loadstore_0 + 25 + 1 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 + 0x54 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_1 + reg_core_0_iram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + reg_core_0_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + reg_core_0_iram0_recording_loadstore_1 + 25 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 + 0x58 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_0 + reg_core_0_dram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_DRAM0_RECORDING_WR_0 + reg_core_0_dram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + reg_core_0_dram0_recording_byteen_0 + 25 + 4 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 + 0x5C + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_0 + reg_core_0_dram0_recording_pc_0 + 0 + 32 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 + 0x60 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_1 + reg_core_0_dram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_DRAM0_RECORDING_WR_1 + reg_core_0_dram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + reg_core_0_dram0_recording_byteen_1 + 25 + 4 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 + 0x64 + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_1 + reg_core_0_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register6 + 0x68 + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + reg_core_x_iram0_dram0_limit_cycle_0 + 0 + 20 + read-write + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register7 + 0x6C + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + reg_core_x_iram0_dram0_limit_cycle_1 + 0 + 20 + read-write + + + + + C0RE_0_LASTPC_BEFORE_EXCEPTION + cpu status register + 0x70 + 0x20 + + + CORE_0_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + C0RE_0_DEBUG_MODE + cpu status register + 0x74 + 0x20 + + + CORE_0_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_0_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CLOCK_GATE + clock register + 0x78 + 0x20 + 0x00000001 + + + CLK_EN + Set 1 force on the clock gate + 0 + 1 + read-write + + + + + DATE + version register + 0x3FC + 0x20 + 0x02109130 + + + ASSIST_DEBUG_DATE + version register + 0 + 28 + read-write + + + + + + + ATOMIC + Atomic Locker + ATOMIC + 0x60011000 + + 0x0 + 0x14 + registers + + + + ADDR_LOCK + hardware lock regsiter + 0x0 + 0x20 + + + LOCK + read to acquire hardware lock, write to release hardware lock + 0 + 2 + read-write + + + + + LR_ADDR + gloable lr address regsiter + 0x4 + 0x20 + + + GLOABLE_LR_ADDR + backup gloable address + 0 + 32 + read-write + + + + + LR_VALUE + gloable lr value regsiter + 0x8 + 0x20 + + + GLOABLE_LR_VALUE + backup gloable value + 0 + 32 + read-write + + + + + LOCK_STATUS + lock status regsiter + 0xC + 0x20 + + + LOCK_STATUS + read hareware lock status for debug + 0 + 2 + read-only + + + + + COUNTER + wait counter register + 0x10 + 0x20 + + + WAIT_COUNTER + delay counter + 0 + 16 + read-write + + + + + + + DMA + DMA (Direct Memory Access) Controller + DMA + 0x60080000 + + 0x0 + 0x1A4 + registers + + + DMA_IN_CH0 + 66 + + + DMA_IN_CH1 + 67 + + + DMA_IN_CH2 + 68 + + + DMA_OUT_CH0 + 69 + + + DMA_OUT_CH1 + 70 + + + DMA_OUT_CH2 + 71 + + + + 3 + 0x10 + IN_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x0 + 0x20 + + + IN_DONE + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-write + + + IN_SUC_EOF + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-write + + + IN_ERR_EOF + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + 2 + 1 + read-write + + + IN_DSCR_ERR + The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write + + + IN_DSCR_EMPTY + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + 4 + 1 + read-write + + + INFIFO_OVF + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 5 + 1 + read-write + + + INFIFO_UDF + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 6 + 1 + read-write + + + + + 3 + 0x10 + IN_INT_ST_CH%s + Masked interrupt of channel 0 + 0x4 + 0x20 + + + IN_DONE + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_OVF + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_UDF + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + + + 3 + 0x10 + IN_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x8 + 0x20 + + + IN_DONE + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_OVF + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_UDF + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + + + 3 + 0x10 + IN_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0xC + 0x20 + + + IN_DONE + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_OVF + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_UDF + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + + + 3 + 0x10 + OUT_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x30 + 0x20 + + + OUT_DONE + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR + The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 5 + 1 + read-write + + + + + 3 + 0x10 + OUT_INT_ST_CH%s + Masked interrupt of channel 0 + 0x34 + 0x20 + + + OUT_DONE + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + + + 3 + 0x10 + OUT_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x38 + 0x20 + + + OUT_DONE + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + + + 3 + 0x10 + OUT_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0x3C + 0x20 + + + OUT_DONE + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + + + AHB_TEST + reserved + 0x60 + 0x20 + + + AHB_TESTMODE + reserved + 0 + 3 + read-write + + + AHB_TESTADDR + reserved + 4 + 2 + read-write + + + + + MISC_CONF + MISC register + 0x64 + 0x20 + + + AHBM_RST_INTER + Set this bit then clear this bit to reset the internal ahb FSM. + 0 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 3 + 1 + read-write + + + + + DATE + Version control register + 0x68 + 0x20 + 0x02202250 + + + DATE + register version. + 0 + 32 + read-write + + + + + 3 + 0xC0 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x70 + 0x20 + + + IN_RST + This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN + Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + 4 + 1 + read-write + + + IN_ETM_EN + Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. + 5 + 1 + read-write + + + + + 3 + 0xC0 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x74 + 0x20 + + + IN_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0xC0 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x78 + 0x20 + 0x07800003 + + + INFIFO_FULL + L1 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_EMPTY + L1 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_CNT + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + IN_REMAIN_UNDER_1B + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B + reserved + 26 + 1 + read-only + + + IN_BUF_HUNGRY + reserved + 27 + 1 + read-only + + + + + 3 + 0xC0 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x7C + 0x20 + 0x00000800 + + + INFIFO_RDATA + This register stores the data popping from DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP + Set this bit to pop data from DMA FIFO. + 12 + 1 + write-only + + + + + 3 + 0xC0 + IN_LINK_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x80 + 0x20 + 0x01100000 + + + INLINK_ADDR + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET + Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + write-only + + + INLINK_START + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + write-only + + + INLINK_RESTART + Set this bit to mount a new inlink descriptor. + 23 + 1 + write-only + + + INLINK_PARK + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + 3 + 0xC0 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x84 + 0x20 + + + INLINK_DSCR_ADDR + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE + reserved + 18 + 2 + read-only + + + IN_STATE + reserved + 20 + 3 + read-only + + + + + 3 + 0xC0 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x88 + 0x20 + + + IN_SUC_EOF_DES_ADDR + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x8C + 0x20 + + + IN_ERR_EOF_DES_ADDR + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x90 + 0x20 + + + INLINK_DSCR + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x94 + 0x20 + + + INLINK_DSCR_BF0 + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x98 + 0x20 + + + INLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x9C + 0x20 + + + RX_PRI + The priority of Rx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + + + 3 + 0xC0 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0xA0 + 0x20 + 0x0000003F + + + PERI_IN_SEL + This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy + 0 + 6 + read-write + + + + + 3 + 0xC0 + OUT_CONF1_CH%s + Configure 1 register of Tx channel 0 + 0xD4 + 0x20 + + + OUT_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0xC0 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel 0 + 0xD8 + 0x20 + 0x07800002 + + + OUTFIFO_FULL + L1 Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_CNT + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 2 + 6 + read-only + + + OUT_REMAIN_UNDER_1B + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B + reserved + 26 + 1 + read-only + + + + + 3 + 0xC0 + OUT_PUSH_CH%s + Push control register of Rx channel 0 + 0xDC + 0x20 + + + OUTFIFO_WDATA + This register stores the data that need to be pushed into DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH + Set this bit to push data into DMA FIFO. + 9 + 1 + write-only + + + + + 3 + 0xC0 + OUT_LINK_CH%s + Link descriptor configure and control register of Tx channel 0 + 0xE0 + 0x20 + 0x00800000 + + + OUTLINK_ADDR + This register stores the 20 least significant bits of the first outlink descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + write-only + + + OUTLINK_START + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + write-only + + + OUTLINK_RESTART + Set this bit to restart a new outlink from the last address. + 22 + 1 + write-only + + + OUTLINK_PARK + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + 3 + 0xC0 + OUT_STATE_CH%s + Transmit status of Tx channel 0 + 0xE4 + 0x20 + + + OUTLINK_DSCR_ADDR + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE + reserved + 18 + 2 + read-only + + + OUT_STATE + reserved + 20 + 3 + read-only + + + + + 3 + 0xC0 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel 0 + 0xE8 + 0x20 + + + OUT_EOF_DES_ADDR + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel 0 + 0xEC + 0x20 + + + OUT_EOF_BFR_DES_ADDR + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_CH%s + Current inlink descriptor address of Tx channel 0 + 0xF0 + 0x20 + + + OUTLINK_DSCR + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_BF0_CH%s + The last inlink descriptor address of Tx channel 0 + 0xF4 + 0x20 + + + OUTLINK_DSCR_BF0 + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Tx channel 0 + 0xF8 + 0x20 + + + OUTLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_PRI_CH%s + Priority register of Tx channel 0. + 0xFC + 0x20 + + + TX_PRI + The priority of Tx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + + + 3 + 0xC0 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel 0 + 0x100 + 0x20 + 0x0000003F + + + PERI_OUT_SEL + This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy + 0 + 6 + read-write + + + + + 3 + 0xC0 + OUT_CONF0_CH%s + Configure 0 register of Tx channel 1 + 0x190 + 0x20 + 0x00000008 + + + OUT_RST + This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + OUT_ETM_EN + Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task. + 6 + 1 + read-write + + + + + + + DS + Digital Signature + DS + 0x6008C000 + + 0x0 + 0xA5C + registers + + + + 512 + 0x1 + Y_MEM[%s] + memory that stores Y + 0x0 + 0x8 + + + 512 + 0x1 + M_MEM[%s] + memory that stores M + 0x200 + 0x8 + + + 512 + 0x1 + RB_MEM[%s] + memory that stores Rb + 0x400 + 0x8 + + + 48 + 0x1 + BOX_MEM[%s] + memory that stores BOX + 0x600 + 0x8 + + + 16 + 0x1 + IV_MEM[%s] + memory that stores IV + 0x630 + 0x8 + + + 512 + 0x1 + X_MEM[%s] + memory that stores X + 0x800 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + memory that stores Z + 0xA00 + 0x8 + + + SET_START + DS start control register + 0xE00 + 0x20 + + + SET_START + set this bit to start DS operation. + 0 + 1 + write-only + + + + + SET_CONTINUE + DS continue control register + 0xE04 + 0x20 + + + SET_CONTINUE + set this bit to continue DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + DS finish control register + 0xE08 + 0x20 + + + SET_FINISH + Set this bit to finish DS process. + 0 + 1 + write-only + + + + + QUERY_BUSY + DS query busy register + 0xE0C + 0x20 + + + QUERY_BUSY + digital signature state. 1'b0: idle, 1'b1: busy + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + DS query key-wrong counter register + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + digital signature key wrong counter + 0 + 4 + read-only + + + + + QUERY_CHECK + DS query check result register + 0xE14 + 0x20 + + + MD_ERROR + MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + 0 + 1 + read-only + + + PADDING_BAD + padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + 1 + 1 + read-only + + + + + DATE + DS version control register + 0xE20 + 0x20 + 0x20200618 + + + DATE + ds version information + 0 + 30 + read-write + + + + + + + ECC + ECC (ECC Hardware Accelerator) + ECC + 0x6008B000 + + 0x0 + 0x78 + registers + + + ECC + 76 + + + + MULT_INT_RAW + ECC interrupt raw register, valid in level. + 0xC + 0x20 + + + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ST + ECC interrupt status register. + 0x10 + 0x20 + + + CALC_DONE_INT_ST + The masked interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ENA + ECC interrupt enable register. + 0x14 + 0x20 + + + CALC_DONE_INT_ENA + The interrupt enable bit for the ecc_calc_done_int interrupt + 0 + 1 + read-write + + + + + MULT_INT_CLR + ECC interrupt clear register. + 0x18 + 0x20 + + + CALC_DONE_INT_CLR + Set this bit to clear the ecc_calc_done_int interrupt + 0 + 1 + write-only + + + + + MULT_CONF + ECC configure register + 0x1C + 0x20 + 0x80000000 + + + START + Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. + 0 + 1 + read-write + + + RESET + Write 1 to reset ECC Accelerator. + 1 + 1 + write-only + + + KEY_LENGTH + The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + SECURITY_MODE + Reserved + 3 + 1 + read-write + + + CLK_EN + Write 1 to force on register clock gate. + 4 + 1 + read-write + + + WORK_MODE + The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. + 5 + 3 + read-write + + + VERIFICATION_RESULT + The verification result bit of ECC Accelerator, only valid when calculation is done. + 8 + 1 + read-only + + + MEM_CLOCK_GATE_FORCE_ON + ECC memory clock gate force on register + 31 + 1 + read-write + + + + + MULT_DATE + Version control register + 0xFC + 0x20 + 0x02201240 + + + DATE + ECC mult version control register + 0 + 28 + read-write + + + + + 32 + 0x1 + K_MEM[%s] + The memory that stores k. + 0x100 + 0x8 + + + 32 + 0x1 + PX_MEM[%s] + The memory that stores Px. + 0x120 + 0x8 + + + 32 + 0x1 + PY_MEM[%s] + The memory that stores Py. + 0x140 + 0x8 + + + + + EFUSE + eFuse Controller + EFUSE + 0x600B0800 + + 0x0 + 0x1D0 + registers + + + EFUSE + 14 + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + Configures the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + Configures the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + Configures the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + Configures the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + Configures the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + Configures the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + Configures the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + Configures the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + Configures the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + Configures the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + Configures the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. + 0 + 7 + read-only + + + SWAP_UART_SDIO_EN + Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped. + 7 + 1 + read-only + + + DIS_ICACHE + Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + 8 + 1 + read-only + + + DIS_USB_JTAG + Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE + Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG + Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS + Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled. + 13 + 1 + read-only + + + DIS_CAN + Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE + Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. + 15 + 1 + read-only + + + SOFT_DIS_JTAG + Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. + 16 + 3 + read-only + + + DIS_PAD_JTAG + Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. + 20 + 1 + read-only + + + USB_DREFH + Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + 21 + 2 + read-only + + + USB_DREFL + Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + 23 + 2 + read-only + + + USB_EXCHG_PINS + Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + 25 + 1 + read-only + + + VDD_SPI_AS_GPIO + Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned. + 26 + 1 + read-only + + + RPT4_RESERVED0_2 + Reserved. + 27 + 2 + read-only + + + RPT4_RESERVED0_1 + Reserved. + 29 + 1 + read-only + + + RPT4_RESERVED0_0 + Reserved. + 30 + 2 + read-only + + + + + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 + 0x20 + + + RPT4_RESERVED1_0 + Reserved. + 0 + 16 + read-only + + + WDT_DELAY_SEL + Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Represents the purpose of Key0. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Represents the purpose of Key1. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 + 0x20 + 0x00080000 + + + KEY_PURPOSE_2 + Represents the purpose of Key2. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Represents the purpose of Key3. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Represents the purpose of Key4. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Represents the purpose of Key5. + 12 + 4 + read-only + + + DPA_SEC_LEVEL + Represents the spa secure level by configuring the clock random divide mode. + 16 + 2 + read-only + + + RPT4_RESERVED2_1 + Reserved. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE + Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + 19 + 1 + read-only + + + SECURE_BOOT_EN + Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + RPT4_RESERVED2_0 + Reserved. + 22 + 6 + read-only + + + FLASH_TPUW + Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT + Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + 1 + 1 + read-only + + + DIS_USB_PRINT + Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 2 + 1 + read-only + + + RPT4_RESERVED3_5 + Reserved. + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Represents whether security download is enabled or disabled. 1: enabled. 0: disabled. + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. + 6 + 2 + read-only + + + RPT4_RESERVED3_4 + Reserved. + 8 + 1 + read-only + + + RPT4_RESERVED3_3 + Reserved. + 9 + 1 + read-only + + + RPT4_RESERVED3_2 + Reserved. + 10 + 2 + read-only + + + RPT4_RESERVED3_1 + Reserved. + 12 + 1 + read-only + + + FORCE_SEND_RESUME + Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced. + 13 + 1 + read-only + + + SECURE_VERSION + Represents the version used by ESP-IDF anti-rollback feature. + 14 + 16 + read-only + + + SECURE_BOOT_DISABLE_FAST_WAKE + Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled. + 30 + 1 + read-only + + + RPT4_RESERVED3_0 + Reserved. + 31 + 1 + read-only + + + + + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 + 0x20 + + + RPT4_RESERVED4_1 + Reserved. + 0 + 24 + read-only + + + RPT4_RESERVED4_0 + Reserved. + 24 + 8 + read-only + + + + + RD_MAC_SPI_SYS_0 + BLOCK1 data register $n. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_1 + BLOCK1 data register $n. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + MAC_EXT + Stores the extended bits of MAC address. + 16 + 16 + read-only + + + + + RD_MAC_SPI_SYS_2 + BLOCK1 data register $n. + 0x4C + 0x20 + + + MAC_SPI_RESERVED + Reserved. + 0 + 14 + read-only + + + SPI_PAD_CONF_1 + Stores the first part of SPI_PAD_CONF. + 14 + 18 + read-only + + + + + RD_MAC_SPI_SYS_3 + BLOCK1 data register $n. + 0x50 + 0x20 + + + SPI_PAD_CONF_2 + Stores the second part of SPI_PAD_CONF. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the first 14 bits of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SPI_SYS_4 + BLOCK1 data register $n. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the first 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_5 + BLOCK1 data register $n. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA0 + Register $n of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA1 + Register $n of BLOCK2 (system). + 0x60 + 0x20 + + + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA2 + Register $n of BLOCK2 (system). + 0x64 + 0x20 + + + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA3 + Register $n of BLOCK2 (system). + 0x68 + 0x20 + + + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA4 + Register $n of BLOCK2 (system). + 0x6C + 0x20 + + + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA5 + Register $n of BLOCK2 (system). + 0x70 + 0x20 + + + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA6 + Register $n of BLOCK2 (system). + 0x74 + 0x20 + + + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA7 + Register $n of BLOCK2 (system). + 0x78 + 0x20 + + + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_USR_DATA0 + Register $n of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA1 + Register $n of BLOCK3 (user). + 0x80 + 0x20 + + + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA2 + Register $n of BLOCK3 (user). + 0x84 + 0x20 + + + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA3 + Register $n of BLOCK3 (user). + 0x88 + 0x20 + + + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA4 + Register $n of BLOCK3 (user). + 0x8C + 0x20 + + + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA5 + Register $n of BLOCK3 (user). + 0x90 + 0x20 + + + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA6 + Register $n of BLOCK3 (user). + 0x94 + 0x20 + + + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA7 + Register $n of BLOCK3 (user). + 0x98 + 0x20 + + + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_KEY0_DATA0 + Register $n of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA1 + Register $n of BLOCK4 (KEY0). + 0xA0 + 0x20 + + + KEY0_DATA1 + Stores the first 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA2 + Register $n of BLOCK4 (KEY0). + 0xA4 + 0x20 + + + KEY0_DATA2 + Stores the second 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA3 + Register $n of BLOCK4 (KEY0). + 0xA8 + 0x20 + + + KEY0_DATA3 + Stores the third 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA4 + Register $n of BLOCK4 (KEY0). + 0xAC + 0x20 + + + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA5 + Register $n of BLOCK4 (KEY0). + 0xB0 + 0x20 + + + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA6 + Register $n of BLOCK4 (KEY0). + 0xB4 + 0x20 + + + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA7 + Register $n of BLOCK4 (KEY0). + 0xB8 + 0x20 + + + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY1_DATA0 + Register $n of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA1 + Register $n of BLOCK5 (KEY1). + 0xC0 + 0x20 + + + KEY1_DATA1 + Stores the first 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA2 + Register $n of BLOCK5 (KEY1). + 0xC4 + 0x20 + + + KEY1_DATA2 + Stores the second 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA3 + Register $n of BLOCK5 (KEY1). + 0xC8 + 0x20 + + + KEY1_DATA3 + Stores the third 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA4 + Register $n of BLOCK5 (KEY1). + 0xCC + 0x20 + + + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA5 + Register $n of BLOCK5 (KEY1). + 0xD0 + 0x20 + + + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA6 + Register $n of BLOCK5 (KEY1). + 0xD4 + 0x20 + + + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA7 + Register $n of BLOCK5 (KEY1). + 0xD8 + 0x20 + + + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY2_DATA0 + Register $n of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA1 + Register $n of BLOCK6 (KEY2). + 0xE0 + 0x20 + + + KEY2_DATA1 + Stores the first 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA2 + Register $n of BLOCK6 (KEY2). + 0xE4 + 0x20 + + + KEY2_DATA2 + Stores the second 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA3 + Register $n of BLOCK6 (KEY2). + 0xE8 + 0x20 + + + KEY2_DATA3 + Stores the third 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA4 + Register $n of BLOCK6 (KEY2). + 0xEC + 0x20 + + + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA5 + Register $n of BLOCK6 (KEY2). + 0xF0 + 0x20 + + + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA6 + Register $n of BLOCK6 (KEY2). + 0xF4 + 0x20 + + + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA7 + Register $n of BLOCK6 (KEY2). + 0xF8 + 0x20 + + + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY3_DATA0 + Register $n of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA1 + Register $n of BLOCK7 (KEY3). + 0x100 + 0x20 + + + KEY3_DATA1 + Stores the first 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA2 + Register $n of BLOCK7 (KEY3). + 0x104 + 0x20 + + + KEY3_DATA2 + Stores the second 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA3 + Register $n of BLOCK7 (KEY3). + 0x108 + 0x20 + + + KEY3_DATA3 + Stores the third 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA4 + Register $n of BLOCK7 (KEY3). + 0x10C + 0x20 + + + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA5 + Register $n of BLOCK7 (KEY3). + 0x110 + 0x20 + + + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA6 + Register $n of BLOCK7 (KEY3). + 0x114 + 0x20 + + + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA7 + Register $n of BLOCK7 (KEY3). + 0x118 + 0x20 + + + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY4_DATA0 + Register $n of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA1 + Register $n of BLOCK8 (KEY4). + 0x120 + 0x20 + + + KEY4_DATA1 + Stores the first 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA2 + Register $n of BLOCK8 (KEY4). + 0x124 + 0x20 + + + KEY4_DATA2 + Stores the second 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA3 + Register $n of BLOCK8 (KEY4). + 0x128 + 0x20 + + + KEY4_DATA3 + Stores the third 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA4 + Register $n of BLOCK8 (KEY4). + 0x12C + 0x20 + + + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA5 + Register $n of BLOCK8 (KEY4). + 0x130 + 0x20 + + + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA6 + Register $n of BLOCK8 (KEY4). + 0x134 + 0x20 + + + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA7 + Register $n of BLOCK8 (KEY4). + 0x138 + 0x20 + + + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY5_DATA0 + Register $n of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA1 + Register $n of BLOCK9 (KEY5). + 0x140 + 0x20 + + + KEY5_DATA1 + Stores the first 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA2 + Register $n of BLOCK9 (KEY5). + 0x144 + 0x20 + + + KEY5_DATA2 + Stores the second 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA3 + Register $n of BLOCK9 (KEY5). + 0x148 + 0x20 + + + KEY5_DATA3 + Stores the third 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA4 + Register $n of BLOCK9 (KEY5). + 0x14C + 0x20 + + + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA5 + Register $n of BLOCK9 (KEY5). + 0x150 + 0x20 + + + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA6 + Register $n of BLOCK9 (KEY5). + 0x154 + 0x20 + + + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA7 + Register $n of BLOCK9 (KEY5). + 0x158 + 0x20 + + + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA0 + Register $n of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA1 + Register $n of BLOCK9 (KEY5). + 0x160 + 0x20 + + + SYS_DATA_PART2_1 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA2 + Register $n of BLOCK10 (system). + 0x164 + 0x20 + + + SYS_DATA_PART2_2 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA3 + Register $n of BLOCK10 (system). + 0x168 + 0x20 + + + SYS_DATA_PART2_3 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA4 + Register $n of BLOCK10 (system). + 0x16C + 0x20 + + + SYS_DATA_PART2_4 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA5 + Register $n of BLOCK10 (system). + 0x170 + 0x20 + + + SYS_DATA_PART2_5 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA6 + Register $n of BLOCK10 (system). + 0x174 + 0x20 + + + SYS_DATA_PART2_6 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA7 + Register $n of BLOCK10 (system). + 0x178 + 0x20 + + + SYS_DATA_PART2_7 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + Indicates a programming error of RD_DIS. + 0 + 7 + read-only + + + SWAP_UART_SDIO_EN_ERR + Indicates a programming error of SWAP_UART_SDIO_EN. + 7 + 1 + read-only + + + DIS_ICACHE_ERR + Indicates a programming error of DIS_ICACHE. + 8 + 1 + read-only + + + DIS_USB_JTAG_ERR + Indicates a programming error of DIS_USB_JTAG. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE_ERR + Indicates a programming error of DIS_DOWNLOAD_ICACHE. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ERR + Indicates a programming error of DIS_USB_DEVICE. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + Indicates a programming error of DIS_FORCE_DOWNLOAD. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS_ERR + Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + 13 + 1 + read-only + + + DIS_TWAI_ERR + Indicates a programming error of DIS_CAN. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE_ERR + Indicates a programming error of JTAG_SEL_ENABLE. + 15 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + Indicates a programming error of SOFT_DIS_JTAG. + 16 + 3 + read-only + + + DIS_PAD_JTAG_ERR + Indicates a programming error of DIS_PAD_JTAG. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + 20 + 1 + read-only + + + USB_DREFH_ERR + Indicates a programming error of USB_DREFH. + 21 + 2 + read-only + + + USB_DREFL_ERR + Indicates a programming error of USB_DREFL. + 23 + 2 + read-only + + + USB_EXCHG_PINS_ERR + Indicates a programming error of USB_EXCHG_PINS. + 25 + 1 + read-only + + + VDD_SPI_AS_GPIO_ERR + Indicates a programming error of VDD_SPI_AS_GPIO. + 26 + 1 + read-only + + + RPT4_RESERVED0_ERR_2 + Reserved. + 27 + 2 + read-only + + + RPT4_RESERVED0_ERR_1 + Reserved. + 29 + 1 + read-only + + + RPT4_RESERVED0_ERR_0 + Reserved. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + RPT4_RESERVED1_ERR_0 + Reserved. + 0 + 16 + read-only + + + WDT_DELAY_SEL_ERR + Indicates a programming error of WDT_DELAY_SEL. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + Indicates a programming error of SPI_BOOT_CRYPT_CNT. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + Indicates a programming error of KEY_PURPOSE_0. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + Indicates a programming error of KEY_PURPOSE_1. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + Indicates a programming error of KEY_PURPOSE_2. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + Indicates a programming error of KEY_PURPOSE_3. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + Indicates a programming error of KEY_PURPOSE_4. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + Indicates a programming error of KEY_PURPOSE_5. + 12 + 4 + read-only + + + SEC_DPA_LEVEL_ERR + Indicates a programming error of SEC_DPA_LEVEL. + 16 + 2 + read-only + + + RPT4_RESERVED2_ERR_1 + Reserved. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE_ERR + Indicates a programming error of CRYPT_DPA_ENABLE. + 19 + 1 + read-only + + + SECURE_BOOT_EN_ERR + Indicates a programming error of SECURE_BOOT_EN. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + 21 + 1 + read-only + + + RPT4_RESERVED2_ERR_0 + Reserved. + 22 + 6 + read-only + + + FLASH_TPUW_ERR + Indicates a programming error of FLASH_TPUW. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_DOWNLOAD_MODE. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT_ERR + Indicates a programming error of DIS_DIRECT_BOOT. + 1 + 1 + read-only + + + USB_PRINT_ERR + Indicates a programming error of UART_PRINT_CHANNEL. + 2 + 1 + read-only + + + RPT4_RESERVED3_ERR_5 + Reserved. + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + Indicates a programming error of UART_PRINT_CONTROL. + 6 + 2 + read-only + + + RPT4_RESERVED3_ERR_4 + Reserved. + 8 + 1 + read-only + + + RPT4_RESERVED3_ERR_3 + Reserved. + 9 + 1 + read-only + + + RPT4_RESERVED3_ERR_2 + Reserved. + 10 + 2 + read-only + + + RPT4_RESERVED3_ERR_1 + Reserved. + 12 + 1 + read-only + + + FORCE_SEND_RESUME_ERR + Indicates a programming error of FORCE_SEND_RESUME. + 13 + 1 + read-only + + + SECURE_VERSION_ERR + Indicates a programming error of SECURE_VERSION. + 14 + 16 + read-only + + + RPT4_RESERVED3_ERR_0 + Reserved. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x190 + 0x20 + + + RPT4_RESERVED4_ERR_1 + Reserved. + 0 + 24 + read-only + + + RPT4_RESERVED4_ERR_0 + Reserved. + 24 + 8 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SPI_8M_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + MAC_SPI_8M_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x1C8 + 0x20 + 0x00000002 + + + MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit to force enable eFuse register configuration clock signal. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: programming operation command 0x5AA5: read operation command. + 0 + 16 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + BLK0_VALID_BIT_CNT + Indicates the number of block valid bit. + 10 + 10 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE1C + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x12010201 + + + THR_A + Configures the read hold time. + 0 + 8 + read-write + + + TRD + Configures the read time. + 8 + 8 + read-write + + + TSUR_A + Configures the read setup time. + 16 + 8 + read-write + + + READ_INIT_NUM + Configures the waiting time of reading eFuse memory. + 24 + 8 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F0 + 0x20 + 0x01300001 + + + TSUP_A + Configures the programming setup time. + 0 + 8 + read-write + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + THP_A + Configures the programming hold time. + 24 + 8 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00C80190 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + TPGM + Configures the active programming time. + 16 + 16 + read-write + + + + + WR_TIM_CONF0_RS_BYPASS + Configurarion register0 of eFuse programming time parameters and rs bypass operation. + 0x1F8 + 0x20 + 0x00002000 + + + BYPASS_RS_CORRECTION + Set this bit to bypass reed solomon correction step. + 0 + 1 + read-write + + + BYPASS_RS_BLK_NUM + Configures block number of programming twice operation. + 1 + 11 + read-write + + + UPDATE + Set this bit to update multi-bit register signals. + 12 + 1 + write-only + + + TPGM_INACTIVE + Configures the inactive programming time. + 13 + 8 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02206300 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + + + EXTMEM + External Memory + EXTMEM + 0x600C8000 + + 0x0 + 0x3C8 + registers + + + + L1_ICACHE_CTRL + L1 instruction Cache(L1-ICache) control register + 0x0 + 0x20 + + + L1_ICACHE_SHUT_IBUS0 + The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + 0 + 1 + read-only + + + L1_ICACHE_SHUT_IBUS1 + The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + 1 + 1 + read-only + + + L1_ICACHE_SHUT_IBUS2 + Reserved + 2 + 1 + read-only + + + L1_ICACHE_SHUT_IBUS3 + Reserved + 3 + 1 + read-only + + + L1_ICACHE_UNDEF_OP + Reserved + 4 + 4 + read-only + + + + + L1_CACHE_CTRL + L1 data Cache(L1-Cache) control register + 0x4 + 0x20 + + + L1_CACHE_SHUT_BUS0 + The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable + 0 + 1 + read-write + + + L1_CACHE_SHUT_BUS1 + The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable + 1 + 1 + read-write + + + L1_CACHE_SHUT_DBUS2 + Reserved + 2 + 1 + read-only + + + L1_CACHE_SHUT_DBUS3 + Reserved + 3 + 1 + read-only + + + L1_CACHE_SHUT_DMA + The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable + 4 + 1 + read-only + + + L1_CACHE_UNDEF_OP + Reserved + 8 + 4 + read-write + + + + + L1_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x8 + 0x20 + + + BYPASS_L1_ICACHE0_EN + The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + 0 + 1 + read-only + + + BYPASS_L1_ICACHE1_EN + The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + 1 + 1 + read-only + + + BYPASS_L1_ICACHE2_EN + Reserved + 2 + 1 + read-only + + + BYPASS_L1_ICACHE3_EN + Reserved + 3 + 1 + read-only + + + BYPASS_L1_DCACHE_EN + The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + 4 + 1 + read-only + + + + + L1_CACHE_ATOMIC_CONF + L1 Cache atomic feature configure register + 0xC + 0x20 + + + L1_CACHE_ATOMIC_EN + The bit is used to enable atomic feature on L1-Cache when multiple cores access L1-Cache. 1: disable, 1: enable. + 0 + 1 + read-only + + + + + L1_ICACHE_CACHESIZE_CONF + L1 instruction Cache CacheSize mode configure register + 0x10 + 0x20 + + + L1_ICACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_ICACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_ICACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_ICACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_ICACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_ICACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L1_ICACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L1_ICACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L1_ICACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L1_ICACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L1_ICACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L1_ICACHE_CACHESIZE_2048K + The field is used to configure cachesize of L1-ICache as 2048k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L1_ICACHE_CACHESIZE_4096K + The field is used to configure cachesize of L1-ICache as 4096k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L1_ICACHE_BLOCKSIZE_CONF + L1 instruction Cache BlockSize mode configure register + 0x14 + 0x20 + + + L1_ICACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L1_CACHE_CACHESIZE_CONF + L1 data Cache CacheSize mode configure register + 0x18 + 0x20 + 0x00000020 + + + L1_CACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-Cache as 1k bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_CACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-Cache as 2k bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_CACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-Cache as 4k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_CACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-Cache as 8k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_CACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-Cache as 16k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_CACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-Cache as 32k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L1_CACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-Cache as 64k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L1_CACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-Cache as 128k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L1_CACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-Cache as 256k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L1_CACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-Cache as 512k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L1_CACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L1_CACHE_CACHESIZE_2048K + The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L1_CACHE_CACHESIZE_4096K + The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L1_CACHE_BLOCKSIZE_CONF + L1 data Cache BlockSize mode configure register + 0x1C + 0x20 + 0x00000004 + + + L1_CACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_CACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_CACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_CACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_CACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_CACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L1_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x20 + 0x20 + + + L1_ICACHE0_WRAP + Set this bit as 1 to enable L1-ICache0 wrap around mode. + 0 + 1 + read-only + + + L1_ICACHE1_WRAP + Set this bit as 1 to enable L1-ICache1 wrap around mode. + 1 + 1 + read-only + + + L1_ICACHE2_WRAP + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_WRAP + Reserved + 3 + 1 + read-only + + + L1_CACHE_WRAP + Set this bit as 1 to enable L1-DCache wrap around mode. + 4 + 1 + read-write + + + + + L1_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x24 + 0x20 + 0x00055555 + + + L1_ICACHE0_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-only + + + L1_ICACHE0_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down + 1 + 1 + read-only + + + L1_ICACHE0_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up + 2 + 1 + read-only + + + L1_ICACHE1_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating. + 4 + 1 + read-only + + + L1_ICACHE1_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down + 5 + 1 + read-only + + + L1_ICACHE1_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up + 6 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_ON + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_PD + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_PU + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_ON + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_PD + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_PU + Reserved + 14 + 1 + read-only + + + L1_CACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: open clock gating. + 16 + 1 + read-write + + + L1_CACHE_TAG_MEM_FORCE_PD + The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down + 17 + 1 + read-write + + + L1_CACHE_TAG_MEM_FORCE_PU + The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up + 18 + 1 + read-write + + + + + L1_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x28 + 0x20 + 0x00055555 + + + L1_ICACHE0_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-only + + + L1_ICACHE0_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down + 1 + 1 + read-only + + + L1_ICACHE0_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up + 2 + 1 + read-only + + + L1_ICACHE1_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating. + 4 + 1 + read-only + + + L1_ICACHE1_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down + 5 + 1 + read-only + + + L1_ICACHE1_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up + 6 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_ON + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_PD + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_PU + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_ON + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_PD + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_PU + Reserved + 14 + 1 + read-only + + + L1_CACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: open clock gating. + 16 + 1 + read-write + + + L1_CACHE_DATA_MEM_FORCE_PD + The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power down + 17 + 1 + read-write + + + L1_CACHE_DATA_MEM_FORCE_PU + The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up + 18 + 1 + read-write + + + + + L1_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x2C + 0x20 + + + L1_ICACHE0_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software. + 0 + 1 + read-only + + + L1_ICACHE0_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 1 + 1 + read-only + + + L1_ICACHE0_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + 2 + 1 + read-only + + + L1_ICACHE1_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software. + 4 + 1 + read-only + + + L1_ICACHE1_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 5 + 1 + read-only + + + L1_ICACHE1_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 6 + 1 + read-only + + + L1_ICACHE2_FREEZE_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_FREEZE_MODE + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_FREEZE_DONE + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_FREEZE_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_FREEZE_MODE + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_FREEZE_DONE + Reserved + 14 + 1 + read-only + + + L1_CACHE_FREEZE_EN + The bit is used to enable freeze operation on L1-Cache. It can be cleared by software. + 16 + 1 + read-write + + + L1_CACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 17 + 1 + read-write + + + L1_CACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-Cache is finished or not. 0: not finished. 1: finished. + 18 + 1 + read-only + + + + + L1_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x30 + 0x20 + 0x00033333 + + + L1_ICACHE0_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable. + 0 + 1 + read-only + + + L1_ICACHE0_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable. + 1 + 1 + read-only + + + L1_ICACHE1_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable. + 4 + 1 + read-only + + + L1_ICACHE1_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable. + 5 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_RD_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_WR_EN + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_RD_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_WR_EN + Reserved + 13 + 1 + read-only + + + L1_CACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: enable. + 16 + 1 + read-write + + + L1_CACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: enable. + 17 + 1 + read-write + + + + + L1_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x34 + 0x20 + 0x00033333 + + + L1_ICACHE0_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable. + 0 + 1 + read-only + + + L1_ICACHE0_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable. + 1 + 1 + read-only + + + L1_ICACHE1_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable. + 4 + 1 + read-only + + + L1_ICACHE1_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable. + 5 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_RD_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_WR_EN + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_RD_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_WR_EN + Reserved + 13 + 1 + read-only + + + L1_CACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: enable. + 16 + 1 + read-write + + + L1_CACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: enable. + 17 + 1 + read-write + + + + + L1_ICACHE0_PRELOCK_CONF + L1 instruction Cache 0 prelock configure register + 0x38 + 0x20 + + + L1_ICACHE0_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache0. + 0 + 1 + read-only + + + L1_ICACHE0_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache0. + 1 + 1 + read-only + + + L1_ICACHE0_PRELOCK_RGID + The bit is used to set the gid of l1 icache0 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE0_PRELOCK_SCT0_ADDR + L1 instruction Cache 0 prelock section0 address configure register + 0x3C + 0x20 + + + L1_ICACHE0_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE0_PRELOCK_SCT1_ADDR + L1 instruction Cache 0 prelock section1 address configure register + 0x40 + 0x20 + + + L1_ICACHE0_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE0_PRELOCK_SCT_SIZE + L1 instruction Cache 0 prelock section size configure register + 0x44 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE0_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE0_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_ICACHE1_PRELOCK_CONF + L1 instruction Cache 1 prelock configure register + 0x48 + 0x20 + + + L1_ICACHE1_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache1. + 0 + 1 + read-only + + + L1_ICACHE1_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache1. + 1 + 1 + read-only + + + L1_ICACHE1_PRELOCK_RGID + The bit is used to set the gid of l1 icache1 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE1_PRELOCK_SCT0_ADDR + L1 instruction Cache 1 prelock section0 address configure register + 0x4C + 0x20 + + + L1_ICACHE1_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE1_PRELOCK_SCT1_ADDR + L1 instruction Cache 1 prelock section1 address configure register + 0x50 + 0x20 + + + L1_ICACHE1_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE1_PRELOCK_SCT_SIZE + L1 instruction Cache 1 prelock section size configure register + 0x54 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE1_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE1_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_ICACHE2_PRELOCK_CONF + L1 instruction Cache 2 prelock configure register + 0x58 + 0x20 + + + L1_ICACHE2_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache2. + 0 + 1 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache2. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOCK_RGID + The bit is used to set the gid of l1 icache2 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT0_ADDR + L1 instruction Cache 2 prelock section0 address configure register + 0x5C + 0x20 + + + L1_ICACHE2_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT1_ADDR + L1 instruction Cache 2 prelock section1 address configure register + 0x60 + 0x20 + + + L1_ICACHE2_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT_SIZE + L1 instruction Cache 2 prelock section size configure register + 0x64 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE2_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_ICACHE3_PRELOCK_CONF + L1 instruction Cache 3 prelock configure register + 0x68 + 0x20 + + + L1_ICACHE3_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache3. + 0 + 1 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache3. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOCK_RGID + The bit is used to set the gid of l1 icache3 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT0_ADDR + L1 instruction Cache 3 prelock section0 address configure register + 0x6C + 0x20 + + + L1_ICACHE3_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT1_ADDR + L1 instruction Cache 3 prelock section1 address configure register + 0x70 + 0x20 + + + L1_ICACHE3_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT_SIZE + L1 instruction Cache 3 prelock section size configure register + 0x74 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE3_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_CACHE_PRELOCK_CONF + L1 Cache prelock configure register + 0x78 + 0x20 + + + L1_CACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-Cache. + 0 + 1 + read-write + + + L1_CACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-Cache. + 1 + 1 + read-write + + + L1_CACHE_PRELOCK_RGID + The bit is used to set the gid of l1 cache prelock. + 2 + 4 + read-only + + + + + L1_CACHE_PRELOCK_SCT0_ADDR + L1 Cache prelock section0 address configure register + 0x7C + 0x20 + + + L1_CACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOCK_SCT1_ADDR + L1 Cache prelock section1 address configure register + 0x80 + 0x20 + + + L1_CACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOCK_SCT_SIZE + L1 Cache prelock section size configure register + 0x84 + 0x20 + 0x3FFF3FFF + + + L1_CACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_CACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + CACHE_LOCK_CTRL + Lock-class (manual lock) operation control register + 0x88 + 0x20 + 0x00000004 + + + CACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done + 0 + 1 + read-write + + + CACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done + 1 + 1 + read-write + + + CACHE_LOCK_DONE + The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished. + 2 + 1 + read-only + + + CACHE_LOCK_RGID + The bit is used to set the gid of cache lock/unlock. + 3 + 4 + read-only + + + + + CACHE_LOCK_MAP + Lock (manual lock) map configure register + 0x8C + 0x20 + + + CACHE_LOCK_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. [4]: L1-Cache + 0 + 6 + read-write + + + + + CACHE_LOCK_ADDR + Lock (manual lock) address configure register + 0x90 + 0x20 + + + CACHE_LOCK_ADDR + Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG + 0 + 32 + read-write + + + + + CACHE_LOCK_SIZE + Lock (manual lock) size configure register + 0x94 + 0x20 + + + CACHE_LOCK_SIZE + Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG + 0 + 16 + read-write + + + + + CACHE_SYNC_CTRL + Sync-class operation control register + 0x98 + 0x20 + 0x00000001 + + + CACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 0 + 1 + read-write + + + CACHE_CLEAN_ENA + The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 1 + 1 + read-write + + + CACHE_WRITEBACK_ENA + The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 2 + 1 + read-write + + + CACHE_WRITEBACK_INVALIDATE_ENA + The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 3 + 1 + read-write + + + CACHE_SYNC_DONE + The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished. + 4 + 1 + read-only + + + CACHE_SYNC_RGID + The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate) + 5 + 4 + read-only + + + + + CACHE_SYNC_MAP + Sync map configure register + 0x9C + 0x20 + 0x0000003F + + + CACHE_SYNC_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. [4]: L1-Cache + 0 + 6 + read-write + + + + + CACHE_SYNC_ADDR + Sync address configure register + 0xA0 + 0x20 + + + CACHE_SYNC_ADDR + Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG + 0 + 32 + read-write + + + + + CACHE_SYNC_SIZE + Sync size configure register + 0xA4 + 0x20 + + + CACHE_SYNC_SIZE + Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG + 0 + 24 + read-write + + + + + L1_ICACHE0_PRELOAD_CTRL + L1 instruction Cache 0 preload-operation control register + 0xA8 + 0x20 + 0x00000002 + + + L1_ICACHE0_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE0_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE0_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE0_PRELOAD_RGID + The bit is used to set the gid of l1 icache0 preload. + 3 + 4 + read-only + + + + + L1_ICACHE0_PRELOAD_ADDR + L1 instruction Cache 0 preload address configure register + 0xAC + 0x20 + + + L1_ICACHE0_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE0_PRELOAD_SIZE + L1 instruction Cache 0 preload size configure register + 0xB0 + 0x20 + + + L1_ICACHE0_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_ICACHE1_PRELOAD_CTRL + L1 instruction Cache 1 preload-operation control register + 0xB4 + 0x20 + 0x00000002 + + + L1_ICACHE1_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE1_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE1_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE1_PRELOAD_RGID + The bit is used to set the gid of l1 icache1 preload. + 3 + 4 + read-only + + + + + L1_ICACHE1_PRELOAD_ADDR + L1 instruction Cache 1 preload address configure register + 0xB8 + 0x20 + + + L1_ICACHE1_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE1_PRELOAD_SIZE + L1 instruction Cache 1 preload size configure register + 0xBC + 0x20 + + + L1_ICACHE1_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_ICACHE2_PRELOAD_CTRL + L1 instruction Cache 2 preload-operation control register + 0xC0 + 0x20 + 0x00000002 + + + L1_ICACHE2_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE2_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE2_PRELOAD_RGID + The bit is used to set the gid of l1 icache2 preload. + 3 + 4 + read-only + + + + + L1_ICACHE2_PRELOAD_ADDR + L1 instruction Cache 2 preload address configure register + 0xC4 + 0x20 + + + L1_ICACHE2_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOAD_SIZE + L1 instruction Cache 2 preload size configure register + 0xC8 + 0x20 + + + L1_ICACHE2_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_ICACHE3_PRELOAD_CTRL + L1 instruction Cache 3 preload-operation control register + 0xCC + 0x20 + 0x00000002 + + + L1_ICACHE3_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE3_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_PRELOAD_RGID + The bit is used to set the gid of l1 icache3 preload. + 3 + 4 + read-only + + + + + L1_ICACHE3_PRELOAD_ADDR + L1 instruction Cache 3 preload address configure register + 0xD0 + 0x20 + + + L1_ICACHE3_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOAD_SIZE + L1 instruction Cache 3 preload size configure register + 0xD4 + 0x20 + + + L1_ICACHE3_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_CACHE_PRELOAD_CTRL + L1 Cache preload-operation control register + 0xD8 + 0x20 + 0x00000002 + + + L1_CACHE_PRELOAD_ENA + The bit is used to enable preload operation on L1-Cache. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_CACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_CACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_CACHE_PRELOAD_RGID + The bit is used to set the gid of l1 cache preload. + 3 + 4 + read-only + + + + + L1_DCACHE_PRELOAD_ADDR + L1 Cache preload address configure register + 0xDC + 0x20 + + + L1_CACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-Cache, which should be used together with L1_CACHE_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOAD_SIZE + L1 Cache preload size configure register + 0xE0 + 0x20 + + + L1_CACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE0_AUTOLOAD_CTRL + L1 instruction Cache 0 autoload-operation control register + 0xE4 + 0x20 + 0x00000002 + + + L1_ICACHE0_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE0_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache0. + 8 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache0. + 9 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache0 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 0 autoload section 0 address configure register + 0xE8 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 0 autoload section 0 size configure register + 0xEC + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 0 autoload section 1 address configure register + 0xF0 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 0 autoload section 1 size configure register + 0xF4 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE1_AUTOLOAD_CTRL + L1 instruction Cache 1 autoload-operation control register + 0xF8 + 0x20 + 0x00000002 + + + L1_ICACHE1_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE1_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache1. + 8 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache1. + 9 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache1 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 1 autoload section 0 address configure register + 0xFC + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 1 autoload section 0 size configure register + 0x100 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 1 autoload section 1 address configure register + 0x104 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 1 autoload section 1 size configure register + 0x108 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE2_AUTOLOAD_CTRL + L1 instruction Cache 2 autoload-operation control register + 0x10C + 0x20 + 0x00000002 + + + L1_ICACHE2_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE2_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache2. + 8 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache2. + 9 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache2 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 2 autoload section 0 address configure register + 0x110 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 2 autoload section 0 size configure register + 0x114 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 2 autoload section 1 address configure register + 0x118 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 2 autoload section 1 size configure register + 0x11C + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE3_AUTOLOAD_CTRL + L1 instruction Cache 3 autoload-operation control register + 0x120 + 0x20 + 0x00000002 + + + L1_ICACHE3_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache3. + 8 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache3. + 9 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache3 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 3 autoload section 0 address configure register + 0x124 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 3 autoload section 0 size configure register + 0x128 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 3 autoload section 1 address configure register + 0x12C + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 3 autoload section 1 size configure register + 0x130 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + Reserved + 0 + 28 + read-only + + + + + L1_CACHE_AUTOLOAD_CTRL + L1 Cache autoload-operation control register + 0x134 + 0x20 + 0x00000002 + + + L1_CACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_CACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-Cache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_CACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-Cache. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_CACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_CACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-Cache. + 8 + 1 + read-write + + + L1_CACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-Cache. + 9 + 1 + read-write + + + L1_CACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L1-Cache. + 10 + 1 + read-only + + + L1_CACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L1-Cache. + 11 + 1 + read-only + + + L1_CACHE_AUTOLOAD_RGID + The bit is used to set the gid of l1 cache autoload. + 12 + 4 + read-only + + + + + L1_CACHE_AUTOLOAD_SCT0_ADDR + L1 Cache autoload section 0 address configure register + 0x138 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_CACHE_AUTOLOAD_SCT0_SIZE + L1 Cache autoload section 0 size configure register + 0x13C + 0x20 + + + L1_CACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_CACHE_AUTOLOAD_SCT1_ADDR + L1 Cache autoload section 1 address configure register + 0x140 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_CACHE_AUTOLOAD_SCT1_SIZE + L1 Cache autoload section 1 size configure register + 0x144 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_CACHE_AUTOLOAD_SCT2_ADDR + L1 Cache autoload section 2 address configure register + 0x148 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 32 + read-only + + + + + L1_CACHE_AUTOLOAD_SCT2_SIZE + L1 Cache autoload section 2 size configure register + 0x14C + 0x20 + + + L1_CACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 + read-only + + + + + L1_CACHE_AUTOLOAD_SCT3_ADDR + L1 Cache autoload section 1 address configure register + 0x150 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 + read-only + + + + + L1_CACHE_AUTOLOAD_SCT3_SIZE + L1 Cache autoload section 1 size configure register + 0x154 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 + read-only + + + + + L1_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x158 + 0x20 + + + L1_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_OVF_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_BUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-write + + + L1_BUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_OVF_INT_ENA + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_ENA + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x15C + 0x20 + + + L1_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_OVF_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_BUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + write-only + + + L1_BUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + write-only + + + L1_DBUS2_OVF_INT_CLR + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_CLR + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x160 + 0x20 + + + L1_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-write + + + L1_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-write + + + L1_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2. + 2 + 1 + read-write + + + L1_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3. + 3 + 1 + read-write + + + L1_BUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-write + + + L1_BUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache. + 6 + 1 + read-write + + + L1_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache. + 7 + 1 + read-write + + + + + L1_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x164 + 0x20 + + + L1_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_OVF_INT_ST + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_ST + Reserved + 3 + 1 + read-only + + + L1_BUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-only + + + L1_BUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-only + + + L1_DBUS2_OVF_INT_ST + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_ST + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x168 + 0x20 + + + L1_ICACHE0_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + 0 + 1 + read-only + + + L1_ICACHE1_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + 1 + 1 + read-only + + + L1_ICACHE2_FAIL_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_CACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x16C + 0x20 + + + L1_ICACHE0_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + 0 + 1 + read-only + + + L1_ICACHE1_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + 1 + 1 + read-only + + + L1_ICACHE2_FAIL_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_CACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + write-only + + + + + L1_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x170 + 0x20 + + + L1_ICACHE0_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE1_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache2. + 2 + 1 + read-write + + + L1_ICACHE3_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache3. + 3 + 1 + read-write + + + L1_CACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-DCache. + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x174 + 0x20 + + + L1_ICACHE0_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache. + 0 + 1 + read-only + + + L1_ICACHE1_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache. + 1 + 1 + read-only + + + L1_ICACHE2_FAIL_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_ST + Reserved + 3 + 1 + read-only + + + L1_CACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x178 + 0x20 + + + L1_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_CNT_ENA + Reserved + 2 + 1 + read-only + + + L1_IBUS3_CNT_ENA + Reserved + 3 + 1 + read-only + + + L1_BUS0_CNT_ENA + The bit is used to enable dbus0 counter in L1-DCache. + 4 + 1 + read-write + + + L1_BUS1_CNT_ENA + The bit is used to enable dbus1 counter in L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_CNT_ENA + Reserved + 6 + 1 + read-only + + + L1_DBUS3_CNT_ENA + Reserved + 7 + 1 + read-only + + + L1_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L1-ICache0. + 16 + 1 + read-only + + + L1_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L1-ICache1. + 17 + 1 + read-only + + + L1_IBUS2_CNT_CLR + Reserved + 18 + 1 + read-only + + + L1_IBUS3_CNT_CLR + Reserved + 19 + 1 + read-only + + + L1_BUS0_CNT_CLR + The bit is used to clear dbus0 counter in L1-DCache. + 20 + 1 + write-only + + + L1_BUS1_CNT_CLR + The bit is used to clear dbus1 counter in L1-DCache. + 21 + 1 + write-only + + + L1_DBUS2_CNT_CLR + Reserved + 22 + 1 + read-only + + + L1_DBUS3_CNT_CLR + Reserved + 23 + 1 + read-only + + + + + L1_IBUS0_ACS_HIT_CNT + L1-ICache bus0 Hit-Access Counter register + 0x17C + 0x20 + + + L1_IBUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_MISS_CNT + L1-ICache bus0 Miss-Access Counter register + 0x180 + 0x20 + + + L1_IBUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_CONFLICT_CNT + L1-ICache bus0 Conflict-Access Counter register + 0x184 + 0x20 + + + L1_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_NXTLVL_CNT + L1-ICache bus0 Next-Level-Access Counter register + 0x188 + 0x20 + + + L1_IBUS0_NXTLVL_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_HIT_CNT + L1-ICache bus1 Hit-Access Counter register + 0x18C + 0x20 + + + L1_IBUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_MISS_CNT + L1-ICache bus1 Miss-Access Counter register + 0x190 + 0x20 + + + L1_IBUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_CONFLICT_CNT + L1-ICache bus1 Conflict-Access Counter register + 0x194 + 0x20 + + + L1_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_NXTLVL_CNT + L1-ICache bus1 Next-Level-Access Counter register + 0x198 + 0x20 + + + L1_IBUS1_NXTLVL_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_HIT_CNT + L1-ICache bus2 Hit-Access Counter register + 0x19C + 0x20 + + + L1_IBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_MISS_CNT + L1-ICache bus2 Miss-Access Counter register + 0x1A0 + 0x20 + + + L1_IBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_CONFLICT_CNT + L1-ICache bus2 Conflict-Access Counter register + 0x1A4 + 0x20 + + + L1_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_NXTLVL_CNT + L1-ICache bus2 Next-Level-Access Counter register + 0x1A8 + 0x20 + + + L1_IBUS2_NXTLVL_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_HIT_CNT + L1-ICache bus3 Hit-Access Counter register + 0x1AC + 0x20 + + + L1_IBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_MISS_CNT + L1-ICache bus3 Miss-Access Counter register + 0x1B0 + 0x20 + + + L1_IBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_CONFLICT_CNT + L1-ICache bus3 Conflict-Access Counter register + 0x1B4 + 0x20 + + + L1_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_NXTLVL_CNT + L1-ICache bus3 Next-Level-Access Counter register + 0x1B8 + 0x20 + + + L1_IBUS3_NXTLVL_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L1_BUS0_ACS_HIT_CNT + L1-Cache bus0 Hit-Access Counter register + 0x1BC + 0x20 + + + L1_BUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS0_ACS_MISS_CNT + L1-Cache bus0 Miss-Access Counter register + 0x1C0 + 0x20 + + + L1_BUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS0_ACS_CONFLICT_CNT + L1-Cache bus0 Conflict-Access Counter register + 0x1C4 + 0x20 + + + L1_BUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS0_ACS_NXTLVL_CNT + L1-Cache bus0 Next-Level-Access Counter register + 0x1C8 + 0x20 + + + L1_BUS0_NXTLVL_CNT + The register records the number of times that L1-Cache accesses L2-Cache due to bus0 accessing L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS1_ACS_HIT_CNT + L1-Cache bus1 Hit-Access Counter register + 0x1CC + 0x20 + + + L1_BUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS1_ACS_MISS_CNT + L1-Cache bus1 Miss-Access Counter register + 0x1D0 + 0x20 + + + L1_BUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS1_ACS_CONFLICT_CNT + L1-Cache bus1 Conflict-Access Counter register + 0x1D4 + 0x20 + + + L1_BUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS1_ACS_NXTLVL_CNT + L1-Cache bus1 Next-Level-Access Counter register + 0x1D8 + 0x20 + + + L1_BUS1_NXTLVL_CNT + The register records the number of times that L1-Cache accesses L2-Cache due to bus1 accessing L1-Cache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_HIT_CNT + L1-DCache bus2 Hit-Access Counter register + 0x1DC + 0x20 + + + L1_DBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_MISS_CNT + L1-DCache bus2 Miss-Access Counter register + 0x1E0 + 0x20 + + + L1_DBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_CONFLICT_CNT + L1-DCache bus2 Conflict-Access Counter register + 0x1E4 + 0x20 + + + L1_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_NXTLVL_CNT + L1-DCache bus2 Next-Level-Access Counter register + 0x1E8 + 0x20 + + + L1_DBUS2_NXTLVL_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_HIT_CNT + L1-DCache bus3 Hit-Access Counter register + 0x1EC + 0x20 + + + L1_DBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_MISS_CNT + L1-DCache bus3 Miss-Access Counter register + 0x1F0 + 0x20 + + + L1_DBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_CONFLICT_CNT + L1-DCache bus3 Conflict-Access Counter register + 0x1F4 + 0x20 + + + L1_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_NXTLVL_CNT + L1-DCache bus3 Next-Level-Access Counter register + 0x1F8 + 0x20 + + + L1_DBUS3_NXTLVL_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_ICACHE0_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x1FC + 0x20 + + + L1_ICACHE0_FAIL_ID + The register records the ID of fail-access when cache0 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE0_FAIL_ATTR + The register records the attribution of fail-access when cache0 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE0_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x200 + 0x20 + + + L1_ICACHE0_FAIL_ADDR + The register records the address of fail-access when cache0 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE1_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x204 + 0x20 + + + L1_ICACHE1_FAIL_ID + The register records the ID of fail-access when cache1 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE1_FAIL_ATTR + The register records the attribution of fail-access when cache1 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE1_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x208 + 0x20 + + + L1_ICACHE1_FAIL_ADDR + The register records the address of fail-access when cache1 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE2_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x20C + 0x20 + + + L1_ICACHE2_FAIL_ID + The register records the ID of fail-access when cache2 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE2_FAIL_ATTR + The register records the attribution of fail-access when cache2 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE2_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x210 + 0x20 + + + L1_ICACHE2_FAIL_ADDR + The register records the address of fail-access when cache2 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE3_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x214 + 0x20 + + + L1_ICACHE3_FAIL_ID + The register records the ID of fail-access when cache3 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE3_FAIL_ATTR + The register records the attribution of fail-access when cache3 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE3_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x218 + 0x20 + + + L1_ICACHE3_FAIL_ADDR + The register records the address of fail-access when cache3 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_CACHE_ACS_FAIL_ID_ATTR + L1-Cache Access Fail ID/attribution information register + 0x21C + 0x20 + + + L1_CACHE_FAIL_ID + The register records the ID of fail-access when cache accesses L1-Cache. + 0 + 16 + read-only + + + L1_CACHE_FAIL_ATTR + The register records the attribution of fail-access when cache accesses L1-Cache. + 16 + 16 + read-only + + + + + L1_DCACHE_ACS_FAIL_ADDR + L1-Cache Access Fail Address information register + 0x220 + 0x20 + + + L1_CACHE_FAIL_ADDR + The register records the address of fail-access when cache accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_CACHE_SYNC_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x224 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_CACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-Cache preload-operation. If preload operation is done, interrupt occurs. + 4 + 1 + read-write + + + CACHE_SYNC_DONE_INT_ENA + The bit is used to enable interrupt of Cache sync-operation done. + 6 + 1 + read-write + + + L1_ICACHE0_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_ENA + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ENA + Reserved + 10 + 1 + read-only + + + L1_CACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-Cache preload-operation error. + 11 + 1 + read-write + + + CACHE_SYNC_ERR_INT_ENA + The bit is used to enable interrupt of Cache sync-operation error. + 13 + 1 + read-write + + + + + L1_CACHE_SYNC_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x228 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_CACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-Cache preload-operation is done. + 4 + 1 + write-only + + + CACHE_SYNC_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + write-only + + + L1_ICACHE0_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_CLR + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_CLR + Reserved + 10 + 1 + read-only + + + L1_CACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-Cache preload-operation error. + 11 + 1 + write-only + + + CACHE_SYNC_ERR_INT_CLR + The bit is used to clear interrupt of Cache sync-operation error. + 13 + 1 + write-only + + + + + L1_CACHE_SYNC_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x22C + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-write + + + L1_ICACHE1_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_DONE_INT_RAW + Reserved + 2 + 1 + read-write + + + L1_ICACHE3_PLD_DONE_INT_RAW + Reserved + 3 + 1 + read-write + + + L1_CACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-Cache preload-operation is done. + 4 + 1 + read-write + + + CACHE_SYNC_DONE_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-write + + + L1_ICACHE0_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs. + 7 + 1 + read-write + + + L1_ICACHE1_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs. + 8 + 1 + read-write + + + L1_ICACHE2_PLD_ERR_INT_RAW + Reserved + 9 + 1 + read-write + + + L1_ICACHE3_PLD_ERR_INT_RAW + Reserved + 10 + 1 + read-write + + + L1_CACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-Cache preload-operation error occurs. + 11 + 1 + read-write + + + CACHE_SYNC_ERR_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation error occurs. + 13 + 1 + read-write + + + + + L1_CACHE_SYNC_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x230 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ST + Reserved + 3 + 1 + read-only + + + L1_CACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-Cache preload-operation is done. + 4 + 1 + read-only + + + CACHE_SYNC_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-only + + + L1_ICACHE0_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_ST + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ST + Reserved + 10 + 1 + read-only + + + L1_CACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-Cache preload-operation error. + 11 + 1 + read-only + + + CACHE_SYNC_ERR_INT_ST + The bit indicates the status of the interrupt of Cache sync-operation error. + 13 + 1 + read-only + + + + + L1_CACHE_SYNC_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x234 + 0x20 + + + L1_ICACHE0_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache0. + 0 + 2 + read-only + + + L1_ICACHE1_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache1. + 2 + 2 + read-only + + + L1_ICACHE2_PLD_ERR_CODE + Reserved + 4 + 2 + read-only + + + L1_ICACHE3_PLD_ERR_CODE + Reserved + 6 + 2 + read-only + + + L1_CACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-Cache. + 8 + 2 + read-only + + + CACHE_SYNC_ERR_CODE + The values 0-2 are available which means sync map, command conflict and size are error in Cache System. + 12 + 2 + read-only + + + + + L1_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x238 + 0x20 + + + L1_ICACHE0_SYNC_RST + set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 0 + 1 + read-only + + + L1_ICACHE1_SYNC_RST + set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 1 + 1 + read-only + + + L1_ICACHE2_SYNC_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_SYNC_RST + Reserved + 3 + 1 + read-only + + + L1_CACHE_SYNC_RST + set this bit to reset sync-logic inside L1-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 4 + 1 + read-write + + + + + L1_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x23C + 0x20 + + + L1_ICACHE0_PLD_RST + set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_RST + set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_RST + Reserved + 3 + 1 + read-only + + + L1_CACHE_PLD_RST + set this bit to reset preload-logic inside L1-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 4 + 1 + read-write + + + + + L1_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x240 + 0x20 + + + L1_ICACHE0_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0. + 0 + 1 + read-only + + + L1_ICACHE1_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1. + 1 + 1 + read-only + + + L1_ICACHE2_ALD_BUF_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_ALD_BUF_CLR + Reserved + 3 + 1 + read-only + + + L1_CACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, autoload will not work in L1-Cache. This bit should not be active when autoload works in L1-Cache. + 4 + 1 + read-write + + + + + L1_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x244 + 0x20 + + + L1_ICACHE0_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed. + 0 + 1 + read-only + + + L1_ICACHE1_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed. + 1 + 1 + read-only + + + L1_ICACHE2_UNALLOC_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_UNALLOC_CLR + Reserved + 3 + 1 + read-only + + + L1_CACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 cache where the unallocate request is responsed but not completed. + 4 + 1 + read-write + + + + + L1_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x248 + 0x20 + + + L1_ICACHE0_TAG_OBJECT + Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register. + 0 + 1 + read-only + + + L1_ICACHE1_TAG_OBJECT + Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register. + 1 + 1 + read-only + + + L1_ICACHE2_TAG_OBJECT + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_TAG_OBJECT + Reserved + 3 + 1 + read-only + + + L1_CACHE_TAG_OBJECT + Set this bit to set L1-Cache tag memory as object. This bit should be onehot with the others fields inside this register. + 4 + 1 + read-write + + + L1_ICACHE0_MEM_OBJECT + Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register. + 6 + 1 + read-only + + + L1_ICACHE1_MEM_OBJECT + Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register. + 7 + 1 + read-only + + + L1_ICACHE2_MEM_OBJECT + Reserved + 8 + 1 + read-only + + + L1_ICACHE3_MEM_OBJECT + Reserved + 9 + 1 + read-only + + + L1_CACHE_MEM_OBJECT + Set this bit to set L1-Cache data memory as object. This bit should be onehot with the others fields inside this register. + 10 + 1 + read-write + + + + + L1_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x24C + 0x20 + + + L1_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + 0 + 3 + read-write + + + + + L1_CACHE_VADDR + Cache Vaddr register + 0x250 + 0x20 + 0x40000000 + + + L1_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + L1_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x254 + 0x20 + 0x00000254 + + + L1_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + 0 + 32 + read-write + + + + + LEVEL_SPLIT0 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x258 + 0x20 + 0x00000258 + + + LEVEL_SPLIT0 + Reserved + 0 + 32 + read-only + + + + + L2_CACHE_CTRL + L2 Cache(L2-Cache) control register + 0x25C + 0x20 + + + L2_CACHE_SHUT_DMA + The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + 4 + 1 + read-only + + + L2_CACHE_UNDEF_OP + Reserved + 5 + 4 + read-only + + + + + L2_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x260 + 0x20 + + + BYPASS_L2_CACHE_EN + The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + 5 + 1 + read-only + + + + + L2_CACHE_CACHESIZE_CONF + L2 Cache CacheSize mode configure register + 0x264 + 0x20 + + + L2_CACHE_CACHESIZE_1K + The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L2_CACHE_CACHESIZE_2K + The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_CACHESIZE_4K + The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_CACHESIZE_8K + The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L2_CACHE_CACHESIZE_16K + The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L2_CACHE_CACHESIZE_32K + The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L2_CACHE_CACHESIZE_64K + The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L2_CACHE_CACHESIZE_128K + The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L2_CACHE_CACHESIZE_256K + The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L2_CACHE_CACHESIZE_512K + The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L2_CACHE_CACHESIZE_1024K + The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L2_CACHE_CACHESIZE_2048K + The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L2_CACHE_CACHESIZE_4096K + The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L2_CACHE_BLOCKSIZE_CONF + L2 Cache BlockSize mode configure register + 0x268 + 0x20 + + + L2_CACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L2_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x26C + 0x20 + + + L2_CACHE_WRAP + Set this bit as 1 to enable L2-Cache wrap around mode. + 5 + 1 + read-only + + + + + L2_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x270 + 0x20 + + + L2_CACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-only + + + L2_CACHE_TAG_MEM_FORCE_PD + The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-only + + + L2_CACHE_TAG_MEM_FORCE_PU + The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 + read-only + + + + + L2_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x274 + 0x20 + + + L2_CACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-only + + + L2_CACHE_DATA_MEM_FORCE_PD + The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-only + + + L2_CACHE_DATA_MEM_FORCE_PU + The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 + read-only + + + + + L2_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x278 + 0x20 + + + L2_CACHE_FREEZE_EN + The bit is used to enable freeze operation on L2-Cache. It can be cleared by software. + 20 + 1 + read-only + + + L2_CACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 21 + 1 + read-only + + + L2_CACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 22 + 1 + read-only + + + + + L2_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x27C + 0x20 + + + L2_CACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable. + 20 + 1 + read-only + + + L2_CACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable. + 21 + 1 + read-only + + + + + L2_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x280 + 0x20 + + + L2_CACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable. + 20 + 1 + read-only + + + L2_CACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable. + 21 + 1 + read-only + + + + + L2_CACHE_PRELOCK_CONF + L2 Cache prelock configure register + 0x284 + 0x20 + + + L2_CACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L2-Cache. + 0 + 1 + read-only + + + L2_CACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L2-Cache. + 1 + 1 + read-only + + + L2_CACHE_PRELOCK_RGID + The bit is used to set the gid of l2 cache prelock. + 2 + 4 + read-only + + + + + L2_CACHE_PRELOCK_SCT0_ADDR + L2 Cache prelock section0 address configure register + 0x288 + 0x20 + + + L2_CACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L2_CACHE_PRELOCK_SCT1_ADDR + L2 Cache prelock section1 address configure register + 0x28C + 0x20 + + + L2_CACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L2_CACHE_PRELOCK_SCT_SIZE + L2 Cache prelock section size configure register + 0x290 + 0x20 + 0xFFFFFFFF + + + L2_CACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + 0 + 16 + read-only + + + L2_CACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + 16 + 16 + read-only + + + + + L2_CACHE_PRELOAD_CTRL + L2 Cache preload-operation control register + 0x294 + 0x20 + 0x00000002 + + + L2_CACHE_PRELOAD_ENA + The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L2_CACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L2_CACHE_PRELOAD_RGID + The bit is used to set the gid of l2 cache preload. + 3 + 4 + read-only + + + + + L2_CACHE_PRELOAD_ADDR + L2 Cache preload address configure register + 0x298 + 0x20 + + + L2_CACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L2_CACHE_PRELOAD_SIZE + L2 Cache preload size configure register + 0x29C + 0x20 + + + L2_CACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + 0 + 16 + read-only + + + + + L2_CACHE_AUTOLOAD_CTRL + L2 Cache autoload-operation control register + 0x2A0 + 0x20 + 0x00000002 + + + L2_CACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable. + 0 + 1 + read-only + + + L2_CACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L2_CACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L2_CACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L2-Cache. + 8 + 1 + read-only + + + L2_CACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L2-Cache. + 9 + 1 + read-only + + + L2_CACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L2-Cache. + 10 + 1 + read-only + + + L2_CACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L2-Cache. + 11 + 1 + read-only + + + L2_CACHE_AUTOLOAD_RGID + The bit is used to set the gid of l2 cache autoload. + 12 + 4 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT0_ADDR + L2 Cache autoload section 0 address configure register + 0x2A4 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT0_SIZE + L2 Cache autoload section 0 size configure register + 0x2A8 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT1_ADDR + L2 Cache autoload section 1 address configure register + 0x2AC + 0x20 + + + L2_CACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT1_SIZE + L2 Cache autoload section 1 size configure register + 0x2B0 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT2_ADDR + L2 Cache autoload section 2 address configure register + 0x2B4 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 32 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT2_SIZE + L2 Cache autoload section 2 size configure register + 0x2B8 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT3_ADDR + L2 Cache autoload section 3 address configure register + 0x2BC + 0x20 + + + L2_CACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT3_SIZE + L2 Cache autoload section 3 size configure register + 0x2C0 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 + read-only + + + + + L2_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x2C4 + 0x20 + + + L2_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ENA + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x2C8 + 0x20 + + + L2_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_CLR + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_CLR + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_CLR + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_CLR + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x2CC + 0x20 + + + L2_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0. + 8 + 1 + read-write + + + L2_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1. + 9 + 1 + read-write + + + L2_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2. + 10 + 1 + read-write + + + L2_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3. + 11 + 1 + read-write + + + L2_DBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache. + 12 + 1 + read-write + + + L2_DBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache. + 13 + 1 + read-write + + + L2_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache. + 14 + 1 + read-write + + + L2_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache. + 15 + 1 + read-write + + + + + L2_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x2D0 + 0x20 + + + L2_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_ST + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ST + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_ST + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ST + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x2D4 + 0x20 + + + L2_CACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-only + + + + + L2_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x2D8 + 0x20 + + + L2_CACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-only + + + + + L2_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x2DC + 0x20 + + + L2_CACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L2-Cache. + 5 + 1 + read-write + + + + + L2_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x2E0 + 0x20 + + + L2_CACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x2E4 + 0x20 + + + L2_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_CNT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_CNT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_CNT_ENA + The bit is used to enable dbus0 counter in L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_CNT_ENA + The bit is used to enable dbus1 counter in L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_CNT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_CNT_ENA + Reserved + 15 + 1 + read-only + + + L2_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L2-Cache. + 24 + 1 + read-only + + + L2_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L2-Cache. + 25 + 1 + read-only + + + L2_IBUS2_CNT_CLR + Reserved + 26 + 1 + read-only + + + L2_IBUS3_CNT_CLR + Reserved + 27 + 1 + read-only + + + L2_DBUS0_CNT_CLR + The bit is used to clear dbus0 counter in L2-Cache. + 28 + 1 + read-only + + + L2_DBUS1_CNT_CLR + The bit is used to clear dbus1 counter in L2-Cache. + 29 + 1 + read-only + + + L2_DBUS2_CNT_CLR + Reserved + 30 + 1 + read-only + + + L2_DBUS3_CNT_CLR + Reserved + 31 + 1 + read-only + + + + + L2_IBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x2E8 + 0x20 + + + L2_IBUS0_HIT_CNT + The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x2EC + 0x20 + + + L2_IBUS0_MISS_CNT + The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x2F0 + 0x20 + + + L2_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_NXTLVL_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x2F4 + 0x20 + + + L2_IBUS0_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x2F8 + 0x20 + + + L2_IBUS1_HIT_CNT + The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x2FC + 0x20 + + + L2_IBUS1_MISS_CNT + The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x300 + 0x20 + + + L2_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_NXTLVL_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x304 + 0x20 + + + L2_IBUS1_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x308 + 0x20 + + + L2_IBUS2_HIT_CNT + The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x30C + 0x20 + + + L2_IBUS2_MISS_CNT + The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x310 + 0x20 + + + L2_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_NXTLVL_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x314 + 0x20 + + + L2_IBUS2_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x318 + 0x20 + + + L2_IBUS3_HIT_CNT + The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x31C + 0x20 + + + L2_IBUS3_MISS_CNT + The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x320 + 0x20 + + + L2_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_NXTLVL_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x324 + 0x20 + + + L2_IBUS3_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x328 + 0x20 + + + L2_DBUS0_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x32C + 0x20 + + + L2_DBUS0_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x330 + 0x20 + + + L2_DBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_NXTLVL_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x334 + 0x20 + + + L2_DBUS0_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x338 + 0x20 + + + L2_DBUS1_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x33C + 0x20 + + + L2_DBUS1_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x340 + 0x20 + + + L2_DBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_NXTLVL_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x344 + 0x20 + + + L2_DBUS1_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x348 + 0x20 + + + L2_DBUS2_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x34C + 0x20 + + + L2_DBUS2_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x350 + 0x20 + + + L2_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_NXTLVL_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x354 + 0x20 + + + L2_DBUS2_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x358 + 0x20 + + + L2_DBUS3_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x35C + 0x20 + + + L2_DBUS3_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x360 + 0x20 + + + L2_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_NXTLVL_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x364 + 0x20 + + + L2_DBUS3_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_CACHE_ACS_FAIL_ID_ATTR + L2-Cache Access Fail ID/attribution information register + 0x368 + 0x20 + + + L2_CACHE_FAIL_ID + The register records the ID of fail-access when L1-Cache accesses L2-Cache. + 0 + 16 + read-only + + + L2_CACHE_FAIL_ATTR + The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache. + 16 + 16 + read-only + + + + + L2_CACHE_ACS_FAIL_ADDR + L2-Cache Access Fail Address information register + 0x36C + 0x20 + + + L2_CACHE_FAIL_ADDR + The register records the address of fail-access when L1-Cache accesses L2-Cache. + 0 + 32 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x370 + 0x20 + + + L2_CACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation done. + 5 + 1 + read-only + + + L2_CACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation error. + 12 + 1 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x374 + 0x20 + + + L2_CACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-only + + + L2_CACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L2-Cache preload-operation error. + 12 + 1 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x378 + 0x20 + + + L2_CACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-write + + + L2_CACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs. + 12 + 1 + read-write + + + + + L2_CACHE_SYNC_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x37C + 0x20 + + + L2_CACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-only + + + L2_CACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L2-Cache preload-operation error. + 12 + 1 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x380 + 0x20 + + + L2_CACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L2-Cache. + 10 + 2 + read-only + + + + + L2_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x384 + 0x20 + + + L2_CACHE_SYNC_RST + set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 5 + 1 + read-only + + + + + L2_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x388 + 0x20 + + + L2_CACHE_PLD_RST + set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 5 + 1 + read-only + + + + + L2_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x38C + 0x20 + + + L2_CACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache. + 5 + 1 + read-only + + + + + L2_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x390 + 0x20 + + + L2_CACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed. + 5 + 1 + read-only + + + + + L2_CACHE_ACCESS_ATTR_CTRL + L1 Cache access Attribute propagation control register + 0x394 + 0x20 + 0x0000000F + + + L2_CACHE_ACCESS_FORCE_CC + Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable. + 0 + 1 + read-only + + + L2_CACHE_ACCESS_FORCE_WB + Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through. + 1 + 1 + read-only + + + L2_CACHE_ACCESS_FORCE_WMA + Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate. + 2 + 1 + read-only + + + L2_CACHE_ACCESS_FORCE_RMA + Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate. + 3 + 1 + read-only + + + + + L2_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x398 + 0x20 + + + L2_CACHE_TAG_OBJECT + Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register. + 5 + 1 + read-only + + + L2_CACHE_MEM_OBJECT + Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register. + 11 + 1 + read-only + + + + + L2_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x39C + 0x20 + + + L2_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + 0 + 3 + read-only + + + + + L2_CACHE_VADDR + Cache Vaddr register + 0x3A0 + 0x20 + 0x40000000 + + + L2_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-only + + + + + L2_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x3A4 + 0x20 + 0x000003A4 + + + L2_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + 0 + 32 + read-only + + + + + LEVEL_SPLIT1 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x3A8 + 0x20 + 0x000003A8 + + + LEVEL_SPLIT1 + Reserved + 0 + 32 + read-only + + + + + CLOCK_GATE + Clock gate control register + 0x3AC + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + REDUNDANCY_SIG0 + Cache redundancy signal 0 register + 0x3B0 + 0x20 + + + CACHE_REDCY_SIG0 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG1 + Cache redundancy signal 1 register + 0x3B4 + 0x20 + + + CACHE_REDCY_SIG1 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG2 + Cache redundancy signal 2 register + 0x3B8 + 0x20 + + + CACHE_REDCY_SIG2 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG3 + Cache redundancy signal 3 register + 0x3BC + 0x20 + + + CACHE_REDCY_SIG3 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG4 + Cache redundancy signal 0 register + 0x3C0 + 0x20 + + + CACHE_REDCY_SIG4 + Those bits are prepared for ECO. + 0 + 4 + read-only + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02202080 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x60091000 + + 0x0 + 0x39C + registers + + + GPIO + 30 + + + GPIO_NMI + 31 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register for GPIO0-31 + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-31 + 0 + 32 + read-write + + + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT1 + GPIO output register for GPIO32-34 + 0x10 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO32-34 + 0 + 3 + read-write + + + + + OUT1_W1TS + GPIO output set register for GPIO32-34 + 0x14 + 0x20 + + + OUT1_W1TS + GPIO output set register for GPIO32-34 + 0 + 3 + write-only + + + + + OUT1_W1TC + GPIO output clear register for GPIO32-34 + 0x18 + 0x20 + + + OUT1_W1TC + GPIO output clear register for GPIO32-34 + 0 + 3 + write-only + + + + + SDIO_SELECT + GPIO sdio select register + 0x1C + 0x20 + + + SDIO_SEL + GPIO sdio select register + 0 + 8 + read-write + + + + + ENABLE + GPIO output enable register for GPIO0-31 + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-31 + 0 + 32 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE1 + GPIO output enable register for GPIO32-34 + 0x2C + 0x20 + + + DATA + GPIO output enable register for GPIO32-34 + 0 + 3 + read-write + + + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-34 + 0x30 + 0x20 + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-34 + 0 + 3 + write-only + + + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-34 + 0x34 + 0x20 + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-34 + 0 + 3 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register for GPIO0-31 + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-31 + 0 + 32 + read-only + + + + + IN1 + GPIO input register for GPIO32-34 + 0x40 + 0x20 + + + DATA_NEXT + GPIO input register for GPIO32-34 + 0 + 3 + read-only + + + + + STATUS + GPIO interrupt status register for GPIO0-31 + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-31 + 0 + 32 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS1 + GPIO interrupt status register for GPIO32-34 + 0x50 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO32-34 + 0 + 3 + read-write + + + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-34 + 0x54 + 0x20 + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-34 + 0 + 3 + write-only + + + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-34 + 0x58 + 0x20 + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-34 + 0 + 3 + write-only + + + + + PCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0x5C + 0x20 + + + PROCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0x60 + 0x20 + + + PROCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + CPUSDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0x64 + 0x20 + + + SDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_INT1 + GPIO PRO_CPU interrupt status register for GPIO32-34 + 0x68 + 0x20 + + + PROCPU_INT1 + GPIO PRO_CPU interrupt status register for GPIO32-34 + 0 + 3 + read-only + + + + + PCPU_NMI_INT1 + GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + 0x6C + 0x20 + + + PROCPU_NMI_INT1 + GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + 0 + 3 + read-only + + + + + CPUSDIO_INT1 + GPIO CPUSDIO interrupt status register for GPIO32-34 + 0x70 + 0x20 + + + SDIO_INT1 + GPIO CPUSDIO interrupt status register for GPIO32-34 + 0 + 3 + read-only + + + + + 35 + 0x4 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + STATUS_NEXT + GPIO interrupt source register for GPIO0-31 + 0x14C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-31 + 0 + 32 + read-only + + + + + STATUS_NEXT1 + GPIO interrupt source register for GPIO32-34 + 0x150 + 0x20 + + + STATUS_INTERRUPT_NEXT1 + GPIO interrupt source register for GPIO32-34 + 0 + 3 + read-only + + + + + 128 + 0x4 + 0-127 + FUNC%s_IN_SEL_CFG + GPIO input function configuration register + 0x154 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + 30 + 0x4 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x554 + 0x20 + 0x00000080 + + + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 8 + read-write + + + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 8 + 1 + read-write + + + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 9 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 10 + 1 + read-write + + + + + CLOCK_GATE + GPIO clock gate register + 0x62C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + DATE + GPIO version register + 0x6FC + 0x20 + 0x02201120 + + + DATE + version register + 0 + 28 + read-write + + + + + + + GPIO_SD + Sigma-Delta Modulation + GPIOSD + 0x60091F00 + + 0x0 + 0x7C + registers + + + + 4 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD0_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD0_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + CLOCK_GATE + Clock Gating Configure Register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 0 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + 8 + 0x4 + GLITCH_FILTER_CH%s + Glitch Filter Configure Register of Channel%s + 0x30 + 0x20 + + + FILTER_CH0_EN + Glitch Filter channel enable bit. + 0 + 1 + read-write + + + FILTER_CH0_INPUT_IO_NUM + Glitch Filter input io number. + 1 + 6 + read-write + + + FILTER_CH0_WINDOW_THRES + Glitch Filter window threshold. + 7 + 6 + read-write + + + FILTER_CH0_WINDOW_WIDTH + Glitch Filter window width. + 13 + 6 + read-write + + + + + 8 + 0x4 + ETM_EVENT_CH%s_CFG + Etm Config register of Channel%s + 0x60 + 0x20 + + + ETM_CH0_EVENT_SEL + Etm event channel select gpio. + 0 + 5 + read-write + + + ETM_CH0_EVENT_EN + Etm event send enable bit. + 7 + 1 + read-write + + + + + ETM_TASK_P0_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA0 + 0x20 + + + ETM_TASK_GPIO0_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO0_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO1_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO1_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO2_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO2_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO3_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO3_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P1_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA4 + 0x20 + + + ETM_TASK_GPIO4_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO4_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO5_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO5_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO6_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO6_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO7_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO7_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P2_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA8 + 0x20 + + + ETM_TASK_GPIO8_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO8_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO9_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO9_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO10_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO10_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO11_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO11_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P3_CFG + Etm Configure Register to decide which GPIO been chosen + 0xAC + 0x20 + + + ETM_TASK_GPIO12_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO12_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO13_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO13_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO14_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO14_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO15_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO15_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P4_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB0 + 0x20 + + + ETM_TASK_GPIO16_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO16_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO17_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO17_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO18_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO18_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO19_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO19_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P5_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB4 + 0x20 + + + ETM_TASK_GPIO20_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO20_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO21_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO21_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO22_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO22_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO23_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO23_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P6_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB8 + 0x20 + + + ETM_TASK_GPIO24_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO24_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO25_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO25_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO26_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO26_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO27_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO27_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P7_CFG + Etm Configure Register to decide which GPIO been chosen + 0xBC + 0x20 + + + ETM_TASK_GPIO28_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO28_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO29_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO29_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO30_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO30_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + + + VERSION + Version Control Register + 0xFC + 0x20 + 0x02203050 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + + + HINF + HINF Peripheral + HINF + 0x60016000 + + 0x0 + 0x54 + registers + + + + CFG_DATA0 + Configure sdio cis content + 0x0 + 0x20 + 0x00926666 + + + DEVICE_ID_FN1 + configure device id of function1 in cis + 0 + 16 + read-write + + + USER_ID_FN1 + configure user id of function1 in cis + 16 + 16 + read-write + + + + + CFG_DATA1 + SDIO configuration register + 0x4 + 0x20 + 0x00232011 + + + SDIO_ENABLE + Sdio clock enable + 0 + 1 + read-write + + + SDIO_IOREADY1 + sdio function1 io ready signal in cis + 1 + 1 + read-write + + + HIGHSPEED_ENABLE + Highspeed enable in cccr + 2 + 1 + read-write + + + HIGHSPEED_MODE + highspeed mode status in cccr + 3 + 1 + read-only + + + SDIO_CD_ENABLE + sdio card detect enable + 4 + 1 + read-write + + + SDIO_IOREADY2 + sdio function1 io ready signal in cis + 5 + 1 + read-write + + + SDIO_INT_MASK + mask sdio interrupt in cccr, high active + 6 + 1 + read-write + + + IOENABLE2 + ioe2 status in cccr + 7 + 1 + read-only + + + CD_DISABLE + card disable status in cccr + 8 + 1 + read-only + + + FUNC1_EPS + function1 eps status in fbr + 9 + 1 + read-only + + + EMP + empc status in cccr + 10 + 1 + read-only + + + IOENABLE1 + ioe1 status in cccr + 11 + 1 + read-only + + + SDIO_VER + sdio version in cccr + 12 + 12 + read-write + + + FUNC2_EPS + function2 eps status in fbr + 24 + 1 + read-only + + + SDIO20_CONF + [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat in delayed cycles control,0:no delay, 1:delay 1 cycle. +[25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed mode. +[26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when [12]=0,posedge when highspeed mode enable. +[27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. +[28]: sdio data pad pull up enable + 25 + 7 + read-write + + + + + CFG_TIMING + Timing configuration registers + 0x8 + 0x20 + 0x15780812 + + + NCRC + configure Ncrc parameter in sdr50/104 mode, no more than 6. + 0 + 3 + read-write + + + PST_END_CMD_LOW_VALUE + configure cycles to lower cmd after voltage is changed to 1.8V. + 3 + 7 + read-write + + + PST_END_DATA_LOW_VALUE + configure cycles to lower data after voltage is changed to 1.8V. + 10 + 6 + read-write + + + SDCLK_STOP_THRES + Configure the number of cycles of module clk to judge sdclk has stopped + 16 + 11 + read-write + + + SAMPLE_CLK_DIVIDER + module clk divider to sample sdclk + 28 + 4 + read-write + + + + + CFG_UPDATE + update sdio configurations + 0xC + 0x20 + + + CONF_UPDATE + update the timing configurations + 0 + 1 + write-only + + + + + CFG_DATA7 + SDIO configuration register + 0x1C + 0x20 + 0x23820000 + + + PIN_STATE + configure cis addr 318 and 574 + 0 + 8 + read-write + + + CHIP_STATE + configure cis addr 312, 315, 568 and 571 + 8 + 8 + read-write + + + SDIO_RST + soft reset control for sdio module + 16 + 1 + read-write + + + SDIO_IOREADY0 + sdio io ready, high enable + 17 + 1 + read-write + + + SDIO_MEM_PD + sdio memory power down, high active + 18 + 1 + read-write + + + ESDIO_DATA1_INT_EN + enable sdio interrupt on data1 line + 19 + 1 + read-write + + + SDIO_SWITCH_VOLT_SW + control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + 20 + 1 + read-write + + + DDR50_BLK_LEN_FIX_EN + enable block length to be fixed to 512 bytes in ddr50 mode + 21 + 1 + read-write + + + CLK_EN + sdio apb clock for configuration force on control:0-gating,1-force on. + 22 + 1 + read-write + + + SDDR50 + configure if support sdr50 mode in cccr + 23 + 1 + read-write + + + SSDR104 + configure if support sdr104 mode in cccr + 24 + 1 + read-write + + + SSDR50 + configure if support ddr50 mode in cccr + 25 + 1 + read-write + + + SDTD + configure if support driver type D in cccr + 26 + 1 + read-write + + + SDTA + configure if support driver type A in cccr + 27 + 1 + read-write + + + SDTC + configure if support driver type C in cccr + 28 + 1 + read-write + + + SAI + configure if support asynchronous interrupt in cccr + 29 + 1 + read-write + + + SDIO_WAKEUP_CLR + clear sdio_wake_up signal after the chip wakes up + 30 + 1 + write-only + + + + + CIS_CONF_W0 + SDIO cis configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W0 + Configure cis addr 39~36 + 0 + 32 + read-write + + + + + CIS_CONF_W1 + SDIO cis configuration register + 0x24 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W1 + Configure cis addr 43~40 + 0 + 32 + read-write + + + + + CIS_CONF_W2 + SDIO cis configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W2 + Configure cis addr 47~44 + 0 + 32 + read-write + + + + + CIS_CONF_W3 + SDIO cis configuration register + 0x2C + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W3 + Configure cis addr 51~48 + 0 + 32 + read-write + + + + + CIS_CONF_W4 + SDIO cis configuration register + 0x30 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W4 + Configure cis addr 55~52 + 0 + 32 + read-write + + + + + CIS_CONF_W5 + SDIO cis configuration register + 0x34 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W5 + Configure cis addr 59~56 + 0 + 32 + read-write + + + + + CIS_CONF_W6 + SDIO cis configuration register + 0x38 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W6 + Configure cis addr 63~60 + 0 + 32 + read-write + + + + + CIS_CONF_W7 + SDIO cis configuration register + 0x3C + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W7 + Configure cis addr 67~64 + 0 + 32 + read-write + + + + + CFG_DATA16 + SDIO cis configuration register + 0x40 + 0x20 + 0x00927777 + + + DEVICE_ID_FN2 + configure device id of function2 in cis + 0 + 16 + read-write + + + USER_ID_FN2 + configure user id of function2 in cis + 16 + 16 + read-write + + + + + CFG_UHS1_INT_MODE + configure int to start and end ahead of time in uhs1 mode + 0x44 + 0x20 + + + INTOE_END_AHEAD_MODE + intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + 0 + 2 + read-write + + + INT_END_AHEAD_MODE + int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + 2 + 2 + read-write + + + INTOE_ST_AHEAD_MODE + intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + 4 + 2 + read-write + + + INT_ST_AHEAD_MODE + int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + 6 + 2 + read-write + + + + + CONF_STATUS + func0 config0 status + 0x54 + 0x20 + + + FUNC0_CONFIG0 + func0 config0 (addr: 0x20f0 ) status + 0 + 8 + read-only + + + SDR25_ST + sdr25 status + 8 + 1 + read-only + + + SDR50_ST + sdr50 status + 9 + 1 + read-only + + + SDR104_ST + sdr104 status + 10 + 1 + read-only + + + DDR50_ST + ddr50 status + 11 + 1 + read-only + + + TUNE_ST + tune_st fsm status + 12 + 3 + read-only + + + SDIO_SWITCH_VOLT_ST + sdio switch voltage status:0-3.3V, 1-1.8V. + 15 + 1 + read-only + + + SDIO_SWITCH_END + sdio switch voltage ldo ready + 16 + 1 + read-only + + + + + SDIO_SLAVE_ECO_LOW + sdio_slave redundant control registers + 0xA4 + 0x20 + + + RDN_ECO_LOW + redundant registers for sdio_slave + 0 + 32 + read-write + + + + + SDIO_SLAVE_ECO_HIGH + sdio_slave redundant control registers + 0xA8 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + redundant registers for sdio_slave + 0 + 32 + read-write + + + + + SDIO_SLAVE_ECO_CONF + sdio_slave redundant control registers + 0xAC + 0x20 + + + SDIO_SLAVE_RDN_RESULT + redundant registers for sdio_slave + 0 + 1 + read-only + + + SDIO_SLAVE_RDN_ENA + redundant registers for sdio_slave + 1 + 1 + read-write + + + SDIO_SLAVE_SDIO_CLK_RDN_RESULT + redundant registers for sdio_slave + 2 + 1 + read-only + + + SDIO_SLAVE_SDIO_CLK_RDN_ENA + redundant registers for sdio_slave + 3 + 1 + read-write + + + SDIO_SLAVE_SDCLK_PAD_RDN_RESULT + redundant registers for sdio_slave + 4 + 1 + read-only + + + SDIO_SLAVE_SDCLK_PAD_RDN_ENA + redundant registers for sdio_slave + 5 + 1 + read-write + + + + + SDIO_SLAVE_LDO_CONF + sdio slave ldo control register + 0xB0 + 0x20 + 0x00000014 + + + LDO_READY_CTL_IN_EN + control ldo ready signal by sdio slave itself + 0 + 1 + read-write + + + LDO_READY_THRES + configure ldo ready counting threshold value, the actual counting target is 2^(ldo_ready_thres)-1 + 1 + 5 + read-write + + + LDO_READY_IGNORE_EN + ignore ldo ready signal + 6 + 1 + read-write + + + + + SDIO_DATE + ******* Description *********** + 0xFC + 0x20 + 0x02203150 + + + SDIO_DATE + sdio version date. + 0 + 32 + read-write + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x6008D000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + + + SET_START + Start hmac operation. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + + + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + + + SET_PARA_END + Finish hmac configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + + + SET_TEXT_ING + Continue typical hmac. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + + + SET_TEXT_END + Start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + + + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 + 1 + write-only + + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + + + QUERY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 + 1 + read-only + + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + + + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 64 + 0x1 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x8 + + + 32 + 0x1 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x8 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 + 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + DATE + Date register. + 0x1FC + 0x20 + 0x20200618 + + + DATE + Hmac date information/ hmac version information. + 0 + 30 + read-write + + + + + + + HP_APM + HP_APM Peripheral + HP_APM + 0x60099000 + + 0x0 + 0x114 + registers + + + HP_APM_M0 + 35 + + + HP_APM_M1 + 36 + + + HP_APM_M2 + 37 + + + HP_APM_M3 + 38 + + + + REGION_FILTER_EN + Region filter enable register + 0x0 + 0x20 + 0x00000001 + + + REGION_FILTER_EN + Region filter enable + 0 + 16 + read-write + + + + + REGION0_ADDR_START + Region address register + 0x4 + 0x20 + + + REGION0_ADDR_START + Start address of region0 + 0 + 32 + read-write + + + + + REGION0_ADDR_END + Region address register + 0x8 + 0x20 + 0xFFFFFFFF + + + REGION0_ADDR_END + End address of region0 + 0 + 32 + read-write + + + + + REGION0_PMS_ATTR + Region access authority attribute register + 0xC + 0x20 + + + REGION0_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION0_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION0_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION0_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION0_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION0_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION0_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION0_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION0_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION1_ADDR_START + Region address register + 0x10 + 0x20 + + + REGION1_ADDR_START + Start address of region1 + 0 + 32 + read-write + + + + + REGION1_ADDR_END + Region address register + 0x14 + 0x20 + 0xFFFFFFFF + + + REGION1_ADDR_END + End address of region1 + 0 + 32 + read-write + + + + + REGION1_PMS_ATTR + Region access authority attribute register + 0x18 + 0x20 + + + REGION1_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION1_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION1_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION1_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION1_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION1_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION1_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION1_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION1_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION2_ADDR_START + Region address register + 0x1C + 0x20 + + + REGION2_ADDR_START + Start address of region2 + 0 + 32 + read-write + + + + + REGION2_ADDR_END + Region address register + 0x20 + 0x20 + 0xFFFFFFFF + + + REGION2_ADDR_END + End address of region2 + 0 + 32 + read-write + + + + + REGION2_PMS_ATTR + Region access authority attribute register + 0x24 + 0x20 + + + REGION2_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION2_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION2_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION2_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION2_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION2_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION2_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION2_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION2_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION3_ADDR_START + Region address register + 0x28 + 0x20 + + + REGION3_ADDR_START + Start address of region3 + 0 + 32 + read-write + + + + + REGION3_ADDR_END + Region address register + 0x2C + 0x20 + 0xFFFFFFFF + + + REGION3_ADDR_END + End address of region3 + 0 + 32 + read-write + + + + + REGION3_PMS_ATTR + Region access authority attribute register + 0x30 + 0x20 + + + REGION3_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION3_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION3_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION3_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION3_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION3_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION3_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION3_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION3_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION4_ADDR_START + Region address register + 0x34 + 0x20 + + + REGION4_ADDR_START + Start address of region4 + 0 + 32 + read-write + + + + + REGION4_ADDR_END + Region address register + 0x38 + 0x20 + 0xFFFFFFFF + + + REGION4_ADDR_END + End address of region4 + 0 + 32 + read-write + + + + + REGION4_PMS_ATTR + Region access authority attribute register + 0x3C + 0x20 + + + REGION4_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION4_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION4_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION4_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION4_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION4_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION4_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION4_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION4_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION5_ADDR_START + Region address register + 0x40 + 0x20 + + + REGION5_ADDR_START + Start address of region5 + 0 + 32 + read-write + + + + + REGION5_ADDR_END + Region address register + 0x44 + 0x20 + 0xFFFFFFFF + + + REGION5_ADDR_END + End address of region5 + 0 + 32 + read-write + + + + + REGION5_PMS_ATTR + Region access authority attribute register + 0x48 + 0x20 + + + REGION5_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION5_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION5_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION5_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION5_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION5_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION5_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION5_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION5_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION6_ADDR_START + Region address register + 0x4C + 0x20 + + + REGION6_ADDR_START + Start address of region6 + 0 + 32 + read-write + + + + + REGION6_ADDR_END + Region address register + 0x50 + 0x20 + 0xFFFFFFFF + + + REGION6_ADDR_END + End address of region6 + 0 + 32 + read-write + + + + + REGION6_PMS_ATTR + Region access authority attribute register + 0x54 + 0x20 + + + REGION6_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION6_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION6_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION6_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION6_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION6_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION6_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION6_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION6_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION7_ADDR_START + Region address register + 0x58 + 0x20 + + + REGION7_ADDR_START + Start address of region7 + 0 + 32 + read-write + + + + + REGION7_ADDR_END + Region address register + 0x5C + 0x20 + 0xFFFFFFFF + + + REGION7_ADDR_END + End address of region7 + 0 + 32 + read-write + + + + + REGION7_PMS_ATTR + Region access authority attribute register + 0x60 + 0x20 + + + REGION7_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION7_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION7_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION7_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION7_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION7_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION7_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION7_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION7_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION8_ADDR_START + Region address register + 0x64 + 0x20 + + + REGION8_ADDR_START + Start address of region8 + 0 + 32 + read-write + + + + + REGION8_ADDR_END + Region address register + 0x68 + 0x20 + 0xFFFFFFFF + + + REGION8_ADDR_END + End address of region8 + 0 + 32 + read-write + + + + + REGION8_PMS_ATTR + Region access authority attribute register + 0x6C + 0x20 + + + REGION8_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION8_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION8_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION8_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION8_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION8_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION8_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION8_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION8_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION9_ADDR_START + Region address register + 0x70 + 0x20 + + + REGION9_ADDR_START + Start address of region9 + 0 + 32 + read-write + + + + + REGION9_ADDR_END + Region address register + 0x74 + 0x20 + 0xFFFFFFFF + + + REGION9_ADDR_END + End address of region9 + 0 + 32 + read-write + + + + + REGION9_PMS_ATTR + Region access authority attribute register + 0x78 + 0x20 + + + REGION9_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION9_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION9_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION9_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION9_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION9_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION9_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION9_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION9_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION10_ADDR_START + Region address register + 0x7C + 0x20 + + + REGION10_ADDR_START + Start address of region10 + 0 + 32 + read-write + + + + + REGION10_ADDR_END + Region address register + 0x80 + 0x20 + 0xFFFFFFFF + + + REGION10_ADDR_END + End address of region10 + 0 + 32 + read-write + + + + + REGION10_PMS_ATTR + Region access authority attribute register + 0x84 + 0x20 + + + REGION10_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION10_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION10_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION10_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION10_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION10_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION10_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION10_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION10_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION11_ADDR_START + Region address register + 0x88 + 0x20 + + + REGION11_ADDR_START + Start address of region11 + 0 + 32 + read-write + + + + + REGION11_ADDR_END + Region address register + 0x8C + 0x20 + 0xFFFFFFFF + + + REGION11_ADDR_END + End address of region11 + 0 + 32 + read-write + + + + + REGION11_PMS_ATTR + Region access authority attribute register + 0x90 + 0x20 + + + REGION11_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION11_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION11_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION11_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION11_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION11_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION11_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION11_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION11_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION12_ADDR_START + Region address register + 0x94 + 0x20 + + + REGION12_ADDR_START + Start address of region12 + 0 + 32 + read-write + + + + + REGION12_ADDR_END + Region address register + 0x98 + 0x20 + 0xFFFFFFFF + + + REGION12_ADDR_END + End address of region12 + 0 + 32 + read-write + + + + + REGION12_PMS_ATTR + Region access authority attribute register + 0x9C + 0x20 + + + REGION12_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION12_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION12_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION12_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION12_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION12_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION12_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION12_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION12_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION13_ADDR_START + Region address register + 0xA0 + 0x20 + + + REGION13_ADDR_START + Start address of region13 + 0 + 32 + read-write + + + + + REGION13_ADDR_END + Region address register + 0xA4 + 0x20 + 0xFFFFFFFF + + + REGION13_ADDR_END + End address of region13 + 0 + 32 + read-write + + + + + REGION13_PMS_ATTR + Region access authority attribute register + 0xA8 + 0x20 + + + REGION13_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION13_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION13_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION13_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION13_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION13_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION13_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION13_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION13_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION14_ADDR_START + Region address register + 0xAC + 0x20 + + + REGION14_ADDR_START + Start address of region14 + 0 + 32 + read-write + + + + + REGION14_ADDR_END + Region address register + 0xB0 + 0x20 + 0xFFFFFFFF + + + REGION14_ADDR_END + End address of region14 + 0 + 32 + read-write + + + + + REGION14_PMS_ATTR + Region access authority attribute register + 0xB4 + 0x20 + + + REGION14_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION14_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION14_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION14_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION14_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION14_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION14_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION14_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION14_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION15_ADDR_START + Region address register + 0xB8 + 0x20 + + + REGION15_ADDR_START + Start address of region15 + 0 + 32 + read-write + + + + + REGION15_ADDR_END + Region address register + 0xBC + 0x20 + 0xFFFFFFFF + + + REGION15_ADDR_END + End address of region15 + 0 + 32 + read-write + + + + + REGION15_PMS_ATTR + Region access authority attribute register + 0xC0 + 0x20 + + + REGION15_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION15_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION15_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION15_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION15_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION15_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION15_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION15_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION15_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + FUNC_CTRL + PMS function control register + 0xC4 + 0x20 + 0x0000000F + + + M0_PMS_FUNC_EN + PMS M0 function enable + 0 + 1 + read-write + + + M1_PMS_FUNC_EN + PMS M1 function enable + 1 + 1 + read-write + + + M2_PMS_FUNC_EN + PMS M2 function enable + 2 + 1 + read-write + + + M3_PMS_FUNC_EN + PMS M3 function enable + 3 + 1 + read-write + + + + + M0_STATUS + M0 status register + 0xC8 + 0x20 + + + M0_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M0_STATUS_CLR + M0 status clear register + 0xCC + 0x20 + + + M0_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M0_EXCEPTION_INFO0 + M0 exception_info0 register + 0xD0 + 0x20 + + + M0_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M0_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M0_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M0_EXCEPTION_INFO1 + M0 exception_info1 register + 0xD4 + 0x20 + + + M0_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M1_STATUS + M1 status register + 0xD8 + 0x20 + + + M1_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M1_STATUS_CLR + M1 status clear register + 0xDC + 0x20 + + + M1_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M1_EXCEPTION_INFO0 + M1 exception_info0 register + 0xE0 + 0x20 + + + M1_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M1_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M1_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M1_EXCEPTION_INFO1 + M1 exception_info1 register + 0xE4 + 0x20 + + + M1_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M2_STATUS + M2 status register + 0xE8 + 0x20 + + + M2_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M2_STATUS_CLR + M2 status clear register + 0xEC + 0x20 + + + M2_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M2_EXCEPTION_INFO0 + M2 exception_info0 register + 0xF0 + 0x20 + + + M2_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M2_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M2_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M2_EXCEPTION_INFO1 + M2 exception_info1 register + 0xF4 + 0x20 + + + M2_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M3_STATUS + M3 status register + 0xF8 + 0x20 + + + M3_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M3_STATUS_CLR + M3 status clear register + 0xFC + 0x20 + + + M3_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M3_EXCEPTION_INFO0 + M3 exception_info0 register + 0x100 + 0x20 + + + M3_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M3_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M3_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M3_EXCEPTION_INFO1 + M3 exception_info1 register + 0x104 + 0x20 + + + M3_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + INT_EN + APM interrupt enable register + 0x108 + 0x20 + + + M0_APM_INT_EN + APM M0 interrupt enable + 0 + 1 + read-write + + + M1_APM_INT_EN + APM M1 interrupt enable + 1 + 1 + read-write + + + M2_APM_INT_EN + APM M2 interrupt enable + 2 + 1 + read-write + + + M3_APM_INT_EN + APM M3 interrupt enable + 3 + 1 + read-write + + + + + CLOCK_GATE + clock gating register + 0x10C + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0x7FC + 0x20 + 0x02205240 + + + DATE + reg_date + 0 + 28 + read-write + + + + + + + HP_SYS + High-Power System + HP_SYS + 0x60095000 + + 0x0 + 0x5C + registers + + + HP_PERI_TIMEOUT + 33 + + + MODEM_PERI_TIMEOUT + 34 + + + + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + 0x0 + 0x20 + + + ENABLE_SPI_MANUAL_ENCRYPT + Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + 0 + 1 + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + reserved + 1 + 1 + read-write + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + 3 + 1 + read-write + + + + + SRAM_USAGE_CONF + HP memory usage configuration register + 0x4 + 0x20 + + + CACHE_USAGE + reserved + 0 + 1 + read-only + + + SRAM_USAGE + 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. + 8 + 4 + read-write + + + MAC_DUMP_ALLOC + Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + 16 + 1 + read-write + + + + + SEC_DPA_CONF + HP anti-DPA security configuration register + 0x8 + 0x20 + + + SEC_DPA_LEVEL + 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger the number, the stronger the ability to resist DPA attacks and the higher the security level, but it will increase the computational overhead of the hardware crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. + 0 + 2 + read-write + + + SEC_DPA_CFG_SEL + This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL. + 2 + 1 + read-write + + + + + CPU_PERI_TIMEOUT_CONF + CPU_PERI_TIMEOUT configuration register + 0xC + 0x20 + 0x0002FFFF + + + CPU_PERI_TIMEOUT_THRES + Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. + 0 + 16 + read-write + + + CPU_PERI_TIMEOUT_INT_CLEAR + Set this bit as 1 to clear timeout interrupt + 16 + 1 + write-only + + + CPU_PERI_TIMEOUT_PROTECT_EN + Set this bit as 1 to enable timeout protection for accessing cpu peripheral registers + 17 + 1 + read-write + + + + + CPU_PERI_TIMEOUT_ADDR + CPU_PERI_TIMEOUT_ADDR register + 0x10 + 0x20 + + + CPU_PERI_TIMEOUT_ADDR + Record the address information of abnormal access + 0 + 32 + read-only + + + + + CPU_PERI_TIMEOUT_UID + CPU_PERI_TIMEOUT_UID register + 0x14 + 0x20 + + + CPU_PERI_TIMEOUT_UID + Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. + 0 + 7 + read-only + + + + + HP_PERI_TIMEOUT_CONF + HP_PERI_TIMEOUT configuration register + 0x18 + 0x20 + 0x0002FFFF + + + HP_PERI_TIMEOUT_THRES + Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. + 0 + 16 + read-write + + + HP_PERI_TIMEOUT_INT_CLEAR + Set this bit as 1 to clear timeout interrupt + 16 + 1 + write-only + + + HP_PERI_TIMEOUT_PROTECT_EN + Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + 17 + 1 + read-write + + + + + HP_PERI_TIMEOUT_ADDR + HP_PERI_TIMEOUT_ADDR register + 0x1C + 0x20 + + + HP_PERI_TIMEOUT_ADDR + Record the address information of abnormal access + 0 + 32 + read-only + + + + + HP_PERI_TIMEOUT_UID + HP_PERI_TIMEOUT_UID register + 0x20 + 0x20 + + + HP_PERI_TIMEOUT_UID + Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. + 0 + 7 + read-only + + + + + MODEM_PERI_TIMEOUT_CONF + MODEM_PERI_TIMEOUT configuration register + 0x24 + 0x20 + 0x0002FFFF + + + MODEM_PERI_TIMEOUT_THRES + Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. + 0 + 16 + read-write + + + MODEM_PERI_TIMEOUT_INT_CLEAR + Set this bit as 1 to clear timeout interrupt + 16 + 1 + write-only + + + MODEM_PERI_TIMEOUT_PROTECT_EN + Set this bit as 1 to enable timeout protection for accessing modem registers + 17 + 1 + read-write + + + + + MODEM_PERI_TIMEOUT_ADDR + MODEM_PERI_TIMEOUT_ADDR register + 0x28 + 0x20 + + + MODEM_PERI_TIMEOUT_ADDR + Record the address information of abnormal access + 0 + 32 + read-only + + + + + MODEM_PERI_TIMEOUT_UID + MODEM_PERI_TIMEOUT_UID register + 0x2C + 0x20 + + + MODEM_PERI_TIMEOUT_UID + Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. + 0 + 7 + read-only + + + + + SDIO_CTRL + SDIO Control configuration register + 0x30 + 0x20 + 0x00000003 + + + DIS_SDIO_PROB + Set this bit as 1 to disable SDIO_PROB function. disable by default. + 0 + 1 + read-write + + + SDIO_WIN_ACCESS_EN + Enable sdio slave to access other peripherals on the chip + 1 + 1 + read-write + + + + + RETENTION_CONF + Retention configuration register + 0x34 + 0x20 + + + RETENTION_DISABLE + Set this bit as 1 to disable retention function. Not disable by default. + 0 + 1 + read-write + + + + + ROM_TABLE_LOCK + Rom-Table lock register + 0x38 + 0x20 + + + ROM_TABLE_LOCK + XXXX + 0 + 1 + read-write + + + + + ROM_TABLE + Rom-Table register + 0x3C + 0x20 + + + ROM_TABLE + XXXX + 0 + 32 + read-write + + + + + CORE_DEBUG_RUNSTALL_CONF + Core Debug runstall configure register + 0x40 + 0x20 + + + CORE_DEBUG_RUNSTALL_ENABLE + Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + 0 + 1 + read-write + + + + + MEM_TEST_CONF + MEM_TEST configuration register + 0x44 + 0x20 + 0x00000020 + + + HP_MEM_WPULSE + This field controls hp system memory WPULSE parameter. + 0 + 3 + read-write + + + HP_MEM_WA + This field controls hp system memory WA parameter. + 3 + 3 + read-write + + + HP_MEM_RA + This field controls hp system memory RA parameter. + 6 + 2 + read-write + + + + + RND_ECO + redcy eco register. + 0x3E0 + 0x20 + + + REDCY_ENA + Only reserved for ECO. + 0 + 1 + read-write + + + REDCY_RESULT + Only reserved for ECO. + 1 + 1 + read-only + + + + + RND_ECO_LOW + redcy eco low register. + 0x3E4 + 0x20 + + + REDCY_LOW + Only reserved for ECO. + 0 + 32 + read-write + + + + + RND_ECO_HIGH + redcy eco high register. + 0x3E8 + 0x20 + 0xFFFFFFFF + + + REDCY_HIGH + Only reserved for ECO. + 0 + 32 + read-write + + + + + CLOCK_GATE + HP-SYSTEM clock gating configure register + 0x3F8 + 0x20 + + + CLK_EN + Set this bit as 1 to force on clock gating. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x02206110 + + + DATE + HP-SYSTEM date information/ HP-SYSTEM version information. + 0 + 28 + read-write + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller 0 + I2C + 0x60004000 + + 0x0 + 0x90 + registers + + + I2C_MASTER + 11 + + + I2C_EXT0 + 50 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + 1: direct output, 0: open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + 1: direct output, 0: open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Set this bit to configure the module as an I2C Master. Clear this bit to configure the +module as an I2C Slave. + 4 + 1 + read-write + + + TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit, +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit, +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Reserved + 8 + 1 + read-write + + + ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + This is the enable bit for slave to send data automatically + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + This is the enable bit to support the 7bit general call function. + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + When in slave mode, 1: master reads from slave, 0: master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + BUS_BUSY + 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + When configured as an I2C Slave, and the address sent by the master is +equal to the address of the slave, then this bit will be of high level. + 5 + 1 + read-only + + + RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + When configured as an I2C Slave, this field is used to configure the slave address. + 0 + 15 + read-write + + + ADDR_10BIT_EN + This field is used to enable the slave 10-bit addressing mode in master mode. + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 5 + read-only + + + RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 5 + read-only + + + TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 5 + read-only + + + TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 5 + read-only + + + SLAVE_RW_POINT + The received data in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. + 11 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + write-only + + + SLAVE_ADDR_UNMATCH_INT_CLR + Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-write + + + SLAVE_ADDR_UNMATCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + 8 + 0x4 + 0-7 + COMD%s + I2C command register %s + 0x58 + 0x20 + + + COMMAND + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + Configure the period of I2C slave stretching SCL line. + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Set this bit to clear the I2C slave SCL stretch function. + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + The enable bit for slave to control ACK level function. + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. + 13 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201172 + + + DATE + This is the the version register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + I2S0 + I2S (Inter-IC Sound) Controller 0 + I2S + 0x6000C000 + + 0x0 + 0x60 + registers + + + I2S1 + 41 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x0000B200 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 5 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 13 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 24 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 27 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x6F3DE300 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 7 + 6 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 18 + 6 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 29 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 30 + 1 + read-write + + + + + RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 + 1 + read-write + + + + + TX_CLKM_CONF + I2S TX clock configure register + 0x34 + 0x20 + 0x00000002 + + + TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 0 + 8 + read-write + + + TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 + 0x20 + 0x004AA004 + + + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. + 0 + 1 + read-write + + + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write + + + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 + read-write + + + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 + 1 + read-write + + + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 + 1 + read-write + + + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 + read-write + + + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 + read-write + + + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 + 1 + read-write + + + + + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 + 0x20 + 0x03F783C0 + + + TX_PDM_FP + I2S TX PDM Fp + 0 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + ETM_CONF + I2S ETM configure register + 0x70 + 0x20 + 0x00010040 + + + ETM_TX_SEND_WORD_NUM + I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + 0 + 10 + read-write + + + ETM_RX_RECEIVE_WORD_NUM + I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + 10 + 10 + read-write + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02201070 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE0 + Interrupt Controller (Core 0) + INTMTX_CORE0 + 0x60010000 + + 0x0 + 0x148 + registers + + + WIFI_MAC + 0 + + + WIFI_MAC_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + LP_TIMER + 7 + + + COEX + 8 + + + BLE_TIMER + 9 + + + BLE_SEC + 10 + + + ZB_MAC + 12 + + + FROM_CPU_INTR0 + 22 + + + FROM_CPU_INTR1 + 23 + + + FROM_CPU_INTR2 + 24 + + + FROM_CPU_INTR3 + 25 + + + CACHE + 28 + + + CPU_PERI_TIMEOUT + 29 + + + + WIFI_MAC_INTR_MAP + register description + 0x0 + 0x20 + + + WIFI_MAC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_MAC_NMI_MAP + register description + 0x4 + 0x20 + + + WIFI_MAC_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_PWR_INTR_MAP + register description + 0x8 + 0x20 + + + WIFI_PWR_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_BB_INTR_MAP + register description + 0xC + 0x20 + + + WIFI_BB_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BT_MAC_INTR_MAP + register description + 0x10 + 0x20 + + + BT_MAC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BT_BB_INTR_MAP + register description + 0x14 + 0x20 + + + BT_BB_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + register description + 0x18 + 0x20 + + + BT_BB_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + LP_TIMER_INTR_MAP + register description + 0x1C + 0x20 + + + LP_TIMER_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + COEX_INTR_MAP + register description + 0x20 + 0x20 + + + COEX_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BLE_TIMER_INTR_MAP + register description + 0x24 + 0x20 + + + BLE_TIMER_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BLE_SEC_INTR_MAP + register description + 0x28 + 0x20 + + + BLE_SEC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + I2C_MST_INTR_MAP + register description + 0x2C + 0x20 + + + I2C_MST_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + ZB_MAC_INTR_MAP + register description + 0x30 + 0x20 + + + ZB_MAC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + PMU_INTR_MAP + register description + 0x34 + 0x20 + + + PMU_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + EFUSE_INTR_MAP + register description + 0x38 + 0x20 + + + EFUSE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_RTC_TIMER_INTR_MAP + register description + 0x3C + 0x20 + + + LP_RTC_TIMER_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_UART_INTR_MAP + register description + 0x40 + 0x20 + + + LP_UART_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_I2C_INTR_MAP + register description + 0x44 + 0x20 + + + LP_I2C_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_WDT_INTR_MAP + register description + 0x48 + 0x20 + + + LP_WDT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_PERI_TIMEOUT_INTR_MAP + register description + 0x4C + 0x20 + + + LP_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_APM_M0_INTR_MAP + register description + 0x50 + 0x20 + + + LP_APM_M0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_APM_M1_INTR_MAP + register description + 0x54 + 0x20 + + + LP_APM_M1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + register description + 0x58 + 0x20 + + + CPU_INTR_FROM_CPU_0_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + register description + 0x5C + 0x20 + + + CPU_INTR_FROM_CPU_1_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + register description + 0x60 + 0x20 + + + CPU_INTR_FROM_CPU_2_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + register description + 0x64 + 0x20 + + + CPU_INTR_FROM_CPU_3_MAP + Need add description + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + register description + 0x68 + 0x20 + + + ASSIST_DEBUG_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TRACE_INTR_MAP + register description + 0x6C + 0x20 + + + TRACE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CACHE_INTR_MAP + register description + 0x70 + 0x20 + + + CACHE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_PERI_TIMEOUT_INTR_MAP + register description + 0x74 + 0x20 + + + CPU_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + register description + 0x78 + 0x20 + + + GPIO_INTERRUPT_PRO_MAP + Need add description + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + register description + 0x7C + 0x20 + + + GPIO_INTERRUPT_PRO_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + PAU_INTR_MAP + register description + 0x80 + 0x20 + + + PAU_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_PERI_TIMEOUT_INTR_MAP + register description + 0x84 + 0x20 + + + HP_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + MODEM_PERI_TIMEOUT_INTR_MAP + register description + 0x88 + 0x20 + + + MODEM_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_APM_M0_INTR_MAP + register description + 0x8C + 0x20 + + + HP_APM_M0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_APM_M1_INTR_MAP + register description + 0x90 + 0x20 + + + HP_APM_M1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_APM_M2_INTR_MAP + register description + 0x94 + 0x20 + + + HP_APM_M2_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_APM_M3_INTR_MAP + register description + 0x98 + 0x20 + + + HP_APM_M3_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_APM0_INTR_MAP + register description + 0x9C + 0x20 + + + LP_APM0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + MSPI_INTR_MAP + register description + 0xA0 + 0x20 + + + MSPI_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + I2S1_INTR_MAP + register description + 0xA4 + 0x20 + + + I2S1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + UHCI0_INTR_MAP + register description + 0xA8 + 0x20 + + + UHCI0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + UART0_INTR_MAP + register description + 0xAC + 0x20 + + + UART0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + UART1_INTR_MAP + register description + 0xB0 + 0x20 + + + UART1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LEDC_INTR_MAP + register description + 0xB4 + 0x20 + + + LEDC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CAN0_INTR_MAP + register description + 0xB8 + 0x20 + + + CAN0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CAN1_INTR_MAP + register description + 0xBC + 0x20 + + + CAN1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + USB_INTR_MAP + register description + 0xC0 + 0x20 + + + USB_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + RMT_INTR_MAP + register description + 0xC4 + 0x20 + + + RMT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + I2C_EXT0_INTR_MAP + register description + 0xC8 + 0x20 + + + I2C_EXT0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG0_T0_INTR_MAP + register description + 0xCC + 0x20 + + + TG0_T0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG0_T1_INTR_MAP + register description + 0xD0 + 0x20 + + + TG0_T1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG0_WDT_INTR_MAP + register description + 0xD4 + 0x20 + + + TG0_WDT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG1_T0_INTR_MAP + register description + 0xD8 + 0x20 + + + TG1_T0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG1_T1_INTR_MAP + register description + 0xDC + 0x20 + + + TG1_T1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG1_WDT_INTR_MAP + register description + 0xE0 + 0x20 + + + TG1_WDT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SYSTIMER_TARGET0_INTR_MAP + register description + 0xE4 + 0x20 + + + SYSTIMER_TARGET0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SYSTIMER_TARGET1_INTR_MAP + register description + 0xE8 + 0x20 + + + SYSTIMER_TARGET1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SYSTIMER_TARGET2_INTR_MAP + register description + 0xEC + 0x20 + + + SYSTIMER_TARGET2_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + APB_ADC_INTR_MAP + register description + 0xF0 + 0x20 + + + APB_ADC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + PWM_INTR_MAP + register description + 0xF4 + 0x20 + + + PWM_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + PCNT_INTR_MAP + register description + 0xF8 + 0x20 + + + PCNT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + PARL_IO_INTR_MAP + register description + 0xFC + 0x20 + + + PARL_IO_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SLC0_INTR_MAP + register description + 0x100 + 0x20 + + + SLC0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SLC1_INTR_MAP + register description + 0x104 + 0x20 + + + SLC1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_IN_CH0_INTR_MAP + register description + 0x108 + 0x20 + + + DMA_IN_CH0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_IN_CH1_INTR_MAP + register description + 0x10C + 0x20 + + + DMA_IN_CH1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_IN_CH2_INTR_MAP + register description + 0x110 + 0x20 + + + DMA_IN_CH2_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_OUT_CH0_INTR_MAP + register description + 0x114 + 0x20 + + + DMA_OUT_CH0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_OUT_CH1_INTR_MAP + register description + 0x118 + 0x20 + + + DMA_OUT_CH1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_OUT_CH2_INTR_MAP + register description + 0x11C + 0x20 + + + DMA_OUT_CH2_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + GPSPI2_INTR_MAP + register description + 0x120 + 0x20 + + + GPSPI2_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + AES_INTR_MAP + register description + 0x124 + 0x20 + + + AES_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SHA_INTR_MAP + register description + 0x128 + 0x20 + + + SHA_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + RSA_INTR_MAP + register description + 0x12C + 0x20 + + + RSA_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + ECC_INTR_MAP + register description + 0x130 + 0x20 + + + ECC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + INTR_STATUS_REG_0 + register description + 0x134 + 0x20 + + + INTR_STATUS_0 + Need add description + 0 + 32 + read-only + + + + + INTR_STATUS_REG_1 + register description + 0x138 + 0x20 + + + INTR_STATUS_1 + Need add description + 0 + 32 + read-only + + + + + INT_STATUS_REG_2 + register description + 0x13C + 0x20 + + + INT_STATUS_2 + Need add description + 0 + 32 + read-only + + + + + CLOCK_GATE + register description + 0x140 + 0x20 + 0x00000001 + + + REG_CLK_EN + Need add description + 0 + 1 + read-write + + + + + INTERRUPT_REG_DATE + register description + 0x7FC + 0x20 + 0x02203110 + + + INTERRUPT_REG_DATE + Need add description + 0 + 28 + read-write + + + + + + + INTPRI + INTPRI Peripheral + INTPRI + 0x600C5000 + + 0x0 + 0xB8 + registers + + + + CPU_INT_ENABLE + register description + 0x0 + 0x20 + + + CPU_INT_ENABLE + Need add description + 0 + 32 + read-write + + + + + CPU_INT_TYPE + register description + 0x4 + 0x20 + + + CPU_INT_TYPE + Need add description + 0 + 32 + read-write + + + + + CPU_INT_EIP_STATUS + register description + 0x8 + 0x20 + + + CPU_INT_EIP_STATUS + Need add description + 0 + 32 + read-only + + + + + CPU_INT_PRI_0 + register description + 0xC + 0x20 + + + CPU_PRI_0_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_1 + register description + 0x10 + 0x20 + + + CPU_PRI_1_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_2 + register description + 0x14 + 0x20 + + + CPU_PRI_2_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_3 + register description + 0x18 + 0x20 + + + CPU_PRI_3_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_4 + register description + 0x1C + 0x20 + + + CPU_PRI_4_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_5 + register description + 0x20 + 0x20 + + + CPU_PRI_5_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_6 + register description + 0x24 + 0x20 + + + CPU_PRI_6_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_7 + register description + 0x28 + 0x20 + + + CPU_PRI_7_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_8 + register description + 0x2C + 0x20 + + + CPU_PRI_8_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_9 + register description + 0x30 + 0x20 + + + CPU_PRI_9_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_10 + register description + 0x34 + 0x20 + + + CPU_PRI_10_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_11 + register description + 0x38 + 0x20 + + + CPU_PRI_11_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_12 + register description + 0x3C + 0x20 + + + CPU_PRI_12_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_13 + register description + 0x40 + 0x20 + + + CPU_PRI_13_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_14 + register description + 0x44 + 0x20 + + + CPU_PRI_14_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_15 + register description + 0x48 + 0x20 + + + CPU_PRI_15_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_16 + register description + 0x4C + 0x20 + + + CPU_PRI_16_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_17 + register description + 0x50 + 0x20 + + + CPU_PRI_17_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_18 + register description + 0x54 + 0x20 + + + CPU_PRI_18_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_19 + register description + 0x58 + 0x20 + + + CPU_PRI_19_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_20 + register description + 0x5C + 0x20 + + + CPU_PRI_20_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_21 + register description + 0x60 + 0x20 + + + CPU_PRI_21_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_22 + register description + 0x64 + 0x20 + + + CPU_PRI_22_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_23 + register description + 0x68 + 0x20 + + + CPU_PRI_23_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_24 + register description + 0x6C + 0x20 + + + CPU_PRI_24_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_25 + register description + 0x70 + 0x20 + + + CPU_PRI_25_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_26 + register description + 0x74 + 0x20 + + + CPU_PRI_26_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_27 + register description + 0x78 + 0x20 + + + CPU_PRI_27_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_28 + register description + 0x7C + 0x20 + + + CPU_PRI_28_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_29 + register description + 0x80 + 0x20 + + + CPU_PRI_29_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_30 + register description + 0x84 + 0x20 + + + CPU_PRI_30_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_31 + register description + 0x88 + 0x20 + + + CPU_PRI_31_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_THRESH + register description + 0x8C + 0x20 + + + CPU_INT_THRESH + Need add description + 0 + 8 + read-write + + + + + CPU_INTR_FROM_CPU_0 + register description + 0x90 + 0x20 + + + CPU_INTR_FROM_CPU_0 + Need add description + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + register description + 0x94 + 0x20 + + + CPU_INTR_FROM_CPU_1 + Need add description + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + register description + 0x98 + 0x20 + + + CPU_INTR_FROM_CPU_2 + Need add description + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + register description + 0x9C + 0x20 + + + CPU_INTR_FROM_CPU_3 + Need add description + 0 + 1 + read-write + + + + + DATE + register description + 0xA0 + 0x20 + 0x02201090 + + + DATE + Need add description + 0 + 28 + read-write + + + + + CLOCK_GATE + register description + 0xA4 + 0x20 + 0x00000001 + + + CLK_EN + Need add description + 0 + 1 + read-write + + + + + CPU_INT_CLEAR + register description + 0xA8 + 0x20 + + + CPU_INT_CLEAR + Need add description + 0 + 32 + read-write + + + + + RND_ECO + redcy eco register. + 0xAC + 0x20 + + + REDCY_ENA + Only reserved for ECO. + 0 + 1 + read-write + + + REDCY_RESULT + Only reserved for ECO. + 1 + 1 + read-only + + + + + RND_ECO_LOW + redcy eco low register. + 0xB0 + 0x20 + + + REDCY_LOW + Only reserved for ECO. + 0 + 32 + read-write + + + + + RND_ECO_HIGH + redcy eco high register. + 0x3FC + 0x20 + 0xFFFFFFFF + + + REDCY_HIGH + Only reserved for ECO. + 0 + 32 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x60090000 + + 0x0 + 0x88 + registers + + + + PIN_CTRL + Clock Output Configuration Register + 0x0 + 0x20 + 0x00001DEF + + + CLK_OUT1 + If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. + 0 + 5 + read-write + + + CLK_OUT2 + If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. + 5 + 5 + read-write + + + CLK_OUT3 + If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. + 10 + 5 + read-write + + + + + 31 + 0x4 + GPIO%s + IO MUX Configure Register for pad XTAL_32K_P + 0x4 + 0x20 + 0x00000800 + + + MCU_OE + Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled. 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + 15 + 1 + read-write + + + + + MODEM_DIAG_EN + GPIO MATRIX Configure Register for modem diag + 0xBC + 0x20 + + + MODEM_DIAG_EN + bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio matrix. 0:enable other signals into gpio matrix + 0 + 32 + read-write + + + + + DATE + IO MUX Version Control Register + 0xFC + 0x20 + 0x02201060 + + + REG_DATE + Version control register + 0 + 28 + read-write + + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x60007000 + + 0x0 + 0x154 + registers + + + LEDC + 45 + + + + 6 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL + This field is used to select one of timers for channel %s. + +0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + 0 + 2 + read-write + + + SIG_OUT_EN + Set this bit to enable signal output on channel %s. + 2 + 1 + read-write + + + IDLE_LV + This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + 3 + 1 + read-write + + + PARA_UP + This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. + 4 + 1 + write-only + + + OVF_NUM + This register is used to configure the maximum times of overflow minus 1. + +The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN + This bit is used to enable the ovf_cnt of channel %s. + 15 + 1 + read-write + + + OVF_CNT_RESET + Set this bit to reset the ovf_cnt of channel %s. + 16 + 1 + write-only + + + + + 6 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT + The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 20 + read-write + + + + + 6 + 0x14 + CH%s_DUTY + Initial duty cycle for channel %s + 0x8 + 0x20 + + + DUTY + This register is used to change the output duty by controlling the Lpoint. + +The output value turns to low when the selected timers has reached the Lpoint. + 0 + 25 + read-write + + + + + 6 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + + + DUTY_START + Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + 31 + 1 + read-write + + + + + 6 + 0x14 + CH%s_DUTY_R + Current duty cycle for channel %s + 0x10 + 0x20 + + + DUTY_CH_R + This register stores the current duty of output signal on channel %s. + 0 + 25 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration + 0xA0 + 0x20 + 0x01000000 + + + DUTY_RES + This register is used to control the range of the counter in timer %s. + 0 + 5 + read-write + + + CLK_DIV + This register is used to configure the divisor for the divider in timer %s. + +The least significant eight bits represent the fractional part. + 5 + 18 + read-write + + + PAUSE + This bit is used to suspend the counter in timer %s. + 23 + 1 + read-write + + + RST + This bit is used to reset timer %s. The counter will show 0 after reset. + 24 + 1 + read-write + + + TICK_SEL + This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + +1'h0: SLOW_CLK 1'h1: REF_TICK + 25 + 1 + read-write + + + PARA_UP + Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + 26 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value + 0xA4 + 0x20 + + + TIMER_CNT + This register stores the current counter value of timer %s. + 0 + 20 + read-only + + + + + INT_RAW + Raw interrupt status + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-write + + + TIMER1_OVF_INT_RAW + Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-write + + + TIMER2_OVF_INT_RAW + Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-write + + + TIMER3_OVF_INT_RAW + Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + 9 + 1 + read-write + + + OVF_CNT_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0xC4 + 0x20 + + + TIMER0_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + 9 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC8 + 0x20 + + + TIMER0_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0xCC + 0x20 + + + TIMER0_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + write-only + + + + + 6 + 0x10 + CH%s_GAMMA_WR + Ledc ch%s gamma ram write register. + 0x100 + 0x20 + + + CH_GAMMA_DUTY_INC + Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s. + +1: Increase 0: Decrease. + 0 + 1 + read-write + + + CH_GAMMA_DUTY_CYCLE + Ledc ch%s gamma duty cycle of current ram write address.The duty will change every LEDC_CH%s_GAMMA_DUTY_CYCLE on channel %s. + 1 + 10 + read-write + + + CH_GAMMA_SCALE + Ledc ch%s gamma scale of current ram write address.This register is used to configure the changing step scale of duty on channel %s. + 11 + 10 + read-write + + + CH_GAMMA_DUTY_NUM + Ledc ch%s gamma duty num of current ram write address.This register is used to control the number of times the duty cycle will be changed. + 21 + 10 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_WR_ADDR + Ledc ch%s gamma ram write address register. + 0x104 + 0x20 + + + CH_GAMMA_WR_ADDR + Ledc ch%s gamma ram write address. + 0 + 4 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_RD_ADDR + Ledc ch%s gamma ram read address register. + 0x108 + 0x20 + + + CH_GAMMA_RD_ADDR + Ledc ch%s gamma ram read address. + 0 + 4 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_RD_DATA + Ledc ch%s gamma ram read data register. + 0x10C + 0x20 + + + CH_GAMMA_RD_DATA + Ledc ch%s gamma ram read data. + 0 + 31 + read-only + + + + + 6 + 0x4 + CH%s_GAMMA_CONF + Ledc ch%s gamma config register. + 0x180 + 0x20 + + + CH_GAMMA_ENTRY_NUM + Ledc ch%s gamma entry num. + 0 + 5 + read-write + + + CH_GAMMA_PAUSE + Ledc ch%s gamma pause, write 1 to pause. + 5 + 1 + write-only + + + CH_GAMMA_RESUME + Ledc ch%s gamma resume, write 1 to resume. + 6 + 1 + write-only + + + + + EVT_TASK_EN0 + Ledc event task enable bit register0. + 0x1A0 + 0x20 + + + EVT_DUTY_CHNG_END_CH0_EN + Ledc ch0 duty change end event enable register, write 1 to enable this event. + 0 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH1_EN + Ledc ch1 duty change end event enable register, write 1 to enable this event. + 1 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH2_EN + Ledc ch2 duty change end event enable register, write 1 to enable this event. + 2 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH3_EN + Ledc ch3 duty change end event enable register, write 1 to enable this event. + 3 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH4_EN + Ledc ch4 duty change end event enable register, write 1 to enable this event. + 4 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH5_EN + Ledc ch5 duty change end event enable register, write 1 to enable this event. + 5 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH0_EN + Ledc ch0 overflow count pulse event enable register, write 1 to enable this event. + 8 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH1_EN + Ledc ch1 overflow count pulse event enable register, write 1 to enable this event. + 9 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH2_EN + Ledc ch2 overflow count pulse event enable register, write 1 to enable this event. + 10 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH3_EN + Ledc ch3 overflow count pulse event enable register, write 1 to enable this event. + 11 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH4_EN + Ledc ch4 overflow count pulse event enable register, write 1 to enable this event. + 12 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH5_EN + Ledc ch5 overflow count pulse event enable register, write 1 to enable this event. + 13 + 1 + read-write + + + EVT_TIME_OVF_TIMER0_EN + Ledc timer0 overflow event enable register, write 1 to enable this event. + 16 + 1 + read-write + + + EVT_TIME_OVF_TIMER1_EN + Ledc timer1 overflow event enable register, write 1 to enable this event. + 17 + 1 + read-write + + + EVT_TIME_OVF_TIMER2_EN + Ledc timer2 overflow event enable register, write 1 to enable this event. + 18 + 1 + read-write + + + EVT_TIME_OVF_TIMER3_EN + Ledc timer3 overflow event enable register, write 1 to enable this event. + 19 + 1 + read-write + + + EVT_TIME0_CMP_EN + Ledc timer0 compare event enable register, write 1 to enable this event. + 20 + 1 + read-write + + + EVT_TIME1_CMP_EN + Ledc timer1 compare event enable register, write 1 to enable this event. + 21 + 1 + read-write + + + EVT_TIME2_CMP_EN + Ledc timer2 compare event enable register, write 1 to enable this event. + 22 + 1 + read-write + + + EVT_TIME3_CMP_EN + Ledc timer3 compare event enable register, write 1 to enable this event. + 23 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH0_EN + Ledc ch0 duty scale update task enable register, write 1 to enable this task. + 24 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH1_EN + Ledc ch1 duty scale update task enable register, write 1 to enable this task. + 25 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH2_EN + Ledc ch2 duty scale update task enable register, write 1 to enable this task. + 26 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH3_EN + Ledc ch3 duty scale update task enable register, write 1 to enable this task. + 27 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH4_EN + Ledc ch4 duty scale update task enable register, write 1 to enable this task. + 28 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH5_EN + Ledc ch5 duty scale update task enable register, write 1 to enable this task. + 29 + 1 + read-write + + + + + EVT_TASK_EN1 + Ledc event task enable bit register1. + 0x1A4 + 0x20 + + + TASK_TIMER0_RES_UPDATE_EN + Ledc timer0 res update task enable register, write 1 to enable this task. + 0 + 1 + read-write + + + TASK_TIMER1_RES_UPDATE_EN + Ledc timer1 res update task enable register, write 1 to enable this task. + 1 + 1 + read-write + + + TASK_TIMER2_RES_UPDATE_EN + Ledc timer2 res update task enable register, write 1 to enable this task. + 2 + 1 + read-write + + + TASK_TIMER3_RES_UPDATE_EN + Ledc timer3 res update task enable register, write 1 to enable this task. + 3 + 1 + read-write + + + TASK_TIMER0_CAP_EN + Ledc timer0 capture task enable register, write 1 to enable this task. + 4 + 1 + read-write + + + TASK_TIMER1_CAP_EN + Ledc timer1 capture task enable register, write 1 to enable this task. + 5 + 1 + read-write + + + TASK_TIMER2_CAP_EN + Ledc timer2 capture task enable register, write 1 to enable this task. + 6 + 1 + read-write + + + TASK_TIMER3_CAP_EN + Ledc timer3 capture task enable register, write 1 to enable this task. + 7 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH0_EN + Ledc ch0 signal out disable task enable register, write 1 to enable this task. + 8 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH1_EN + Ledc ch1 signal out disable task enable register, write 1 to enable this task. + 9 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH2_EN + Ledc ch2 signal out disable task enable register, write 1 to enable this task. + 10 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH3_EN + Ledc ch3 signal out disable task enable register, write 1 to enable this task. + 11 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH4_EN + Ledc ch4 signal out disable task enable register, write 1 to enable this task. + 12 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH5_EN + Ledc ch5 signal out disable task enable register, write 1 to enable this task. + 13 + 1 + read-write + + + TASK_OVF_CNT_RST_CH0_EN + Ledc ch0 overflow count reset task enable register, write 1 to enable this task. + 16 + 1 + read-write + + + TASK_OVF_CNT_RST_CH1_EN + Ledc ch1 overflow count reset task enable register, write 1 to enable this task. + 17 + 1 + read-write + + + TASK_OVF_CNT_RST_CH2_EN + Ledc ch2 overflow count reset task enable register, write 1 to enable this task. + 18 + 1 + read-write + + + TASK_OVF_CNT_RST_CH3_EN + Ledc ch3 overflow count reset task enable register, write 1 to enable this task. + 19 + 1 + read-write + + + TASK_OVF_CNT_RST_CH4_EN + Ledc ch4 overflow count reset task enable register, write 1 to enable this task. + 20 + 1 + read-write + + + TASK_OVF_CNT_RST_CH5_EN + Ledc ch5 overflow count reset task enable register, write 1 to enable this task. + 21 + 1 + read-write + + + TASK_TIMER0_RST_EN + Ledc timer0 reset task enable register, write 1 to enable this task. + 24 + 1 + read-write + + + TASK_TIMER1_RST_EN + Ledc timer1 reset task enable register, write 1 to enable this task. + 25 + 1 + read-write + + + TASK_TIMER2_RST_EN + Ledc timer2 reset task enable register, write 1 to enable this task. + 26 + 1 + read-write + + + TASK_TIMER3_RST_EN + Ledc timer3 reset task enable register, write 1 to enable this task. + 27 + 1 + read-write + + + TASK_TIMER0_PAUSE_RESUME_EN + Ledc timer0 pause resume task enable register, write 1 to enable this task. + 28 + 1 + read-write + + + TASK_TIMER1_PAUSE_RESUME_EN + Ledc timer1 pause resume task enable register, write 1 to enable this task. + 29 + 1 + read-write + + + TASK_TIMER2_PAUSE_RESUME_EN + Ledc timer2 pause resume task enable register, write 1 to enable this task. + 30 + 1 + read-write + + + TASK_TIMER3_PAUSE_RESUME_EN + Ledc timer3 pause resume task enable register, write 1 to enable this task. + 31 + 1 + read-write + + + + + EVT_TASK_EN2 + Ledc event task enable bit register2. + 0x1A8 + 0x20 + + + TASK_GAMMA_RESTART_CH0_EN + Ledc ch0 gamma restart task enable register, write 1 to enable this task. + 0 + 1 + read-write + + + TASK_GAMMA_RESTART_CH1_EN + Ledc ch1 gamma restart task enable register, write 1 to enable this task. + 1 + 1 + read-write + + + TASK_GAMMA_RESTART_CH2_EN + Ledc ch2 gamma restart task enable register, write 1 to enable this task. + 2 + 1 + read-write + + + TASK_GAMMA_RESTART_CH3_EN + Ledc ch3 gamma restart task enable register, write 1 to enable this task. + 3 + 1 + read-write + + + TASK_GAMMA_RESTART_CH4_EN + Ledc ch4 gamma restart task enable register, write 1 to enable this task. + 4 + 1 + read-write + + + TASK_GAMMA_RESTART_CH5_EN + Ledc ch5 gamma restart task enable register, write 1 to enable this task. + 5 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH0_EN + Ledc ch0 gamma pause task enable register, write 1 to enable this task. + 8 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH1_EN + Ledc ch1 gamma pause task enable register, write 1 to enable this task. + 9 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH2_EN + Ledc ch2 gamma pause task enable register, write 1 to enable this task. + 10 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH3_EN + Ledc ch3 gamma pause task enable register, write 1 to enable this task. + 11 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH4_EN + Ledc ch4 gamma pause task enable register, write 1 to enable this task. + 12 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH5_EN + Ledc ch5 gamma pause task enable register, write 1 to enable this task. + 13 + 1 + read-write + + + TASK_GAMMA_RESUME_CH0_EN + Ledc ch0 gamma resume task enable register, write 1 to enable this task. + 16 + 1 + read-write + + + TASK_GAMMA_RESUME_CH1_EN + Ledc ch1 gamma resume task enable register, write 1 to enable this task. + 17 + 1 + read-write + + + TASK_GAMMA_RESUME_CH2_EN + Ledc ch2 gamma resume task enable register, write 1 to enable this task. + 18 + 1 + read-write + + + TASK_GAMMA_RESUME_CH3_EN + Ledc ch3 gamma resume task enable register, write 1 to enable this task. + 19 + 1 + read-write + + + TASK_GAMMA_RESUME_CH4_EN + Ledc ch4 gamma resume task enable register, write 1 to enable this task. + 20 + 1 + read-write + + + TASK_GAMMA_RESUME_CH5_EN + Ledc ch5 gamma resume task enable register, write 1 to enable this task. + 21 + 1 + read-write + + + + + 4 + 0x4 + TIMER%s_CMP + Ledc timer%s compare value register. + 0x1B0 + 0x20 + + + TIMER_CMP + This register stores ledc timer%s compare value. + 0 + 20 + read-write + + + + + 4 + 0x4 + TIMER%s_CNT_CAP + Ledc timer%s count value capture register. + 0x1C0 + 0x20 + + + TIMER_CNT_CAP + This register stores ledc timer%s count value. + 0 + 20 + read-only + + + + + CONF + Global ledc configuration register + 0x1F0 + 0x20 + + + APB_CLK_SEL + This bit is used to select clock source for the 4 timers . + +2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + 0 + 2 + read-write + + + GAMMA_RAM_CLK_EN_CH0 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 2 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH1 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 3 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH2 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 4 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH3 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 5 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH4 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 6 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH5 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 7 + 1 + read-write + + + CLK_EN + This bit is used to control clock. + +1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 31 + 1 + read-write + + + + + DATE + Version control register + 0x1FC + 0x20 + 0x02111150 + + + LEDC_DATE + This is the version control register. + 0 + 28 + read-write + + + + + + + LP_PERI + LP_PERI Peripheral + LPPERI + 0x600B2800 + + 0x0 + 0x28 + registers + + + LP_PERI_TIMEOUT + 19 + + + + CLK_EN + need_des + 0x0 + 0x20 + 0x7F800000 + + + LP_TOUCH_CK_EN + need_des + 23 + 1 + read-write + + + RNG_CK_EN + need_des + 24 + 1 + read-write + + + OTP_DBG_CK_EN + need_des + 25 + 1 + read-write + + + LP_UART_CK_EN + need_des + 26 + 1 + read-write + + + LP_IO_CK_EN + need_des + 27 + 1 + read-write + + + LP_EXT_I2C_CK_EN + need_des + 28 + 1 + read-write + + + LP_ANA_I2C_CK_EN + need_des + 29 + 1 + read-write + + + EFUSE_CK_EN + need_des + 30 + 1 + read-write + + + LP_CPU_CK_EN + need_des + 31 + 1 + read-write + + + + + RESET_EN + need_des + 0x4 + 0x20 + + + BUS_RESET_EN + need_des + 23 + 1 + write-only + + + LP_TOUCH_RESET_EN + need_des + 24 + 1 + read-write + + + OTP_DBG_RESET_EN + need_des + 25 + 1 + read-write + + + LP_UART_RESET_EN + need_des + 26 + 1 + read-write + + + LP_IO_RESET_EN + need_des + 27 + 1 + read-write + + + LP_EXT_I2C_RESET_EN + need_des + 28 + 1 + read-write + + + LP_ANA_I2C_RESET_EN + need_des + 29 + 1 + read-write + + + EFUSE_RESET_EN + need_des + 30 + 1 + read-write + + + LP_CPU_RESET_EN + need_des + 31 + 1 + write-only + + + + + RNG_DATA + need_des + 0x8 + 0x20 + + + RND_DATA + need_des + 0 + 32 + read-only + + + + + CPU + need_des + 0xC + 0x20 + 0x80000000 + + + LPCORE_DBGM_UNAVALIABLE + need_des + 31 + 1 + read-write + + + + + BUS_TIMEOUT + need_des + 0x10 + 0x20 + 0xBFFFC000 + + + LP_PERI_TIMEOUT_THRES + need_des + 14 + 16 + read-write + + + LP_PERI_TIMEOUT_INT_CLEAR + need_des + 30 + 1 + write-only + + + LP_PERI_TIMEOUT_PROTECT_EN + need_des + 31 + 1 + read-write + + + + + BUS_TIMEOUT_ADDR + need_des + 0x14 + 0x20 + + + LP_PERI_TIMEOUT_ADDR + need_des + 0 + 32 + read-only + + + + + BUS_TIMEOUT_UID + need_des + 0x18 + 0x20 + + + LP_PERI_TIMEOUT_UID + need_des + 0 + 7 + read-only + + + + + MEM_CTRL + need_des + 0x1C + 0x20 + 0x80000000 + + + UART_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + UART_WAKEUP_FLAG + need_des + 1 + 1 + read-write + + + UART_WAKEUP_EN + need_des + 29 + 1 + read-write + + + UART_MEM_FORCE_PD + need_des + 30 + 1 + read-write + + + UART_MEM_FORCE_PU + need_des + 31 + 1 + read-write + + + + + INTERRUPT_SOURCE + need_des + 0x20 + 0x20 + + + LP_INTERRUPT_SOURCE + BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, lp_io_int + 0 + 6 + read-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02206130 + + + LPPERI_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_ANA + LP_ANA Peripheral + LP_ANA + 0x600B2C00 + + 0x0 + 0x34 + registers + + + + BOD_MODE0_CNTL + need_des + 0x0 + 0x20 + 0x0FFC0100 + + + BOD_MODE0_CLOSE_FLASH_ENA + need_des + 6 + 1 + read-write + + + BOD_MODE0_PD_RF_ENA + need_des + 7 + 1 + read-write + + + BOD_MODE0_INTR_WAIT + need_des + 8 + 10 + read-write + + + BOD_MODE0_RESET_WAIT + need_des + 18 + 10 + read-write + + + BOD_MODE0_CNT_CLR + need_des + 28 + 1 + read-write + + + BOD_MODE0_INTR_ENA + need_des + 29 + 1 + read-write + + + BOD_MODE0_RESET_SEL + need_des + 30 + 1 + read-write + + + BOD_MODE0_RESET_ENA + need_des + 31 + 1 + read-write + + + + + BOD_MODE1_CNTL + need_des + 0x4 + 0x20 + + + BOD_MODE1_RESET_ENA + need_des + 31 + 1 + read-write + + + + + CK_GLITCH_CNTL + need_des + 0x8 + 0x20 + + + CK_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + FIB_ENABLE + need_des + 0xC + 0x20 + 0xFFFFFFFF + + + ANA_FIB_ENA + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x10 + 0x20 + + + BOD_MODE0_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x14 + 0x20 + + + BOD_MODE0_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x18 + 0x20 + + + BOD_MODE0_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x1C + 0x20 + + + BOD_MODE0_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x20 + 0x20 + + + BOD_MODE0_LP_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_INT_ST + need_des + 0x24 + 0x20 + + + BOD_MODE0_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x28 + 0x20 + + + BOD_MODE0_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x2C + 0x20 + + + BOD_MODE0_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02202260 + + + LP_ANA_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_AON + LP_AON Peripheral + LP_AON + 0x600B1000 + + 0x0 + 0x5C + registers + + + + STORE0 + need_des + 0x0 + 0x20 + + + LP_AON_STORE0 + need_des + 0 + 32 + read-write + + + + + STORE1 + need_des + 0x4 + 0x20 + + + LP_AON_STORE1 + need_des + 0 + 32 + read-write + + + + + STORE2 + need_des + 0x8 + 0x20 + + + LP_AON_STORE2 + need_des + 0 + 32 + read-write + + + + + STORE3 + need_des + 0xC + 0x20 + + + LP_AON_STORE3 + need_des + 0 + 32 + read-write + + + + + STORE4 + need_des + 0x10 + 0x20 + + + LP_AON_STORE4 + need_des + 0 + 32 + read-write + + + + + STORE5 + need_des + 0x14 + 0x20 + + + LP_AON_STORE5 + need_des + 0 + 32 + read-write + + + + + STORE6 + need_des + 0x18 + 0x20 + + + LP_AON_STORE6 + need_des + 0 + 32 + read-write + + + + + STORE7 + need_des + 0x1C + 0x20 + + + LP_AON_STORE7 + need_des + 0 + 32 + read-write + + + + + STORE8 + need_des + 0x20 + 0x20 + + + LP_AON_STORE8 + need_des + 0 + 32 + read-write + + + + + STORE9 + need_des + 0x24 + 0x20 + + + LP_AON_STORE9 + need_des + 0 + 32 + read-write + + + + + GPIO_MUX + need_des + 0x28 + 0x20 + + + SEL + need_des + 0 + 8 + read-write + + + + + GPIO_HOLD0 + need_des + 0x2C + 0x20 + + + GPIO_HOLD0 + need_des + 0 + 32 + read-write + + + + + GPIO_HOLD1 + need_des + 0x30 + 0x20 + + + GPIO_HOLD1 + need_des + 0 + 32 + read-write + + + + + SYS_CFG + need_des + 0x34 + 0x20 + + + FORCE_DOWNLOAD_BOOT + need_des + 30 + 1 + read-write + + + HPSYS_SW_RESET + need_des + 31 + 1 + write-only + + + + + CPUCORE0_CFG + need_des + 0x38 + 0x20 + 0x40000000 + + + CPU_CORE0_SW_STALL + need_des + 0 + 8 + read-write + + + CPU_CORE0_SW_RESET + need_des + 28 + 1 + write-only + + + CPU_CORE0_OCD_HALT_ON_RESET + need_des + 29 + 1 + read-write + + + CPU_CORE0_STAT_VECTOR_SEL + need_des + 30 + 1 + read-write + + + CPU_CORE0_DRESET_MASK + need_des + 31 + 1 + read-write + + + + + IO_MUX + need_des + 0x3C + 0x20 + + + RESET_DISABLE + need_des + 31 + 1 + read-write + + + + + EXT_WAKEUP_CNTL + need_des + 0x40 + 0x20 + + + EXT_WAKEUP_STATUS + need_des + 0 + 8 + read-only + + + EXT_WAKEUP_STATUS_CLR + need_des + 14 + 1 + write-only + + + EXT_WAKEUP_SEL + need_des + 15 + 8 + read-write + + + EXT_WAKEUP_LV + need_des + 23 + 8 + read-write + + + EXT_WAKEUP_FILTER + need_des + 31 + 1 + read-write + + + + + USB + need_des + 0x44 + 0x20 + + + RESET_DISABLE + need_des + 31 + 1 + read-write + + + + + LPBUS + need_des + 0x48 + 0x20 + 0xB0200000 + + + FAST_MEM_WPULSE + This field controls fast memory WPULSE parameter. + 16 + 3 + read-write + + + FAST_MEM_WA + This field controls fast memory WA parameter. + 19 + 3 + read-write + + + FAST_MEM_RA + This field controls fast memory RA parameter. + 22 + 2 + read-write + + + FAST_MEM_MUX_FSM_IDLE + need_des + 28 + 1 + read-only + + + FAST_MEM_MUX_SEL_STATUS + need_des + 29 + 1 + read-only + + + FAST_MEM_MUX_SEL_UPDATE + need_des + 30 + 1 + write-only + + + FAST_MEM_MUX_SEL + need_des + 31 + 1 + read-write + + + + + SDIO_ACTIVE + need_des + 0x4C + 0x20 + 0x02800000 + + + SDIO_ACT_DNUM + need_des + 22 + 10 + read-write + + + + + LPCORE + need_des + 0x50 + 0x20 + + + ETM_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + ETM_WAKEUP_FLAG + need_des + 1 + 1 + read-write + + + DISABLE + need_des + 31 + 1 + read-write + + + + + SAR_CCT + need_des + 0x54 + 0x20 + + + SAR2_PWDET_CCT + need_des + 29 + 3 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02205280 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_APM + Low-power Access Permission Management Controller + LP_APM + 0x600B3800 + + 0x0 + 0x64 + registers + + + LP_APM_M0 + 20 + + + LP_APM_M1 + 21 + + + LP_APM0 + 39 + + + + REGION_FILTER_EN + Region filter enable register + 0x0 + 0x20 + 0x00000001 + + + REGION_FILTER_EN + Region filter enable + 0 + 4 + read-write + + + + + REGION0_ADDR_START + Region address register + 0x4 + 0x20 + + + REGION0_ADDR_START + Start address of region0 + 0 + 32 + read-write + + + + + REGION0_ADDR_END + Region address register + 0x8 + 0x20 + 0xFFFFFFFF + + + REGION0_ADDR_END + End address of region0 + 0 + 32 + read-write + + + + + REGION0_PMS_ATTR + Region access authority attribute register + 0xC + 0x20 + + + REGION0_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION0_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION0_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION0_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION0_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION0_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION0_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION0_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION0_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION1_ADDR_START + Region address register + 0x10 + 0x20 + + + REGION1_ADDR_START + Start address of region1 + 0 + 32 + read-write + + + + + REGION1_ADDR_END + Region address register + 0x14 + 0x20 + 0xFFFFFFFF + + + REGION1_ADDR_END + End address of region1 + 0 + 32 + read-write + + + + + REGION1_PMS_ATTR + Region access authority attribute register + 0x18 + 0x20 + + + REGION1_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION1_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION1_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION1_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION1_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION1_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION1_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION1_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION1_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION2_ADDR_START + Region address register + 0x1C + 0x20 + + + REGION2_ADDR_START + Start address of region2 + 0 + 32 + read-write + + + + + REGION2_ADDR_END + Region address register + 0x20 + 0x20 + 0xFFFFFFFF + + + REGION2_ADDR_END + End address of region2 + 0 + 32 + read-write + + + + + REGION2_PMS_ATTR + Region access authority attribute register + 0x24 + 0x20 + + + REGION2_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION2_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION2_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION2_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION2_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION2_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION2_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION2_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION2_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION3_ADDR_START + Region address register + 0x28 + 0x20 + + + REGION3_ADDR_START + Start address of region3 + 0 + 32 + read-write + + + + + REGION3_ADDR_END + Region address register + 0x2C + 0x20 + 0xFFFFFFFF + + + REGION3_ADDR_END + End address of region3 + 0 + 32 + read-write + + + + + REGION3_PMS_ATTR + Region access authority attribute register + 0x30 + 0x20 + + + REGION3_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION3_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION3_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION3_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION3_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION3_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION3_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION3_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION3_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + FUNC_CTRL + PMS function control register + 0xC4 + 0x20 + 0x00000003 + + + M0_PMS_FUNC_EN + PMS M0 function enable + 0 + 1 + read-write + + + M1_PMS_FUNC_EN + PMS M1 function enable + 1 + 1 + read-write + + + + + M0_STATUS + M0 status register + 0xC8 + 0x20 + + + M0_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M0_STATUS_CLR + M0 status clear register + 0xCC + 0x20 + + + M0_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M0_EXCEPTION_INFO0 + M0 exception_info0 register + 0xD0 + 0x20 + + + M0_EXCEPTION_REGION + Exception region + 0 + 4 + read-only + + + M0_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M0_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M0_EXCEPTION_INFO1 + M0 exception_info1 register + 0xD4 + 0x20 + + + M0_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M1_STATUS + M1 status register + 0xD8 + 0x20 + + + M1_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M1_STATUS_CLR + M1 status clear register + 0xDC + 0x20 + + + M1_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M1_EXCEPTION_INFO0 + M1 exception_info0 register + 0xE0 + 0x20 + + + M1_EXCEPTION_REGION + Exception region + 0 + 4 + read-only + + + M1_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M1_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M1_EXCEPTION_INFO1 + M1 exception_info1 register + 0xE4 + 0x20 + + + M1_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + INT_EN + APM interrupt enable register + 0xE8 + 0x20 + + + M0_APM_INT_EN + APM M0 interrupt enable + 0 + 1 + read-write + + + M1_APM_INT_EN + APM M1 interrupt enable + 1 + 1 + read-write + + + + + CLOCK_GATE + clock gating register + 0xEC + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0xFC + 0x20 + 0x02205240 + + + DATE + reg_date + 0 + 28 + read-write + + + + + + + LP_APM0 + LP_APM0 Peripheral + LP_APM0 + 0x60099800 + + 0x0 + 0x54 + registers + + + + REGION_FILTER_EN + Region filter enable register + 0x0 + 0x20 + 0x00000001 + + + REGION_FILTER_EN + Region filter enable + 0 + 4 + read-write + + + + + REGION0_ADDR_START + Region address register + 0x4 + 0x20 + + + REGION0_ADDR_START + Start address of region0 + 0 + 32 + read-write + + + + + REGION0_ADDR_END + Region address register + 0x8 + 0x20 + 0xFFFFFFFF + + + REGION0_ADDR_END + End address of region0 + 0 + 32 + read-write + + + + + REGION0_PMS_ATTR + Region access authority attribute register + 0xC + 0x20 + + + REGION0_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION0_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION0_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION0_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION0_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION0_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION0_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION0_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION0_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION1_ADDR_START + Region address register + 0x10 + 0x20 + + + REGION1_ADDR_START + Start address of region1 + 0 + 32 + read-write + + + + + REGION1_ADDR_END + Region address register + 0x14 + 0x20 + 0xFFFFFFFF + + + REGION1_ADDR_END + End address of region1 + 0 + 32 + read-write + + + + + REGION1_PMS_ATTR + Region access authority attribute register + 0x18 + 0x20 + + + REGION1_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION1_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION1_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION1_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION1_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION1_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION1_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION1_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION1_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION2_ADDR_START + Region address register + 0x1C + 0x20 + + + REGION2_ADDR_START + Start address of region2 + 0 + 32 + read-write + + + + + REGION2_ADDR_END + Region address register + 0x20 + 0x20 + 0xFFFFFFFF + + + REGION2_ADDR_END + End address of region2 + 0 + 32 + read-write + + + + + REGION2_PMS_ATTR + Region access authority attribute register + 0x24 + 0x20 + + + REGION2_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION2_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION2_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION2_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION2_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION2_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION2_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION2_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION2_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION3_ADDR_START + Region address register + 0x28 + 0x20 + + + REGION3_ADDR_START + Start address of region3 + 0 + 32 + read-write + + + + + REGION3_ADDR_END + Region address register + 0x2C + 0x20 + 0xFFFFFFFF + + + REGION3_ADDR_END + End address of region3 + 0 + 32 + read-write + + + + + REGION3_PMS_ATTR + Region access authority attribute register + 0x30 + 0x20 + + + REGION3_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION3_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION3_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION3_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION3_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION3_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION3_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION3_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION3_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + FUNC_CTRL + PMS function control register + 0xC4 + 0x20 + 0x00000001 + + + M0_PMS_FUNC_EN + PMS M0 function enable + 0 + 1 + read-write + + + + + M0_STATUS + M0 status register + 0xC8 + 0x20 + + + M0_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M0_STATUS_CLR + M0 status clear register + 0xCC + 0x20 + + + M0_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M0_EXCEPTION_INFO0 + M0 exception_info0 register + 0xD0 + 0x20 + + + M0_EXCEPTION_REGION + Exception region + 0 + 4 + read-only + + + M0_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M0_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M0_EXCEPTION_INFO1 + M0 exception_info1 register + 0xD4 + 0x20 + + + M0_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + INT_EN + APM interrupt enable register + 0xD8 + 0x20 + + + M0_APM_INT_EN + APM M0 interrupt enable + 0 + 1 + read-write + + + + + CLOCK_GATE + clock gating register + 0xDC + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0x7FC + 0x20 + 0x02205240 + + + DATE + reg_date + 0 + 28 + read-write + + + + + + + LP_CLKRST + LP_CLKRST Peripheral + LP_CLKRST + 0x600B0400 + + 0x0 + 0x34 + registers + + + + LP_CLK_CONF + need_des + 0x0 + 0x20 + 0x00000004 + + + SLOW_CLK_SEL + need_des + 0 + 2 + read-write + + + FAST_CLK_SEL + need_des + 2 + 1 + read-write + + + LP_PERI_DIV_NUM + need_des + 3 + 8 + read-write + + + + + LP_CLK_PO_EN + need_des + 0x4 + 0x20 + 0x000007FF + + + AON_SLOW_OEN + need_des + 0 + 1 + read-write + + + AON_FAST_OEN + need_des + 1 + 1 + read-write + + + SOSC_OEN + need_des + 2 + 1 + read-write + + + FOSC_OEN + need_des + 3 + 1 + read-write + + + OSC32K_OEN + need_des + 4 + 1 + read-write + + + XTAL32K_OEN + need_des + 5 + 1 + read-write + + + CORE_EFUSE_OEN + need_des + 6 + 1 + read-write + + + SLOW_OEN + need_des + 7 + 1 + read-write + + + FAST_OEN + need_des + 8 + 1 + read-write + + + RNG_OEN + need_des + 9 + 1 + read-write + + + LPBUS_OEN + need_des + 10 + 1 + read-write + + + + + LP_CLK_EN + need_des + 0x8 + 0x20 + + + FAST_ORI_GATE + need_des + 31 + 1 + read-write + + + + + LP_RST_EN + need_des + 0xC + 0x20 + + + AON_EFUSE_CORE_RESET_EN + need_des + 28 + 1 + read-write + + + LP_TIMER_RESET_EN + need_des + 29 + 1 + read-write + + + WDT_RESET_EN + need_des + 30 + 1 + read-write + + + ANA_PERI_RESET_EN + need_des + 31 + 1 + read-write + + + + + RESET_CAUSE + need_des + 0x10 + 0x20 + 0x00000020 + + + RESET_CAUSE + need_des + 0 + 5 + read-only + + + CORE0_RESET_FLAG + need_des + 5 + 1 + read-only + + + CORE0_RESET_CAUSE_CLR + need_des + 29 + 1 + write-only + + + CORE0_RESET_FLAG_SET + need_des + 30 + 1 + write-only + + + CORE0_RESET_FLAG_CLR + need_des + 31 + 1 + write-only + + + + + CPU_RESET + need_des + 0x14 + 0x20 + 0x04400000 + + + RTC_WDT_CPU_RESET_LENGTH + need_des + 22 + 3 + read-write + + + RTC_WDT_CPU_RESET_EN + need_des + 25 + 1 + read-write + + + CPU_STALL_WAIT + need_des + 26 + 5 + read-write + + + CPU_STALL_EN + need_des + 31 + 1 + read-write + + + + + FOSC_CNTL + need_des + 0x18 + 0x20 + 0x2B000000 + + + FOSC_DFREQ + need_des + 22 + 10 + read-write + + + + + RC32K_CNTL + need_des + 0x1C + 0x20 + 0x2B000000 + + + RC32K_DFREQ + need_des + 22 + 10 + read-write + + + + + CLK_TO_HP + need_des + 0x20 + 0x20 + 0xF0000000 + + + ICG_HP_XTAL32K + need_des + 28 + 1 + read-write + + + ICG_HP_SOSC + need_des + 29 + 1 + read-write + + + ICG_HP_OSC32K + need_des + 30 + 1 + read-write + + + ICG_HP_FOSC + need_des + 31 + 1 + read-write + + + + + LPMEM_FORCE + need_des + 0x24 + 0x20 + + + LPMEM_CLK_FORCE_ON + need_des + 31 + 1 + read-write + + + + + LPPERI + need_des + 0x28 + 0x20 + + + LP_I2C_CLK_SEL + need_des + 30 + 1 + read-write + + + LP_UART_CLK_SEL + need_des + 31 + 1 + read-write + + + + + XTAL32K + need_des + 0x2C + 0x20 + 0x66C00000 + + + DRES_XTAL32K + need_des + 22 + 3 + read-write + + + DGM_XTAL32K + need_des + 25 + 3 + read-write + + + DBUF_XTAL32K + need_des + 28 + 1 + read-write + + + DAC_XTAL32K + need_des + 29 + 3 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02206090 + + + CLKRST_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_I2C0 + Low-power I2C (Inter-Integrated Circuit) Controller 0 + LP_I2C0 + 0x600B1800 + + 0x0 + 0x88 + registers + + + LP_I2C + 17 + + + + I2C_SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + I2C_SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + I2C_SDA_FORCE_OUT + 1: direct output, 0: open drain output. + 0 + 1 + read-write + + + I2C_SCL_FORCE_OUT + 1: direct output, 0: open drain output. + 1 + 1 + read-write + + + I2C_SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + I2C_RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + I2C_TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + I2C_TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit, +0: send data from the most significant bit. + 6 + 1 + read-write + + + I2C_RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit, +0: receive data from the most significant bit. + 7 + 1 + read-write + + + I2C_CLK_EN + Reserved + 8 + 1 + read-write + + + I2C_ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + I2C_FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + I2C_CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + + + I2C_SR + Describe I2C work status. + 0x8 + 0x20 + + + I2C_RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + I2C_ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + I2C_BUS_BUSY + 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + I2C_RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 5 + read-only + + + I2C_TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 5 + read-only + + + I2C_SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK + 24 + 3 + read-only + + + I2C_SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + 28 + 3 + read-only + + + + + I2C_TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + I2C_TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + I2C_TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + I2C_FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + I2C_RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 4 + read-only + + + I2C_RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 4 + read-only + + + I2C_TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 4 + read-only + + + I2C_TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 4 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x00004046 + + + RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 4 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 4 + read-write + + + NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + I2C_DATA + Rx FIFO read data. + 0x1C + 0x20 + + + I2C_FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-only + + + + + I2C_INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + I2C_RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + I2C_TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + I2C_RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + I2C_END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + I2C_BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + I2C_ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + I2C_MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + I2C_TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + I2C_TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + I2C_TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + I2C_NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + I2C_TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + I2C_RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + I2C_SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + I2C_SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + I2C_DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + I2C_INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + I2C_RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + I2C_TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + I2C_RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + I2C_END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + I2C_BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + I2C_ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + I2C_MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + I2C_TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + I2C_TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + I2C_TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + I2C_NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + I2C_TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + I2C_RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + I2C_SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + I2C_SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + I2C_DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + + + I2C_INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + I2C_RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + I2C_TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + I2C_RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + I2C_END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + I2C_BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + I2C_ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + I2C_MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + I2C_TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + I2C_TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + I2C_TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + I2C_NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + I2C_TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + I2C_RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + I2C_SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + I2C_SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + I2C_DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + + + I2C_INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + I2C_RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + I2C_TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + I2C_RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + I2C_END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + I2C_BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + I2C_ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + I2C_MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + I2C_TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + I2C_TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + I2C_TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + I2C_NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + I2C_TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + I2C_RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + I2C_SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + I2C_SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + I2C_DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + I2C_SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + I2C_SCL_HIGH_PERIOD + This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + I2C_SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + I2C_SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + I2C_SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + I2C_SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + I2C_SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + I2C_SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + I2C_CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + I2C_SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + I2C_SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + I2C_SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + I2C_SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + I2C_SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + I2C_COMD0 + I2C command register 0 + 0x58 + 0x20 + + + I2C_COMMAND0 + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND0_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + I2C_COMD1 + I2C command register 1 + 0x5C + 0x20 + + + I2C_COMMAND1 + This is the content of command 1. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND1_DONE + When command 1 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + I2C_COMD2 + I2C command register 2 + 0x60 + 0x20 + + + I2C_COMMAND2 + This is the content of command 2. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND2_DONE + When command 2 is done in I2C Master mode, this bit changes to high +Level. + 31 + 1 + read-write + + + + + I2C_COMD3 + I2C command register 3 + 0x64 + 0x20 + + + I2C_COMMAND3 + This is the content of command 3. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND3_DONE + When command 3 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + I2C_COMD4 + I2C command register 4 + 0x68 + 0x20 + + + I2C_COMMAND4 + This is the content of command 4. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND4_DONE + When command 4 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + I2C_COMD5 + I2C command register 5 + 0x6C + 0x20 + + + I2C_COMMAND5 + This is the content of command 5. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND5_DONE + When command 5 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + I2C_COMD6 + I2C command register 6 + 0x70 + 0x20 + + + I2C_COMMAND6 + This is the content of command 6. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND6_DONE + When command 6 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + I2C_COMD7 + I2C command register 7 + 0x74 + 0x20 + + + I2C_COMMAND7 + This is the content of command 7. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND7_DONE + When command 7 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + I2C_SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + I2C_SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + I2C_SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + I2C_SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + I2C_SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + I2C_SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + I2C_SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + I2C_SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + I2C_SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + I2C_DATE + Version register + 0xF8 + 0x20 + 0x02201143 + + + I2C_DATE + This is the the version register. + 0 + 32 + read-write + + + + + I2C_TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + I2C_TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + I2C_RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + I2C_RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + LP_I2C_ANA_MST + LP_I2C_ANA_MST Peripheral + LP_I2C_ANA_MST + 0x600B2400 + + 0x0 + 0x1C + registers + + + + I2C0_CTRL + need_des + 0x0 + 0x20 + + + LP_I2C_ANA_MAST_I2C0_CTRL + need_des + 0 + 25 + read-write + + + LP_I2C_ANA_MAST_I2C0_BUSY + need_des + 25 + 1 + read-only + + + + + I2C0_CONF + need_des + 0x4 + 0x20 + 0x07000000 + + + LP_I2C_ANA_MAST_I2C0_CONF + need_des + 0 + 24 + read-write + + + LP_I2C_ANA_MAST_I2C0_STATUS + reserved + 24 + 8 + read-only + + + + + I2C0_DATA + need_des + 0x8 + 0x20 + 0x00000900 + + + LP_I2C_ANA_MAST_I2C0_RDATA + need_des + 0 + 8 + read-only + + + LP_I2C_ANA_MAST_I2C0_CLK_SEL + need_des + 8 + 3 + read-write + + + LP_I2C_ANA_MAST_I2C_MST_SEL + need des + 11 + 1 + read-write + + + + + ANA_CONF1 + need_des + 0xC + 0x20 + + + LP_I2C_ANA_MAST_ANA_CONF1 + need_des + 0 + 24 + read-write + + + + + NOUSE + need_des + 0x10 + 0x20 + + + LP_I2C_ANA_MAST_I2C_MST_NOUSE + need_des + 0 + 32 + read-write + + + + + DEVICE_EN + need_des + 0x14 + 0x20 + + + LP_I2C_ANA_MAST_I2C_DEVICE_EN + need_des + 0 + 12 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02007301 + + + LP_I2C_ANA_MAST_I2C_MAT_DATE + need_des + 0 + 28 + read-write + + + LP_I2C_ANA_MAST_I2C_MAT_CLK_EN + need_des + 28 + 1 + read-write + + + + + + + LP_IO + LP_IO Peripheral + LP_IO + 0x600B2000 + + 0x0 + 0x7C + registers + + + + OUT_DATA + need des + 0x0 + 0x20 + + + LP_GPIO_OUT_DATA + set lp gpio output data + 0 + 8 + read-write + + + + + OUT_DATA_W1TS + need des + 0x4 + 0x20 + + + LP_GPIO_OUT_DATA_W1TS + set one time output data + 0 + 8 + write-only + + + + + OUT_DATA_W1TC + need des + 0x8 + 0x20 + + + LP_GPIO_OUT_DATA_W1TC + clear one time output data + 0 + 8 + write-only + + + + + OUT_ENABLE + need des + 0xC + 0x20 + + + LP_GPIO_ENABLE + set lp gpio output data + 0 + 8 + read-write + + + + + OUT_ENABLE_W1TS + need des + 0x10 + 0x20 + + + LP_GPIO_ENABLE_W1TS + set one time output data + 0 + 8 + write-only + + + + + OUT_ENABLE_W1TC + need des + 0x14 + 0x20 + + + LP_GPIO_ENABLE_W1TC + clear one time output data + 0 + 8 + write-only + + + + + STATUS + need des + 0x18 + 0x20 + + + LP_GPIO_STATUS_INTERRUPT + set lp gpio output data + 0 + 8 + read-write + + + + + STATUS_W1TS + need des + 0x1C + 0x20 + + + LP_GPIO_STATUS_W1TS + set one time output data + 0 + 8 + write-only + + + + + STATUS_W1TC + need des + 0x20 + 0x20 + + + LP_GPIO_STATUS_W1TC + clear one time output data + 0 + 8 + write-only + + + + + IN + need des + 0x24 + 0x20 + + + LP_GPIO_IN_DATA_NEXT + need des + 0 + 8 + read-only + + + + + PIN0 + need des + 0x28 + 0x20 + + + LP_GPIO0_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO0_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO0_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO0_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO0_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO0_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN1 + need des + 0x2C + 0x20 + + + LP_GPIO1_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO1_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO1_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO1_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO1_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO1_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN2 + need des + 0x30 + 0x20 + + + LP_GPIO2_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO2_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO2_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO2_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO2_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO2_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN3 + need des + 0x34 + 0x20 + + + LP_GPIO3_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO3_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO3_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO3_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO3_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO3_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN4 + need des + 0x38 + 0x20 + + + LP_GPIO4_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO4_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO4_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO4_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO4_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO4_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN5 + need des + 0x3C + 0x20 + + + LP_GPIO5_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO5_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO5_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO5_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO5_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO5_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN6 + need des + 0x40 + 0x20 + + + LP_GPIO6_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO6_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO6_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO6_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO6_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO6_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN7 + need des + 0x44 + 0x20 + + + LP_GPIO7_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO7_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO7_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO7_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO7_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO7_FILTER_EN + need des + 11 + 1 + read-write + + + + + GPIO0 + need des + 0x48 + 0x20 + + + LP_GPIO0_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO0_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO0_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO0_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO0_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO0_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO0_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO0_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO0_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO0_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO0_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO1 + need des + 0x4C + 0x20 + + + LP_GPIO1_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO1_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO1_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO1_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO1_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO1_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO1_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO1_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO1_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO1_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO1_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO2 + need des + 0x50 + 0x20 + + + LP_GPIO2_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO2_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO2_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO2_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO2_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO2_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO2_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO2_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO2_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO2_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO2_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO3 + need des + 0x54 + 0x20 + + + LP_GPIO3_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO3_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO3_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO3_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO3_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO3_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO3_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO3_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO3_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO3_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO3_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO4 + need des + 0x58 + 0x20 + + + LP_GPIO4_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO4_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO4_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO4_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO4_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO4_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO4_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO4_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO4_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO4_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO4_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO5 + need des + 0x5C + 0x20 + + + LP_GPIO5_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO5_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO5_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO5_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO5_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO5_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO5_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO5_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO5_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO5_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO5_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO6 + need des + 0x60 + 0x20 + + + LP_GPIO6_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO6_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO6_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO6_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO6_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO6_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO6_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO6_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO6_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO6_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO6_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO7 + need des + 0x64 + 0x20 + + + LP_GPIO7_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO7_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO7_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO7_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO7_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO7_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO7_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO7_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO7_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO7_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO7_MCU_SEL + need des + 12 + 3 + read-write + + + + + STATUS_INTERRUPT + need des + 0x68 + 0x20 + + + LP_GPIO_STATUS_INTERRUPT_NEXT + need des + 0 + 8 + read-only + + + + + DEBUG_SEL0 + need des + 0x6C + 0x20 + + + LP_DEBUG_SEL0 + need des + 0 + 7 + read-write + + + LP_DEBUG_SEL1 + need des + 7 + 7 + read-write + + + LP_DEBUG_SEL2 + need des + 14 + 7 + read-write + + + LP_DEBUG_SEL3 + need des + 21 + 7 + read-write + + + + + DEBUG_SEL1 + need des + 0x70 + 0x20 + + + LP_DEBUG_SEL4 + need des + 0 + 7 + read-write + + + + + LPI2C + need des + 0x74 + 0x20 + 0xC0000000 + + + LP_I2C_SDA_IE + need des + 30 + 1 + read-write + + + LP_I2C_SCL_IE + need des + 31 + 1 + read-write + + + + + DATE + need des + 0x3FC + 0x20 + 0x02202100 + + + LP_IO_DATE + need des + 0 + 31 + read-write + + + CLK_EN + need des + 31 + 1 + read-write + + + + + + + LP_TEE + Low-power Trusted Execution Environment + LP_TEE + 0x600B3400 + + 0x0 + 0x10 + registers + + + + M0_MODE_CTRL + Tee mode control register + 0x0 + 0x20 + 0x00000003 + + + M0_MODE + M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + CLOCK_GATE + Clock gating register + 0x4 + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + FORCE_ACC_HP + need_des + 0x90 + 0x20 + + + LP_AON_FORCE_ACC_HPMEM_EN + need_des + 0 + 1 + read-write + + + + + DATE + Version register + 0xFC + 0x20 + 0x02205270 + + + DATE + reg_tee_date + 0 + 28 + read-write + + + + + + + LP_TIMER + Low-power Timer + LP_TIMER + 0x600B0C00 + + 0x0 + 0x4C + registers + + + LP_RTC_TIMER + 15 + + + + TAR0_LOW + need_des + 0x0 + 0x20 + + + MAIN_TIMER_TAR_LOW0 + need_des + 0 + 32 + read-write + + + + + TAR0_HIGH + need_des + 0x4 + 0x20 + + + MAIN_TIMER_TAR_HIGH0 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN0 + need_des + 31 + 1 + write-only + + + + + TAR1_LOW + need_des + 0x8 + 0x20 + + + MAIN_TIMER_TAR_LOW1 + need_des + 0 + 32 + read-write + + + + + TAR1_HIGH + need_des + 0xC + 0x20 + + + MAIN_TIMER_TAR_HIGH1 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN1 + need_des + 31 + 1 + write-only + + + + + UPDATE + need_des + 0x10 + 0x20 + + + MAIN_TIMER_UPDATE + need_des + 28 + 1 + write-only + + + MAIN_TIMER_XTAL_OFF + need_des + 29 + 1 + read-write + + + MAIN_TIMER_SYS_STALL + need_des + 30 + 1 + read-write + + + MAIN_TIMER_SYS_RST + need_des + 31 + 1 + read-write + + + + + MAIN_BUF0_LOW + need_des + 0x14 + 0x20 + + + MAIN_TIMER_BUF0_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF0_HIGH + need_des + 0x18 + 0x20 + + + MAIN_TIMER_BUF0_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_BUF1_LOW + need_des + 0x1C + 0x20 + + + MAIN_TIMER_BUF1_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF1_HIGH + need_des + 0x20 + 0x20 + + + MAIN_TIMER_BUF1_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_OVERFLOW + need_des + 0x24 + 0x20 + + + MAIN_TIMER_ALARM_LOAD + need_des + 31 + 1 + write-only + + + + + INT_RAW + need_des + 0x28 + 0x20 + + + OVERFLOW_RAW + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x2C + 0x20 + + + OVERFLOW_ST + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x30 + 0x20 + + + OVERFLOW_ENA + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x34 + 0x20 + + + OVERFLOW_CLR + need_des + 30 + 1 + write-only + + + SOC_WAKEUP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x38 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_RAW + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_INT_ST + need_des + 0x3C + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ST + need_des + 30 + 1 + read-only + + + MAIN_TIMER_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x40 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ENA + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x44 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_CLR + need_des + 30 + 1 + write-only + + + MAIN_TIMER_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02111150 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_UART + Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + LP_UART + 0x600B1400 + + 0x0 + 0x84 + registers + + + LP_UART + 16 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-write + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-write + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-write + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-write + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-write + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-write + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-write + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-write + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-write + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-write + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-write + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 3 + 5 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 19 + 5 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0 + Configuration register 0 + 0x20 + 0x20 + 0x0010001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 3 + 5 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 11 + 5 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 3 + 5 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001420F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 13 + 5 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0 + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00006000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 3 + 5 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 11 + 5 + read-write + + + + + TXBRK_CONF + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF + RS485 mode configuration + 0x4C + 0x20 + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + + + AT_CMD_PRECNT + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 3 + 5 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 12 + 5 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 3 + 5 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 12 + 5 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03701000 + + + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 + read-write + + + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. + 12 + 8 + read-write + + + SCLK_SEL + UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 + 1 + read-write + + + RST_CORE + Write 1 then write 0 to this bit to reset UART Tx/Rx. + 23 + 1 + read-write + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02201260 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + LP_WDT + Low-power Watchdog Timer + LP_WDT + 0x600B1C00 + + 0x0 + 0x38 + registers + + + LP_WDT + 18 + + + + WDTCONFIG0 + need_des + 0x0 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + need_des + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + need_des + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + need_des + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + need_des + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + need_des + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + need_des + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + need_des + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + need_des + 16 + 3 + read-write + + + WDT_STG3 + need_des + 19 + 3 + read-write + + + WDT_STG2 + need_des + 22 + 3 + read-write + + + WDT_STG1 + need_des + 25 + 3 + read-write + + + WDT_STG0 + need_des + 28 + 3 + read-write + + + WDT_EN + need_des + 31 + 1 + read-write + + + + + CONFIG1 + need_des + 0x4 + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG2 + need_des + 0x8 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG3 + need_des + 0xC + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG4 + need_des + 0x10 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + need_des + 0 + 32 + read-write + + + + + WDTFEED + need_des + 0x14 + 0x20 + + + RTC_WDT_FEED + need_des + 31 + 1 + write-only + + + + + WDTWPROTECT + need_des + 0x18 + 0x20 + + + WDT_WKEY + need_des + 0 + 32 + read-write + + + + + SWD_CONF + need_des + 0x1C + 0x20 + 0x12C00000 + + + SWD_RESET_FLAG + need_des + 0 + 1 + read-only + + + SWD_AUTO_FEED_EN + need_des + 18 + 1 + read-write + + + SWD_RST_FLAG_CLR + need_des + 19 + 1 + write-only + + + SWD_SIGNAL_WIDTH + need_des + 20 + 10 + read-write + + + SWD_DISABLE + need_des + 30 + 1 + read-write + + + SWD_FEED + need_des + 31 + 1 + write-only + + + + + SWD_WPROTECT + need_des + 0x20 + 0x20 + + + SWD_WKEY + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x24 + 0x20 + + + SUPER_WDT_INT_RAW + need_des + 30 + 1 + read-write + + + LP_WDT_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST_RTC + need_des + 0x28 + 0x20 + + + SUPER_WDT_INT_ST + need_des + 30 + 1 + read-only + + + WDT_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA_RTC + need_des + 0x2C + 0x20 + + + SUPER_WDT_INT_ENA + need_des + 30 + 1 + read-write + + + WDT_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR_RTC + need_des + 0x30 + 0x20 + + + SUPER_WDT_INT_CLR + need_des + 30 + 1 + write-only + + + WDT_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02112080 + + + LP_WDT_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + MCPWM0 + Motor Control Pulse-Width Modulation 0 + MCPWM + 0x60014000 + + 0x0 + 0x130 + registers + + + MCPWM0 + 61 + + + + CLK_CFG + PWM clock prescaler register. + 0x0 + 0x20 + + + CLK_PRESCALE + Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + 0 + 8 + read-write + + + + + TIMER0_CFG0 + PWM timer0 period and update method configuration register. + 0x4 + 0x20 + 0x0000FF00 + + + TIMER0_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER0_PERIOD + period shadow register of PWM timer0 + 8 + 16 + read-write + + + TIMER0_PERIOD_UPMETHOD + Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER0_CFG1 + PWM timer0 working mode and start/stop control configuration register. + 0x8 + 0x20 + + + TIMER0_START + PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER0_MOD + PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER0_SYNC + PWM timer0 sync function configuration register. + 0xC + 0x20 + + + TIMER0_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER0_SYNCO_SEL + PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit + 2 + 2 + read-write + + + TIMER0_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER0_PHASE_DIRECTION + Configure the PWM timer0's direction when timer0 mode is up-down mode: 0-increase,1-decrease + 20 + 1 + read-write + + + + + TIMER0_STATUS + PWM timer0 status register. + 0x10 + 0x20 + + + TIMER0_VALUE + current PWM timer0 counter value + 0 + 16 + read-only + + + TIMER0_DIRECTION + current PWM timer0 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER1_CFG0 + PWM timer1 period and update method configuration register. + 0x14 + 0x20 + 0x0000FF00 + + + TIMER1_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER1_PERIOD + period shadow register of PWM timer1 + 8 + 16 + read-write + + + TIMER1_PERIOD_UPMETHOD + Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER1_CFG1 + PWM timer1 working mode and start/stop control configuration register. + 0x18 + 0x20 + + + TIMER1_START + PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER1_MOD + PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER1_SYNC + PWM timer1 sync function configuration register. + 0x1C + 0x20 + + + TIMER1_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER1_SYNCO_SEL + PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer1_sync_sw bit + 2 + 2 + read-write + + + TIMER1_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER1_PHASE_DIRECTION + Configure the PWM timer1's direction when timer1 mode is up-down mode: 0-increase,1-decrease + 20 + 1 + read-write + + + + + TIMER1_STATUS + PWM timer1 status register. + 0x20 + 0x20 + + + TIMER1_VALUE + current PWM timer1 counter value + 0 + 16 + read-only + + + TIMER1_DIRECTION + current PWM timer1 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER2_CFG0 + PWM timer2 period and update method configuration register. + 0x24 + 0x20 + 0x0000FF00 + + + TIMER2_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER2_PERIOD + period shadow register of PWM timer2 + 8 + 16 + read-write + + + TIMER2_PERIOD_UPMETHOD + Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER2_CFG1 + PWM timer2 working mode and start/stop control configuration register. + 0x28 + 0x20 + + + TIMER2_START + PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER2_MOD + PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER2_SYNC + PWM timer2 sync function configuration register. + 0x2C + 0x20 + + + TIMER2_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER2_SYNCO_SEL + PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit + 2 + 2 + read-write + + + TIMER2_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER2_PHASE_DIRECTION + Configure the PWM timer2's direction when timer2 mode is up-down mode: 0-increase,1-decrease + 20 + 1 + read-write + + + + + TIMER2_STATUS + PWM timer2 status register. + 0x30 + 0x20 + + + TIMER2_VALUE + current PWM timer2 counter value + 0 + 16 + read-only + + + TIMER2_DIRECTION + current PWM timer2 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER_SYNCI_CFG + Synchronization input selection for three PWM timers. + 0x34 + 0x20 + + + TIMER0_SYNCISEL + select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 0 + 3 + read-write + + + TIMER1_SYNCISEL + select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 3 + 3 + read-write + + + TIMER2_SYNCISEL + select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + invert SYNC0 from GPIO matrix + 9 + 1 + read-write + + + EXTERNAL_SYNCI1_INVERT + invert SYNC1 from GPIO matrix + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + invert SYNC2 from GPIO matrix + 11 + 1 + read-write + + + + + OPERATOR_TIMERSEL + Select specific timer for PWM operators. + 0x38 + 0x20 + + + OPERATOR0_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2 + 0 + 2 + read-write + + + OPERATOR1_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2 + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2 + 4 + 2 + read-write + + + + + GEN0_STMP_CFG + Transfer status and update method for time stamp registers A and B + 0x3C + 0x20 + + + CMPR0_A_UPMETHOD + Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR0_B_UPMETHOD + Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR0_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR0_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + GEN0_TSTMP_A + Shadow register for register A. + 0x40 + 0x20 + + + CMPR0_A + PWM generator 0 time stamp A's shadow register + 0 + 16 + read-write + + + + + GEN0_TSTMP_B + Shadow register for register B. + 0x44 + 0x20 + + + CMPR0_B + PWM generator 0 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN0_CFG0 + Fault event T0 and T1 handling + 0x48 + 0x20 + + + GEN0_CFG_UPMETHOD + Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + 0 + 4 + read-write + + + GEN0_T0_SEL + Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN0_T1_SEL + Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN0_FORCE + Permissives to force PWM0A and PWM0B outputs by software + 0x4C + 0x20 + 0x00000020 + + + GEN0_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN0_A_CNTUFORCE_MODE + Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN0_B_CNTUFORCE_MODE + Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN0_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN0_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN0_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN0_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN0_A + Actions triggered by events on PWM0A + 0x50 + 0x20 + + + UTEZ + Action on PWM0A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN0_B + Actions triggered by events on PWM0B + 0x54 + 0x20 + + + UTEZ + Action on PWM0B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DT0_CFG + dead time type selection and configuration + 0x58 + 0x20 + 0x00018000 + + + DB0_FED_UPMETHOD + Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 0 + 4 + read-write + + + DB0_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 4 + 4 + read-write + + + DB0_DEB_MODE + S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB0_A_OUTSWAP + S6 in table + 9 + 1 + read-write + + + DB0_B_OUTSWAP + S7 in table + 10 + 1 + read-write + + + DB0_RED_INSEL + S4 in table + 11 + 1 + read-write + + + DB0_FED_INSEL + S5 in table + 12 + 1 + read-write + + + DB0_RED_OUTINVERT + S2 in table + 13 + 1 + read-write + + + DB0_FED_OUTINVERT + S3 in table + 14 + 1 + read-write + + + DB0_A_OUTBYPASS + S1 in table + 15 + 1 + read-write + + + DB0_B_OUTBYPASS + S0 in table + 16 + 1 + read-write + + + DB0_CLK_SEL + Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DT0_FED_CFG + Shadow register for falling edge delay (FED). + 0x5C + 0x20 + + + DB0_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DT0_RED_CFG + Shadow register for rising edge delay (RED). + 0x60 + 0x20 + + + DB0_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CARRIER0_CFG + Carrier enable and configuratoin + 0x64 + 0x20 + + + CHOPPER0_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER0_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER0_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER0_OSHTWTH + width of the first pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER0_OUT_INVERT + when set, invert the output of PWM0A and PWM0B for this submodule + 12 + 1 + read-write + + + CHOPPER0_IN_INVERT + when set, invert the input of PWM0A and PWM0B for this submodule + 13 + 1 + read-write + + + + + FH0_CFG0 + Actions on PWM0A and PWM0B trip events + 0x68 + 0x20 + + + TZ0_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ0_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ0_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ0_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ0_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ0_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ0_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ0_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ0_A_CBC_D + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 8 + 2 + read-write + + + TZ0_A_CBC_U + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 10 + 2 + read-write + + + TZ0_A_OST_D + One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 12 + 2 + read-write + + + TZ0_A_OST_U + One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 14 + 2 + read-write + + + TZ0_B_CBC_D + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 16 + 2 + read-write + + + TZ0_B_CBC_U + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + 18 + 2 + read-write + + + TZ0_B_OST_D + One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 20 + 2 + read-write + + + TZ0_B_OST_U + One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 22 + 2 + read-write + + + + + FH0_CFG1 + Software triggers for fault handler actions + 0x6C + 0x20 + + + TZ0_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ0_CBCPULSE + cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP + 1 + 2 + read-write + + + TZ0_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ0_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + FH0_STATUS + Status of fault events. + 0x70 + 0x20 + + + TZ0_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ0_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + GEN1_STMP_CFG + Transfer status and update method for time stamp registers A and B + 0x74 + 0x20 + + + CMPR1_A_UPMETHOD + Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR1_B_UPMETHOD + Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR1_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR1_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + GEN1_TSTMP_A + Shadow register for register A. + 0x78 + 0x20 + + + CMPR1_A + PWM generator 1 time stamp A's shadow register + 0 + 16 + read-write + + + + + GEN1_TSTMP_B + Shadow register for register B. + 0x7C + 0x20 + + + CMPR1_B + PWM generator 1 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN1_CFG0 + Fault event T0 and T1 handling + 0x80 + 0x20 + + + GEN1_CFG_UPMETHOD + Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update. + 0 + 4 + read-write + + + GEN1_T0_SEL + Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN1_T1_SEL + Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN1_FORCE + Permissives to force PWM1A and PWM1B outputs by software + 0x84 + 0x20 + 0x00000020 + + + GEN1_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN1_A_CNTUFORCE_MODE + Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN1_B_CNTUFORCE_MODE + Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN1_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN1_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN1_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN1_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN1_A + Actions triggered by events on PWM1A + 0x88 + 0x20 + + + UTEZ + Action on PWM1A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN1_B + Actions triggered by events on PWM1B + 0x8C + 0x20 + + + UTEZ + Action on PWM1B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DT1_CFG + dead time type selection and configuration + 0x90 + 0x20 + 0x00018000 + + + DB1_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 0 + 4 + read-write + + + DB1_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 4 + 4 + read-write + + + DB1_DEB_MODE + S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB1_A_OUTSWAP + S6 in table + 9 + 1 + read-write + + + DB1_B_OUTSWAP + S7 in table + 10 + 1 + read-write + + + DB1_RED_INSEL + S4 in table + 11 + 1 + read-write + + + DB1_FED_INSEL + S5 in table + 12 + 1 + read-write + + + DB1_RED_OUTINVERT + S2 in table + 13 + 1 + read-write + + + DB1_FED_OUTINVERT + S3 in table + 14 + 1 + read-write + + + DB1_A_OUTBYPASS + S1 in table + 15 + 1 + read-write + + + DB1_B_OUTBYPASS + S0 in table + 16 + 1 + read-write + + + DB1_CLK_SEL + Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DT1_FED_CFG + Shadow register for falling edge delay (FED). + 0x94 + 0x20 + + + DB1_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DT1_RED_CFG + Shadow register for rising edge delay (RED). + 0x98 + 0x20 + + + DB1_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CARRIER1_CFG + Carrier enable and configuratoin + 0x9C + 0x20 + + + CHOPPER1_EN + When set, carrier1 function is enabled. When cleared, carrier1 is bypassed + 0 + 1 + read-write + + + CHOPPER1_PRESCALE + PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER1_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER1_OSHTWTH + width of the first pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER1_OUT_INVERT + when set, invert the output of PWM1A and PWM1B for this submodule + 12 + 1 + read-write + + + CHOPPER1_IN_INVERT + when set, invert the input of PWM1A and PWM1B for this submodule + 13 + 1 + read-write + + + + + FH1_CFG0 + Actions on PWM1A and PWM1B trip events + 0xA0 + 0x20 + + + TZ1_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ1_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ1_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ1_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ1_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ1_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ1_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ1_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ1_A_CBC_D + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 8 + 2 + read-write + + + TZ1_A_CBC_U + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 10 + 2 + read-write + + + TZ1_A_OST_D + One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing,1: force low, 2: force high, 3: toggle + 12 + 2 + read-write + + + TZ1_A_OST_U + One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 14 + 2 + read-write + + + TZ1_B_CBC_D + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 16 + 2 + read-write + + + TZ1_B_CBC_U + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 18 + 2 + read-write + + + TZ1_B_OST_D + One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 20 + 2 + read-write + + + TZ1_B_OST_U + One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 22 + 2 + read-write + + + + + FH1_CFG1 + Software triggers for fault handler actions + 0xA4 + 0x20 + + + TZ1_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ1_CBCPULSE + cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP + 1 + 2 + read-write + + + TZ1_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ1_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + FH1_STATUS + Status of fault events. + 0xA8 + 0x20 + + + TZ1_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ1_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + GEN2_STMP_CFG + Transfer status and update method for time stamp registers A and B + 0xAC + 0x20 + + + CMPR2_A_UPMETHOD + Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR2_B_UPMETHOD + Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR2_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR2_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + GEN2_TSTMP_A + Shadow register for register A. + 0xB0 + 0x20 + + + CMPR2_A + PWM generator 2 time stamp A's shadow register + 0 + 16 + read-write + + + + + GEN2_TSTMP_B + Shadow register for register B. + 0xB4 + 0x20 + + + CMPR2_B + PWM generator 2 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN2_CFG0 + Fault event T0 and T1 handling + 0xB8 + 0x20 + + + GEN2_CFG_UPMETHOD + Update method for PWM generator 2's active register of configuration. 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update. + 0 + 4 + read-write + + + GEN2_T0_SEL + Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN2_T1_SEL + Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN2_FORCE + Permissives to force PWM2A and PWM2B outputs by software + 0xBC + 0x20 + 0x00000020 + + + GEN2_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN2_A_CNTUFORCE_MODE + Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN2_B_CNTUFORCE_MODE + Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN2_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN2_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN2_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN2_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN2_A + Actions triggered by events on PWM2A + 0xC0 + 0x20 + + + UTEZ + Action on PWM2A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN2_B + Actions triggered by events on PWM2B + 0xC4 + 0x20 + + + UTEZ + Action on PWM2B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DT2_CFG + dead time type selection and configuration + 0xC8 + 0x20 + 0x00018000 + + + DB2_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 0 + 4 + read-write + + + DB2_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 4 + 4 + read-write + + + DB2_DEB_MODE + S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB2_A_OUTSWAP + S6 in table + 9 + 1 + read-write + + + DB2_B_OUTSWAP + S7 in table + 10 + 1 + read-write + + + DB2_RED_INSEL + S4 in table + 11 + 1 + read-write + + + DB2_FED_INSEL + S5 in table + 12 + 1 + read-write + + + DB2_RED_OUTINVERT + S2 in table + 13 + 1 + read-write + + + DB2_FED_OUTINVERT + S3 in table + 14 + 1 + read-write + + + DB2_A_OUTBYPASS + S1 in table + 15 + 1 + read-write + + + DB2_B_OUTBYPASS + S0 in table + 16 + 1 + read-write + + + DB2_CLK_SEL + Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DT2_FED_CFG + Shadow register for falling edge delay (FED). + 0xCC + 0x20 + + + DB2_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DT2_RED_CFG + Shadow register for rising edge delay (RED). + 0xD0 + 0x20 + + + DB2_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CARRIER2_CFG + Carrier enable and configuratoin + 0xD4 + 0x20 + + + CHOPPER2_EN + When set, carrier2 function is enabled. When cleared, carrier2 is bypassed + 0 + 1 + read-write + + + CHOPPER2_PRESCALE + PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER2_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER2_OSHTWTH + width of the first pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER2_OUT_INVERT + when set, invert the output of PWM2A and PWM2B for this submodule + 12 + 1 + read-write + + + CHOPPER2_IN_INVERT + when set, invert the input of PWM2A and PWM2B for this submodule + 13 + 1 + read-write + + + + + FH2_CFG0 + Actions on PWM2A and PWM2B trip events + 0xD8 + 0x20 + + + TZ2_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ2_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ2_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ2_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ2_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ2_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ2_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ2_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ2_A_CBC_D + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 8 + 2 + read-write + + + TZ2_A_CBC_U + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 10 + 2 + read-write + + + TZ2_A_OST_D + One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 12 + 2 + read-write + + + TZ2_A_OST_U + One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 14 + 2 + read-write + + + TZ2_B_CBC_D + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 16 + 2 + read-write + + + TZ2_B_CBC_U + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 18 + 2 + read-write + + + TZ2_B_OST_D + One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 20 + 2 + read-write + + + TZ2_B_OST_U + One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 22 + 2 + read-write + + + + + FH2_CFG1 + Software triggers for fault handler actions + 0xDC + 0x20 + + + TZ2_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ2_CBCPULSE + cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP + 1 + 2 + read-write + + + TZ2_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ2_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + FH2_STATUS + Status of fault events. + 0xE0 + 0x20 + + + TZ2_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ2_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + FAULT_DETECT + Fault detection configuration and status + 0xE4 + 0x20 + + + F0_EN + When set, event_f0 generation is enabled + 0 + 1 + read-write + + + F1_EN + When set, event_f1 generation is enabled + 1 + 1 + read-write + + + F2_EN + When set, event_f2 generation is enabled + 2 + 1 + read-write + + + F0_POLE + Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 3 + 1 + read-write + + + F1_POLE + Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 4 + 1 + read-write + + + F2_POLE + Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 5 + 1 + read-write + + + EVENT_F0 + Set and reset by hardware. If set, event_f0 is on going + 6 + 1 + read-only + + + EVENT_F1 + Set and reset by hardware. If set, event_f1 is on going + 7 + 1 + read-only + + + EVENT_F2 + Set and reset by hardware. If set, event_f2 is on going + 8 + 1 + read-only + + + + + CAP_TIMER_CFG + Configure capture timer + 0xE8 + 0x20 + + + CAP_TIMER_EN + When set, capture timer incrementing under APB_clk is enabled. + 0 + 1 + read-write + + + CAP_SYNCI_EN + When set, capture timer sync is enabled. + 1 + 1 + read-write + + + CAP_SYNCI_SEL + capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix + 2 + 3 + read-write + + + CAP_SYNC_SW + When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture timer is loaded with value in phase register. + 5 + 1 + write-only + + + + + CAP_TIMER_PHASE + Phase for capture timer sync + 0xEC + 0x20 + + + CAP_PHASE + Phase value for capture timer sync operation. + 0 + 32 + read-write + + + + + CAP_CH0_CFG + Capture channel 0 configuration and enable + 0xF0 + 0x20 + + + CAP0_EN + When set, capture on channel 0 is enabled + 0 + 1 + read-write + + + CAP0_MODE + Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP0_PRESCALE + Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1 + 3 + 8 + read-write + + + CAP0_IN_INVERT + when set, CAP0 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP0_SW + Write 1 will trigger a software forced capture on channel 0 + 12 + 1 + write-only + + + + + CAP_CH1_CFG + Capture channel 1 configuration and enable + 0xF4 + 0x20 + + + CAP1_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP1_MODE + Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP1_PRESCALE + Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1 + 3 + 8 + read-write + + + CAP1_IN_INVERT + when set, CAP1 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP1_SW + Write 1 will trigger a software forced capture on channel 1 + 12 + 1 + write-only + + + + + CAP_CH2_CFG + Capture channel 2 configuration and enable + 0xF8 + 0x20 + + + CAP2_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP2_MODE + Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP2_PRESCALE + Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1 + 3 + 8 + read-write + + + CAP2_IN_INVERT + when set, CAP2 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP2_SW + Write 1 will trigger a software forced capture on channel 2 + 12 + 1 + write-only + + + + + CAP_CH0 + ch0 capture value status register + 0xFC + 0x20 + + + CAP0_VALUE + Value of last capture on channel 0 + 0 + 32 + read-only + + + + + CAP_CH1 + ch1 capture value status register + 0x100 + 0x20 + + + CAP1_VALUE + Value of last capture on channel 1 + 0 + 32 + read-only + + + + + CAP_CH2 + ch2 capture value status register + 0x104 + 0x20 + + + CAP2_VALUE + Value of last capture on channel 2 + 0 + 32 + read-only + + + + + CAP_STATUS + Edge of last capture trigger + 0x108 + 0x20 + + + CAP0_EDGE + Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + 0 + 1 + read-only + + + CAP1_EDGE + Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + 1 + 1 + read-only + + + CAP2_EDGE + Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + 2 + 1 + read-only + + + + + UPDATE_CFG + Enable update. + 0x10C + 0x20 + 0x00000055 + + + GLOBAL_UP_EN + The global enable of update of all active registers in MCPWM module + 0 + 1 + read-write + + + GLOBAL_FORCE_UP + a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module + 1 + 1 + read-write + + + OP0_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled + 2 + 1 + read-write + + + OP0_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0 + 3 + 1 + read-write + + + OP1_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled + 4 + 1 + read-write + + + OP1_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1 + 5 + 1 + read-write + + + OP2_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled + 6 + 1 + read-write + + + OP2_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2 + 7 + 1 + read-write + + + + + INT_ENA + Interrupt enable bits + 0x110 + 0x20 + + + TIMER0_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_ENA + The enable bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_ENA + The enable bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_ENA + The enable bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-write + + + FAULT1_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-write + + + FAULT2_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-write + + + CMPR0_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_ENA + The enable bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-write + + + CAP1_INT_ENA + The enable bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-write + + + CAP2_INT_ENA + The enable bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-write + + + + + INT_RAW + Raw interrupt status + 0x114 + 0x20 + + + TIMER0_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_RAW + The raw status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_RAW + The raw status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_RAW + The raw status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-write + + + FAULT1_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-write + + + FAULT2_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-write + + + CMPR0_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-write + + + CAP1_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-write + + + CAP2_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x118 + 0x20 + + + TIMER0_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_ST + The masked status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_ST + The masked status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_ST + The masked status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-only + + + FAULT1_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-only + + + FAULT2_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-only + + + CMPR0_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_ST + The masked status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-only + + + CAP1_INT_ST + The masked status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-only + + + CAP2_INT_ST + The masked status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x11C + 0x20 + + + TIMER0_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 0 stops. + 0 + 1 + write-only + + + TIMER1_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 1 stops. + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 2 stops. + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + write-only + + + TIMER0_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + write-only + + + TIMER1_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + write-only + + + TIMER2_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + write-only + + + FAULT0_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 starts. + 9 + 1 + write-only + + + FAULT1_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 starts. + 10 + 1 + write-only + + + FAULT2_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 starts. + 11 + 1 + write-only + + + FAULT0_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 ends. + 12 + 1 + write-only + + + FAULT1_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 ends. + 13 + 1 + write-only + + + FAULT2_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 ends. + 14 + 1 + write-only + + + CMPR0_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + write-only + + + CMPR1_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + write-only + + + CMPR2_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + write-only + + + CMPR0_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + write-only + + + CMPR1_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + write-only + + + CMPR2_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + write-only + + + TZ0_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + write-only + + + TZ1_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + write-only + + + TZ2_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + write-only + + + TZ0_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + write-only + + + TZ1_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + write-only + + + TZ2_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + write-only + + + CAP0_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 0. + 27 + 1 + write-only + + + CAP1_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 1. + 28 + 1 + write-only + + + CAP2_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 2. + 29 + 1 + write-only + + + + + EVT_EN + MCPWM event enable register + 0x120 + 0x20 + + + EVT_TIMER0_STOP_EN + set this bit high to enable timer0 stop event generate + 0 + 1 + read-write + + + EVT_TIMER1_STOP_EN + set this bit high to enable timer1 stop event generate + 1 + 1 + read-write + + + EVT_TIMER2_STOP_EN + set this bit high to enable timer2 stop event generate + 2 + 1 + read-write + + + EVT_TIMER0_TEZ_EN + set this bit high to enable timer0 equal zero event generate + 3 + 1 + read-write + + + EVT_TIMER1_TEZ_EN + set this bit high to enable timer1 equal zero event generate + 4 + 1 + read-write + + + EVT_TIMER2_TEZ_EN + set this bit high to enable timer2 equal zero event generate + 5 + 1 + read-write + + + EVT_TIMER0_TEP_EN + set this bit high to enable timer0 equal period event generate + 6 + 1 + read-write + + + EVT_TIMER1_TEP_EN + set this bit high to enable timer1 equal period event generate + 7 + 1 + read-write + + + EVT_TIMER2_TEP_EN + set this bit high to enable timer2 equal period event generate + 8 + 1 + read-write + + + EVT_OP0_TEA_EN + set this bit high to enable PWM generator0 timer equal a event generate + 9 + 1 + read-write + + + EVT_OP1_TEA_EN + set this bit high to enable PWM generator1 timer equal a event generate + 10 + 1 + read-write + + + EVT_OP2_TEA_EN + set this bit high to enable PWM generator2 timer equal a event generate + 11 + 1 + read-write + + + EVT_OP0_TEB_EN + set this bit high to enable PWM generator0 timer equal b event generate + 12 + 1 + read-write + + + EVT_OP1_TEB_EN + set this bit high to enable PWM generator1 timer equal b event generate + 13 + 1 + read-write + + + EVT_OP2_TEB_EN + set this bit high to enable PWM generator2 timer equal b event generate + 14 + 1 + read-write + + + EVT_F0_EN + set this bit high to enable fault0 event generate + 15 + 1 + read-write + + + EVT_F1_EN + set this bit high to enable fault1 event generate + 16 + 1 + read-write + + + EVT_F2_EN + set this bit high to enable fault2 event generate + 17 + 1 + read-write + + + EVT_F0_CLR_EN + set this bit high to enable fault0 clear event generate + 18 + 1 + read-write + + + EVT_F1_CLR_EN + set this bit high to enable fault1 clear event generate + 19 + 1 + read-write + + + EVT_F2_CLR_EN + set this bit high to enable fault2 clear event generate + 20 + 1 + read-write + + + EVT_TZ0_CBC_EN + set this bit high to enable cycle by cycle trip0 event generate + 21 + 1 + read-write + + + EVT_TZ1_CBC_EN + set this bit high to enable cycle by cycle trip1 event generate + 22 + 1 + read-write + + + EVT_TZ2_CBC_EN + set this bit high to enable cycle by cycle trip2 event generate + 23 + 1 + read-write + + + EVT_TZ0_OST_EN + set this bit high to enable one shot trip0 event generate + 24 + 1 + read-write + + + EVT_TZ1_OST_EN + set this bit high to enable one shot trip1 event generate + 25 + 1 + read-write + + + EVT_TZ2_OST_EN + set this bit high to enable one shot trip2 event generate + 26 + 1 + read-write + + + EVT_CAP0_EN + set this bit high to enable capture0 event generate + 27 + 1 + read-write + + + EVT_CAP1_EN + set this bit high to enable capture1 event generate + 28 + 1 + read-write + + + EVT_CAP2_EN + set this bit high to enable capture2 event generate + 29 + 1 + read-write + + + + + TASK_EN + MCPWM task enable register + 0x124 + 0x20 + + + TASK_CMPR0_A_UP_EN + set this bit high to enable PWM generator0 timer stamp A's shadow register update task receive + 0 + 1 + read-write + + + TASK_CMPR1_A_UP_EN + set this bit high to enable PWM generator1 timer stamp A's shadow register update task receive + 1 + 1 + read-write + + + TASK_CMPR2_A_UP_EN + set this bit high to enable PWM generator2 timer stamp A's shadow register update task receive + 2 + 1 + read-write + + + TASK_CMPR0_B_UP_EN + set this bit high to enable PWM generator0 timer stamp B's shadow register update task receive + 3 + 1 + read-write + + + TASK_CMPR1_B_UP_EN + set this bit high to enable PWM generator1 timer stamp B's shadow register update task receive + 4 + 1 + read-write + + + TASK_CMPR2_B_UP_EN + set this bit high to enable PWM generator2 timer stamp B's shadow register update task receive + 5 + 1 + read-write + + + TASK_GEN_STOP_EN + set this bit high to enable all PWM generate stop task receive + 6 + 1 + read-write + + + TASK_TIMER0_SYNC_EN + set this bit high to enable timer0 sync task receive + 7 + 1 + read-write + + + TASK_TIMER1_SYNC_EN + set this bit high to enable timer1 sync task receive + 8 + 1 + read-write + + + TASK_TIMER2_SYNC_EN + set this bit high to enable timer2 sync task receive + 9 + 1 + read-write + + + TASK_TIMER0_PERIOD_UP_EN + set this bit high to enable timer0 period update task receive + 10 + 1 + read-write + + + TASK_TIMER1_PERIOD_UP_EN + set this bit high to enable timer1 period update task receive + 11 + 1 + read-write + + + TASK_TIMER2_PERIOD_UP_EN + set this bit high to enable timer2 period update task receive + 12 + 1 + read-write + + + TASK_TZ0_OST_EN + set this bit high to enable one shot trip0 task receive + 13 + 1 + read-write + + + TASK_TZ1_OST_EN + set this bit high to enable one shot trip1 task receive + 14 + 1 + read-write + + + TASK_TZ2_OST_EN + set this bit high to enable one shot trip2 task receive + 15 + 1 + read-write + + + TASK_CLR0_OST_EN + set this bit high to enable one shot trip0 clear task receive + 16 + 1 + read-write + + + TASK_CLR1_OST_EN + set this bit high to enable one shot trip1 clear task receive + 17 + 1 + read-write + + + TASK_CLR2_OST_EN + set this bit high to enable one shot trip2 clear task receive + 18 + 1 + read-write + + + TASK_CAP0_EN + set this bit high to enable capture0 task receive + 19 + 1 + read-write + + + TASK_CAP1_EN + set this bit high to enable capture1 task receive + 20 + 1 + read-write + + + TASK_CAP2_EN + set this bit high to enable capture2 task receive + 21 + 1 + read-write + + + + + CLK + MCPWM APB configuration register + 0x128 + 0x20 + + + EN + Force clock on for this register file + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x12C + 0x20 + 0x02201240 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + MEM_MONITOR + MEM_MONITOR Peripheral + MEM_MONITOR + 0x60092000 + + 0x0 + 0x30 + registers + + + + LOG_SETTING + log config regsiter + 0x0 + 0x20 + 0x00000080 + + + LOG_ENA + enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA. + 0 + 3 + read-write + + + LOG_MODE + This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100: HALFWORD monitor, 4'b1000: BYTE monitor. + 3 + 4 + read-write + + + LOG_MEM_LOOP_ENABLE + Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + 7 + 1 + read-write + + + + + LOG_CHECK_DATA + check data regsiter + 0x4 + 0x20 + + + LOG_CHECK_DATA + The special check data, when write this special data, it will trigger logging. + 0 + 32 + read-write + + + + + LOG_DATA_MASK + check data mask register + 0x8 + 0x20 + + + LOG_DATA_MASK + byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on. + 0 + 4 + read-write + + + + + LOG_MIN + log boundary regsiter + 0xC + 0x20 + + + LOG_MIN + the min address of log range + 0 + 32 + read-write + + + + + LOG_MAX + log boundary regsiter + 0x10 + 0x20 + + + LOG_MAX + the max address of log range + 0 + 32 + read-write + + + + + LOG_MEM_START + log message store range register + 0x14 + 0x20 + + + LOG_MEM_START + the start address of writing logging message + 0 + 32 + read-write + + + + + LOG_MEM_END + log message store range register + 0x18 + 0x20 + + + LOG_MEM_END + the end address of writing logging message + 0 + 32 + read-write + + + + + LOG_MEM_CURRENT_ADDR + current writing address. + 0x1C + 0x20 + + + LOG_MEM_CURRENT_ADDR + means next writing address + 0 + 32 + read-only + + + + + LOG_MEM_ADDR_UPDATE + writing address update + 0x20 + 0x20 + + + LOG_MEM_ADDR_UPDATE + Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + 0 + 1 + write-only + + + + + LOG_MEM_FULL_FLAG + full flag status register + 0x24 + 0x20 + + + LOG_MEM_FULL_FLAG + 1 means memory write loop at least one time at the range of MEM_START and MEM_END + 0 + 1 + read-only + + + CLR_LOG_MEM_FULL_FLAG + Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + 1 + 1 + write-only + + + + + CLOCK_GATE + clock gate force on register + 0x28 + 0x20 + + + CLK_EN + Set 1 to force on the clk of mem_monitor register + 0 + 1 + read-write + + + + + DATE + version register + 0x3FC + 0x20 + 0x02202140 + + + DATE + version register + 0 + 28 + read-write + + + + + + + MODEM_LPCON + MODEM_LPCON Peripheral + MODEM_LPCON + 0x600AF000 + + 0x0 + 0x30 + registers + + + + TEST_CONF + 0x0 + 0x20 + + + CLK_EN + 0 + 1 + read-write + + + CLK_DEBUG_ENA + 1 + 1 + read-write + + + + + LP_TIMER_CONF + 0x4 + 0x20 + + + CLK_LP_TIMER_SEL_OSC_SLOW + 0 + 1 + read-write + + + CLK_LP_TIMER_SEL_OSC_FAST + 1 + 1 + read-write + + + CLK_LP_TIMER_SEL_XTAL + 2 + 1 + read-write + + + CLK_LP_TIMER_SEL_XTAL32K + 3 + 1 + read-write + + + CLK_LP_TIMER_DIV_NUM + 4 + 12 + read-write + + + + + COEX_LP_CLK_CONF + 0x8 + 0x20 + + + CLK_COEX_LP_SEL_OSC_SLOW + 0 + 1 + read-write + + + CLK_COEX_LP_SEL_OSC_FAST + 1 + 1 + read-write + + + CLK_COEX_LP_SEL_XTAL + 2 + 1 + read-write + + + CLK_COEX_LP_SEL_XTAL32K + 3 + 1 + read-write + + + CLK_COEX_LP_DIV_NUM + 4 + 12 + read-write + + + + + WIFI_LP_CLK_CONF + 0xC + 0x20 + + + CLK_WIFIPWR_LP_SEL_OSC_SLOW + 0 + 1 + read-write + + + CLK_WIFIPWR_LP_SEL_OSC_FAST + 1 + 1 + read-write + + + CLK_WIFIPWR_LP_SEL_XTAL + 2 + 1 + read-write + + + CLK_WIFIPWR_LP_SEL_XTAL32K + 3 + 1 + read-write + + + CLK_WIFIPWR_LP_DIV_NUM + 4 + 12 + read-write + + + + + I2C_MST_CLK_CONF + 0x10 + 0x20 + + + CLK_I2C_MST_SEL_160M + 0 + 1 + read-write + + + + + MODEM_32K_CLK_CONF + 0x14 + 0x20 + + + CLK_MODEM_32K_SEL + 0 + 2 + read-write + + + + + CLK_CONF + 0x18 + 0x20 + + + CLK_WIFIPWR_EN + 0 + 1 + read-write + + + CLK_COEX_EN + 1 + 1 + read-write + + + CLK_I2C_MST_EN + 2 + 1 + read-write + + + CLK_LP_TIMER_EN + 3 + 1 + read-write + + + + + CLK_CONF_FORCE_ON + 0x1C + 0x20 + + + CLK_WIFIPWR_FO + 0 + 1 + read-write + + + CLK_COEX_FO + 1 + 1 + read-write + + + CLK_I2C_MST_FO + 2 + 1 + read-write + + + CLK_LP_TIMER_FO + 3 + 1 + read-write + + + CLK_BCMEM_FO + 4 + 1 + read-write + + + CLK_I2C_MST_MEM_FO + 5 + 1 + read-write + + + CLK_CHAN_FREQ_MEM_FO + 6 + 1 + read-write + + + CLK_PBUS_MEM_FO + 7 + 1 + read-write + + + CLK_AGC_MEM_FO + 8 + 1 + read-write + + + CLK_DC_MEM_FO + 9 + 1 + read-write + + + + + CLK_CONF_POWER_ST + 0x20 + 0x20 + + + CLK_WIFIPWR_ST_MAP + 16 + 4 + read-write + + + CLK_COEX_ST_MAP + 20 + 4 + read-write + + + CLK_I2C_MST_ST_MAP + 24 + 4 + read-write + + + CLK_LP_APB_ST_MAP + 28 + 4 + read-write + + + + + RST_CONF + 0x24 + 0x20 + + + RST_WIFIPWR + 0 + 1 + write-only + + + RST_COEX + 1 + 1 + write-only + + + RST_I2C_MST + 2 + 1 + write-only + + + RST_LP_TIMER + 3 + 1 + write-only + + + + + MEM_CONF + 0x28 + 0x20 + 0x00020015 + + + DC_MEM_FORCE_PU + 0 + 1 + read-write + + + DC_MEM_FORCE_PD + 1 + 1 + read-write + + + AGC_MEM_FORCE_PU + 2 + 1 + read-write + + + AGC_MEM_FORCE_PD + 3 + 1 + read-write + + + PBUS_MEM_FORCE_PU + 4 + 1 + read-write + + + PBUS_MEM_FORCE_PD + 5 + 1 + read-write + + + BC_MEM_FORCE_PU + 6 + 1 + read-write + + + BC_MEM_FORCE_PD + 7 + 1 + read-write + + + I2C_MST_MEM_FORCE_PU + 8 + 1 + read-write + + + I2C_MST_MEM_FORCE_PD + 9 + 1 + read-write + + + CHAN_FREQ_MEM_FORCE_PU + 10 + 1 + read-write + + + CHAN_FREQ_MEM_FORCE_PD + 11 + 1 + read-write + + + MODEM_PWR_MEM_WP + 12 + 3 + read-write + + + MODEM_PWR_MEM_WA + 15 + 3 + read-write + + + MODEM_PWR_MEM_RA + 18 + 2 + read-write + + + + + DATE + 0x2C + 0x20 + 0x02206240 + + + DATE + 0 + 28 + read-write + + + + + + + MODEM_SYSCON + MODEM_SYSCON Peripheral + MODEM_SYSCON + 0x600A9800 + + 0x0 + 0x28 + registers + + + + TEST_CONF + 0x0 + 0x20 + + + CLK_EN + 0 + 1 + read-write + + + + + CLK_CONF + 0x4 + 0x20 + 0x00200000 + + + CLK_DATA_DUMP_MUX + 21 + 1 + read-write + + + CLK_ETM_EN + 22 + 1 + read-write + + + CLK_ZB_APB_EN + 23 + 1 + read-write + + + CLK_ZB_MAC_EN + 24 + 1 + read-write + + + CLK_MODEM_SEC_ECB_EN + 25 + 1 + read-write + + + CLK_MODEM_SEC_CCM_EN + 26 + 1 + read-write + + + CLK_MODEM_SEC_BAH_EN + 27 + 1 + read-write + + + CLK_MODEM_SEC_APB_EN + 28 + 1 + read-write + + + CLK_MODEM_SEC_EN + 29 + 1 + read-write + + + CLK_BLE_TIMER_EN + 30 + 1 + read-write + + + CLK_DATA_DUMP_EN + 31 + 1 + read-write + + + + + CLK_CONF_FORCE_ON + 0x8 + 0x20 + + + CLK_ETM_FO + 22 + 1 + read-write + + + CLK_ZB_APB_FO + 23 + 1 + read-write + + + CLK_ZB_MAC_FO + 24 + 1 + read-write + + + CLK_MODEM_SEC_ECB_FO + 25 + 1 + read-write + + + CLK_MODEM_SEC_CCM_FO + 26 + 1 + read-write + + + CLK_MODEM_SEC_BAH_FO + 27 + 1 + read-write + + + CLK_MODEM_SEC_APB_FO + 28 + 1 + read-write + + + CLK_MODEM_SEC_FO + 29 + 1 + read-write + + + CLK_BLE_TIMER_FO + 30 + 1 + read-write + + + CLK_DATA_DUMP_FO + 31 + 1 + read-write + + + + + CLK_CONF_POWER_ST + 0xC + 0x20 + + + CLK_ZB_ST_MAP + 8 + 4 + read-write + + + CLK_FE_ST_MAP + 12 + 4 + read-write + + + CLK_BT_ST_MAP + 16 + 4 + read-write + + + CLK_WIFI_ST_MAP + 20 + 4 + read-write + + + CLK_MODEM_PERI_ST_MAP + 24 + 4 + read-write + + + CLK_MODEM_APB_ST_MAP + 28 + 4 + read-write + + + + + MODEM_RST_CONF + 0x10 + 0x20 + + + RST_WIFIBB + 8 + 1 + read-write + + + RST_WIFIMAC + 10 + 1 + read-write + + + RST_FE + 14 + 1 + read-write + + + RST_BTMAC_APB + 15 + 1 + read-write + + + RST_BTMAC + 16 + 1 + read-write + + + RST_BTBB_APB + 17 + 1 + read-write + + + RST_BTBB + 18 + 1 + read-write + + + RST_ETM + 22 + 1 + read-write + + + RST_ZBMAC + 24 + 1 + read-write + + + RST_MODEM_ECB + 25 + 1 + read-write + + + RST_MODEM_CCM + 26 + 1 + read-write + + + RST_MODEM_BAH + 27 + 1 + read-write + + + RST_MODEM_SEC + 29 + 1 + read-write + + + RST_BLE_TIMER + 30 + 1 + read-write + + + RST_DATA_DUMP + 31 + 1 + read-write + + + + + CLK_CONF1 + 0x14 + 0x20 + + + CLK_WIFIBB_22M_EN + 0 + 1 + read-write + + + CLK_WIFIBB_40M_EN + 1 + 1 + read-write + + + CLK_WIFIBB_44M_EN + 2 + 1 + read-write + + + CLK_WIFIBB_80M_EN + 3 + 1 + read-write + + + CLK_WIFIBB_40X_EN + 4 + 1 + read-write + + + CLK_WIFIBB_80X_EN + 5 + 1 + read-write + + + CLK_WIFIBB_40X1_EN + 6 + 1 + read-write + + + CLK_WIFIBB_80X1_EN + 7 + 1 + read-write + + + CLK_WIFIBB_160X1_EN + 8 + 1 + read-write + + + CLK_WIFIMAC_EN + 9 + 1 + read-write + + + CLK_WIFI_APB_EN + 10 + 1 + read-write + + + CLK_FE_20M_EN + 11 + 1 + read-write + + + CLK_FE_40M_EN + 12 + 1 + read-write + + + CLK_FE_80M_EN + 13 + 1 + read-write + + + CLK_FE_160M_EN + 14 + 1 + read-write + + + CLK_FE_CAL_160M_EN + 15 + 1 + read-write + + + CLK_FE_APB_EN + 16 + 1 + read-write + + + CLK_BT_APB_EN + 17 + 1 + read-write + + + CLK_BT_EN + 18 + 1 + read-write + + + CLK_WIFIBB_480M_EN + 19 + 1 + read-write + + + CLK_FE_480M_EN + 20 + 1 + read-write + + + CLK_FE_ANAMODE_40M_EN + 21 + 1 + read-write + + + CLK_FE_ANAMODE_80M_EN + 22 + 1 + read-write + + + CLK_FE_ANAMODE_160M_EN + 23 + 1 + read-write + + + + + CLK_CONF1_FORCE_ON + 0x18 + 0x20 + + + CLK_WIFIBB_22M_FO + 0 + 1 + read-write + + + CLK_WIFIBB_40M_FO + 1 + 1 + read-write + + + CLK_WIFIBB_44M_FO + 2 + 1 + read-write + + + CLK_WIFIBB_80M_FO + 3 + 1 + read-write + + + CLK_WIFIBB_40X_FO + 4 + 1 + read-write + + + CLK_WIFIBB_80X_FO + 5 + 1 + read-write + + + CLK_WIFIBB_40X1_FO + 6 + 1 + read-write + + + CLK_WIFIBB_80X1_FO + 7 + 1 + read-write + + + CLK_WIFIBB_160X1_FO + 8 + 1 + read-write + + + CLK_WIFIMAC_FO + 9 + 1 + read-write + + + CLK_WIFI_APB_FO + 10 + 1 + read-write + + + CLK_FE_20M_FO + 11 + 1 + read-write + + + CLK_FE_40M_FO + 12 + 1 + read-write + + + CLK_FE_80M_FO + 13 + 1 + read-write + + + CLK_FE_160M_FO + 14 + 1 + read-write + + + CLK_FE_CAL_160M_FO + 15 + 1 + read-write + + + CLK_FE_APB_FO + 16 + 1 + read-write + + + CLK_BT_APB_FO + 17 + 1 + read-write + + + CLK_BT_FO + 18 + 1 + read-write + + + CLK_WIFIBB_480M_FO + 19 + 1 + read-write + + + CLK_FE_480M_FO + 20 + 1 + read-write + + + CLK_FE_ANAMODE_40M_FO + 21 + 1 + read-write + + + CLK_FE_ANAMODE_80M_FO + 22 + 1 + read-write + + + CLK_FE_ANAMODE_160M_FO + 23 + 1 + read-write + + + + + WIFI_BB_CFG + 0x1C + 0x20 + + + WIFI_BB_CFG + 0 + 32 + read-write + + + + + MEM_CONF + 0x20 + 0x20 + 0x00000020 + + + MODEM_MEM_WP + 0 + 3 + read-write + + + MODEM_MEM_WA + 3 + 3 + read-write + + + MODEM_MEM_RA + 6 + 2 + read-write + + + + + DATE + 0x24 + 0x20 + 0x02206300 + + + DATE + 0 + 28 + read-write + + + + + + + OTP_DEBUG + OTP_DEBUG Peripheral + OTP_DEBUG + 0x600B3C00 + + 0x0 + 0x210 + registers + + + + WR_DIS + Otp debuger block0 data register1. + 0x0 + 0x20 + + + BLOCK0_WR_DIS + Otp block0 write disable data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W1 + Otp debuger block0 data register2. + 0x4 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W1 + Otp block0 backup1 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W2 + Otp debuger block0 data register3. + 0x8 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W2 + Otp block0 backup1 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W3 + Otp debuger block0 data register4. + 0xC + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W3 + Otp block0 backup1 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W4 + Otp debuger block0 data register5. + 0x10 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W4 + Otp block0 backup1 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W5 + Otp debuger block0 data register6. + 0x14 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W5 + Otp block0 backup1 word5 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W1 + Otp debuger block0 data register7. + 0x18 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W1 + Otp block0 backup2 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W2 + Otp debuger block0 data register8. + 0x1C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W2 + Otp block0 backup2 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W3 + Otp debuger block0 data register9. + 0x20 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W3 + Otp block0 backup2 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W4 + Otp debuger block0 data register10. + 0x24 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W4 + Otp block0 backup2 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W5 + Otp debuger block0 data register11. + 0x28 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W5 + Otp block0 backup2 word5 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W1 + Otp debuger block0 data register12. + 0x2C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W1 + Otp block0 backup3 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W2 + Otp debuger block0 data register13. + 0x30 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W2 + Otp block0 backup3 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W3 + Otp debuger block0 data register14. + 0x34 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W3 + Otp block0 backup3 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W4 + Otp debuger block0 data register15. + 0x38 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W4 + Otp block0 backup3 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W5 + Otp debuger block0 data register16. + 0x3C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W5 + Otp block0 backup3 word5 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W1 + Otp debuger block0 data register17. + 0x40 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W1 + Otp block0 backup4 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W2 + Otp debuger block0 data register18. + 0x44 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W2 + Otp block0 backup4 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W3 + Otp debuger block0 data register19. + 0x48 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W3 + Otp block0 backup4 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W4 + Otp debuger block0 data register20. + 0x4C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W4 + Otp block0 backup4 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W5 + Otp debuger block0 data register21. + 0x50 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W5 + Otp block0 backup4 word5 data. + 0 + 32 + read-only + + + + + BLK1_W1 + Otp debuger block1 data register1. + 0x54 + 0x20 + + + BLOCK1_W1 + Otp block1 word1 data. + 0 + 32 + read-only + + + + + BLK1_W2 + Otp debuger block1 data register2. + 0x58 + 0x20 + + + BLOCK1_W2 + Otp block1 word2 data. + 0 + 32 + read-only + + + + + BLK1_W3 + Otp debuger block1 data register3. + 0x5C + 0x20 + + + BLOCK1_W3 + Otp block1 word3 data. + 0 + 32 + read-only + + + + + BLK1_W4 + Otp debuger block1 data register4. + 0x60 + 0x20 + + + BLOCK1_W4 + Otp block1 word4 data. + 0 + 32 + read-only + + + + + BLK1_W5 + Otp debuger block1 data register5. + 0x64 + 0x20 + + + BLOCK1_W5 + Otp block1 word5 data. + 0 + 32 + read-only + + + + + BLK1_W6 + Otp debuger block1 data register6. + 0x68 + 0x20 + + + BLOCK1_W6 + Otp block1 word6 data. + 0 + 32 + read-only + + + + + BLK1_W7 + Otp debuger block1 data register7. + 0x6C + 0x20 + + + BLOCK1_W7 + Otp block1 word7 data. + 0 + 32 + read-only + + + + + BLK1_W8 + Otp debuger block1 data register8. + 0x70 + 0x20 + + + BLOCK1_W8 + Otp block1 word8 data. + 0 + 32 + read-only + + + + + BLK1_W9 + Otp debuger block1 data register9. + 0x74 + 0x20 + + + BLOCK1_W9 + Otp block1 word9 data. + 0 + 32 + read-only + + + + + BLK2_W1 + Otp debuger block2 data register1. + 0x78 + 0x20 + + + BLOCK2_W1 + Otp block2 word1 data. + 0 + 32 + read-only + + + + + BLK2_W2 + Otp debuger block2 data register2. + 0x7C + 0x20 + + + BLOCK2_W2 + Otp block2 word2 data. + 0 + 32 + read-only + + + + + BLK2_W3 + Otp debuger block2 data register3. + 0x80 + 0x20 + + + BLOCK2_W3 + Otp block2 word3 data. + 0 + 32 + read-only + + + + + BLK2_W4 + Otp debuger block2 data register4. + 0x84 + 0x20 + + + BLOCK2_W4 + Otp block2 word4 data. + 0 + 32 + read-only + + + + + BLK2_W5 + Otp debuger block2 data register5. + 0x88 + 0x20 + + + BLOCK2_W5 + Otp block2 word5 data. + 0 + 32 + read-only + + + + + BLK2_W6 + Otp debuger block2 data register6. + 0x8C + 0x20 + + + BLOCK2_W6 + Otp block2 word6 data. + 0 + 32 + read-only + + + + + BLK2_W7 + Otp debuger block2 data register7. + 0x90 + 0x20 + + + BLOCK2_W7 + Otp block2 word7 data. + 0 + 32 + read-only + + + + + BLK2_W8 + Otp debuger block2 data register8. + 0x94 + 0x20 + + + BLOCK2_W8 + Otp block2 word8 data. + 0 + 32 + read-only + + + + + BLK2_W9 + Otp debuger block2 data register9. + 0x98 + 0x20 + + + BLOCK2_W9 + Otp block2 word9 data. + 0 + 32 + read-only + + + + + BLK2_W10 + Otp debuger block2 data register10. + 0x9C + 0x20 + + + BLOCK2_W10 + Otp block2 word10 data. + 0 + 32 + read-only + + + + + BLK2_W11 + Otp debuger block2 data register11. + 0xA0 + 0x20 + + + BLOCK2_W11 + Otp block2 word11 data. + 0 + 32 + read-only + + + + + BLK3_W1 + Otp debuger block3 data register1. + 0xA4 + 0x20 + + + BLOCK3_W1 + Otp block3 word1 data. + 0 + 32 + read-only + + + + + BLK3_W2 + Otp debuger block3 data register2. + 0xA8 + 0x20 + + + BLOCK3_W2 + Otp block3 word2 data. + 0 + 32 + read-only + + + + + BLK3_W3 + Otp debuger block3 data register3. + 0xAC + 0x20 + + + BLOCK3_W3 + Otp block3 word3 data. + 0 + 32 + read-only + + + + + BLK3_W4 + Otp debuger block3 data register4. + 0xB0 + 0x20 + + + BLOCK3_W4 + Otp block3 word4 data. + 0 + 32 + read-only + + + + + BLK3_W5 + Otp debuger block3 data register5. + 0xB4 + 0x20 + + + BLOCK3_W5 + Otp block3 word5 data. + 0 + 32 + read-only + + + + + BLK3_W6 + Otp debuger block3 data register6. + 0xB8 + 0x20 + + + BLOCK3_W6 + Otp block3 word6 data. + 0 + 32 + read-only + + + + + BLK3_W7 + Otp debuger block3 data register7. + 0xBC + 0x20 + + + BLOCK3_W7 + Otp block3 word7 data. + 0 + 32 + read-only + + + + + BLK3_W8 + Otp debuger block3 data register8. + 0xC0 + 0x20 + + + BLOCK3_W8 + Otp block3 word8 data. + 0 + 32 + read-only + + + + + BLK3_W9 + Otp debuger block3 data register9. + 0xC4 + 0x20 + + + BLOCK3_W9 + Otp block3 word9 data. + 0 + 32 + read-only + + + + + BLK3_W10 + Otp debuger block3 data register10. + 0xC8 + 0x20 + + + BLOCK3_W10 + Otp block3 word10 data. + 0 + 32 + read-only + + + + + BLK3_W11 + Otp debuger block3 data register11. + 0xCC + 0x20 + + + BLOCK3_W11 + Otp block3 word11 data. + 0 + 32 + read-only + + + + + BLK4_W1 + Otp debuger block4 data register1. + 0xD0 + 0x20 + + + BLOCK4_W1 + Otp block4 word1 data. + 0 + 32 + read-only + + + + + BLK4_W2 + Otp debuger block4 data register2. + 0xD4 + 0x20 + + + BLOCK4_W2 + Otp block4 word2 data. + 0 + 32 + read-only + + + + + BLK4_W3 + Otp debuger block4 data register3. + 0xD8 + 0x20 + + + BLOCK4_W3 + Otp block4 word3 data. + 0 + 32 + read-only + + + + + BLK4_W4 + Otp debuger block4 data register4. + 0xDC + 0x20 + + + BLOCK4_W4 + Otp block4 word4 data. + 0 + 32 + read-only + + + + + BLK4_W5 + Otp debuger block4 data register5. + 0xE0 + 0x20 + + + BLOCK4_W5 + Otp block4 word5 data. + 0 + 32 + read-only + + + + + BLK4_W6 + Otp debuger block4 data register6. + 0xE4 + 0x20 + + + BLOCK4_W6 + Otp block4 word6 data. + 0 + 32 + read-only + + + + + BLK4_W7 + Otp debuger block4 data register7. + 0xE8 + 0x20 + + + BLOCK4_W7 + Otp block4 word7 data. + 0 + 32 + read-only + + + + + BLK4_W8 + Otp debuger block4 data register8. + 0xEC + 0x20 + + + BLOCK4_W8 + Otp block4 word8 data. + 0 + 32 + read-only + + + + + BLK4_W9 + Otp debuger block4 data register9. + 0xF0 + 0x20 + + + BLOCK4_W9 + Otp block4 word9 data. + 0 + 32 + read-only + + + + + BLK4_W10 + Otp debuger block4 data registe10. + 0xF4 + 0x20 + + + BLOCK4_W10 + Otp block4 word10 data. + 0 + 32 + read-only + + + + + BLK4_W11 + Otp debuger block4 data register11. + 0xF8 + 0x20 + + + BLOCK4_W11 + Otp block4 word11 data. + 0 + 32 + read-only + + + + + BLK5_W1 + Otp debuger block5 data register1. + 0xFC + 0x20 + + + BLOCK5_W1 + Otp block5 word1 data. + 0 + 32 + read-only + + + + + BLK5_W2 + Otp debuger block5 data register2. + 0x100 + 0x20 + + + BLOCK5_W2 + Otp block5 word2 data. + 0 + 32 + read-only + + + + + BLK5_W3 + Otp debuger block5 data register3. + 0x104 + 0x20 + + + BLOCK5_W3 + Otp block5 word3 data. + 0 + 32 + read-only + + + + + BLK5_W4 + Otp debuger block5 data register4. + 0x108 + 0x20 + + + BLOCK5_W4 + Otp block5 word4 data. + 0 + 32 + read-only + + + + + BLK5_W5 + Otp debuger block5 data register5. + 0x10C + 0x20 + + + BLOCK5_W5 + Otp block5 word5 data. + 0 + 32 + read-only + + + + + BLK5_W6 + Otp debuger block5 data register6. + 0x110 + 0x20 + + + BLOCK5_W6 + Otp block5 word6 data. + 0 + 32 + read-only + + + + + BLK5_W7 + Otp debuger block5 data register7. + 0x114 + 0x20 + + + BLOCK5_W7 + Otp block5 word7 data. + 0 + 32 + read-only + + + + + BLK5_W8 + Otp debuger block5 data register8. + 0x118 + 0x20 + + + BLOCK5_W8 + Otp block5 word8 data. + 0 + 32 + read-only + + + + + BLK5_W9 + Otp debuger block5 data register9. + 0x11C + 0x20 + + + BLOCK5_W9 + Otp block5 word9 data. + 0 + 32 + read-only + + + + + BLK5_W10 + Otp debuger block5 data register10. + 0x120 + 0x20 + + + BLOCK5_W10 + Otp block5 word10 data. + 0 + 32 + read-only + + + + + BLK5_W11 + Otp debuger block5 data register11. + 0x124 + 0x20 + + + BLOCK5_W11 + Otp block5 word11 data. + 0 + 32 + read-only + + + + + BLK6_W1 + Otp debuger block6 data register1. + 0x128 + 0x20 + + + BLOCK6_W1 + Otp block6 word1 data. + 0 + 32 + read-only + + + + + BLK6_W2 + Otp debuger block6 data register2. + 0x12C + 0x20 + + + BLOCK6_W2 + Otp block6 word2 data. + 0 + 32 + read-only + + + + + BLK6_W3 + Otp debuger block6 data register3. + 0x130 + 0x20 + + + BLOCK6_W3 + Otp block6 word3 data. + 0 + 32 + read-only + + + + + BLK6_W4 + Otp debuger block6 data register4. + 0x134 + 0x20 + + + BLOCK6_W4 + Otp block6 word4 data. + 0 + 32 + read-only + + + + + BLK6_W5 + Otp debuger block6 data register5. + 0x138 + 0x20 + + + BLOCK6_W5 + Otp block6 word5 data. + 0 + 32 + read-only + + + + + BLK6_W6 + Otp debuger block6 data register6. + 0x13C + 0x20 + + + BLOCK6_W6 + Otp block6 word6 data. + 0 + 32 + read-only + + + + + BLK6_W7 + Otp debuger block6 data register7. + 0x140 + 0x20 + + + BLOCK6_W7 + Otp block6 word7 data. + 0 + 32 + read-only + + + + + BLK6_W8 + Otp debuger block6 data register8. + 0x144 + 0x20 + + + BLOCK6_W8 + Otp block6 word8 data. + 0 + 32 + read-only + + + + + BLK6_W9 + Otp debuger block6 data register9. + 0x148 + 0x20 + + + BLOCK6_W9 + Otp block6 word9 data. + 0 + 32 + read-only + + + + + BLK6_W10 + Otp debuger block6 data register10. + 0x14C + 0x20 + + + BLOCK6_W10 + Otp block6 word10 data. + 0 + 32 + read-only + + + + + BLK6_W11 + Otp debuger block6 data register11. + 0x150 + 0x20 + + + BLOCK6_W11 + Otp block6 word11 data. + 0 + 32 + read-only + + + + + BLK7_W1 + Otp debuger block7 data register1. + 0x154 + 0x20 + + + BLOCK7_W1 + Otp block7 word1 data. + 0 + 32 + read-only + + + + + BLK7_W2 + Otp debuger block7 data register2. + 0x158 + 0x20 + + + BLOCK7_W2 + Otp block7 word2 data. + 0 + 32 + read-only + + + + + BLK7_W3 + Otp debuger block7 data register3. + 0x15C + 0x20 + + + BLOCK7_W3 + Otp block7 word3 data. + 0 + 32 + read-only + + + + + BLK7_W4 + Otp debuger block7 data register4. + 0x160 + 0x20 + + + BLOCK7_W4 + Otp block7 word4 data. + 0 + 32 + read-only + + + + + BLK7_W5 + Otp debuger block7 data register5. + 0x164 + 0x20 + + + BLOCK7_W5 + Otp block7 word5 data. + 0 + 32 + read-only + + + + + BLK7_W6 + Otp debuger block7 data register6. + 0x168 + 0x20 + + + BLOCK7_W6 + Otp block7 word6 data. + 0 + 32 + read-only + + + + + BLK7_W7 + Otp debuger block7 data register7. + 0x16C + 0x20 + + + BLOCK7_W7 + Otp block7 word7 data. + 0 + 32 + read-only + + + + + BLK7_W8 + Otp debuger block7 data register8. + 0x170 + 0x20 + + + BLOCK7_W8 + Otp block7 word8 data. + 0 + 32 + read-only + + + + + BLK7_W9 + Otp debuger block7 data register9. + 0x174 + 0x20 + + + BLOCK7_W9 + Otp block7 word9 data. + 0 + 32 + read-only + + + + + BLK7_W10 + Otp debuger block7 data register10. + 0x178 + 0x20 + + + BLOCK7_W10 + Otp block7 word10 data. + 0 + 32 + read-only + + + + + BLK7_W11 + Otp debuger block7 data register11. + 0x17C + 0x20 + + + BLOCK7_W11 + Otp block7 word11 data. + 0 + 32 + read-only + + + + + BLK8_W1 + Otp debuger block8 data register1. + 0x180 + 0x20 + + + BLOCK8_W1 + Otp block8 word1 data. + 0 + 32 + read-only + + + + + BLK8_W2 + Otp debuger block8 data register2. + 0x184 + 0x20 + + + BLOCK8_W2 + Otp block8 word2 data. + 0 + 32 + read-only + + + + + BLK8_W3 + Otp debuger block8 data register3. + 0x188 + 0x20 + + + BLOCK8_W3 + Otp block8 word3 data. + 0 + 32 + read-only + + + + + BLK8_W4 + Otp debuger block8 data register4. + 0x18C + 0x20 + + + BLOCK8_W4 + Otp block8 word4 data. + 0 + 32 + read-only + + + + + BLK8_W5 + Otp debuger block8 data register5. + 0x190 + 0x20 + + + BLOCK8_W5 + Otp block8 word5 data. + 0 + 32 + read-only + + + + + BLK8_W6 + Otp debuger block8 data register6. + 0x194 + 0x20 + + + BLOCK8_W6 + Otp block8 word6 data. + 0 + 32 + read-only + + + + + BLK8_W7 + Otp debuger block8 data register7. + 0x198 + 0x20 + + + BLOCK8_W7 + Otp block8 word7 data. + 0 + 32 + read-only + + + + + BLK8_W8 + Otp debuger block8 data register8. + 0x19C + 0x20 + + + BLOCK8_W8 + Otp block8 word8 data. + 0 + 32 + read-only + + + + + BLK8_W9 + Otp debuger block8 data register9. + 0x1A0 + 0x20 + + + BLOCK8_W9 + Otp block8 word9 data. + 0 + 32 + read-only + + + + + BLK8_W10 + Otp debuger block8 data register10. + 0x1A4 + 0x20 + + + BLOCK8_W10 + Otp block8 word10 data. + 0 + 32 + read-only + + + + + BLK8_W11 + Otp debuger block8 data register11. + 0x1A8 + 0x20 + + + BLOCK8_W11 + Otp block8 word11 data. + 0 + 32 + read-only + + + + + BLK9_W1 + Otp debuger block9 data register1. + 0x1AC + 0x20 + + + BLOCK9_W1 + Otp block9 word1 data. + 0 + 32 + read-only + + + + + BLK9_W2 + Otp debuger block9 data register2. + 0x1B0 + 0x20 + + + BLOCK9_W2 + Otp block9 word2 data. + 0 + 32 + read-only + + + + + BLK9_W3 + Otp debuger block9 data register3. + 0x1B4 + 0x20 + + + BLOCK9_W3 + Otp block9 word3 data. + 0 + 32 + read-only + + + + + BLK9_W4 + Otp debuger block9 data register4. + 0x1B8 + 0x20 + + + BLOCK9_W4 + Otp block9 word4 data. + 0 + 32 + read-only + + + + + BLK9_W5 + Otp debuger block9 data register5. + 0x1BC + 0x20 + + + BLOCK9_W5 + Otp block9 word5 data. + 0 + 32 + read-only + + + + + BLK9_W6 + Otp debuger block9 data register6. + 0x1C0 + 0x20 + + + BLOCK9_W6 + Otp block9 word6 data. + 0 + 32 + read-only + + + + + BLK9_W7 + Otp debuger block9 data register7. + 0x1C4 + 0x20 + + + BLOCK9_W7 + Otp block9 word7 data. + 0 + 32 + read-only + + + + + BLK9_W8 + Otp debuger block9 data register8. + 0x1C8 + 0x20 + + + BLOCK9_W8 + Otp block9 word8 data. + 0 + 32 + read-only + + + + + BLK9_W9 + Otp debuger block9 data register9. + 0x1CC + 0x20 + + + BLOCK9_W9 + Otp block9 word9 data. + 0 + 32 + read-only + + + + + BLK9_W10 + Otp debuger block9 data register10. + 0x1D0 + 0x20 + + + BLOCK9_W10 + Otp block9 word10 data. + 0 + 32 + read-only + + + + + BLK9_W11 + Otp debuger block9 data register11. + 0x1D4 + 0x20 + + + BLOCK9_W11 + Otp block9 word11 data. + 0 + 32 + read-only + + + + + BLK10_W1 + Otp debuger block10 data register1. + 0x1D8 + 0x20 + + + BLOCK10_W1 + Otp block10 word1 data. + 0 + 32 + read-only + + + + + BLK10_W2 + Otp debuger block10 data register2. + 0x1DC + 0x20 + + + BLOCK10_W2 + Otp block10 word2 data. + 0 + 32 + read-only + + + + + BLK10_W3 + Otp debuger block10 data register3. + 0x1E0 + 0x20 + + + BLOCK10_W3 + Otp block10 word3 data. + 0 + 32 + read-only + + + + + BLK10_W4 + Otp debuger block10 data register4. + 0x1E4 + 0x20 + + + BLOCK10_W4 + Otp block10 word4 data. + 0 + 32 + read-only + + + + + BLK10_W5 + Otp debuger block10 data register5. + 0x1E8 + 0x20 + + + BLOCK10_W5 + Otp block10 word5 data. + 0 + 32 + read-only + + + + + BLK10_W6 + Otp debuger block10 data register6. + 0x1EC + 0x20 + + + BLOCK10_W6 + Otp block10 word6 data. + 0 + 32 + read-only + + + + + BLK10_W7 + Otp debuger block10 data register7. + 0x1F0 + 0x20 + + + BLOCK10_W7 + Otp block10 word7 data. + 0 + 32 + read-only + + + + + BLK10_W8 + Otp debuger block10 data register8. + 0x1F4 + 0x20 + + + BLOCK10_W8 + Otp block10 word8 data. + 0 + 32 + read-only + + + + + BLK10_W9 + Otp debuger block10 data register9. + 0x1F8 + 0x20 + + + BLOCK10_W9 + Otp block10 word9 data. + 0 + 32 + read-only + + + + + BLK10_W10 + Otp debuger block10 data register10. + 0x1FC + 0x20 + + + BLOCK19_W10 + Otp block10 word10 data. + 0 + 32 + read-only + + + + + BLK10_W11 + Otp debuger block10 data register11. + 0x200 + 0x20 + + + BLOCK10_W11 + Otp block10 word11 data. + 0 + 32 + read-only + + + + + CLK + Otp debuger clk_en configuration register. + 0x204 + 0x20 + + + EN + Force clock on for this register file. + 0 + 1 + read-write + + + + + APB2OTP_EN + Otp_debuger apb2otp enable configuration register. + 0x208 + 0x20 + + + APB2OTP_EN + Debug mode enable signal. + 0 + 1 + read-write + + + + + DATE + eFuse version register. + 0x20C + 0x20 + 0x20211028 + + + DATE + Stores otp_debug version. + 0 + 28 + read-write + + + + + + + PARL_IO + Parallel IO Controller + PARL_IO + 0x60015000 + + 0x0 + 0x2C + registers + + + PARL_IO + 63 + + + + RX_CFG0 + Parallel RX module configuration register0. + 0x0 + 0x20 + + + RX_EOF_GEN_SEL + Write 0 to select eof generated manchnism by configured data byte length. Write 1 to select eof generated manchnism by external enable signal. + 0 + 1 + read-write + + + RX_START + Write 1 to start rx global data sampling. + 1 + 1 + read-write + + + RX_DATA_BYTELEN + Configures rx receieved data byte length. + 2 + 16 + read-write + + + RX_SW_EN + Write 1 to enable software data sampling. + 18 + 1 + read-write + + + RX_PULSE_SUBMODE_SEL + Pulse submode selection. +0000: positive pulse start(data bit included) && positive pulse end(data bit included) +0001: positive pulse start(data bit included) && positive pulse end (data bit excluded) +0010: positive pulse start(data bit excluded) && positive pulse end (data bit included) +0011: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) +0100: positive pulse start(data bit included) && length end +0101: positive pulse start(data bit excluded) && length end +0110: negative pulse start(data bit included) && negative pulse end(data bit included) +0111: negative pulse start(data bit included) && negative pulse end (data bit excluded) +1000: negative pulse start(data bit excluded) && negative pulse end (data bit included) +1001: negative pulse start(data bit excluded) && negative pulse end (data bit excluded) +1010: negative pulse start(data bit included) && length end +1011: negative pulse start(data bit excluded) && length end + 19 + 4 + read-write + + + RX_LEVEL_SUBMODE_SEL + Write 0 to sample data at high level of external enable signal. Write 1 to sample data at low level of external enable signal. + 23 + 1 + read-write + + + RX_SMP_MODE_SEL + Rx data sampling mode selection. +000: external level enable mode +001: external pulse enable mode +010: internal software enable mode + 24 + 2 + read-write + + + RX_CLK_EDGE_SEL + Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable sampling data on the falling edge of rx clock. + 26 + 1 + read-write + + + RX_BIT_PACK_ORDER + Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0 to pack bits into 1byte from LSB when data bus width is 4/2/1 bits. + 27 + 1 + read-write + + + RX_BUS_WID_SEL + Rx data bus width selection. +100: bus width is 1 bit +011: bus width is 2 bits +010: bus width is 4 bits +001: bus width is 8 bits +000: bus width is 16 bits + 28 + 3 + read-write + + + RX_FIFO_SRST + Write 1 to enable soft reset of async fifo in rx module. + 31 + 1 + read-write + + + + + RX_CFG1 + Parallel RX module configuration register1. + 0x4 + 0x20 + 0x0FFFF008 + + + RX_REG_UPDATE + Write 1 to update rx register configuration signals. + 2 + 1 + write-only + + + RX_TIMEOUT_EN + Write 1 to enable timeout count to generate error eof. + 3 + 1 + read-write + + + RX_EXT_EN_SEL + Configures rx external enable signal selection from 16 data lines. + 12 + 4 + read-write + + + RX_TIMEOUT_THRESHOLD + Configures rx threshold of timeout counter. + 16 + 16 + read-write + + + + + TX_CFG0 + Parallel TX module configuration register0. + 0x8 + 0x20 + + + TX_BYTELEN + Configures tx sending data byte length. + 2 + 16 + read-write + + + TX_GATING_EN + Write 1 to enable output tx clock gating. + 18 + 1 + read-write + + + TX_START + Write 1 to start tx global data output. + 19 + 1 + read-write + + + TX_HW_VALID_EN + Write 1 to enable tx hardware data valid signal. + 20 + 1 + read-write + + + TX_SMP_EDGE_SEL + Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable sampling data on the falling edge of tx clock. + 25 + 1 + read-write + + + TX_BIT_UNPACK_ORDER + Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write 0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits. + 26 + 1 + read-write + + + TX_BUS_WID_SEL + Tx data bus width selection. +100: bus width is 1 bit +011: bus width is 2 bits +010: bus width is 4 bits +001: bus width is 8 bits +000: bus width is 16 bits + 27 + 3 + read-write + + + TX_FIFO_SRST + Write 1 to enable soft reset of async fifo in tx module. + 30 + 1 + read-write + + + + + TX_CFG1 + Parallel TX module configuration register1. + 0xC + 0x20 + + + TX_IDLE_VALUE + Configures data value on tx bus when IDLE state. + 16 + 16 + read-write + + + + + ST + Parallel IO module status register0. + 0x10 + 0x20 + + + TX_READY + Represents the status that tx is ready. + 31 + 1 + read-only + + + + + INT_ENA + Parallel IO interrupt enable singal configuration register. + 0x14 + 0x20 + + + TX_FIFO_REMPTY_INT_ENA + Write 1 to enable TX_FIFO_REMPTY_INTR. + 0 + 1 + read-write + + + RX_FIFO_WFULL_INT_ENA + Write 1 to enable RX_FIFO_WFULL_INTR. + 1 + 1 + read-write + + + TX_EOF_INT_ENA + Write 1 to enable TX_EOF_INTR. + 2 + 1 + read-write + + + + + INT_RAW + Parallel IO interrupt raw singal status register. + 0x18 + 0x20 + + + TX_FIFO_REMPTY_INT_RAW + The raw interrupt status of TX_FIFO_REMPTY_INTR. + 0 + 1 + read-write + + + RX_FIFO_WFULL_INT_RAW + The raw interrupt status of RX_FIFO_WFULL_INTR. + 1 + 1 + read-write + + + TX_EOF_INT_RAW + The raw interrupt status of TX_EOF_INTR. + 2 + 1 + read-write + + + + + INT_ST + Parallel IO interrupt singal status register. + 0x1C + 0x20 + + + TX_FIFO_REMPTY_INT_ST + The masked interrupt status of TX_FIFO_REMPTY_INTR. + 0 + 1 + read-only + + + RX_FIFO_WFULL_INT_ST + The masked interrupt status of RX_FIFO_WFULL_INTR. + 1 + 1 + read-only + + + TX_EOF_INT_ST + The masked interrupt status of TX_EOF_INTR. + 2 + 1 + read-only + + + + + INT_CLR + Parallel IO interrupt clear singal configuration register. + 0x20 + 0x20 + + + TX_FIFO_REMPTY_INT_CLR + Write 1 to clear TX_FIFO_REMPTY_INTR. + 0 + 1 + write-only + + + RX_FIFO_WFULL_INT_CLR + Write 1 to clear RX_FIFO_WFULL_INTR. + 1 + 1 + write-only + + + TX_EOF_INT_CLR + Write 1 to clear TX_EOF_INTR. + 2 + 1 + write-only + + + + + CLK + Parallel IO clk configuration register + 0x120 + 0x20 + + + EN + Force clock on for this register file + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x3FC + 0x20 + 0x02202240 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + PAU + PAU Peripheral + PAU + 0x60093000 + + 0x0 + 0x4C + registers + + + PAU + 32 + + + + REGDMA_CONF + Peri backup control register + 0x0 + 0x20 + + + FLOW_ERR + backup error type + 0 + 3 + read-only + + + START + backup start signal + 3 + 1 + write-only + + + TO_MEM + backup direction(reg to mem / mem to reg) + 4 + 1 + read-write + + + LINK_SEL + Link select + 5 + 2 + read-write + + + START_MAC + mac sw backup start signal + 7 + 1 + write-only + + + TO_MEM_MAC + mac sw backup direction(reg to mem / mem to reg) + 8 + 1 + read-write + + + SEL_MAC + mac hw/sw select + 9 + 1 + read-write + + + + + REGDMA_CLK_CONF + Clock control register + 0x4 + 0x20 + + + CLK_EN + clock enable + 0 + 1 + read-write + + + + + REGDMA_ETM_CTRL + ETM start ctrl reg + 0x8 + 0x20 + + + ETM_START_0 + etm_start_0 reg + 0 + 1 + write-only + + + ETM_START_1 + etm_start_1 reg + 1 + 1 + write-only + + + ETM_START_2 + etm_start_2 reg + 2 + 1 + write-only + + + ETM_START_3 + etm_start_3 reg + 3 + 1 + write-only + + + + + REGDMA_LINK_0_ADDR + link_0_addr + 0xC + 0x20 + + + LINK_ADDR_0 + link_0_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_1_ADDR + Link_1_addr + 0x10 + 0x20 + + + LINK_ADDR_1 + Link_1_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_2_ADDR + Link_2_addr + 0x14 + 0x20 + + + LINK_ADDR_2 + Link_2_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_3_ADDR + Link_3_addr + 0x18 + 0x20 + + + LINK_ADDR_3 + Link_3_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_MAC_ADDR + Link_mac_addr + 0x1C + 0x20 + + + LINK_ADDR_MAC + Link_mac_addr reg + 0 + 32 + read-write + + + + + REGDMA_CURRENT_LINK_ADDR + current link addr + 0x20 + 0x20 + + + CURRENT_LINK_ADDR + current link addr reg + 0 + 32 + read-only + + + + + REGDMA_BACKUP_ADDR + Backup addr + 0x24 + 0x20 + + + BACKUP_ADDR + backup addr reg + 0 + 32 + read-only + + + + + REGDMA_MEM_ADDR + mem addr + 0x28 + 0x20 + + + MEM_ADDR + mem addr reg + 0 + 32 + read-only + + + + + REGDMA_BKP_CONF + backup config + 0x2C + 0x20 + 0x7D101920 + + + READ_INTERVAL + Link read_interval + 0 + 7 + read-write + + + LINK_TOUT_THRES + link wait timeout threshold + 7 + 10 + read-write + + + BURST_LIMIT + burst limit + 17 + 5 + read-write + + + BACKUP_TOUT_THRES + Backup timeout threshold + 22 + 10 + read-write + + + + + RETENTION_LINK_BASE + retention dma link base + 0x30 + 0x20 + + + LINK_BASE_ADDR + retention dma link base + 0 + 27 + read-write + + + + + RETENTION_CFG + retention_cfg + 0x34 + 0x20 + 0xFFFFFFFF + + + RET_INV_CFG + retention inv scan out + 0 + 32 + read-write + + + + + INT_ENA + Read only register for error and done + 0x38 + 0x20 + + + DONE_INT_ENA + backup done flag + 0 + 1 + read-write + + + ERROR_INT_ENA + error flag + 1 + 1 + read-write + + + + + INT_RAW + Read only register for error and done + 0x3C + 0x20 + + + DONE_INT_RAW + backup done flag + 0 + 1 + read-write + + + ERROR_INT_RAW + error flag + 1 + 1 + read-write + + + + + INT_CLR + Read only register for error and done + 0x40 + 0x20 + + + DONE_INT_CLR + backup done flag + 0 + 1 + write-only + + + ERROR_INT_CLR + error flag + 1 + 1 + write-only + + + + + INT_ST + Read only register for error and done + 0x44 + 0x20 + + + DONE_INT_ST + backup done flag + 0 + 1 + read-only + + + ERROR_INT_ST + error flag + 1 + 1 + read-only + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x02203070 + + + DATE + REGDMA date information/ REGDMA version information. + 0 + 28 + read-write + + + + + + + PCNT + Pulse Count Controller + PCNT + 0x60012000 + + 0x0 + 0x68 + registers + + + PCNT + 62 + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES + This sets the maximum threshold, in APB_CLK cycles, for the filter. + +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN + This is the enable bit for unit %s's thr_h_lim comparator. + 12 + 1 + read-write + + + THR_L_LIM_EN + This is the enable bit for unit %s's thr_l_lim comparator. + 13 + 1 + read-write + + + THR_THRES0_EN + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE + This register sets the behavior when the signal input of channel 0 detects a negative edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 16 + 2 + read-write + + + CH0_POS_MODE + This register sets the behavior when the signal input of channel 0 detects a positive edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 18 + 2 + read-write + + + CH0_HCTRL_MODE + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 20 + 2 + read-write + + + CH0_LCTRL_MODE + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 22 + 2 + read-write + + + CH1_NEG_MODE + This register sets the behavior when the signal input of channel 1 detects a negative edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 24 + 2 + read-write + + + CH1_POS_MODE + This register sets the behavior when the signal input of channel 1 detects a positive edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 26 + 2 + read-write + + + CH1_HCTRL_MODE + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 28 + 2 + read-write + + + CH1_LCTRL_MODE + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0 + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1 + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM + This register is used to configure the thr_h_lim value for unit %s. + 0 + 16 + read-write + + + CNT_L_LIM + This register is used to configure the thr_l_lim value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + CNT + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0 + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1 + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2 + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3 + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0 + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1 + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2 + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3 + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0 + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1 + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2 + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3 + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0 + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1 + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2 + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3 + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + ZERO_MODE + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + THRES1 + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others + 2 + 1 + read-only + + + THRES0 + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others + 3 + 1 + read-only + + + L_LIM + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others + 4 + 1 + read-only + + + H_LIM + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others + 5 + 1 + read-only + + + ZERO + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000001 + + + CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 0's counter. + 1 + 1 + read-write + + + CNT_RST_U1 + Set this bit to clear unit 1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 1's counter. + 3 + 1 + read-write + + + CNT_RST_U2 + Set this bit to clear unit 2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 2's counter. + 5 + 1 + read-write + + + CNT_RST_U3 + Set this bit to clear unit 3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 3's counter. + 7 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x19072601 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + PCR + PCR Peripheral + PCR + 0x60096000 + + 0x0 + 0x14C + registers + + + + UART0_CONF + UART0 configuration register + 0x0 + 0x20 + 0x00000001 + + + UART0_CLK_EN + Set 1 to enable uart0 apb clock + 0 + 1 + read-write + + + UART0_RST_EN + Set 0 to reset uart0 module + 1 + 1 + read-write + + + + + UART0_SCLK_CONF + UART0_SCLK configuration register + 0x4 + 0x20 + 0x00700000 + + + UART0_SCLK_DIV_A + The denominator of the frequency divider factor of the uart0 function clock. + 0 + 6 + read-write + + + UART0_SCLK_DIV_B + The numerator of the frequency divider factor of the uart0 function clock. + 6 + 6 + read-write + + + UART0_SCLK_DIV_NUM + The integral part of the frequency divider factor of the uart0 function clock. + 12 + 8 + read-write + + + UART0_SCLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL. + 20 + 2 + read-write + + + UART0_SCLK_EN + Set 1 to enable uart0 function clock + 22 + 1 + read-write + + + + + UART0_PD_CTRL + UART0 power control register + 0x8 + 0x20 + 0x00000002 + + + UART0_MEM_FORCE_PU + Set this bit to force power down UART0 memory. + 1 + 1 + read-write + + + UART0_MEM_FORCE_PD + Set this bit to force power up UART0 memory. + 2 + 1 + read-write + + + + + UART1_CONF + UART1 configuration register + 0xC + 0x20 + 0x00000001 + + + UART1_CLK_EN + Set 1 to enable uart1 apb clock + 0 + 1 + read-write + + + UART1_RST_EN + Set 0 to reset uart1 module + 1 + 1 + read-write + + + + + UART1_SCLK_CONF + UART1_SCLK configuration register + 0x10 + 0x20 + 0x00700000 + + + UART1_SCLK_DIV_A + The denominator of the frequency divider factor of the uart1 function clock. + 0 + 6 + read-write + + + UART1_SCLK_DIV_B + The numerator of the frequency divider factor of the uart1 function clock. + 6 + 6 + read-write + + + UART1_SCLK_DIV_NUM + The integral part of the frequency divider factor of the uart1 function clock. + 12 + 8 + read-write + + + UART1_SCLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL. + 20 + 2 + read-write + + + UART1_SCLK_EN + Set 1 to enable uart0 function clock + 22 + 1 + read-write + + + + + UART1_PD_CTRL + UART1 power control register + 0x14 + 0x20 + 0x00000002 + + + UART1_MEM_FORCE_PU + Set this bit to force power down UART1 memory. + 1 + 1 + read-write + + + UART1_MEM_FORCE_PD + Set this bit to force power up UART1 memory. + 2 + 1 + read-write + + + + + MSPI_CONF + MSPI configuration register + 0x18 + 0x20 + 0x00000005 + + + MSPI_CLK_EN + Set 1 to enable mspi clock, include mspi pll clock + 0 + 1 + read-write + + + MSPI_RST_EN + Set 0 to reset mspi module + 1 + 1 + read-write + + + MSPI_PLL_CLK_EN + Set 1 to enable mspi pll clock + 2 + 1 + read-write + + + + + MSPI_CLK_CONF + MSPI_CLK configuration register + 0x1C + 0x20 + 0x00000300 + + + MSPI_FAST_LS_DIV_NUM + Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a low-speed clock-source such as XTAL/FOSC. + 0 + 8 + read-write + + + MSPI_FAST_HS_DIV_NUM + Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a high-speed clock-source such as SPLL. + 8 + 8 + read-write + + + + + I2C0_CONF + I2C configuration register + 0x20 + 0x20 + 0x00000001 + + + I2C0_CLK_EN + Set 1 to enable i2c apb clock + 0 + 1 + read-write + + + I2C0_RST_EN + Set 0 to reset i2c module + 1 + 1 + read-write + + + + + I2C_SCLK_CONF + I2C_SCLK configuration register + 0x24 + 0x20 + 0x00400000 + + + I2C_SCLK_DIV_A + The denominator of the frequency divider factor of the i2c function clock. + 0 + 6 + read-write + + + I2C_SCLK_DIV_B + The numerator of the frequency divider factor of the i2c function clock. + 6 + 6 + read-write + + + I2C_SCLK_DIV_NUM + The integral part of the frequency divider factor of the i2c function clock. + 12 + 8 + read-write + + + I2C_SCLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + I2C_SCLK_EN + Set 1 to enable i2c function clock + 22 + 1 + read-write + + + + + UHCI_CONF + UHCI configuration register + 0x28 + 0x20 + 0x00000001 + + + UHCI_CLK_EN + Set 1 to enable uhci clock + 0 + 1 + read-write + + + UHCI_RST_EN + Set 0 to reset uhci module + 1 + 1 + read-write + + + + + RMT_CONF + RMT configuration register + 0x2C + 0x20 + 0x00000001 + + + RMT_CLK_EN + Set 1 to enable rmt apb clock + 0 + 1 + read-write + + + RMT_RST_EN + Set 0 to reset rmt module + 1 + 1 + read-write + + + + + RMT_SCLK_CONF + RMT_SCLK configuration register + 0x30 + 0x20 + 0x00501000 + + + SCLK_DIV_A + The denominator of the frequency divider factor of the rmt function clock. + 0 + 6 + read-write + + + SCLK_DIV_B + The numerator of the frequency divider factor of the rmt function clock. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor of the rmt function clock. + 12 + 8 + read-write + + + SCLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1(default): 80MHz, 2: FOSC, 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set 1 to enable rmt function clock + 22 + 1 + read-write + + + + + LEDC_CONF + LEDC configuration register + 0x34 + 0x20 + 0x00000001 + + + LEDC_CLK_EN + Set 1 to enable ledc apb clock + 0 + 1 + read-write + + + LEDC_RST_EN + Set 0 to reset ledc module + 1 + 1 + read-write + + + + + LEDC_SCLK_CONF + LEDC_SCLK configuration register + 0x38 + 0x20 + 0x00400000 + + + LEDC_SCLK_SEL + set this field to select clock-source. 0(default): do not select anyone clock, 1: 80MHz, 2: FOSC, 3: XTAL. + 20 + 2 + read-write + + + LEDC_SCLK_EN + Set 1 to enable ledc function clock + 22 + 1 + read-write + + + + + TIMERGROUP0_CONF + TIMERGROUP0 configuration register + 0x3C + 0x20 + 0x00000001 + + + TG0_CLK_EN + Set 1 to enable timer_group0 apb clock + 0 + 1 + read-write + + + TG0_RST_EN + Set 0 to reset timer_group0 module + 1 + 1 + read-write + + + + + TIMERGROUP0_TIMER_CLK_CONF + TIMERGROUP0_TIMER_CLK configuration register + 0x40 + 0x20 + 0x00400000 + + + TG0_TIMER_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG0_TIMER_CLK_EN + Set 1 to enable timer_group0 timer clock + 22 + 1 + read-write + + + + + TIMERGROUP0_WDT_CLK_CONF + TIMERGROUP0_WDT_CLK configuration register + 0x44 + 0x20 + 0x00400000 + + + TG0_WDT_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG0_WDT_CLK_EN + Set 1 to enable timer_group0 wdt clock + 22 + 1 + read-write + + + + + TIMERGROUP1_CONF + TIMERGROUP1 configuration register + 0x48 + 0x20 + 0x00000001 + + + TG1_CLK_EN + Set 1 to enable timer_group1 apb clock + 0 + 1 + read-write + + + TG1_RST_EN + Set 0 to reset timer_group1 module + 1 + 1 + read-write + + + + + TIMERGROUP1_TIMER_CLK_CONF + TIMERGROUP1_TIMER_CLK configuration register + 0x4C + 0x20 + 0x00400000 + + + TG1_TIMER_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG1_TIMER_CLK_EN + Set 1 to enable timer_group1 timer clock + 22 + 1 + read-write + + + + + TIMERGROUP1_WDT_CLK_CONF + TIMERGROUP1_WDT_CLK configuration register + 0x50 + 0x20 + 0x00400000 + + + TG1_WDT_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG1_WDT_CLK_EN + Set 1 to enable timer_group0 wdt clock + 22 + 1 + read-write + + + + + SYSTIMER_CONF + SYSTIMER configuration register + 0x54 + 0x20 + 0x00000001 + + + SYSTIMER_CLK_EN + Set 1 to enable systimer apb clock + 0 + 1 + read-write + + + SYSTIMER_RST_EN + Set 0 to reset systimer module + 1 + 1 + read-write + + + + + SYSTIMER_FUNC_CLK_CONF + SYSTIMER_FUNC_CLK configuration register + 0x58 + 0x20 + 0x00400000 + + + SYSTIMER_FUNC_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + SYSTIMER_FUNC_CLK_EN + Set 1 to enable systimer function clock + 22 + 1 + read-write + + + + + TWAI0_CONF + TWAI0 configuration register + 0x5C + 0x20 + 0x00000001 + + + TWAI0_CLK_EN + Set 1 to enable twai0 apb clock + 0 + 1 + read-write + + + TWAI0_RST_EN + Set 0 to reset twai0 module + 1 + 1 + read-write + + + + + TWAI0_FUNC_CLK_CONF + TWAI0_FUNC_CLK configuration register + 0x60 + 0x20 + 0x00400000 + + + TWAI0_FUNC_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + TWAI0_FUNC_CLK_EN + Set 1 to enable twai0 function clock + 22 + 1 + read-write + + + + + TWAI1_CONF + TWAI1 configuration register + 0x64 + 0x20 + 0x00000001 + + + TWAI1_CLK_EN + Set 1 to enable twai1 apb clock + 0 + 1 + read-write + + + TWAI1_RST_EN + Set 0 to reset twai1 module + 1 + 1 + read-write + + + + + TWAI1_FUNC_CLK_CONF + TWAI1_FUNC_CLK configuration register + 0x68 + 0x20 + 0x00400000 + + + TWAI1_FUNC_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + TWAI1_FUNC_CLK_EN + Set 1 to enable twai1 function clock + 22 + 1 + read-write + + + + + I2S_CONF + I2S configuration register + 0x6C + 0x20 + 0x00000001 + + + I2S_CLK_EN + Set 1 to enable i2s apb clock + 0 + 1 + read-write + + + I2S_RST_EN + Set 0 to reset i2s module + 1 + 1 + read-write + + + + + I2S_TX_CLKM_CONF + I2S_TX_CLKM configuration register + 0x70 + 0x20 + 0x00402000 + + + I2S_TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 12 + 8 + read-write + + + I2S_TX_CLKM_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 20 + 2 + read-write + + + I2S_TX_CLKM_EN + Set 1 to enable i2s_tx function clock + 22 + 1 + read-write + + + + + I2S_TX_CLKM_DIV_CONF + I2S_TX_CLKM_DIV configuration register + 0x74 + 0x20 + 0x00000200 + + + I2S_TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + I2S_TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + I2S_TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + I2S_TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + I2S_RX_CLKM_CONF + I2S_RX_CLKM configuration register + 0x78 + 0x20 + 0x00402000 + + + I2S_RX_CLKM_DIV_NUM + Integral I2S clock divider value + 12 + 8 + read-write + + + I2S_RX_CLKM_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 20 + 2 + read-write + + + I2S_RX_CLKM_EN + Set 1 to enable i2s_rx function clock + 22 + 1 + read-write + + + I2S_MCLK_SEL + This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + 23 + 1 + read-write + + + + + I2S_RX_CLKM_DIV_CONF + I2S_RX_CLKM_DIV configuration register + 0x7C + 0x20 + 0x00000200 + + + I2S_RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + I2S_RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + I2S_RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + I2S_RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + SARADC_CONF + SARADC configuration register + 0x80 + 0x20 + 0x00000005 + + + SARADC_CLK_EN + no use + 0 + 1 + read-write + + + SARADC_RST_EN + Set 0 to reset function_register of saradc module + 1 + 1 + read-write + + + SARADC_REG_CLK_EN + Set 1 to enable saradc apb clock + 2 + 1 + read-write + + + SARADC_REG_RST_EN + Set 0 to reset apb_register of saradc module + 3 + 1 + read-write + + + + + SARADC_CLKM_CONF + SARADC_CLKM configuration register + 0x84 + 0x20 + 0x00404000 + + + SARADC_CLKM_DIV_A + The denominator of the frequency divider factor of the saradc function clock. + 0 + 6 + read-write + + + SARADC_CLKM_DIV_B + The numerator of the frequency divider factor of the saradc function clock. + 6 + 6 + read-write + + + SARADC_CLKM_DIV_NUM + The integral part of the frequency divider factor of the saradc function clock. + 12 + 8 + read-write + + + SARADC_CLKM_SEL + set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + SARADC_CLKM_EN + Set 1 to enable saradc function clock + 22 + 1 + read-write + + + + + TSENS_CLK_CONF + TSENS_CLK configuration register + 0x88 + 0x20 + 0x00400000 + + + TSENS_CLK_SEL + set this field to select clock-source. 0(default): FOSC, 1: XTAL. + 20 + 1 + read-write + + + TSENS_CLK_EN + Set 1 to enable tsens clock + 22 + 1 + read-write + + + TSENS_RST_EN + Set 0 to reset tsens module + 23 + 1 + read-write + + + + + USB_DEVICE_CONF + USB_DEVICE configuration register + 0x8C + 0x20 + 0x00000001 + + + USB_DEVICE_CLK_EN + Set 1 to enable usb_device clock + 0 + 1 + read-write + + + USB_DEVICE_RST_EN + Set 0 to reset usb_device module + 1 + 1 + read-write + + + + + INTMTX_CONF + INTMTX configuration register + 0x90 + 0x20 + 0x00000001 + + + INTMTX_CLK_EN + Set 1 to enable intmtx clock + 0 + 1 + read-write + + + INTMTX_RST_EN + Set 0 to reset intmtx module + 1 + 1 + read-write + + + + + PCNT_CONF + PCNT configuration register + 0x94 + 0x20 + 0x00000001 + + + PCNT_CLK_EN + Set 1 to enable pcnt clock + 0 + 1 + read-write + + + PCNT_RST_EN + Set 0 to reset pcnt module + 1 + 1 + read-write + + + + + ETM_CONF + ETM configuration register + 0x98 + 0x20 + 0x00000001 + + + ETM_CLK_EN + Set 1 to enable etm clock + 0 + 1 + read-write + + + ETM_RST_EN + Set 0 to reset etm module + 1 + 1 + read-write + + + + + PWM_CONF + PWM configuration register + 0x9C + 0x20 + 0x00000001 + + + PWM_CLK_EN + Set 1 to enable pwm clock + 0 + 1 + read-write + + + PWM_RST_EN + Set 0 to reset pwm module + 1 + 1 + read-write + + + + + PWM_CLK_CONF + PWM_CLK configuration register + 0xA0 + 0x20 + 0x00404000 + + + PWM_DIV_NUM + The integral part of the frequency divider factor of the pwm function clock. + 12 + 8 + read-write + + + PWM_CLKM_SEL + set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC. + 20 + 2 + read-write + + + PWM_CLKM_EN + set this field as 1 to activate pwm clkm. + 22 + 1 + read-write + + + + + PARL_IO_CONF + PARL_IO configuration register + 0xA4 + 0x20 + 0x00000001 + + + PARL_CLK_EN + Set 1 to enable parl apb clock + 0 + 1 + read-write + + + PARL_RST_EN + Set 0 to reset parl apb reg + 1 + 1 + read-write + + + + + PARL_CLK_RX_CONF + PARL_CLK_RX configuration register + 0xA8 + 0x20 + 0x00040000 + + + PARL_CLK_RX_DIV_NUM + The integral part of the frequency divider factor of the parl rx clock. + 0 + 16 + read-write + + + PARL_CLK_RX_SEL + set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad. + 16 + 2 + read-write + + + PARL_CLK_RX_EN + Set 1 to enable parl rx clock + 18 + 1 + read-write + + + PARL_RX_RST_EN + Set 0 to reset parl rx module + 19 + 1 + read-write + + + + + PARL_CLK_TX_CONF + PARL_CLK_TX configuration register + 0xAC + 0x20 + 0x00040000 + + + PARL_CLK_TX_DIV_NUM + The integral part of the frequency divider factor of the parl tx clock. + 0 + 16 + read-write + + + PARL_CLK_TX_SEL + set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad. + 16 + 2 + read-write + + + PARL_CLK_TX_EN + Set 1 to enable parl tx clock + 18 + 1 + read-write + + + PARL_TX_RST_EN + Set 0 to reset parl tx module + 19 + 1 + read-write + + + + + SDIO_SLAVE_CONF + SDIO_SLAVE configuration register + 0xB0 + 0x20 + 0x00000001 + + + SDIO_SLAVE_CLK_EN + Set 1 to enable sdio_slave clock + 0 + 1 + read-write + + + SDIO_SLAVE_RST_EN + Set 0 to reset sdio_slave module + 1 + 1 + read-write + + + + + PVT_MONITOR_CONF + PVT_MONITOR configuration register + 0xB4 + 0x20 + 0x0000001D + + + PVT_MONITOR_CLK_EN + Set 1 to enable apb clock of pvt module + 0 + 1 + read-write + + + PVT_MONITOR_RST_EN + Set 0 to reset all pvt monitor module + 1 + 1 + read-write + + + PVT_MONITOR_SITE1_CLK_EN + Set 1 to enable function clock of modem pvt module + 2 + 1 + read-write + + + PVT_MONITOR_SITE2_CLK_EN + Set 1 to enable function clock of cpu pvt module + 3 + 1 + read-write + + + PVT_MONITOR_SITE3_CLK_EN + Set 1 to enable function clock of hp_peri pvt module + 4 + 1 + read-write + + + + + PVT_MONITOR_FUNC_CLK_CONF + PVT_MONITOR function clock configuration register + 0xB8 + 0x20 + 0x00400000 + + + PVT_MONITOR_FUNC_CLK_DIV_NUM + The integral part of the frequency divider factor of the pvt_monitor function clock. + 0 + 4 + read-write + + + PVT_MONITOR_FUNC_CLK_SEL + set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL divided by 3. + 20 + 1 + read-write + + + PVT_MONITOR_FUNC_CLK_EN + Set 1 to enable source clock of pvt sitex + 22 + 1 + read-write + + + + + GDMA_CONF + GDMA configuration register + 0xBC + 0x20 + 0x00000001 + + + GDMA_CLK_EN + Set 1 to enable gdma clock + 0 + 1 + read-write + + + GDMA_RST_EN + Set 0 to reset gdma module + 1 + 1 + read-write + + + + + SPI2_CONF + SPI2 configuration register + 0xC0 + 0x20 + 0x00000001 + + + SPI2_CLK_EN + Set 1 to enable spi2 apb clock + 0 + 1 + read-write + + + SPI2_RST_EN + Set 0 to reset spi2 module + 1 + 1 + read-write + + + + + SPI2_CLKM_CONF + SPI2_CLKM configuration register + 0xC4 + 0x20 + 0x00400000 + + + SPI2_CLKM_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + SPI2_CLKM_EN + Set 1 to enable spi2 function clock + 22 + 1 + read-write + + + + + AES_CONF + AES configuration register + 0xC8 + 0x20 + 0x00000001 + + + AES_CLK_EN + Set 1 to enable aes clock + 0 + 1 + read-write + + + AES_RST_EN + Set 0 to reset aes module + 1 + 1 + read-write + + + + + SHA_CONF + SHA configuration register + 0xCC + 0x20 + 0x00000001 + + + SHA_CLK_EN + Set 1 to enable sha clock + 0 + 1 + read-write + + + SHA_RST_EN + Set 0 to reset sha module + 1 + 1 + read-write + + + + + RSA_CONF + RSA configuration register + 0xD0 + 0x20 + 0x00000001 + + + RSA_CLK_EN + Set 1 to enable rsa clock + 0 + 1 + read-write + + + RSA_RST_EN + Set 0 to reset rsa module + 1 + 1 + read-write + + + + + RSA_PD_CTRL + RSA power control register + 0xD4 + 0x20 + 0x00000002 + + + RSA_MEM_PD + Set this bit to power down rsa internal memory. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set this bit to force power up rsa internal memory + 1 + 1 + read-write + + + RSA_MEM_FORCE_PD + Set this bit to force power down rsa internal memory. + 2 + 1 + read-write + + + + + ECC_CONF + ECC configuration register + 0xD8 + 0x20 + 0x00000001 + + + ECC_CLK_EN + Set 1 to enable ecc clock + 0 + 1 + read-write + + + ECC_RST_EN + Set 0 to reset ecc module + 1 + 1 + read-write + + + + + ECC_PD_CTRL + ECC power control register + 0xDC + 0x20 + 0x00000002 + + + ECC_MEM_PD + Set this bit to power down ecc internal memory. + 0 + 1 + read-write + + + ECC_MEM_FORCE_PU + Set this bit to force power up ecc internal memory + 1 + 1 + read-write + + + ECC_MEM_FORCE_PD + Set this bit to force power down ecc internal memory. + 2 + 1 + read-write + + + + + DS_CONF + DS configuration register + 0xE0 + 0x20 + 0x00000001 + + + DS_CLK_EN + Set 1 to enable ds clock + 0 + 1 + read-write + + + DS_RST_EN + Set 0 to reset ds module + 1 + 1 + read-write + + + + + HMAC_CONF + HMAC configuration register + 0xE4 + 0x20 + 0x00000001 + + + HMAC_CLK_EN + Set 1 to enable hmac clock + 0 + 1 + read-write + + + HMAC_RST_EN + Set 0 to reset hmac module + 1 + 1 + read-write + + + + + IOMUX_CONF + IOMUX configuration register + 0xE8 + 0x20 + 0x00000001 + + + IOMUX_CLK_EN + Set 1 to enable iomux apb clock + 0 + 1 + read-write + + + IOMUX_RST_EN + Set 0 to reset iomux module + 1 + 1 + read-write + + + + + IOMUX_CLK_CONF + IOMUX_CLK configuration register + 0xEC + 0x20 + 0x00700000 + + + IOMUX_FUNC_CLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL. + 20 + 2 + read-write + + + IOMUX_FUNC_CLK_EN + Set 1 to enable iomux function clock + 22 + 1 + read-write + + + + + MEM_MONITOR_CONF + MEM_MONITOR configuration register + 0xF0 + 0x20 + 0x00000001 + + + MEM_MONITOR_CLK_EN + Set 1 to enable mem_monitor clock + 0 + 1 + read-write + + + MEM_MONITOR_RST_EN + Set 0 to reset mem_monitor module + 1 + 1 + read-write + + + + + REGDMA_CONF + REGDMA configuration register + 0xF4 + 0x20 + + + REGDMA_CLK_EN + Set 1 to enable regdma clock + 0 + 1 + read-write + + + REGDMA_RST_EN + Set 0 to reset regdma module + 1 + 1 + read-write + + + + + RETENTION_CONF + retention configuration register + 0xF8 + 0x20 + + + RETENTION_CLK_EN + Set 1 to enable retention clock + 0 + 1 + read-write + + + RETENTION_RST_EN + Set 0 to reset retention module + 1 + 1 + read-write + + + + + TRACE_CONF + TRACE configuration register + 0xFC + 0x20 + 0x00000001 + + + TRACE_CLK_EN + Set 1 to enable trace clock + 0 + 1 + read-write + + + TRACE_RST_EN + Set 0 to reset trace module + 1 + 1 + read-write + + + + + ASSIST_CONF + ASSIST configuration register + 0x100 + 0x20 + 0x00000001 + + + ASSIST_CLK_EN + Set 1 to enable assist clock + 0 + 1 + read-write + + + ASSIST_RST_EN + Set 0 to reset assist module + 1 + 1 + read-write + + + + + CACHE_CONF + CACHE configuration register + 0x104 + 0x20 + 0x00000001 + + + CACHE_CLK_EN + Set 1 to enable cache clock + 0 + 1 + read-write + + + CACHE_RST_EN + Set 0 to reset cache module + 1 + 1 + read-write + + + + + MODEM_APB_CONF + MODEM_APB configuration register + 0x108 + 0x20 + 0x00000001 + + + MODEM_APB_CLK_EN + This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). + 0 + 1 + read-write + + + MODEM_RST_EN + Set this file as 1 to reset modem-subsystem. + 1 + 1 + read-write + + + + + TIMEOUT_CONF + TIMEOUT configuration register + 0x10C + 0x20 + + + CPU_TIMEOUT_RST_EN + Set 0 to reset cpu_peri timeout module + 1 + 1 + read-write + + + HP_TIMEOUT_RST_EN + Set 0 to reset hp_peri timeout module and hp_modem timeout module + 2 + 1 + read-write + + + + + SYSCLK_CONF + SYSCLK configuration register + 0x110 + 0x20 + 0x28000200 + + + LS_DIV_NUM + clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed clock-source such as XTAL/FOSC. + 0 + 8 + read-only + + + HS_DIV_NUM + clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + 8 + 8 + read-only + + + SOC_CLK_SEL + This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. + 16 + 2 + read-write + + + CLK_XTAL_FREQ + This field indicates the frequency(MHz) of XTAL. + 24 + 7 + read-only + + + + + CPU_WAITI_CONF + CPU_WAITI configuration register + 0x114 + 0x20 + 0x0000000D + + + CPUPERIOD_SEL + Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + 0 + 2 + read-only + + + PLL_FREQ_SEL + Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + 2 + 1 + read-only + + + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 3 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 4 + 4 + read-write + + + + + CPU_FREQ_CONF + CPU_FREQ configuration register + 0x118 + 0x20 + + + CPU_LS_DIV_NUM + Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM. + 0 + 8 + read-write + + + CPU_HS_DIV_NUM + Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM. + 8 + 8 + read-write + + + CPU_HS_120M_FORCE + Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. + 16 + 1 + read-write + + + + + AHB_FREQ_CONF + AHB_FREQ configuration register + 0x11C + 0x20 + 0x00000300 + + + AHB_LS_DIV_NUM + Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_CPU_LS_DIV_NUM. + 0 + 8 + read-write + + + AHB_HS_DIV_NUM + Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM. + 8 + 8 + read-write + + + + + APB_FREQ_CONF + APB_FREQ configuration register + 0x120 + 0x20 + + + APB_DECREASE_DIV_NUM + If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be automatically down to clk_apb_decrease only when no access is on apb-bus, and will recover to the previous frequency when a new access appears on apb-bus. Set as one within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note that enable this function will reduce performance. Users can set this field as zero to disable the auto-decrease-apb-freq function. By default, this function is disable. + 0 + 8 + read-write + + + APB_DIV_NUM + Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is div1(default)/div2/div4 of clk_ahb. + 8 + 8 + read-write + + + + + SYSCLK_FREQ_QUERY_0 + SYSCLK frequency query 0 register + 0x124 + 0x20 + 0x0001E014 + + + FOSC_FREQ + This field indicates the frequency(MHz) of FOSC. + 0 + 8 + read-only + + + PLL_FREQ + This field indicates the frequency(MHz) of SPLL. + 8 + 10 + read-only + + + + + PLL_DIV_CLK_EN + SPLL DIV clock-gating configuration register + 0x128 + 0x20 + 0x0000007F + + + PLL_240M_CLK_EN + This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 0 + 1 + read-write + + + PLL_160M_CLK_EN + This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 1 + 1 + read-write + + + PLL_120M_CLK_EN + This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 2 + 1 + read-write + + + PLL_80M_CLK_EN + This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 3 + 1 + read-write + + + PLL_48M_CLK_EN + This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 4 + 1 + read-write + + + PLL_40M_CLK_EN + This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 5 + 1 + read-write + + + PLL_20M_CLK_EN + This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 6 + 1 + read-write + + + + + CTRL_CLK_OUT_EN + CLK_OUT_EN configuration register + 0x12C + 0x20 + 0x000007FF + + + CLK20_OEN + Set 1 to enable 20m clock + 0 + 1 + read-write + + + CLK22_OEN + Set 1 to enable 22m clock + 1 + 1 + read-write + + + CLK44_OEN + Set 1 to enable 44m clock + 2 + 1 + read-write + + + CLK_BB_OEN + Set 1 to enable bb clock + 3 + 1 + read-write + + + CLK80_OEN + Set 1 to enable 80m clock + 4 + 1 + read-write + + + CLK160_OEN + Set 1 to enable 160m clock + 5 + 1 + read-write + + + CLK_320M_OEN + Set 1 to enable 320m clock + 6 + 1 + read-write + + + CLK_ADC_INF_OEN + Reserved + 7 + 1 + read-write + + + CLK_DAC_CPU_OEN + Reserved + 8 + 1 + read-write + + + CLK40X_BB_OEN + Set 1 to enable 40x_bb clock + 9 + 1 + read-write + + + CLK_XTAL_OEN + Set 1 to enable xtal clock + 10 + 1 + read-write + + + + + CTRL_TICK_CONF + TICK configuration register + 0x130 + 0x20 + 0x00010727 + + + XTAL_TICK_NUM + ******* Description *********** + 0 + 8 + read-write + + + FOSC_TICK_NUM + ******* Description *********** + 8 + 8 + read-write + + + TICK_ENABLE + ******* Description *********** + 16 + 1 + read-write + + + RST_TICK_CNT + ******* Description *********** + 17 + 1 + read-write + + + + + CTRL_32K_CONF + 32KHz clock configuration register + 0x134 + 0x20 + + + CLK_32K_SEL + This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + 0 + 2 + read-write + + + + + SRAM_POWER_CONF + HP SRAM/ROM configuration register + 0x138 + 0x20 + 0x0000700F + + + SRAM_FORCE_PU + Set this bit to force power up SRAM + 0 + 4 + read-write + + + SRAM_FORCE_PD + Set this bit to force power down SRAM. + 4 + 4 + read-write + + + SRAM_CLKGATE_FORCE_ON + 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A gate-clock will be used when accessing the SRAM. + 8 + 4 + read-write + + + ROM_FORCE_PU + Set this bit to force power up ROM + 12 + 3 + read-write + + + ROM_FORCE_PD + Set this bit to force power down ROM. + 15 + 3 + read-write + + + ROM_CLKGATE_FORCE_ON + 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A gate-clock will be used when accessing the ROM. + 18 + 3 + read-write + + + + + RESET_EVENT_BYPASS + reset event bypass backdoor configuration register + 0xFF0 + 0x20 + 0x00000002 + + + APM + This field is used to control reset event relationship for tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, but also some reset event. + 0 + 1 + read-write + + + RESET_EVENT_BYPASS + This field is used to control reset event relationship for system-bus. 1: system bus (including arbiter/router) will only be reset by power-reset. some reset event will be bypass. 0: system bus (including arbiter/router) will not only be reset by power-reset, but also some reset event. + 1 + 1 + read-write + + + + + FPGA_DEBUG + fpga debug register + 0xFF4 + 0x20 + 0xFFFFFFFF + + + FPGA_DEBUG + Only used in fpga debug. + 0 + 32 + read-write + + + + + CLOCK_GATE + PCR clock gating configure register + 0xFF8 + 0x20 + + + CLK_EN + Set this bit as 1 to force on clock gating. + 0 + 1 + read-write + + + + + DATE + Date register. + 0xFFC + 0x20 + 0x02206150 + + + DATE + PCR version information. + 0 + 28 + read-write + + + + + + + PMU + PMU Peripheral + PMU + 0x600B0000 + + 0x0 + 0x1A8 + registers + + + PMU + 13 + + + + HP_ACTIVE_DIG_POWER + need_des + 0x0 + 0x20 + + + HP_ACTIVE_VDD_SPI_PD_EN + need_des + 21 + 1 + read-write + + + HP_ACTIVE_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_ACTIVE_PD_HP_MEM_PD_EN + need_des + 23 + 4 + read-write + + + HP_ACTIVE_PD_HP_WIFI_PD_EN + need_des + 27 + 1 + read-write + + + HP_ACTIVE_PD_HP_CPU_PD_EN + need_des + 29 + 1 + read-write + + + HP_ACTIVE_PD_HP_AON_PD_EN + need_des + 30 + 1 + read-write + + + HP_ACTIVE_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_ICG_HP_FUNC + need_des + 0x4 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_HP_APB + need_des + 0x8 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_MODEM + need_des + 0xC + 0x20 + + + HP_ACTIVE_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_SYS_CNTL + need_des + 0x10 + 0x20 + + + HP_ACTIVE_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_ACTIVE_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_ACTIVE_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_ACTIVE_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_ACTIVE_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_ACTIVE_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_ACTIVE_HP_CK_POWER + need_des + 0x14 + 0x20 + + + HP_ACTIVE_I2C_ISO_EN + need_des + 26 + 1 + read-write + + + HP_ACTIVE_I2C_RETENTION + need_des + 27 + 1 + read-write + + + HP_ACTIVE_XPD_BB_I2C + need_des + 28 + 1 + read-write + + + HP_ACTIVE_XPD_BBPLL_I2C + need_des + 29 + 1 + read-write + + + HP_ACTIVE_XPD_BBPLL + need_des + 30 + 1 + read-write + + + + + HP_ACTIVE_BIAS + need_des + 0x18 + 0x20 + + + HP_ACTIVE_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_ACTIVE_DBG_ATTEN + need_des + 26 + 4 + read-write + + + HP_ACTIVE_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_BACKUP + need_des + 0x1C + 0x20 + + + HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_SLEEP2ACTIVE_RETENTION_EN + need_des + 11 + 1 + read-write + + + HP_MODEM2ACTIVE_RETENTION_EN + need_des + 12 + 1 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_CLK_SEL + need_des + 14 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_CLK_SEL + need_des + 16 + 2 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_MODE + need_des + 20 + 3 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODE + need_des + 23 + 3 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_EN + need_des + 29 + 1 + read-write + + + HP_MODEM2ACTIVE_BACKUP_EN + need_des + 30 + 1 + read-write + + + + + HP_ACTIVE_BACKUP_CLK + need_des + 0x20 + 0x20 + + + HP_ACTIVE_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_SYSCLK + need_des + 0x24 + 0x20 + + + HP_ACTIVE_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_ACTIVE_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_ACTIVE_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_ACTIVE_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_ACTIVE_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_REGULATOR0 + need_des + 0x28 + 0x20 + 0xC6677180 + + + LP_DBIAS_VOL + need_des + 4 + 5 + read-only + + + HP_DBIAS_VOL + need_des + 9 + 5 + read-only + + + DIG_REGULATOR0_DBIAS_SEL + need_des + 14 + 1 + read-write + + + DIG_DBIAS_INIT + need_des + 15 + 1 + write-only + + + HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_ACTIVE_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_ACTIVE_HP_REGULATOR1 + need_des + 0x2C + 0x20 + + + HP_ACTIVE_HP_REGULATOR_DRV_B + need_des + 8 + 24 + read-write + + + + + HP_ACTIVE_XTAL + need_des + 0x30 + 0x20 + 0x80000000 + + + HP_ACTIVE_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_MODEM_DIG_POWER + need_des + 0x34 + 0x20 + + + HP_MODEM_VDD_SPI_PD_EN + need_des + 21 + 1 + read-write + + + HP_MODEM_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_MODEM_PD_HP_MEM_PD_EN + need_des + 23 + 4 + read-write + + + HP_MODEM_PD_HP_WIFI_PD_EN + need_des + 27 + 1 + read-write + + + HP_MODEM_PD_HP_CPU_PD_EN + need_des + 29 + 1 + read-write + + + HP_MODEM_PD_HP_AON_PD_EN + need_des + 30 + 1 + read-write + + + HP_MODEM_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_MODEM_ICG_HP_FUNC + need_des + 0x38 + 0x20 + 0xFFFFFFFF + + + HP_MODEM_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_MODEM_ICG_HP_APB + need_des + 0x3C + 0x20 + 0xFFFFFFFF + + + HP_MODEM_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_MODEM_ICG_MODEM + need_des + 0x40 + 0x20 + + + HP_MODEM_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_MODEM_HP_SYS_CNTL + need_des + 0x44 + 0x20 + + + HP_MODEM_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_MODEM_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_MODEM_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_MODEM_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_MODEM_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_MODEM_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_MODEM_HP_CK_POWER + need_des + 0x48 + 0x20 + + + HP_MODEM_I2C_ISO_EN + need_des + 26 + 1 + read-write + + + HP_MODEM_I2C_RETENTION + need_des + 27 + 1 + read-write + + + HP_MODEM_XPD_BB_I2C + need_des + 28 + 1 + read-write + + + HP_MODEM_XPD_BBPLL_I2C + need_des + 29 + 1 + read-write + + + HP_MODEM_XPD_BBPLL + need_des + 30 + 1 + read-write + + + + + HP_MODEM_BIAS + need_des + 0x4C + 0x20 + + + HP_MODEM_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_MODEM_DBG_ATTEN + need_des + 26 + 4 + read-write + + + HP_MODEM_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_MODEM_BACKUP + need_des + 0x50 + 0x20 + + + HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + read-write + + + HP_MODEM_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_SLEEP2MODEM_RETENTION_EN + need_des + 11 + 1 + read-write + + + HP_SLEEP2MODEM_BACKUP_CLK_SEL + need_des + 14 + 2 + read-write + + + HP_SLEEP2MODEM_BACKUP_MODE + need_des + 20 + 3 + read-write + + + HP_SLEEP2MODEM_BACKUP_EN + need_des + 29 + 1 + read-write + + + + + HP_MODEM_BACKUP_CLK + need_des + 0x54 + 0x20 + + + HP_MODEM_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_MODEM_SYSCLK + need_des + 0x58 + 0x20 + + + HP_MODEM_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_MODEM_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_MODEM_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_MODEM_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_MODEM_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_MODEM_HP_REGULATOR0 + need_des + 0x5C + 0x20 + 0xC6670000 + + + HP_MODEM_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_MODEM_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_MODEM_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_MODEM_HP_REGULATOR1 + need_des + 0x60 + 0x20 + + + HP_MODEM_HP_REGULATOR_DRV_B + need_des + 8 + 24 + read-write + + + + + HP_MODEM_XTAL + need_des + 0x64 + 0x20 + 0x80000000 + + + HP_MODEM_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_DIG_POWER + need_des + 0x68 + 0x20 + + + HP_SLEEP_VDD_SPI_PD_EN + need_des + 21 + 1 + read-write + + + HP_SLEEP_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_SLEEP_PD_HP_MEM_PD_EN + need_des + 23 + 4 + read-write + + + HP_SLEEP_PD_HP_WIFI_PD_EN + need_des + 27 + 1 + read-write + + + HP_SLEEP_PD_HP_CPU_PD_EN + need_des + 29 + 1 + read-write + + + HP_SLEEP_PD_HP_AON_PD_EN + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_ICG_HP_FUNC + need_des + 0x6C + 0x20 + 0xFFFFFFFF + + + HP_SLEEP_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_ICG_HP_APB + need_des + 0x70 + 0x20 + 0xFFFFFFFF + + + HP_SLEEP_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_ICG_MODEM + need_des + 0x74 + 0x20 + + + HP_SLEEP_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_SLEEP_HP_SYS_CNTL + need_des + 0x78 + 0x20 + + + HP_SLEEP_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_SLEEP_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_SLEEP_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_SLEEP_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_SLEEP_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_SLEEP_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_SLEEP_HP_CK_POWER + need_des + 0x7C + 0x20 + + + HP_SLEEP_I2C_ISO_EN + need_des + 26 + 1 + read-write + + + HP_SLEEP_I2C_RETENTION + need_des + 27 + 1 + read-write + + + HP_SLEEP_XPD_BB_I2C + need_des + 28 + 1 + read-write + + + HP_SLEEP_XPD_BBPLL_I2C + need_des + 29 + 1 + read-write + + + HP_SLEEP_XPD_BBPLL + need_des + 30 + 1 + read-write + + + + + HP_SLEEP_BIAS + need_des + 0x80 + 0x20 + + + HP_SLEEP_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_SLEEP_DBG_ATTEN + need_des + 26 + 4 + read-write + + + HP_SLEEP_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_BACKUP + need_des + 0x84 + 0x20 + + + HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE + need_des + 8 + 2 + read-write + + + HP_SLEEP_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_MODEM2SLEEP_RETENTION_EN + need_des + 12 + 1 + read-write + + + HP_ACTIVE2SLEEP_RETENTION_EN + need_des + 13 + 1 + read-write + + + HP_MODEM2SLEEP_BACKUP_CLK_SEL + need_des + 16 + 2 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_CLK_SEL + need_des + 18 + 2 + read-write + + + HP_MODEM2SLEEP_BACKUP_MODE + need_des + 23 + 3 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_MODE + need_des + 26 + 3 + read-write + + + HP_MODEM2SLEEP_BACKUP_EN + need_des + 30 + 1 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_BACKUP_CLK + need_des + 0x88 + 0x20 + + + HP_SLEEP_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_SYSCLK + need_des + 0x8C + 0x20 + + + HP_SLEEP_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_SLEEP_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_SLEEP_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_SLEEP_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_SLEEP_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_SLEEP_HP_REGULATOR0 + need_des + 0x90 + 0x20 + 0xC6670000 + + + HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_SLEEP_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_SLEEP_HP_REGULATOR1 + need_des + 0x94 + 0x20 + + + HP_SLEEP_HP_REGULATOR_DRV_B + need_des + 8 + 24 + read-write + + + + + HP_SLEEP_XTAL + need_des + 0x98 + 0x20 + 0x80000000 + + + HP_SLEEP_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_LP_REGULATOR0 + need_des + 0x9C + 0x20 + 0xC6600000 + + + HP_SLEEP_LP_REGULATOR_SLP_XPD + need_des + 21 + 1 + read-write + + + HP_SLEEP_LP_REGULATOR_XPD + need_des + 22 + 1 + read-write + + + HP_SLEEP_LP_REGULATOR_SLP_DBIAS + need_des + 23 + 4 + read-write + + + HP_SLEEP_LP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_SLEEP_LP_REGULATOR1 + need_des + 0xA0 + 0x20 + + + HP_SLEEP_LP_REGULATOR_DRV_B + need_des + 28 + 4 + read-write + + + + + HP_SLEEP_LP_DCDC_RESERVE + need_des + 0xA4 + 0x20 + + + HP_SLEEP_LP_DCDC_RESERVE + need_des + 0 + 32 + write-only + + + + + HP_SLEEP_LP_DIG_POWER + need_des + 0xA8 + 0x20 + + + HP_SLEEP_LP_MEM_DSLP + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_LP_PERI_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_LP_CK_POWER + need_des + 0xAC + 0x20 + 0x40000000 + + + HP_SLEEP_XPD_XTAL32K + need_des + 28 + 1 + read-write + + + HP_SLEEP_XPD_RC32K + need_des + 29 + 1 + read-write + + + HP_SLEEP_XPD_FOSC_CLK + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_OSC_CLK + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_BIAS_RESERVE + need_des + 0xB0 + 0x20 + + + LP_SLEEP_LP_BIAS_RESERVE + need_des + 0 + 32 + write-only + + + + + LP_SLEEP_LP_REGULATOR0 + need_des + 0xB4 + 0x20 + 0xC6600000 + + + LP_SLEEP_LP_REGULATOR_SLP_XPD + need_des + 21 + 1 + read-write + + + LP_SLEEP_LP_REGULATOR_XPD + need_des + 22 + 1 + read-write + + + LP_SLEEP_LP_REGULATOR_SLP_DBIAS + need_des + 23 + 4 + read-write + + + LP_SLEEP_LP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + LP_SLEEP_LP_REGULATOR1 + need_des + 0xB8 + 0x20 + + + LP_SLEEP_LP_REGULATOR_DRV_B + need_des + 28 + 4 + read-write + + + + + LP_SLEEP_XTAL + need_des + 0xBC + 0x20 + 0x80000000 + + + LP_SLEEP_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_DIG_POWER + need_des + 0xC0 + 0x20 + + + LP_SLEEP_LP_MEM_DSLP + need_des + 30 + 1 + read-write + + + LP_SLEEP_PD_LP_PERI_PD_EN + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_CK_POWER + need_des + 0xC4 + 0x20 + 0x40000000 + + + LP_SLEEP_XPD_XTAL32K + need_des + 28 + 1 + read-write + + + LP_SLEEP_XPD_RC32K + need_des + 29 + 1 + read-write + + + LP_SLEEP_XPD_FOSC_CLK + need_des + 30 + 1 + read-write + + + LP_SLEEP_PD_OSC_CLK + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_BIAS + need_des + 0xC8 + 0x20 + + + LP_SLEEP_XPD_BIAS + need_des + 25 + 1 + read-write + + + LP_SLEEP_DBG_ATTEN + need_des + 26 + 4 + read-write + + + LP_SLEEP_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + IMM_HP_CK_POWER + need_des + 0xCC + 0x20 + read-write + + + TIE_LOW_GLOBAL_BBPLL_ICG + need_des + 0 + 1 + write-only + + + TIE_LOW_GLOBAL_XTAL_ICG + need_des + 1 + 1 + write-only + + + TIE_LOW_I2C_RETENTION + need_des + 2 + 1 + write-only + + + TIE_LOW_XPD_BB_I2C + need_des + 3 + 1 + write-only + + + TIE_LOW_XPD_BBPLL_I2C + need_des + 4 + 1 + write-only + + + TIE_LOW_XPD_BBPLL + need_des + 5 + 1 + write-only + + + TIE_LOW_XPD_XTAL + need_des + 6 + 1 + write-only + + + TIE_HIGH_GLOBAL_BBPLL_ICG + need_des + 25 + 1 + write-only + + + TIE_HIGH_GLOBAL_XTAL_ICG + need_des + 26 + 1 + write-only + + + TIE_HIGH_I2C_RETENTION + need_des + 27 + 1 + write-only + + + TIE_HIGH_XPD_BB_I2C + need_des + 28 + 1 + write-only + + + TIE_HIGH_XPD_BBPLL_I2C + need_des + 29 + 1 + write-only + + + TIE_HIGH_XPD_BBPLL + need_des + 30 + 1 + write-only + + + TIE_HIGH_XPD_XTAL + need_des + 31 + 1 + write-only + + + + + IMM_SLEEP_SYSCLK + need_des + 0xD0 + 0x20 + + + UPDATE_DIG_ICG_SWITCH + need_des + 28 + 1 + write-only + + + TIE_LOW_ICG_SLP_SEL + need_des + 29 + 1 + write-only + + + TIE_HIGH_ICG_SLP_SEL + need_des + 30 + 1 + write-only + + + UPDATE_DIG_SYS_CLK_SEL + need_des + 31 + 1 + write-only + + + + + IMM_HP_FUNC_ICG + need_des + 0xD4 + 0x20 + + + UPDATE_DIG_ICG_FUNC_EN + need_des + 31 + 1 + write-only + + + + + IMM_HP_APB_ICG + need_des + 0xD8 + 0x20 + + + UPDATE_DIG_ICG_APB_EN + need_des + 31 + 1 + write-only + + + + + IMM_MODEM_ICG + need_des + 0xDC + 0x20 + + + UPDATE_DIG_ICG_MODEM_EN + need_des + 31 + 1 + write-only + + + + + IMM_LP_ICG + need_des + 0xE0 + 0x20 + + + TIE_LOW_LP_ROOTCLK_SEL + need_des + 30 + 1 + write-only + + + TIE_HIGH_LP_ROOTCLK_SEL + need_des + 31 + 1 + write-only + + + + + IMM_PAD_HOLD_ALL + need_des + 0xE4 + 0x20 + + + TIE_HIGH_LP_PAD_HOLD_ALL + need_des + 28 + 1 + write-only + + + TIE_LOW_LP_PAD_HOLD_ALL + need_des + 29 + 1 + write-only + + + TIE_HIGH_HP_PAD_HOLD_ALL + need_des + 30 + 1 + write-only + + + TIE_LOW_HP_PAD_HOLD_ALL + need_des + 31 + 1 + write-only + + + + + IMM_I2C_ISO + need_des + 0xE8 + 0x20 + + + TIE_HIGH_I2C_ISO_EN + need_des + 30 + 1 + write-only + + + TIE_LOW_I2C_ISO_EN + need_des + 31 + 1 + write-only + + + + + POWER_WAIT_TIMER0 + need_des + 0xEC + 0x20 + 0x7FBFDFE0 + + + DG_HP_POWERDOWN_TIMER + need_des + 5 + 9 + read-write + + + DG_HP_POWERUP_TIMER + need_des + 14 + 9 + read-write + + + DG_HP_WAIT_TIMER + need_des + 23 + 9 + read-write + + + + + POWER_WAIT_TIMER1 + need_des + 0xF0 + 0x20 + 0x7FFFFE00 + + + DG_LP_POWERDOWN_TIMER + need_des + 9 + 7 + read-write + + + DG_LP_POWERUP_TIMER + need_des + 16 + 7 + read-write + + + DG_LP_WAIT_TIMER + need_des + 23 + 9 + read-write + + + + + POWER_PD_TOP_CNTL + need_des + 0xF4 + 0x20 + 0x0000001C + + + FORCE_TOP_RESET + need_des + 0 + 1 + read-write + + + FORCE_TOP_ISO + need_des + 1 + 1 + read-write + + + FORCE_TOP_PU + need_des + 2 + 1 + read-write + + + FORCE_TOP_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_TOP_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_TOP_PD + need_des + 5 + 1 + read-write + + + PD_TOP_MASK + need_des + 6 + 5 + read-write + + + PD_TOP_PD_MASK + need_des + 27 + 5 + read-write + + + + + POWER_PD_HPAON_CNTL + need_des + 0xF8 + 0x20 + 0x0000001C + + + FORCE_HP_AON_RESET + need_des + 0 + 1 + read-write + + + FORCE_HP_AON_ISO + need_des + 1 + 1 + read-write + + + FORCE_HP_AON_PU + need_des + 2 + 1 + read-write + + + FORCE_HP_AON_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_HP_AON_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_HP_AON_PD + need_des + 5 + 1 + read-write + + + PD_HP_AON_MASK + need_des + 6 + 5 + read-write + + + PD_HP_AON_PD_MASK + need_des + 27 + 5 + read-write + + + + + POWER_PD_HPCPU_CNTL + need_des + 0xFC + 0x20 + 0x0000001C + + + FORCE_HP_CPU_RESET + need_des + 0 + 1 + read-write + + + FORCE_HP_CPU_ISO + need_des + 1 + 1 + read-write + + + FORCE_HP_CPU_PU + need_des + 2 + 1 + read-write + + + FORCE_HP_CPU_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_HP_CPU_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_HP_CPU_PD + need_des + 5 + 1 + read-write + + + PD_HP_CPU_MASK + need_des + 6 + 5 + read-write + + + PD_HP_CPU_PD_MASK + need_des + 27 + 5 + read-write + + + + + POWER_PD_HPPERI_RESERVE + need_des + 0x100 + 0x20 + + + HP_PERI_RESERVE + need_des + 0 + 32 + write-only + + + + + POWER_PD_HPWIFI_CNTL + need_des + 0x104 + 0x20 + 0x0000001C + + + FORCE_HP_WIFI_RESET + need_des + 0 + 1 + read-write + + + FORCE_HP_WIFI_ISO + need_des + 1 + 1 + read-write + + + FORCE_HP_WIFI_PU + need_des + 2 + 1 + read-write + + + FORCE_HP_WIFI_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_HP_WIFI_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_HP_WIFI_PD + need_des + 5 + 1 + read-write + + + PD_HP_WIFI_MASK + need_des + 6 + 5 + read-write + + + PD_HP_WIFI_PD_MASK + need_des + 27 + 5 + read-write + + + + + POWER_PD_LPPERI_CNTL + need_des + 0x108 + 0x20 + 0x0000001C + + + FORCE_LP_PERI_RESET + need_des + 0 + 1 + read-write + + + FORCE_LP_PERI_ISO + need_des + 1 + 1 + read-write + + + FORCE_LP_PERI_PU + need_des + 2 + 1 + read-write + + + FORCE_LP_PERI_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_LP_PERI_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_LP_PERI_PD + need_des + 5 + 1 + read-write + + + + + POWER_PD_MEM_CNTL + need_des + 0x10C + 0x20 + 0xFF000000 + + + FORCE_HP_MEM_ISO + need_des + 0 + 4 + read-write + + + FORCE_HP_MEM_PD + need_des + 4 + 4 + read-write + + + FORCE_HP_MEM_NO_ISO + need_des + 24 + 4 + read-write + + + FORCE_HP_MEM_PU + need_des + 28 + 4 + read-write + + + + + POWER_PD_MEM_MASK + need_des + 0x110 + 0x20 + + + PD_HP_MEM2_PD_MASK + need_des + 0 + 5 + read-write + + + PD_HP_MEM1_PD_MASK + need_des + 5 + 5 + read-write + + + PD_HP_MEM0_PD_MASK + need_des + 10 + 5 + read-write + + + PD_HP_MEM2_MASK + need_des + 17 + 5 + read-write + + + PD_HP_MEM1_MASK + need_des + 22 + 5 + read-write + + + PD_HP_MEM0_MASK + need_des + 27 + 5 + read-write + + + + + POWER_HP_PAD + need_des + 0x114 + 0x20 + + + FORCE_HP_PAD_NO_ISO_ALL + need_des + 0 + 1 + read-write + + + FORCE_HP_PAD_ISO_ALL + need_des + 1 + 1 + read-write + + + + + POWER_VDD_SPI_CNTL + need_des + 0x118 + 0x20 + 0x63FC0000 + + + VDD_SPI_PWR_WAIT + need_des + 18 + 11 + read-write + + + VDD_SPI_PWR_SW + need_des + 29 + 2 + read-write + + + VDD_SPI_PWR_SEL_SW + need_des + 31 + 1 + read-write + + + + + POWER_CK_WAIT_CNTL + need_des + 0x11C + 0x20 + 0x01000100 + + + WAIT_XTL_STABLE + need_des + 0 + 16 + read-write + + + WAIT_PLL_STABLE + need_des + 16 + 16 + read-write + + + + + SLP_WAKEUP_CNTL0 + need_des + 0x120 + 0x20 + + + SLEEP_REQ + need_des + 31 + 1 + write-only + + + + + SLP_WAKEUP_CNTL1 + need_des + 0x124 + 0x20 + + + SLEEP_REJECT_ENA + need_des + 0 + 31 + read-write + + + SLP_REJECT_EN + need_des + 31 + 1 + read-write + + + + + SLP_WAKEUP_CNTL2 + need_des + 0x128 + 0x20 + + + WAKEUP_ENA + need_des + 0 + 32 + read-write + + + + + SLP_WAKEUP_CNTL3 + need_des + 0x12C + 0x20 + + + LP_MIN_SLP_VAL + need_des + 0 + 8 + read-write + + + HP_MIN_SLP_VAL + need_des + 8 + 8 + read-write + + + SLEEP_PRT_SEL + need_des + 16 + 2 + read-write + + + + + SLP_WAKEUP_CNTL4 + need_des + 0x130 + 0x20 + + + SLP_REJECT_CAUSE_CLR + need_des + 31 + 1 + write-only + + + + + SLP_WAKEUP_CNTL5 + need_des + 0x134 + 0x20 + 0x01000080 + + + MODEM_WAIT_TARGET + need_des + 0 + 20 + read-write + + + LP_ANA_WAIT_TARGET + need_des + 24 + 8 + read-write + + + + + SLP_WAKEUP_CNTL6 + need_des + 0x138 + 0x20 + 0x00000080 + + + SOC_WAKEUP_WAIT + need_des + 0 + 20 + read-write + + + SOC_WAKEUP_WAIT_CFG + need_des + 30 + 2 + read-write + + + + + SLP_WAKEUP_CNTL7 + need_des + 0x13C + 0x20 + 0x00010000 + + + ANA_WAIT_TARGET + need_des + 16 + 16 + read-write + + + + + SLP_WAKEUP_STATUS0 + need_des + 0x140 + 0x20 + + + WAKEUP_CAUSE + need_des + 0 + 32 + read-only + + + + + SLP_WAKEUP_STATUS1 + need_des + 0x144 + 0x20 + + + REJECT_CAUSE + need_des + 0 + 32 + read-only + + + + + HP_CK_POWERON + need_des + 0x148 + 0x20 + 0x00000032 + + + I2C_POR_WAIT_TARGET + need_des + 0 + 8 + read-write + + + + + HP_CK_CNTL + need_des + 0x14C + 0x20 + 0x00000A0A + + + MODIFY_ICG_CNTL_WAIT + need_des + 0 + 8 + read-write + + + SWITCH_ICG_CNTL_WAIT + need_des + 8 + 8 + read-write + + + + + POR_STATUS + need_des + 0x150 + 0x20 + 0x80000000 + + + POR_DONE + need_des + 31 + 1 + read-only + + + + + RF_PWC + need_des + 0x154 + 0x20 + 0x08000000 + + + PERIF_I2C_RSTB + need_des + 26 + 1 + read-write + + + XPD_PERIF_I2C + need_des + 27 + 1 + read-write + + + XPD_TXRF_I2C + need_des + 28 + 1 + read-write + + + XPD_RFRX_PBUS + need_des + 29 + 1 + read-write + + + XPD_CKGEN_I2C + need_des + 30 + 1 + read-write + + + XPD_PLL_I2C + need_des + 31 + 1 + read-write + + + + + BACKUP_CFG + need_des + 0x158 + 0x20 + 0x80000000 + + + BACKUP_SYS_CLK_NO_DIV + need_des + 31 + 1 + read-write + + + + + INT_RAW + need_des + 0x15C + 0x20 + + + LP_CPU_EXC_INT_RAW + need_des + 27 + 1 + read-write + + + SDIO_IDLE_INT_RAW + need_des + 28 + 1 + read-write + + + SW_INT_RAW + need_des + 29 + 1 + read-write + + + SOC_SLEEP_REJECT_INT_RAW + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_RAW + need_des + 31 + 1 + read-write + + + + + HP_INT_ST + need_des + 0x160 + 0x20 + + + LP_CPU_EXC_INT_ST + need_des + 27 + 1 + read-only + + + SDIO_IDLE_INT_ST + need_des + 28 + 1 + read-only + + + SW_INT_ST + need_des + 29 + 1 + read-only + + + SOC_SLEEP_REJECT_INT_ST + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_ST + need_des + 31 + 1 + read-only + + + + + HP_INT_ENA + need_des + 0x164 + 0x20 + + + LP_CPU_EXC_INT_ENA + need_des + 27 + 1 + read-write + + + SDIO_IDLE_INT_ENA + need_des + 28 + 1 + read-write + + + SW_INT_ENA + need_des + 29 + 1 + read-write + + + SOC_SLEEP_REJECT_INT_ENA + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_ENA + need_des + 31 + 1 + read-write + + + + + HP_INT_CLR + need_des + 0x168 + 0x20 + + + LP_CPU_EXC_INT_CLR + need_des + 27 + 1 + write-only + + + SDIO_IDLE_INT_CLR + need_des + 28 + 1 + write-only + + + SW_INT_CLR + need_des + 29 + 1 + write-only + + + SOC_SLEEP_REJECT_INT_CLR + need_des + 30 + 1 + write-only + + + SOC_WAKEUP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x16C + 0x20 + + + LP_CPU_WAKEUP_INT_RAW + need_des + 20 + 1 + read-write + + + MODEM_SWITCH_ACTIVE_END_INT_RAW + need_des + 21 + 1 + read-write + + + SLEEP_SWITCH_ACTIVE_END_INT_RAW + need_des + 22 + 1 + read-write + + + SLEEP_SWITCH_MODEM_END_INT_RAW + need_des + 23 + 1 + read-write + + + MODEM_SWITCH_SLEEP_END_INT_RAW + need_des + 24 + 1 + read-write + + + ACTIVE_SWITCH_SLEEP_END_INT_RAW + need_des + 25 + 1 + read-write + + + MODEM_SWITCH_ACTIVE_START_INT_RAW + need_des + 26 + 1 + read-write + + + SLEEP_SWITCH_ACTIVE_START_INT_RAW + need_des + 27 + 1 + read-write + + + SLEEP_SWITCH_MODEM_START_INT_RAW + need_des + 28 + 1 + read-write + + + MODEM_SWITCH_SLEEP_START_INT_RAW + need_des + 29 + 1 + read-write + + + ACTIVE_SWITCH_SLEEP_START_INT_RAW + need_des + 30 + 1 + read-write + + + HP_SW_TRIGGER_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_INT_ST + need_des + 0x170 + 0x20 + + + LP_CPU_WAKEUP_INT_ST + need_des + 20 + 1 + read-only + + + MODEM_SWITCH_ACTIVE_END_INT_ST + need_des + 21 + 1 + read-only + + + SLEEP_SWITCH_ACTIVE_END_INT_ST + need_des + 22 + 1 + read-only + + + SLEEP_SWITCH_MODEM_END_INT_ST + need_des + 23 + 1 + read-only + + + MODEM_SWITCH_SLEEP_END_INT_ST + need_des + 24 + 1 + read-only + + + ACTIVE_SWITCH_SLEEP_END_INT_ST + need_des + 25 + 1 + read-only + + + MODEM_SWITCH_ACTIVE_START_INT_ST + need_des + 26 + 1 + read-only + + + SLEEP_SWITCH_ACTIVE_START_INT_ST + need_des + 27 + 1 + read-only + + + SLEEP_SWITCH_MODEM_START_INT_ST + need_des + 28 + 1 + read-only + + + MODEM_SWITCH_SLEEP_START_INT_ST + need_des + 29 + 1 + read-only + + + ACTIVE_SWITCH_SLEEP_START_INT_ST + need_des + 30 + 1 + read-only + + + HP_SW_TRIGGER_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x174 + 0x20 + + + LP_CPU_WAKEUP_INT_ENA + need_des + 20 + 1 + read-write + + + MODEM_SWITCH_ACTIVE_END_INT_ENA + need_des + 21 + 1 + read-write + + + SLEEP_SWITCH_ACTIVE_END_INT_ENA + need_des + 22 + 1 + read-write + + + SLEEP_SWITCH_MODEM_END_INT_ENA + need_des + 23 + 1 + read-write + + + MODEM_SWITCH_SLEEP_END_INT_ENA + need_des + 24 + 1 + read-write + + + ACTIVE_SWITCH_SLEEP_END_INT_ENA + need_des + 25 + 1 + read-write + + + MODEM_SWITCH_ACTIVE_START_INT_ENA + need_des + 26 + 1 + read-write + + + SLEEP_SWITCH_ACTIVE_START_INT_ENA + need_des + 27 + 1 + read-write + + + SLEEP_SWITCH_MODEM_START_INT_ENA + need_des + 28 + 1 + read-write + + + MODEM_SWITCH_SLEEP_START_INT_ENA + need_des + 29 + 1 + read-write + + + ACTIVE_SWITCH_SLEEP_START_INT_ENA + need_des + 30 + 1 + read-write + + + HP_SW_TRIGGER_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x178 + 0x20 + + + LP_CPU_WAKEUP_INT_CLR + need_des + 20 + 1 + write-only + + + MODEM_SWITCH_ACTIVE_END_INT_CLR + need_des + 21 + 1 + write-only + + + SLEEP_SWITCH_ACTIVE_END_INT_CLR + need_des + 22 + 1 + write-only + + + SLEEP_SWITCH_MODEM_END_INT_CLR + need_des + 23 + 1 + write-only + + + MODEM_SWITCH_SLEEP_END_INT_CLR + need_des + 24 + 1 + write-only + + + ACTIVE_SWITCH_SLEEP_END_INT_CLR + need_des + 25 + 1 + write-only + + + MODEM_SWITCH_ACTIVE_START_INT_CLR + need_des + 26 + 1 + write-only + + + SLEEP_SWITCH_ACTIVE_START_INT_CLR + need_des + 27 + 1 + write-only + + + SLEEP_SWITCH_MODEM_START_INT_CLR + need_des + 28 + 1 + write-only + + + MODEM_SWITCH_SLEEP_START_INT_CLR + need_des + 29 + 1 + write-only + + + ACTIVE_SWITCH_SLEEP_START_INT_CLR + need_des + 30 + 1 + write-only + + + HP_SW_TRIGGER_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_CPU_PWR0 + need_des + 0x17C + 0x20 + 0x1FF00000 + + + LP_CPU_WAITI_RDY + need_des + 0 + 1 + read-only + + + LP_CPU_STALL_RDY + need_des + 1 + 1 + read-only + + + LP_CPU_FORCE_STALL + need_des + 18 + 1 + read-write + + + LP_CPU_SLP_WAITI_FLAG_EN + need_des + 19 + 1 + read-write + + + LP_CPU_SLP_STALL_FLAG_EN + need_des + 20 + 1 + read-write + + + LP_CPU_SLP_STALL_WAIT + need_des + 21 + 8 + read-write + + + LP_CPU_SLP_STALL_EN + need_des + 29 + 1 + read-write + + + LP_CPU_SLP_RESET_EN + need_des + 30 + 1 + read-write + + + LP_CPU_SLP_BYPASS_INTR_EN + need_des + 31 + 1 + read-write + + + + + LP_CPU_PWR1 + need_des + 0x180 + 0x20 + + + LP_CPU_WAKEUP_EN + need_des + 0 + 16 + read-write + + + LP_CPU_SLEEP_REQ + need_des + 31 + 1 + write-only + + + + + HP_LP_CPU_COMM + need_des + 0x184 + 0x20 + + + LP_TRIGGER_HP + need_des + 30 + 1 + write-only + + + HP_TRIGGER_LP + need_des + 31 + 1 + write-only + + + + + HP_REGULATOR_CFG + need_des + 0x188 + 0x20 + + + DIG_REGULATOR_EN_CAL + need_des + 31 + 1 + read-write + + + + + MAIN_STATE + need_des + 0x18C + 0x20 + 0x08100800 + + + MAIN_LAST_ST_STATE + need_des + 11 + 7 + read-only + + + MAIN_TAR_ST_STATE + need_des + 18 + 7 + read-only + + + MAIN_CUR_ST_STATE + need_des + 25 + 7 + read-only + + + + + PWR_STATE + need_des + 0x190 + 0x20 + 0x00802000 + + + BACKUP_ST_STATE + need_des + 13 + 5 + read-only + + + LP_PWR_ST_STATE + need_des + 18 + 5 + read-only + + + HP_PWR_ST_STATE + need_des + 23 + 9 + read-only + + + + + CLK_STATE0 + need_des + 0x194 + 0x20 + 0x00000003 + + + STABLE_XPD_BBPLL_STATE + need_des + 0 + 1 + read-only + + + STABLE_XPD_XTAL_STATE + need_des + 1 + 1 + read-only + + + SYS_CLK_SLP_SEL_STATE + need_des + 15 + 1 + read-only + + + SYS_CLK_SEL_STATE + need_des + 16 + 2 + read-only + + + SYS_CLK_NO_DIV_STATE + need_des + 18 + 1 + read-only + + + ICG_SYS_CLK_EN_STATE + need_des + 19 + 1 + read-only + + + ICG_MODEM_SWITCH_STATE + need_des + 20 + 1 + read-only + + + ICG_MODEM_CODE_STATE + need_des + 21 + 2 + read-only + + + ICG_SLP_SEL_STATE + need_des + 23 + 1 + read-only + + + ICG_GLOBAL_XTAL_STATE + need_des + 24 + 1 + read-only + + + ICG_GLOBAL_PLL_STATE + need_des + 25 + 1 + read-only + + + ANA_I2C_ISO_EN_STATE + need_des + 26 + 1 + read-only + + + ANA_I2C_RETENTION_STATE + need_des + 27 + 1 + read-only + + + ANA_XPD_BB_I2C_STATE + need_des + 28 + 1 + read-only + + + ANA_XPD_BBPLL_I2C_STATE + need_des + 29 + 1 + read-only + + + ANA_XPD_BBPLL_STATE + need_des + 30 + 1 + read-only + + + ANA_XPD_XTAL_STATE + need_des + 31 + 1 + read-only + + + + + CLK_STATE1 + need_des + 0x198 + 0x20 + 0xFFFFFFFF + + + ICG_FUNC_EN_STATE + need_des + 0 + 32 + read-only + + + + + CLK_STATE2 + need_des + 0x19C + 0x20 + 0xFFFFFFFF + + + ICG_APB_EN_STATE + need_des + 0 + 32 + read-only + + + + + VDD_SPI_STATUS + need_des + 0x1A0 + 0x20 + + + STABLE_VDD_SPI_PWR_DRV + need_des + 31 + 1 + read-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02206250 + + + PMU_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + RMT + Remote Control + RMT + 0x60006000 + + 0x0 + 0x78 + registers + + + RMT + 49 + + + + 4 + 0x4 + CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + DATA + Read and write data for channel %s via APB FIFO. + 0 + 32 + read-write + + + + + 2 + 0x4 + CH%s_TX_CONF0 + Channel %s configure register 0 + 0x10 + 0x20 + 0x00710200 + + + TX_START + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + write-only + + + MEM_RD_RST + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 1 + 1 + write-only + + + APB_MEM_RST + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + TX_CONTI_MODE + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN + This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 4 + 1 + read-write + + + IDLE_OUT_LV + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 5 + 1 + read-write + + + IDLE_OUT_EN + This is the output enable-control bit for CHANNEL%s in IDLE state. + 6 + 1 + read-write + + + TX_STOP + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 7 + 1 + read-write + + + DIV_CNT + This register is used to configure the divider for clock of CHANNEL%s. + 8 + 8 + read-write + + + MEM_SIZE + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 16 + 3 + read-write + + + CARRIER_EFF_EN + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 20 + 1 + read-write + + + CARRIER_EN + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 21 + 1 + read-write + + + CARRIER_OUT_LV + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 22 + 1 + read-write + + + AFIFO_RST + Reserved + 23 + 1 + write-only + + + CONF_UPDATE + synchronization bit for CHANNEL%s + 24 + 1 + write-only + + + + + 2 + 0x8 + 2-3 + CH%s_RX_CONF0 + Channel %s configure register 0 + 0x18 + 0x20 + 0x30FFFF02 + + + DIV_CNT + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 15 + read-write + + + MEM_SIZE + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 23 + 3 + read-write + + + CARRIER_EN + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 2 + 0x8 + 2-3 + CH%s_RX_CONF1 + Channel %s configure register 1 + 0x1C + 0x20 + 0x000001E8 + + + RX_EN + Set this bit to enable receiver to receive data on CHANNEL%s. + 0 + 1 + read-write + + + MEM_WR_RST + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 1 + 1 + write-only + + + APB_MEM_RST + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + MEM_OWNER + This register marks the ownership of CHANNEL%s's ram block. + +1'h1: Receiver is using the ram. + +1'h0: APB bus is using the ram. + 3 + 1 + read-write + + + RX_FILTER_EN + This is the receive filter's enable bit for CHANNEL%s. + 4 + 1 + read-write + + + RX_FILTER_THRES + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 5 + 8 + read-write + + + MEM_RX_WRAP_EN + This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. + 13 + 1 + read-write + + + AFIFO_RST + Reserved + 14 + 1 + write-only + + + CONF_UPDATE + synchronization bit for CHANNEL%s + 15 + 1 + write-only + + + + + 2 + 0x4 + CH%s_TX_STATUS + Channel %s status register + 0x28 + 0x20 + + + MEM_RADDR_EX + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 0 + 9 + read-only + + + STATE + This register records the FSM status of CHANNEL%s. + 9 + 3 + read-only + + + APB_MEM_WADDR + This register records the memory address offset when writes RAM over APB bus. + 12 + 9 + read-only + + + APB_MEM_RD_ERR + This status bit will be set if the offset address out of memory size when reading via APB bus. + 21 + 1 + read-only + + + MEM_EMPTY + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 22 + 1 + read-only + + + APB_MEM_WR_ERR + This status bit will be set if the offset address out of memory size when writes via APB bus. + 23 + 1 + read-only + + + APB_MEM_RADDR + This register records the memory address offset when reading RAM over APB bus. + 24 + 8 + read-only + + + + + 2 + 0x4 + CH%s_RX_STATUS + Channel %s status register + 0x30 + 0x20 + + + MEM_WADDR_EX + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 9 + read-only + + + APB_MEM_RADDR + This register records the memory address offset when reads RAM over APB bus. + 12 + 9 + read-only + + + STATE + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_OWNER_ERR + This status bit will be set when the ownership of memory block is wrong. + 25 + 1 + read-only + + + MEM_FULL + This status bit will be set if the receiver receives more data than the memory size. + 26 + 1 + read-only + + + APB_MEM_RD_ERR + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0x38 + 0x20 + + + 2 + 0x1 + 0-1 + CH%s_TX_END + The interrupt raw bit for CHANNEL%s. Triggered when transmission done. + 0 + 1 + read-write + + + 2 + 0x1 + 2-3 + CH%s_RX_END + The interrupt raw bit for CHANNEL2. Triggered when reception done. + 2 + 1 + read-write + + + 2 + 0x1 + 0-1 + CH%s_TX_ERR + The interrupt raw bit for CHANNEL4. Triggered when error occurs. + 4 + 1 + read-write + + + 2 + 0x1 + 2-3 + CH%s_RX_ERR + The interrupt raw bit for CHANNEL6. Triggered when error occurs. + 6 + 1 + read-write + + + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT + The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. + 8 + 1 + read-write + + + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT + The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. + 10 + 1 + read-write + + + 2 + 0x1 + 0-1 + CH%s_TX_LOOP + The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. + 12 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x3C + 0x20 + + + 2 + 0x1 + 0-1 + CH%s_TX_END + The masked interrupt status bit for CH%s_TX_END_INT. + 0 + 1 + read-only + + + 2 + 0x1 + 2-3 + CH%s_RX_END + The masked interrupt status bit for CH2_RX_END_INT. + 2 + 1 + read-only + + + 2 + 0x1 + 0-1 + CH%s_TX_ERR + The masked interrupt status bit for CH4_ERR_INT. + 4 + 1 + read-only + + + 2 + 0x1 + 2-3 + CH%s_RX_ERR + The masked interrupt status bit for CH6_ERR_INT. + 6 + 1 + read-only + + + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT + The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. + 8 + 1 + read-only + + + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT + The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + 10 + 1 + read-only + + + 2 + 0x1 + 0-1 + CH%s_X_LOOP + The masked interrupt status bit for CH%s_TX_LOOP_INT. + 12 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x40 + 0x20 + + + 2 + 0x1 + 0-1 + CH%s_TX_END + The interrupt enable bit for CH%s_TX_END_INT. + 0 + 1 + read-write + + + 2 + 0x1 + 2-3 + CH%s_RX_END + The interrupt enable bit for CH2_RX_END_INT. + 2 + 1 + read-write + + + 2 + 0x1 + 0-1 + CH%s_TX_ERR + The interrupt enable bit for CH4_ERR_INT. + 4 + 1 + read-write + + + 2 + 0x1 + 2-3 + CH%s_RX_ERR + The interrupt enable bit for CH6_ERR_INT. + 6 + 1 + read-write + + + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT + The interrupt enable bit for CH%s_TX_THR_EVENT_INT. + 8 + 1 + read-write + + + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT + The interrupt enable bit for CH2_RX_THR_EVENT_INT. + 10 + 1 + read-write + + + 2 + 0x1 + 0-1 + CH%s_X_LOOP + The interrupt enable bit for CH%s_TX_LOOP_INT. + 12 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x44 + 0x20 + + + 2 + 0x1 + 0-1 + CH%s_TX_END + Set this bit to clear theCH%s_TX_END_INT interrupt. + 0 + 1 + write-only + + + 2 + 0x1 + 2-3 + CH%s_RX_END + Set this bit to clear theCH2_RX_END_INT interrupt. + 2 + 1 + write-only + + + 2 + 0x1 + 0-1 + CH%s_TX_ERR + Set this bit to clear theCH4_ERR_INT interrupt. + 4 + 1 + write-only + + + 2 + 0x1 + 2-3 + CH%s_RX_ERR + Set this bit to clear theCH6_ERR_INT interrupt. + 6 + 1 + write-only + + + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT + Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. + 8 + 1 + write-only + + + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT + Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + 10 + 1 + write-only + + + 2 + 0x1 + 0-1 + CH%s_TX_LOOP + Set this bit to clear theCH%s_TX_LOOP_INT interrupt. + 12 + 1 + write-only + + + + + 2 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x48 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 2 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x50 + 0x20 + + + CARRIER_LOW_THRES + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + 2 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0x58 + 0x20 + 0x00000080 + + + TX_LIM + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + LOOP_STOP_EN + This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + 21 + 1 + read-write + + + + + 2 + 0x4 + CH%s_RX_LIM + Channel %s Rx event configuration register + 0x60 + 0x20 + 0x00000080 + + + RMT_RX_LIM + This register is used to configure the maximum entries that CHANNEL%s can receive. + 0 + 9 + read-write + + + + + SYS_CONF + RMT apb configuration register + 0x68 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 1 + 1 + read-write + + + MEM_FORCE_PD + Set this bit to power down RMT memory. + 2 + 1 + read-write + + + MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 3 + 1 + read-write + + + SCLK_DIV_NUM + the integral part of the fractional divisor + 4 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor + 12 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor + 18 + 6 + read-write + + + SCLK_SEL + choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + 24 + 2 + read-write + + + SCLK_ACTIVE + rmt_sclk switch + 26 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0x6C + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 2 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0x70 + 0x20 + + + TX_REF_CNT_RST + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + write-only + + + TX_REF_CNT_RST_CH1 + This register is used to reset the clock divider of CHANNEL1. + 1 + 1 + write-only + + + RX_REF_CNT_RST_CH2 + This register is used to reset the clock divider of CHANNEL2. + 2 + 1 + write-only + + + RX_REF_CNT_RST_CH3 + This register is used to reset the clock divider of CHANNEL3. + 3 + 1 + write-only + + + + + DATE + RMT version register + 0xCC + 0x20 + 0x02108213 + + + RMT_DATE + This is the version register. + 0 + 28 + read-write + + + + + + + RNG + Hardware Random Number Generator + RNG + 0x600B2800 + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0x8 + 0x20 + read-only + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x6008A000 + + 0x0 + 0x74 + registers + + + RSA + 75 + + + + 384 + 0x1 + M_MEM[%s] + The memory that stores M + 0x0 + 0x8 + read-write + + + 384 + 0x1 + Z_MEM[%s] + The memory that stores Z + 0x200 + 0x8 + read-write + + + 384 + 0x1 + Y_MEM[%s] + The memory that stores Y + 0x400 + 0x8 + read-write + + + 384 + 0x1 + X_MEM[%s] + The memory that stores X + 0x600 + 0x8 + read-write + + + M_PRIME + RSA M_prime register + 0x800 + 0x20 + + + M_PRIME + Those bits stores m' + 0 + 32 + read-write + + + + + MODE + RSA mode register + 0x804 + 0x20 + + + MODE + rsa mode (rsa length). + 0 + 7 + read-write + + + + + QUERY_CLEAN + RSA query clean register + 0x808 + 0x20 + + + QUERY_CLEAN + query clean + 0 + 1 + read-only + + + + + SET_START_MODEXP + RSA modular exponentiation trigger register. + 0x80C + 0x20 + + + SET_START_MODEXP + start modular exponentiation + 0 + 1 + write-only + + + + + SET_START_MODMULT + RSA modular multiplication trigger register. + 0x810 + 0x20 + + + SET_START_MODMULT + start modular multiplication + 0 + 1 + write-only + + + + + SET_START_MULT + RSA normal multiplication trigger register. + 0x814 + 0x20 + + + SET_START_MULT + start multiplicaiton + 0 + 1 + write-only + + + + + QUERY_IDLE + RSA query idle register + 0x818 + 0x20 + + + QUERY_IDLE + query rsa idle. 1'b0: busy, 1'b1: idle + 0 + 1 + read-only + + + + + INT_CLR + RSA interrupt clear register + 0x81C + 0x20 + + + CLEAR_INTERRUPT + set this bit to clear RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + RSA constant time option register + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut). + 0 + 1 + read-write + + + + + SEARCH_ENABLE + RSA search option + 0x824 + 0x20 + + + SEARCH_ENABLE + Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS. + 0 + 1 + read-write + + + + + SEARCH_POS + RSA search position configure register + 0x828 + 0x20 + + + SEARCH_POS + Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high. + 0 + 12 + read-write + + + + + INT_ENA + RSA interrupt enable register + 0x82C + 0x20 + + + INT_ENA + Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default). + 0 + 1 + read-write + + + + + DATE + RSA version control register + 0x830 + 0x20 + 0x20200618 + + + DATE + rsa version information + 0 + 30 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x60089000 + + 0x0 + 0xB0 + registers + + + SHA + 74 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + Sha mode. + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + Sha t_string (used if and only if mode == SHA_512/t). + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + Sha t_length (used if and only if mode == SHA_512/t). + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + Dma-sha block number. + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + Reserved. + 1 + 31 + write-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + Reserved. + 1 + 31 + write-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + Sha busy state. 1'b0: idle. 1'b1: busy. + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + Start dma-sha. + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + Continue dma-sha. + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + Clear sha interrupt. + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20201229 + + + DATE + Sha date information/ sha version information. + 0 + 30 + read-write + + + + + 64 + 0x1 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x8 + + + 64 + 0x1 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x8 + + + + + SLCHOST + SLCHOST Peripheral + SLCHOST + 0x60017000 + + 0x0 + 0x104 + registers + + + SLC0 + 64 + + + SLC1 + 65 + + + + FUNC2_0 + *******Description*********** + 0x10 + 0x20 + + + SLC_FUNC2_INT + *******Description*********** + 24 + 1 + read-write + + + + + FUNC2_1 + *******Description*********** + 0x14 + 0x20 + + + SLC_FUNC2_INT_EN + *******Description*********** + 0 + 1 + read-write + + + + + FUNC2_2 + *******Description*********** + 0x20 + 0x20 + 0x00000001 + + + SLC_FUNC1_MDSTAT + *******Description*********** + 0 + 1 + read-write + + + + + GPIO_STATUS0 + *******Description*********** + 0x34 + 0x20 + + + GPIO_SDIO_INT0 + *******Description*********** + 0 + 32 + read-only + + + + + GPIO_STATUS1 + *******Description*********** + 0x38 + 0x20 + + + GPIO_SDIO_INT1 + *******Description*********** + 0 + 32 + read-only + + + + + GPIO_IN0 + *******Description*********** + 0x3C + 0x20 + + + GPIO_SDIO_IN0 + *******Description*********** + 0 + 32 + read-only + + + + + GPIO_IN1 + *******Description*********** + 0x40 + 0x20 + + + GPIO_SDIO_IN1 + *******Description*********** + 0 + 32 + read-only + + + + + SLC0HOST_TOKEN_RDATA + *******Description*********** + 0x44 + 0x20 + + + SLC0_TOKEN0 + *******Description*********** + 0 + 12 + read-only + + + SLC0_RX_PF_VALID + *******Description*********** + 12 + 1 + read-only + + + HOSTSLCHOST_SLC0_TOKEN1 + *******Description*********** + 16 + 12 + read-only + + + SLC0_RX_PF_EOF + *******Description*********** + 28 + 4 + read-only + + + + + SLC0_HOST_PF + *******Description*********** + 0x48 + 0x20 + + + SLC0_PF_DATA + *******Description*********** + 0 + 32 + read-only + + + + + SLC1_HOST_PF + *******Description*********** + 0x4C + 0x20 + + + SLC1_PF_DATA + *******Description*********** + 0 + 32 + read-only + + + + + SLC0HOST_INT_RAW + *******Description*********** + 0x50 + 0x20 + + + SLC0_TOHOST_BIT0_INT_RAW + *******Description*********** + 0 + 1 + read-write + + + SLC0_TOHOST_BIT1_INT_RAW + *******Description*********** + 1 + 1 + read-write + + + SLC0_TOHOST_BIT2_INT_RAW + *******Description*********** + 2 + 1 + read-write + + + SLC0_TOHOST_BIT3_INT_RAW + *******Description*********** + 3 + 1 + read-write + + + SLC0_TOHOST_BIT4_INT_RAW + *******Description*********** + 4 + 1 + read-write + + + SLC0_TOHOST_BIT5_INT_RAW + *******Description*********** + 5 + 1 + read-write + + + SLC0_TOHOST_BIT6_INT_RAW + *******Description*********** + 6 + 1 + read-write + + + SLC0_TOHOST_BIT7_INT_RAW + *******Description*********** + 7 + 1 + read-write + + + SLC0_TOKEN0_1TO0_INT_RAW + *******Description*********** + 8 + 1 + read-write + + + SLC0_TOKEN1_1TO0_INT_RAW + *******Description*********** + 9 + 1 + read-write + + + SLC0_TOKEN0_0TO1_INT_RAW + *******Description*********** + 10 + 1 + read-write + + + SLC0_TOKEN1_0TO1_INT_RAW + *******Description*********** + 11 + 1 + read-write + + + SLC0HOST_RX_SOF_INT_RAW + *******Description*********** + 12 + 1 + read-write + + + SLC0HOST_RX_EOF_INT_RAW + *******Description*********** + 13 + 1 + read-write + + + SLC0HOST_RX_START_INT_RAW + *******Description*********** + 14 + 1 + read-write + + + SLC0HOST_TX_START_INT_RAW + *******Description*********** + 15 + 1 + read-write + + + SLC0_RX_UDF_INT_RAW + *******Description*********** + 16 + 1 + read-write + + + SLC0_TX_OVF_INT_RAW + *******Description*********** + 17 + 1 + read-write + + + SLC0_RX_PF_VALID_INT_RAW + *******Description*********** + 18 + 1 + read-write + + + SLC0_EXT_BIT0_INT_RAW + *******Description*********** + 19 + 1 + read-write + + + SLC0_EXT_BIT1_INT_RAW + *******Description*********** + 20 + 1 + read-write + + + SLC0_EXT_BIT2_INT_RAW + *******Description*********** + 21 + 1 + read-write + + + SLC0_EXT_BIT3_INT_RAW + *******Description*********** + 22 + 1 + read-write + + + SLC0_RX_NEW_PACKET_INT_RAW + *******Description*********** + 23 + 1 + read-write + + + SLC0_HOST_RD_RETRY_INT_RAW + *******Description*********** + 24 + 1 + read-write + + + GPIO_SDIO_INT_RAW + *******Description*********** + 25 + 1 + read-write + + + + + SLC1HOST_INT_RAW + *******Description*********** + 0x54 + 0x20 + + + SLC1_TOHOST_BIT0_INT_RAW + *******Description*********** + 0 + 1 + read-write + + + SLC1_TOHOST_BIT1_INT_RAW + *******Description*********** + 1 + 1 + read-write + + + SLC1_TOHOST_BIT2_INT_RAW + *******Description*********** + 2 + 1 + read-write + + + SLC1_TOHOST_BIT3_INT_RAW + *******Description*********** + 3 + 1 + read-write + + + SLC1_TOHOST_BIT4_INT_RAW + *******Description*********** + 4 + 1 + read-write + + + SLC1_TOHOST_BIT5_INT_RAW + *******Description*********** + 5 + 1 + read-write + + + SLC1_TOHOST_BIT6_INT_RAW + *******Description*********** + 6 + 1 + read-write + + + SLC1_TOHOST_BIT7_INT_RAW + *******Description*********** + 7 + 1 + read-write + + + SLC1_TOKEN0_1TO0_INT_RAW + *******Description*********** + 8 + 1 + read-write + + + SLC1_TOKEN1_1TO0_INT_RAW + *******Description*********** + 9 + 1 + read-write + + + SLC1_TOKEN0_0TO1_INT_RAW + *******Description*********** + 10 + 1 + read-write + + + SLC1_TOKEN1_0TO1_INT_RAW + *******Description*********** + 11 + 1 + read-write + + + SLC1HOST_RX_SOF_INT_RAW + *******Description*********** + 12 + 1 + read-write + + + SLC1HOST_RX_EOF_INT_RAW + *******Description*********** + 13 + 1 + read-write + + + SLC1HOST_RX_START_INT_RAW + *******Description*********** + 14 + 1 + read-write + + + SLC1HOST_TX_START_INT_RAW + *******Description*********** + 15 + 1 + read-write + + + SLC1_RX_UDF_INT_RAW + *******Description*********** + 16 + 1 + read-write + + + SLC1_TX_OVF_INT_RAW + *******Description*********** + 17 + 1 + read-write + + + SLC1_RX_PF_VALID_INT_RAW + *******Description*********** + 18 + 1 + read-write + + + SLC1_EXT_BIT0_INT_RAW + *******Description*********** + 19 + 1 + read-write + + + SLC1_EXT_BIT1_INT_RAW + *******Description*********** + 20 + 1 + read-write + + + SLC1_EXT_BIT2_INT_RAW + *******Description*********** + 21 + 1 + read-write + + + SLC1_EXT_BIT3_INT_RAW + *******Description*********** + 22 + 1 + read-write + + + SLC1_WIFI_RX_NEW_PACKET_INT_RAW + *******Description*********** + 23 + 1 + read-write + + + SLC1_HOST_RD_RETRY_INT_RAW + *******Description*********** + 24 + 1 + read-write + + + SLC1_BT_RX_NEW_PACKET_INT_RAW + *******Description*********** + 25 + 1 + read-write + + + + + SLC0HOST_INT_ST + *******Description*********** + 0x58 + 0x20 + + + SLC0_TOHOST_BIT0_INT_ST + *******Description*********** + 0 + 1 + read-only + + + SLC0_TOHOST_BIT1_INT_ST + *******Description*********** + 1 + 1 + read-only + + + SLC0_TOHOST_BIT2_INT_ST + *******Description*********** + 2 + 1 + read-only + + + SLC0_TOHOST_BIT3_INT_ST + *******Description*********** + 3 + 1 + read-only + + + SLC0_TOHOST_BIT4_INT_ST + *******Description*********** + 4 + 1 + read-only + + + SLC0_TOHOST_BIT5_INT_ST + *******Description*********** + 5 + 1 + read-only + + + SLC0_TOHOST_BIT6_INT_ST + *******Description*********** + 6 + 1 + read-only + + + SLC0_TOHOST_BIT7_INT_ST + *******Description*********** + 7 + 1 + read-only + + + SLC0_TOKEN0_1TO0_INT_ST + *******Description*********** + 8 + 1 + read-only + + + SLC0_TOKEN1_1TO0_INT_ST + *******Description*********** + 9 + 1 + read-only + + + SLC0_TOKEN0_0TO1_INT_ST + *******Description*********** + 10 + 1 + read-only + + + SLC0_TOKEN1_0TO1_INT_ST + *******Description*********** + 11 + 1 + read-only + + + SLC0HOST_RX_SOF_INT_ST + *******Description*********** + 12 + 1 + read-only + + + SLC0HOST_RX_EOF_INT_ST + *******Description*********** + 13 + 1 + read-only + + + SLC0HOST_RX_START_INT_ST + *******Description*********** + 14 + 1 + read-only + + + SLC0HOST_TX_START_INT_ST + *******Description*********** + 15 + 1 + read-only + + + SLC0_RX_UDF_INT_ST + *******Description*********** + 16 + 1 + read-only + + + SLC0_TX_OVF_INT_ST + *******Description*********** + 17 + 1 + read-only + + + SLC0_RX_PF_VALID_INT_ST + *******Description*********** + 18 + 1 + read-only + + + SLC0_EXT_BIT0_INT_ST + *******Description*********** + 19 + 1 + read-only + + + SLC0_EXT_BIT1_INT_ST + *******Description*********** + 20 + 1 + read-only + + + SLC0_EXT_BIT2_INT_ST + *******Description*********** + 21 + 1 + read-only + + + SLC0_EXT_BIT3_INT_ST + *******Description*********** + 22 + 1 + read-only + + + SLC0_RX_NEW_PACKET_INT_ST + *******Description*********** + 23 + 1 + read-only + + + SLC0_HOST_RD_RETRY_INT_ST + *******Description*********** + 24 + 1 + read-only + + + GPIO_SDIO_INT_ST + *******Description*********** + 25 + 1 + read-only + + + + + SLC1HOST_INT_ST + *******Description*********** + 0x5C + 0x20 + + + SLC1_TOHOST_BIT0_INT_ST + *******Description*********** + 0 + 1 + read-only + + + SLC1_TOHOST_BIT1_INT_ST + *******Description*********** + 1 + 1 + read-only + + + SLC1_TOHOST_BIT2_INT_ST + *******Description*********** + 2 + 1 + read-only + + + SLC1_TOHOST_BIT3_INT_ST + *******Description*********** + 3 + 1 + read-only + + + SLC1_TOHOST_BIT4_INT_ST + *******Description*********** + 4 + 1 + read-only + + + SLC1_TOHOST_BIT5_INT_ST + *******Description*********** + 5 + 1 + read-only + + + SLC1_TOHOST_BIT6_INT_ST + *******Description*********** + 6 + 1 + read-only + + + SLC1_TOHOST_BIT7_INT_ST + *******Description*********** + 7 + 1 + read-only + + + SLC1_TOKEN0_1TO0_INT_ST + *******Description*********** + 8 + 1 + read-only + + + SLC1_TOKEN1_1TO0_INT_ST + *******Description*********** + 9 + 1 + read-only + + + SLC1_TOKEN0_0TO1_INT_ST + *******Description*********** + 10 + 1 + read-only + + + SLC1_TOKEN1_0TO1_INT_ST + *******Description*********** + 11 + 1 + read-only + + + SLC1HOST_RX_SOF_INT_ST + *******Description*********** + 12 + 1 + read-only + + + SLC1HOST_RX_EOF_INT_ST + *******Description*********** + 13 + 1 + read-only + + + SLC1HOST_RX_START_INT_ST + *******Description*********** + 14 + 1 + read-only + + + SLC1HOST_TX_START_INT_ST + *******Description*********** + 15 + 1 + read-only + + + SLC1_RX_UDF_INT_ST + *******Description*********** + 16 + 1 + read-only + + + SLC1_TX_OVF_INT_ST + *******Description*********** + 17 + 1 + read-only + + + SLC1_RX_PF_VALID_INT_ST + *******Description*********** + 18 + 1 + read-only + + + SLC1_EXT_BIT0_INT_ST + *******Description*********** + 19 + 1 + read-only + + + SLC1_EXT_BIT1_INT_ST + *******Description*********** + 20 + 1 + read-only + + + SLC1_EXT_BIT2_INT_ST + *******Description*********** + 21 + 1 + read-only + + + SLC1_EXT_BIT3_INT_ST + *******Description*********** + 22 + 1 + read-only + + + SLC1_WIFI_RX_NEW_PACKET_INT_ST + *******Description*********** + 23 + 1 + read-only + + + SLC1_HOST_RD_RETRY_INT_ST + *******Description*********** + 24 + 1 + read-only + + + SLC1_BT_RX_NEW_PACKET_INT_ST + *******Description*********** + 25 + 1 + read-only + + + + + PKT_LEN + *******Description*********** + 0x60 + 0x20 + + + HOSTSLCHOST_SLC0_LEN + *******Description*********** + 0 + 20 + read-only + + + HOSTSLCHOST_SLC0_LEN_CHECK + *******Description*********** + 20 + 12 + read-only + + + + + STATE_W0 + *******Description*********** + 0x64 + 0x20 + + + SLCHOST_STATE0 + *******Description*********** + 0 + 8 + read-only + + + SLCHOST_STATE1 + *******Description*********** + 8 + 8 + read-only + + + SLCHOST_STATE2 + *******Description*********** + 16 + 8 + read-only + + + SLCHOST_STATE3 + *******Description*********** + 24 + 8 + read-only + + + + + STATE_W1 + *******Description*********** + 0x68 + 0x20 + + + SLCHOST_STATE4 + *******Description*********** + 0 + 8 + read-only + + + SLCHOST_STATE5 + *******Description*********** + 8 + 8 + read-only + + + SLCHOST_STATE6 + *******Description*********** + 16 + 8 + read-only + + + SLCHOST_STATE7 + *******Description*********** + 24 + 8 + read-only + + + + + CONF_W0 + *******Description*********** + 0x6C + 0x20 + + + SLCHOST_CONF0 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF1 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF2 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF3 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W1 + *******Description*********** + 0x70 + 0x20 + + + SLCHOST_CONF4 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF5 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF6 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF7 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W2 + *******Description*********** + 0x74 + 0x20 + + + SLCHOST_CONF8 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF9 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF10 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF11 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W3 + *******Description*********** + 0x78 + 0x20 + 0x000000C0 + + + SLCHOST_CONF12 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF13 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF14 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF15 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W4 + *******Description*********** + 0x7C + 0x20 + 0x000001FF + + + SLCHOST_CONF16 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF17 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF18 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF19 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W5 + *******Description*********** + 0x80 + 0x20 + + + SLCHOST_CONF20 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF21 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF22 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF23 + *******Description*********** + 24 + 8 + read-write + + + + + WIN_CMD + *******Description*********** + 0x84 + 0x20 + + + SLCHOST_WIN_CMD + *******Description*********** + 0 + 16 + read-write + + + + + CONF_W6 + *******Description*********** + 0x88 + 0x20 + + + SLCHOST_CONF24 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF25 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF26 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF27 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W7 + *******Description*********** + 0x8C + 0x20 + + + SLCHOST_CONF28 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF29 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF30 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF31 + *******Description*********** + 24 + 8 + read-write + + + + + PKT_LEN0 + *******Description*********** + 0x90 + 0x20 + + + HOSTSLCHOST_SLC0_LEN0 + *******Description*********** + 0 + 20 + read-only + + + HOSTSLCHOST_SLC0_LEN0_CHECK + *******Description*********** + 20 + 12 + read-only + + + + + PKT_LEN1 + *******Description*********** + 0x94 + 0x20 + + + HOSTSLCHOST_SLC0_LEN1 + *******Description*********** + 0 + 20 + read-only + + + HOSTSLCHOST_SLC0_LEN1_CHECK + *******Description*********** + 20 + 12 + read-only + + + + + PKT_LEN2 + *******Description*********** + 0x98 + 0x20 + + + HOSTSLCHOST_SLC0_LEN2 + *******Description*********** + 0 + 20 + read-only + + + HOSTSLCHOST_SLC0_LEN2_CHECK + *******Description*********** + 20 + 12 + read-only + + + + + CONF_W8 + *******Description*********** + 0x9C + 0x20 + + + SLCHOST_CONF32 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF33 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF34 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF35 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W9 + *******Description*********** + 0xA0 + 0x20 + + + SLCHOST_CONF36 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF37 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF38 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF39 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W10 + *******Description*********** + 0xA4 + 0x20 + + + SLCHOST_CONF40 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF41 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF42 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF43 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W11 + *******Description*********** + 0xA8 + 0x20 + + + SLCHOST_CONF44 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF45 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF46 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF47 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W12 + *******Description*********** + 0xAC + 0x20 + + + SLCHOST_CONF48 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF49 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF50 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF51 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W13 + *******Description*********** + 0xB0 + 0x20 + + + SLCHOST_CONF52 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF53 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF54 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF55 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W14 + *******Description*********** + 0xB4 + 0x20 + + + SLCHOST_CONF56 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF57 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF58 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF59 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W15 + *******Description*********** + 0xB8 + 0x20 + + + SLCHOST_CONF60 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF61 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF62 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF63 + *******Description*********** + 24 + 8 + read-write + + + + + CHECK_SUM0 + *******Description*********** + 0xBC + 0x20 + + + SLCHOST_CHECK_SUM0 + *******Description*********** + 0 + 32 + read-only + + + + + CHECK_SUM1 + *******Description*********** + 0xC0 + 0x20 + 0x0000013F + + + SLCHOST_CHECK_SUM1 + *******Description*********** + 0 + 32 + read-only + + + + + SLC1HOST_TOKEN_RDATA + *******Description*********** + 0xC4 + 0x20 + + + SLC1_TOKEN0 + *******Description*********** + 0 + 12 + read-only + + + SLC1_RX_PF_VALID + *******Description*********** + 12 + 1 + read-only + + + HOSTSLCHOST_SLC1_TOKEN1 + *******Description*********** + 16 + 12 + read-only + + + SLC1_RX_PF_EOF + *******Description*********** + 28 + 4 + read-only + + + + + SLC0HOST_TOKEN_WDATA + *******Description*********** + 0xC8 + 0x20 + + + SLC0HOST_TOKEN0_WD + *******Description*********** + 0 + 12 + read-write + + + SLC0HOST_TOKEN1_WD + *******Description*********** + 16 + 12 + read-write + + + + + SLC1HOST_TOKEN_WDATA + *******Description*********** + 0xCC + 0x20 + + + SLC1HOST_TOKEN0_WD + *******Description*********** + 0 + 12 + read-write + + + SLC1HOST_TOKEN1_WD + *******Description*********** + 16 + 12 + read-write + + + + + TOKEN_CON + *******Description*********** + 0xD0 + 0x20 + + + SLC0HOST_TOKEN0_DEC + *******Description*********** + 0 + 1 + write-only + + + SLC0HOST_TOKEN1_DEC + *******Description*********** + 1 + 1 + write-only + + + SLC0HOST_TOKEN0_WR + *******Description*********** + 2 + 1 + write-only + + + SLC0HOST_TOKEN1_WR + *******Description*********** + 3 + 1 + write-only + + + SLC1HOST_TOKEN0_DEC + *******Description*********** + 4 + 1 + write-only + + + SLC1HOST_TOKEN1_DEC + *******Description*********** + 5 + 1 + write-only + + + SLC1HOST_TOKEN0_WR + *******Description*********** + 6 + 1 + write-only + + + SLC1HOST_TOKEN1_WR + *******Description*********** + 7 + 1 + write-only + + + SLC0HOST_LEN_WR + *******Description*********** + 8 + 1 + write-only + + + + + SLC0HOST_INT_CLR + *******Description*********** + 0xD4 + 0x20 + + + SLC0_TOHOST_BIT0_INT_CLR + *******Description*********** + 0 + 1 + write-only + + + SLC0_TOHOST_BIT1_INT_CLR + *******Description*********** + 1 + 1 + write-only + + + SLC0_TOHOST_BIT2_INT_CLR + *******Description*********** + 2 + 1 + write-only + + + SLC0_TOHOST_BIT3_INT_CLR + *******Description*********** + 3 + 1 + write-only + + + SLC0_TOHOST_BIT4_INT_CLR + *******Description*********** + 4 + 1 + write-only + + + SLC0_TOHOST_BIT5_INT_CLR + *******Description*********** + 5 + 1 + write-only + + + SLC0_TOHOST_BIT6_INT_CLR + *******Description*********** + 6 + 1 + write-only + + + SLC0_TOHOST_BIT7_INT_CLR + *******Description*********** + 7 + 1 + write-only + + + SLC0_TOKEN0_1TO0_INT_CLR + *******Description*********** + 8 + 1 + write-only + + + SLC0_TOKEN1_1TO0_INT_CLR + *******Description*********** + 9 + 1 + write-only + + + SLC0_TOKEN0_0TO1_INT_CLR + *******Description*********** + 10 + 1 + write-only + + + SLC0_TOKEN1_0TO1_INT_CLR + *******Description*********** + 11 + 1 + write-only + + + SLC0HOST_RX_SOF_INT_CLR + *******Description*********** + 12 + 1 + write-only + + + SLC0HOST_RX_EOF_INT_CLR + *******Description*********** + 13 + 1 + write-only + + + SLC0HOST_RX_START_INT_CLR + *******Description*********** + 14 + 1 + write-only + + + SLC0HOST_TX_START_INT_CLR + *******Description*********** + 15 + 1 + write-only + + + SLC0_RX_UDF_INT_CLR + *******Description*********** + 16 + 1 + write-only + + + SLC0_TX_OVF_INT_CLR + *******Description*********** + 17 + 1 + write-only + + + SLC0_RX_PF_VALID_INT_CLR + *******Description*********** + 18 + 1 + write-only + + + SLC0_EXT_BIT0_INT_CLR + *******Description*********** + 19 + 1 + write-only + + + SLC0_EXT_BIT1_INT_CLR + *******Description*********** + 20 + 1 + write-only + + + SLC0_EXT_BIT2_INT_CLR + *******Description*********** + 21 + 1 + write-only + + + SLC0_EXT_BIT3_INT_CLR + *******Description*********** + 22 + 1 + write-only + + + SLC0_RX_NEW_PACKET_INT_CLR + *******Description*********** + 23 + 1 + write-only + + + SLC0_HOST_RD_RETRY_INT_CLR + *******Description*********** + 24 + 1 + write-only + + + GPIO_SDIO_INT_CLR + *******Description*********** + 25 + 1 + write-only + + + + + SLC1HOST_INT_CLR + *******Description*********** + 0xD8 + 0x20 + + + SLC1_TOHOST_BIT0_INT_CLR + *******Description*********** + 0 + 1 + write-only + + + SLC1_TOHOST_BIT1_INT_CLR + *******Description*********** + 1 + 1 + write-only + + + SLC1_TOHOST_BIT2_INT_CLR + *******Description*********** + 2 + 1 + write-only + + + SLC1_TOHOST_BIT3_INT_CLR + *******Description*********** + 3 + 1 + write-only + + + SLC1_TOHOST_BIT4_INT_CLR + *******Description*********** + 4 + 1 + write-only + + + SLC1_TOHOST_BIT5_INT_CLR + *******Description*********** + 5 + 1 + write-only + + + SLC1_TOHOST_BIT6_INT_CLR + *******Description*********** + 6 + 1 + write-only + + + SLC1_TOHOST_BIT7_INT_CLR + *******Description*********** + 7 + 1 + write-only + + + SLC1_TOKEN0_1TO0_INT_CLR + *******Description*********** + 8 + 1 + write-only + + + SLC1_TOKEN1_1TO0_INT_CLR + *******Description*********** + 9 + 1 + write-only + + + SLC1_TOKEN0_0TO1_INT_CLR + *******Description*********** + 10 + 1 + write-only + + + SLC1_TOKEN1_0TO1_INT_CLR + *******Description*********** + 11 + 1 + write-only + + + SLC1HOST_RX_SOF_INT_CLR + *******Description*********** + 12 + 1 + write-only + + + SLC1HOST_RX_EOF_INT_CLR + *******Description*********** + 13 + 1 + write-only + + + SLC1HOST_RX_START_INT_CLR + *******Description*********** + 14 + 1 + write-only + + + SLC1HOST_TX_START_INT_CLR + *******Description*********** + 15 + 1 + write-only + + + SLC1_RX_UDF_INT_CLR + *******Description*********** + 16 + 1 + write-only + + + SLC1_TX_OVF_INT_CLR + *******Description*********** + 17 + 1 + write-only + + + SLC1_RX_PF_VALID_INT_CLR + *******Description*********** + 18 + 1 + write-only + + + SLC1_EXT_BIT0_INT_CLR + *******Description*********** + 19 + 1 + write-only + + + SLC1_EXT_BIT1_INT_CLR + *******Description*********** + 20 + 1 + write-only + + + SLC1_EXT_BIT2_INT_CLR + *******Description*********** + 21 + 1 + write-only + + + SLC1_EXT_BIT3_INT_CLR + *******Description*********** + 22 + 1 + write-only + + + SLC1_WIFI_RX_NEW_PACKET_INT_CLR + *******Description*********** + 23 + 1 + write-only + + + SLC1_HOST_RD_RETRY_INT_CLR + *******Description*********** + 24 + 1 + write-only + + + SLC1_BT_RX_NEW_PACKET_INT_CLR + *******Description*********** + 25 + 1 + write-only + + + + + SLC0HOST_FUNC1_INT_ENA + *******Description*********** + 0xDC + 0x20 + + + FN1_SLC0_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + FN1_SLC0_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + FN1_SLC0_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + FN1_SLC0_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + FN1_SLC0_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + FN1_SLC0HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + FN1_SLC0HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + FN1_SLC0HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + FN1_SLC0HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + FN1_SLC0_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + FN1_SLC0_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + FN1_SLC0_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + FN1_SLC0_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + FN1_SLC0_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + FN1_SLC0_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + FN1_SLC0_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + FN1_SLC0_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + FN1_SLC0_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + FN1_GPIO_SDIO_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC1HOST_FUNC1_INT_ENA + *******Description*********** + 0xE0 + 0x20 + + + FN1_SLC1_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + FN1_SLC1_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + FN1_SLC1_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + FN1_SLC1_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + FN1_SLC1_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + FN1_SLC1HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + FN1_SLC1HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + FN1_SLC1HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + FN1_SLC1HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + FN1_SLC1_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + FN1_SLC1_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + FN1_SLC1_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + FN1_SLC1_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + FN1_SLC1_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + FN1_SLC1_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + FN1_SLC1_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + FN1_SLC1_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC0HOST_FUNC2_INT_ENA + *******Description*********** + 0xE4 + 0x20 + + + FN2_SLC0_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + FN2_SLC0_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + FN2_SLC0_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + FN2_SLC0_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + FN2_SLC0_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + FN2_SLC0HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + FN2_SLC0HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + FN2_SLC0HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + FN2_SLC0HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + FN2_SLC0_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + FN2_SLC0_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + FN2_SLC0_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + FN2_SLC0_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + FN2_SLC0_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + FN2_SLC0_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + FN2_SLC0_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + FN2_SLC0_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + FN2_SLC0_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + FN2_GPIO_SDIO_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC1HOST_FUNC2_INT_ENA + *******Description*********** + 0xE8 + 0x20 + + + FN2_SLC1_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + FN2_SLC1_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + FN2_SLC1_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + FN2_SLC1_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + FN2_SLC1_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + FN2_SLC1HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + FN2_SLC1HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + FN2_SLC1HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + FN2_SLC1HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + FN2_SLC1_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + FN2_SLC1_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + FN2_SLC1_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + FN2_SLC1_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + FN2_SLC1_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + FN2_SLC1_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + FN2_SLC1_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + FN2_SLC1_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC0HOST_INT_ENA + *******Description*********** + 0xEC + 0x20 + + + SLC0_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + SLC0_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + SLC0_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + SLC0_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + SLC0_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + SLC0_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + SLC0_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + SLC0_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + SLC0_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + SLC0_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + SLC0_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + SLC0_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + SLC0HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + SLC0HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + SLC0HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + SLC0HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + SLC0_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + SLC0_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + SLC0_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + SLC0_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + SLC0_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + SLC0_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + SLC0_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + SLC0_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + SLC0_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + GPIO_SDIO_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC1HOST_INT_ENA + *******Description*********** + 0xF0 + 0x20 + + + SLC1_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + SLC1_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + SLC1_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + SLC1_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + SLC1_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + SLC1_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + SLC1_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + SLC1_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + SLC1_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + SLC1_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + SLC1_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + SLC1_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + SLC1HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + SLC1HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + SLC1HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + SLC1HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + SLC1_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + SLC1_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + SLC1_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + SLC1_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + SLC1_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + SLC1_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + SLC1_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + SLC1_WIFI_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + SLC1_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + SLC1_BT_RX_NEW_PACKET_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC0HOST_RX_INFOR + *******Description*********** + 0xF4 + 0x20 + + + SLC0HOST_RX_INFOR + *******Description*********** + 0 + 20 + read-write + + + + + SLC1HOST_RX_INFOR + *******Description*********** + 0xF8 + 0x20 + + + SLC1HOST_RX_INFOR + *******Description*********** + 0 + 20 + read-write + + + + + SLC0HOST_LEN_WD + *******Description*********** + 0xFC + 0x20 + + + SLC0HOST_LEN_WD + *******Description*********** + 0 + 32 + read-write + + + + + SLC_APBWIN_WDATA + *******Description*********** + 0x100 + 0x20 + + + SLC_APBWIN_WDATA + *******Description*********** + 0 + 32 + read-write + + + + + SLC_APBWIN_CONF + *******Description*********** + 0x104 + 0x20 + + + SLC_APBWIN_ADDR + *******Description*********** + 0 + 28 + read-write + + + SLC_APBWIN_WR + *******Description*********** + 28 + 1 + read-write + + + SLC_APBWIN_START + *******Description*********** + 29 + 1 + read-write + + + + + SLC_APBWIN_RDATA + *******Description*********** + 0x108 + 0x20 + + + SLC_APBWIN_RDATA + *******Description*********** + 0 + 32 + read-only + + + + + RDCLR0 + *******Description*********** + 0x10C + 0x20 + 0x0003C044 + + + SLCHOST_SLC0_BIT7_CLRADDR + *******Description*********** + 0 + 9 + read-write + + + SLCHOST_SLC0_BIT6_CLRADDR + *******Description*********** + 9 + 9 + read-write + + + + + RDCLR1 + *******Description*********** + 0x110 + 0x20 + 0x0003C1E0 + + + SLCHOST_SLC1_BIT7_CLRADDR + *******Description*********** + 0 + 9 + read-write + + + SLCHOST_SLC1_BIT6_CLRADDR + *******Description*********** + 9 + 9 + read-write + + + + + SLC0HOST_INT_ENA1 + *******Description*********** + 0x114 + 0x20 + + + SLC0_TOHOST_BIT0_INT_ENA1 + *******Description*********** + 0 + 1 + read-write + + + SLC0_TOHOST_BIT1_INT_ENA1 + *******Description*********** + 1 + 1 + read-write + + + SLC0_TOHOST_BIT2_INT_ENA1 + *******Description*********** + 2 + 1 + read-write + + + SLC0_TOHOST_BIT3_INT_ENA1 + *******Description*********** + 3 + 1 + read-write + + + SLC0_TOHOST_BIT4_INT_ENA1 + *******Description*********** + 4 + 1 + read-write + + + SLC0_TOHOST_BIT5_INT_ENA1 + *******Description*********** + 5 + 1 + read-write + + + SLC0_TOHOST_BIT6_INT_ENA1 + *******Description*********** + 6 + 1 + read-write + + + SLC0_TOHOST_BIT7_INT_ENA1 + *******Description*********** + 7 + 1 + read-write + + + SLC0_TOKEN0_1TO0_INT_ENA1 + *******Description*********** + 8 + 1 + read-write + + + SLC0_TOKEN1_1TO0_INT_ENA1 + *******Description*********** + 9 + 1 + read-write + + + SLC0_TOKEN0_0TO1_INT_ENA1 + *******Description*********** + 10 + 1 + read-write + + + SLC0_TOKEN1_0TO1_INT_ENA1 + *******Description*********** + 11 + 1 + read-write + + + SLC0HOST_RX_SOF_INT_ENA1 + *******Description*********** + 12 + 1 + read-write + + + SLC0HOST_RX_EOF_INT_ENA1 + *******Description*********** + 13 + 1 + read-write + + + SLC0HOST_RX_START_INT_ENA1 + *******Description*********** + 14 + 1 + read-write + + + SLC0HOST_TX_START_INT_ENA1 + *******Description*********** + 15 + 1 + read-write + + + SLC0_RX_UDF_INT_ENA1 + *******Description*********** + 16 + 1 + read-write + + + SLC0_TX_OVF_INT_ENA1 + *******Description*********** + 17 + 1 + read-write + + + SLC0_RX_PF_VALID_INT_ENA1 + *******Description*********** + 18 + 1 + read-write + + + SLC0_EXT_BIT0_INT_ENA1 + *******Description*********** + 19 + 1 + read-write + + + SLC0_EXT_BIT1_INT_ENA1 + *******Description*********** + 20 + 1 + read-write + + + SLC0_EXT_BIT2_INT_ENA1 + *******Description*********** + 21 + 1 + read-write + + + SLC0_EXT_BIT3_INT_ENA1 + *******Description*********** + 22 + 1 + read-write + + + SLC0_RX_NEW_PACKET_INT_ENA1 + *******Description*********** + 23 + 1 + read-write + + + SLC0_HOST_RD_RETRY_INT_ENA1 + *******Description*********** + 24 + 1 + read-write + + + GPIO_SDIO_INT_ENA1 + *******Description*********** + 25 + 1 + read-write + + + + + SLC1HOST_INT_ENA1 + *******Description*********** + 0x118 + 0x20 + + + SLC1_TOHOST_BIT0_INT_ENA1 + *******Description*********** + 0 + 1 + read-write + + + SLC1_TOHOST_BIT1_INT_ENA1 + *******Description*********** + 1 + 1 + read-write + + + SLC1_TOHOST_BIT2_INT_ENA1 + *******Description*********** + 2 + 1 + read-write + + + SLC1_TOHOST_BIT3_INT_ENA1 + *******Description*********** + 3 + 1 + read-write + + + SLC1_TOHOST_BIT4_INT_ENA1 + *******Description*********** + 4 + 1 + read-write + + + SLC1_TOHOST_BIT5_INT_ENA1 + *******Description*********** + 5 + 1 + read-write + + + SLC1_TOHOST_BIT6_INT_ENA1 + *******Description*********** + 6 + 1 + read-write + + + SLC1_TOHOST_BIT7_INT_ENA1 + *******Description*********** + 7 + 1 + read-write + + + SLC1_TOKEN0_1TO0_INT_ENA1 + *******Description*********** + 8 + 1 + read-write + + + SLC1_TOKEN1_1TO0_INT_ENA1 + *******Description*********** + 9 + 1 + read-write + + + SLC1_TOKEN0_0TO1_INT_ENA1 + *******Description*********** + 10 + 1 + read-write + + + SLC1_TOKEN1_0TO1_INT_ENA1 + *******Description*********** + 11 + 1 + read-write + + + SLC1HOST_RX_SOF_INT_ENA1 + *******Description*********** + 12 + 1 + read-write + + + SLC1HOST_RX_EOF_INT_ENA1 + *******Description*********** + 13 + 1 + read-write + + + SLC1HOST_RX_START_INT_ENA1 + *******Description*********** + 14 + 1 + read-write + + + SLC1HOST_TX_START_INT_ENA1 + *******Description*********** + 15 + 1 + read-write + + + SLC1_RX_UDF_INT_ENA1 + *******Description*********** + 16 + 1 + read-write + + + SLC1_TX_OVF_INT_ENA1 + *******Description*********** + 17 + 1 + read-write + + + SLC1_RX_PF_VALID_INT_ENA1 + *******Description*********** + 18 + 1 + read-write + + + SLC1_EXT_BIT0_INT_ENA1 + *******Description*********** + 19 + 1 + read-write + + + SLC1_EXT_BIT1_INT_ENA1 + *******Description*********** + 20 + 1 + read-write + + + SLC1_EXT_BIT2_INT_ENA1 + *******Description*********** + 21 + 1 + read-write + + + SLC1_EXT_BIT3_INT_ENA1 + *******Description*********** + 22 + 1 + read-write + + + SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 + *******Description*********** + 23 + 1 + read-write + + + SLC1_HOST_RD_RETRY_INT_ENA1 + *******Description*********** + 24 + 1 + read-write + + + SLC1_BT_RX_NEW_PACKET_INT_ENA1 + *******Description*********** + 25 + 1 + read-write + + + + + SLCHOSTDATE + *******Description*********** + 0x178 + 0x20 + 0x21060700 + + + SLCHOST_DATE + *******Description*********** + 0 + 32 + read-write + + + + + SLCHOSTID + *******Description*********** + 0x17C + 0x20 + 0x00000600 + + + SLCHOST_ID + *******Description*********** + 0 + 32 + read-write + + + + + CONF + *******Description*********** + 0x1F0 + 0x20 + + + FRC_SDIO11 + *******Description*********** + 0 + 5 + read-write + + + FRC_SDIO20 + *******Description*********** + 5 + 5 + read-write + + + FRC_NEG_SAMP + *******Description*********** + 10 + 5 + read-write + + + FRC_POS_SAMP + *******Description*********** + 15 + 5 + read-write + + + FRC_QUICK_IN + *******Description*********** + 20 + 5 + read-write + + + SDIO20_INT_DELAY + *******Description*********** + 25 + 1 + read-write + + + SDIO_PAD_PULLUP + *******Description*********** + 26 + 1 + read-write + + + HSPEED_CON_EN + *******Description*********** + 27 + 1 + read-write + + + + + INF_ST + *******Description*********** + 0x1F4 + 0x20 + + + SDIO20_MODE + *******Description*********** + 0 + 5 + read-only + + + SDIO_NEG_SAMP + *******Description*********** + 5 + 5 + read-only + + + SDIO_QUICK_IN + *******Description*********** + 10 + 5 + read-only + + + DLL_ON_SW + dll is controlled by software + 15 + 1 + read-write + + + DLL_ON + Software dll on + 16 + 1 + read-write + + + CLK_MODE_SW + dll clock mode is controlled by software + 17 + 1 + read-write + + + CLK_MODE + Software set clock mode + 18 + 2 + read-write + + + + + + + SOC_ETM + Event Task Matrix + SOC_ETM + 0x60013000 + + 0x0 + 0x1B0 + registers + + + + CH_ENA_AD0 + channel enable register + 0x0 + 0x20 + + + CH_ENA0 + ch0 enable + 0 + 1 + read-write + + + CH_ENA1 + ch1 enable + 1 + 1 + read-write + + + CH_ENA2 + ch2 enable + 2 + 1 + read-write + + + CH_ENA3 + ch3 enable + 3 + 1 + read-write + + + CH_ENA4 + ch4 enable + 4 + 1 + read-write + + + CH_ENA5 + ch5 enable + 5 + 1 + read-write + + + CH_ENA6 + ch6 enable + 6 + 1 + read-write + + + CH_ENA7 + ch7 enable + 7 + 1 + read-write + + + CH_ENA8 + ch8 enable + 8 + 1 + read-write + + + CH_ENA9 + ch9 enable + 9 + 1 + read-write + + + CH_ENA10 + ch10 enable + 10 + 1 + read-write + + + CH_ENA11 + ch11 enable + 11 + 1 + read-write + + + CH_ENA12 + ch12 enable + 12 + 1 + read-write + + + CH_ENA13 + ch13 enable + 13 + 1 + read-write + + + CH_ENA14 + ch14 enable + 14 + 1 + read-write + + + CH_ENA15 + ch15 enable + 15 + 1 + read-write + + + CH_ENA16 + ch16 enable + 16 + 1 + read-write + + + CH_ENA17 + ch17 enable + 17 + 1 + read-write + + + CH_ENA18 + ch18 enable + 18 + 1 + read-write + + + CH_ENA19 + ch19 enable + 19 + 1 + read-write + + + CH_ENA20 + ch20 enable + 20 + 1 + read-write + + + CH_ENA21 + ch21 enable + 21 + 1 + read-write + + + CH_ENA22 + ch22 enable + 22 + 1 + read-write + + + CH_ENA23 + ch23 enable + 23 + 1 + read-write + + + CH_ENA24 + ch24 enable + 24 + 1 + read-write + + + CH_ENA25 + ch25 enable + 25 + 1 + read-write + + + CH_ENA26 + ch26 enable + 26 + 1 + read-write + + + CH_ENA27 + ch27 enable + 27 + 1 + read-write + + + CH_ENA28 + ch28 enable + 28 + 1 + read-write + + + CH_ENA29 + ch29 enable + 29 + 1 + read-write + + + CH_ENA30 + ch30 enable + 30 + 1 + read-write + + + CH_ENA31 + ch31 enable + 31 + 1 + read-write + + + + + CH_ENA_AD0_SET + channel enable set register + 0x4 + 0x20 + + + CH_SET0 + ch0 set + 0 + 1 + write-only + + + CH_SET1 + ch1 set + 1 + 1 + write-only + + + CH_SET2 + ch2 set + 2 + 1 + write-only + + + CH_SET3 + ch3 set + 3 + 1 + write-only + + + CH_SET4 + ch4 set + 4 + 1 + write-only + + + CH_SET5 + ch5 set + 5 + 1 + write-only + + + CH_SET6 + ch6 set + 6 + 1 + write-only + + + CH_SET7 + ch7 set + 7 + 1 + write-only + + + CH_SET8 + ch8 set + 8 + 1 + write-only + + + CH_SET9 + ch9 set + 9 + 1 + write-only + + + CH_SET10 + ch10 set + 10 + 1 + write-only + + + CH_SET11 + ch11 set + 11 + 1 + write-only + + + CH_SET12 + ch12 set + 12 + 1 + write-only + + + CH_SET13 + ch13 set + 13 + 1 + write-only + + + CH_SET14 + ch14 set + 14 + 1 + write-only + + + CH_SET15 + ch15 set + 15 + 1 + write-only + + + CH_SET16 + ch16 set + 16 + 1 + write-only + + + CH_SET17 + ch17 set + 17 + 1 + write-only + + + CH_SET18 + ch18 set + 18 + 1 + write-only + + + CH_SET19 + ch19 set + 19 + 1 + write-only + + + CH_SET20 + ch20 set + 20 + 1 + write-only + + + CH_SET21 + ch21 set + 21 + 1 + write-only + + + CH_SET22 + ch22 set + 22 + 1 + write-only + + + CH_SET23 + ch23 set + 23 + 1 + write-only + + + CH_SET24 + ch24 set + 24 + 1 + write-only + + + CH_SET25 + ch25 set + 25 + 1 + write-only + + + CH_SET26 + ch26 set + 26 + 1 + write-only + + + CH_SET27 + ch27 set + 27 + 1 + write-only + + + CH_SET28 + ch28 set + 28 + 1 + write-only + + + CH_SET29 + ch29 set + 29 + 1 + write-only + + + CH_SET30 + ch30 set + 30 + 1 + write-only + + + CH_SET31 + ch31 set + 31 + 1 + write-only + + + + + CH_ENA_AD0_CLR + channel enable clear register + 0x8 + 0x20 + + + CH_CLR0 + ch0 clear + 0 + 1 + write-only + + + CH_CLR1 + ch1 clear + 1 + 1 + write-only + + + CH_CLR2 + ch2 clear + 2 + 1 + write-only + + + CH_CLR3 + ch3 clear + 3 + 1 + write-only + + + CH_CLR4 + ch4 clear + 4 + 1 + write-only + + + CH_CLR5 + ch5 clear + 5 + 1 + write-only + + + CH_CLR6 + ch6 clear + 6 + 1 + write-only + + + CH_CLR7 + ch7 clear + 7 + 1 + write-only + + + CH_CLR8 + ch8 clear + 8 + 1 + write-only + + + CH_CLR9 + ch9 clear + 9 + 1 + write-only + + + CH_CLR10 + ch10 clear + 10 + 1 + write-only + + + CH_CLR11 + ch11 clear + 11 + 1 + write-only + + + CH_CLR12 + ch12 clear + 12 + 1 + write-only + + + CH_CLR13 + ch13 clear + 13 + 1 + write-only + + + CH_CLR14 + ch14 clear + 14 + 1 + write-only + + + CH_CLR15 + ch15 clear + 15 + 1 + write-only + + + CH_CLR16 + ch16 clear + 16 + 1 + write-only + + + CH_CLR17 + ch17 clear + 17 + 1 + write-only + + + CH_CLR18 + ch18 clear + 18 + 1 + write-only + + + CH_CLR19 + ch19 clear + 19 + 1 + write-only + + + CH_CLR20 + ch20 clear + 20 + 1 + write-only + + + CH_CLR21 + ch21 clear + 21 + 1 + write-only + + + CH_CLR22 + ch22 clear + 22 + 1 + write-only + + + CH_CLR23 + ch23 clear + 23 + 1 + write-only + + + CH_CLR24 + ch24 clear + 24 + 1 + write-only + + + CH_CLR25 + ch25 clear + 25 + 1 + write-only + + + CH_CLR26 + ch26 clear + 26 + 1 + write-only + + + CH_CLR27 + ch27 clear + 27 + 1 + write-only + + + CH_CLR28 + ch28 clear + 28 + 1 + write-only + + + CH_CLR29 + ch29 clear + 29 + 1 + write-only + + + CH_CLR30 + ch30 clear + 30 + 1 + write-only + + + CH_CLR31 + ch31 clear + 31 + 1 + write-only + + + + + CH_ENA_AD1 + channel enable register + 0xC + 0x20 + + + CH_ENA32 + ch32 enable + 0 + 1 + read-write + + + CH_ENA33 + ch33 enable + 1 + 1 + read-write + + + CH_ENA34 + ch34 enable + 2 + 1 + read-write + + + CH_ENA35 + ch35 enable + 3 + 1 + read-write + + + CH_ENA36 + ch36 enable + 4 + 1 + read-write + + + CH_ENA37 + ch37 enable + 5 + 1 + read-write + + + CH_ENA38 + ch38 enable + 6 + 1 + read-write + + + CH_ENA39 + ch39 enable + 7 + 1 + read-write + + + CH_ENA40 + ch40 enable + 8 + 1 + read-write + + + CH_ENA41 + ch41 enable + 9 + 1 + read-write + + + CH_ENA42 + ch42 enable + 10 + 1 + read-write + + + CH_ENA43 + ch43 enable + 11 + 1 + read-write + + + CH_ENA44 + ch44 enable + 12 + 1 + read-write + + + CH_ENA45 + ch45 enable + 13 + 1 + read-write + + + CH_ENA46 + ch46 enable + 14 + 1 + read-write + + + CH_ENA47 + ch47 enable + 15 + 1 + read-write + + + CH_ENA48 + ch48 enable + 16 + 1 + read-write + + + CH_ENA49 + ch49 enable + 17 + 1 + read-write + + + + + CH_ENA_AD1_SET + channel enable set register + 0x10 + 0x20 + + + CH_SET32 + ch32 set + 0 + 1 + write-only + + + CH_SET33 + ch33 set + 1 + 1 + write-only + + + CH_SET34 + ch34 set + 2 + 1 + write-only + + + CH_SET35 + ch35 set + 3 + 1 + write-only + + + CH_SET36 + ch36 set + 4 + 1 + write-only + + + CH_SET37 + ch37 set + 5 + 1 + write-only + + + CH_SET38 + ch38 set + 6 + 1 + write-only + + + CH_SET39 + ch39 set + 7 + 1 + write-only + + + CH_SET40 + ch40 set + 8 + 1 + write-only + + + CH_SET41 + ch41 set + 9 + 1 + write-only + + + CH_SET42 + ch42 set + 10 + 1 + write-only + + + CH_SET43 + ch43 set + 11 + 1 + write-only + + + CH_SET44 + ch44 set + 12 + 1 + write-only + + + CH_SET45 + ch45 set + 13 + 1 + write-only + + + CH_SET46 + ch46 set + 14 + 1 + write-only + + + CH_SET47 + ch47 set + 15 + 1 + write-only + + + CH_SET48 + ch48 set + 16 + 1 + write-only + + + CH_SET49 + ch49 set + 17 + 1 + write-only + + + + + CH_ENA_AD1_CLR + channel enable clear register + 0x14 + 0x20 + + + CH_CLR32 + ch32 clear + 0 + 1 + write-only + + + CH_CLR33 + ch33 clear + 1 + 1 + write-only + + + CH_CLR34 + ch34 clear + 2 + 1 + write-only + + + CH_CLR35 + ch35 clear + 3 + 1 + write-only + + + CH_CLR36 + ch36 clear + 4 + 1 + write-only + + + CH_CLR37 + ch37 clear + 5 + 1 + write-only + + + CH_CLR38 + ch38 clear + 6 + 1 + write-only + + + CH_CLR39 + ch39 clear + 7 + 1 + write-only + + + CH_CLR40 + ch40 clear + 8 + 1 + write-only + + + CH_CLR41 + ch41 clear + 9 + 1 + write-only + + + CH_CLR42 + ch42 clear + 10 + 1 + write-only + + + CH_CLR43 + ch43 clear + 11 + 1 + write-only + + + CH_CLR44 + ch44 clear + 12 + 1 + write-only + + + CH_CLR45 + ch45 clear + 13 + 1 + write-only + + + CH_CLR46 + ch46 clear + 14 + 1 + write-only + + + CH_CLR47 + ch47 clear + 15 + 1 + write-only + + + CH_CLR48 + ch48 clear + 16 + 1 + write-only + + + CH_CLR49 + ch49 clear + 17 + 1 + write-only + + + + + CH0_EVT_ID + channel0 event id register + 0x18 + 0x20 + + + CH0_EVT_ID + ch0_evt_id + 0 + 8 + read-write + + + + + CH0_TASK_ID + channel0 task id register + 0x1C + 0x20 + + + CH0_TASK_ID + ch0_task_id + 0 + 8 + read-write + + + + + CH1_EVT_ID + channel1 event id register + 0x20 + 0x20 + + + CH1_EVT_ID + ch1_evt_id + 0 + 8 + read-write + + + + + CH1_TASK_ID + channel1 task id register + 0x24 + 0x20 + + + CH1_TASK_ID + ch1_task_id + 0 + 8 + read-write + + + + + CH2_EVT_ID + channel2 event id register + 0x28 + 0x20 + + + CH2_EVT_ID + ch2_evt_id + 0 + 8 + read-write + + + + + CH2_TASK_ID + channel2 task id register + 0x2C + 0x20 + + + CH2_TASK_ID + ch2_task_id + 0 + 8 + read-write + + + + + CH3_EVT_ID + channel3 event id register + 0x30 + 0x20 + + + CH3_EVT_ID + ch3_evt_id + 0 + 8 + read-write + + + + + CH3_TASK_ID + channel3 task id register + 0x34 + 0x20 + + + CH3_TASK_ID + ch3_task_id + 0 + 8 + read-write + + + + + CH4_EVT_ID + channel4 event id register + 0x38 + 0x20 + + + CH4_EVT_ID + ch4_evt_id + 0 + 8 + read-write + + + + + CH4_TASK_ID + channel4 task id register + 0x3C + 0x20 + + + CH4_TASK_ID + ch4_task_id + 0 + 8 + read-write + + + + + CH5_EVT_ID + channel5 event id register + 0x40 + 0x20 + + + CH5_EVT_ID + ch5_evt_id + 0 + 8 + read-write + + + + + CH5_TASK_ID + channel5 task id register + 0x44 + 0x20 + + + CH5_TASK_ID + ch5_task_id + 0 + 8 + read-write + + + + + CH6_EVT_ID + channel6 event id register + 0x48 + 0x20 + + + CH6_EVT_ID + ch6_evt_id + 0 + 8 + read-write + + + + + CH6_TASK_ID + channel6 task id register + 0x4C + 0x20 + + + CH6_TASK_ID + ch6_task_id + 0 + 8 + read-write + + + + + CH7_EVT_ID + channel7 event id register + 0x50 + 0x20 + + + CH7_EVT_ID + ch7_evt_id + 0 + 8 + read-write + + + + + CH7_TASK_ID + channel7 task id register + 0x54 + 0x20 + + + CH7_TASK_ID + ch7_task_id + 0 + 8 + read-write + + + + + CH8_EVT_ID + channel8 event id register + 0x58 + 0x20 + + + CH8_EVT_ID + ch8_evt_id + 0 + 8 + read-write + + + + + CH8_TASK_ID + channel8 task id register + 0x5C + 0x20 + + + CH8_TASK_ID + ch8_task_id + 0 + 8 + read-write + + + + + CH9_EVT_ID + channel9 event id register + 0x60 + 0x20 + + + CH9_EVT_ID + ch9_evt_id + 0 + 8 + read-write + + + + + CH9_TASK_ID + channel9 task id register + 0x64 + 0x20 + + + CH9_TASK_ID + ch9_task_id + 0 + 8 + read-write + + + + + CH10_EVT_ID + channel10 event id register + 0x68 + 0x20 + + + CH10_EVT_ID + ch10_evt_id + 0 + 8 + read-write + + + + + CH10_TASK_ID + channel10 task id register + 0x6C + 0x20 + + + CH10_TASK_ID + ch10_task_id + 0 + 8 + read-write + + + + + CH11_EVT_ID + channel11 event id register + 0x70 + 0x20 + + + CH11_EVT_ID + ch11_evt_id + 0 + 8 + read-write + + + + + CH11_TASK_ID + channel11 task id register + 0x74 + 0x20 + + + CH11_TASK_ID + ch11_task_id + 0 + 8 + read-write + + + + + CH12_EVT_ID + channel12 event id register + 0x78 + 0x20 + + + CH12_EVT_ID + ch12_evt_id + 0 + 8 + read-write + + + + + CH12_TASK_ID + channel12 task id register + 0x7C + 0x20 + + + CH12_TASK_ID + ch12_task_id + 0 + 8 + read-write + + + + + CH13_EVT_ID + channel13 event id register + 0x80 + 0x20 + + + CH13_EVT_ID + ch13_evt_id + 0 + 8 + read-write + + + + + CH13_TASK_ID + channel13 task id register + 0x84 + 0x20 + + + CH13_TASK_ID + ch13_task_id + 0 + 8 + read-write + + + + + CH14_EVT_ID + channel14 event id register + 0x88 + 0x20 + + + CH14_EVT_ID + ch14_evt_id + 0 + 8 + read-write + + + + + CH14_TASK_ID + channel14 task id register + 0x8C + 0x20 + + + CH14_TASK_ID + ch14_task_id + 0 + 8 + read-write + + + + + CH15_EVT_ID + channel15 event id register + 0x90 + 0x20 + + + CH15_EVT_ID + ch15_evt_id + 0 + 8 + read-write + + + + + CH15_TASK_ID + channel15 task id register + 0x94 + 0x20 + + + CH15_TASK_ID + ch15_task_id + 0 + 8 + read-write + + + + + CH16_EVT_ID + channel16 event id register + 0x98 + 0x20 + + + CH16_EVT_ID + ch16_evt_id + 0 + 8 + read-write + + + + + CH16_TASK_ID + channel16 task id register + 0x9C + 0x20 + + + CH16_TASK_ID + ch16_task_id + 0 + 8 + read-write + + + + + CH17_EVT_ID + channel17 event id register + 0xA0 + 0x20 + + + CH17_EVT_ID + ch17_evt_id + 0 + 8 + read-write + + + + + CH17_TASK_ID + channel17 task id register + 0xA4 + 0x20 + + + CH17_TASK_ID + ch17_task_id + 0 + 8 + read-write + + + + + CH18_EVT_ID + channel18 event id register + 0xA8 + 0x20 + + + CH18_EVT_ID + ch18_evt_id + 0 + 8 + read-write + + + + + CH18_TASK_ID + channel18 task id register + 0xAC + 0x20 + + + CH18_TASK_ID + ch18_task_id + 0 + 8 + read-write + + + + + CH19_EVT_ID + channel19 event id register + 0xB0 + 0x20 + + + CH19_EVT_ID + ch19_evt_id + 0 + 8 + read-write + + + + + CH19_TASK_ID + channel19 task id register + 0xB4 + 0x20 + + + CH19_TASK_ID + ch19_task_id + 0 + 8 + read-write + + + + + CH20_EVT_ID + channel20 event id register + 0xB8 + 0x20 + + + CH20_EVT_ID + ch20_evt_id + 0 + 8 + read-write + + + + + CH20_TASK_ID + channel20 task id register + 0xBC + 0x20 + + + CH20_TASK_ID + ch20_task_id + 0 + 8 + read-write + + + + + CH21_EVT_ID + channel21 event id register + 0xC0 + 0x20 + + + CH21_EVT_ID + ch21_evt_id + 0 + 8 + read-write + + + + + CH21_TASK_ID + channel21 task id register + 0xC4 + 0x20 + + + CH21_TASK_ID + ch21_task_id + 0 + 8 + read-write + + + + + CH22_EVT_ID + channel22 event id register + 0xC8 + 0x20 + + + CH22_EVT_ID + ch22_evt_id + 0 + 8 + read-write + + + + + CH22_TASK_ID + channel22 task id register + 0xCC + 0x20 + + + CH22_TASK_ID + ch22_task_id + 0 + 8 + read-write + + + + + CH23_EVT_ID + channel23 event id register + 0xD0 + 0x20 + + + CH23_EVT_ID + ch23_evt_id + 0 + 8 + read-write + + + + + CH23_TASK_ID + channel23 task id register + 0xD4 + 0x20 + + + CH23_TASK_ID + ch23_task_id + 0 + 8 + read-write + + + + + CH24_EVT_ID + channel24 event id register + 0xD8 + 0x20 + + + CH24_EVT_ID + ch24_evt_id + 0 + 8 + read-write + + + + + CH24_TASK_ID + channel24 task id register + 0xDC + 0x20 + + + CH24_TASK_ID + ch24_task_id + 0 + 8 + read-write + + + + + CH25_EVT_ID + channel25 event id register + 0xE0 + 0x20 + + + CH25_EVT_ID + ch25_evt_id + 0 + 8 + read-write + + + + + CH25_TASK_ID + channel25 task id register + 0xE4 + 0x20 + + + CH25_TASK_ID + ch25_task_id + 0 + 8 + read-write + + + + + CH26_EVT_ID + channel26 event id register + 0xE8 + 0x20 + + + CH26_EVT_ID + ch26_evt_id + 0 + 8 + read-write + + + + + CH26_TASK_ID + channel26 task id register + 0xEC + 0x20 + + + CH26_TASK_ID + ch26_task_id + 0 + 8 + read-write + + + + + CH27_EVT_ID + channel27 event id register + 0xF0 + 0x20 + + + CH27_EVT_ID + ch27_evt_id + 0 + 8 + read-write + + + + + CH27_TASK_ID + channel27 task id register + 0xF4 + 0x20 + + + CH27_TASK_ID + ch27_task_id + 0 + 8 + read-write + + + + + CH28_EVT_ID + channel28 event id register + 0xF8 + 0x20 + + + CH28_EVT_ID + ch28_evt_id + 0 + 8 + read-write + + + + + CH28_TASK_ID + channel28 task id register + 0xFC + 0x20 + + + CH28_TASK_ID + ch28_task_id + 0 + 8 + read-write + + + + + CH29_EVT_ID + channel29 event id register + 0x100 + 0x20 + + + CH29_EVT_ID + ch29_evt_id + 0 + 8 + read-write + + + + + CH29_TASK_ID + channel29 task id register + 0x104 + 0x20 + + + CH29_TASK_ID + ch29_task_id + 0 + 8 + read-write + + + + + CH30_EVT_ID + channel30 event id register + 0x108 + 0x20 + + + CH30_EVT_ID + ch30_evt_id + 0 + 8 + read-write + + + + + CH30_TASK_ID + channel30 task id register + 0x10C + 0x20 + + + CH30_TASK_ID + ch30_task_id + 0 + 8 + read-write + + + + + CH31_EVT_ID + channel31 event id register + 0x110 + 0x20 + + + CH31_EVT_ID + ch31_evt_id + 0 + 8 + read-write + + + + + CH31_TASK_ID + channel31 task id register + 0x114 + 0x20 + + + CH31_TASK_ID + ch31_task_id + 0 + 8 + read-write + + + + + CH32_EVT_ID + channel32 event id register + 0x118 + 0x20 + + + CH32_EVT_ID + ch32_evt_id + 0 + 8 + read-write + + + + + CH32_TASK_ID + channel32 task id register + 0x11C + 0x20 + + + CH32_TASK_ID + ch32_task_id + 0 + 8 + read-write + + + + + CH33_EVT_ID + channel33 event id register + 0x120 + 0x20 + + + CH33_EVT_ID + ch33_evt_id + 0 + 8 + read-write + + + + + CH33_TASK_ID + channel33 task id register + 0x124 + 0x20 + + + CH33_TASK_ID + ch33_task_id + 0 + 8 + read-write + + + + + CH34_EVT_ID + channel34 event id register + 0x128 + 0x20 + + + CH34_EVT_ID + ch34_evt_id + 0 + 8 + read-write + + + + + CH34_TASK_ID + channel34 task id register + 0x12C + 0x20 + + + CH34_TASK_ID + ch34_task_id + 0 + 8 + read-write + + + + + CH35_EVT_ID + channel35 event id register + 0x130 + 0x20 + + + CH35_EVT_ID + ch35_evt_id + 0 + 8 + read-write + + + + + CH35_TASK_ID + channel35 task id register + 0x134 + 0x20 + + + CH35_TASK_ID + ch35_task_id + 0 + 8 + read-write + + + + + CH36_EVT_ID + channel36 event id register + 0x138 + 0x20 + + + CH36_EVT_ID + ch36_evt_id + 0 + 8 + read-write + + + + + CH36_TASK_ID + channel36 task id register + 0x13C + 0x20 + + + CH36_TASK_ID + ch36_task_id + 0 + 8 + read-write + + + + + CH37_EVT_ID + channel37 event id register + 0x140 + 0x20 + + + CH37_EVT_ID + ch37_evt_id + 0 + 8 + read-write + + + + + CH37_TASK_ID + channel37 task id register + 0x144 + 0x20 + + + CH37_TASK_ID + ch37_task_id + 0 + 8 + read-write + + + + + CH38_EVT_ID + channel38 event id register + 0x148 + 0x20 + + + CH38_EVT_ID + ch38_evt_id + 0 + 8 + read-write + + + + + CH38_TASK_ID + channel38 task id register + 0x14C + 0x20 + + + CH38_TASK_ID + ch38_task_id + 0 + 8 + read-write + + + + + CH39_EVT_ID + channel39 event id register + 0x150 + 0x20 + + + CH39_EVT_ID + ch39_evt_id + 0 + 8 + read-write + + + + + CH39_TASK_ID + channel39 task id register + 0x154 + 0x20 + + + CH39_TASK_ID + ch39_task_id + 0 + 8 + read-write + + + + + CH40_EVT_ID + channel40 event id register + 0x158 + 0x20 + + + CH40_EVT_ID + ch40_evt_id + 0 + 8 + read-write + + + + + CH40_TASK_ID + channel40 task id register + 0x15C + 0x20 + + + CH40_TASK_ID + ch40_task_id + 0 + 8 + read-write + + + + + CH41_EVT_ID + channel41 event id register + 0x160 + 0x20 + + + CH41_EVT_ID + ch41_evt_id + 0 + 8 + read-write + + + + + CH41_TASK_ID + channel41 task id register + 0x164 + 0x20 + + + CH41_TASK_ID + ch41_task_id + 0 + 8 + read-write + + + + + CH42_EVT_ID + channel42 event id register + 0x168 + 0x20 + + + CH42_EVT_ID + ch42_evt_id + 0 + 8 + read-write + + + + + CH42_TASK_ID + channel42 task id register + 0x16C + 0x20 + + + CH42_TASK_ID + ch42_task_id + 0 + 8 + read-write + + + + + CH43_EVT_ID + channel43 event id register + 0x170 + 0x20 + + + CH43_EVT_ID + ch43_evt_id + 0 + 8 + read-write + + + + + CH43_TASK_ID + channel43 task id register + 0x174 + 0x20 + + + CH43_TASK_ID + ch43_task_id + 0 + 8 + read-write + + + + + CH44_EVT_ID + channel44 event id register + 0x178 + 0x20 + + + CH44_EVT_ID + ch44_evt_id + 0 + 8 + read-write + + + + + CH44_TASK_ID + channel44 task id register + 0x17C + 0x20 + + + CH44_TASK_ID + ch44_task_id + 0 + 8 + read-write + + + + + CH45_EVT_ID + channel45 event id register + 0x180 + 0x20 + + + CH45_EVT_ID + ch45_evt_id + 0 + 8 + read-write + + + + + CH45_TASK_ID + channel45 task id register + 0x184 + 0x20 + + + CH45_TASK_ID + ch45_task_id + 0 + 8 + read-write + + + + + CH46_EVT_ID + channel46 event id register + 0x188 + 0x20 + + + CH46_EVT_ID + ch46_evt_id + 0 + 8 + read-write + + + + + CH46_TASK_ID + channel46 task id register + 0x18C + 0x20 + + + CH46_TASK_ID + ch46_task_id + 0 + 8 + read-write + + + + + CH47_EVT_ID + channel47 event id register + 0x190 + 0x20 + + + CH47_EVT_ID + ch47_evt_id + 0 + 8 + read-write + + + + + CH47_TASK_ID + channel47 task id register + 0x194 + 0x20 + + + CH47_TASK_ID + ch47_task_id + 0 + 8 + read-write + + + + + CH48_EVT_ID + channel48 event id register + 0x198 + 0x20 + + + CH48_EVT_ID + ch48_evt_id + 0 + 8 + read-write + + + + + CH48_TASK_ID + channel48 task id register + 0x19C + 0x20 + + + CH48_TASK_ID + ch48_task_id + 0 + 8 + read-write + + + + + CH49_EVT_ID + channel49 event id register + 0x1A0 + 0x20 + + + CH49_EVT_ID + ch49_evt_id + 0 + 8 + read-write + + + + + CH49_TASK_ID + channel49 task id register + 0x1A4 + 0x20 + + + CH49_TASK_ID + ch49_task_id + 0 + 8 + read-write + + + + + CLK_EN + etm clock enable register + 0x1A8 + 0x20 + + + CLK_EN + clock enable + 0 + 1 + read-write + + + + + DATE + etm date register + 0x1AC + 0x20 + 0x02203092 + + + DATE + date + 0 + 28 + read-write + + + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller 0 + SPI0 + 0x60002000 + + 0x0 + 0x138 + registers + + + + SPI_MEM_CMD + SPI0 FSM status register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_USR + SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-only + + + + + SPI_MEM_CTRL + SPI0 control register. + 0x8 + 0x20 + 0x802C200C + + + SPI_MEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller. + 0 + 1 + read-only + + + SPI_MEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller. + 1 + 1 + read-write + + + SPI_MEM_FDUMMY_RIN + In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-only + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-only + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-only + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-only + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_DQS_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-only + + + SPI_MEM_DATA_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI0 control1 register. + 0xC + 0x20 + 0x28E00000 + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_AR_SIZE0_1_SUPPORT_EN + 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + 21 + 1 + read-write + + + SPI_AW_SIZE0_1_SUPPORT_EN + 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + 22 + 1 + read-write + + + SPI_AXI_RDATA_BACK_FAST + 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available. + 23 + 1 + read-only + + + SPI_MEM_RRESP_ECC_ERR_EN + 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. + 24 + 1 + read-write + + + SPI_MEM_AR_SPLICE_EN + Set this bit to enable AXI Read Splice-transfer. + 25 + 1 + read-only + + + SPI_MEM_AW_SPLICE_EN + Set this bit to enable AXI Write Splice-transfer. + 26 + 1 + read-only + + + SPI_MEM_RAM0_EN + When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 27 + 1 + read-only + + + SPI_MEM_DUAL_RAM_EN + Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 28 + 1 + read-only + + + SPI_MEM_FAST_WRITE_EN + Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2. + 29 + 1 + read-write + + + SPI_MEM_RXFIFO_RST + The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. + 30 + 1 + write-only + + + SPI_MEM_TXFIFO_RST + The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. + 31 + 1 + write-only + + + + + SPI_MEM_CTRL2 + SPI0 control2 register. + 0x10 + 0x20 + 0x00002C21 + + + SPI_MEM_CS_SETUP_TIME + (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. + 0 + 5 + read-write + + + SPI_MEM_CS_HOLD_TIME + SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. + 5 + 5 + read-write + + + SPI_MEM_ECC_CS_HOLD_TIME + SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. + 10 + 3 + read-only + + + SPI_MEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash. + 13 + 1 + read-only + + + SPI_MEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + 14 + 1 + read-only + + + SPI_MEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 24 + 1 + read-only + + + SPI_MEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SPI_MEM_SYNC_RESET + The spi0_mst_st and spi0_slv_st will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock. + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI0 user register. + 0x18 + 0x20 + + + SPI_MEM_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. + 6 + 1 + read-write + + + SPI_MEM_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 7 + 1 + read-write + + + SPI_MEM_CK_OUT_EDGE + The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + 9 + 1 + read-write + + + SPI_MEM_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000047 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_DBYTELEN + SPI0 USR_CMD read or write data byte length -1 + 6 + 3 + read-only + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI0 misc register + 0x34 + 0x20 + + + SPI_MEM_FSUB_PIN + For SPI0, flash is connected to SUBPINs. + 7 + 1 + read-only + + + SPI_MEM_SSUB_PIN + For SPI0, sram is connected to SUBPINs. + 8 + 1 + read-only + + + SPI_MEM_CK_IDLE_EDGE + 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_CACHE_FCTRL + SPI0 bit mode control register. + 0x3C + 0x20 + 0xC0000000 + + + SPI_MEM_AXI_REQ_EN + For SPI0, AXI master access enable, 1: enable, 0:disable. + 0 + 1 + read-write + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_CACHE_FLASH_USR_CMD + For SPI0, cache read flash for user define command, 1: enable, 0:disable. + 2 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + SPI_SAME_AW_AR_ADDR_CHK_EN + Set this bit to check AXI read/write the same address region. + 30 + 1 + read-only + + + SPI_CLOSE_AXI_INF_EN + Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP. + 31 + 1 + read-write + + + + + SPI_MEM_CACHE_SCTRL + SPI0 external RAM control register + 0x40 + 0x20 + 0x0055C070 + + + SPI_MEM_CACHE_USR_SADDR_4BYTE + For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable. + 0 + 1 + read-only + + + SPI_MEM_USR_SRAM_DIO + For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + 1 + 1 + read-only + + + SPI_MEM_USR_SRAM_QIO + For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + 2 + 1 + read-only + + + SPI_MEM_USR_WR_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations. + 3 + 1 + read-only + + + SPI_MEM_USR_RD_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations. + 4 + 1 + read-only + + + SPI_MEM_CACHE_SRAM_USR_RCMD + For SPI0, In the external RAM mode cache read external RAM for user define command. + 5 + 1 + read-only + + + SPI_MEM_SRAM_RDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1). + 6 + 6 + read-only + + + SPI_MEM_SRAM_ADDR_BITLEN + For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1). + 14 + 6 + read-only + + + SPI_MEM_CACHE_SRAM_USR_WCMD + For SPI0, In the external RAM mode cache write sram for user define command + 20 + 1 + read-only + + + SPI_MEM_SRAM_OCT + reserved + 21 + 1 + read-only + + + SPI_MEM_SRAM_WDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1). + 22 + 6 + read-only + + + + + SPI_MEM_SRAM_CMD + SPI0 external RAM mode control register + 0x44 + 0x20 + 0xC0400000 + + + SPI_MEM_SCLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. + 0 + 2 + read-only + + + SPI_MEM_SWB_MODE + Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. + 2 + 8 + read-only + + + SPI_MEM_SDIN_DUAL + For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 10 + 1 + read-only + + + SPI_MEM_SDOUT_DUAL + For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 11 + 1 + read-only + + + SPI_MEM_SADDR_DUAL + For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 12 + 1 + read-only + + + SPI_MEM_SDIN_QUAD + For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 14 + 1 + read-only + + + SPI_MEM_SDOUT_QUAD + For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 15 + 1 + read-only + + + SPI_MEM_SADDR_QUAD + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 16 + 1 + read-only + + + SPI_MEM_SCMD_QUAD + For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 17 + 1 + read-only + + + SPI_MEM_SDIN_OCT + For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + 18 + 1 + read-only + + + SPI_MEM_SDOUT_OCT + For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + 19 + 1 + read-only + + + SPI_MEM_SADDR_OCT + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-only + + + SPI_MEM_SCMD_OCT + For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + 21 + 1 + read-only + + + SPI_MEM_SDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 22 + 1 + read-write + + + SPI_MEM_SDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 23 + 1 + read-only + + + SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller. + 24 + 1 + read-only + + + SPI_SMEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller. + 25 + 1 + read-only + + + SPI_SMEM_DQS_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-only + + + SPI_SMEM_DATA_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-only + + + + + SPI_MEM_SRAM_DRD_CMD + SPI0 external RAM DDR read command control register + 0x48 + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE + For SPI0,When cache mode is enable it is the read command value of command phase for sram. + 0 + 16 + read-only + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN + For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-only + + + + + SPI_MEM_SRAM_DWR_CMD + SPI0 external RAM DDR write command control register + 0x4C + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE + For SPI0,When cache mode is enable it is the write command value of command phase for sram. + 0 + 16 + read-only + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN + For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-only + + + + + SPI_MEM_SRAM_CLK + SPI0 external RAM clock control register + 0x50 + 0x20 + 0x00030103 + + + SPI_MEM_SCLKCNT_L + For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-only + + + SPI_MEM_SCLKCNT_H + For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-only + + + SPI_MEM_SCLKCNT_N + For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-only + + + SPI_MEM_SCLK_EQU_SYSCLK + For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock. + 31 + 1 + read-only + + + + + SPI_MEM_FSM + SPI0 FSM status register + 0x54 + 0x20 + 0x00000200 + + + SPI_MEM_LOCK_DELAY_TIME + The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + 7 + 5 + read-write + + + + + SPI_MEM_INT_ENA + SPI0 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_ECC_ERR_INT_ENA + The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_ENA + The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-write + + + SPI_MEM_AXI_RADDR_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-write + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT__ENA + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + + + SPI_MEM_INT_CLR + SPI0 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_ECC_ERR_INT_CLR + The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_CLR + The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + write-only + + + SPI_MEM_AXI_RADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + write-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + + + SPI_MEM_INT_RAW + SPI0 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-write + + + SPI_MEM_ECC_ERR_INT_RAW + The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_RAW + The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others. + 6 + 1 + read-write + + + SPI_MEM_AXI_RADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others. + 7 + 1 + read-write + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others. + 9 + 1 + read-only + + + + + SPI_MEM_INT_ST + SPI0 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_ECC_ERR_INT_ST + The status bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_ST + The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-only + + + SPI_MEM_AXI_RADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + + + SPI_MEM_DDR + SPI0 flash DDR mode control register + 0xD4 + 0x20 + 0x00003020 + + + SPI_FMEM_DDR_EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-only + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-only + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-only + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-only + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-only + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-only + + + SPI_FMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash. + 12 + 1 + read-only + + + SPI_FMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash. + 13 + 1 + read-only + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-only + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-only + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-only + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-only + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-only + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-only + + + + + SPI_SMEM_DDR + SPI0 external RAM DDR mode control register + 0xD8 + 0x20 + 0x00003020 + + + EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-only + + + SPI_SMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-only + + + RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-only + + + WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-only + + + CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-only + + + SPI_SMEM_OUTMINBYTELEN + It is the minimum output data length in the DDR psram. + 5 + 7 + read-only + + + SPI_SMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM. + 12 + 1 + read-only + + + SPI_SMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM. + 13 + 1 + read-only + + + SPI_SMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-only + + + DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-only + + + SPI_SMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-only + + + SPI_SMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-only + + + SPI_SMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-only + + + SPI_SMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to external RAM. . + 28 + 1 + read-only + + + SPI_SMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-only + + + SPI_SMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-only + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ATTR + MSPI flash ACE section %s attribute register + 0x100 + 0x20 + 0x00000003 + + + SPI_FMEM_PMS_RD_ATTR + 1: SPI1 flash ACE section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_FMEM_PMS_WR_ATTR + 1: SPI1 flash ACE section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_FMEM_PMS_ECC + SPI1 flash ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ADDR + SPI1 flash ACE section %s start address register + 0x110 + 0x20 + + + S + SPI1 flash ACE section %s start address value + 0 + 26 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_SIZE + SPI1 flash ACE section %s start address register + 0x120 + 0x20 + 0x00001000 + + + SPI_FMEM_PMS_SIZE + SPI1 flash ACE section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE) + 0 + 14 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ATTR + SPI1 flash ACE section %s start address register + 0x130 + 0x20 + 0x00000003 + + + SPI_SMEM_PMS_RD_ATTR + 1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_SMEM_PMS_WR_ATTR + 1: SPI1 external RAM ACE section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_SMEM_PMS_ECC + SPI1 external RAM ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ADDR + SPI1 external RAM ACE section %s start address register + 0x140 + 0x20 + + + S + SPI1 external RAM ACE section %s start address value + 0 + 26 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_SIZE + SPI1 external RAM ACE section %s start address register + 0x150 + 0x20 + 0x00001000 + + + SPI_SMEM_PMS_SIZE + SPI1 external RAM ACE section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE) + 0 + 14 + read-write + + + + + SPI_MEM_PMS_REJECT + SPI1 access reject register + 0x164 + 0x20 + + + SPI_MEM_REJECT_ADDR + This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 0 + 26 + read-only + + + SPI_MEM_PM_EN + Set this bit to enable SPI0/1 transfer permission control function. + 26 + 1 + read-write + + + SPI_MEM_PMS_LD + 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 28 + 1 + read-only + + + SPI_MEM_PMS_ST + 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 29 + 1 + read-only + + + SPI_MEM_PMS_MULTI_HIT + 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 30 + 1 + read-only + + + SPI_MEM_PMS_IVD + 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 31 + 1 + read-only + + + + + SPI_MEM_ECC_CTRL + MSPI ECC control register + 0x168 + 0x20 + 0x01005000 + + + SPI_FMEM_ECC_ERR_INT_NUM + Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + 11 + 6 + read-only + + + SPI_FMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + 17 + 1 + read-only + + + SPI_FMEM_PAGE_SIZE + Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SPI_FMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-only + + + SPI_MEM_USR_ECC_ADDR_EN + Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + 21 + 1 + read-only + + + SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN + 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + 24 + 1 + read-only + + + SPI_MEM_ECC_ERR_BITS + Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7) + 25 + 7 + read-only + + + + + SPI_MEM_ECC_ERR_ADDR + MSPI ECC error address register + 0x16C + 0x20 + + + SPI_MEM_ECC_ERR_ADDR + This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 0 + 26 + read-only + + + SPI_MEM_ECC_ERR_CNT + This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 26 + 6 + read-only + + + + + SPI_MEM_AXI_ERR_ADDR + SPI0 AXI request error address. + 0x170 + 0x20 + 0xFC000000 + + + SPI_MEM_AXI_ERR_ADDR + This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + 0 + 26 + read-only + + + SPI_MEM_ALL_FIFO_EMPTY + The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others. + 26 + 1 + read-only + + + SPI_RDATA_AFIFO_REMPTY + 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + 27 + 1 + read-only + + + SPI_RADDR_AFIFO_REMPTY + 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + 28 + 1 + read-only + + + SPI_WDATA_AFIFO_REMPTY + 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + 29 + 1 + read-only + + + SPI_WBLEN_AFIFO_REMPTY + 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + 30 + 1 + read-only + + + SPI_ALL_AXI_TRANS_AFIFO_EMPTY + This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE. + 31 + 1 + read-only + + + + + SPI_SMEM_ECC_CTRL + MSPI ECC control register + 0x174 + 0x20 + 0x00080000 + + + SPI_SMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + 17 + 1 + read-only + + + SPI_SMEM_PAGE_SIZE + Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-only + + + SPI_SMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-only + + + + + SPI_MEM_TIMING_CALI + SPI0 flash timing calibration register + 0x180 + 0x20 + 0x00000001 + + + SPI_MEM_TIMING_CLK_ENA + The bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-write + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + SPI_MEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. + 5 + 1 + read-only + + + UPDATE + Set this bit to update delay mode, delay num and extra dummy in MSPI. + 6 + 1 + write-only + + + + + SPI_MEM_DIN_MODE + MSPI flash input timing delay mode control register + 0x184 + 0x20 + + + SPI_MEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_MEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_MEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_MEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_MEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 12 + 3 + read-write + + + SPI_MEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 15 + 3 + read-write + + + SPI_MEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 18 + 3 + read-write + + + SPI_MEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 21 + 3 + read-write + + + SPI_MEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 24 + 3 + read-write + + + + + SPI_MEM_DIN_NUM + MSPI flash input timing delay number control register + 0x188 + 0x20 + + + SPI_MEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_MEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_MEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_MEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_MEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_MEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_MEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_MEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_MEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_MEM_DOUT_MODE + MSPI flash output timing adjustment control register + 0x18C + 0x20 + + + SPI_MEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_MEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_MEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_MEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_MEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 4 + 1 + read-write + + + SPI_MEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 5 + 1 + read-write + + + SPI_MEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 6 + 1 + read-write + + + SPI_MEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 7 + 1 + read-write + + + SPI_MEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 8 + 1 + read-write + + + + + SPI_SMEM_TIMING_CALI + MSPI external RAM timing calibration register + 0x190 + 0x20 + 0x00000001 + + + SPI_SMEM_TIMING_CLK_ENA + For sram, the bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-only + + + SPI_SMEM_TIMING_CALI + For sram, the bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-only + + + SPI_SMEM_EXTRA_DUMMY_CYCLELEN + For sram, add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-only + + + SPI_SMEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. + 5 + 1 + read-only + + + + + SPI_SMEM_DIN_MODE + MSPI external RAM input timing delay mode control register + 0x194 + 0x20 + + + SPI_SMEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-only + + + SPI_SMEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-only + + + SPI_SMEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-only + + + SPI_SMEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-only + + + SPI_SMEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 12 + 3 + read-only + + + SPI_SMEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 15 + 3 + read-only + + + SPI_SMEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 18 + 3 + read-only + + + SPI_SMEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 21 + 3 + read-only + + + SPI_SMEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 24 + 3 + read-only + + + + + SPI_SMEM_DIN_NUM + MSPI external RAM input timing delay number control register + 0x198 + 0x20 + + + SPI_SMEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-only + + + SPI_SMEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-only + + + SPI_SMEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-only + + + SPI_SMEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-only + + + SPI_SMEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-only + + + SPI_SMEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-only + + + SPI_SMEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-only + + + SPI_SMEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-only + + + SPI_SMEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 16 + 2 + read-only + + + + + SPI_SMEM_DOUT_MODE + MSPI external RAM output timing adjustment control register + 0x19C + 0x20 + + + SPI_SMEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-only + + + SPI_SMEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-only + + + SPI_SMEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-only + + + SPI_SMEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-only + + + SPI_SMEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 4 + 1 + read-only + + + SPI_SMEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 5 + 1 + read-only + + + SPI_SMEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 6 + 1 + read-only + + + SPI_SMEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 7 + 1 + read-only + + + SPI_SMEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 8 + 1 + read-only + + + + + SPI_SMEM_AC + MSPI external RAM ECC and SPI CS timing control register + 0x1A0 + 0x20 + 0x8000B084 + + + SPI_SMEM_CS_SETUP + For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 0 + 1 + read-only + + + SPI_SMEM_CS_HOLD + For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + 1 + 1 + read-only + + + SPI_SMEM_CS_SETUP_TIME + For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. + 2 + 5 + read-only + + + SPI_SMEM_CS_HOLD_TIME + For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. + 7 + 5 + read-only + + + SPI_SMEM_ECC_CS_HOLD_TIME + SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. + 12 + 3 + read-only + + + SPI_SMEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM. + 15 + 1 + read-only + + + SPI_SMEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. + 16 + 1 + read-only + + + SPI_SMEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-only + + + SPI_SMEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 31 + 1 + read-only + + + + + SPI_MEM_CLOCK_GATE + SPI0 clock gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PLAIN_BASE + The base address of the memory that stores plaintext in Manual Encryption + 0x300 + 0x20 + + + SPI_XTS_PLAIN + This field is only used to generate include file in c case. This field is useless. Please do not use this field. + 0 + 32 + read-write + + + + + SPI_MEM_XTS_LINESIZE + Manual Encryption Line-Size register + 0x340 + 0x20 + + + SPI_XTS_LINESIZE + This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved. + 0 + 2 + read-write + + + + + SPI_MEM_XTS_DESTINATION + Manual Encryption destination register + 0x344 + 0x20 + + + SPI_XTS_DESTINATION + This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PHYSICAL_ADDRESS + Manual Encryption physical address register + 0x348 + 0x20 + + + SPI_XTS_PHYSICAL_ADDRESS + This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. + 0 + 26 + read-write + + + + + SPI_MEM_XTS_TRIGGER + Manual Encryption physical address register + 0x34C + 0x20 + + + SPI_XTS_TRIGGER + Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_RELEASE + Manual Encryption physical address register + 0x350 + 0x20 + + + SPI_XTS_RELEASE + Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_DESTROY + Manual Encryption physical address register + 0x354 + 0x20 + + + SPI_XTS_DESTROY + Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_STATE + Manual Encryption physical address register + 0x358 + 0x20 + + + SPI_XTS_STATE + This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi. + 0 + 2 + read-only + + + + + SPI_MEM_XTS_DATE + Manual Encryption version register + 0x35C + 0x20 + 0x20201010 + + + SPI_XTS_DATE + This bits stores the last modified-time of manual encryption feature. + 0 + 30 + read-write + + + + + SPI_MEM_MMU_ITEM_CONTENT + MSPI-MMU item content register + 0x37C + 0x20 + 0x0000037C + + + SPI_MMU_ITEM_CONTENT + MSPI-MMU item content + 0 + 32 + read-write + + + + + SPI_MEM_MMU_ITEM_INDEX + MSPI-MMU item index register + 0x380 + 0x20 + + + SPI_MMU_ITEM_INDEX + MSPI-MMU item index + 0 + 32 + read-write + + + + + SPI_MEM_MMU_POWER_CTRL + MSPI MMU power control register + 0x384 + 0x20 + 0x13200004 + + + SPI_MMU_MEM_FORCE_ON + Set this bit to enable mmu-memory clock force on + 0 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PD + Set this bit to force mmu-memory powerdown + 1 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PU + Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc. + 2 + 1 + read-write + + + SPI_MMU_PAGE_SIZE + 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + 3 + 2 + read-write + + + SPI_MEM_AUX_CTRL + MMU PSRAM aux control register + 16 + 14 + read-only + + + SPI_MEM_RDN_ENA + ECO register enable bit + 30 + 1 + read-only + + + SPI_MEM_RDN_RESULT + MSPI module clock domain and AXI clock domain ECO register result register + 31 + 1 + read-only + + + + + SPI_MEM_DPA_CTRL + SPI memory cryption DPA register + 0x388 + 0x20 + 0x0000000F + + + SPI_CRYPT_SECURITY_LEVEL + Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing) + 0 + 3 + read-write + + + SPI_CRYPT_CALC_D_DPA_EN + Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1. + 3 + 1 + read-write + + + SPI_CRYPT_DPA_SELECT_REGISTER + 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + 4 + 1 + read-write + + + + + SPI_MEM_REGISTERRND_ECO_HIGH + MSPI ECO high register + 0x3F0 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_HIGH + ECO high register + 0 + 32 + read-only + + + + + SPI_MEM_REGISTERRND_ECO_LOW + MSPI ECO low register + 0x3F4 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_LOW + ECO low register + 0 + 32 + read-only + + + + + SPI_MEM_DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02203030 + + + SPI_MEM_DATE + SPI0 register version. + 0 + 28 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller 1 + SPI1 + 0x60003000 + + 0x0 + 0xAC + registers + + + + SPI_MEM_CMD + SPI1 memory command register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI1 master FSM. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + SPI_MEM_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + SPI_MEM_FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + SPI_MEM_FLASH_RES + This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + SPI_MEM_FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_FLASH_PP + Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + SPI_MEM_FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + SPI_MEM_FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + SPI_MEM_FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + SPI_MEM_FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + SPI_MEM_FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + SPI_MEM_FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + SPI_MEM_ADDR + SPI1 address register + 0x4 + 0x20 + + + SPI_MEM_USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + SPI_MEM_CTRL + SPI1 control register. + 0x8 + 0x20 + 0x002CA00C + + + SPI_MEM_FDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-only + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-only + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-only + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-only + + + SPI_MEM_FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-only + + + SPI_MEM_TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-only + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_WRSR_2B + two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI1 control1 register. + 0xC + 0x20 + 0x00000FFC + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_MEM_CS_HOLD_DLY_RES + After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. + 2 + 10 + read-write + + + + + SPI_MEM_CTRL2 + SPI1 control2 register. + 0x10 + 0x20 + + + SPI_MEM_SYNC_RESET + The FSM will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI1 clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + reserved + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + SPI_MEM_CK_OUT_EDGE + the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + 9 + 1 + read-write + + + SPI_MEM_FWRITE_DUAL + In the write operations read-data phase apply 2 signals + 12 + 1 + read-write + + + SPI_MEM_FWRITE_QUAD + In the write operations read-data phase apply 4 signals + 13 + 1 + read-write + + + SPI_MEM_FWRITE_DIO + In the write operations address phase and read-data phase apply 2 signals. + 14 + 1 + read-write + + + SPI_MEM_FWRITE_QIO + In the write operations address phase and read-data phase apply 4 signals. + 15 + 1 + read-write + + + SPI_MEM_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 24 + 1 + read-only + + + SPI_MEM_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 25 + 1 + read-only + + + SPI_MEM_USR_DUMMY_IDLE + SPI clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_MOSI + This bit enable the write-data phase of an operation. + 27 + 1 + read-write + + + SPI_MEM_USR_MISO + This bit enable the read-data phase of an operation. + 28 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + SPI_MEM_USR_ADDR + This bit enable the address phase of an operation. + 30 + 1 + read-write + + + SPI_MEM_USR_COMMAND + This bit enable the command phase of an operation. + 31 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_MOSI_DLEN + SPI1 send data bit length control register. + 0x24 + 0x20 + + + SPI_MEM_USR_MOSI_DBITLEN + The length in bits of write-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_MISO_DLEN + SPI1 receive data bit length control register. + 0x28 + 0x20 + + + SPI_MEM_USR_MISO_DBITLEN + The length in bits of read-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_RD_STATUS + SPI1 status register. + 0x2C + 0x20 + + + SPI_MEM_STATUS + The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + 0 + 16 + read-write + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI1 misc register + 0x34 + 0x20 + 0x00000002 + + + SPI_MEM_CS0_DIS + SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. + 0 + 1 + read-write + + + SPI_MEM_CS1_DIS + SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. + 1 + 1 + read-write + + + SPI_MEM_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_TX_CRC + SPI1 TX CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + SPI_MEM_CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + + + SPI_MEM_W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + SPI_MEM_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + SPI_MEM_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + SPI_MEM_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + SPI_MEM_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + SPI_MEM_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + SPI_MEM_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + SPI_MEM_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + SPI_MEM_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + SPI_MEM_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + SPI_MEM_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + SPI_MEM_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + SPI_MEM_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + SPI_MEM_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + SPI_MEM_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + SPI_MEM_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + SPI_MEM_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00050001 + + + SPI_MEM_WAITI_EN + 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported. + 0 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY + The dummy phase enable when wait flash idle (RDSR) + 1 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_EN + 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer. + 2 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_CYCLELEN + When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared. + 3 + 2 + read-write + + + SPI_MEM_WAITI_CMD_2B + 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + 9 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + SPI_MEM_WAITI_CMD + The command value to wait flash idle(RDSR). + 16 + 16 + read-write + + + + + SPI_MEM_FLASH_SUS_CTRL + SPI1 flash suspend control register + 0x9C + 0x20 + 0x08002000 + + + SPI_MEM_FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + SPI_MEM_FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + SPI_MEM_FLASH_PER_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_PES_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. + 3 + 1 + read-write + + + SPI_MEM_PES_PER_EN + Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PES_EN + Set this bit to enable Auto-suspending function. + 5 + 1 + read-write + + + SPI_MEM_PESR_END_MSK + The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. + 6 + 16 + read-write + + + SPI_FMEM_RD_SUS_2B + 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit + 22 + 1 + read-write + + + SPI_MEM_PER_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. + 23 + 1 + read-write + + + SPI_MEM_PES_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. + 24 + 1 + read-write + + + SPI_MEM_SUS_TIMEOUT_CNT + When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. + 25 + 7 + read-write + + + + + SPI_MEM_FLASH_SUS_CMD + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x00057575 + + + SPI_MEM_FLASH_PES_COMMAND + Program/Erase suspend command. + 0 + 16 + read-write + + + SPI_MEM_WAIT_PESR_COMMAND + Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + 16 + 16 + read-write + + + + + SPI_MEM_SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + 0x7A7A0000 + + + SPI_MEM_FLASH_SUS + The status of flash suspend, only used in SPI1. + 0 + 1 + read-write + + + SPI_MEM_WAIT_PESR_CMD_2B + 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + 1 + 1 + read-write + + + SPI_MEM_FLASH_HPM_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_RES_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + SPI_MEM_FLASH_DP_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PER_DLY_128 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + SPI_MEM_FLASH_PES_DLY_128 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + SPI_MEM_SPI0_LOCK_EN + 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + 7 + 1 + read-write + + + SPI_MEM_FLASH_PESR_CMD_2B + 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8. + 15 + 1 + read-write + + + SPI_MEM_FLASH_PER_COMMAND + Program/Erase resume command. + 16 + 16 + read-write + + + + + SPI_MEM_INT_ENA + SPI1 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + SPI_MEM_PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + SPI_MEM_WPE_END_INT_ENA + The enable bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-write + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-write + + + + + SPI_MEM_INT_CLR + SPI1 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + SPI_MEM_PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + SPI_MEM_WPE_END_INT_CLR + The clear bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + write-only + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + write-only + + + + + SPI_MEM_INT_RAW + SPI1 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + 0 + 1 + read-write + + + SPI_MEM_PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + 1 + 1 + read-write + + + SPI_MEM_WPE_END_INT_RAW + The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. + 2 + 1 + read-write + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-write + + + SPI_MEM_BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 10 + 1 + read-write + + + + + SPI_MEM_INT_ST + SPI1 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + SPI_MEM_PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + SPI_MEM_WPE_END_INT_ST + The status bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-only + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-only + + + + + SPI_MEM_DDR + SPI1 DDR control register + 0xD4 + 0x20 + 0x00000020 + + + SPI_FMEM_DDR_EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-only + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi ddr mode. + 1 + 1 + read-only + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi ddr mode. + 2 + 1 + read-only + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi ddr mode. + 3 + 1 + read-only + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when ddr mode. + 4 + 1 + read-only + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-only + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-only + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-only + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-only + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-only + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-only + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-only + + + + + SPI_MEM_TIMING_CALI + SPI1 timing control register + 0x180 + 0x20 + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + + + SPI_MEM_CLOCK_GATE + SPI1 clk_gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_MEM_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_DATE + Version control register + 0x3FC + 0x20 + 0x02202160 + + + SPI_MEM_DATE + Version control register + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller 2 + SPI2 + 0x60081000 + + 0x0 + 0x98 + registers + + + MSPI + 40 + + + SPI2 + 72 + + + + CMD + Command control register + 0x0 + 0x20 + + + CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + ADDR + Address value register + 0x4 + 0x20 + + + USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-only + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-only + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-only + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-only + + + TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-only + + + USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-only + + + DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-only + + + ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-only + + + CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-only + + + SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-only + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-only + + + DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 10 + 2 + read-only + + + DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 2 + read-only + + + DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 14 + 2 + read-only + + + TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-only + + + DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-only + + + DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-only + + + DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-only + + + + + DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-only + + + DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-only + + + DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-only + + + DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-only + + + D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-only + + + + + DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-write + + + SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-write + + + SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-write + + + SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-write + + + SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-write + + + TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-write + + + APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-write + + + APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-write + + + + + DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + MST_FD_WAIT_DMA_TX_DATA + In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. + 29 + 1 + read-write + + + + + SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + DATE + Version control + 0xF0 + 0x20 + 0x02201300 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x6000A000 + + 0x0 + 0x90 + registers + + + SYSTIMER_TARGET0 + 57 + + + SYSTIMER_TARGET1 + 58 + + + SYSTIMER_TARGET2 + 59 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + ETM_EN + enable systimer's etm task and event + 1 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-write + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-write + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-write + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + REAL_TARGET0_LO + system timer comp0 actual target value low register + 0x74 + 0x20 + + + TARGET0_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET0_HI + system timer comp0 actual target value high register + 0x78 + 0x20 + + + TARGET0_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET1_LO + system timer comp1 actual target value low register + 0x7C + 0x20 + + + TARGET1_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET1_HI + system timer comp1 actual target value high register + 0x80 + 0x20 + + + TARGET1_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET2_LO + system timer comp2 actual target value low register + 0x84 + 0x20 + + + TARGET2_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET2_HI + system timer comp2 actual target value high register + 0x88 + 0x20 + + + TARGET2_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02201073 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TEE + TEE Peripheral + TEE + 0x60098000 + + 0x0 + 0x88 + registers + + + + M0_MODE_CTRL + Tee mode control register + 0x0 + 0x20 + + + M0_MODE + M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M1_MODE_CTRL + Tee mode control register + 0x4 + 0x20 + 0x00000003 + + + M1_MODE + M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M2_MODE_CTRL + Tee mode control register + 0x8 + 0x20 + + + M2_MODE + M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M3_MODE_CTRL + Tee mode control register + 0xC + 0x20 + 0x00000003 + + + M3_MODE + M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M4_MODE_CTRL + Tee mode control register + 0x10 + 0x20 + 0x00000003 + + + M4_MODE + M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M5_MODE_CTRL + Tee mode control register + 0x14 + 0x20 + 0x00000003 + + + M5_MODE + M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M6_MODE_CTRL + Tee mode control register + 0x18 + 0x20 + 0x00000003 + + + M6_MODE + M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M7_MODE_CTRL + Tee mode control register + 0x1C + 0x20 + 0x00000003 + + + M7_MODE + M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M8_MODE_CTRL + Tee mode control register + 0x20 + 0x20 + 0x00000003 + + + M8_MODE + M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M9_MODE_CTRL + Tee mode control register + 0x24 + 0x20 + 0x00000003 + + + M9_MODE + M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M10_MODE_CTRL + Tee mode control register + 0x28 + 0x20 + 0x00000003 + + + M10_MODE + M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M11_MODE_CTRL + Tee mode control register + 0x2C + 0x20 + 0x00000003 + + + M11_MODE + M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M12_MODE_CTRL + Tee mode control register + 0x30 + 0x20 + 0x00000003 + + + M12_MODE + M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M13_MODE_CTRL + Tee mode control register + 0x34 + 0x20 + 0x00000003 + + + M13_MODE + M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M14_MODE_CTRL + Tee mode control register + 0x38 + 0x20 + 0x00000003 + + + M14_MODE + M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M15_MODE_CTRL + Tee mode control register + 0x3C + 0x20 + 0x00000003 + + + M15_MODE + M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M16_MODE_CTRL + Tee mode control register + 0x40 + 0x20 + 0x00000003 + + + M16_MODE + M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M17_MODE_CTRL + Tee mode control register + 0x44 + 0x20 + 0x00000003 + + + M17_MODE + M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M18_MODE_CTRL + Tee mode control register + 0x48 + 0x20 + 0x00000003 + + + M18_MODE + M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M19_MODE_CTRL + Tee mode control register + 0x4C + 0x20 + 0x00000003 + + + M19_MODE + M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M20_MODE_CTRL + Tee mode control register + 0x50 + 0x20 + 0x00000003 + + + M20_MODE + M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M21_MODE_CTRL + Tee mode control register + 0x54 + 0x20 + 0x00000003 + + + M21_MODE + M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M22_MODE_CTRL + Tee mode control register + 0x58 + 0x20 + 0x00000003 + + + M22_MODE + M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M23_MODE_CTRL + Tee mode control register + 0x5C + 0x20 + 0x00000003 + + + M23_MODE + M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M24_MODE_CTRL + Tee mode control register + 0x60 + 0x20 + 0x00000003 + + + M24_MODE + M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M25_MODE_CTRL + Tee mode control register + 0x64 + 0x20 + 0x00000003 + + + M25_MODE + M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M26_MODE_CTRL + Tee mode control register + 0x68 + 0x20 + 0x00000003 + + + M26_MODE + M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M27_MODE_CTRL + Tee mode control register + 0x6C + 0x20 + 0x00000003 + + + M27_MODE + M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M28_MODE_CTRL + Tee mode control register + 0x70 + 0x20 + 0x00000003 + + + M28_MODE + M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M29_MODE_CTRL + Tee mode control register + 0x74 + 0x20 + 0x00000003 + + + M29_MODE + M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M30_MODE_CTRL + Tee mode control register + 0x78 + 0x20 + 0x00000003 + + + M30_MODE + M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M31_MODE_CTRL + Tee mode control register + 0x7C + 0x20 + 0x00000003 + + + M31_MODE + M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + CLOCK_GATE + Clock gating register + 0x80 + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0xFFC + 0x20 + 0x02205282 + + + DATE + reg_tee_date + 0 + 28 + read-write + + + + + + + TIMG0 + Timer Group 0 + TIMG + 0x60008000 + + 0x0 + 0x68 + registers + + + TG0_T0_LEVEL + 51 + + + TG0_T1_LEVEL + 52 + + + TG0_WDT_LEVEL + 53 + + + + T0CONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + DIVCNT_RST + When set, Timer %s 's clock divider counter will be reset. + 12 + 1 + write-only + + + DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + T0LO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + T0HI + Timer %s current value, high 22 bits + 0x8 + 0x20 + + + HI + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. + 0 + 22 + read-only + + + + + T0UPDATE + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + 0xC + 0x20 + + + UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + T0ALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + T0ALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + ALARM_HI + Timer %s alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + T0LOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base +Counter. + 0 + 32 + read-write + + + + + T0LOADHI + Timer %s reload value, high 22 bits + 0x1C + 0x20 + + + LOAD_HI + High 22 bits of the value that a reload will load onto timer %s time-base +counter. + 0 + 22 + read-write + + + + + T0LOAD + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + 0x20 + 0x20 + + + LOAD + Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + WDT reset CPU enable. + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_USE_XTAL + choose WDT clock:0-apb_clk, 1-xtal_clk. + 21 + 1 + read-write + + + WDT_CONF_UPDATE_EN + update the WDT configuration registers + 22 + 1 + write-only + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_DIVCNT_RST + When set, WDT 's clock divider counter will be reset. + 0 + 1 + write-only + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. (WO) + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configure register + 0x68 + 0x20 + 0x00011000 + + + RTC_CALI_START_CYCLING + 0: one-shot frequency calculation,1: periodic frequency calculation, + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + 13 + 2 + read-write + + + RTC_CALI_RDY + indicate one-shot frequency calculation is done. + 15 + 1 + read-only + + + RTC_CALI_MAX + Configure the time to calculate RTC slow clock's frequency. + 16 + 15 + read-write + + + RTC_CALI_START + Set this bit to start one-shot frequency calculation. + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + indicate periodic frequency calculation is done. + 0 + 1 + read-only + + + RTC_CALI_VALUE + When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency. + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-only + + + + + INT_ST_TIMERS + Masked interrupt status + 0x78 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0x7C + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 1 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02206072 + + + NTIMGS_DATE + Timer version control register + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + 0x70000000 + + + ETM_EN + enable timer's etm task and event + 28 + 1 + read-write + + + WDT_CLK_IS_ACTIVE + enable WDT's clock + 29 + 1 + read-write + + + TIMER_CLK_IS_ACTIVE + enable Timer 30's clock + 30 + 1 + read-write + + + CLK_EN + Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group 1 + 0x60009000 + + TG1_T0_LEVEL + 54 + + + TG1_T1_LEVEL + 55 + + + TG1_WDT_LEVEL + 56 + + + + TRACE + RISC-V Trace Encoder + TRACE + 0x600C0000 + + 0x0 + 0x30 + registers + + + TRACE + 27 + + + + MEM_START_ADDR + mem start addr + 0x0 + 0x20 + + + MEM_STAET_ADDR + The start address of trace memory + 0 + 32 + read-write + + + + + MEM_END_ADDR + mem end addr + 0x4 + 0x20 + 0xFFFFFFFF + + + MEM_END_ADDR + The end address of trace memory + 0 + 32 + read-write + + + + + MEM_CURRENT_ADDR + mem current addr + 0x8 + 0x20 + + + MEM_CURRENT_ADDR + current_mem_addr,indicate that next writing addr + 0 + 32 + read-only + + + + + MEM_ADDR_UPDATE + mem addr update + 0xC + 0x20 + + + MEM_CURRENT_ADDR_UPDATE + when set this reg, the current_mem_addr will update to start_addr + 0 + 1 + write-only + + + + + FIFO_STATUS + fifo status register + 0x10 + 0x20 + 0x00000001 + + + FIFO_EMPTY + 1 indicate that fifo is empty + 0 + 1 + read-only + + + WORK_STATUS + mem_full interrupt status + 1 + 1 + read-only + + + + + INTR_ENA + interrupt enable register + 0x14 + 0x20 + + + FIFO_OVERFLOW_INTR_ENA + Set 1 enable fifo_overflow interrupt + 0 + 1 + read-write + + + MEM_FULL_INTR_ENA + Set 1 enable mem_full interrupt + 1 + 1 + read-write + + + + + INTR_RAW + interrupt status register + 0x18 + 0x20 + + + FIFO_OVERFLOW_INTR_RAW + fifo_overflow interrupt status + 0 + 1 + read-only + + + MEM_FULL_INTR_RAW + mem_full interrupt status + 1 + 1 + read-only + + + + + INTR_CLR + interrupt clear register + 0x1C + 0x20 + + + FIFO_OVERFLOW_INTR_CLR + Set 1 clr fifo overflow interrupt + 0 + 1 + write-only + + + MEM_FULL_INTR_CLR + Set 1 clr mem full interrupt + 1 + 1 + write-only + + + + + TRIGGER + trigger register + 0x20 + 0x20 + 0x0000000C + + + ON + [0] set 1 start trace. + 0 + 1 + write-only + + + OFF + set 1 stop trace. + 1 + 1 + write-only + + + MEM_LOOP + if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr + 2 + 1 + read-write + + + RESTART_ENA + enable encoder auto-restart, when lost package, the encoder will end, if enable auto-restart, when fifo empty, encoder will restart and send a sync package. + 3 + 1 + read-write + + + + + RESYNC_PROLONGED + resync configuration register + 0x24 + 0x20 + 0x00000080 + + + RESYNC_PROLONGED + count number, when count to this value, send a sync package + 0 + 24 + read-write + + + RESYNC_MODE + resyc mode sel: 0: default, cycle count 1: package num count + 24 + 1 + read-write + + + + + CLOCK_GATE + Clock gate control register + 0x28 + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02203030 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + + + TWAI0 + Two-Wire Automotive Interface + TWAI + 0x6000B000 + + 0x0 + 0x80 + registers + + + TWAI0 + 46 + + + + MODE + TWAI mode register. + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission. + 2 + 1 + read-write + + + RX_FILTER_MODE + 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active). + 3 + 1 + read-write + + + + + CMD + TWAI command register. + 0x4 + 0x20 + + + TX_REQ + 1: present, a message shall be transmitted. 0: absent + 0 + 1 + write-only + + + ABORT_TX + 1: present, if not already in progress, a pending transmission request is cancelled. 0: absent + 1 + 1 + write-only + + + RELEASE_BUF + 1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action + 2 + 1 + write-only + + + CLEAR_DATA_OVERRUN + 1: clear, the data overrun status bit is cleared. 0: no action. + 3 + 1 + write-only + + + SELF_RX_REQUEST + 1: present, a message shall be transmitted and received simultaneously. 0: absent. + 4 + 1 + write-only + + + + + STATUS + TWAI status register. + 0x8 + 0x20 + + + RX_BUF_ST + 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available + 0 + 1 + read-only + + + OVERRUN + 1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given + 1 + 1 + read-only + + + TX_BUF_ST + 1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted + 2 + 1 + read-only + + + TRANSMISSION_COMPLETE + 1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed + 3 + 1 + read-only + + + RECEIVE + 1: receive, the TWAI controller is receiving a message. 0: idle + 4 + 1 + read-only + + + TRANSMIT + 1: transmit, the TWAI controller is transmitting a message. 0: idle + 5 + 1 + read-only + + + ERR + 1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit + 6 + 1 + read-only + + + BUS_OFF_ST + 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities + 7 + 1 + read-only + + + MISS_ST + 1: current message is destroyed because of FIFO overflow. + 8 + 1 + read-only + + + + + INTERRUPT + Interrupt signals' register. + 0xC + 0x20 + + + RECEIVE_INT_ST + 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset + 0 + 1 + read-only + + + TRANSMIT_INT_ST + 1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset + 1 + 1 + read-only + + + ERR_WARNING_INT_ST + 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset + 2 + 1 + read-only + + + DATA_OVERRUN_INT_ST + 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset + 3 + 1 + read-only + + + ERR_PASSIVE_INT_ST + 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset + 5 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset + 6 + 1 + read-only + + + BUS_ERR_INT_ST + 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset + 7 + 1 + read-only + + + IDLE_INT_ST + 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset + 8 + 1 + read-only + + + + + INTERRUPT_ENABLE + Interrupt enable register. + 0x10 + 0x20 + + + EXT_RECEIVE_INT_ENA + 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable + 0 + 1 + read-write + + + EXT_TRANSMIT_INT_ENA + 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable + 1 + 1 + read-write + + + EXT_ERR_WARNING_INT_ENA + 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 2 + 1 + read-write + + + EXT_DATA_OVERRUN_INT_ENA + 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 3 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable + 5 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable + 7 + 1 + read-write + + + IDLE_INT_ENA + 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable + 8 + 1 + read-only + + + + + BUS_TIMING_0 + Bit timing configuration register 0. + 0x18 + 0x20 + + + BAUD_PRESC + The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. + 14 + 2 + read-write + + + + + BUS_TIMING_1 + Bit timing configuration register 1. + 0x1C + 0x20 + + + TIME_SEG1 + The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 0 + 4 + read-write + + + TIME_SEG2 + The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 4 + 3 + read-write + + + TIME_SAMP + 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode. + 7 + 1 + read-write + + + + + ARB_LOST_CAP + TWAI arbiter lost capture register. + 0x2C + 0x20 + + + ARBITRATION_LOST_CAPTURE + This register contains information about the bit position of losing arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + TWAI error info capture register. + 0x30 + 0x20 + + + ERR_CAPTURE_CODE_SEGMENT + This register contains information about the location of errors on the bus. + 0 + 5 + read-only + + + ERR_CAPTURE_CODE_DIRECTION + 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + 5 + 1 + read-only + + + ERR_CAPTURE_CODE_TYPE + 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + TWAI error threshold configuration register. + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + RX_ERR_CNT + Rx error counter register. + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + TX_ERR_CNT + Tx error counter register. + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + DATA_0 + Data register 0. + 0x40 + 0x20 + + + TX_BYTE_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0. + 0 + 8 + read-write + + + + + DATA_1 + Data register 1. + 0x44 + 0x20 + + + TX_BYTE_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1. + 0 + 8 + read-write + + + + + DATA_2 + Data register 2. + 0x48 + 0x20 + + + TX_BYTE_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2. + 0 + 8 + read-write + + + + + DATA_3 + Data register 3. + 0x4C + 0x20 + + + TX_BYTE_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3. + 0 + 8 + read-write + + + + + DATA_4 + Data register 4. + 0x50 + 0x20 + + + TX_BYTE_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4. + 0 + 8 + read-write + + + + + DATA_5 + Data register 5. + 0x54 + 0x20 + + + TX_BYTE_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5. + 0 + 8 + read-write + + + + + DATA_6 + Data register 6. + 0x58 + 0x20 + + + TX_BYTE_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6. + 0 + 8 + read-write + + + + + DATA_7 + Data register 7. + 0x5C + 0x20 + + + TX_BYTE_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7. + 0 + 8 + read-write + + + + + DATA_8 + Data register 8. + 0x60 + 0x20 + + + TX_BYTE_8 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8. + 0 + 8 + read-write + + + + + DATA_9 + Data register 9. + 0x64 + 0x20 + + + DATA_9 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9. + 0 + 8 + read-write + + + + + DATA_10 + Data register 10. + 0x68 + 0x20 + + + TX_BYTE_10 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10. + 0 + 8 + read-write + + + + + DATA_11 + Data register 11. + 0x6C + 0x20 + + + TX_BYTE_11 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11. + 0 + 8 + read-write + + + + + DATA_12 + Data register 12. + 0x70 + 0x20 + + + TX_BYTE_12 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12. + 0 + 8 + read-write + + + + + RX_MESSAGE_CNT + Received message counter register. + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock divider register. + 0x7C + 0x20 + + + CD + These bits are used to define the frequency at the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode. + 8 + 1 + read-write + + + + + SW_STANDBY_CFG + Software configure standby pin directly. + 0x80 + 0x20 + 0x00000002 + + + SW_STANDBY_EN + Enable standby pin. + 0 + 1 + read-write + + + SW_STANDBY_CLR + Clear standby pin. + 1 + 1 + read-write + + + + + HW_CFG + Hardware configure standby pin. + 0x84 + 0x20 + + + HW_STANDBY_EN + Enable function that hardware control standby pin. + 0 + 1 + read-write + + + + + HW_STANDBY_CNT + Configure standby counter. + 0x88 + 0x20 + 0x00000001 + + + STANDBY_WAIT_CNT + Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. + 0 + 32 + read-write + + + + + IDLE_INTR_CNT + Configure idle interrupt counter. + 0x8C + 0x20 + 0x00000001 + + + IDLE_INTR_CNT + Configure the number of cycles before triggering idle interrupt. + 0 + 32 + read-write + + + + + ECO_CFG + ECO configuration register. + 0x90 + 0x20 + 0x00000002 + + + RDN_ENA + Enable eco module. + 0 + 1 + read-write + + + RDN_RESULT + Output of eco module. + 1 + 1 + read-only + + + + + + + TWAI1 + Two-Wire Automotive Interface + 0x6000D000 + + TWAI1 + 47 + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART + 0x60000000 + + 0x0 + 0x98 + registers + + + UART0 + 43 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-write + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-write + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-write + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-write + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-write + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-write + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-write + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-write + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-write + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-write + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-write + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-write + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 8 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 8 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0 + a + 0x20 + 0x20 + 0x0010001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 7 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 8 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 9 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 10 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 11 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 14 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 19 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 8 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 8 + 8 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 0 + 8 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001404F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 10 + 8 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0 + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x0000E000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 0 + 8 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 8 + 8 + read-write + + + + + TXBRK_CONF + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 0 + 8 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 9 + 8 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 0 + 8 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 9 + 8 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x74 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x78 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x7C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x80 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x84 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03701000 + + + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 + read-write + + + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. + 12 + 8 + read-write + + + SCLK_SEL + UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 + 1 + read-write + + + RST_CORE + Write 1 then write 0 to this bit to reset UART Tx/Rx. + 23 + 1 + read-write + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02201260 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + 0x60001000 + + UART1 + 44 + + + + UHCI0 + Universal Host Controller Interface 0 + UHCI + 0x60005000 + + 0x0 + 0x84 + registers + + + UHCI0 + 42 + + + + CONF0 + UHCI Configuration Register0 + 0x0 + 0x20 + 0x000006E0 + + + TX_RST + Write 1 then write 0 to this bit to reset decode state machine. + 0 + 1 + read-write + + + RX_RST + Write 1 then write 0 to this bit to reset encode state machine. + 1 + 1 + read-write + + + UART0_CE + Set this bit to link up HCI and UART0. + 2 + 1 + read-write + + + UART1_CE + Set this bit to link up HCI and UART1. + 3 + 1 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. + 8 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. + 9 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + 10 + 1 + read-write + + + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. + 11 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + + + + + INT_RAW + UHCI Interrupt Raw Register + 0x4 + 0x20 + + + RX_START_INT_RAW + Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully. + 0 + 1 + read-write + + + TX_START_INT_RAW + Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter. + 1 + 1 + read-write + + + RX_HUNG_INT_RAW + Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value. + 2 + 1 + read-write + + + TX_HUNG_INT_RAW + Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_RAW + Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_RAW + Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode. + 5 + 1 + read-write + + + OUT_EOF_INT_RAW + Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF. + 6 + 1 + read-write + + + APP_CTRL0_INT_RAW + Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1. + 7 + 1 + read-write + + + APP_CTRL1_INT_RAW + Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1. + 8 + 1 + read-write + + + + + INT_ST + UHCI Interrupt Status Register + 0x8 + 0x20 + + + RX_START_INT_ST + Indicates the interrupt status of UHCI_RX_START_INT. + 0 + 1 + read-only + + + TX_START_INT_ST + Indicates the interrupt status of UHCI_TX_START_INT. + 1 + 1 + read-only + + + RX_HUNG_INT_ST + Indicates the interrupt status of UHCI_RX_HUNG_INT. + 2 + 1 + read-only + + + TX_HUNG_INT_ST + Indicates the interrupt status of UHCI_TX_HUNG_INT. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + Indicates the interrupt status of UHCI_OUT_EOF_INT. + 6 + 1 + read-only + + + APP_CTRL0_INT_ST + Indicates the interrupt status of UHCI_APP_CTRL0_INT. + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + Indicates the interrupt status of UHCI_APP_CTRL1_INT. + 8 + 1 + read-only + + + + + INT_ENA + UHCI Interrupt Enable Register + 0xC + 0x20 + + + RX_START_INT_ENA + Set this bit to enable the interrupt of UHCI_RX_START_INT. + 0 + 1 + read-write + + + TX_START_INT_ENA + Set this bit to enable the interrupt of UHCI_TX_START_INT. + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + 6 + 1 + read-write + + + APP_CTRL0_INT_ENA + Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + 7 + 1 + read-write + + + APP_CTRL1_INT_ENA + Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + 8 + 1 + read-write + + + + + INT_CLR + UHCI Interrupt Clear Register + 0x10 + 0x20 + + + RX_START_INT_CLR + Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + 0 + 1 + write-only + + + TX_START_INT_CLR + Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + 3 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + 6 + 1 + write-only + + + APP_CTRL0_INT_CLR + Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + 7 + 1 + write-only + + + APP_CTRL1_INT_CLR + Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + 8 + 1 + write-only + + + + + CONF1 + UHCI Configuration Register1 + 0x14 + 0x20 + 0x00000033 + + + CHECK_SUM_EN + Set this bit to enable head checksum check when receiving. + 0 + 1 + read-write + + + CHECK_SEQ_EN + Set this bit to enable sequence number check when receiving. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to support CRC calculation, and data integrity check bit should 1. + 2 + 1 + read-write + + + SAVE_HEAD + Set this bit to save data packet head when UHCI receive data. + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + Set this bit to encode data packet with checksum. + 4 + 1 + read-write + + + TX_ACK_NUM_RE + Set this bit to encode data packet with ACK when reliable data packet is ready. + 5 + 1 + read-write + + + WAIT_SW_START + Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + 7 + 1 + read-write + + + SW_START + Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + 8 + 1 + write-only + + + + + STATE0 + UHCI Receive Status Register + 0x18 + 0x20 + + + RX_ERR_CAUSE + Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error. + 0 + 3 + read-only + + + DECODE_STATE + Indicates UHCI decoder status. + 3 + 3 + read-only + + + + + STATE1 + UHCI Transmit Status Register + 0x1C + 0x20 + + + ENCODE_STATE + Indicates UHCI encoder status. + 0 + 3 + read-only + + + + + ESCAPE_CONF + UHCI Escapes Configuration Register0 + 0x20 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to enable resolve char 0xC0 when DMA receiving data. + 0 + 1 + read-write + + + TX_DB_ESC_EN + Set this bit to enable resolve char 0xDB when DMA receiving data. + 1 + 1 + read-write + + + TX_11_ESC_EN + Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + 2 + 1 + read-write + + + TX_13_ESC_EN + Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + 3 + 1 + read-write + + + RX_C0_ESC_EN + Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + 4 + 1 + read-write + + + RX_DB_ESC_EN + Set this bit to enable replacing 0xDB with special char when DMA receiving data. + 5 + 1 + read-write + + + RX_11_ESC_EN + Set this bit to enable replacing 0x11 with special char when DMA receiving data. + 6 + 1 + read-write + + + RX_13_ESC_EN + Set this bit to enable replacing 0x13 with special char when DMA receiving data. + 7 + 1 + read-write + + + + + HUNG_CONF + UHCI Hung Configuration Register0 + 0x24 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data. + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + Configures the maximum counter value. + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + Set this bit to enable TX FIFO timeout when receiving. + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data. + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + Configures the maximum counter value. + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + Set this bit to enable TX FIFO timeout when DMA sending data. + 23 + 1 + read-write + + + + + ACK_NUM + UHCI Ack Value Configuration Register0 + 0x28 + 0x20 + + + ACK_NUM + Indicates the ACK number during software flow control. + 0 + 3 + read-write + + + LOAD + Set this bit to load the ACK value of UHCI_ACK_NUM. + 3 + 1 + write-only + + + + + RX_HEAD + UHCI Head Register + 0x2C + 0x20 + + + RX_HEAD + Stores the head of received packet. + 0 + 32 + read-only + + + + + QUICK_SENT + UCHI Quick send Register + 0x30 + 0x20 + + + SINGLE_SEND_NUM + Configures single_send mode. + 0 + 3 + read-write + + + SINGLE_SEND_EN + Set this bit to enable sending short packet with single_send mode. + 3 + 1 + write-only + + + ALWAYS_SEND_NUM + Configures always_send mode. + 4 + 3 + read-write + + + ALWAYS_SEND_EN + Set this bit to enable sending short packet with always_send mode. + 7 + 1 + read-write + + + + + REG_Q0_WORD0 + UHCI Q0_WORD0 Quick Send Register + 0x34 + 0x20 + + + SEND_Q0_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q0_WORD1 + UHCI Q0_WORD1 Quick Send Register + 0x38 + 0x20 + + + SEND_Q0_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD0 + UHCI Q1_WORD0 Quick Send Register + 0x3C + 0x20 + + + SEND_Q1_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD1 + UHCI Q1_WORD1 Quick Send Register + 0x40 + 0x20 + + + SEND_Q1_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD0 + UHCI Q2_WORD0 Quick Send Register + 0x44 + 0x20 + + + SEND_Q2_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD1 + UHCI Q2_WORD1 Quick Send Register + 0x48 + 0x20 + + + SEND_Q2_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD0 + UHCI Q3_WORD0 Quick Send Register + 0x4C + 0x20 + + + SEND_Q3_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD1 + UHCI Q3_WORD1 Quick Send Register + 0x50 + 0x20 + + + SEND_Q3_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD0 + UHCI Q4_WORD0 Quick Send Register + 0x54 + 0x20 + + + SEND_Q4_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD1 + UHCI Q4_WORD1 Quick Send Register + 0x58 + 0x20 + + + SEND_Q4_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD0 + UHCI Q5_WORD0 Quick Send Register + 0x5C + 0x20 + + + SEND_Q5_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD1 + UHCI Q5_WORD1 Quick Send Register + 0x60 + 0x20 + + + SEND_Q5_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD0 + UHCI Q6_WORD0 Quick Send Register + 0x64 + 0x20 + + + SEND_Q6_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD1 + UHCI Q6_WORD1 Quick Send Register + 0x68 + 0x20 + + + SEND_Q6_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + ESC_CONF0 + UHCI Escapes Sequence Configuration Register0 + 0x6C + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + Configures the delimiter for encoding, default value is 0xC0. + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDC. + 16 + 8 + read-write + + + + + ESC_CONF1 + UHCI Escapes Sequence Configuration Register1 + 0x70 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + Configures the char needing encoding, which is 0xDB as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDD. + 16 + 8 + read-write + + + + + ESC_CONF2 + UHCI Escapes Sequence Configuration Register2 + 0x74 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + Configures the char needing encoding, which is 0x11 as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDE. + 16 + 8 + read-write + + + + + ESC_CONF3 + UHCI Escapes Sequence Configuration Register3 + 0x78 + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + Configures the char needing encoding, which is 0x13 as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDF. + 16 + 8 + read-write + + + + + PKT_THRES + UCHI Packet Length Configuration Register + 0x7C + 0x20 + 0x00000080 + + + PKT_THRS + Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + 0 + 13 + read-write + + + + + DATE + UHCI Version Register + 0x80 + 0x20 + 0x02201100 + + + DATE + Configures version. + 0 + 32 + read-write + + + + + + + USB_DEVICE + Full-speed USB Serial/JTAG Controller + USB_DEVICE + 0x6000F000 + + 0x0 + 0x70 + registers + + + USB_DEVICE + 48 + + + + EP1 + FIFO access for the CDC-ACM data IN and OUT endpoints. + 0x0 + 0x20 + + + RDWR_BYTE + Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. + 0 + 8 + read-write + + + + + EP1_CONF + Configuration and control registers for the CDC-ACM FIFOs. + 0x4 + 0x20 + 0x00000002 + + + WR_DONE + Set this bit to indicate writing byte data to UART Tx FIFO is done. + 0 + 1 + write-only + + + SERIAL_IN_EP_DATA_FREE + 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. + 1 + 1 + read-only + + + SERIAL_OUT_EP_DATA_AVAIL + 1'b1: Indicate there is data in UART Rx FIFO. + 2 + 1 + read-only + + + + + INT_RAW + Interrupt raw status register. + 0x8 + 0x20 + 0x00000008 + + + JTAG_IN_FLUSH_INT_RAW + The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + 0 + 1 + read-write + + + SOF_INT_RAW + The raw interrupt bit turns to high level when SOF frame is received. + 1 + 1 + read-write + + + SERIAL_OUT_RECV_PKT_INT_RAW + The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + 2 + 1 + read-write + + + SERIAL_IN_EMPTY_INT_RAW + The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + 3 + 1 + read-write + + + PID_ERR_INT_RAW + The raw interrupt bit turns to high level when pid error is detected. + 4 + 1 + read-write + + + CRC5_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC5 error is detected. + 5 + 1 + read-write + + + CRC16_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC16 error is detected. + 6 + 1 + read-write + + + STUFF_ERR_INT_RAW + The raw interrupt bit turns to high level when stuff error is detected. + 7 + 1 + read-write + + + IN_TOKEN_REC_IN_EP1_INT_RAW + The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + 8 + 1 + read-write + + + USB_BUS_RESET_INT_RAW + The raw interrupt bit turns to high level when usb bus reset is detected. + 9 + 1 + read-write + + + OUT_EP1_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + 10 + 1 + read-write + + + OUT_EP2_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + 11 + 1 + read-write + + + RTS_CHG_INT_RAW + The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. + 12 + 1 + read-write + + + DTR_CHG_INT_RAW + The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. + 13 + 1 + read-write + + + GET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of GET LINE CODING request is received. + 14 + 1 + read-write + + + SET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of SET LINE CODING request is received. + 15 + 1 + read-write + + + + + INT_ST + Interrupt status register. + 0xC + 0x20 + + + JTAG_IN_FLUSH_INT_ST + The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-only + + + SOF_INT_ST + The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-only + + + SERIAL_OUT_RECV_PKT_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-only + + + SERIAL_IN_EMPTY_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-only + + + PID_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-only + + + CRC5_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-only + + + CRC16_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-only + + + STUFF_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-only + + + IN_TOKEN_REC_IN_EP1_INT_ST + The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-only + + + USB_BUS_RESET_INT_ST + The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-only + + + OUT_EP1_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-only + + + OUT_EP2_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-only + + + RTS_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-only + + + DTR_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-only + + + GET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-only + + + SET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-only + + + + + INT_ENA + Interrupt enable status register. + 0x10 + 0x20 + + + JTAG_IN_FLUSH_INT_ENA + The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-write + + + SOF_INT_ENA + The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-write + + + SERIAL_OUT_RECV_PKT_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-write + + + SERIAL_IN_EMPTY_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-write + + + PID_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-write + + + CRC5_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-write + + + CRC16_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-write + + + STUFF_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-write + + + IN_TOKEN_REC_IN_EP1_INT_ENA + The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-write + + + USB_BUS_RESET_INT_ENA + The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-write + + + OUT_EP1_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-write + + + OUT_EP2_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-write + + + RTS_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-write + + + DTR_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-write + + + GET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-write + + + SET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-write + + + + + INT_CLR + Interrupt clear status register. + 0x14 + 0x20 + + + JTAG_IN_FLUSH_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + write-only + + + SOF_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + 1 + 1 + write-only + + + SERIAL_OUT_RECV_PKT_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + write-only + + + SERIAL_IN_EMPTY_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + write-only + + + PID_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + write-only + + + CRC5_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + write-only + + + CRC16_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + write-only + + + STUFF_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + write-only + + + IN_TOKEN_REC_IN_EP1_INT_CLR + Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + 8 + 1 + write-only + + + USB_BUS_RESET_INT_CLR + Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + write-only + + + OUT_EP1_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + write-only + + + OUT_EP2_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + write-only + + + RTS_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + write-only + + + DTR_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + write-only + + + GET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + write-only + + + SET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + write-only + + + + + CONF0 + PHY hardware configuration. + 0x18 + 0x20 + 0x00004200 + + + PHY_SEL + Select internal/external PHY + 0 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software control USB D+ D- exchange + 1 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange + 2 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 3 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 5 + 2 + read-write + + + VREF_OVERRIDE + Enable software control input threshold + 7 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software control USB D+ D- pullup pulldown + 8 + 1 + read-write + + + DP_PULLUP + Control USB D+ pull up. + 9 + 1 + read-write + + + DP_PULLDOWN + Control USB D+ pull down. + 10 + 1 + read-write + + + DM_PULLUP + Control USB D- pull up. + 11 + 1 + read-write + + + DM_PULLDOWN + Control USB D- pull down. + 12 + 1 + read-write + + + PULLUP_VALUE + Control pull up value. + 13 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function. + 14 + 1 + read-write + + + USB_JTAG_BRIDGE_EN + Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. + 15 + 1 + read-write + + + + + TEST + Registers used for debugging the PHY. + 0x1C + 0x20 + 0x00000030 + + + TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + TEST_RX_RCV + USB RCV value in test + 4 + 1 + read-only + + + TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + JFIFO_ST + JTAG FIFO status and control registers. + 0x20 + 0x20 + 0x00000044 + + + IN_FIFO_CNT + JTAT in fifo counter. + 0 + 2 + read-only + + + IN_FIFO_EMPTY + 1: JTAG in fifo is empty. + 2 + 1 + read-only + + + IN_FIFO_FULL + 1: JTAG in fifo is full. + 3 + 1 + read-only + + + OUT_FIFO_CNT + JTAT out fifo counter. + 4 + 2 + read-only + + + OUT_FIFO_EMPTY + 1: JTAG out fifo is empty. + 6 + 1 + read-only + + + OUT_FIFO_FULL + 1: JTAG out fifo is full. + 7 + 1 + read-only + + + IN_FIFO_RESET + Write 1 to reset JTAG in fifo. + 8 + 1 + read-write + + + OUT_FIFO_RESET + Write 1 to reset JTAG out fifo. + 9 + 1 + read-write + + + + + FRAM_NUM + Last received SOF frame index register. + 0x24 + 0x20 + + + SOF_FRAME_INDEX + Frame index of received SOF frame. + 0 + 11 + read-only + + + + + IN_EP0_ST + Control IN endpoint status information. + 0x28 + 0x20 + 0x00000001 + + + IN_EP0_STATE + State of IN Endpoint 0. + 0 + 2 + read-only + + + IN_EP0_WR_ADDR + Write data address of IN endpoint 0. + 2 + 7 + read-only + + + IN_EP0_RD_ADDR + Read data address of IN endpoint 0. + 9 + 7 + read-only + + + + + IN_EP1_ST + CDC-ACM IN endpoint status information. + 0x2C + 0x20 + 0x00000001 + + + IN_EP1_STATE + State of IN Endpoint 1. + 0 + 2 + read-only + + + IN_EP1_WR_ADDR + Write data address of IN endpoint 1. + 2 + 7 + read-only + + + IN_EP1_RD_ADDR + Read data address of IN endpoint 1. + 9 + 7 + read-only + + + + + IN_EP2_ST + CDC-ACM interrupt IN endpoint status information. + 0x30 + 0x20 + 0x00000001 + + + IN_EP2_STATE + State of IN Endpoint 2. + 0 + 2 + read-only + + + IN_EP2_WR_ADDR + Write data address of IN endpoint 2. + 2 + 7 + read-only + + + IN_EP2_RD_ADDR + Read data address of IN endpoint 2. + 9 + 7 + read-only + + + + + IN_EP3_ST + JTAG IN endpoint status information. + 0x34 + 0x20 + 0x00000001 + + + IN_EP3_STATE + State of IN Endpoint 3. + 0 + 2 + read-only + + + IN_EP3_WR_ADDR + Write data address of IN endpoint 3. + 2 + 7 + read-only + + + IN_EP3_RD_ADDR + Read data address of IN endpoint 3. + 9 + 7 + read-only + + + + + OUT_EP0_ST + Control OUT endpoint status information. + 0x38 + 0x20 + + + OUT_EP0_STATE + State of OUT Endpoint 0. + 0 + 2 + read-only + + + OUT_EP0_WR_ADDR + Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + 2 + 7 + read-only + + + OUT_EP0_RD_ADDR + Read data address of OUT endpoint 0. + 9 + 7 + read-only + + + + + OUT_EP1_ST + CDC-ACM OUT endpoint status information. + 0x3C + 0x20 + + + OUT_EP1_STATE + State of OUT Endpoint 1. + 0 + 2 + read-only + + + OUT_EP1_WR_ADDR + Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + 2 + 7 + read-only + + + OUT_EP1_RD_ADDR + Read data address of OUT endpoint 1. + 9 + 7 + read-only + + + OUT_EP1_REC_DATA_CNT + Data count in OUT endpoint 1 when one packet is received. + 16 + 7 + read-only + + + + + OUT_EP2_ST + JTAG OUT endpoint status information. + 0x40 + 0x20 + + + OUT_EP2_STATE + State of OUT Endpoint 2. + 0 + 2 + read-only + + + OUT_EP2_WR_ADDR + Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + 2 + 7 + read-only + + + OUT_EP2_RD_ADDR + Read data address of OUT endpoint 2. + 9 + 7 + read-only + + + + + MISC_CONF + Clock enable control + 0x44 + 0x20 + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 0 + 1 + read-write + + + + + MEM_CONF + Memory power control + 0x48 + 0x20 + 0x00000002 + + + USB_MEM_PD + 1: power down usb memory. + 0 + 1 + read-write + + + USB_MEM_CLK_EN + 1: Force clock on for usb memory. + 1 + 1 + read-write + + + + + CHIP_RST + CDC-ACM chip reset control. + 0x4C + 0x20 + + + RTS + 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + 0 + 1 + read-only + + + DTR + 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + 1 + 1 + read-only + + + USB_UART_CHIP_RST_DIS + Set this bit to disable chip reset from usb serial channel to reset chip. + 2 + 1 + read-write + + + + + SET_LINE_CODE_W0 + W0 of SET_LINE_CODING command. + 0x50 + 0x20 + + + DW_DTE_RATE + The value of dwDTERate set by host through SET_LINE_CODING command. + 0 + 32 + read-only + + + + + SET_LINE_CODE_W1 + W1 of SET_LINE_CODING command. + 0x54 + 0x20 + + + BCHAR_FORMAT + The value of bCharFormat set by host through SET_LINE_CODING command. + 0 + 8 + read-only + + + BPARITY_TYPE + The value of bParityTpye set by host through SET_LINE_CODING command. + 8 + 8 + read-only + + + BDATA_BITS + The value of bDataBits set by host through SET_LINE_CODING command. + 16 + 8 + read-only + + + + + GET_LINE_CODE_W0 + W0 of GET_LINE_CODING command. + 0x58 + 0x20 + + + GET_DW_DTE_RATE + The value of dwDTERate set by software which is requested by GET_LINE_CODING command. + 0 + 32 + read-write + + + + + GET_LINE_CODE_W1 + W1 of GET_LINE_CODING command. + 0x5C + 0x20 + + + GET_BDATA_BITS + The value of bCharFormat set by software which is requested by GET_LINE_CODING command. + 0 + 8 + read-write + + + GET_BPARITY_TYPE + The value of bParityTpye set by software which is requested by GET_LINE_CODING command. + 8 + 8 + read-write + + + GET_BCHAR_FORMAT + The value of bDataBits set by software which is requested by GET_LINE_CODING command. + 16 + 8 + read-write + + + + + CONFIG_UPDATE + Configuration registers' value update + 0x60 + 0x20 + + + CONFIG_UPDATE + Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. + 0 + 1 + write-only + + + + + SER_AFIFO_CONFIG + Serial AFIFO configure register + 0x64 + 0x20 + 0x00000010 + + + SERIAL_IN_AFIFO_RESET_WR + Write 1 to reset CDC_ACM IN async FIFO write clock domain. + 0 + 1 + read-write + + + SERIAL_IN_AFIFO_RESET_RD + Write 1 to reset CDC_ACM IN async FIFO read clock domain. + 1 + 1 + read-write + + + SERIAL_OUT_AFIFO_RESET_WR + Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + 2 + 1 + read-write + + + SERIAL_OUT_AFIFO_RESET_RD + Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + 3 + 1 + read-write + + + SERIAL_OUT_AFIFO_REMPTY + CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + 4 + 1 + read-only + + + SERIAL_IN_AFIFO_WFULL + CDC_ACM OUT IN async FIFO empty signal in write clock domain. + 5 + 1 + read-only + + + + + BUS_RESET_ST + USB Bus reset status register + 0x68 + 0x20 + 0x00000001 + + + USB_BUS_RESET_ST + USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released. + 0 + 1 + read-only + + + + + DATE + Date register + 0x80 + 0x20 + 0x02109220 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + \ No newline at end of file diff --git a/.vscode/esp32s3.base.svd b/.vscode/esp32s3.base.svd index fd52ddda..b39bfacc 100644 --- a/.vscode/esp32s3.base.svd +++ b/.vscode/esp32s3.base.svd @@ -4,10 +4,9 @@ ESPRESSIF ESP32-S3 ESP32 S-Series - 16 + 20 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) - - Copyright 2023 Espressif Systems (Shanghai) PTE LTD + Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,15 +18,14 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. - + limitations under the License. Xtensa LX7 r0p0 little false true - 3 + 0 false 32 @@ -55,7 +53,7 @@ 0x20 - KEY_0 + KEY Stores AES keys. 0 32 @@ -72,7 +70,7 @@ 0x20 - TEXT_IN_0 + TEXT_IN Stores the source data when the AES accelerator operates in the Typical AES working mode. 0 32 @@ -89,7 +87,7 @@ 0x20 - TEXT_OUT_0 + TEXT_OUT Stores the result data when the AES accelerator operates in the Typical AES working mode. 0 32 @@ -2376,7 +2374,7 @@ - CORE_0_INTERRUPT_ENA + CORE_0_MONTR_ENA core0 monitor enable configuration register 0x0 0x20 @@ -2468,7 +2466,7 @@ - CORE_0_INTERRUPT_RAW + CORE_0_INTR_RAW core0 monitor interrupt status register 0x4 0x20 @@ -2560,90 +2558,90 @@ - CORE_0_INTERRUPT_RLS + CORE_0_INTR_ENA core0 monitor interrupt enable register 0x8 0x20 - CORE_0_AREA_DRAM0_0_RD_RLS + CORE_0_AREA_DRAM0_0_RD_INTR_ENA Core0 dram0 area0 read monitor interrupt enable 0 1 read-write - CORE_0_AREA_DRAM0_0_WR_RLS + CORE_0_AREA_DRAM0_0_WR_INTR_ENA Core0 dram0 area0 write monitor interrupt enable 1 1 read-write - CORE_0_AREA_DRAM0_1_RD_RLS + CORE_0_AREA_DRAM0_1_RD_INTR_ENA Core0 dram0 area1 read monitor interrupt enable 2 1 read-write - CORE_0_AREA_DRAM0_1_WR_RLS + CORE_0_AREA_DRAM0_1_WR_INTR_ENA Core0 dram0 area1 write monitor interrupt enable 3 1 read-write - CORE_0_AREA_PIF_0_RD_RLS + CORE_0_AREA_PIF_0_RD_INTR_ENA Core0 PIF area0 read monitor interrupt enable 4 1 read-write - CORE_0_AREA_PIF_0_WR_RLS + CORE_0_AREA_PIF_0_WR_INTR_ENA Core0 PIF area0 write monitor interrupt enable 5 1 read-write - CORE_0_AREA_PIF_1_RD_RLS + CORE_0_AREA_PIF_1_RD_INTR_ENA Core0 PIF area1 read monitor interrupt enable 6 1 read-write - CORE_0_AREA_PIF_1_WR_RLS + CORE_0_AREA_PIF_1_WR_INTR_ENA Core0 PIF area1 write monitor interrupt enable 7 1 read-write - CORE_0_SP_SPILL_MIN_RLS + CORE_0_SP_SPILL_MIN_INTR_ENA Core0 stackpoint overflow monitor interrupt enable 8 1 read-write - CORE_0_SP_SPILL_MAX_RLS + CORE_0_SP_SPILL_MAX_INTR_ENA Core0 stackpoint underflow monitor interrupt enable 9 1 read-write - CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA IBUS busy monitor interrupt enable 10 1 read-write - CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA DBUS busy monitor interrupt enbale 11 1 @@ -2652,7 +2650,7 @@ - CORE_0_INTERRUPT_CLR + CORE_0_INTR_CLR core0 monitor interrupt clr register 0xC 0x20 @@ -3275,7 +3273,7 @@ - CORE_1_INTERRUPT_ENA + CORE_1_MONTR_ENA Core1 monitor enable configuration register 0x90 0x20 @@ -3367,7 +3365,7 @@ - CORE_1_INTERRUPT_RAW + CORE_1_INTR_RAW Core1 monitor interrupt status register 0x94 0x20 @@ -3459,90 +3457,90 @@ - CORE_1_INTERRUPT_RLS + CORE_1_INTR_ENA Core1 monitor interrupt enable register 0x98 0x20 - CORE_1_AREA_DRAM0_0_RD_RLS + CORE_1_AREA_DRAM0_0_RD_INTR_ENA Core1 dram0 area0 read monitor interrupt enable 0 1 read-write - CORE_1_AREA_DRAM0_0_WR_RLS + CORE_1_AREA_DRAM0_0_WR_INTR_ENA Core1 dram0 area0 write monitor interrupt enable 1 1 read-write - CORE_1_AREA_DRAM0_1_RD_RLS + CORE_1_AREA_DRAM0_1_RD_INTR_ENA Core1 dram0 area1 read monitor interrupt enable 2 1 read-write - CORE_1_AREA_DRAM0_1_WR_RLS + CORE_1_AREA_DRAM0_1_WR_INTR_ENA Core1 dram0 area1 write monitor interrupt enable 3 1 read-write - CORE_1_AREA_PIF_0_RD_RLS + CORE_1_AREA_PIF_0_RD_INTR_ENA Core1 PIF area0 read monitor interrupt enable 4 1 read-write - CORE_1_AREA_PIF_0_WR_RLS + CORE_1_AREA_PIF_0_WR_INTR_ENA Core1 PIF area0 write monitor interrupt enable 5 1 read-write - CORE_1_AREA_PIF_1_RD_RLS + CORE_1_AREA_PIF_1_RD_INTR_ENA Core1 PIF area1 read monitor interrupt enable 6 1 read-write - CORE_1_AREA_PIF_1_WR_RLS + CORE_1_AREA_PIF_1_WR_INTR_ENA Core1 PIF area1 write monitor interrupt enable 7 1 read-write - CORE_1_SP_SPILL_MIN_RLS + CORE_1_SP_SPILL_MIN_INTR_ENA Core1 stackpoint overflow monitor interrupt enable 8 1 read-write - CORE_1_SP_SPILL_MAX_RLS + CORE_1_SP_SPILL_MAX_INTR_ENA Core1 stackpoint underflow monitor interrupt enable 9 1 read-write - CORE_1_IRAM0_EXCEPTION_MONITOR_RLS + CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA IBUS busy monitor interrupt enable 10 1 read-write - CORE_1_DRAM0_EXCEPTION_MONITOR_RLS + CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA DBUS busy monitor interrupt enbale 11 1 @@ -3551,7 +3549,7 @@ - CORE_1_INTERRUPT_CLR + CORE_1_INTR_CLR Core1 monitor interrupt clr register 0x9C 0x20 @@ -6189,7 +6187,7 @@ 0x20 - IV_0 + IV Stores IV block data 0 32 @@ -12475,7 +12473,7 @@ 0x20 - QUREY_CHECK + QUERY_CHECK Hmac configuration state. 0: key are agree with purpose. 1: error 0 1 @@ -18196,7 +18194,7 @@ level. INTERRUPT_CORE1 Interrupt Controller (Core 1) INTERRUPT_CORE1 - 0x600C2800 + 0x600C2000 0x0 0x1A4 @@ -20050,7 +20048,7 @@ level. LCD_CAM - LCD_CAM Peripheral + Camera/LCD Controller LCD_CAM 0x60041000 @@ -26641,36 +26639,19 @@ Any pulses with width less than this will be ignored when the filter is enabled. - 4 + 8 0x4 - TX_CH%sDATA + CH%sDATA The read and write data register for CHANNEL%s by apb fifo access. 0x0 0x20 - CHDATA + DATA Read and write data for channel %s via APB FIFO. 0 32 - read-only - - - - - 4 - 0x4 - RX_CH%sDATA - The read and write data register for CHANNEL$n by apb fifo access. - 0x10 - 0x20 - - - CHDATA - Read and write data for channel 0 via APB FIFO. - 0 - 32 - read-only + read-write @@ -26797,6 +26778,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x8 + 4-7 CH%s_RX_CONF0 Channel %s configure register 0 0x30 @@ -26847,6 +26829,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x8 + 4-7 CH%s_RX_CONF1 Channel %s configure register 1 0x34 @@ -27030,7 +27013,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_END_INT_RAW + CH%s_TX_END The interrupt raw bit for CHANNEL%s. Triggered when transmission done. 0 1 @@ -27040,7 +27023,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_ERR_INT_RAW + CH%s_TX_ERR The interrupt raw bit for CHANNEL%s. Triggered when error occurs. 4 1 @@ -27050,7 +27033,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_RAW + CH%s_TX_THR_EVENT The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. 8 1 @@ -27060,7 +27043,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_RAW + CH%s_TX_LOOP The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. 12 1 @@ -27070,7 +27053,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 4-7 - CH%s_RX_END_INT_RAW + CH%s_RX_END The interrupt raw bit for CHANNEL4. Triggered when reception done. 16 1 @@ -27080,49 +27063,31 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 4-7 - CH%s_RX_ERR_INT_RAW + CH%s_RX_ERR The interrupt raw bit for CHANNEL4. Triggered when error occurs. 20 1 read-write - CH4_RX_THR_EVENT_INT_RAW + 4 + 0x1 + 4-7 + CH%s_RX_THR_EVENT The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. 24 1 read-write - CH5_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value. - 25 - 1 - read-write - - - CH6_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value. - 26 - 1 - read-write - - - CH7_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value. - 27 - 1 - read-write - - - TX_CH3_DMA_ACCESS_FAIL_INT_RAW + TX_CH3_DMA_ACCESS_FAIL The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. 28 1 read-write - RX_CH7_DMA_ACCESS_FAIL_INT_RAW + RX_CH7_DMA_ACCESS_FAIL The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. 29 1 @@ -27140,7 +27105,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_END_INT_ST + CH%s_TX_END The masked interrupt status bit for CH%s_TX_END_INT. 0 1 @@ -27150,7 +27115,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_ERR_INT_ST + CH%s_TX_ERR The masked interrupt status bit for CH%s_ERR_INT. 4 1 @@ -27160,7 +27125,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_ST + CH%s_TX_THR_EVENT The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. 8 1 @@ -27170,7 +27135,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_ST + CH%s_TX_LOOP The masked interrupt status bit for CH%s_TX_LOOP_INT. 12 1 @@ -27180,7 +27145,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 4-7 - CH%s_RX_END_INT_ST + CH%s_RX_END The masked interrupt status bit for CH4_RX_END_INT. 16 1 @@ -27190,49 +27155,31 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 4-7 - CH%s_RX_ERR_INT_ST + CH%s_RX_ERR The masked interrupt status bit for CH4_ERR_INT. 20 1 read-only - CH4_RX_THR_EVENT_INT_ST + 4 + 0x1 + 4-7 + CH%s_RX_THR_EVENT The masked interrupt status bit for CH4_RX_THR_EVENT_INT. 24 1 read-only - CH5_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH5_RX_THR_EVENT_INT. - 25 - 1 - read-only - - - CH6_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH6_RX_THR_EVENT_INT. - 26 - 1 - read-only - - - CH7_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH7_RX_THR_EVENT_INT. - 27 - 1 - read-only - - - TX_CH3_DMA_ACCESS_FAIL_INT_ST + TX_CH3_DMA_ACCESS_FAIL The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. 28 1 read-only - RX_CH7_DMA_ACCESS_FAIL_INT_ST + RX_CH7_DMA_ACCESS_FAIL The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. 29 1 @@ -27250,7 +27197,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_END_INT_ENA + CH%s_TX_END The interrupt enable bit for CH%s_TX_END_INT. 0 1 @@ -27260,7 +27207,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_ERR_INT_ENA + CH%s_TX_ERR The interrupt enable bit for CH%s_ERR_INT. 4 1 @@ -27270,7 +27217,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_ENA + CH%s_TX_THR_EVENT The interrupt enable bit for CH%s_TX_THR_EVENT_INT. 8 1 @@ -27280,7 +27227,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_ENA + CH%s_TX_LOOP The interrupt enable bit for CH%s_TX_LOOP_INT. 12 1 @@ -27290,7 +27237,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 4-7 - CH%s_RX_END_INT_ENA + CH%s_RX_END The interrupt enable bit for CH4_RX_END_INT. 16 1 @@ -27300,49 +27247,31 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 4-7 - CH%s_RX_ERR_INT_ENA + CH%s_RX_ERR The interrupt enable bit for CH4_ERR_INT. 20 1 read-write - CH4_RX_THR_EVENT_INT_ENA + 4 + 0x1 + 4-7 + CH%s_RX_THR_EVENT The interrupt enable bit for CH4_RX_THR_EVENT_INT. 24 1 read-write - CH5_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH5_RX_THR_EVENT_INT. - 25 - 1 - read-write - - - CH6_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH6_RX_THR_EVENT_INT. - 26 - 1 - read-write - - - CH7_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH7_RX_THR_EVENT_INT. - 27 - 1 - read-write - - - TX_CH3_DMA_ACCESS_FAIL_INT_ENA + TX_CH3_DMA_ACCESS_FAIL The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. 28 1 read-write - RX_CH7_DMA_ACCESS_FAIL_INT_ENA + RX_CH7_DMA_ACCESS_FAIL The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. 29 1 @@ -27360,7 +27289,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_END_INT_CLR + CH%s_TX_END Set this bit to clear theCH%s_TX_END_INT interrupt. 0 1 @@ -27370,7 +27299,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_ERR_INT_CLR + CH%s_TX_ERR Set this bit to clear theCH%s_ERR_INT interrupt. 4 1 @@ -27380,7 +27309,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_THR_EVENT_INT_CLR + CH%s_TX_THR_EVENT Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. 8 1 @@ -27390,7 +27319,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 0-3 - CH%s_TX_LOOP_INT_CLR + CH%s_TX_LOOP Set this bit to clear theCH%s_TX_LOOP_INT interrupt. 12 1 @@ -27400,7 +27329,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 4-7 - CH%s_RX_END_INT_CLR + CH%s_RX_END Set this bit to clear theCH4_RX_END_INT interrupt. 16 1 @@ -27409,50 +27338,32 @@ Any pulses with width less than this will be ignored when the filter is enabled. 4 0x1 - RX_CH4,RX_CH5,RX_CH6,RX_CH7 - CH%s_RX_ERR_INT_CLR + 4-7 + CH%s_RX_ERR Set this bit to clear theCH4_ERR_INT interrupt. 20 1 write-only - CH4_RX_THR_EVENT_INT_CLR + 4 + 0x1 + 4-7 + CH%s_RX_THR_EVENT Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. 24 1 write-only - CH5_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. - 25 - 1 - write-only - - - CH6_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. - 26 - 1 - write-only - - - CH7_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. - 27 - 1 - write-only - - - TX_CH3_DMA_ACCESS_FAIL_INT_CLR + TX_CH3_DMA_ACCESS_FAIL Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. 28 1 write-only - RX_CH7_DMA_ACCESS_FAIL_INT_CLR + RX_CH7_DMA_ACCESS_FAIL Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. 29 1 @@ -27565,7 +27476,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000080 - RX_LIM + RX_LIM_CH4 This register is used to configure the maximum entries that CHANNEL%s can receive. 0 9 @@ -27704,9 +27615,9 @@ Any pulses with width less than this will be ignored when the filter is enabled. 8 0x1 - TX_REF_CNT_RST_CH0,TX_REF_CNT_RST_CH1,TX_REF_CNT_RST_CH2,TX_REF_CNT_RST_CH3,RX_REF_CNT_RST_CH4,RX_REF_CNT_RST_CH5,RX_REF_CNT_RST_CH6,RX_REF_CNT_RST_CH7 + 0-7 CH%s - This register is used to reset the clock divider of CHANNEL0. + This register is used to reset the clock divider of CHANNEL%s. 0 1 write-only @@ -32811,7 +32722,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. RTC_I2C - RTC_I2C Peripheral + Low-power I2C (Inter-Integrated Circuit) Controller RTC_I2C 0x60008C00 @@ -33786,7 +33697,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. RTC_IO - RTC_IO Peripheral + Low-power Input/Output RTC_IO 0x60008400 @@ -36067,6 +35978,1378 @@ Any pulses with width less than this will be ignored when the filter is enabled. + + SDHOST + SD/MMC Host Controller + SDHOST + 0x60028000 + + 0x0 + 0xA4 + registers + + + + CTRL + Control register + 0x0 + 0x20 + + + CONTROLLER_RESET + To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. + 0 + 1 + read-write + + + FIFO_RESET + To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. +Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. + 1 + 1 + read-write + + + DMA_RESET + To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. + 2 + 1 + read-write + + + INT_ENABLE + Global interrupt enable/disable bit. 0: Disable; 1: Enable. + 4 + 1 + read-write + + + READ_WAIT + For sending read-wait to SDIO cards. + 6 + 1 + read-write + + + SEND_IRQ_RESPONSE + Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. + 7 + 1 + read-write + + + ABORT_READ_DATA + After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. + 8 + 1 + read-write + + + SEND_CCSD + When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. +NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. + 9 + 1 + read-write + + + SEND_AUTO_STOP_CCSD + Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. + 10 + 1 + read-write + + + CEATA_DEVICE_INTERRUPT_STATUS + Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit. + 11 + 1 + read-write + + + + + CLKDIV + Clock divider configuration register + 0x8 + 0x20 + + + CLK_DIVIDER0 + Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 0 + 8 + read-write + + + CLK_DIVIDER1 + Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 8 + 8 + read-write + + + CLK_DIVIDER2 + Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 16 + 8 + read-write + + + CLK_DIVIDER3 + Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 24 + 8 + read-write + + + + + CLKSRC + Clock source selection register + 0xC + 0x20 + + + CLKSRC + Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value. +00 : Clock divider 0; +01 : Clock divider 1; +10 : Clock divider 2; +11 : Clock divider 3. + 0 + 4 + read-write + + + + + CLKENA + Clock enable register + 0x10 + 0x20 + + + CCLK_ENABLE + Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. +0: Clock disabled; +1: Clock enabled. + 0 + 2 + read-write + + + LP_ENABLE + Disable clock when the card is in IDLE state. One bit per card. +0: clock disabled; +1: clock enabled. + 16 + 2 + read-write + + + + + TMOUT + Data and response timeout configuration register + 0x14 + 0x20 + 0xFFFFFF40 + + + RESPONSE_TIMEOUT + Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out. + 0 + 8 + read-write + + + DATA_TIMEOUT + Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. +NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled. + 8 + 24 + read-write + + + + + CTYPE + Card bus width configuration register + 0x18 + 0x20 + + + CARD_WIDTH4 + One bit per card indicates if card is 1-bit or 4-bit mode. +0: 1-bit mode; +1: 4-bit mode. +Bit[1:0] correspond to card[1:0] respectively. + 0 + 2 + read-write + + + CARD_WIDTH8 + One bit per card indicates if card is in 8-bit mode. +0: Non 8-bit mode; +1: 8-bit mode. +Bit[17:16] correspond to card[1:0] respectively. + 16 + 2 + read-write + + + + + BLKSIZ + Card data block size configuration register + 0x1C + 0x20 + 0x00000200 + + + BLOCK_SIZE + Block size. + 0 + 16 + read-write + + + + + BYTCNT + Data transfer length configuration register + 0x20 + 0x20 + 0x00000200 + + + BYTE_COUNT + Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer. + 0 + 32 + read-write + + + + + INTMASK + SDIO interrupt mask register + 0x24 + 0x20 + + + INT_MASK + These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): Rx Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation-by-host timeout; +Bit 9 (DRTO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-write + + + SDIO_INT_MASK + SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt. + 16 + 2 + read-write + + + + + CMDARG + Command argument data register + 0x28 + 0x20 + + + CMDARG + Value indicates command argument to be passed to the card. + 0 + 32 + read-write + + + + + CMD + Command and boot configuration register + 0x2C + 0x20 + 0x20000000 + + + INDEX + Command index. + 0 + 6 + read-write + + + RESPONSE_EXPECT + 0: No response expected from card; 1: Response expected from card. + 6 + 1 + read-write + + + RESPONSE_LENGTH + 0: Short response expected from card; 1: Long response expected from card. + 7 + 1 + read-write + + + CHECK_RESPONSE_CRC + 0: Do not check; 1: Check response CRC. +Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. + 8 + 1 + read-write + + + DATA_EXPECTED + 0: No data transfer expected; 1: Data transfer expected. + 9 + 1 + read-write + + + READ_WRITE + 0: Read from card; 1: Write to card. +Don't care if no data is expected from card. + 10 + 1 + read-write + + + TRANSFER_MODE + 0: Block data transfer command; 1: Stream data transfer command. +Don't care if no data expected. + 11 + 1 + read-write + + + SEND_AUTO_STOP + 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer. + 12 + 1 + read-write + + + WAIT_PRVDATA_COMPLETE + 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. +The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command. + 13 + 1 + read-write + + + STOP_ABORT_CMD + 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. +When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. + 14 + 1 + read-write + + + SEND_INITIALIZATION + 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. +After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. + 15 + 1 + read-write + + + CARD_NUMBER + Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported. + 16 + 5 + read-write + + + UPDATE_CLOCK_REGISTERS_ONLY + 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. +Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. +Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. + 21 + 1 + read-write + + + READ_CEATA_DEVICE + Read access flag. +0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; +1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. +Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. + 22 + 1 + read-write + + + CCS_EXPECTED + Expected Command Completion Signal (CCS) configuration. +0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; +1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. +If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. + 23 + 1 + read-write + + + USE_HOLE + Use Hold Register. +0: CMD and DATA sent to card bypassing HOLD Register; +1: CMD and DATA sent to card through the HOLD Register. + 29 + 1 + read-write + + + START_CMD + Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register. + 31 + 1 + read-write + + + + + RESP0 + Response data register + 0x30 + 0x20 + + + RESPONSE0 + Bit[31:0] of response. + 0 + 32 + read-only + + + + + RESP1 + Long response data register + 0x34 + 0x20 + + + RESPONSE1 + Bit[63:32] of long response. + 0 + 32 + read-only + + + + + RESP2 + Long response data register + 0x38 + 0x20 + + + RESPONSE2 + Bit[95:64] of long response. + 0 + 32 + read-only + + + + + RESP3 + Long response data register + 0x3C + 0x20 + + + RESPONSE3 + Bit[127:96] of long response. + 0 + 32 + read-only + + + + + MINTSTS + Masked interrupt status register + 0x40 + 0x20 + + + INT_STATUS_MSK + Interrupt enabled only if corresponding bit in interrupt mask register is set. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-only + + + SDIO_INTERRUPT_MSK + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). + 16 + 2 + read-only + + + + + RINTSTS + Raw interrupt status register + 0x44 + 0x20 + + + INT_STATUS_RAW + Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-write + + + SDIO_INTERRUPT_RAW + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. +0: No SDIO interrupt from card; +1: SDIO interrupt from card. + 16 + 2 + read-write + + + + + STATUS + SD/MMC status register + 0x48 + 0x20 + 0x00000716 + + + FIFO_RX_WATERMARK + FIFO reached Receive watermark level, not qualified with data transfer. + 0 + 1 + read-only + + + FIFO_TX_WATERMARK + FIFO reached Transmit watermark level, not qualified with data transfer. + 1 + 1 + read-only + + + FIFO_EMPTY + FIFO is empty status. + 2 + 1 + read-only + + + FIFO_FULL + FIFO is full status. + 3 + 1 + read-only + + + COMMAND_FSM_STATES + Command FSM states. +0: Idle; +1: Send init sequence; +2: Send cmd start bit; +3: Send cmd tx bit; +4: Send cmd index + arg; +5: Send cmd crc7; +6: Send cmd end bit; +7: Receive resp start bit; +8: Receive resp IRQ response; +9: Receive resp tx bit; +10: Receive resp cmd idx; +11: Receive resp data; +12: Receive resp crc7; +13: Receive resp end bit; +14: Cmd path wait NCC; +15: Wait, cmd-to-response turnaround. + 4 + 4 + read-only + + + DATA_3_STATUS + Raw selected sdhost_card_data[3], checks whether card is present. +0: card not present; +1: card present. + 8 + 1 + read-only + + + DATA_BUSY + Inverted version of raw selected sdhost_card_data[0]. +0: Card data not busy; +1: Card data busy. + 9 + 1 + read-only + + + DATA_STATE_MC_BUSY + Data transmit or receive state-machine is busy. + 10 + 1 + read-only + + + RESPONSE_INDEX + Index of previous response, including any auto-stop sent by core. + 11 + 6 + read-only + + + FIFO_COUNT + FIFO count, number of filled locations in FIFO. + 17 + 13 + read-only + + + + + FIFOTH + FIFO configuration register + 0x4C + 0x20 + + + TX_WMARK + FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. + 0 + 12 + read-write + + + RX_WMARK + FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. + 16 + 11 + read-write + + + DMA_MULTIPLE_TRANSACTION_SIZE + Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. + 28 + 3 + read-write + + + + + CDETECT + Card detect register + 0x50 + 0x20 + + + CARD_DETECT_N + Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented. + 0 + 2 + read-only + + + + + WRTPRT + Card write protection (WP) status register + 0x54 + 0x20 + + + WRITE_PROTECT + Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. + 0 + 2 + read-only + + + + + TCBCNT + Transferred byte count register + 0x5C + 0x20 + + + TCBCNT + Number of bytes transferred by CIU unit to card. + 0 + 32 + read-only + + + + + TBBCNT + Transferred byte count register + 0x60 + 0x20 + + + TBBCNT + Number of bytes transferred between Host/DMA memory and BIU FIFO. + 0 + 32 + read-only + + + + + DEBNCE + Debounce filter time configuration register + 0x64 + 0x20 + + + DEBOUNCE_COUNT + Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted or removed. + 0 + 24 + read-write + + + + + USRID + User ID (scratchpad) register + 0x68 + 0x20 + + + USRID + User identification register, value set by user. Can also be used as a scratchpad register by user. + 0 + 32 + read-write + + + + + VERID + Version ID (scratchpad) register + 0x6C + 0x20 + 0x5432270A + + + VERSIONID + Hardware version register. Can also be read by fireware. + 0 + 32 + read-only + + + + + HCON + Hardware feature register + 0x70 + 0x20 + 0x03444CC3 + + + CARD_TYPE + Hardware support SDIO and MMC. + 0 + 1 + read-only + + + CARD_NUM + Support card number is 2. + 1 + 5 + read-only + + + BUS_TYPE + Register config is APB bus. + 6 + 1 + read-only + + + DATA_WIDTH + Regisger data widht is 32. + 7 + 3 + read-only + + + ADDR_WIDTH + Register address width is 32. + 10 + 6 + read-only + + + DMA_WIDTH + DMA data witdth is 32. + 18 + 3 + read-only + + + RAM_INDISE + Inside RAM in SDMMC module. + 21 + 1 + read-only + + + HOLD + Have a hold regiser in data path . + 22 + 1 + read-only + + + NUM_CLK_DIV + Have 4 clk divider in design . + 24 + 2 + read-only + + + + + UHS + UHS-1 register + 0x74 + 0x20 + + + DDR + DDR mode selecton,1 bit for each card. +0-Non-DDR mdoe. +1-DDR mdoe. + 16 + 2 + read-write + + + + + RST_N + Card reset register + 0x78 + 0x20 + 0x00000001 + + + CARD_RESET + Hardware reset. +1: Active mode; +0: Reset. +These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. + 0 + 2 + read-write + + + + + BMOD + Burst mode transfer configuration register + 0x80 + 0x20 + + + SWR + Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle. + 0 + 1 + read-write + + + FB + Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. + 1 + 1 + read-write + + + DE + IDMAC Enable. When set, the IDMAC is enabled. + 7 + 1 + read-write + + + PBL + Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. +PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access. + 8 + 3 + read-write + + + + + PLDMND + Poll demand configuration register + 0x84 + 0x20 + + + PD + Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only . + 0 + 32 + write-only + + + + + DBADDR + Descriptor base address register + 0x88 + 0x20 + + + DBADDR + Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. + 0 + 32 + read-write + + + + + IDSTS + IDMAC status register + 0x8C + 0x20 + + + TI + Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. + 0 + 1 + read-write + + + RI + Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. + 4 + 1 + read-write + + + CES + Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: +EBE : End Bit Error; +RTO : Response Timeout/Boot Ack Timeout; +RCRC : Response CRC; +SBE : Start Bit Error; +DRTO : Data Read Timeout/BDS timeout; +DCRC : Data CRC for Receive; +RE : Response Error. +Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error. + 5 + 1 + read-write + + + NIS + Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit. + 8 + 1 + read-write + + + AIS + Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit. + 9 + 1 + read-write + + + FBE_CODE + Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. +001: Host Abort received during transmission; +010: Host Abort received during reception; +Others: Reserved. + 10 + 3 + read-write + + + FSM + DMAC FSM present state. +0: DMA_IDLE (idle state); +1: DMA_SUSPEND (suspend state); +2: DESC_RD (descriptor reading state); +3: DESC_CHK (descriptor checking state); +4: DMA_RD_REQ_WAIT (read-data request waiting state); +5: DMA_WR_REQ_WAIT (write-data request waiting state); +6: DMA_RD (data-read state); +7: DMA_WR (data-write state); +8: DESC_CLOSE (descriptor close state). + 13 + 4 + read-write + + + + + IDINTEN + IDMAC interrupt enable register + 0x90 + 0x20 + + + TI + Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. + 0 + 1 + read-write + + + RI + Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. + 4 + 1 + read-write + + + CES + Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. + 5 + 1 + read-write + + + NI + Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: +IDINTEN[0]: Transmit Interrupt; +IDINTEN[1]: Receive Interrupt. + 8 + 1 + read-write + + + AI + Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: +IDINTEN[2]: Fatal Bus Error Interrupt; +IDINTEN[4]: DU Interrupt. + 9 + 1 + read-write + + + + + DSCADDR + Host descriptor address pointer + 0x94 + 0x20 + + + DSCADDR + Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. + 0 + 32 + read-only + + + + + BUFADDR + Host buffer address pointer register + 0x98 + 0x20 + + + BUFADDR + Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC. + 0 + 32 + read-only + + + + + CARDTHRCTL + Card Threshold Control register + 0x100 + 0x20 + + + CARDRDTHREN + Card read threshold enable. +1'b0-Card read threshold disabled. +1'b1-Card read threshold enabled. + 0 + 1 + read-write + + + CARDCLRINTEN + Busy clear interrupt generation: +1'b0-Busy clear interrypt disabled. +1'b1-Busy clear interrypt enabled. + 1 + 1 + read-write + + + CARDWRTHREN + Applicable when HS400 mode is enabled. +1'b0-Card write Threshold disabled. +1'b1-Card write Threshold enabled. + 2 + 1 + read-write + + + CARDTHRESHOLD + The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. + 16 + 16 + read-write + + + + + EMMCDDR + eMMC DDR register + 0x10C + 0x20 + + + HALFSTARTBIT + Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: +1'b0-Full cycle. +1'b1-less than one full cycle. + 0 + 2 + read-write + + + HS400_MODE + Set 1 to enable HS400 mode. + 31 + 1 + read-write + + + + + ENSHIFT + Enable Phase Shift register + 0x110 + 0x20 + + + ENABLE_SHIFT + Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. +2'b00-Default phase shift. +2'b01-Enables shifted to next immediate positive edge. +2'b10-Enables shifted to next immediate negative edge. +2'b11-Reserved. + 0 + 4 + read-write + + + + + BUFFIFO + CPU write and read transmit data by FIFO + 0x200 + 0x20 + + + BUFFIFO + CPU write and read transmit data by FIFO. This register points to the current Data FIFO . + 0 + 32 + read-write + + + + + CLK_EDGE_SEL + SDIO control register. + 0x800 + 0x20 + 0x00820200 + + + CCLKIN_EDGE_DRV_SEL + It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270. + 0 + 3 + read-write + + + CCLKIN_EDGE_SAM_SEL + It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270. + 3 + 3 + read-write + + + CCLKIN_EDGE_SLF_SEL + It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270. + 6 + 3 + read-write + + + CCLLKIN_EDGE_H + The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + 9 + 4 + read-write + + + CCLLKIN_EDGE_L + The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + 13 + 4 + read-write + + + CCLLKIN_EDGE_N + The clock division of cclk_in. + 17 + 4 + read-write + + + ESDIO_MODE + Enable esdio mode. + 21 + 1 + read-write + + + ESD_MODE + Enable esd mode. + 22 + 1 + read-write + + + CCLK_EN + Sdio clock enable. + 23 + 1 + read-write + + + + + SENS SENS Peripheral @@ -45145,7 +46428,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. reserved. 1 31 - read-only + write-only @@ -45160,7 +46443,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. reserved. 1 31 - read-only + write-only @@ -53084,8 +54367,7 @@ counter. LOAD - -Write any value to trigger a timer %s time-base counter reload. + Write any value to trigger a timer %s time-base counter reload. 0 32 write-only @@ -53138,32 +54420,28 @@ Write any value to trigger a timer %s time-base counter reload. WDT_STG3 - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 23 2 read-write WDT_STG2 - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 25 2 read-write WDT_STG1 - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 27 2 read-write WDT_STG0 - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 29 2 read-write @@ -60847,6 +62125,12 @@ protection is enabled. 1 read-write + + ENA32KHZSUSP + 3 + 1 + read-write + DEVADDR 4 @@ -67602,7 +68886,7 @@ protection is enabled. 0x20 - PLAIN_0 + PLAIN Stores the nth 32-bit piece of plaintext. 0 32 diff --git a/.vscode/launch.json b/.vscode/launch.json index 8ed9f15e..3e95c8d2 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -5,7 +5,6 @@ "version": "0.2.0", "configurations": [ { - // more info at: https://github.com/Marus/cortex-debug/blob/master/package.json "name": "Attach (USB JTAG)", "type": "cortex-debug", "request": "attach", // attach instead of launch, because otherwise flash write is attempted, but fails @@ -34,7 +33,6 @@ ] }, { - // more info at: https://github.com/Marus/cortex-debug/blob/master/package.json "name": "Attach (USB JTAG, release)", "type": "cortex-debug", "request": "attach", // attach instead of launch, because otherwise flash write is attempted, but fails @@ -63,7 +61,34 @@ ] }, { - // more info at: https://github.com/Marus/cortex-debug/blob/master/package.json + "name": "Attach (C6, USB JTAG, debug)", + "type": "cortex-debug", + "request": "attach", // attach instead of launch, because otherwise flash write is attempted, but fails + "cwd": "${workspaceRoot}", + "executable": "target/riscv32imac-unknown-none-elf/debug/card_io_fw", + "servertype": "openocd", + "interface": "jtag", + "svdFile": ".vscode/esp32c6.base.svd", + "toolchainPrefix": "riscv32-esp-elf", + "openOCDPreConfigLaunchCommands": [ + "set ESP_RTOS none" + ], + "serverpath": "${userHome}/openocd-esp32/bin/openocd.exe", + "configFiles": [ + "board/esp32c6-builtin.cfg" + ], + "overrideAttachCommands": [ + "set remote hardware-watchpoint-limit 2", + "mon halt", + "flushregs" + ], + "overrideRestartCommands": [ + "mon reset halt", + "flushregs", + "c" + ] + }, + { "name": "Attach (esp-prog JTAG)", "type": "cortex-debug", "request": "attach", // attach instead of launch, because otherwise flash write is attempted, but fails diff --git a/.vscode/settings.json b/.vscode/settings.json index 3c4fc398..e77b6620 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,5 +1,9 @@ { "rust-analyzer.check.allTargets": false, "rust-analyzer.showUnlinkedFileNotification": false, - "cortex-debug.variableUseNaturalFormat": false + "cortex-debug.variableUseNaturalFormat": false, + "rust-analyzer.cargo.features": [ + "esp32c6", + "hw_v6" + ] } \ No newline at end of file diff --git a/Cargo.toml b/Cargo.toml index 050c819a..d53be2a8 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -35,9 +35,10 @@ log = { version = "0.4.18", default-features = false, features = [ ] } logger = { path = "logger" } signal-processing = { path = "signal-processing" } -norfs = { git = "https://github.com/card-io-ecg/norfs.git", rev = "62cd6ea" } -norfs-driver = { git = "https://github.com/card-io-ecg/norfs.git", rev = "62cd6ea" } -norfs-esp32s3 = { git = "https://github.com/card-io-ecg/norfs.git", rev = "62cd6ea" } +norfs = { git = "https://github.com/card-io-ecg/norfs.git", rev = "01c1905" } +norfs-driver = { git = "https://github.com/card-io-ecg/norfs.git", rev = "01c1905" } +norfs-esp32s3 = { git = "https://github.com/card-io-ecg/norfs.git", rev = "01c1905" } +norfs-esp32c6 = { git = "https://github.com/card-io-ecg/norfs.git", rev = "01c1905" } object-chain = "0.1.3" bad-server = { path = "bad-server" } defmt = { version = "=0.3.5" } @@ -64,6 +65,17 @@ esp32s3-hal = { version = "0.13.0", optional = true, features = [ "embassy-time-systick", "eh1", ] } +esp32c6-hal = { version = "0.6.0", optional = true, default-features = false, features = [ + "rt", + "vectored", + "zero-rtc-bss", + "embassy-generic-queue-8", + "async", + "embassy", + "embassy-executor-thread", + "embassy-executor-interrupt", + "eh1", +] } esp-backtrace = { version = "0.9.0", features = [ "panic-handler", "exception-handler", @@ -72,13 +84,16 @@ esp-println = { version = "0.7.0", default-features = false, features = [ "critical-section", ] } esp-alloc = "0.3.0" -esp-wifi = { git = "https://github.com/esp-rs/esp-wifi.git", rev = "0db7a70", default-features = false, features = [ +esp-wifi = { version = "0.1.1", default-features = false, features = [ "phy-enable-usb", "ps-max-modem", "wifi", - "embedded-svc", "async", - "embassy-net" + "embassy-net", + "tcp", + "dns", + "ipv4", + "dhcpv4" ] } display-interface = { git = "https://github.com/therealprof/display-interface.git" } @@ -128,6 +143,9 @@ norfs-driver = { workspace = true } norfs-esp32s3 = { workspace = true, optional = true, features = [ "critical-section", ] } +norfs-esp32c6 = { workspace = true, optional = true, features = [ + "critical-section", +] } heapless = { workspace = true } object-chain = { workspace = true } ufmt = { workspace = true } @@ -141,8 +159,10 @@ crc = "3.0.1" enumset = "1.1.3" [patch.crates-io] -# esp32s3-hal = { git = "https://github.com/esp-rs/esp-hal.git", rev = "0c8dd59163472133870a62b6248f50953f02defc" } -# esp-println = { git = "https://github.com/esp-rs/esp-println.git" } +esp32s3-hal = { git = "https://github.com/bugadani/esp-hal.git", branch = "c6sleep" } +esp32c6-hal = { git = "https://github.com/bugadani/esp-hal.git", branch = "c6sleep" } +esp-println = { git = "https://github.com/esp-rs/esp-println.git" } +esp-wifi = { git = "https://github.com/esp-rs/esp-wifi.git", rev = "d46dfc4" } # esp-backtrace = { path = "../../esp-backtrace" } # embedded-text = { git = "https://github.com/embedded-graphics/embedded-text.git" } # esp32-hal = { path = "../../esp-hal/esp32-hal" } @@ -153,33 +173,39 @@ enumset = "1.1.3" # esp32c6-hal = { path = "../../esp-hal/esp32c6-hal" } # esp-hal-common = { path = "../../esp-hal/esp-hal-common" } # esp-hal-procmacros = { path = "../../esp-hal/esp-hal-procmacros" } - -[patch.'https://github.com/esp-rs/esp-wifi.git'] # esp-wifi = { path = "../esp-wifi/esp-wifi" } -# esp-wifi = { git = "https://github.com/bugadani/esp-wifi.git" } [features] -default = ["esp32s3", "defmt"] +default = ["defmt"] battery_adc = [] battery_max17055 = ["dep:max17055"] -bitbang_spi = [] - -hw_v1 = ["battery_adc"] -hw_v2 = ["battery_max17055"] # also v3 -hw_v4 = ["battery_max17055"] +hw_v1 = ["battery_adc", "esp32s3"] +hw_v2 = ["battery_max17055", "esp32s3"] # skipped v3 +hw_v4 = ["battery_max17055", "esp32s3"] +hw_v6 = ["battery_max17055"] # skipped v5, v6 has S3 and C6 options # MCU options # esp32s2 = ["dep:esp32s2", "dep:esp32s2-hal", "esp-backtrace/esp32s2", "esp-println/esp32s2", "rtt"] esp32s3 = [ "dep:esp32s3-hal", + "esp32s3-hal/embassy-time-systick", "dep:norfs-esp32s3", "esp-backtrace/esp32s3", "esp-println/esp32s3", "jtag_serial", "esp-wifi/esp32s3", ] +esp32c6 = [ + "dep:esp32c6-hal", + "esp32c6-hal/embassy-time-timg0", + "dep:norfs-esp32c6", + "esp-backtrace/esp32c6", + "esp-println/esp32c6", + "jtag_serial", + "esp-wifi/esp32c6", +] # Signal processing downsampler-light = [] # uses IIR-based filtering and less memory @@ -195,7 +221,8 @@ log = [ "esp-println/log", "esp-println/colors", "esp-wifi/log", - "esp32s3-hal/log", + "esp32s3-hal?/log", + "esp32c6-hal?/log", "logger/log", "config-site/log", @@ -215,9 +242,10 @@ defmt = [ "embedded-io/defmt-03", "embedded-svc/defmt", "embedded-graphics/defmt", - "esp-println/defmt", + "esp-println/defmt-espflash", "esp-wifi/defmt", - "esp32s3-hal/defmt", + "esp32s3-hal?/defmt", + "esp32c6-hal?/defmt", "logger/defmt", "config-site/defmt", diff --git a/README.md b/README.md index 4e112e1c..4c10cdf8 100644 --- a/README.md +++ b/README.md @@ -29,7 +29,7 @@ Commands - `cargo xbuild `: Build the firmware for a `` version board. - `cargo xrun `: Build and run the firmware on a `` version board. - `cargo monitor`: Connect to the Card/IO device and display serial output. - `` can be omitted, or one of: `v1`, `v2`. Defaults to the latest version. + `` can be omitted, or one of: `v1`, `v2`, `v4`, `v6_s3`, `v6_c6`. Defaults to `v4`. - `cargo xcheck `: runs `cargo check` - `cargo xclippy `: runs `cargo clippy` - `cargo xdoc [--open]`: runs `cargo doc` and optionally opens the generated documentation. diff --git a/build.rs b/build.rs index f9792a7a..d574b004 100644 --- a/build.rs +++ b/build.rs @@ -2,6 +2,7 @@ enum Mcu { ESP32S2, ESP32S3, + ESP32C6, } impl Mcu { @@ -9,15 +10,17 @@ impl Mcu { match self { Self::ESP32S2 => "ESP32-S2", Self::ESP32S3 => "ESP32-S3", + Self::ESP32C6 => "ESP32-C6", } } } -#[derive(Clone, Copy)] +#[derive(Clone, Copy, PartialEq, PartialOrd)] enum HwVersion { V1, V2, V4, + V6, } impl HwVersion { @@ -26,10 +29,31 @@ impl HwVersion { Self::V1 => "v1", Self::V2 => "v2", Self::V4 => "v4", + Self::V6 => "v6", } } } +struct BuildConfig { + mcu: Mcu, + hw_version: HwVersion, +} + +impl BuildConfig { + fn as_str(&self) -> String { + let mcu = if self.hw_version >= HwVersion::V6 { + match self.mcu { + Mcu::ESP32S2 => "s2", + Mcu::ESP32S3 => "s3", + Mcu::ESP32C6 => "c6", + } + } else { + "" + }; + format!("{}{}", self.hw_version.as_str(), mcu) + } +} + fn get_unique(values: [(bool, T); N]) -> Option { let mut count = 0; let mut result = None; @@ -51,10 +75,11 @@ fn main() { let mcu_features = [ (cfg!(feature = "esp32s2"), Mcu::ESP32S2), (cfg!(feature = "esp32s3"), Mcu::ESP32S3), + (cfg!(feature = "esp32c6"), Mcu::ESP32C6), ]; let Some(mcu) = get_unique(mcu_features) else { - panic!("Exactly 1 MCU must be selected via its Cargo feature (esp32s2, esp32s3)"); + panic!("Exactly 1 MCU must be selected via its Cargo feature (esp32s2, esp32s3, esp32c6)"); }; // Ensure that only a single HW version @@ -62,12 +87,15 @@ fn main() { (cfg!(feature = "hw_v1"), HwVersion::V1), (cfg!(feature = "hw_v2"), HwVersion::V2), (cfg!(feature = "hw_v4"), HwVersion::V4), + (cfg!(feature = "hw_v6"), HwVersion::V6), ]; let Some(hw_version) = get_unique(hw_features) else { - panic!("Exactly 1 hardware version must be selected via its Cargo feature (hw_v1, hw_v2, hw_v4)"); + panic!("Exactly 1 hardware version must be selected via its Cargo feature (hw_v1, hw_v2, hw_v4, hw_v6)"); }; + let build_config = BuildConfig { mcu, hw_version }; + if cfg!(feature = "defmt") { println!("cargo:rustc-link-arg=-Tdefmt.x"); } @@ -87,7 +115,7 @@ fn main() { println!("cargo:rustc-env=FW_VERSION={pkg_version}-{git_hash_str}"); println!("cargo:rustc-env=MCU_MODEL={}", mcu.as_str()); - println!("cargo:rustc-env=HW_VERSION={}", hw_version.as_str()); + println!("cargo:rustc-env=HW_VERSION={}", build_config.as_str()); // Device info list items println!( @@ -97,6 +125,6 @@ fn main() { println!( "cargo:rustc-env=HW_VERSION_MENU_ITEM=HW {:>17}", - format!("{}/{}", mcu.as_str(), hw_version.as_str()) + format!("{}/{}", mcu.as_str(), build_config.as_str()) ); } diff --git a/cfg_esp32c6.toml b/cfg_esp32c6.toml new file mode 100644 index 00000000..157c5c65 --- /dev/null +++ b/cfg_esp32c6.toml @@ -0,0 +1,16 @@ +[esp-wifi] +heap_size = 131072 + +rx_queue_size = 16 +static_rx_buf_num = 32 +dynamic_rx_buf_num = 16 + +tx_queue_size = 16 +static_tx_buf_num = 12 +dynamic_tx_buf_num = 16 + +ampdu_rx_enable = 1 +ampdu_tx_enable = 1 +rx_ba_win = 8 +max_burst_size = 0 # 0 means no limit +tick_rate_hz = 200 diff --git a/cfg.toml b/cfg_esp32s3.toml similarity index 100% rename from cfg.toml rename to cfg_esp32s3.toml diff --git a/src/board/drivers/battery_monitor/battery_fg.rs b/src/board/drivers/battery_monitor/battery_fg.rs index ce7df443..dac6603b 100644 --- a/src/board/drivers/battery_monitor/battery_fg.rs +++ b/src/board/drivers/battery_monitor/battery_fg.rs @@ -3,7 +3,9 @@ use embedded_hal::digital::OutputPin; use embedded_hal_async::{delay::DelayUs, i2c::I2c}; use max17055::Max17055; -use crate::{hal::gpio::RTCPinWithResistors, task_control::TaskControlToken, Shared}; +#[cfg(all(feature = "esp32s3", not(feature = "hw_v6")))] +use crate::hal::gpio::RTCPinWithResistors; +use crate::{task_control::TaskControlToken, Shared}; #[derive(Clone, Copy, Debug)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -19,7 +21,7 @@ pub struct BatteryFg { impl BatteryFg where - EN: OutputPin + RTCPinWithResistors, + EN: OutputPin, I2C: I2c, { pub fn new(fg: Max17055, enable: EN) -> Self { @@ -46,11 +48,18 @@ where }) } - pub fn disable(&mut self) { + #[cfg(all(feature = "esp32s3", not(feature = "hw_v6")))] + pub fn disable(&mut self) + where + EN: RTCPinWithResistors, + { // We want to keep the fuel gauge out of shutdown mode self.enable.rtcio_pad_hold(true); self.enable.rtcio_pullup(true); } + + #[cfg(any(not(feature = "esp32s3"), feature = "hw_v6"))] + pub fn disable(&mut self) {} } #[embassy_executor::task] diff --git a/src/board/drivers/mod.rs b/src/board/drivers/mod.rs index e2a6b3e0..6723746c 100644 --- a/src/board/drivers/mod.rs +++ b/src/board/drivers/mod.rs @@ -1,5 +1,5 @@ pub mod battery_monitor; -#[cfg(feature = "bitbang_spi")] +#[cfg(feature = "esp32c6")] pub mod bitbang_spi; pub mod display; pub mod frontend; diff --git a/src/board/hardware/v1.rs b/src/board/hardware/v1.rs index ae48ebfe..94278d34 100644 --- a/src/board/hardware/v1.rs +++ b/src/board/hardware/v1.rs @@ -7,7 +7,7 @@ use crate::board::{ hal::{ self, adc::ADC2, - clock::{ClockControl, CpuClock}, + clock::ClockControl, embassy, gdma::*, gpio::{Analog, Floating, GpioPin, Input, Output, PullUp, PushPull}, @@ -15,6 +15,7 @@ use crate::board::{ prelude::*, spi::{master::dma::SpiDma, FullDuplexMode}, systimer::SystemTimer, + timer::TimerGroup, Rtc, IO, }, utils::DummyOutputPin, @@ -50,8 +51,11 @@ pub type AdcClockEnable = DummyOutputPin; pub type AdcDrdy = GpioPin, 4>; pub type AdcReset = GpioPin, 2>; pub type TouchDetect = GpioPin, 1>; -pub type AdcSpi<'d> = - ExclusiveDevice, AdcChipSelect, Delay>; +pub type AdcSpi = ExclusiveDevice< + SpiDma<'static, AdcSpiInstance, Channel1, FullDuplexMode>, + AdcChipSelect, + Delay, +>; pub type BatteryAdcInput = GpioPin; pub type BatteryAdcEnable = GpioPin, 8>; @@ -59,9 +63,9 @@ pub type VbusDetect = GpioPin, 47>; pub type ChargeCurrentInput = GpioPin; pub type ChargerStatus = GpioPin, 21>; -pub type EcgFrontend = Frontend, AdcDrdy, AdcReset, AdcClockEnable, TouchDetect>; +pub type EcgFrontend = Frontend; pub type PoweredEcgFrontend = - PoweredFrontend, AdcDrdy, AdcReset, AdcClockEnable, TouchDetect>; + PoweredFrontend; pub type Display = DisplayType; @@ -74,7 +78,7 @@ impl super::startup::StartupResources { let peripherals = Peripherals::take(); let system = peripherals.SYSTEM.split(); - let clocks = ClockControl::configure(system.clock_control, CpuClock::Clock240MHz).freeze(); + let clocks = ClockControl::max(system.clock_control).freeze(); embassy::init(&clocks, SystemTimer::new(peripherals.SYSTIMER)); @@ -96,19 +100,21 @@ impl super::startup::StartupResources { ); let adc = Self::create_frontend_driver( - dma.channel1, - peripherals::Interrupt::DMA_IN_CH1, - peripherals::Interrupt::DMA_OUT_CH1, - peripherals.SPI3, - io.pins.gpio6, - io.pins.gpio7, - io.pins.gpio5, + Self::create_frontend_spi( + dma.channel1, + peripherals::Interrupt::DMA_IN_CH1, + peripherals::Interrupt::DMA_OUT_CH1, + peripherals.SPI3, + io.pins.gpio6, + io.pins.gpio7, + io.pins.gpio5, + io.pins.gpio18, + &clocks, + ), io.pins.gpio4, io.pins.gpio2, DummyOutputPin, io.pins.gpio1, - io.pins.gpio18, - &clocks, ); // Battery ADC @@ -127,10 +133,9 @@ impl super::startup::StartupResources { wifi: static_cell::make_static! { WifiDriver::new( peripherals.WIFI, - peripherals.TIMG1, + TimerGroup::new(peripherals.TIMG1, &clocks).timer0, peripherals.RNG, system.radio_clock_control, - &clocks, ) }, clocks, diff --git a/src/board/hardware/v2.rs b/src/board/hardware/v2.rs index 40df47d1..5a91f473 100644 --- a/src/board/hardware/v2.rs +++ b/src/board/hardware/v2.rs @@ -17,7 +17,7 @@ use crate::board::{ }, hal::{ self, - clock::{ClockControl, CpuClock}, + clock::ClockControl, embassy, gdma::*, gpio::{Floating, GpioPin, Input, Output, PullUp, PushPull}, @@ -25,6 +25,7 @@ use crate::board::{ prelude::*, spi::{master::dma::SpiDma, FullDuplexMode}, systimer::SystemTimer, + timer::TimerGroup, Rtc, IO, }, utils::DummyOutputPin, @@ -60,15 +61,18 @@ pub type AdcClockEnable = GpioPin, 38>; pub type AdcDrdy = GpioPin, 4>; pub type AdcReset = GpioPin, 2>; pub type TouchDetect = GpioPin, 1>; -pub type AdcSpi<'d> = - ExclusiveDevice, AdcChipSelect, Delay>; +pub type AdcSpi = ExclusiveDevice< + SpiDma<'static, AdcSpiInstance, Channel1, FullDuplexMode>, + AdcChipSelect, + Delay, +>; pub type VbusDetect = GpioPin, 17>; pub type ChargerStatus = GpioPin, 47>; -pub type EcgFrontend = Frontend, AdcDrdy, AdcReset, AdcClockEnable, TouchDetect>; +pub type EcgFrontend = Frontend; pub type PoweredEcgFrontend = - PoweredFrontend, AdcDrdy, AdcReset, AdcClockEnable, TouchDetect>; + PoweredFrontend; pub type Display = DisplayType; @@ -103,7 +107,7 @@ impl super::startup::StartupResources { let peripherals = Peripherals::take(); let system = peripherals.SYSTEM.split(); - let clocks = ClockControl::configure(system.clock_control, CpuClock::Clock240MHz).freeze(); + let clocks = ClockControl::max(system.clock_control).freeze(); embassy::init(&clocks, SystemTimer::new(peripherals.SYSTIMER)); @@ -125,19 +129,21 @@ impl super::startup::StartupResources { ); let adc = Self::create_frontend_driver( - dma.channel1, - peripherals::Interrupt::DMA_IN_CH1, - peripherals::Interrupt::DMA_OUT_CH1, - peripherals.SPI3, - io.pins.gpio6, - io.pins.gpio7, - io.pins.gpio5, + Self::create_frontend_spi( + dma.channel1, + peripherals::Interrupt::DMA_IN_CH1, + peripherals::Interrupt::DMA_OUT_CH1, + peripherals.SPI3, + io.pins.gpio6, + io.pins.gpio7, + io.pins.gpio5, + io.pins.gpio18, + &clocks, + ), io.pins.gpio4, io.pins.gpio2, io.pins.gpio38, io.pins.gpio1, - io.pins.gpio18, - &clocks, ); // Battery ADC @@ -172,10 +178,9 @@ impl super::startup::StartupResources { wifi: static_cell::make_static! { WifiDriver::new( peripherals.WIFI, - peripherals.TIMG1, + TimerGroup::new(peripherals.TIMG1, &clocks).timer0, peripherals.RNG, system.radio_clock_control, - &clocks, ) }, clocks, diff --git a/src/board/hardware/v4.rs b/src/board/hardware/v4.rs index 778dd10c..62863502 100644 --- a/src/board/hardware/v4.rs +++ b/src/board/hardware/v4.rs @@ -6,7 +6,7 @@ use crate::board::{ }, hal::{ self, - clock::{ClockControl, CpuClock}, + clock::ClockControl, embassy, gdma::*, gpio::{Floating, GpioPin, Input, Output, PullUp, PushPull, Unknown}, @@ -15,6 +15,7 @@ use crate::board::{ prelude::*, spi::{master::dma::SpiDma, FullDuplexMode}, systimer::SystemTimer, + timer::TimerGroup, Rtc, IO, }, utils::DummyOutputPin, @@ -50,16 +51,19 @@ pub type AdcClockEnable = GpioPin, 38>; pub type AdcDrdy = GpioPin, 4>; pub type AdcReset = GpioPin, 2>; pub type TouchDetect = GpioPin, 1>; -pub type AdcSpi<'d> = - ExclusiveDevice, AdcChipSelect, Delay>; +pub type AdcSpi = ExclusiveDevice< + SpiDma<'static, AdcSpiInstance, Channel1, FullDuplexMode>, + AdcChipSelect, + Delay, +>; pub type BatteryAdcEnable = GpioPin, 8>; pub type VbusDetect = GpioPin, 17>; pub type ChargerStatus = GpioPin, 47>; -pub type EcgFrontend = Frontend, AdcDrdy, AdcReset, AdcClockEnable, TouchDetect>; +pub type EcgFrontend = Frontend; pub type PoweredEcgFrontend = - PoweredFrontend, AdcDrdy, AdcReset, AdcClockEnable, TouchDetect>; + PoweredFrontend; pub type Display = DisplayType; @@ -76,7 +80,7 @@ impl super::startup::StartupResources { let peripherals = Peripherals::take(); let system = peripherals.SYSTEM.split(); - let clocks = ClockControl::configure(system.clock_control, CpuClock::Clock240MHz).freeze(); + let clocks = ClockControl::max(system.clock_control).freeze(); embassy::init(&clocks, SystemTimer::new(peripherals.SYSTIMER)); @@ -98,19 +102,21 @@ impl super::startup::StartupResources { ); let adc = Self::create_frontend_driver( - dma.channel1, - peripherals::Interrupt::DMA_IN_CH1, - peripherals::Interrupt::DMA_OUT_CH1, - peripherals.SPI3, - io.pins.gpio6, - io.pins.gpio7, - io.pins.gpio5, + Self::create_frontend_spi( + dma.channel1, + peripherals::Interrupt::DMA_IN_CH1, + peripherals::Interrupt::DMA_OUT_CH1, + peripherals.SPI3, + io.pins.gpio6, + io.pins.gpio7, + io.pins.gpio5, + io.pins.gpio18, + &clocks, + ), io.pins.gpio4, io.pins.gpio2, io.pins.gpio38, io.pins.gpio1, - io.pins.gpio18, - &clocks, ); let battery_monitor = Self::setup_battery_monitor_fg( @@ -132,10 +138,9 @@ impl super::startup::StartupResources { wifi: static_cell::make_static! { WifiDriver::new( peripherals.WIFI, - peripherals.TIMG1, + TimerGroup::new(peripherals.TIMG1, &clocks).timer0, peripherals.RNG, system.radio_clock_control, - &clocks, ) }, clocks, diff --git a/src/board/hardware/v6c6.rs b/src/board/hardware/v6c6.rs new file mode 100644 index 00000000..b9efe869 --- /dev/null +++ b/src/board/hardware/v6c6.rs @@ -0,0 +1,145 @@ +use crate::board::{ + drivers::{ + battery_monitor::battery_fg::BatteryFg as BatteryFgType, + display::Display as DisplayType, + frontend::{Frontend, PoweredFrontend}, + }, + hal::{ + self, + clock::ClockControl, + embassy, + gdma::*, + gpio::{Floating, GpioPin, Input, Output, PullUp, PushPull, Unknown}, + i2c::I2C, + peripherals::{self, Peripherals}, + prelude::*, + spi::{master::dma::SpiDma, FullDuplexMode}, + systimer::SystemTimer, + timer::TimerGroup, + Rtc, IO, + }, + utils::DummyOutputPin, + wifi::WifiDriver, +}; +use display_interface_spi::SPIInterface; +use embassy_time::Delay; +use embedded_hal_bus::spi::ExclusiveDevice; + +pub use crate::board::drivers::bitbang_spi::BitbangSpi; + +pub type DisplaySpiInstance = hal::peripherals::SPI2; +pub type DisplayDmaChannel = ChannelCreator0; +pub type DisplayDataCommand = GpioPin, 8>; +pub type DisplayChipSelect = GpioPin, 11>; +pub type DisplayReset = GpioPin, 10>; +pub type DisplaySclk = GpioPin, 22>; +pub type DisplayMosi = GpioPin, 21>; + +pub type DisplayInterface<'a> = SPIInterface, DisplayDataCommand>; +pub type DisplaySpi<'d> = ExclusiveDevice< + SpiDma<'d, DisplaySpiInstance, Channel0, FullDuplexMode>, + DummyOutputPin, + Delay, +>; + +pub type AdcSclk = GpioPin, 6>; +pub type AdcMosi = GpioPin, 7>; +pub type AdcMiso = GpioPin, 5>; +pub type AdcChipSelect = GpioPin, 9>; +pub type AdcClockEnable = GpioPin, 23>; +pub type AdcDrdy = GpioPin, 4>; +pub type AdcReset = GpioPin, 15>; +pub type TouchDetect = GpioPin, 2>; +pub type AdcSpiBus = BitbangSpi; +pub type AdcSpi = ExclusiveDevice; + +pub type BatteryAdcEnable = DummyOutputPin; +pub type VbusDetect = GpioPin, 3>; +pub type ChargerStatus = GpioPin, 20>; + +pub type EcgFrontend = Frontend; +pub type PoweredEcgFrontend = + PoweredFrontend; + +pub type Display = DisplayType; + +pub type BatteryFgI2cInstance = hal::peripherals::I2C0; +pub type I2cSda = GpioPin; +pub type I2cScl = GpioPin; +pub type BatteryFgI2c = I2C<'static, BatteryFgI2cInstance>; +pub type BatteryFg = BatteryFgType; + +impl super::startup::StartupResources { + pub async fn initialize() -> Self { + Self::common_init(); + + let peripherals = Peripherals::take(); + + let system = peripherals.SYSTEM.split(); + let clocks = ClockControl::max(system.clock_control).freeze(); + + embassy::init(&clocks, TimerGroup::new(peripherals.TIMG0, &clocks).timer0); + + let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); + + let dma = Gdma::new(peripherals.DMA); + + let display = Self::create_display_driver( + dma.channel0, + peripherals::Interrupt::DMA_IN_CH0, + peripherals::Interrupt::DMA_OUT_CH0, + peripherals.SPI2, + io.pins.gpio10, + io.pins.gpio8, + io.pins.gpio11, + io.pins.gpio22, + io.pins.gpio21, + &clocks, + ); + + let adc = Self::create_frontend_driver( + ExclusiveDevice::new( + BitbangSpi::new( + io.pins.gpio7.into(), + io.pins.gpio5.into(), + io.pins.gpio6.into(), + 1u32.MHz(), + ), + io.pins.gpio9.into(), + Delay, + ), + io.pins.gpio4, + io.pins.gpio15, + io.pins.gpio23, + io.pins.gpio2, + ); + + let battery_monitor = Self::setup_battery_monitor_fg( + peripherals.I2C0, + peripherals::Interrupt::I2C_EXT0, + io.pins.gpio19, + io.pins.gpio18, + io.pins.gpio3, + io.pins.gpio20, + DummyOutputPin, + &clocks, + ) + .await; + + Self { + display, + frontend: adc, + battery_monitor, + wifi: static_cell::make_static! { + WifiDriver::new( + peripherals.WIFI, + SystemTimer::new(peripherals.SYSTIMER).alarm0, + peripherals.RNG, + system.radio_clock_control, + ) + }, + clocks, + rtc: Rtc::new(peripherals.LP_CLKRST), + } + } +} diff --git a/src/board/hardware/v6s3.rs b/src/board/hardware/v6s3.rs new file mode 100644 index 00000000..596bc4a8 --- /dev/null +++ b/src/board/hardware/v6s3.rs @@ -0,0 +1,146 @@ +use crate::board::{ + drivers::{ + battery_monitor::battery_fg::BatteryFg as BatteryFgType, + display::Display as DisplayType, + frontend::{Frontend, PoweredFrontend}, + }, + hal::{ + self, + clock::ClockControl, + embassy, + gdma::*, + gpio::{Floating, GpioPin, Input, Output, PullUp, PushPull, Unknown}, + i2c::I2C, + peripherals::{self, Peripherals}, + prelude::*, + spi::{master::dma::SpiDma, FullDuplexMode}, + systimer::SystemTimer, + timer::TimerGroup, + Rtc, IO, + }, + utils::DummyOutputPin, + wifi::WifiDriver, +}; +use display_interface_spi::SPIInterface; +use embassy_time::Delay; +use embedded_hal_bus::spi::ExclusiveDevice; + +pub type DisplaySpiInstance = hal::peripherals::SPI2; +pub type DisplayDmaChannel = ChannelCreator0; +pub type DisplayDataCommand = GpioPin, 17>; +pub type DisplayChipSelect = GpioPin, 8>; +pub type DisplayReset = GpioPin, 18>; +pub type DisplaySclk = GpioPin, 39>; +pub type DisplayMosi = GpioPin, 38>; + +pub type DisplayInterface<'a> = SPIInterface, DisplayDataCommand>; +pub type DisplaySpi<'d> = ExclusiveDevice< + SpiDma<'d, DisplaySpiInstance, Channel0, FullDuplexMode>, + DummyOutputPin, + Delay, +>; + +pub type AdcDmaChannel = ChannelCreator1; +pub type AdcSpiInstance = hal::peripherals::SPI3; +pub type AdcSclk = GpioPin, 6>; +pub type AdcMosi = GpioPin, 7>; +pub type AdcMiso = GpioPin, 5>; +pub type AdcChipSelect = GpioPin, 0>; +pub type AdcClockEnable = GpioPin, 40>; +pub type AdcDrdy = GpioPin, 4>; +pub type AdcReset = GpioPin, 42>; +pub type TouchDetect = GpioPin, 1>; +pub type AdcSpiBus = SpiDma<'static, AdcSpiInstance, Channel1, FullDuplexMode>; +pub type AdcSpi = ExclusiveDevice; + +pub type BatteryAdcEnable = DummyOutputPin; +pub type VbusDetect = GpioPin, 2>; +pub type ChargerStatus = GpioPin, 37>; + +pub type EcgFrontend = Frontend; +pub type PoweredEcgFrontend = + PoweredFrontend; + +pub type Display = DisplayType; + +pub type BatteryFgI2cInstance = hal::peripherals::I2C0; +pub type I2cSda = GpioPin; +pub type I2cScl = GpioPin; +pub type BatteryFgI2c = I2C<'static, BatteryFgI2cInstance>; +pub type BatteryFg = BatteryFgType; + +impl super::startup::StartupResources { + pub async fn initialize() -> Self { + Self::common_init(); + + let peripherals = Peripherals::take(); + + let system = peripherals.SYSTEM.split(); + let clocks = ClockControl::max(system.clock_control).freeze(); + + embassy::init(&clocks, SystemTimer::new(peripherals.SYSTIMER)); + + let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); + + let dma = Gdma::new(peripherals.DMA); + + let display = Self::create_display_driver( + dma.channel0, + peripherals::Interrupt::DMA_IN_CH0, + peripherals::Interrupt::DMA_OUT_CH0, + peripherals.SPI2, + io.pins.gpio18, + io.pins.gpio17, + io.pins.gpio8, + io.pins.gpio39, + io.pins.gpio38, + &clocks, + ); + + let adc = Self::create_frontend_driver( + Self::create_frontend_spi( + dma.channel1, + peripherals::Interrupt::DMA_IN_CH1, + peripherals::Interrupt::DMA_OUT_CH1, + peripherals.SPI3, + io.pins.gpio6, + io.pins.gpio7, + io.pins.gpio5, + io.pins.gpio0, + &clocks, + ), + io.pins.gpio4, + io.pins.gpio42, + io.pins.gpio40, + io.pins.gpio1, + ); + + let battery_monitor = Self::setup_battery_monitor_fg( + peripherals.I2C0, + peripherals::Interrupt::I2C_EXT0, + io.pins.gpio36, + io.pins.gpio35, + io.pins.gpio2, + io.pins.gpio37, + DummyOutputPin, + &clocks, + ) + .await; + + Self { + display, + frontend: adc, + battery_monitor, + wifi: static_cell::make_static! { + WifiDriver::new( + peripherals.WIFI, + TimerGroup::new(peripherals.TIMG1, &clocks).timer0, + peripherals.RNG, + system.radio_clock_control, + ) + }, + clocks, + rtc: Rtc::new(peripherals.RTC_CNTL), + } + } +} diff --git a/src/board/mod.rs b/src/board/mod.rs index aa4f50f1..60863970 100644 --- a/src/board/mod.rs +++ b/src/board/mod.rs @@ -1,10 +1,17 @@ #[cfg_attr(feature = "hw_v1", path = "hardware/v1.rs")] #[cfg_attr(feature = "hw_v2", path = "hardware/v2.rs")] #[cfg_attr(feature = "hw_v4", path = "hardware/v4.rs")] -#[cfg_attr( // We default to hw_v2 if no feature is selected to help rust-analyzer for example - // TODO - not(any(feature = "hw_v1", feature = "hw_v2", feature = "hw_v4")), - path = "hardware/v2.rs" +#[cfg_attr(all(feature = "hw_v6", feature = "esp32s3"), path = "hardware/v6s3.rs")] +#[cfg_attr(all(feature = "hw_v6", feature = "esp32c6"), path = "hardware/v6c6.rs")] +#[cfg_attr( // We default to hw_v6/esp32c6 if no feature is selected to help rust-analyzer for example + not(any( + feature = "hw_v1", + feature = "hw_v2", + feature = "hw_v4", + all(feature = "hw_v6", feature = "esp32s3"), + all(feature = "hw_v6", feature = "esp32c6") + )), + path = "hardware/v6c6.rs" )] pub mod hardware; @@ -25,7 +32,30 @@ pub use esp32s2_hal as hal; #[cfg(feature = "esp32s3")] pub use esp32s3_hal as hal; +#[cfg(feature = "esp32c6")] +pub use esp32c6_hal as hal; + pub use hardware::*; pub const DEFAULT_BACKEND_URL: &str = "https://stingray-prime-monkey.ngrok-free.app"; pub const LOW_BATTERY_PERCENTAGE: u8 = 5; + +#[cfg(feature = "esp32c6")] +#[no_mangle] +extern "C" fn fminf(x: f32, y: f32) -> f32 { + if x < y { + x + } else { + y + } +} + +#[cfg(feature = "esp32c6")] +#[no_mangle] +extern "C" fn fmaxf(x: f32, y: f32) -> f32 { + if x > y { + x + } else { + y + } +} diff --git a/src/board/ota/mod.rs b/src/board/ota/mod.rs index c93157d6..fc677b22 100644 --- a/src/board/ota/mod.rs +++ b/src/board/ota/mod.rs @@ -4,7 +4,14 @@ use crc::{Algorithm, Crc}; use macros::partition; use norfs::medium::StorageMedium; use norfs_driver::medium::MediumError; -use norfs_esp32s3::{InternalDriver, InternalPartition, SmallInternalDriver}; + +#[cfg(feature = "esp32s3")] +use norfs_esp32s3 as norfs_impl; + +#[cfg(feature = "esp32c6")] +use norfs_esp32c6 as norfs_impl; + +use norfs_impl::{InternalDriver, InternalPartition, SmallInternalDriver}; #[partition("otadata")] pub struct OtaDataPartition; diff --git a/src/board/startup.rs b/src/board/startup.rs index cc69f9a6..9ed4715e 100644 --- a/src/board/startup.rs +++ b/src/board/startup.rs @@ -1,6 +1,5 @@ use display_interface_spi::SPIInterface; use embassy_time::Delay; -use embedded_hal::digital::OutputPin; use embedded_hal_bus::spi::ExclusiveDevice; use static_cell::make_static; @@ -13,24 +12,23 @@ use crate::{ gpio::OutputPin as _, interrupt, peripherals, spi::{ - master::{ - dma::{WithDmaSpi2, WithDmaSpi3}, - Instance, Spi, - }, + master::{dma::*, Instance, Spi}, SpiMode, }, Rtc, }, utils::DummyOutputPin, wifi::WifiDriver, - AdcChipSelect, AdcClockEnable, AdcDmaChannel, AdcDrdy, AdcMiso, AdcMosi, AdcReset, AdcSclk, - AdcSpiInstance, ChargerStatus, Display, DisplayChipSelect, DisplayDataCommand, - DisplayDmaChannel, DisplayMosi, DisplayReset, DisplaySclk, DisplaySpiInstance, EcgFrontend, - TouchDetect, VbusDetect, + AdcClockEnable, AdcDrdy, AdcReset, AdcSpi, ChargerStatus, Display, DisplayChipSelect, + DisplayDataCommand, DisplayDmaChannel, DisplayMosi, DisplayReset, DisplaySclk, + DisplaySpiInstance, EcgFrontend, TouchDetect, VbusDetect, }, heap::init_heap, }; +#[cfg(feature = "esp32s3")] +use crate::board::{AdcChipSelect, AdcDmaChannel, AdcMiso, AdcMosi, AdcSclk, AdcSpiInstance}; + #[cfg(feature = "battery_max17055")] use { crate::{ @@ -63,17 +61,34 @@ impl StartupResources { use core::ptr::addr_of; - extern "C" { - static mut _stack_start_cpu0: u8; - static mut _stack_end_cpu0: u8; - } + #[cfg(feature = "esp32s3")] + let stack_range = { + extern "C" { + static mut _stack_start_cpu0: u8; + static mut _stack_end_cpu0: u8; + } + + // We only use a single core for now, so we can write both stack regions. + let stack_start = unsafe { addr_of!(_stack_start_cpu0) as usize }; + let stack_end = unsafe { addr_of!(_stack_end_cpu0) as usize }; - // We only use a single core for now, so we can write both stack regions. - let stack_start = unsafe { addr_of!(_stack_start_cpu0) as usize }; - let stack_end = unsafe { addr_of!(_stack_end_cpu0) as usize }; - let _stack_protection = make_static!(crate::stack_protection::StackMonitor::protect( stack_start..stack_end - )); + }; + #[cfg(feature = "esp32c6")] + let stack_range = { + extern "C" { + static mut _stack_start: u8; + static mut _stack_end: u8; + } + + // We only use a single core for now, so we can write both stack regions. + let stack_start = unsafe { addr_of!(_stack_start) as usize }; + let stack_end = unsafe { addr_of!(_stack_end) as usize }; + + stack_start..stack_end + }; + let _stack_protection = + make_static!(crate::stack_protection::StackMonitor::protect(stack_range)); } #[inline(always)] @@ -106,20 +121,15 @@ impl StartupResources { const DESCR_SET_COUNT: usize = 1; static mut DISP_SPI_DESCRIPTORS: [u32; DESCR_SET_COUNT * 3] = [0; DESCR_SET_COUNT * 3]; static mut DISP_SPI_RX_DESCRIPTORS: [u32; DESCR_SET_COUNT * 3] = [0; DESCR_SET_COUNT * 3]; - let display_spi = Spi::new_no_cs_no_miso( - display_spi, - display_sclk.into(), - display_mosi.into(), - 40u32.MHz(), - SpiMode::Mode0, - clocks, - ) - .with_dma(display_dma_channel.configure( - false, - unsafe { &mut DISP_SPI_DESCRIPTORS }, - unsafe { &mut DISP_SPI_RX_DESCRIPTORS }, - DmaPriority::Priority0, - )); + let display_spi = Spi::new(display_spi, 40u32.MHz(), SpiMode::Mode0, clocks) + .with_sck(display_sclk.into()) + .with_mosi(display_mosi.into()) + .with_dma(display_dma_channel.configure( + false, + unsafe { &mut DISP_SPI_DESCRIPTORS }, + unsafe { &mut DISP_SPI_RX_DESCRIPTORS }, + DmaPriority::Priority0, + )); Display::new( SPIInterface::new( @@ -132,7 +142,8 @@ impl StartupResources { #[inline(always)] #[allow(clippy::too_many_arguments)] - pub(crate) fn create_frontend_driver( + #[cfg(feature = "esp32s3")] + pub(crate) fn create_frontend_spi( adc_dma_channel: AdcDmaChannel, dma_in_interrupt: peripherals::Interrupt, dma_out_interrupt: peripherals::Interrupt, @@ -140,14 +151,12 @@ impl StartupResources { adc_sclk: impl Into, adc_mosi: impl Into, adc_miso: impl Into, - adc_drdy: impl Into, - adc_reset: impl Into, - adc_clock_enable: impl Into, - touch_detect: impl Into, adc_cs: impl Into, clocks: &Clocks, - ) -> EcgFrontend { + ) -> AdcSpi { + use embedded_hal::digital::OutputPin; + unwrap!(interrupt::enable( dma_in_interrupt, interrupt::Priority::Priority1 @@ -157,12 +166,6 @@ impl StartupResources { interrupt::Priority::Priority1 )); - // DRDY - unwrap!(interrupt::enable( - peripherals::Interrupt::GPIO, - interrupt::Priority::Priority3, - )); - let mut adc_cs: AdcChipSelect = adc_cs.into(); unwrap!(adc_cs.set_high().ok()); @@ -170,26 +173,39 @@ impl StartupResources { const DESCR_SET_COUNT: usize = 1; static mut ADC_SPI_DESCRIPTORS: [u32; DESCR_SET_COUNT * 3] = [0; DESCR_SET_COUNT * 3]; static mut ADC_SPI_RX_DESCRIPTORS: [u32; DESCR_SET_COUNT * 3] = [0; DESCR_SET_COUNT * 3]; - Frontend::new( - ExclusiveDevice::new( - Spi::new_no_cs( - adc_spi, - adc_sclk.into(), - adc_mosi.into(), - adc_miso.into(), - 1u32.MHz(), - SpiMode::Mode1, - clocks, - ) + + ExclusiveDevice::new( + Spi::new(adc_spi, 1u32.MHz(), SpiMode::Mode1, clocks) + .with_sck(adc_sclk.into()) + .with_mosi(adc_mosi.into()) + .with_miso(adc_miso.into()) .with_dma(adc_dma_channel.configure( false, unsafe { &mut ADC_SPI_DESCRIPTORS }, unsafe { &mut ADC_SPI_RX_DESCRIPTORS }, DmaPriority::Priority1, )), - adc_cs, - Delay, - ), + adc_cs, + Delay, + ) + } + + #[inline(always)] + pub(crate) fn create_frontend_driver( + adc_spi: AdcSpi, + adc_drdy: impl Into, + adc_reset: impl Into, + adc_clock_enable: impl Into, + touch_detect: impl Into, + ) -> EcgFrontend { + // DRDY + unwrap!(interrupt::enable( + peripherals::Interrupt::GPIO, + interrupt::Priority::Priority3, + )); + + Frontend::new( + adc_spi, adc_drdy.into(), adc_reset.into(), adc_clock_enable.into(), diff --git a/src/board/storage.rs b/src/board/storage.rs index e53a635b..7ade5420 100644 --- a/src/board/storage.rs +++ b/src/board/storage.rs @@ -2,7 +2,14 @@ use core::ops::{Deref, DerefMut}; use macros::partition; use norfs::{medium::cache::ReadCache, Storage, StorageError}; -use norfs_esp32s3::{InternalDriver, InternalPartition}; + +#[cfg(feature = "esp32s3")] +use norfs_esp32s3 as norfs_impl; + +#[cfg(feature = "esp32c6")] +use norfs_esp32c6 as norfs_impl; + +use norfs_impl::{InternalDriver, InternalPartition}; #[partition("storage")] pub struct ConfigPartition; diff --git a/src/board/wifi/mod.rs b/src/board/wifi/mod.rs index e889d997..3ff0cd93 100644 --- a/src/board/wifi/mod.rs +++ b/src/board/wifi/mod.rs @@ -1,13 +1,18 @@ use core::{hint::unreachable_unchecked, mem, ops::Deref, ptr::NonNull}; +#[cfg(feature = "esp32s3")] +type WifiTimer = + crate::hal::timer::Timer>; +#[cfg(feature = "esp32c6")] +type WifiTimer = crate::hal::systimer::Alarm; + use crate::{ board::{ hal::{ clock::Clocks, - peripherals::{RNG, TIMG1, WIFI}, + peripherals::{RNG, WIFI}, system::RadioClockControl, - timer::{Timer0, TimerGroup}, - Rng, Timer, + Rng, }, wifi::{ ap::{Ap, ApState}, @@ -85,7 +90,7 @@ pub struct WifiDriver { } struct WifiInitResources { - timer: Timer>, + timer: WifiTimer, rng: Rng, rcc: RadioClockControl, } @@ -141,22 +146,12 @@ impl WifiDriverState { } impl WifiDriver { - pub fn new( - wifi: WIFI, - timer: TIMG1, - rng: RNG, - rcc: RadioClockControl, - clocks: &Clocks, - ) -> Self { + pub fn new(wifi: WIFI, timer: WifiTimer, rng: RNG, rcc: RadioClockControl) -> Self { let rng = Rng::new(rng); Self { wifi, rng, - state: WifiDriverState::Uninitialized(WifiInitResources { - timer: TimerGroup::new(timer, clocks).timer0, - rng, - rcc, - }), + state: WifiDriverState::Uninitialized(WifiInitResources { timer, rng, rcc }), } } diff --git a/src/main.rs b/src/main.rs index 26abd227..f4626fbb 100644 --- a/src/main.rs +++ b/src/main.rs @@ -28,20 +28,9 @@ use norfs::{medium::StorageMedium, Storage, StorageError}; use signal_processing::compressing_buffer::CompressingBuffer; use static_cell::StaticCell; -#[cfg(feature = "hw_v1")] -use crate::{ - board::{hal::gpio::RTCPinWithResistors, ChargerStatus}, - sleep::disable_gpio_wakeup, -}; - -#[cfg(any(feature = "hw_v2", feature = "hw_v4"))] -use crate::board::VbusDetect; - #[cfg(feature = "battery_max17055")] pub use crate::states::menu::battery_info::battery_info_menu; -#[cfg(feature = "hw_v1")] -use crate::states::adc_setup::adc_setup; use crate::{ board::{ config::{Config, ConfigFile}, @@ -49,16 +38,13 @@ use crate::{ self, embassy::executor::{FromCpu1, InterruptExecutor}, entry, - gpio::RTCPin, interrupt::Priority, prelude::{interrupt, main}, - rtc_cntl::sleep::{RtcioWakeupSource, WakeupLevel}, Delay, }, initialized::{Context, InnerContext}, startup::StartupResources, storage::FileSystem, - TouchDetect, }, states::{ charging::charging, @@ -76,9 +62,27 @@ use crate::{ }, }; +#[cfg(feature = "hw_v1")] +use crate::{board::ChargerStatus, sleep::disable_gpio_wakeup, states::adc_setup::adc_setup}; + +use crate::board::{ + hal::rtc_cntl::{sleep, sleep::WakeupLevel}, + TouchDetect, +}; + +#[cfg(any(feature = "hw_v2", feature = "hw_v4", feature = "hw_v6"))] +use crate::board::VbusDetect; + +#[cfg(feature = "esp32s3")] +use crate::board::hal::gpio::RTCPin as RtcWakeupPin; + +#[cfg(feature = "esp32c6")] +use crate::board::hal::gpio::RTCPinWithResistors as RtcWakeupPin; + mod board; mod heap; pub mod human_readable; +#[cfg(feature = "hw_v1")] mod sleep; mod stack_protection; mod states; @@ -227,6 +231,9 @@ async fn main(_spawner: Spawner) { #[cfg(feature = "hw_v4")] info!("Hardware version: v4"); + #[cfg(feature = "hw_v6")] + info!("Hardware version: v6"); + let mut storage = FileSystem::mount().await; let config = load_config(storage.as_deref_mut()).await; @@ -306,34 +313,33 @@ async fn main(_spawner: Spawner) { let battery_monitor = board.inner.battery_monitor; + let mut rtc = resources.rtc; let is_charging = battery_monitor.is_plugged(); #[cfg(feature = "hw_v1")] let (_, mut charger_pin) = battery_monitor.stop().await; - #[cfg(any(feature = "hw_v2", feature = "hw_v4"))] + #[cfg(not(feature = "hw_v1"))] let (mut charger_pin, _) = battery_monitor.stop().await; let (_, _, _, mut touch) = board.frontend.split(); - let mut rtc = resources.rtc; - let mut wakeup_pins = heapless::Vec::<(&mut dyn RTCPin, WakeupLevel), 2>::new(); - setup_wakeup_pins(&mut wakeup_pins, &mut touch, &mut charger_pin, is_charging); - let rtcio = RtcioWakeupSource::new(&mut wakeup_pins); - - rtc.sleep_deep(&[&rtcio], &mut delay); + let mut wakeup_pins = heapless::Vec::<(&mut dyn RtcWakeupPin, WakeupLevel), 2>::new(); + let wakeup_source = + setup_wakeup_pins(&mut wakeup_pins, &mut touch, &mut charger_pin, is_charging); + rtc.sleep_deep(&[&wakeup_source], &mut delay); // Shouldn't reach this. If we do, we just exit the task, which means the executor // will have nothing else to do. Not ideal, but again, we shouldn't reach this. } #[cfg(feature = "hw_v1")] -fn setup_wakeup_pins<'a, const N: usize>( - wakeup_pins: &mut heapless::Vec<(&'a mut dyn RTCPin, WakeupLevel), N>, - touch: &'a mut TouchDetect, - charger_pin: &'a mut ChargerStatus, +fn setup_wakeup_pins<'a, 'b, const N: usize>( + wakeup_pins: &'a mut heapless::Vec<(&'b mut dyn RtcWakeupPin, WakeupLevel), N>, + touch: &'b mut TouchDetect, + charger_pin: &'b mut ChargerStatus, is_charging: bool, -) { +) -> sleep::RtcioWakeupSource<'a, 'b> { unwrap!(wakeup_pins.push((touch, WakeupLevel::Low)).ok()); if is_charging { @@ -351,15 +357,45 @@ fn setup_wakeup_pins<'a, const N: usize>( unwrap!(wakeup_pins.push((charger_pin, WakeupLevel::Low)).ok()); } + + sleep::RtcioWakeupSource::new(wakeup_pins) +} + +#[cfg(any( + feature = "hw_v2", + feature = "hw_v4", + all(feature = "hw_v6", feature = "esp32s3") +))] +fn setup_wakeup_pins<'a, 'b, const N: usize>( + wakeup_pins: &'a mut heapless::Vec<(&'b mut dyn RtcWakeupPin, WakeupLevel), N>, + touch: &'b mut TouchDetect, + charger_pin: &'b mut VbusDetect, + is_charging: bool, +) -> sleep::RtcioWakeupSource<'a, 'b> { + let charger_level = if is_charging { + // Wake up momentarily when charger is disconnected + WakeupLevel::Low + } else { + // We want to wake up when the charger is connected, or the electrodes are touched. + + // In v2, the charger status is not connected to an RTC IO pin, so we use the VBUS + // detect pin instead. This is a high level signal when the charger is connected. + WakeupLevel::High + }; + + unwrap!(wakeup_pins.push((touch, WakeupLevel::Low)).ok()); + unwrap!(wakeup_pins.push((charger_pin, charger_level)).ok()); + + sleep::RtcioWakeupSource::new(wakeup_pins) } -#[cfg(any(feature = "hw_v2", feature = "hw_v4"))] -fn setup_wakeup_pins<'a, const N: usize>( - wakeup_pins: &mut heapless::Vec<(&'a mut dyn RTCPin, WakeupLevel), N>, - touch: &'a mut TouchDetect, - charger_pin: &'a mut VbusDetect, +#[cfg(all(feature = "hw_v6", feature = "esp32c6"))] +fn setup_wakeup_pins<'a, 'b, const N: usize>( + wakeup_pins: &'a mut heapless::Vec<(&'b mut dyn RtcWakeupPin, WakeupLevel), N>, + touch: &'b mut TouchDetect, + charger_pin: &'b mut VbusDetect, is_charging: bool, -) { +) -> sleep::Ext1WakeupSource<'a, 'b> { let charger_level = if is_charging { // Wake up momentarily when charger is disconnected WakeupLevel::Low @@ -373,4 +409,6 @@ fn setup_wakeup_pins<'a, const N: usize>( unwrap!(wakeup_pins.push((touch, WakeupLevel::Low)).ok()); unwrap!(wakeup_pins.push((charger_pin, charger_level)).ok()); + + sleep::Ext1WakeupSource::new(wakeup_pins) } diff --git a/src/sleep.rs b/src/sleep.rs index c9d234f4..b5ee20f3 100644 --- a/src/sleep.rs +++ b/src/sleep.rs @@ -1,6 +1,5 @@ use crate::board::hal::{gpio::GpioPin, peripherals}; -#[allow(unused)] enum RtcioWakeupType { Disable = 0, LowLevel = 4, @@ -21,7 +20,6 @@ fn enable_gpio_wakeup(_pin: &GpioPin, level: Rtc } // Wakeup remains enabled after waking from deep sleep, so we need to disable it manually. -#[allow(unused)] pub fn disable_gpio_wakeup(pin: &GpioPin) { enable_gpio_wakeup(pin, RtcioWakeupType::Disable) } diff --git a/src/stack_protection.rs b/src/stack_protection.rs index d0b2f306..90918639 100644 --- a/src/stack_protection.rs +++ b/src/stack_protection.rs @@ -26,10 +26,16 @@ impl StackMonitor { /// accessing the canary prior to that. However, this is a good enough approximation for our /// purposes. pub fn protect(stack: Range) -> Self { + let (bottom, top) = if stack.start < stack.end { + (stack.start, stack.end) + } else { + (stack.end, stack.start) + }; + info!( "StackMonitor::protect({:?}, {})", - stack.start as *const u32, - stack.end - stack.start + top as *const u32, + top - bottom ); let mut assist = conjure(); @@ -39,14 +45,15 @@ impl StackMonitor { // We watch writes to the last word in the stack. match get_core() { Cpu::ProCpu => assist.enable_region0_monitor( - stack.start as u32 + CANARY_GRANULARITY, - stack.start as u32 + CANARY_GRANULARITY + CANARY_UNITS * CANARY_GRANULARITY, + bottom as u32 + CANARY_GRANULARITY, + bottom as u32 + CANARY_GRANULARITY + CANARY_UNITS * CANARY_GRANULARITY, true, true, ), + #[cfg(feature = "esp32s3")] Cpu::AppCpu => assist.enable_core1_region0_monitor( - stack.start as u32 + CANARY_GRANULARITY, - stack.start as u32 + CANARY_GRANULARITY + CANARY_UNITS * CANARY_GRANULARITY, + bottom as u32 + CANARY_GRANULARITY, + bottom as u32 + CANARY_GRANULARITY + CANARY_UNITS * CANARY_GRANULARITY, true, true, ), @@ -65,6 +72,7 @@ impl Drop for StackMonitor { fn drop(&mut self) { match get_core() { Cpu::ProCpu => self.assist.disable_region0_monitor(), + #[cfg(feature = "esp32s3")] Cpu::AppCpu => self.assist.disable_core1_region0_monitor(), } } @@ -84,6 +92,7 @@ fn ASSIST_DEBUG() { pc = da.get_region_monitor_pc(); da.clear_region0_monitor_interrupt(); } + #[cfg(feature = "esp32s3")] Cpu::AppCpu => { is_overflow = da.is_core1_region0_monitor_interrupt_set(); pc = da.get_core1_region_monitor_pc(); diff --git a/src/states/measure.rs b/src/states/measure.rs index c3cdbf50..50bf4654 100644 --- a/src/states/measure.rs +++ b/src/states/measure.rs @@ -40,10 +40,7 @@ type MessageQueue = Channel; unsafe impl Send for PoweredEcgFrontend {} struct EcgTaskParams { - token: TaskControlToken< - Result<(), Error< as ErrorType>::Error>>, - PoweredEcgFrontend, - >, + token: TaskControlToken::Error>>, PoweredEcgFrontend>, sender: Arc, } @@ -338,7 +335,7 @@ async fn reader_task(params: EcgTaskParams) { async fn read_ecg( queue: &MessageQueue, frontend: &mut PoweredEcgFrontend, -) -> Result<(), Error< as ErrorType>::Error>> { +) -> Result<(), Error<::Error>> { loop { match frontend.read().await { Ok(sample) => { diff --git a/xtask/src/main.rs b/xtask/src/main.rs index 3b8c55d6..87445b93 100644 --- a/xtask/src/main.rs +++ b/xtask/src/main.rs @@ -1,4 +1,4 @@ -use std::env; +use std::{env, path::PathBuf}; use anyhow::Result as AnyResult; use clap::{Parser, Subcommand, ValueEnum}; @@ -11,7 +11,6 @@ pub enum Subcommands { Build { /// Which hardware version to build for. hw: Option, - variant: Option, }, /// Builds the firmware and dumps the assembly. @@ -24,15 +23,19 @@ pub enum Subcommands { Test, /// Connects to the Card/IO device to display serial output. - Monitor { variant: Option }, + Monitor { + /// Which hardware version is connected. + hw: Option, + + profile: Option, + }, /// Builds, flashes and runs the firmware on a connected device. Run { /// Which hardware version to run on. hw: Option, - #[arg(long)] - release: bool, + profile: Option, }, /// Checks the project for errors. @@ -75,8 +78,10 @@ pub enum Subcommands { pub enum HardwareVersion { V1, V2, - #[default] V4, + V6S3, + #[default] + V6C6, } impl HardwareVersion { @@ -85,21 +90,38 @@ impl HardwareVersion { HardwareVersion::V1 => "hw_v1", HardwareVersion::V2 => "hw_v2", HardwareVersion::V4 => "hw_v4", + HardwareVersion::V6S3 => "hw_v6,esp32s3", + HardwareVersion::V6C6 => "hw_v6,esp32c6", } } -} -#[derive(Debug, Clone, Copy, PartialEq, Eq, ValueEnum)] -pub enum BuildVariant { - StackSizes, + fn soc(&self) -> SocConfig { + match self { + HardwareVersion::V6C6 => SocConfig::C6, + _ => SocConfig::S3, + } + } + + fn flash_size(&self) -> u32 { + 2 + } } #[derive(Debug, Clone, Copy, PartialEq, Eq, ValueEnum)] -pub enum MonitorVariant { +pub enum Profile { Debug, Release, } +impl Profile { + fn as_str(&self) -> &str { + match self { + Profile::Debug => "debug", + Profile::Release => "release", + } + } +} + #[derive(Debug, Parser)] #[clap(about, version, propagate_version = true)] pub struct Cli { @@ -116,49 +138,30 @@ fn cargo(command: &[&str]) -> Expression { cmd("rustup", args_vec) } -fn build(hw: HardwareVersion, opt: Option, timings: bool) -> AnyResult<()> { - let build_flags = [ - "--target=xtensa-esp32s3-none-elf", - &format!("--features={}", hw.feature()), - "-Zbuild-std=core,alloc", - "-Zbuild-std-features=panic_immediate_abort", - ]; - - if let Some(option) = opt { - match option { - BuildVariant::StackSizes => { - let mut command = vec!["rustc"]; - - command.extend_from_slice(&build_flags); - command.extend_from_slice(&[ - "--profile=lto", - "--", - "-Zemit-stack-sizes", - "--emit=llvm-bc", - ]); - - cargo(&command).run()?; - - return Ok(()); - } - } - } +fn build(config: BuildConfig, timings: bool) -> AnyResult<()> { + let build_flags = config.build_flags(); + let build_flags = build_flags.iter().map(|s| s.as_str()).collect::>(); if timings { - let mut command = vec!["build", "--release", "--timings"]; + let mut command = vec!["build", "--timings"]; command.extend_from_slice(&build_flags); cargo(&command).run()?; } + match config.soc { + SocConfig::S3 => std::fs::copy("cfg_esp32s3.toml", "cfg.toml").ok(), + SocConfig::C6 => std::fs::copy("cfg_esp32c6.toml", "cfg.toml").ok(), + }; + + let flash_size = format!("-s{}mb", config.version.flash_size()); let mut command = vec![ "espflash", "save-image", - "--release", "--chip", - "esp32s3", - "-s2mb", + config.soc.chip(), + &flash_size, "target/card_io_fw.bin", ]; command.extend_from_slice(&build_flags); @@ -168,18 +171,9 @@ fn build(hw: HardwareVersion, opt: Option, timings: bool) -> AnyRe Ok(()) } -fn run(hw: HardwareVersion, release: bool) -> AnyResult<()> { - let hw = format!("--features={}", hw.feature()); - let mut build_flags = vec![ - "--target=xtensa-esp32s3-none-elf", - &hw, - "-Zbuild-std=core,alloc", - ]; - - if release { - build_flags.push("--release"); - build_flags.push("-Zbuild-std-features=panic_immediate_abort"); - } +fn run(config: BuildConfig) -> AnyResult<()> { + let build_flags = config.build_flags(); + let build_flags = build_flags.iter().map(|s| s.as_str()).collect::>(); // println!("🛠️ Building firmware"); // @@ -190,6 +184,11 @@ fn run(hw: HardwareVersion, release: bool) -> AnyResult<()> { println!("💾 Building and flashing firmware"); + match config.soc { + SocConfig::S3 => std::fs::copy("cfg_esp32s3.toml", "cfg.toml").ok(), + SocConfig::C6 => std::fs::copy("cfg_esp32c6.toml", "cfg.toml").ok(), + }; + let mut args = vec![ "espflash", "flash", @@ -204,17 +203,12 @@ fn run(hw: HardwareVersion, release: bool) -> AnyResult<()> { Ok(()) } -fn monitor(variant: MonitorVariant) -> AnyResult<()> { - let variant = match variant { - MonitorVariant::Debug => "debug", - MonitorVariant::Release => "release", - }; - +fn monitor(config: BuildConfig) -> AnyResult<()> { cargo(&[ "espflash", "monitor", "-e", - &format!("./target/xtensa-esp32s3-none-elf/{variant}/card_io_fw"), + &config.elf_string(), "--log-format=defmt", ]) .run()?; @@ -222,28 +216,24 @@ fn monitor(variant: MonitorVariant) -> AnyResult<()> { Ok(()) } -fn checks(hw: HardwareVersion) -> AnyResult<()> { - cargo(&[ - "check", - "--target=xtensa-esp32s3-none-elf", - "-Zbuild-std=core,alloc", - "-Zbuild-std-features=panic_immediate_abort", - &format!("--features={}", hw.feature()), - ]) - .run()?; +fn checks(config: BuildConfig) -> AnyResult<()> { + let build_flags = config.build_flags(); + let build_flags = build_flags.iter().map(|s| s.as_str()).collect::>(); + + let mut args = vec!["check"]; + args.extend_from_slice(&build_flags); + + cargo(&args).run()?; Ok(()) } -fn docs(open: bool, hw: HardwareVersion) -> AnyResult<()> { - let hw = format!("--features={}", hw.feature()); - let mut args = vec![ - "doc", - "--target=xtensa-esp32s3-none-elf", - "-Zbuild-std=core,alloc", - "-Zbuild-std-features=panic_immediate_abort", - &hw, - ]; +fn docs(config: BuildConfig, open: bool) -> AnyResult<()> { + let build_flags = config.build_flags(); + let build_flags = build_flags.iter().map(|s| s.as_str()).collect::>(); + + let mut args = vec!["doc"]; + args.extend_from_slice(&build_flags); if open { args.push("--open"); @@ -254,16 +244,16 @@ fn docs(open: bool, hw: HardwareVersion) -> AnyResult<()> { Ok(()) } -fn extra_checks(hw: HardwareVersion) -> AnyResult<()> { +fn extra_checks(config: BuildConfig) -> AnyResult<()> { cargo(&["fmt", "--check"]).run()?; - cargo(&[ - "clippy", - "--target=xtensa-esp32s3-none-elf", - "-Zbuild-std=core,alloc", - "-Zbuild-std-features=panic_immediate_abort", - &format!("--features={}", hw.feature()), - ]) - .run()?; + + let build_flags = config.build_flags(); + let build_flags = build_flags.iter().map(|s| s.as_str()).collect::>(); + + let mut args = vec!["clippy"]; + args.extend_from_slice(&build_flags); + + cargo(&args).run()?; Ok(()) } @@ -304,13 +294,12 @@ fn example(package: String, name: String, watch: bool) -> AnyResult<()> { Ok(()) } -fn asm() -> AnyResult<()> { - let elf = "./target/xtensa-esp32s3-none-elf/release/card_io_fw"; - cmd!("xtensa-esp32s3-elf-objdump", "-d", elf) +fn asm(config: BuildConfig) -> AnyResult<()> { + cmd!(config.tool("objdump"), "-d", config.elf_string()) .stdout_path("target/asm.s") .run()?; - cmd!("xtensa-esp32s3-elf-nm", elf, "-S", "--size-sort",) + cmd!(config.tool("nm"), config.elf_string(), "-S", "--size-sort") .stdout_path("target/syms.txt") .run()?; @@ -331,17 +320,18 @@ fn main() -> AnyResult<()> { env::set_var("DEFMT_LOG", "card_io_fw=debug,info"); match cli.subcommand { - Subcommands::Build { hw, variant: opt } => build(hw.unwrap_or_default(), opt, false), + Subcommands::Build { hw } => build(BuildConfig::from(hw), false), Subcommands::Test => test(), Subcommands::Asm { hw } => { - build(hw.unwrap_or_default(), None, true)?; - asm() + let config = BuildConfig::from(hw); + build(config, true)?; + asm(config) } - Subcommands::Monitor { variant } => monitor(variant.unwrap_or(MonitorVariant::Debug)), - Subcommands::Run { hw, release } => run(hw.unwrap_or_default(), release), - Subcommands::Check { hw } => checks(hw.unwrap_or_default()), - Subcommands::Doc { open, hw } => docs(open, hw.unwrap_or_default()), - Subcommands::ExtraCheck { hw } => extra_checks(hw.unwrap_or_default()), + Subcommands::Monitor { hw, profile } => monitor(BuildConfig::new(hw, profile)), + Subcommands::Run { hw, profile } => run(BuildConfig::new(hw, profile)), + Subcommands::Check { hw } => checks(BuildConfig::from(hw)), + Subcommands::Doc { hw, open } => docs(BuildConfig::from(hw), open), + Subcommands::ExtraCheck { hw } => extra_checks(BuildConfig::from(hw)), Subcommands::Example { package, name, @@ -349,3 +339,90 @@ fn main() -> AnyResult<()> { } => example(package, name, watch), } } + +#[derive(Clone, Copy, Parser, Debug)] +enum SocConfig { + S3, + C6, +} + +impl SocConfig { + fn chip(self) -> &'static str { + match self { + SocConfig::S3 => "esp32s3", + SocConfig::C6 => "esp32c6", + } + } + + fn triple(self) -> &'static str { + match self { + SocConfig::S3 => "xtensa-esp32s3-none", + SocConfig::C6 => "riscv32imac-unknown-none", + } + } + + fn target(self) -> String { + format!("{}-elf", self.triple()) + } + + fn target_folder(self, profile: Profile) -> PathBuf { + PathBuf::from("./target") + .join(self.target()) + .join(profile.as_str()) + } +} + +#[derive(Clone, Copy)] +struct BuildConfig { + version: HardwareVersion, + profile: Profile, + soc: SocConfig, +} + +impl From> for BuildConfig { + fn from(hw: Option) -> Self { + Self::new(hw, None) + } +} + +impl BuildConfig { + fn new(hw: Option, variant: Option) -> BuildConfig { + let hw = hw.unwrap_or_default(); + Self { + version: hw, + soc: hw.soc(), + profile: variant.unwrap_or(Profile::Debug), + } + } + + fn target_folder(&self) -> PathBuf { + self.soc.target_folder(self.profile) + } + + fn elf(&self) -> PathBuf { + self.target_folder().join("card_io_fw") + } + + fn elf_string(&self) -> String { + self.elf().display().to_string() + } + + fn tool(&self, tool: &str) -> String { + format!("xtensa-esp32s3-elf-{tool}") + } + + fn build_flags(self) -> Vec { + let mut flags = vec![ + format!("--target={}", self.soc.target()), + format!("--features={}", self.version.feature()), + String::from("-Zbuild-std=core,alloc"), + ]; + + if self.profile == Profile::Release { + flags.push(String::from("--release")); + flags.push(String::from("-Zbuild-std-features=panic_immediate_abort")); + } + + flags + } +}