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[dkehlet]

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[dkehlet]

Two questions came in today:
1. The pair of input & output ports data_in/data_out and data_in_f/data_out_f seems to have same functionality. Can I merge these signals, only expose one interface at AIB 2.1 top…
I’m sure you know the AIB spec defines these as separate MAC/PHY signals. This is how the open source model at
https://github.com/chipsalliance/aib-phy-hardware/tree/master/v2.0/rev1/rtl
implements them. We separated them because of our timing closure experience. Since they come from different sources (register or FIFO) you will have to mux between data_out and data_out_f depending on the application’s use case of register or FIFO. And, this is at the boundary of the PHY which may be timing critical to get to the application. So we left that choice to the application, since in our experience register mode or FIFO mode was fixed at application design time. The application only connects to data_out or data_out_f, not both.

If you feel strongly otherwise, I don’t think it would be a spec violation to implement your Verilog code with a common port. However, it is likely to cause confusion with users, in addition to timing closure difficulty.

2. AIB 2.1 are using 2 clock source m_wr_clk and m_rd_clk. Can I assume that the frequency of 2 clock sources are always identical for example m_wr_clk is 2 GHz, m_rd_clk must be 2GHz ?
No, for m_wr_clk (data_in_f, goes to TX pins) and m_rd_clk (data_out_f, comes from Rx pins) you must allow these to be independent clock sources. A simple example is Ethernet. Outgoing Ethernet data (m_wr_clk) is clocked from a local source. Incoming Ethernet data may be at the frequency of the input line rate, set by the far-away Ethernet source. In this Ethernet example you would have to use m_fs_fwd_clk to create m_rd_clk.

And I shouldn’t never see any case that the frequency of m_wr_clk is different with m_rd_clk, for example m_wr_clk is 2 GHz but m_rd_clk is only 1GHz…
Regarding the quarter rate, half rate or full rate settings, they must be the same between data_in_f and data_out_f. From the spec 2.2.2.1:
The AIB Adapter shall assume that the m_wr_clk and m_rd_clk inputs correspond in frequency to the PC’s full rate, half rate or quarter rate setting. For example, a 4Gbps AIB interface has m_fs_fwd_clk at 2GHz. A quarter rate setting for the AIB Adapter PC has m_rd_clk at 500MHz, but still at 0PPM difference from m_fs_fwd_clk