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Pull requests: chipsalliance/firrtl
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Fix optimization of register with reset but invalid connection (backport #2520)
Backport
Automated backport, please consider for minor release
bp-conflict
#2521
opened Apr 22, 2022 by
mergify
bot
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Fold VerilogModulusCleanup into LegalizeVerilog (backport #2485)
Backport
Automated backport, please consider for minor release
bp-conflict
#2486
opened Mar 2, 2022 by
mergify
bot
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Update scalatest to 3.2.11
Please Merge
Accepted PRs that are ready to be merged. Useful when waiting on CI.
#2470
opened Jan 24, 2022 by
scala-steward
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Support parsing missing keywords as ids (backport #2381)
Backport
Automated backport, please consider for minor release
#2383
opened Oct 9, 2021 by
mergify
bot
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Support parsing missing keywords as ids (backport #2381)
Backport
Automated backport, please consider for minor release
bp-conflict
#2382
opened Oct 9, 2021 by
mergify
bot
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Relax spec on 0-bit mux select, use SFC behavior (backport #2285)
Backport
Automated backport, please consider for minor release
#2288
opened Jul 6, 2021 by
mergify
bot
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[spec] Explicit widths may be non-negative, not just positive (backport #2277)
Backport
Automated backport, please consider for minor release
bp-conflict
#2279
opened Jun 21, 2021 by
mergify
bot
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