Getting the litex+picorv32+litedram test integrated and working

[gatecat]

I've currently been investigating what's needed to get litedram working with fpga-interchange, now that basic differential IO are working.

My current progress is at https://github.com/gatecat/litex-fpga-interchange, which shows some promise in terms of calibration before crashing (see the detailed issues below):

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 BIOS built on Jul 26 2021 19:09:45
 BIOS CRC passed (be68b3b4)

 Migen git sha1: --------
 LiteX git sha1: 751e9969

--=============== SoC ==================--
CPU:		PicoRV32 @ 60MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		262144KiB 16-bit @ 480MT/s (CL-6 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write latency calibration:
m0:0 m1:0 
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |00000000000000000000000000000000| delays: -
  m0, b02: |00000000000000000000000000000000| delays: -
  m0, b03: |00000000000000000000000000000000| delays: -
  m0, b04: |00000000000000000000000000000000| delays: -
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00011111111111111110000000000000| delays: 11+-08
  m0, b07: |00000000000000000000000000000111| delays: 30+-01
  best: m0, b06 delays: 11+-08
  m1, b00: |00000000000000000000000000000000| delays: -
  m1, b01: |00000000000000000000000000000000| delays: -
  m1, b02: |00000000000000000000000000000000| delays: -
  m1, b03: |00000000000000000000000000000000| delays: -
  m1, b04: |00000000000000000000000000000000| delays: -m
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |00011111111111111111000000000000| delays: 11+-08
  m1, b07: |00000000000000000000000000000001| delays: 31+-00
  best: m1, b06 delays: 11+-08
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...

Significant issues:

• carrys are disabled, because having them enabled causes placement to fail. This is probably because we are missing the "use a latch to route through carries" trick when both CO and O are needed at the same time, although I haven't investigated in detail yet. Either this needs to be implemented or worked around post-synthesis
• the above causes the design to fail timing massively, but we can't lower frequency any further or litedram stops working reliably (even in Vivado). this is probably why it crashes at that point, it's lucky it even gets that far
• the lack of default cell connections in RapidWright (Add missing cell pin default connections Xilinx/RapidWright#199) mean we have a nextpnr Python script to wire these up: https://github.com/gatecat/litex-fpga-interchange/blob/13f5f723e74eb051a444d8740ee7232ccc536ec8/default_ports.py
• we have to patch the JSON to convert A[15] of RAMB36E1s from GND to VCC, a transform Vivado does but we don't otherwise mirror: https://github.com/gatecat/litex-fpga-interchange/blob/main/fixup_bram.py
• missing OBUFDS support ([Interchange] XC7 OBUFDS misses a PIP begin enabled YosysHQ/nextpnr#773) means we have to convert these to OBUFTDS for PnR purposes: https://github.com/gatecat/litex-fpga-interchange/blob/13f5f723e74eb051a444d8740ee7232ccc536ec8/fixup_obufds.py
• the IDELAYCTRL has to be manually placed: https://github.com/gatecat/litex-fpga-interchange/blob/13f5f723e74eb051a444d8740ee7232ccc536ec8/run_yosys.tcl#L11-L12
• the FD cell that LiteX uses is missing from Yosys: https://github.com/gatecat/litex-fpga-interchange/blob/13f5f723e74eb051a444d8740ee7232ccc536ec8/remap.v#L13-L19

Although this looks like a long list, I think we are actually impressively close to the goal here! Hopefully most of these issues don't prove to be to much work and then we can get this from proof-of-concept to properly integrated.