PLL test (off-chip feedback) fails the dcp_diff_fasm test

[mkurc-ant]

The PLL test (from #68) that utilizes external feedback fails the FASM difference test on some routing features. There are no difference in features related to the PLL itself (with chipsalliance/python-fpga-interchange#119).

--- fpga-interchange-tests/build/tests/features/pll/basys3/pll_ext_fb.bit.fasm        2021-09-06 09:50:10.530591329 +0200
+++ fpga-interchange-tests/build/tests/features/pll/basys3/pll_ext_fb.dcp.bit.fasm    2021-09-06 09:49:54.874841415 +0200
@@ -1059,6 +1059,10 @@
 CLK_HROW_TOP_R_X60Y78.CLK_HROW_CK_MUX_OUT_L11.CLK_HROW_R_CK_GCLK0
 CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK0_ACTIVE

+CMT_TOP_R_LOWER_B_X8Y9.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB3
+CMT_TOP_R_LOWER_B_X8Y9.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB3
+CMT_TOP_R_LOWER_B_X8Y9.MMCM_CLK_FREQ_BB_NS0_ACTIVE
+
 CMT_TOP_R_UPPER_T_X8Y44.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0
 CMT_TOP_R_UPPER_T_X8Y44.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1
 CMT_TOP_R_UPPER_T_X8Y44.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2
@@ -1099,9 +1103,9 @@
 CMT_TOP_R_UPPER_T_X8Y44.PLLE2_ADV.LKTABLE[39:0] = 40'b1111111111100111000111111010010000000001
 CMT_TOP_R_UPPER_T_X8Y44.PLLE2_ADV.LOCKREG3_RESERVED[0]
 CMT_TOP_R_UPPER_T_X8Y44.PLLE2_ADV.TABLE[9:0] = 10'b1111010100
+CMT_TOP_R_UPPER_T_X8Y44.PLL_CLK_FREQ_BB0_NS_ACTIVE

 HCLK_CMT_X8Y26.HCLK_CMT_CCIO0_ACTIVE
-HCLK_CMT_X8Y26.HCLK_CMT_CCIO0_USED
 HCLK_CMT_X8Y26.HCLK_CMT_CK_BUFHCLK0_USED
 HCLK_CMT_X8Y26.HCLK_CMT_CK_BUFHCLK10_USED
 HCLK_CMT_X8Y26.HCLK_CMT_CK_BUFHCLK11_USED

[acomodi]

This probably requires an addition to the extra PIP features: https://github.com/SymbiFlow/python-fpga-interchange/blob/5004f1c19e9f0bd9f87447502770b65a367878c7/fpga_interchange/fasm_generators/xc7/xc7.py#L1451-L1584