From 6b90dc289489c146b80f31a0841bd1dfaef2178c Mon Sep 17 00:00:00 2001 From: chengguanghui Date: Mon, 6 Jan 2025 18:18:54 +0800 Subject: [PATCH] fix `hartReset` in DM --- src/main/scala/devices/debug/Debug.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index efaf345fb5f..95982b84690 100755 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -660,7 +660,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { - hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) + hartResetNxt(component) := DMCONTROLNext.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } }