Resume groups

[markuslauterbach]

Hi all,

we are currently experimenting with various Rocket Chip multicore setups, and would like to integrate our Rocket Chip design into a heterogeneous FPGA system which also includes cores from other architectures. For such a system, cross-triggering (for halt/resume) between all cores (RISC-V cores and other 3rd party cores) would be important. To enable such heterogeneous cross-triggering, the RISC-V debug spec v1.0 defines "halt groups", "resume groups" and "external triggers".

The Rocket Chip configurator does already support halt groups (nHaltGroups) and external triggers (nExtTriggers), but it seems it does not support resume groups yet. I assume one possible reason for this could be that resume groups are not necessary for homogeneous "RISC-V only" systems, because instead of using resume groups you can simply select all RISC-V cores in the debug module and then make a resume request. However, this does of course not work if you also want to resume cores of other architectures as well, so in that case you would need resume groups.

The discussion in #3024 does mention that resume groups were not implemented, but I could not find a reason or plans for the future.

Is there any plan to add support for resume groups in the future?

Thanks!

Best regards, Markus

[ZenithalHourlyRate]

Is there any plan to add support for resume groups in the future?

No.

Currently we are busy with cleaning up legacy code (e.g. Chisel._), repo splitting (#3037) and adding support of ISA extensions, I'm afraid there is no timeline for this feature.

We welcome contributions. If you implement such feature we are happy to see it upstreamed.

[markuslauterbach]

Thanks for the feedback, that is good to know. We may give it a try, although I am afraid we do not have much experience in that area (our expertise lies more on the debug tool side). If we happen to come up with anything useful, we will let you know.