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computer-hardware.bigb
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= Computer hardware
{wiki}
= Moore's law
{c}
{parent=Computer hardware}
{wiki}
Born: 1965
Died: 2010+-ish
= Semiconductor device fabrication
{parent=Computer hardware}
{wiki}
= Semiconductor physical implementation
{synonym}
https://en.wikipedia.org/wiki/Semiconductor_device
This is the lowest level of abstraction computer, at which the basic gates and power are described.
At this level, you are basically thinking about the 3D layered structure of a chip, and how to make machines that will allow you to create better, usually smaller, gates.
= Semiconductor research institute
{parent=Semiconductor device fabrication}
{tag=Research institute}
= IMEC
{c}
{parent=Semiconductor research institute}
{title2=1984-}
{title2=Belgium}
{wiki}
\Video[https://www.youtube.com/watch?v=RO7E7RX0L2Y]
{title=imec: The Semiconductor Watering Hole by <Asianometry> (2022)}
{description=A key thing they do is have a small prototype fab that brings in-development equipment from different vendors together to make sure the are working well together. Cool.}
= Computer research institute
{parent=Semiconductor research institute}
= Xerox PARC
{c}
{parent=Computer research institute}
{wiki=PARC_(company)}
What a legendary place.
= Semiconductor equipment maker
{parent=Semiconductor device fabrication}
= Company that makes semiconductor production equipment
{synonym}
As mentioned at https://youtu.be/16BzIG0lrEs?t=397 from <video Applied Materials by Asianometry (2021)}>, originally the companies <fabs> would make their own equipment. But eventually things got so complicated that it became worth it for separate companies to focus on equipment, which then then sell to the fabs.
= ASML Holding
{c}
{parent=Semiconductor equipment maker}
{title2=1984-}
{wiki}
= ASML
{c}
{synonym}
As of 2020 leading makers of the most important <fab> <photolithography> equipment.
\Video[https://www.youtube.com/watch?v=CFsn1CUyXWs]
{title=ASML: TSMC's Critical Supplier by <Asianometry> (2021)}
\Video[https://www.youtube.com/watch?v=SB8qIO6Ti_M]
{title=How ASML Won Lithography by <Asianometry> (2021)}
{description=
First there were dominant Elmer and Geophysics Corporation of America dominating the market.
Then a Japanese government project managed to make Nikon and Canon Inc. catch up, and in 1989, when <Ciro Santilli> was born, they had 70% of the market.
https://youtu.be/SB8qIO6Ti_M?t=240 In 1995, ASML had reached 25% market share. Then it managed the folloging faster than the others:
* TwinScan, reached 50% market share in 2002
* Immersion litography
* EUV. There was a big split between EUV vs particle beams, and ASML bet on EUV and EUV won.
* https://youtu.be/SB8qIO6Ti_M?t=459 they have an insane number of <software engineers> working on software for the machine, which is insanely complex. They are big on <UML>.
* https://youtu.be/SB8qIO6Ti_M?t=634 they use <ZEISS> optics, don't develop their own. More precisely, the majority owned subsidiary <Carl Zeiss SMT>.
* https://youtu.be/SB8qIO6Ti_M?t=703 <IMEC> collaborations worked well. Notably the <ASML>/<Philips>/<ZEISS> trinity
}
* https://www.youtube.com/watch?v=XLNsYecX_2Q ASML: Chip making goes vacuum with EUV (2009) Self promotional video, some good shots of their buildings.
= ASM International
{c}
{parent=ASML Holding}
{title2=1964}
{wiki}
Parent/predecessor of <ASML>.
= Applied Materials
{c}
{parent=Semiconductor equipment maker}
{title2=1967-}
{wiki}
\Video[https://www.youtube.com/watch?v=16BzIG0lrEs]
{title=<Applied Materials> by <Asianometry> (2021)}
{description=They are <chemical vapor deposition> fanatics basically.}
= Power, performance and area
{parent=Semiconductor device fabrication}
{title2=PPA}
https://en.wikichip.org/wiki/power-performance-area
This is the mantra of the <semiconductor industry>:
* power and area are the main limiting factors of chips, i.e., your budget:
* chip area is ultra expensive because there are sporadic errors in the fabrication process, and each error in any part of the chip can potentially break the entire chip. Although there are
The percentage of working chips is called the yield.
In some cases however, e.g. if the error only affects single CPU of a multi-core CPU, then they actually deactivate the broken CPU after testing, and sell the worse CPU cheaper with a clear branding of that: this is called binning https://www.tomshardware.com/uk/reviews/glossary-binning-definition,5892.html
* power is a major semiconductor limit as of 2010's and onwards. If everything turns on at once, the chip would burn. Designs have to account for that.
* performance is the goal.
Conceptually, this is basically a set of algorithms that you want your hardware to solve, each one with a respective weight of importance.
Serial performance is fundamentally limited by the <critical path>[longest path] that electrons have to travel in a given clock cycle.
The way to work around it is to create pipelines, splitting up single operations into multiple smaller operations, and storing intermediate results in memories.
= Wafer
{disambiguate=electronics}
{parent=Semiconductor device fabrication}
= Wafer
{synonym}
= Czochralski method
{c}
{parent=Wafer (electronics)}
{wiki}
= Semiconductor fabrication plant
{parent=Semiconductor device fabrication}
{title2=foundry}
{wiki}
= Fab
{synonym}
{title2}
They put a lot of expensive equipment together, much of it <company that makes semiconductor production equipment>[made by other companies], and they make the entire chip for companies ordering them.
= Company with a semiconductor fabrication plant
{parent=Semiconductor fabrication plant}
A list of <semiconductor fabrication plant>[fabs] can be seen at: https://en.wikipedia.org/wiki/List_of_semiconductor_fabrication_plants and basically summarizes all the companies that have fabs.
= Fairchild Semiconductor
{c}
{parent=Company with a semiconductor fabrication plant}
{wiki}
= Fairchild
{c}
{synonym}
Some nice insights at: <Robert Noyce: The Man Behind the Microchip by Leslie Berlin (2006)>.
= GlobalFoundries
{c}
{parent=Company with a semiconductor fabrication plant}
{title2=2009}
{title2=AMD spinout}
{wiki}
<AMD> just gave up this risky part of the business amidst the <fabless> boom. Sound like a wise move. They then fell more and more away from the state of the art, and moved into more niche areas.
= Infineon Technologies
{parent=Company with a semiconductor fabrication plant}
{tag=Siemens spinoff}
{title2=1999}
{wiki}
= Infineon
{c}
{synonym}
= SMIC
{c}
{parent=Company with a semiconductor fabrication plant}
{tag=Chinese semiconductor industry}
{title2=Chinese TSMC}
{wiki}
\Video[https://www.youtube.com/watch?v=aL_kzMlqgt4]
{title=SMIC, Explained by <Asianometry> (2021)}
= TSMC
{c}
{parent=Company with a semiconductor fabrication plant}
{wiki}
One of the companies that has fabs, which buys machines from companies such as ASML and puts them together in so called "silicon fabs" to make the chips
As the quintessential <fabless> <fab>, there is on thing TSMC can never ever do: sell their own design! It must forever remain a <fab>-only company, that will never compete with its customers. This is highlighted e.g. at https://youtu.be/TRZqE6H-dww?t=936 from <video How Nvidia Won Graphics Cards by Asianometry (2021)>.
\Video[https://www.youtube.com/watch?v=9fVrWDdll0g]
{title=How <Taiwan> Created TSMC by <Asianometry> (2020)}
{description=Some points:
* UCM failed because it focused too much on the internal market, and was shielded from external competition, so it didn't become world leading
* one of TSMC's great advances was the <fabless> business model approach.
* they managed to do large technology transfers from the West to kickstart things off
* one of their main victories was investing early in <CMOS>, before it became huge, and winning that market
}
= Semiconductor fabrication step
{parent=Semiconductor fabrication plant}
{wiki}
= Chemical vapor deposition
{parent=Semiconductor fabrication step}
{wiki}
= Photolithography
{parent=Semiconductor fabrication step}
{wiki}
= Extreme ultraviolet lithography
{parent=Photolithography}
{wiki}
= EUV
{c}
{synonym}
{title2}
= Photomask
{parent=Photolithography}
{wiki}
= Standard cell library
{parent=Semiconductor device fabrication}
{wiki}
Basically what <register transfer level> compiles to in order to achieve a real chip implementation.
After this is done, the final step is <place and route>.
They can be designed by third parties besides the <semiconductor fabrication plants>. E.g. <Arm Ltd.> markets its <Arm Artisan>[Artisan] Standard Cell Libraries as mentioned e.g. at: https://web.archive.org/web/20211007050341/https://developer.arm.com/ip-products/physical-ip/logic This came from a 2004 acquisition: https://www.eetimes.com/arm-to-acquire-artisan-components-for-913-million/[], <if a product of a big company has a catchy name it came from an acquisition>[obviously].
The standard cell library is typically composed of a bunch of versions of somewhat simple gates, e.g.:
* AND with 2 inputs
* AND with 3 inputs
* AND with 4 inputs
* OR with 2 inputs
* OR with 3 inputs
and so on.
Each of those gates has to be designed by hand as a <3D> structure that can be produced in a given <fab>.
Simulations are then carried out, and the electric properties of those structures are characterized in a standard way as a bunch of tables of numbers that specify things like:
* how long it takes for electrons to pass through
* how much heat it produces
Those are then used in <power, performance and area> estimates.
= Open source standard cell library
{parent=Standard cell library}
Open source ones:
* https://www.quora.com/Are-there-good-open-source-standard-cell-libraries-to-learn-IC-synthesis-with-EDA-tools/answer/Ciro-Santilli Are there good open source standard cell libraries to learn IC synthesis with EDA tools?
= Electronic design automation
{parent=Semiconductor device fabrication}
{title2=EDA}
{wiki}
= EDA tool
{c}
{synonym}
A set of software programs that <compile> high level <register transfer level> languages such as <Verilog> into something that a <fab> can actually produce. One is reminded of a <compiler toolchain> but on a lower level.
The most important steps of that include:
* <logic synthesis>: mapping the <Verilog> to a <standard cell library>
* <place and route>: mapping the synthesis output into the 2D surface of the chip
= Electronic design automation phase
{parent=Electronic design automation}
= Logic synthesis
{parent=Electronic design automation phase}
{wiki}
Step of <electronic design automation> that maps the <register transfer level> input (e.g. <Verilog>) to a <standard cell library>.
The output of this step is another <Verilog> file, but one that exclusively uses interlinked cell library components.
= Place and route
{parent=Electronic design automation phase}
{wiki}
Given a bunch of interlinked <standard cell library> elements from the <logic synthesis> step, actually decide where exactly they are going to go on 2D (stacked 2D) <integrated circuit> surface.
Sample output format of place and route would be <GDSII>.
= Integrated circuit layout
{parent=Place and route}
{wiki}
= GDSII
{c}
{parent=Integrated circuit layout}
{wiki}
\Image[https://upload.wikimedia.org/wikipedia/commons/a/aa/Silicon_chip_3d.png]
{title=3D rendering of a GDSII file.}
= EDA company
{c}
{parent=Electronic design automation}
{tag=Technology company}
= EDA vendor
{c}
{synonym}
The main ones as of 2020 are:
* <Mentor Graphics>, which was bought by <Siemens> in 2017
* <Cadence Design Systems>
* <Synopsys>
= Cadence Design Systems
{c}
{parent=EDA company}
{wiki}
= Mentor Graphics
{c}
{parent=EDA company}
{wiki}
= Synopsys
{c}
{parent=EDA company}
{wiki}
= Open source EDA tool
{parent=Electronic design automation}
= qflow
{parent=Open source EDA tool}
Cool looking <open source EDA tool>[open source EDA toolchain]:
* http://opencircuitdesign.com/qflow/
* https://github.com/RTimothyEdwards/qflow
They apparently even produced a real working small <RISC-V> chip with the flow, not bad.
= Semiconductor process node
{parent=Semiconductor device fabrication}
= Semiconductor device fabrication bibilography
{parent=Semiconductor device fabrication}
= Asianometry
{c}
{parent=Semiconductor device fabrication bibilography}
{tag=The best technology YouTube channels}
https://www.youtube.com/channel/UC1LpsuAUaKoMzzJSEt5WImw
Very good channel to learn some basics of <semiconductor device fabrication>!
Focuses mostly on the <semiconductor industry>.
https://youtu.be/aL_kzMlqgt4?t=661 from <video SMIC, Explained by Asianometry (2021)> from mentions he is of Chinese ascent, ancestors from Ningbo. Earlier in the same video he mentions he worked on some startups. He doesn't appear to speak perfect Mandarin Chinese anymore though based on pronounciation of Chinese names.
https://asianometry.substack.com/ gives an abbreviated name "Jon Y".
\Video[https://www.youtube.com/watch?v=X9Zm3K05Utk]
{title=Reflecting on Asianometry in 2022 by <Asianometry> (2022)}
{description=Mentions his insane work schedule: 4 hours research in the morning, then day job, then editing and uploading until midnight. Appears to be based in <Taipei>. Two videos a week. So even at the current 400k subs, he still can't make a living.}
= Integrated circuit
{parent=Computer hardware}
{title2=IC}
{wiki}
It is quite amazing to read through books such as <The Supermen: The Story of Seymour Cray by Charles J. Murray (1997)>, as it makes you notice that earlier <CPUs> (all before the 70's) were not made with <integrated circuits>, but rather smaller pieces glued up on <PCBs>! E.g. the <arithmetic logic unit> was actually a discrete component at one point.
The reason for this can also be understood quite clearly by reading books such as <Robert Noyce: The Man Behind the Microchip by Leslie Berlin (2006)>. The first <integrated circuits> were just too small for this. It was initially unimaginable that a CPU would fit in a single chip! Even just having a very small number of components on a chip was already revolutionary and enough to kick-start the industry. Just imagine how much money any level of integration saved in those early days for production, e.g. as opposed to manually soldering <point-to-point constructions>. Also the reliability, size an weight gains were amazing. In particular for military and spacial applications originally.
\Video[https://www.youtube.com/watch?v=z47Gv2cdFtA]
{title=A briefing on semiconductors by <Fairchild Semiconductor> (1967)}
{description=
Uploaded by the <Computer History Museum>. <There is value in tutorials written by early pioneers of the field>, this is pure <gold>.
Shows:
* <photomasks>
* <silicon> <ingots> and <wafer (electronics)> processing
}
= Interconnect
{parent=Integrated circuit}
{disambiguate=integrated_circuits}
= Chip interconnect
{synonym}
{title2}
= Application-specific integrated circuit
{parent=Integrated circuit}
{wiki}
= ASIC
{c}
{synonym}
{title2}
= Hardware acceleration
{synonym}
{title2}
= Hardware accelerator
{synonym}
= System on a chip
{parent=Integrated circuit}
{wiki}
= SoC
{c}
{synonym}
{title2}
= Register transfer level
{parent=Computer hardware}
{title2=RTL}
{wiki}
Register transfer level is the abstraction level at which computer chips are mostly designed.
The only two truly relevant RTL languages as of 2020 are: <Verilog> and <VHDL>. Everything else compiles to those, because that's all that <EDA vendors> support.
Much like a <C (language)> compiler abstracts away the <CPU> assembly to:
* increase portability across ISAs
* do optimizations that programmers can't feasibly do without going crazy
Compilers for RTL languages such as Verilog and <VHDL> abstract away the details of the specific <semiconductor physical implementation>[semiconductor technology] used for those exact same reasons.
The compilers essentially compile the RTL languages into a <standard cell library>.
Examples of companies that work at this level include:
* <Intel>. Intel also has <semiconductor fabrication plants> however.
* <Arm Company> which does not have <fabs>, and is therefore called a "<fabless>" company.
= High-level synthesis
{parent=Register transfer level}
{wiki}
= Fabless manufacturing
{parent=Register transfer level}
{wiki}
= Fabless
{synonym}
In the past, most computer designers would have their own <fabs>.
But once designs started getting very complicated, it started to make sense to separate concerns between designers and <fabs>.
What this means is that design companies would primarily write <register transfer level>, then use <electronic design automation> tools to get a final manufacturable chip, and then send that to the <fab>.
It is in this point of time that <TSMC> came along, and benefied and helped establish this trend.
The term "Fabless" could in theory refer to other areas of industry besides the <semiconductor industry>, but it is mostly used in that context.
= Fabless semiconductor company
{parent=Fabless manufacturing}
= Logic gate
{parent=Register transfer level}
{wiki}
= Truth table
{parent=Logic gate}
{wiki}
= Verilog
{c}
{parent=Register transfer level}
{wiki}
Examples under \a[verilog], more details at <Verilator>.
= Value change dump
{parent=Verilog}
{title2=VCD}
{wiki}
= Verilator
{c}
{parent=Verilog}
{wiki}
<Verilog> simulator that <transpiles> to <C++>.
One very good thing about this is that it makes it easy to create test cases directly in C++. You just supply inputs and clock the simulation directly in a C++ loop, then read outputs and assert them with `assert()`. And you can inspect variables by printing them or with GDB. This is infinitely more convenient than doing these IO-type tasks in <Verilog> itself.
Some simulation examples under \a[verilog].
First install <Verilator>. On <Ubuntu>:
``
sudo apt install verilator
``
Tested on Verilator 4.038, <Ubuntu 22.04>.
Run all examples, which have assertions in them:
``
cd verilator
make run
``
File structure is for example:
* \a[verilog/counter.v]: <Verilog> file
* \a[verilog/counter.cpp]: <C++> loop which clocks the design and runs tests with assertions on the outputs
* \a[verilog/counter.params]: <GCC> compilation flags for this example
* \a[verilog/counter_tb.v]: <Verilog> version of the <C++> test. Not used by Verilator. Verilator can't actually run out `_tb` files, because they do in Verilog IO things that we do better from <C++> in Verilator, so Verilator didn't bother implementing them. This is a good thing.
Example list:
* \a[verilog/negator.v], \a[verilog/negator.cpp]: the simplest non-identity combinatorial circuit!
* \a[verilog/counter.v], \a[verilog/counter.cpp]: sequential hello world. Synchronous active high reset with active high enable signal. Adapted from: http://www.asic-world.com/verilog/first1.html
* \a[verilog/subleq.v], \a[verilog/subleq.cpp]: subleq <one instruction set computer> with separated instruction and data RAMs
= Verilator interactive example
{c}
{parent=Verilator}
The example under \a[verilog/interactive] showcases how to create a simple interactive visual <verilog> example using <verilator> and <sdl>.
\Image[https://raw.githubusercontent.com/cirosantilli/media/master/verilog-interactive.gif]
You could e.g. expand such an example to create a simple (or complex) <video game> for example if you were insane enough. But please don't waste your time doing that, <backward design>[Ciro Santilli begs you].
The example is also described at: https://stackoverflow.com/questions/38108243/is-it-possible-to-do-interactive-user-input-and-output-simulation-in-vhdl-or-ver/38174654#38174654
Usage: install dependencies:
``
sudo apt install libsdl2-dev verilator
``
then run as either:
``
make run RUN=and2
make run RUN=move
``
Tested on Verilator 4.038, Ubuntu 22.04.
File overview:
* and2
* \a[verilog/interactive/and2.cpp]
* \a[verilog/interactive/and2.v]
* move
* \a[verilog/interactive/move.cpp]
* \a[verilog/interactive/move.v]
* \a[verilog/interactive/display.cpp]
In those examples, the more interesting application specific logic is delegated to Verilog (e.g.: move game character on map), while boring timing and display matters can be handled by SDL and C++.
= VHDL
{c}
{parent=Register transfer level}
{wiki}
Examples under \a[vhdl], more details at: <GHDL>.
= GHDL
{c}
{parent=VHDL}
https://github.com/ghdl/ghdl
Examples under \a[vhdl].
First install <GHDL>. On <Ubuntu>:
``
sudo apt install verilator
``
Tested on Verilator 1.0.0, <Ubuntu 22.04>.
Run all examples, which have assertions in them:
``
cd vhdl
./run
``
Files:
* Examples
* Basic
* \a[vhdl/hello_world_tb.vhdl]: hello world
* \a[vhdl/min_tb.vhdl]: min
* \a[vhdl/assert_tb.vhdl]: assert
* Lexer
* \a[vhdl/comments_tb.vhdl]: comments
* \a[vhdl/case_insensitive_tb.vhdl]: case insensitive
* \a[vhdl/whitespace_tb.vhdl]: whitespace
* \a[vhdl/literals_tb.vhdl]: literals
* Flow control
* \a[vhdl/procedure_tb.vhdl]: procedure
* \a[vhdl/function_tb.vhdl]: function
* \a[vhdl/operators_tb.vhdl]: operators
* Types
* \a[vhdl/integer_types_tb.vhdl]: integer types
* \a[vhdl/array_tb.vhdl]: array
* \a[vhdl/record_tb.vhdl.bak]: record. TODO fails with "GHDL Bug occurred" on GHDL 1.0.0
* \a[vhdl/generic_tb.vhdl]: generic
* \a[vhdl/package_test_tb.vhdl]: Packages
* \a[vhdl/standard_package_tb.vhdl]: standard package
* textio
* \a[vhdl/write_tb.vhdl]: write
* \a[vhdl/read_tb.vhdl]: read
* \a[vhdl/std_logic_tb.vhdl]: std_logic
* \a[vhdl/stop_delta_tb.vhdl]: `--stop-delta`
* Applications
* Combinatoric
* \a[vhdl/adder.vhdl]: adder
* \a[vhdl/sqrt8_tb.vhdl]: sqrt8
* Sequential
* \a[vhdl/clock_tb.vhdl]: clock
* \a[vhdl/counter.vhdl]: counter
* Helpers
* \a[vhdl/template_tb.vhdl]: template
= Microarchitecture
{parent=Computer hardware}
{tag=Computer architecture}
{wiki}
= Computer hardware component type
{parent=Computer hardware}
= Processor
{disambiguate=computing}
{parent=Computer hardware component type}
= Instruction set architecture
{parent=Processor (computing)}
{wiki}
= ISA
{c}
{synonym}
{title2}
The main interface between the <central processing unit> and <software>.
= Assembly language
{parent=Instruction set architecture}
{wiki}
= Assembly
{synonym}
A human readable way to write instructions for an <instruction set architecture>.
One of the topics covered in <Ciro Santilli>'s <Linux Kernel Module Cheat>.
= Assembler
{disambiguate=computing}
{parent=Assembly language}
= GNU Assembler
{c}
{parent=Assembler (computing)}
{tag=gcc}
{wiki}
= GNU GAS
{c}
{synonym}
{title2}
= Calling convention
{parent=Instruction set architecture}
{wiki}
= List of instruction set architectures
{parent=Instruction set architecture}
List of <instruction set architecture>.
= One instruction set computer
{parent=List of instruction set architectures}
{title2=OISC}
{wiki}
https://stackoverflow.com/questions/3711443/minimal-instruction-set-to-solve-any-problem-with-a-computer-program/38523869#38523869
= ARM architecture family
{c}
{parent=List of instruction set architectures}
{tag=Arm (company)}
= ARM instruction set
{c}
{synonym}
= ARM
{c}
{disambiguate=ISA}
{synonym}
This <ISA> basically completely dominated the <smartphone> market of the 2010s and beyond, but it started appearing in other areas as the end of <Moore's law> made it more economical logical for large companies to start developing their own semiconductor, e.g. <Google custom silicon>, <Amazon custom silicon>.
It is exciting to see ARM entering the <server>, <desktop> and <supercomputer> market circa 2020, beyond its dominant mobile position and roots.
<Ciro Santilli> likes <Ciro Santilli's self perceived creative personality>[to see the underdogs rise], and bite off dominant ones.
The excitement also applies to <RISC-V> possibly over ARM mobile market one day conversely however.
Basically, as long as were a huge company seeking to develop a <CPU> and able to control your own ecosystem independently of <Windows>' desktop domination (held by the need for backward compatibility with a billion end user programs), ARM would be a possibility on your mind.
* in 2020, the Fugaku supercomputer, which uses an ARM-based <Fujitsu> designed chip, because the number 1 fastest supercomputer in <TOP500>: https://www.top500.org/lists/top500/2021/11/
It was later beaten by another <x86> supercomputer https://www.top500.org/lists/top500/2022/06/[], but the message was clearly heard.
* 2012 https://hackaday.com/2012/07/09/pedal-powered-32-core-arm-linux-server/ pedal-powered 32-core Arm Linux server. A <publicity stunt>, but still, cool.
* <AWS Graviton>
= PowerPC
{c}
{parent=List of instruction set architectures}
{wiki}
= RISC-V
{c}
{parent=List of instruction set architectures}
{wiki}
The leading no-royalties options as of 2020.
<China> has been a major <RISC-V> potential user in the late 2010s, since the country is trying to increase its <semiconductor industry> independence, especially given economic sanctions imposed by the <USA>.
E.g. a result of this, the <RISC-V Foundation> moved its legal headquarters to <Switzerland> in 2019 to try and overcome some of the sanctions.
= RISC-V International
{c}
{parent=RISC-V}
= RISC-V Foundation
{c}
{synonym}
{title2}
= SiFive
{c}
{parent=RISC-V}
{wiki}
Leading <RISC-V> consultants as of 2020, they are basically trying to become the <Red Hat> of the <semiconductor industry>.
= RISC-V timer
{parent=RISC-V}
{tag=QEMU}
= riscv/timer.S
{parent=RISC-V timer}
{file}
TODO: the interrupt is firing only once:
* https://www.reddit.com/r/RISCV/comments/ov4vhh/timer_interrupt/
Adapted from: https://danielmangum.com/posts/risc-v-bytes-timer-interrupts/
Tested on <Ubuntu 23.10>:
``
sudo apt install binutils-riscv64-unknown-elf qemu-system-misc gdb-multiarch
cd riscv
make
``
Then on shell 1:
``
qemu-system-riscv64 -machine virt -cpu rv64 -smp 1 -s -S -nographic -bios none -kernel timer.elf
``
and on shell 2:
``
gdb-multiarch timer.elf -nh -ex "target remote :1234" -ex 'display /i $pc' -ex 'break *mtrap' -ex 'display *0x2004000' -ex 'display *0x200BFF8'
``
<GDB> should break infinitel many times on `mtrap` as interrupts happen.
= RISC-V priviledged ISA
{parent=RISC-V}
= RISC-V MSTATUS register
{parent=RISC-V priviledged ISA}
= RISC-V MSTATUS.MIE field
{parent=RISC-V MSTATUS register}
= x86
{c}
{parent=List of instruction set architectures}
{wiki}
\Include[x86-paging]
= x86 custom instructions
{c}
{parent=x86}
<Intel> is known to have created customized chips for very large clients.
This is mentioned e.g. at: https://www.theregister.com/2021/03/23/google_to_build_server_socs/
\Q[Intel is known to do custom-ish cuts of Xeons for big customers.]
Those chips are then used only in large scale server deployments of those very large clients. <Google> is one of them most likely, given their penchant for <Google custom hardware>.
TODO better sources.
= Y86
{c}
{parent=List of instruction set architectures}
https://esolangs.org/wiki/Y86 mentions:
\Q[Y86 is a toy RISC CPU instruction set for education purpose.]
One specification at: http://web.cse.ohio-state.edu/~reeves.92/CSE2421sp13/PracticeProblemsY86.pdf
= Type of processor
{parent=Processor (computing)}
= Central processing unit
{parent=Type of processor}
{wiki}
= CPU
{c}
{synonym}
{title2}
= CPUs
{c}
{synonym}
= Arithmetic logic unit
{parent=Central processing unit}
{wiki}
= Microcontroller
{parent=Central processing unit}
{wiki}
As of 2020's, it is basically a cheap/slow/simple CPU used in <embedded system> applications.
= MicroPython
{parent=Microcontroller}
{tag=Python (programming language)}
{wiki}
It is interpreted. It actually implements a Python (-like ?) interpreter that can run on a microcontroller. See e.g.: <Compile MicroPython code for Micro Bit locally>.
As a result, it is both very convenient, as it does not require a C toolchain to build for, but also very slow and produces larger images.
= Microcontroller vs CPU
{parent=Microcontroller}
{wiki}
* https://electronics.stackexchange.com/questions/1092/whats-the-difference-between-a-microcontroller-and-a-microprocessor
* https://electronics.stackexchange.com/questions/227796/why-are-relatively-simpler-devices-such-as-microcontrollers-so-much-slower-than
= CPU architecture
{c}
{parent=Central processing unit}
{tag=Microarchitecture}
{wiki}
= Instruction pipelining
{parent=CPU architecture}
The first thing you must understand is the <Classic RISC pipeline> with a concrete example.
= JavaScript CPU microarchitecture simulator
{c}
{parent=Instruction pipelining}
{tag=JavaScript library}
= JavaScript CPU simulator
{synonym}
= y86.js.org
{c}
{parent=JavaScript CPU microarchitecture simulator}
{tag=Y86}
* https://y86.js.org/
* https://github.com/shuding/y86
The good:
* slick <UI>! But very hard to read characters, they're way too small.
* attempts to show state diffs with a flash. But it goes by too fast, would be better if it were more permanent
* <Reverse debugging>
The bad:
* educational <ISA>
* unclear what flags mean from UI, no explanation on hover. Likely the authors assume knowledge of the <Y86> book.
= WebRISC-V
{c}
{parent=JavaScript CPU microarchitecture simulator}
{tag=RISC-V}
https://webriscv.dii.unisi.it/
The good:
* <Reverse debugging>
* circuit diagram
The bad:
* Clunky <UI>
* circuit diagram doesn't show any state??
= Hazard
{disambiguate=computer architecture}
{parent=Instruction pipelining}
{wiki}
= Pipeline stall
{parent=Hazard (computer architecture)}
{wiki}
= Classic RISC pipeline
{parent=Instruction pipelining}
{wiki}
= Microprocessor
{parent=Central processing unit}
{wiki}
Basically a synonym for <central processing unit> nowadays: https://electronics.stackexchange.com/questions/44740/whats-the-difference-between-a-microprocessor-and-a-cpu
= Field-programmable gate array
{parent=Type of processor}
{wiki}
= FPGA
{c}
{synonym}
{title2}
= FPGAs
{c}
{synonym}
It basically replaces a bunch of discrete <digital> components with a single chip. So you don't have to wire things manually.
Particularly fundamental if you would be putting those chips up a thousand cell towers for signal processing, and ever felt the need to reprogram them! Resoldering would be fun, would it? So you just do a over the wire update of everything.
Vs a <microcontroller>: same reason why you would want to use discrete components: speed. Especially when you want to do a bunch of things in parallel fast.
One limitation is that it only handles digital electronics: https://electronics.stackexchange.com/questions/25525/are-there-any-analog-fpgas There are some analog analogs, but they are much more restricted due to signal loss, which is exactly what digital electronics is very good at mitigating.
\Video[https://www.youtube.com/watch?v=gl4CuzOH6I4]
{title=First FPGA experiences with a Digilent Cora Z7 Xilinx Zynq by <Marco Reps> (2018)}
{description=Good video, actually gives some rationale of a use case that a <microcontroller> wouldn't handle because it is not fast enough.}
\Video[https://www.youtube.com/watch?v=0zrqYy369NQ]
{title=FPGA Dev Board Tutorial by Ben Heck (2016)}
\Video[https://www.youtube.com/watch?v=m-8G1Yixb34]
{title=The History of the FPGA by <Asianometry> (2022)}
= FPGA company
{c}
{parent=Field-programmable gate array}
{tag=Semiconductor company}
= Xilinx
{c}
{parent=FPGA company}
{title2=1984-2022}
{wiki}
= Graphics processing unit
{parent=Type of processor}
{wiki}
= GPU
{c}
{synonym}
{title2}
= GPUs
{c}
{synonym}
= General-purpose computing on graphics processing units
{parent=Graphics processing unit}
{wiki}
= GPGPU
{c}