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mcoshiro
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EMP FPGA2 (#343)
* rudiments of a dual-fpga EMP project * updates for decl files * move files to proper locations * dummy payload test * update dependencies * Updates for dual-FPGA using latest emp fwk * F1 builds * working build for F2 with trivial payload (CSP test) * update build script * Update emp_project_decl_f2.vhd fix which inter-fpga quads are implemented on F2 * update to tags on emp-fwk and CM_FPGA_FW * emp-fwk to 0.9.0-alpha2 * more updates for 0.9.0-pre2 * tweak build script * Update setup_project.sh * Manually copy EMP changes from emp_dual_* branches * Some fixes to DualFPGA project generation after copy-merging * Some more compatibility changes * Many bug fixes, FPGA2 project now outputs tracks in simulation * Updates to make things work out-of-the-box * First attempt at allowing simultaneous builds for both FPGAs * Some fixes for FPGA1 build and integration * Fixes to control signals on EMP FPGA1 project * Fix make rule for individual FPGA projects * Manually copied FPGA2-targeted changes from dual_fpga2_4_ryd_validupdates * Cleanup based on suggestions from Andrew. Also updated README * Fix issue introduced by attempting to combine vsim.tcl scripts * Remove commented code * Removed left-over PHONY target --------- Co-authored-by: Peter Wittich <[email protected]>
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‎IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile

+2-5
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ input_file = mem/in.txt
44
proj_path = ../../../../proj
55
hls_script_path = ../../script
66

7-
all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input lut_inclusion
7+
all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input
88

99
$(core_dir):
1010
@mkdir cgn mem
@@ -32,9 +32,6 @@ add_common_files:
3232
hdl_add_files: $(core_file)
3333
cd hdl; ln -s ../../../hdl/*.vhd .
3434

35-
lut_inclusion:
36-
@python3 scripts/lut_copy.py
37-
3835
$(input_file): $(core_dir)
3936
@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsCMBarrel/InputStubs -o $(input_file)
4037

@@ -53,4 +50,4 @@ sim: $(input_file) $(core_file) $(core_dir)
5350
@cd $(hls_script_path); vivado -mode batch -source runSim.tcl
5451
@python3 scripts/fwtosim_comparison.py -e mem/out.txt -s $(hls_script_path)/dataOut/TF_L1L2.txt
5552

56-
.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input lut_inclusion core_patch
53+
.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input core_patch

‎IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl

+2-7
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,11 @@
11
set_property SOURCE_SET sources_1 [get_filesets sim_1]
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add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/mem/in.txt
3-
set lut_script [file dirname [file normalize ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/pre_msim.tcl ]]
4-
append lut_script "/pre_msim.tcl"
5-
add_files -fileset utils_1 -norecurse $lut_script
6-
#set_property STEPS.SYNTH_DESIGN.TCL.PRE $lut_script [get_runs sim_1]
7-
#add_files -fileset sim_1 -norecurse ../../src/firmware-hls/firmware/mem/out.txt
8-
set pre_path "set_property -name {xsim.compile.tcl.pre} -value {$lut_script} -objects \[\get_filesets \sim_1\]"
9-
eval ${pre_path}
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# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
125
set_property source_mgmt_mode None [current_project]
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set_property top top [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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set_property target_language VHDL [current_project]
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set_property simulator_language VHDL [current_project]
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# Re-enabling previously disabled source management mode.
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set_property source_mgmt_mode All [current_project]

‎IntegrationTests/DualFPGA/firmware/Makefile

+65
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@@ -0,0 +1,65 @@
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core_file_fpga1 = scripts/xciMaker_fpga1
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core_file_fpga2 = scripts/xciMaker_fpga2
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core_dir = cgn
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input_file_fpga1 = mem/in_fpga1.txt
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input_file_fpga2 = mem/in_fpga2.txt
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fpga1_hls_script_path = ../../CombinedConfig_FPGA1/script
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fpga2_hls_script_path = ../../CombinedConfig_FPGA2/script
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9+
all: add_common_files $(core_file_fpga1) $(core_file_fpga2) hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj $(input_file_fpga1) $(input_file_fpga2) apollo_input_fpga1 apollo_input_fpga2
10+
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fpga1: add_common_files $(core_file_fpga1) hdl_add_files_fpga1 xciCreation_fpga1 kfin_adj $(input_file_fpga1) apollo_input_fpga1
12+
13+
fpga2: add_common_files $(core_file_fpga2) hdl_add_files_fpga2 xciCreation_fpga2 kfin_adj $(input_file_fpga2) apollo_input_fpga2
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$(core_dir):
16+
@mkdir cgn mem
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@mkdir cgn/f1
18+
@mkdir cgn/f2
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@cd mem; ln -s ../../../../emData/LUTsSplit LUTs
20+
@cd mem; ln -s ../../../../emData/MemPrintsSplit MemPrintsSplit
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@cd hdl; ln -s ../../../common common
22+
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$(core_file_fpga1): $(core_dir)
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make -C $(fpga1_hls_script_path) -j 24 Work
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@python3 scripts/include_cores.py -s $(fpga1_hls_script_path) -o $(core_file_fpga1) -f f1
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$(core_file_fpga2): $(core_dir)
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make -C $(fpga2_hls_script_path) -j 24 Work
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@python3 scripts/include_cores.py -s $(fpga2_hls_script_path) -o $(core_file_fpga2) -f f2
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kfin_adj:
32+
@python3 scripts/kf_link_mod.py
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xciCreation_fpga1: $(core_file_fpga1)
35+
make -f $(core_file_fpga1) -j 8 all
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xciCreation_fpga2: $(core_file_fpga2)
38+
make -f $(core_file_fpga2) -j 8 all
39+
40+
add_common_files:
41+
@if [ ! -d ucf ]; then mkdir ucf; fi
42+
@cd ucf; ln -s ../../../common/ucf/*.tcl .
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@cd scripts; ln -s ../../../common/script/emp/* .
44+
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hdl_add_files_fpga1: $(core_file)
46+
cd hdl; ln -s ../../../CombinedConfig_FPGA1/hdl/SectorProcessor.vhd SectorProcessor_f1.vhd
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cd hdl; ln -s ../../../CombinedConfig_FPGA1/hdl/memUtil_pkg.vhd memUtil_pkg_f1.vhd
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hdl_add_files_fpga2: $(core_file)
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cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/SectorProcessor.vhd SectorProcessor_f2.vhd
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cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/memUtil_pkg.vhd memUtil_pkg_f2.vhd
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$(input_file_fpga1): $(core_dir)
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@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsSplit/InputStubs -o $(input_file_fpga1)
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$(input_file_fpga2): $(core_dir)
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@python3 scripts/convert_emData2EMP_Link_FPGA2.py -d mem/MemPrintsSplit/ -o $(input_file_fpga2)
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apollo_input_fpga1: $(input_file_fpga1)
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@python3 scripts/split_emp_input.py -i $(input_file_fpga1) -o mem/in_fpga1_
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apollo_input_fpga2: $(input_file_fpga2)
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@python3 scripts/split_emp_input.py -i $(input_file_fpga2) -o mem/in_fpga2_
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.PHONY: all fpga1 fpga2 add_common_files hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj apollo_input_fpga1 apollo_input_fpga2

‎IntegrationTests/DualFPGA/firmware/cfg/apollo.dep

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@@ -0,0 +1,15 @@
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# common for both FPGAs
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3+
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src -c emp-fwk:components/datapath emp_data_types.vhd
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src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd
6+
7+
include -c ipbus-firmware:components/ipbus_slaves ipbus_syncreg_v.dep ipbus_ctrlreg_v.dep ipbus_reg_v.dep ipbus_freq_ctr.dep
8+
9+
#src ../constrs/floorplan_emp
10+
11+
include -c emp-fwk:components/links/slink slink.dep
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13+
addrtab -c emp-fwk:components/payload emp_payload.xml
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15+

‎IntegrationTests/DualFPGA/firmware/cfg/apollo_f1.dep

+8
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@@ -0,0 +1,8 @@
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include payload_f1.dep
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src emp_project_decl_f1.vhd
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setup ../ucf/ip.tcl
5+
6+
include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep
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8+
include apollo.dep

‎IntegrationTests/DualFPGA/firmware/cfg/apollo_f2.dep

+8
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@@ -0,0 +1,8 @@
1+
2+
include payload_f2.dep
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src emp_project_decl_f2.vhd
4+
setup ../ucf/ip.tcl
5+
6+
include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p2_2.dep
7+
8+
include apollo.dep

‎IntegrationTests/DualFPGA/firmware/cfg/payload_f1.dep

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#Payload and top level
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src payload_f1.vhd
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src tf1_wrapper.vhd
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src linktosecproc.vhd
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src secproc1tolink.vhd
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src --vhdl2008 SectorProcessor_f1.vhd
7+
#src common/hdl/emp/pkgs/tf_interface_pkg.vhd
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src memUtil_pkg_f1.vhd
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src memUtil_aux_pkg_f1.vhd
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src common/hdl/emp/pkgs/GCU_utils.vhd
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src conv_pkg_f1.vhd
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include -c firmware-hls:KalmanFilter/common components.dep
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14+
#Track Builder dependencies
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src common/hdl/CreateStartSignal.vhd
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#src --vhdl2008 common/hdl/tf_lut.vhd
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src --vhdl2008 common/hdl/tf_mem_bin.vhd
18+
src --vhdl2008 common/hdl/tf_mem_format.vhd
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src --vhdl2008 common/hdl/tf_mem.vhd
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src --vhdl2008 common/hdl/tf_merge_streamer.vhd
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src common/hdl/tf_pkg.vhd
22+
src --vhdl2008 common/hdl/tf_pipe_delay.vhd
23+
24+
################
25+
# Include Cores
26+
################
27+
iprepo *
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src ../cgn/f1/*/*/*.xci
29+

‎IntegrationTests/DualFPGA/firmware/cfg/payload_f2.dep

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src memUtil_pkg_f2.vhd
2+
src memUtil_aux_pkg_f2.vhd
3+
src payload_f2.vhd
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src linktosecproc2.vhd
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src sp2_mem_writer.vhd
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src tf2_wrapper.vhd
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src --vhdl2008 SectorProcessor_f2.vhd
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src tf_to_kf.vhd
9+
src kf_wrapper.vhd
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src common/hdl/emp/pkgs/tf_interface_pkg.vhd
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src kf_input_merger.vhd
12+
13+
# KF
14+
include -c firmware-hls:KalmanFilter/kfin components.dep
15+
include -c firmware-hls:KalmanFilter/kf components.dep
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include -c firmware-hls:KalmanFilter/kfout components.dep
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include -c firmware-hls:KalmanFilter/tq components.dep
18+
include -c firmware-hls:KalmanFilter/common components.dep
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20+
#Tracklet dependencies
21+
src common/hdl/CreateStartSignal.vhd
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#src --vhdl2008 common/hdl/tf_lut.vhd
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src --vhdl2008 common/hdl/tf_mem_bin.vhd
24+
src --vhdl2008 common/hdl/tf_mem_format.vhd
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src --vhdl2008 common/hdl/tf_mem.vhd
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src --vhdl2008 common/hdl/tf_mem_tproj.vhd
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src --vhdl2008 common/hdl/tf_mem_tpar.vhd
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src --vhdl2008 common/hdl/mem_reader.vhd
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src common/hdl/tf_pkg.vhd
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src --vhdl2008 common/hdl/tf_pipe_delay.vhd
31+
32+
#Floorplan
33+
src ../ucf/floorplan_f2.tcl
34+
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################
36+
# Include Cores
37+
################
38+
iprepo *
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src ../cgn/f2/*/*/*.xci
40+

‎IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep

+14
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#don't include cm_v2_p1_2 since without decoder, it will have unresolved tcds2 dependencies
2+
@fpga_position = "1"
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@fpga_speed_grade = "-2-e"
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include payload_f1.dep
6+
setup ../ucf/vsim_f1.tcl
7+
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include -c emp-fwk:boards/testbench top.dep
9+
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src tb_decl_f1.vhd
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src emp_project_decl_f1.vhd
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src -c emp-fwk:components/links/slink emp_slink_types.vhd
13+
14+
include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p1.dep

‎IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep

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#don't include cm_v2_p1_2 since without decoder, it will have unresolved tcds2 dependencies
2+
@fpga_position = "2"
3+
@fpga_speed_grade = "-2-e"
4+
5+
include payload_f2.dep
6+
setup ../ucf/vsim_f2.tcl
7+
8+
include -c emp-fwk:boards/testbench top.dep
9+
10+
src tb_decl_f2.vhd
11+
src emp_project_decl_f2.vhd
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src -c emp-fwk:components/links/slink emp_slink_types.vhd
13+
14+
include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p2.dep

‎IntegrationTests/DualFPGA/firmware/hdl/conv_pkg_f1.vhd

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1+
library ieee;
2+
use ieee.std_logic_1164.all;
3+
4+
use work.emp_data_types.all;
5+
use work.hybrid_data_types.all;
6+
7+
package conv_pkg_f1 is
8+
9+
function conv_single (l : ldata)
10+
return t_packet;
11+
12+
end package conv_pkg_f1;
13+
14+
package body conv_pkg_f1 is
15+
16+
function conv_single(l : ldata) return t_packet is
17+
variable s : t_packet;
18+
begin
19+
s.valid := l(68).valid;
20+
s.start_of_orbit := l(68).start_of_orbit;
21+
s.start := l(68).start;
22+
s.last := l(68).last;
23+
return s;
24+
end;
25+
26+
end package body conv_pkg_f1;
27+
28+
29+
30+

‎IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f1.vhd

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1+
2+
library IEEE;
3+
use IEEE.STD_LOGIC_1164.all;
4+
5+
use work.emp_framework_decl.all;
6+
use work.emp_device_types.all;
7+
use work.emp_slink_types.all;
8+
9+
package emp_project_decl is
10+
11+
constant PAYLOAD_REV : std_logic_vector(31 downto 0) := X"12345678";
12+
13+
-- Latency buffer size
14+
constant LB_ADDR_WIDTH : integer := 10;
15+
16+
-- Clock setup
17+
constant CLOCK_COMMON_RATIO : integer := 36;
18+
constant CLOCK_RATIO : integer := 6;
19+
constant CLOCK_AUX_DIV : clock_divisor_array_t := (18, 9, 4); -- Dividers of CLOCK_COMMON_RATIO * 40 MHz
20+
21+
-- Readdjust if latency changes for FPGA1 algorithm
22+
constant PAYLOAD_LATENCY : integer := 140;
23+
24+
-- F1 transmits to F2 on inter-fpga links
25+
constant REGION_CONF : region_conf_array_t := (
26+
0 => kDummyRegion, -- service c2c
27+
1 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
28+
2 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
29+
3 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
30+
4 => kDummyRegion, -- not routed
31+
5 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
32+
6 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
33+
7 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
34+
8 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
35+
9 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
36+
10 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
37+
11 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
38+
12 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
39+
13 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
40+
14 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
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15 => kDummyRegion, -- not routed
42+
------cross
43+
----- all MGTs instantiated bidirectionally for now
44+
16 => kDummyRegion, -- not routed
45+
17 => (gty25, buf, no_fmt, buf, gty25), -- firefly
46+
18 => (gty25, buf, no_fmt, buf, gty25), -- firefly
47+
19 => (gty25, buf, no_fmt, buf, gty25), -- firefly
48+
20 => kDummyRegion, -- not routed
49+
21 => (gty25, buf, no_fmt, buf, gty25), -- firefly
50+
22 => (gty25, buf, no_fmt, buf, gty25), -- firefly
51+
23 => (gty25, buf, no_fmt, buf, gty25), -- firefly
52+
24 => (gty25, buf, no_fmt, buf, gty25), -- firefly
53+
25 => (gty25, buf, no_fmt, buf, gty25), -- firefly
54+
26 => (gty25, buf, no_fmt, buf, gty25), -- firefly
55+
27 => (gty25, buf, no_fmt, buf, gty25), -- firefly
56+
28 => (gty25, buf, no_fmt, buf, gty25), -- firefly
57+
29 => (gty25, buf, no_fmt, buf, gty25), -- firefly
58+
30 => (gty25, buf, no_fmt, buf, gty25), -- firefly
59+
31 => kDummyRegion, -- service tcds
60+
61+
others => kDummyRegion
62+
);
63+
64+
-- Specify the slink quad using the corresponding region conf ID
65+
-- Specify slink channels to enable using the channel mask
66+
constant SLINK_CONF : slink_conf_array_t := (
67+
others => kNoSlink
68+
);
69+
70+
71+
end emp_project_decl;

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