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jasonfan393jasonfan393
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first FPGA with merged TPARs (#60)
* add dict that tracks TPAR merging scheme * changes to add tf_merge_streamer * add stream signals to tb * add functioning tb * change merging scheme to be consistent with FPGA2 * add split flags * remove some magic numbers * small fixes * change inner AS size for disks * change split flag for 2 fpga projects to an int * add more flags * fix some bugs * fix fixme * small fix * fix bugs * update for TPAR addr size * update to remove hardcoded dict * add missing change from commit * only gen dictionary for split projects * add default value for mpar_dict for other projects * add missing split tags * address comment
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4 files changed

+259
-123
lines changed

4 files changed

+259
-123
lines changed

‎TrackletGraph.py

+18-6
Original file line numberDiff line numberDiff line change
@@ -210,10 +210,7 @@ def populate_bitwidths(mem,hls_dir): # FIXME this information should be parsed f
210210
elif mem.mtype == "AllStubs" or mem.mtype == "InputLink":
211211
mem.bitwidth = 36
212212
elif mem.mtype == "AllInnerStubs":
213-
if disk>-1:
214-
mem.bitwidth = 52
215-
else:
216-
mem.bitwidth = 51
213+
mem.bitwidth = 51
217214
elif mem.mtype == "DTCLink":
218215
mem.bitwidth = 39
219216
elif mem.mtype == "StubPairs":
@@ -637,17 +634,32 @@ def get_proc_module(self, instance_name, verbose=True):
637634
print("WARNING!! Cannot find module", instance_name,"!!")
638635
return None
639636

640-
def get_all_module_units(self, module):
637+
def get_all_module_units(self, module, split = 0):
641638
"Return all the ProcModule objects of a given type"
642639
modules = {}
643640
for instance_name in self.__proc_dict:
644641
#FIXME
645-
if instance_name.startswith(module+"_") or instance_name.startswith("VMSMER_"):
642+
if split == 2:
643+
if instance_name.startswith(module+"_") or instance_name.startswith("VMSMER_"):
644+
modules[instance_name]=self.__proc_dict[instance_name]
645+
elif instance_name.startswith(module+"_"):
646646
modules[instance_name]=self.__proc_dict[instance_name]
647647
if not modules:
648648
print("WARNING!! Cannot find any modules with name starting with", module,"!!")
649649
else:
650650
return modules
651+
def get_MPAR_dict(self):
652+
#returns a dict which containing info related to the mergining
653+
#of TPROJ memories for split FPGA projects
654+
MPAR_dict = {}
655+
PC_dict = self.get_all_module_units("PC")
656+
for key, value in PC_dict.items():
657+
iTCs = key[7:]
658+
seed = key[3:7]
659+
if seed not in MPAR_dict:
660+
MPAR_dict[seed] = []
661+
MPAR_dict[seed].append(iTCs)
662+
return MPAR_dict
651663

652664
def get_mem_module(self, instance_name, verbose=True):
653665
" Return a MemModule object given the instance name "

‎WriteHDLUtils.py

+17-17
Original file line numberDiff line numberDiff line change
@@ -1192,7 +1192,7 @@ def parseProcFunction(proc_name, fname_def):
11921192
return arg_types_list, arg_names_list, templ_pars_list
11931193

11941194
def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars,
1195-
f_matchArgPortNames, first_of_type, extraports,delay,split=False):
1195+
f_matchArgPortNames, first_of_type, extraports,delay,split=0):
11961196
####
11971197
# function name
11981198

@@ -1352,7 +1352,7 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars,
13521352
if "DL" in memory.inst and "AS" not in memory.inst: # DTCLink
13531353
string_mem_ports += writeProcDTCLinkRHSPorts(tmp_argname,memory)
13541354
else:
1355-
string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory)
1355+
string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory, split=split)
13561356

13571357
if portname.replace("outer","").find("out") != -1:
13581358
if memory.isFIFO():
@@ -1362,7 +1362,7 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars,
13621362
if portname.find("trackpar") != -1 and (module.mtype == "TrackletCalculator" or module.mtype == "TrackletProcessor"):
13631363
string_mem_ports += writeProcMemoryLHSPorts(tmp_argname,memory,split)
13641364
elif portname.find("trackpar") != -1 and module.mtype == "PurgeDuplicates":
1365-
string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory)
1365+
string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory,split=split)
13661366

13671367
# Remove the already added module and name from the lists
13681368
portNameList.remove(portname)
@@ -1397,17 +1397,17 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars,
13971397
return str_ctrl_wire,module_str
13981398

13991399
################################
1400-
def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, split = False):
1400+
def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, split = 0):
14011401
if module.mtype == 'InputRouter':
14021402
return writeModuleInst_generic(module, hls_src_dir,
14031403
writeTemplatePars_IR,
14041404
matchArgPortNames_IR,
1405-
first_of_type, extraports, delay)
1405+
first_of_type, extraports, delay, split)
14061406
elif module.mtype == 'VMRouter':
14071407
return writeModuleInst_generic(module, hls_src_dir,
14081408
writeTemplatePars_VMR,
14091409
matchArgPortNames_VMR,
1410-
first_of_type, extraports, delay)
1410+
first_of_type, extraports, delay, split)
14111411
elif module.mtype == 'VMRouterCM':
14121412
return writeModuleInst_generic(module, hls_src_dir,
14131413
writeTemplatePars_VMRCM,
@@ -1417,7 +1417,7 @@ def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, s
14171417
return writeModuleInst_generic(module, hls_src_dir,
14181418
writeTemplatePars_TE,
14191419
matchArgPortNames_TE,
1420-
first_of_type, extraports, delay)
1420+
first_of_type, extraports, delay, split)
14211421
elif module.mtype == 'TrackletProcessor':
14221422
return writeModuleInst_generic(module, hls_src_dir,
14231423
writeTemplatePars_TP,
@@ -1427,51 +1427,51 @@ def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, s
14271427
return writeModuleInst_generic(module, hls_src_dir,
14281428
writeTemplatePars_TC,
14291429
matchArgPortNames_TC,
1430-
first_of_type, extraports, delay)
1430+
first_of_type, extraports, delay, split)
14311431
elif module.mtype == 'ProjectionRouter':
14321432
return writeModuleInst_generic(module, hls_src_dir,
14331433
writeTemplatePars_PR,
14341434
matchArgPortNames_PR,
1435-
first_of_type, extraports, delay)
1435+
first_of_type, extraports, delay, split)
14361436
elif module.mtype == 'MatchEngine':
14371437
return writeModuleInst_generic(module, hls_src_dir,
14381438
writeTemplatePars_ME,
14391439
matchArgPortNames_ME,
1440-
first_of_type, extraports, delay)
1440+
first_of_type, extraports, delay, split)
14411441
elif module.mtype == 'MatchCalculator':
14421442
return writeModuleInst_generic(module, hls_src_dir,
14431443
writeTemplatePars_MC,
14441444
matchArgPortNames_MC,
1445-
first_of_type, extraports, delay)
1445+
first_of_type, extraports, delay, split)
14461446
elif module.mtype == 'MatchProcessor':
14471447
return writeModuleInst_generic(module, hls_src_dir,
14481448
writeTemplatePars_MP,
14491449
matchArgPortNames_MP,
1450-
first_of_type, extraports, delay)
1450+
first_of_type, extraports, delay, split)
14511451
elif module.mtype == 'FitTrack':
14521452
return writeModuleInst_generic(module, hls_src_dir,
14531453
writeTemplatePars_FT,
14541454
matchArgPortNames_FT,
1455-
first_of_type, extraports, delay)
1455+
first_of_type, extraports, delay, split)
14561456
elif module.mtype == 'TrackBuilder':
14571457
return writeModuleInst_generic(module, hls_src_dir,
14581458
writeTemplatePars_TB,
14591459
matchArgPortNames_TB,
1460-
first_of_type, extraports, delay)
1460+
first_of_type, extraports, delay, split)
14611461
elif module.mtype == 'PurgeDuplicate':
14621462
return writeModuleInst_generic(module, hls_src_dir,
14631463
writeTemplatePars_PD,
14641464
matchArgPortNames_PD,
1465-
first_of_type, extraports, delay)
1465+
first_of_type, extraports, delay, split)
14661466
elif module.mtype == 'ProjectionCalculator':
14671467
return writeModuleInst_generic(module, hls_src_dir,
14681468
writeTemplatePars_PC,
14691469
matchArgPortNames_PC,
1470-
first_of_type, extraports, delay)
1470+
first_of_type, extraports, delay, split)
14711471
elif module.mtype == 'VMSMERouter':
14721472
return writeModuleInst_generic(module, hls_src_dir,
14731473
writeTemplatePars_VMSMER,
14741474
matchArgPortNames_VMSMER,
1475-
first_of_type, extraports, delay)
1475+
first_of_type, extraports, delay, split)
14761476
else:
14771477
raise ValueError(module.mtype + " is unknown.")

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