From efa78e05637fe7c6850094bf7bd86d9082ae4abb Mon Sep 17 00:00:00 2001 From: Michael Oshiro Date: Thu, 10 Oct 2024 07:38:29 -0400 Subject: [PATCH 1/3] Added changes to propagate TP_bx_vld to tf_merge_stream and output bx from merge_stream module --- WriteVHDLSyntax.py | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 7140c57..be793a4 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -646,10 +646,15 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl merge_parameterlist += " NUM_INPUTS => "+str(numInputs)+",\n" merge_parameterlist += " NUM_EXTRA_BITS => 2,\n" merge_portlist += " bx_in => TP_bx_out,\n" + merge_portlist += " bx_in_vld => TP_bx_out_vld,\n" merge_portlist += " rst => '0',\n" merge_portlist += " clk => clk,\n" merge_portlist += " enb_arr => open,\n" - merge_portlist += " bx_out => open,\n" + #This will make output for first stream_merge module (is there a less hacky way?) + if (seed+PCGroup)=='L1L2ABC': + merge_portlist += " bx_out => TP_bx_out_merged,\n" + else: + merge_portlist += " bx_out => open,\n" merge_portlist += " merged_dout => MPAR_"+seed+PCGroup+"_stream_V_dout,\n" for i in range(4): merge_portlist += " din"+str(i)+"=>TPAR_"+seed+PCGroup[i%numInputs]+"_V_dout,\n" for i in range(4): merge_portlist += " nent"+str(i)+"=>TPAR_"+seed+PCGroup[i%numInputs]+"_AV_dout_nent,\n" @@ -668,6 +673,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl merge_parameterlist += " NUM_INPUTS => "+str(numInputs)+",\n" merge_parameterlist += " NUM_EXTRA_BITS => 0,\n" merge_portlist += " bx_in => TP_bx_out,\n" + merge_portlist += " bx_in_vld => TP_bx_out_vld,\n" merge_portlist += " rst => '0',\n" merge_portlist += " clk => clk,\n" merge_portlist += " enb_arr => open,\n" @@ -782,6 +788,8 @@ def writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, del string_ctrl_signals += " reset : in std_logic;\n" string_ctrl_signals += " "+initial_proc+"_start : in std_logic;\n" string_ctrl_signals += " "+initial_proc+"_bx_in : in std_logic_vector(2 downto 0);\n" + if split == 1: + string_ctrl_signals += " TP_bx_out_merged : out std_logic_vector(2 downto 0);\n" if split == 2: string_ctrl_signals += " "+initial_proc+"_bx_out : out std_logic_vector(2 downto 0);\n" string_ctrl_signals += " "+initial_proc+"_bx_out_vld : out std_logic;\n" @@ -1528,7 +1536,9 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_ int_ctrl_func += " start => PC_done\n" int_ctrl_func += " );\n\n" - + #if "TP_" in mtype and first_of_type : + # int_ctrl_wire += " signal TP_bx_out_vld_int : std_logic;\n" + if first_proc: mtype_up = module.mtype_short() else: @@ -1613,7 +1623,7 @@ def writeProcBXPort(modName,isInput,isInitial,first_of_type,delay): if first_of_type and not ("VMSMER" in modName or "PC" in modName): bx_str += " bx_o_V => "+modName.split("_")[0]+"_bx_out,\n" #bx_str += " bx_o_V_ap_vld => "+modName+"_bx_out_vld,\n" - if "FT_" in modName: + if ("FT_" in modName) or ("TP_" in modName): bx_str += " bx_o_V_ap_vld => "+modName.split("_")[0]+"_bx_out_vld,\n" else: bx_str += " bx_o_V_ap_vld => open,\n" From 20898b279f9256ef172cf256ba029c00f201dc1a Mon Sep 17 00:00:00 2001 From: Michael Oshiro Date: Thu, 10 Oct 2024 07:50:58 -0400 Subject: [PATCH 2/3] Cleanup comment --- WriteVHDLSyntax.py | 3 --- 1 file changed, 3 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index be793a4..91a23a3 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -1535,9 +1535,6 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_ int_ctrl_func += " bx => PC_bx_out,\n" int_ctrl_func += " start => PC_done\n" int_ctrl_func += " );\n\n" - - #if "TP_" in mtype and first_of_type : - # int_ctrl_wire += " signal TP_bx_out_vld_int : std_logic;\n" if first_proc: mtype_up = module.mtype_short() From dbd9e736a833614604537cd17486d9f89dfd648b Mon Sep 17 00:00:00 2001 From: Michael Oshiro Date: Wed, 23 Oct 2024 09:21:11 -0400 Subject: [PATCH 3/3] Incorporate Andrew's suggestion; make TPAR memories into URAM --- WriteVHDLSyntax.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 91a23a3..e060c72 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -420,6 +420,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl interface = int(memInfo.is_final) - int(memInfo.is_initial) + first_merge_streamer = True + for memmod in memList: nmem = 0 @@ -592,6 +594,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl parameterlist += " NUM_PHI_BINS => 8,\n" parameterlist += " NUM_RZ_BINS => 16,\n" parameterlist += " NUM_COPY => "+str(ncopy)+"\n" + if "TPAR" in mem: + parameterlist += " MEM_TYPE => \"ultra\",\n" #FIXME implement delay for disks # Write ports @@ -651,8 +655,9 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl merge_portlist += " clk => clk,\n" merge_portlist += " enb_arr => open,\n" #This will make output for first stream_merge module (is there a less hacky way?) - if (seed+PCGroup)=='L1L2ABC': + if first_merge_streamer: merge_portlist += " bx_out => TP_bx_out_merged,\n" + first_merge_streamer = False else: merge_portlist += " bx_out => open,\n" merge_portlist += " merged_dout => MPAR_"+seed+PCGroup+"_stream_V_dout,\n"