cpu0.fit.eqn

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--D1_flag_c is flag_reg:inst2|flag_c at LC3_G33
--operation mode is normal

D1_flag_c_lut_out = !D1L71;
D1_flag_c = DFFEA(D1_flag_c_lut_out, GLOBAL(clk), reset, , , , );

--D1L2Q is flag_reg:inst2|flag_c~4 at LC3_G33
--operation mode is normal

D1L2Q = D1_flag_c;


--D1_flag_z is flag_reg:inst2|flag_z at LC2_G36
--operation mode is normal

D1_flag_z_lut_out = B1L552 & B1L952 & B1L752;
D1_flag_z = DFFEA(D1_flag_z_lut_out, GLOBAL(clk), reset, , D1L9, , );

--D1L8Q is flag_reg:inst2|flag_z~10 at LC2_G36
--operation mode is normal

D1L8Q = D1_flag_z;


--D1_flag_v is flag_reg:inst2|flag_v at LC2_G37
--operation mode is normal

D1_flag_v_lut_out = !B1L892;
D1_flag_v = DFFEA(D1_flag_v_lut_out, GLOBAL(clk), reset, , D1L9, , );

--D1L6Q is flag_reg:inst2|flag_v~6 at LC2_G37
--operation mode is normal

D1L6Q = D1_flag_v;


--D1_flag_s is flag_reg:inst2|flag_s at LC8_G37
--operation mode is normal

D1_flag_s_lut_out = B1L251;
D1_flag_s = DFFEA(D1_flag_s_lut_out, GLOBAL(clk), reset, , D1L9, , );

--D1L4Q is flag_reg:inst2|flag_s~6 at LC8_G37
--operation mode is normal

D1L4Q = D1_flag_s;


--J1_q[15] is ar:inst9|q[15] at LC6_G30
--operation mode is normal

J1_q[15]_lut_out = H1_rec[1] & B1L251 # !H1_rec[1] & (K1_q[15]);
J1_q[15] = DFFEA(J1_q[15]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L33Q is ar:inst9|q[15]~80 at LC6_G30
--operation mode is normal

J1L33Q = J1_q[15];


--J1_q[14] is ar:inst9|q[14] at LC4_F30
--operation mode is normal

J1_q[14]_lut_out = H1_rec[1] & B1L341 # !H1_rec[1] & (K1_q[14]);
J1_q[14] = DFFEA(J1_q[14]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L13Q is ar:inst9|q[14]~81 at LC4_F30
--operation mode is normal

J1L13Q = J1_q[14];


--J1_q[13] is ar:inst9|q[13] at LC7_F34
--operation mode is normal

J1_q[13]_lut_out = H1_rec[1] & B1L331 # !H1_rec[1] & (K1_q[13]);
J1_q[13] = DFFEA(J1_q[13]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L92Q is ar:inst9|q[13]~82 at LC7_F34
--operation mode is normal

J1L92Q = J1_q[13];


--J1_q[12] is ar:inst9|q[12] at LC3_F31
--operation mode is normal

J1_q[12]_lut_out = H1_rec[1] & B1L321 # !H1_rec[1] & (K1_q[12]);
J1_q[12] = DFFEA(J1_q[12]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L72Q is ar:inst9|q[12]~83 at LC3_F31
--operation mode is normal

J1L72Q = J1_q[12];


--J1_q[11] is ar:inst9|q[11] at LC5_D45
--operation mode is normal

J1_q[11]_lut_out = H1_rec[1] & B1L311 # !H1_rec[1] & (K1_q[11]);
J1_q[11] = DFFEA(J1_q[11]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L52Q is ar:inst9|q[11]~84 at LC5_D45
--operation mode is normal

J1L52Q = J1_q[11];


--J1_q[10] is ar:inst9|q[10] at LC3_D45
--operation mode is normal

J1_q[10]_lut_out = H1_rec[1] & B1L301 # !H1_rec[1] & (K1_q[10]);
J1_q[10] = DFFEA(J1_q[10]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L32Q is ar:inst9|q[10]~85 at LC3_D45
--operation mode is normal

J1L32Q = J1_q[10];


--J1_q[9] is ar:inst9|q[9] at LC6_D45
--operation mode is normal

J1_q[9]_lut_out = H1_rec[1] & B1L39 # !H1_rec[1] & (K1_q[9]);
J1_q[9] = DFFEA(J1_q[9]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L12Q is ar:inst9|q[9]~86 at LC6_D45
--operation mode is normal

J1L12Q = J1_q[9];


--J1_q[8] is ar:inst9|q[8] at LC4_D45
--operation mode is normal

J1_q[8]_lut_out = H1_rec[1] & B1L38 # !H1_rec[1] & (K1_q[8]);
J1_q[8] = DFFEA(J1_q[8]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L91Q is ar:inst9|q[8]~87 at LC4_D45
--operation mode is normal

J1L91Q = J1_q[8];


--J1_q[7] is ar:inst9|q[7] at LC7_C47
--operation mode is normal

J1_q[7]_lut_out = H1_rec[1] & B1L37 # !H1_rec[1] & (K1_q[7]);
J1_q[7] = DFFEA(J1_q[7]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L71Q is ar:inst9|q[7]~88 at LC7_C47
--operation mode is normal

J1L71Q = J1_q[7];


--J1_q[6] is ar:inst9|q[6] at LC3_G40
--operation mode is normal

J1_q[6]_lut_out = H1_rec[1] & B1L36 # !H1_rec[1] & (K1_q[6]);
J1_q[6] = DFFEA(J1_q[6]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L51Q is ar:inst9|q[6]~89 at LC3_G40
--operation mode is normal

J1L51Q = J1_q[6];


--J1_q[5] is ar:inst9|q[5] at LC8_D45
--operation mode is normal

J1_q[5]_lut_out = H1_rec[1] & B1L35 # !H1_rec[1] & (K1_q[5]);
J1_q[5] = DFFEA(J1_q[5]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L31Q is ar:inst9|q[5]~90 at LC8_D45
--operation mode is normal

J1L31Q = J1_q[5];


--J1_q[4] is ar:inst9|q[4] at LC4_H44
--operation mode is normal

J1_q[4]_lut_out = H1_rec[1] & B1L34 # !H1_rec[1] & (K1_q[4]);
J1_q[4] = DFFEA(J1_q[4]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L11Q is ar:inst9|q[4]~91 at LC4_H44
--operation mode is normal

J1L11Q = J1_q[4];


--J1_q[3] is ar:inst9|q[3] at LC1_D45
--operation mode is normal

J1_q[3]_lut_out = H1_rec[1] & B1L33 # !H1_rec[1] & (K1_q[3]);
J1_q[3] = DFFEA(J1_q[3]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L9Q is ar:inst9|q[3]~92 at LC1_D45
--operation mode is normal

J1L9Q = J1_q[3];


--J1_q[2] is ar:inst9|q[2] at LC4_H47
--operation mode is normal

J1_q[2]_lut_out = H1_rec[1] & B1L32 # !H1_rec[1] & (K1_q[2]);
J1_q[2] = DFFEA(J1_q[2]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L7Q is ar:inst9|q[2]~93 at LC4_H47
--operation mode is normal

J1L7Q = J1_q[2];


--J1_q[1] is ar:inst9|q[1] at LC2_D45
--operation mode is normal

J1_q[1]_lut_out = H1_rec[1] & B1L31 # !H1_rec[1] & (K1_q[1]);
J1_q[1] = DFFEA(J1_q[1]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L5Q is ar:inst9|q[1]~94 at LC2_D45
--operation mode is normal

J1L5Q = J1_q[1];


--J1_q[0] is ar:inst9|q[0] at LC1_E46
--operation mode is normal

J1_q[0]_lut_out = H1_rec[1] & B1L4 # !H1_rec[1] & (K1_q[0]);
J1_q[0] = DFFEA(J1_q[0]_lut_out, GLOBAL(clk), reset, , H1_rec[0], , );

--J1L3Q is ar:inst9|q[0]~95 at LC1_E46
--operation mode is normal

J1L3Q = J1_q[0];


--R1L171 is reg_out:inst33|reg_data[15]~2733 at LC4_I22
--operation mode is normal

R1L171 = sel[0] & reg_sel[3];

--R1L871 is reg_out:inst33|reg_data[15]~2870 at LC4_I22
--operation mode is normal

R1L871 = sel[0] & reg_sel[3];


--R1L271 is reg_out:inst33|reg_data[15]~2734 at LC3_I22
--operation mode is normal

R1L271 = sel[1] & R1L171 & reg_sel[2] & reg_sel[1];

--R1L971 is reg_out:inst33|reg_data[15]~2871 at LC3_I22
--operation mode is normal

R1L971 = sel[1] & R1L171 & reg_sel[2] & reg_sel[1];


--G1_q[15] is ir:inst7|q[15] at LC4_H20
--operation mode is normal

G1_q[15]_lut_out = A1L73;
G1_q[15] = DFFEA(G1_q[15]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L53Q is ir:inst7|q[15]~274 at LC4_H20
--operation mode is normal

G1L53Q = G1_q[15];


--K1_q[15] is pc:inst10|q[15] at LC3_G30
--operation mode is normal

K1_q[15]_lut_out = B1L251;
K1_q[15] = DFFEA(K1_q[15]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L33Q is pc:inst10|q[15]~94 at LC3_G30
--operation mode is normal

K1L33Q = K1_q[15];


--R1L371 is reg_out:inst33|reg_data[15]~2735 at LC3_G37
--operation mode is normal

R1L371 = R1L271 & (reg_sel[0] & (G1_q[15]) # !reg_sel[0] & K1_q[15]);

--R1L081 is reg_out:inst33|reg_data[15]~2872 at LC3_G37
--operation mode is normal

R1L081 = R1L271 & (reg_sel[0] & (G1_q[15]) # !reg_sel[0] & K1_q[15]);


--L21_q[15] is reg:inst23|q[15] at LC3_K26
--operation mode is normal

L21_q[15]_lut_out = B1L251;
L21_q[15] = DFFEA(L21_q[15]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L33Q is reg:inst23|q[15]~94 at LC3_K26
--operation mode is normal

L21L33Q = L21_q[15];


--L01_q[15] is reg:inst21|q[15] at LC1_K19
--operation mode is normal

L01_q[15]_lut_out = B1L251;
L01_q[15] = DFFEA(L01_q[15]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L33Q is reg:inst21|q[15]~94 at LC1_K19
--operation mode is normal

L01L33Q = L01_q[15];


--L8_q[15] is reg:inst19|q[15] at LC1_K31
--operation mode is normal

L8_q[15]_lut_out = B1L251;
L8_q[15] = DFFEA(L8_q[15]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L33Q is reg:inst19|q[15]~94 at LC1_K31
--operation mode is normal

L8L33Q = L8_q[15];


--M1L586 is reg_mux:inst27|reg_out[15]~336 at LC5_K19
--operation mode is normal

M1L586 = reg_sel[1] & (L01_q[15] # reg_sel[2]) # !reg_sel[1] & L8_q[15] & (!reg_sel[2]);

--M1L596 is reg_mux:inst27|reg_out[15]~496 at LC5_K19
--operation mode is normal

M1L596 = reg_sel[1] & (L01_q[15] # reg_sel[2]) # !reg_sel[1] & L8_q[15] & (!reg_sel[2]);


--L41_q[15] is reg:inst25|q[15] at LC2_K26
--operation mode is normal

L41_q[15]_lut_out = B1L251;
L41_q[15] = DFFEA(L41_q[15]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L33Q is reg:inst25|q[15]~94 at LC2_K26
--operation mode is normal

L41L33Q = L41_q[15];


--M1L686 is reg_mux:inst27|reg_out[15]~337 at LC5_K26
--operation mode is normal

M1L686 = M1L586 & (L41_q[15] # !reg_sel[2]) # !M1L586 & (reg_sel[2] & L21_q[15]);

--M1L696 is reg_mux:inst27|reg_out[15]~497 at LC5_K26
--operation mode is normal

M1L696 = M1L586 & (L41_q[15] # !reg_sel[2]) # !M1L586 & (reg_sel[2] & L21_q[15]);


--L5_q[15] is reg:inst16|q[15] at LC2_K25
--operation mode is normal

L5_q[15]_lut_out = B1L251;
L5_q[15] = DFFEA(L5_q[15]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L33Q is reg:inst16|q[15]~94 at LC2_K25
--operation mode is normal

L5L33Q = L5_q[15];


--L3_q[15] is reg:inst14|q[15] at LC1_K29
--operation mode is normal

L3_q[15]_lut_out = B1L251;
L3_q[15] = DFFEA(L3_q[15]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L33Q is reg:inst14|q[15]~94 at LC1_K29
--operation mode is normal

L3L33Q = L3_q[15];


--L1_q[15] is reg:inst12|q[15] at LC4_K18
--operation mode is normal

L1_q[15]_lut_out = B1L251;
L1_q[15] = DFFEA(L1_q[15]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L33Q is reg:inst12|q[15]~94 at LC4_K18
--operation mode is normal

L1L33Q = L1_q[15];


--M1L786 is reg_mux:inst27|reg_out[15]~338 at LC5_K25
--operation mode is normal

M1L786 = reg_sel[1] & (L3_q[15] # reg_sel[2]) # !reg_sel[1] & L1_q[15] & (!reg_sel[2]);

--M1L796 is reg_mux:inst27|reg_out[15]~498 at LC5_K25
--operation mode is normal

M1L796 = reg_sel[1] & (L3_q[15] # reg_sel[2]) # !reg_sel[1] & L1_q[15] & (!reg_sel[2]);


--L7_q[15] is reg:inst18|q[15] at LC2_K27
--operation mode is normal

L7_q[15]_lut_out = B1L251;
L7_q[15] = DFFEA(L7_q[15]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L33Q is reg:inst18|q[15]~94 at LC2_K27
--operation mode is normal

L7L33Q = L7_q[15];


--M1L886 is reg_mux:inst27|reg_out[15]~339 at LC6_K25
--operation mode is normal

M1L886 = M1L786 & (L7_q[15] # !reg_sel[2]) # !M1L786 & (reg_sel[2] & L5_q[15]);

--M1L896 is reg_mux:inst27|reg_out[15]~499 at LC6_K25
--operation mode is normal

M1L896 = M1L786 & (L7_q[15] # !reg_sel[2]) # !M1L786 & (reg_sel[2] & L5_q[15]);


--L4_q[15] is reg:inst15|q[15] at LC1_K25
--operation mode is normal

L4_q[15]_lut_out = B1L251;
L4_q[15] = DFFEA(L4_q[15]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L33Q is reg:inst15|q[15]~94 at LC1_K25
--operation mode is normal

L4L33Q = L4_q[15];


--L2_q[15] is reg:inst13|q[15] at LC3_K25
--operation mode is normal

L2_q[15]_lut_out = B1L251;
L2_q[15] = DFFEA(L2_q[15]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L33Q is reg:inst13|q[15]~94 at LC3_K25
--operation mode is normal

L2L33Q = L2_q[15];


--L61_q[15] is reg:inst30|q[15] at LC2_K18
--operation mode is normal

L61_q[15]_lut_out = B1L251;
L61_q[15] = DFFEA(L61_q[15]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L33Q is reg:inst30|q[15]~94 at LC2_K18
--operation mode is normal

L61L33Q = L61_q[15];


--M1L986 is reg_mux:inst27|reg_out[15]~340 at LC7_K25
--operation mode is normal

M1L986 = reg_sel[1] & (L2_q[15] # reg_sel[2]) # !reg_sel[1] & L61_q[15] & (!reg_sel[2]);

--M1L996 is reg_mux:inst27|reg_out[15]~500 at LC7_K25
--operation mode is normal

M1L996 = reg_sel[1] & (L2_q[15] # reg_sel[2]) # !reg_sel[1] & L61_q[15] & (!reg_sel[2]);


--L6_q[15] is reg:inst17|q[15] at LC3_G27
--operation mode is normal

L6_q[15]_lut_out = B1L251;
L6_q[15] = DFFEA(L6_q[15]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L33Q is reg:inst17|q[15]~94 at LC3_G27
--operation mode is normal

L6L33Q = L6_q[15];


--M1L096 is reg_mux:inst27|reg_out[15]~341 at LC8_K25
--operation mode is normal

M1L096 = M1L986 & (L6_q[15] # !reg_sel[2]) # !M1L986 & (reg_sel[2] & L4_q[15]);

--M1L007 is reg_mux:inst27|reg_out[15]~501 at LC8_K25
--operation mode is normal

M1L007 = M1L986 & (L6_q[15] # !reg_sel[2]) # !M1L986 & (reg_sel[2] & L4_q[15]);


--M1L196 is reg_mux:inst27|reg_out[15]~342 at LC4_K25
--operation mode is normal

M1L196 = reg_sel[0] & (M1L886 # reg_sel[3]) # !reg_sel[0] & M1L096 & (!reg_sel[3]);

--M1L107 is reg_mux:inst27|reg_out[15]~502 at LC4_K25
--operation mode is normal

M1L107 = reg_sel[0] & (M1L886 # reg_sel[3]) # !reg_sel[0] & M1L096 & (!reg_sel[3]);


--L31_q[15] is reg:inst24|q[15] at LC4_K26
--operation mode is normal

L31_q[15]_lut_out = B1L251;
L31_q[15] = DFFEA(L31_q[15]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L33Q is reg:inst24|q[15]~94 at LC4_K26
--operation mode is normal

L31L33Q = L31_q[15];


--L11_q[15] is reg:inst22|q[15] at LC4_G27
--operation mode is normal

L11_q[15]_lut_out = B1L251;
L11_q[15] = DFFEA(L11_q[15]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L33Q is reg:inst22|q[15]~94 at LC4_G27
--operation mode is normal

L11L33Q = L11_q[15];


--L9_q[15] is reg:inst20|q[15] at LC3_K19
--operation mode is normal

L9_q[15]_lut_out = B1L251;
L9_q[15] = DFFEA(L9_q[15]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L33Q is reg:inst20|q[15]~94 at LC3_K19
--operation mode is normal

L9L33Q = L9_q[15];


--M1L296 is reg_mux:inst27|reg_out[15]~343 at LC4_K19
--operation mode is normal

M1L296 = reg_sel[1] & (L11_q[15] # reg_sel[2]) # !reg_sel[1] & L9_q[15] & (!reg_sel[2]);

--M1L207 is reg_mux:inst27|reg_out[15]~503 at LC4_K19
--operation mode is normal

M1L207 = reg_sel[1] & (L11_q[15] # reg_sel[2]) # !reg_sel[1] & L9_q[15] & (!reg_sel[2]);


--L51_q[15] is reg:inst26|q[15] at LC4_K30
--operation mode is normal

L51_q[15]_lut_out = B1L251;
L51_q[15] = DFFEA(L51_q[15]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L33Q is reg:inst26|q[15]~94 at LC4_K30
--operation mode is normal

L51L33Q = L51_q[15];


--M1L396 is reg_mux:inst27|reg_out[15]~344 at LC6_K26
--operation mode is normal

M1L396 = M1L296 & (L51_q[15] # !reg_sel[2]) # !M1L296 & (reg_sel[2] & L31_q[15]);

--M1L307 is reg_mux:inst27|reg_out[15]~504 at LC6_K26
--operation mode is normal

M1L307 = M1L296 & (L51_q[15] # !reg_sel[2]) # !M1L296 & (reg_sel[2] & L31_q[15]);


--M1L496 is reg_mux:inst27|reg_out[15]~345 at LC7_K26
--operation mode is normal

M1L496 = M1L196 & (M1L396 # !reg_sel[3]) # !M1L196 & (reg_sel[3] & M1L686);

--M1L407 is reg_mux:inst27|reg_out[15]~505 at LC7_K26
--operation mode is normal

M1L407 = M1L196 & (M1L396 # !reg_sel[3]) # !M1L196 & (reg_sel[3] & M1L686);


--R1L471 is reg_out:inst33|reg_data[15]~2736 at LC4_G37
--operation mode is normal

R1L471 = R1L371 # !sel[1] & !sel[0] & M1L496;

--R1L181 is reg_out:inst33|reg_data[15]~2873 at LC4_G37
--operation mode is normal

R1L181 = R1L371 # !sel[1] & !sel[0] & M1L496;


--N1L951 is bus_mux:inst28|alu_sr[15]~635 at LC8_G16
--operation mode is normal

N1L951 = !H1_alu_in_sel[2] & H1_alu_in_sel[1] & H1_alu_in_sel[0] & H1_offset[7];

--N1L261 is bus_mux:inst28|alu_sr[15]~653 at LC8_G16
--operation mode is normal

N1L261 = !H1_alu_in_sel[2] & H1_alu_in_sel[1] & H1_alu_in_sel[0] & H1_offset[7];


--M1L5001 is reg_mux:inst27|sr[15]~336 at LC6_K19
--operation mode is normal

M1L5001 = H1_sour_reg[0] & (L9_q[15] # H1_sour_reg[1]) # !H1_sour_reg[0] & L8_q[15] & (!H1_sour_reg[1]);

--M1L5101 is reg_mux:inst27|sr[15]~496 at LC6_K19
--operation mode is normal

M1L5101 = H1_sour_reg[0] & (L9_q[15] # H1_sour_reg[1]) # !H1_sour_reg[0] & L8_q[15] & (!H1_sour_reg[1]);


--M1L6001 is reg_mux:inst27|sr[15]~337 at LC8_K19
--operation mode is normal

M1L6001 = M1L5001 & (L11_q[15] # !H1_sour_reg[1]) # !M1L5001 & (H1_sour_reg[1] & L01_q[15]);

--M1L6101 is reg_mux:inst27|sr[15]~497 at LC8_K19
--operation mode is normal

M1L6101 = M1L5001 & (L11_q[15] # !H1_sour_reg[1]) # !M1L5001 & (H1_sour_reg[1] & L01_q[15]);


--M1L7001 is reg_mux:inst27|sr[15]~338 at LC1_K11
--operation mode is normal

M1L7001 = H1_sour_reg[1] & (L6_q[15] # H1_sour_reg[0]) # !H1_sour_reg[1] & L4_q[15] & (!H1_sour_reg[0]);

--M1L7101 is reg_mux:inst27|sr[15]~498 at LC1_K11
--operation mode is normal

M1L7101 = H1_sour_reg[1] & (L6_q[15] # H1_sour_reg[0]) # !H1_sour_reg[1] & L4_q[15] & (!H1_sour_reg[0]);


--M1L8001 is reg_mux:inst27|sr[15]~339 at LC2_K11
--operation mode is normal

M1L8001 = M1L7001 & (L7_q[15] # !H1_sour_reg[0]) # !M1L7001 & (H1_sour_reg[0] & L5_q[15]);

--M1L8101 is reg_mux:inst27|sr[15]~499 at LC2_K11
--operation mode is normal

M1L8101 = M1L7001 & (L7_q[15] # !H1_sour_reg[0]) # !M1L7001 & (H1_sour_reg[0] & L5_q[15]);


--M1L9001 is reg_mux:inst27|sr[15]~340 at LC7_K18
--operation mode is normal

M1L9001 = H1_sour_reg[0] & (L1_q[15] # H1_sour_reg[1]) # !H1_sour_reg[0] & L61_q[15] & (!H1_sour_reg[1]);

--M1L9101 is reg_mux:inst27|sr[15]~500 at LC7_K18
--operation mode is normal

M1L9101 = H1_sour_reg[0] & (L1_q[15] # H1_sour_reg[1]) # !H1_sour_reg[0] & L61_q[15] & (!H1_sour_reg[1]);


--M1L0101 is reg_mux:inst27|sr[15]~341 at LC3_K11
--operation mode is normal

M1L0101 = M1L9001 & (L3_q[15] # !H1_sour_reg[1]) # !M1L9001 & (H1_sour_reg[1] & L2_q[15]);

--M1L0201 is reg_mux:inst27|sr[15]~501 at LC3_K11
--operation mode is normal

M1L0201 = M1L9001 & (L3_q[15] # !H1_sour_reg[1]) # !M1L9001 & (H1_sour_reg[1] & L2_q[15]);


--M1L1101 is reg_mux:inst27|sr[15]~342 at LC4_K11
--operation mode is normal

M1L1101 = H1_sour_reg[2] & (M1L8001 # H1_sour_reg[3]) # !H1_sour_reg[2] & M1L0101 & (!H1_sour_reg[3]);

--M1L1201 is reg_mux:inst27|sr[15]~502 at LC4_K11
--operation mode is normal

M1L1201 = H1_sour_reg[2] & (M1L8001 # H1_sour_reg[3]) # !H1_sour_reg[2] & M1L0101 & (!H1_sour_reg[3]);


--M1L2101 is reg_mux:inst27|sr[15]~343 at LC5_K11
--operation mode is normal

M1L2101 = H1_sour_reg[1] & (L41_q[15] # H1_sour_reg[0]) # !H1_sour_reg[1] & L21_q[15] & (!H1_sour_reg[0]);

--M1L2201 is reg_mux:inst27|sr[15]~503 at LC5_K11
--operation mode is normal

M1L2201 = H1_sour_reg[1] & (L41_q[15] # H1_sour_reg[0]) # !H1_sour_reg[1] & L21_q[15] & (!H1_sour_reg[0]);


--M1L3101 is reg_mux:inst27|sr[15]~344 at LC6_K11
--operation mode is normal

M1L3101 = M1L2101 & (L51_q[15] # !H1_sour_reg[0]) # !M1L2101 & (H1_sour_reg[0] & L31_q[15]);

--M1L3201 is reg_mux:inst27|sr[15]~504 at LC6_K11
--operation mode is normal

M1L3201 = M1L2101 & (L51_q[15] # !H1_sour_reg[0]) # !M1L2101 & (H1_sour_reg[0] & L31_q[15]);


--M1L4101 is reg_mux:inst27|sr[15]~345 at LC8_K11
--operation mode is normal

M1L4101 = M1L1101 & (M1L3101 # !H1_sour_reg[3]) # !M1L1101 & (H1_sour_reg[3] & M1L6001);

--M1L4201 is reg_mux:inst27|sr[15]~505 at LC8_K11
--operation mode is normal

M1L4201 = M1L1101 & (M1L3101 # !H1_sour_reg[3]) # !M1L1101 & (H1_sour_reg[3] & M1L6001);


--N1L061 is bus_mux:inst28|alu_sr[15]~636 at LC7_K11
--operation mode is normal

N1L061 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L4101;

--N1L361 is bus_mux:inst28|alu_sr[15]~654 at LC7_K11
--operation mode is normal

N1L361 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L4101;


--R1L1 is reg_out:inst33|Mux~585 at LC5_G37
--operation mode is normal

R1L1 = reg_sel[1] & (reg_sel[0] # !N1L221) # !reg_sel[1] & H1_offset[7] & (!reg_sel[0]);

--R1L33 is reg_out:inst33|Mux~617 at LC5_G37
--operation mode is normal

R1L33 = reg_sel[1] & (reg_sel[0] # !N1L221) # !reg_sel[1] & H1_offset[7] & (!reg_sel[0]);


--B1L941 is alu:inst|alu_out[15]~5772 at LC5_G27
--operation mode is normal

B1L941 = H1_alu_func[0] & (H1_alu_func[1] # !T3_unreg_res_node[17]) # !H1_alu_func[0] & T1_unreg_res_node[16] & (!H1_alu_func[1]);

--B1L351 is alu:inst|alu_out[15]~5850 at LC5_G27
--operation mode is normal

B1L351 = H1_alu_func[0] & (H1_alu_func[1] # !T3_unreg_res_node[17]) # !H1_alu_func[0] & T1_unreg_res_node[16] & (!H1_alu_func[1]);


--B1L051 is alu:inst|alu_out[15]~5773 at LC6_G27
--operation mode is normal

B1L051 = H1_alu_func[1] & (B1L941 & (N1L061 # !N1L221) # !B1L941 & N1L061 & !N1L221) # !H1_alu_func[1] & B1L941;

--B1L451 is alu:inst|alu_out[15]~5851 at LC6_G27
--operation mode is normal

B1L451 = H1_alu_func[1] & (B1L941 & (N1L061 # !N1L221) # !B1L941 & N1L061 & !N1L221) # !H1_alu_func[1] & B1L941;


--N1L811 is bus_mux:inst28|alu_dr[15]~2293 at LC4_H21
--operation mode is normal

N1L811 = !H1_alu_in_sel[1] & H1_alu_in_sel[2];

--N1L321 is bus_mux:inst28|alu_dr[15]~2367 at LC4_H21
--operation mode is normal

N1L321 = !H1_alu_in_sel[1] & H1_alu_in_sel[2];


--K1_q[14] is pc:inst10|q[14] at LC4_F46
--operation mode is normal

K1_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
K1_q[14] = DFFEA(K1_q[14]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L13Q is pc:inst10|q[14]~95 at LC4_F46
--operation mode is normal

K1L13Q = K1_q[14];


--N1L011 is bus_mux:inst28|alu_dr[14]~2294 at LC2_F10
--operation mode is normal

N1L011 = N1L811 & (H1_alu_in_sel[0] & (A1L83) # !H1_alu_in_sel[0] & K1_q[14]);

--N1L411 is bus_mux:inst28|alu_dr[14]~2368 at LC2_F10
--operation mode is normal

N1L411 = N1L811 & (H1_alu_in_sel[0] & (A1L83) # !H1_alu_in_sel[0] & K1_q[14]);


--N1L111 is bus_mux:inst28|alu_dr[14]~2295 at LC3_F10
--operation mode is normal

N1L111 = !H1_alu_in_sel[2] & H1_alu_in_sel[1] & H1_alu_in_sel[0] & K1_q[14];

--N1L511 is bus_mux:inst28|alu_dr[14]~2369 at LC3_F10
--operation mode is normal

N1L511 = !H1_alu_in_sel[2] & H1_alu_in_sel[1] & H1_alu_in_sel[0] & K1_q[14];


--N1L911 is bus_mux:inst28|alu_dr[15]~2296 at LC1_E16
--operation mode is normal

N1L911 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2];

--N1L421 is bus_mux:inst28|alu_dr[15]~2370 at LC1_E16
--operation mode is normal

N1L421 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2];


--L6_q[14] is reg:inst17|q[14] at LC3_F11
--operation mode is normal

L6_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L6_q[14] = DFFEA(L6_q[14]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L13Q is reg:inst17|q[14]~95 at LC3_F11
--operation mode is normal

L6L13Q = L6_q[14];


--L01_q[14] is reg:inst21|q[14] at LC8_F20
--operation mode is normal

L01_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L01_q[14] = DFFEA(L01_q[14]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L13Q is reg:inst21|q[14]~95 at LC8_F20
--operation mode is normal

L01L13Q = L01_q[14];


--L2_q[14] is reg:inst13|q[14] at LC4_F11
--operation mode is normal

L2_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L2_q[14] = DFFEA(L2_q[14]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L13Q is reg:inst13|q[14]~95 at LC4_F11
--operation mode is normal

L2L13Q = L2_q[14];


--M1L182 is reg_mux:inst27|dr[14]~336 at LC5_F11
--operation mode is normal

M1L182 = H1_dest_reg[3] & (L01_q[14] # H1_dest_reg[2]) # !H1_dest_reg[3] & L2_q[14] & (!H1_dest_reg[2]);

--M1L192 is reg_mux:inst27|dr[14]~496 at LC5_F11
--operation mode is normal

M1L192 = H1_dest_reg[3] & (L01_q[14] # H1_dest_reg[2]) # !H1_dest_reg[3] & L2_q[14] & (!H1_dest_reg[2]);


--L41_q[14] is reg:inst25|q[14] at LC5_F9
--operation mode is normal

L41_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L41_q[14] = DFFEA(L41_q[14]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L13Q is reg:inst25|q[14]~95 at LC5_F9
--operation mode is normal

L41L13Q = L41_q[14];


--M1L282 is reg_mux:inst27|dr[14]~337 at LC1_F11
--operation mode is normal

M1L282 = M1L182 & (L41_q[14] # !H1_dest_reg[2]) # !M1L182 & (H1_dest_reg[2] & L6_q[14]);

--M1L292 is reg_mux:inst27|dr[14]~497 at LC1_F11
--operation mode is normal

M1L292 = M1L182 & (L41_q[14] # !H1_dest_reg[2]) # !M1L182 & (H1_dest_reg[2] & L6_q[14]);


--L9_q[14] is reg:inst20|q[14] at LC3_F27
--operation mode is normal

L9_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L9_q[14] = DFFEA(L9_q[14]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L13Q is reg:inst20|q[14]~95 at LC3_F27
--operation mode is normal

L9L13Q = L9_q[14];


--L5_q[14] is reg:inst16|q[14] at LC4_F9
--operation mode is normal

L5_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L5_q[14] = DFFEA(L5_q[14]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L13Q is reg:inst16|q[14]~95 at LC4_F9
--operation mode is normal

L5L13Q = L5_q[14];


--L1_q[14] is reg:inst12|q[14] at LC2_F20
--operation mode is normal

L1_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L1_q[14] = DFFEA(L1_q[14]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L13Q is reg:inst12|q[14]~95 at LC2_F20
--operation mode is normal

L1L13Q = L1_q[14];


--M1L382 is reg_mux:inst27|dr[14]~338 at LC4_F10
--operation mode is normal

M1L382 = H1_dest_reg[2] & (L5_q[14] # H1_dest_reg[3]) # !H1_dest_reg[2] & L1_q[14] & (!H1_dest_reg[3]);

--M1L392 is reg_mux:inst27|dr[14]~498 at LC4_F10
--operation mode is normal

M1L392 = H1_dest_reg[2] & (L5_q[14] # H1_dest_reg[3]) # !H1_dest_reg[2] & L1_q[14] & (!H1_dest_reg[3]);


--L31_q[14] is reg:inst24|q[14] at LC1_F20
--operation mode is normal

L31_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L31_q[14] = DFFEA(L31_q[14]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L13Q is reg:inst24|q[14]~95 at LC1_F20
--operation mode is normal

L31L13Q = L31_q[14];


--M1L482 is reg_mux:inst27|dr[14]~339 at LC5_F10
--operation mode is normal

M1L482 = M1L382 & (L31_q[14] # !H1_dest_reg[3]) # !M1L382 & (H1_dest_reg[3] & L9_q[14]);

--M1L492 is reg_mux:inst27|dr[14]~499 at LC5_F10
--operation mode is normal

M1L492 = M1L382 & (L31_q[14] # !H1_dest_reg[3]) # !M1L382 & (H1_dest_reg[3] & L9_q[14]);


--L4_q[14] is reg:inst15|q[14] at LC6_F9
--operation mode is normal

L4_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L4_q[14] = DFFEA(L4_q[14]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L13Q is reg:inst15|q[14]~95 at LC6_F9
--operation mode is normal

L4L13Q = L4_q[14];


--L8_q[14] is reg:inst19|q[14] at LC1_F9
--operation mode is normal

L8_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L8_q[14] = DFFEA(L8_q[14]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L13Q is reg:inst19|q[14]~95 at LC1_F9
--operation mode is normal

L8L13Q = L8_q[14];


--L61_q[14] is reg:inst30|q[14] at LC2_F9
--operation mode is normal

L61_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L61_q[14] = DFFEA(L61_q[14]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L13Q is reg:inst30|q[14]~95 at LC2_F9
--operation mode is normal

L61L13Q = L61_q[14];


--M1L582 is reg_mux:inst27|dr[14]~340 at LC1_F12
--operation mode is normal

M1L582 = H1_dest_reg[3] & (L8_q[14] # H1_dest_reg[2]) # !H1_dest_reg[3] & L61_q[14] & (!H1_dest_reg[2]);

--M1L592 is reg_mux:inst27|dr[14]~500 at LC1_F12
--operation mode is normal

M1L592 = H1_dest_reg[3] & (L8_q[14] # H1_dest_reg[2]) # !H1_dest_reg[3] & L61_q[14] & (!H1_dest_reg[2]);


--L21_q[14] is reg:inst23|q[14] at LC5_F20
--operation mode is normal

L21_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L21_q[14] = DFFEA(L21_q[14]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L13Q is reg:inst23|q[14]~95 at LC5_F20
--operation mode is normal

L21L13Q = L21_q[14];


--M1L682 is reg_mux:inst27|dr[14]~341 at LC3_F12
--operation mode is normal

M1L682 = M1L582 & (L21_q[14] # !H1_dest_reg[2]) # !M1L582 & (H1_dest_reg[2] & L4_q[14]);

--M1L692 is reg_mux:inst27|dr[14]~501 at LC3_F12
--operation mode is normal

M1L692 = M1L582 & (L21_q[14] # !H1_dest_reg[2]) # !M1L582 & (H1_dest_reg[2] & L4_q[14]);


--M1L782 is reg_mux:inst27|dr[14]~342 at LC7_F10
--operation mode is normal

M1L782 = H1_dest_reg[0] & (M1L482 # H1_dest_reg[1]) # !H1_dest_reg[0] & M1L682 & (!H1_dest_reg[1]);

--M1L792 is reg_mux:inst27|dr[14]~502 at LC7_F10
--operation mode is normal

M1L792 = H1_dest_reg[0] & (M1L482 # H1_dest_reg[1]) # !H1_dest_reg[0] & M1L682 & (!H1_dest_reg[1]);


--L11_q[14] is reg:inst22|q[14] at LC2_F7
--operation mode is normal

L11_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L11_q[14] = DFFEA(L11_q[14]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L13Q is reg:inst22|q[14]~95 at LC2_F7
--operation mode is normal

L11L13Q = L11_q[14];


--L7_q[14] is reg:inst18|q[14] at LC6_F20
--operation mode is normal

L7_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L7_q[14] = DFFEA(L7_q[14]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L13Q is reg:inst18|q[14]~95 at LC6_F20
--operation mode is normal

L7L13Q = L7_q[14];


--L3_q[14] is reg:inst14|q[14] at LC3_F20
--operation mode is normal

L3_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L3_q[14] = DFFEA(L3_q[14]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L13Q is reg:inst14|q[14]~95 at LC3_F20
--operation mode is normal

L3L13Q = L3_q[14];


--M1L882 is reg_mux:inst27|dr[14]~343 at LC3_F7
--operation mode is normal

M1L882 = H1_dest_reg[2] & (L7_q[14] # H1_dest_reg[3]) # !H1_dest_reg[2] & L3_q[14] & (!H1_dest_reg[3]);

--M1L892 is reg_mux:inst27|dr[14]~503 at LC3_F7
--operation mode is normal

M1L892 = H1_dest_reg[2] & (L7_q[14] # H1_dest_reg[3]) # !H1_dest_reg[2] & L3_q[14] & (!H1_dest_reg[3]);


--L51_q[14] is reg:inst26|q[14] at LC5_F7
--operation mode is normal

L51_q[14]_lut_out = H1_alu_func[2] & B1L041 # !H1_alu_func[2] & (B1L241);
L51_q[14] = DFFEA(L51_q[14]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L13Q is reg:inst26|q[14]~95 at LC5_F7
--operation mode is normal

L51L13Q = L51_q[14];


--M1L982 is reg_mux:inst27|dr[14]~344 at LC4_F7
--operation mode is normal

M1L982 = M1L882 & (L51_q[14] # !H1_dest_reg[3]) # !M1L882 & (H1_dest_reg[3] & L11_q[14]);

--M1L992 is reg_mux:inst27|dr[14]~504 at LC4_F7
--operation mode is normal

M1L992 = M1L882 & (L51_q[14] # !H1_dest_reg[3]) # !M1L882 & (H1_dest_reg[3] & L11_q[14]);


--M1L092 is reg_mux:inst27|dr[14]~345 at LC8_F10
--operation mode is normal

M1L092 = M1L782 & (M1L982 # !H1_dest_reg[1]) # !M1L782 & (H1_dest_reg[1] & M1L282);

--M1L003 is reg_mux:inst27|dr[14]~505 at LC8_F10
--operation mode is normal

M1L003 = M1L782 & (M1L982 # !H1_dest_reg[1]) # !M1L782 & (H1_dest_reg[1] & M1L282);


--N1L211 is bus_mux:inst28|alu_dr[14]~2297 at LC6_F10
--operation mode is normal

N1L211 = N1L111 # N1L011 # M1L092 & N1L911;

--N1L611 is bus_mux:inst28|alu_dr[14]~2371 at LC6_F10
--operation mode is normal

N1L611 = N1L111 # N1L011 # M1L092 & N1L911;


--B1L151 is alu:inst|alu_out[15]~5774 at LC7_G27
--operation mode is normal

B1L151 = H1_alu_func[0] & (N1L211) # !H1_alu_func[0] & (N1L221 $ !N1L061);

--B1L551 is alu:inst|alu_out[15]~5852 at LC7_G27
--operation mode is normal

B1L551 = H1_alu_func[0] & (N1L211) # !H1_alu_func[0] & (N1L221 $ !N1L061);


--B1L251 is alu:inst|alu_out[15]~5775 at LC1_G27
--operation mode is normal

B1L251 = H1_alu_func[2] & !H1_alu_func[1] & B1L151 # !H1_alu_func[2] & (B1L051);

--B1L651 is alu:inst|alu_out[15]~5853 at LC1_G27
--operation mode is normal

B1L651 = H1_alu_func[2] & !H1_alu_func[1] & B1L151 # !H1_alu_func[2] & (B1L051);


--R1L2 is reg_out:inst33|Mux~586 at LC6_G37
--operation mode is normal

R1L2 = R1L1 & (B1L251 # !reg_sel[0]) # !R1L1 & (reg_sel[0] & N1L061);

--R1L43 is reg_out:inst33|Mux~618 at LC6_G37
--operation mode is normal

R1L43 = R1L1 & (B1L251 # !reg_sel[0]) # !R1L1 & (reg_sel[0] & N1L061);


--R1L571 is reg_out:inst33|reg_data[15]~2737 at LC2_I22
--operation mode is normal

R1L571 = !sel[1] & !reg_sel[3] & !reg_sel[2] & sel[0];

--R1L281 is reg_out:inst33|reg_data[15]~2874 at LC2_I22
--operation mode is normal

R1L281 = !sel[1] & !reg_sel[3] & !reg_sel[2] & sel[0];


--R1L671 is reg_out:inst33|reg_data[15]~2738 at LC1_G37
--operation mode is normal

R1L671 = R1L471 # R1L571 & R1L2;

--R1L381 is reg_out:inst33|reg_data[15]~2875 at LC1_G37
--operation mode is normal

R1L381 = R1L471 # R1L571 & R1L2;


--G1_q[11] is ir:inst7|q[11] at LC3_H19
--operation mode is normal

G1_q[11]_lut_out = A1L14;
G1_q[11] = DFFEA(G1_q[11]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L72Q is ir:inst7|q[11]~275 at LC3_H19
--operation mode is normal

G1L72Q = G1_q[11];


--K1_q[11] is pc:inst10|q[11] at LC2_F34
--operation mode is normal

K1_q[11]_lut_out = B1L311;
K1_q[11] = DFFEA(K1_q[11]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L52Q is pc:inst10|q[11]~96 at LC2_F34
--operation mode is normal

K1L52Q = K1_q[11];


--R1L241 is reg_out:inst33|reg_data[11]~2742 at LC1_F25
--operation mode is normal

R1L241 = R1L271 & (reg_sel[0] & (G1_q[11]) # !reg_sel[0] & K1_q[11]);

--R1L541 is reg_out:inst33|reg_data[11]~2876 at LC1_F25
--operation mode is normal

R1L541 = R1L271 & (reg_sel[0] & (G1_q[11]) # !reg_sel[0] & K1_q[11]);


--L21_q[11] is reg:inst23|q[11] at LC2_H39
--operation mode is normal

L21_q[11]_lut_out = B1L311;
L21_q[11] = DFFEA(L21_q[11]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L52Q is reg:inst23|q[11]~96 at LC2_H39
--operation mode is normal

L21L52Q = L21_q[11];


--L01_q[11] is reg:inst21|q[11] at LC4_H42
--operation mode is normal

L01_q[11]_lut_out = B1L311;
L01_q[11] = DFFEA(L01_q[11]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L52Q is reg:inst21|q[11]~96 at LC4_H42
--operation mode is normal

L01L52Q = L01_q[11];


--L8_q[11] is reg:inst19|q[11] at LC6_H52
--operation mode is normal

L8_q[11]_lut_out = B1L311;
L8_q[11] = DFFEA(L8_q[11]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L52Q is reg:inst19|q[11]~96 at LC6_H52
--operation mode is normal

L8L52Q = L8_q[11];


--M1L506 is reg_mux:inst27|reg_out[11]~346 at LC1_H42
--operation mode is normal

M1L506 = reg_sel[1] & (L01_q[11] # reg_sel[2]) # !reg_sel[1] & L8_q[11] & (!reg_sel[2]);

--M1L516 is reg_mux:inst27|reg_out[11]~506 at LC1_H42
--operation mode is normal

M1L516 = reg_sel[1] & (L01_q[11] # reg_sel[2]) # !reg_sel[1] & L8_q[11] & (!reg_sel[2]);


--L41_q[11] is reg:inst25|q[11] at LC4_F32
--operation mode is normal

L41_q[11]_lut_out = B1L311;
L41_q[11] = DFFEA(L41_q[11]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L52Q is reg:inst25|q[11]~96 at LC4_F32
--operation mode is normal

L41L52Q = L41_q[11];


--M1L606 is reg_mux:inst27|reg_out[11]~347 at LC3_H39
--operation mode is normal

M1L606 = M1L506 & (L41_q[11] # !reg_sel[2]) # !M1L506 & (reg_sel[2] & L21_q[11]);

--M1L616 is reg_mux:inst27|reg_out[11]~507 at LC3_H39
--operation mode is normal

M1L616 = M1L506 & (L41_q[11] # !reg_sel[2]) # !M1L506 & (reg_sel[2] & L21_q[11]);


--L5_q[11] is reg:inst16|q[11] at LC8_H46
--operation mode is normal

L5_q[11]_lut_out = B1L311;
L5_q[11] = DFFEA(L5_q[11]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L52Q is reg:inst16|q[11]~96 at LC8_H46
--operation mode is normal

L5L52Q = L5_q[11];


--L3_q[11] is reg:inst14|q[11] at LC2_H50
--operation mode is normal

L3_q[11]_lut_out = B1L311;
L3_q[11] = DFFEA(L3_q[11]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L52Q is reg:inst14|q[11]~96 at LC2_H50
--operation mode is normal

L3L52Q = L3_q[11];


--L1_q[11] is reg:inst12|q[11] at LC5_H40
--operation mode is normal

L1_q[11]_lut_out = B1L311;
L1_q[11] = DFFEA(L1_q[11]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L52Q is reg:inst12|q[11]~96 at LC5_H40
--operation mode is normal

L1L52Q = L1_q[11];


--M1L706 is reg_mux:inst27|reg_out[11]~348 at LC4_H40
--operation mode is normal

M1L706 = reg_sel[1] & (L3_q[11] # reg_sel[2]) # !reg_sel[1] & L1_q[11] & (!reg_sel[2]);

--M1L716 is reg_mux:inst27|reg_out[11]~508 at LC4_H40
--operation mode is normal

M1L716 = reg_sel[1] & (L3_q[11] # reg_sel[2]) # !reg_sel[1] & L1_q[11] & (!reg_sel[2]);


--L7_q[11] is reg:inst18|q[11] at LC1_E33
--operation mode is normal

L7_q[11]_lut_out = B1L311;
L7_q[11] = DFFEA(L7_q[11]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L52Q is reg:inst18|q[11]~96 at LC1_E33
--operation mode is normal

L7L52Q = L7_q[11];


--M1L806 is reg_mux:inst27|reg_out[11]~349 at LC1_H46
--operation mode is normal

M1L806 = M1L706 & (L7_q[11] # !reg_sel[2]) # !M1L706 & (reg_sel[2] & L5_q[11]);

--M1L816 is reg_mux:inst27|reg_out[11]~509 at LC1_H46
--operation mode is normal

M1L816 = M1L706 & (L7_q[11] # !reg_sel[2]) # !M1L706 & (reg_sel[2] & L5_q[11]);


--L4_q[11] is reg:inst15|q[11] at LC7_H46
--operation mode is normal

L4_q[11]_lut_out = B1L311;
L4_q[11] = DFFEA(L4_q[11]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L52Q is reg:inst15|q[11]~96 at LC7_H46
--operation mode is normal

L4L52Q = L4_q[11];


--L2_q[11] is reg:inst13|q[11] at LC7_H50
--operation mode is normal

L2_q[11]_lut_out = B1L311;
L2_q[11] = DFFEA(L2_q[11]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L52Q is reg:inst13|q[11]~96 at LC7_H50
--operation mode is normal

L2L52Q = L2_q[11];


--L61_q[11] is reg:inst30|q[11] at LC1_E31
--operation mode is normal

L61_q[11]_lut_out = B1L311;
L61_q[11] = DFFEA(L61_q[11]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L52Q is reg:inst30|q[11]~96 at LC1_E31
--operation mode is normal

L61L52Q = L61_q[11];


--M1L906 is reg_mux:inst27|reg_out[11]~350 at LC3_H40
--operation mode is normal

M1L906 = reg_sel[1] & (L2_q[11] # reg_sel[2]) # !reg_sel[1] & L61_q[11] & (!reg_sel[2]);

--M1L916 is reg_mux:inst27|reg_out[11]~510 at LC3_H40
--operation mode is normal

M1L916 = reg_sel[1] & (L2_q[11] # reg_sel[2]) # !reg_sel[1] & L61_q[11] & (!reg_sel[2]);


--L6_q[11] is reg:inst17|q[11] at LC6_H46
--operation mode is normal

L6_q[11]_lut_out = B1L311;
L6_q[11] = DFFEA(L6_q[11]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L52Q is reg:inst17|q[11]~96 at LC6_H46
--operation mode is normal

L6L52Q = L6_q[11];


--M1L016 is reg_mux:inst27|reg_out[11]~351 at LC2_H46
--operation mode is normal

M1L016 = M1L906 & (L6_q[11] # !reg_sel[2]) # !M1L906 & (reg_sel[2] & L4_q[11]);

--M1L026 is reg_mux:inst27|reg_out[11]~511 at LC2_H46
--operation mode is normal

M1L026 = M1L906 & (L6_q[11] # !reg_sel[2]) # !M1L906 & (reg_sel[2] & L4_q[11]);


--M1L116 is reg_mux:inst27|reg_out[11]~352 at LC3_H46
--operation mode is normal

M1L116 = reg_sel[0] & (M1L806 # reg_sel[3]) # !reg_sel[0] & M1L016 & (!reg_sel[3]);

--M1L126 is reg_mux:inst27|reg_out[11]~512 at LC3_H46
--operation mode is normal

M1L126 = reg_sel[0] & (M1L806 # reg_sel[3]) # !reg_sel[0] & M1L016 & (!reg_sel[3]);


--L31_q[11] is reg:inst24|q[11] at LC5_H52
--operation mode is normal

L31_q[11]_lut_out = B1L311;
L31_q[11] = DFFEA(L31_q[11]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L52Q is reg:inst24|q[11]~96 at LC5_H52
--operation mode is normal

L31L52Q = L31_q[11];


--L11_q[11] is reg:inst22|q[11] at LC5_H42
--operation mode is normal

L11_q[11]_lut_out = B1L311;
L11_q[11] = DFFEA(L11_q[11]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L52Q is reg:inst22|q[11]~96 at LC5_H42
--operation mode is normal

L11L52Q = L11_q[11];


--L9_q[11] is reg:inst20|q[11] at LC6_G46
--operation mode is normal

L9_q[11]_lut_out = B1L311;
L9_q[11] = DFFEA(L9_q[11]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L52Q is reg:inst20|q[11]~96 at LC6_G46
--operation mode is normal

L9L52Q = L9_q[11];


--M1L216 is reg_mux:inst27|reg_out[11]~353 at LC3_H42
--operation mode is normal

M1L216 = reg_sel[1] & (L11_q[11] # reg_sel[2]) # !reg_sel[1] & L9_q[11] & (!reg_sel[2]);

--M1L226 is reg_mux:inst27|reg_out[11]~513 at LC3_H42
--operation mode is normal

M1L226 = reg_sel[1] & (L11_q[11] # reg_sel[2]) # !reg_sel[1] & L9_q[11] & (!reg_sel[2]);


--L51_q[11] is reg:inst26|q[11] at LC2_G31
--operation mode is normal

L51_q[11]_lut_out = B1L311;
L51_q[11] = DFFEA(L51_q[11]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L52Q is reg:inst26|q[11]~96 at LC2_G31
--operation mode is normal

L51L52Q = L51_q[11];


--M1L316 is reg_mux:inst27|reg_out[11]~354 at LC4_H39
--operation mode is normal

M1L316 = M1L216 & (L51_q[11] # !reg_sel[2]) # !M1L216 & (reg_sel[2] & L31_q[11]);

--M1L326 is reg_mux:inst27|reg_out[11]~514 at LC4_H39
--operation mode is normal

M1L326 = M1L216 & (L51_q[11] # !reg_sel[2]) # !M1L216 & (reg_sel[2] & L31_q[11]);


--M1L416 is reg_mux:inst27|reg_out[11]~355 at LC8_H39
--operation mode is normal

M1L416 = M1L116 & (M1L316 # !reg_sel[3]) # !M1L116 & (reg_sel[3] & M1L606);

--M1L426 is reg_mux:inst27|reg_out[11]~515 at LC8_H39
--operation mode is normal

M1L426 = M1L116 & (M1L316 # !reg_sel[3]) # !M1L116 & (reg_sel[3] & M1L606);


--R1L341 is reg_out:inst33|reg_data[11]~2743 at LC2_F25
--operation mode is normal

R1L341 = R1L241 # !sel[1] & !sel[0] & M1L416;

--R1L641 is reg_out:inst33|reg_data[11]~2877 at LC2_F25
--operation mode is normal

R1L641 = R1L241 # !sel[1] & !sel[0] & M1L416;


--M1L529 is reg_mux:inst27|sr[11]~346 at LC6_H42
--operation mode is normal

M1L529 = H1_sour_reg[0] & (L9_q[11] # H1_sour_reg[1]) # !H1_sour_reg[0] & L8_q[11] & (!H1_sour_reg[1]);

--M1L539 is reg_mux:inst27|sr[11]~506 at LC6_H42
--operation mode is normal

M1L539 = H1_sour_reg[0] & (L9_q[11] # H1_sour_reg[1]) # !H1_sour_reg[0] & L8_q[11] & (!H1_sour_reg[1]);


--M1L629 is reg_mux:inst27|sr[11]~347 at LC7_H42
--operation mode is normal

M1L629 = M1L529 & (L11_q[11] # !H1_sour_reg[1]) # !M1L529 & (H1_sour_reg[1] & L01_q[11]);

--M1L639 is reg_mux:inst27|sr[11]~507 at LC7_H42
--operation mode is normal

M1L639 = M1L529 & (L11_q[11] # !H1_sour_reg[1]) # !M1L529 & (H1_sour_reg[1] & L01_q[11]);


--M1L729 is reg_mux:inst27|sr[11]~348 at LC4_H46
--operation mode is normal

M1L729 = H1_sour_reg[1] & (L6_q[11] # H1_sour_reg[0]) # !H1_sour_reg[1] & L4_q[11] & (!H1_sour_reg[0]);

--M1L739 is reg_mux:inst27|sr[11]~508 at LC4_H46
--operation mode is normal

M1L739 = H1_sour_reg[1] & (L6_q[11] # H1_sour_reg[0]) # !H1_sour_reg[1] & L4_q[11] & (!H1_sour_reg[0]);


--M1L829 is reg_mux:inst27|sr[11]~349 at LC5_H46
--operation mode is normal

M1L829 = M1L729 & (L7_q[11] # !H1_sour_reg[0]) # !M1L729 & (H1_sour_reg[0] & L5_q[11]);

--M1L839 is reg_mux:inst27|sr[11]~509 at LC5_H46
--operation mode is normal

M1L839 = M1L729 & (L7_q[11] # !H1_sour_reg[0]) # !M1L729 & (H1_sour_reg[0] & L5_q[11]);


--M1L929 is reg_mux:inst27|sr[11]~350 at LC6_H40
--operation mode is normal

M1L929 = H1_sour_reg[0] & (L1_q[11] # H1_sour_reg[1]) # !H1_sour_reg[0] & L61_q[11] & (!H1_sour_reg[1]);

--M1L939 is reg_mux:inst27|sr[11]~510 at LC6_H40
--operation mode is normal

M1L939 = H1_sour_reg[0] & (L1_q[11] # H1_sour_reg[1]) # !H1_sour_reg[0] & L61_q[11] & (!H1_sour_reg[1]);


--M1L039 is reg_mux:inst27|sr[11]~351 at LC7_H40
--operation mode is normal

M1L039 = M1L929 & (L3_q[11] # !H1_sour_reg[1]) # !M1L929 & (H1_sour_reg[1] & L2_q[11]);

--M1L049 is reg_mux:inst27|sr[11]~511 at LC7_H40
--operation mode is normal

M1L049 = M1L929 & (L3_q[11] # !H1_sour_reg[1]) # !M1L929 & (H1_sour_reg[1] & L2_q[11]);


--M1L139 is reg_mux:inst27|sr[11]~352 at LC8_H40
--operation mode is normal

M1L139 = H1_sour_reg[2] & (M1L829 # H1_sour_reg[3]) # !H1_sour_reg[2] & M1L039 & (!H1_sour_reg[3]);

--M1L149 is reg_mux:inst27|sr[11]~512 at LC8_H40
--operation mode is normal

M1L149 = H1_sour_reg[2] & (M1L829 # H1_sour_reg[3]) # !H1_sour_reg[2] & M1L039 & (!H1_sour_reg[3]);


--M1L239 is reg_mux:inst27|sr[11]~353 at LC5_H39
--operation mode is normal

M1L239 = H1_sour_reg[1] & (L41_q[11] # H1_sour_reg[0]) # !H1_sour_reg[1] & L21_q[11] & (!H1_sour_reg[0]);

--M1L249 is reg_mux:inst27|sr[11]~513 at LC5_H39
--operation mode is normal

M1L249 = H1_sour_reg[1] & (L41_q[11] # H1_sour_reg[0]) # !H1_sour_reg[1] & L21_q[11] & (!H1_sour_reg[0]);


--M1L339 is reg_mux:inst27|sr[11]~354 at LC6_H39
--operation mode is normal

M1L339 = M1L239 & (L51_q[11] # !H1_sour_reg[0]) # !M1L239 & (H1_sour_reg[0] & L31_q[11]);

--M1L349 is reg_mux:inst27|sr[11]~514 at LC6_H39
--operation mode is normal

M1L349 = M1L239 & (L51_q[11] # !H1_sour_reg[0]) # !M1L239 & (H1_sour_reg[0] & L31_q[11]);


--M1L439 is reg_mux:inst27|sr[11]~355 at LC1_H40
--operation mode is normal

M1L439 = M1L139 & (M1L339 # !H1_sour_reg[3]) # !M1L139 & (H1_sour_reg[3] & M1L629);

--M1L449 is reg_mux:inst27|sr[11]~515 at LC1_H40
--operation mode is normal

M1L449 = M1L139 & (M1L339 # !H1_sour_reg[3]) # !M1L139 & (H1_sour_reg[3] & M1L629);


--N1L151 is bus_mux:inst28|alu_sr[11]~637 at LC1_G16
--operation mode is normal

N1L151 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L439;

--N1L251 is bus_mux:inst28|alu_sr[11]~655 at LC1_G16
--operation mode is normal

N1L251 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L439;


--N1L68 is bus_mux:inst28|alu_dr[11]~2298 at LC5_H21
--operation mode is normal

N1L68 = N1L811 & (H1_alu_in_sel[0] & (A1L14) # !H1_alu_in_sel[0] & K1_q[11]);

--N1L09 is bus_mux:inst28|alu_dr[11]~2372 at LC5_H21
--operation mode is normal

N1L09 = N1L811 & (H1_alu_in_sel[0] & (A1L14) # !H1_alu_in_sel[0] & K1_q[11]);


--M1L122 is reg_mux:inst27|dr[11]~346 at LC8_H42
--operation mode is normal

M1L122 = H1_dest_reg[0] & (L9_q[11] # H1_dest_reg[1]) # !H1_dest_reg[0] & L8_q[11] & (!H1_dest_reg[1]);

--M1L132 is reg_mux:inst27|dr[11]~506 at LC8_H42
--operation mode is normal

M1L132 = H1_dest_reg[0] & (L9_q[11] # H1_dest_reg[1]) # !H1_dest_reg[0] & L8_q[11] & (!H1_dest_reg[1]);


--M1L222 is reg_mux:inst27|dr[11]~347 at LC2_H42
--operation mode is normal

M1L222 = M1L122 & (L11_q[11] # !H1_dest_reg[1]) # !M1L122 & (H1_dest_reg[1] & L01_q[11]);

--M1L232 is reg_mux:inst27|dr[11]~507 at LC2_H42
--operation mode is normal

M1L232 = M1L122 & (L11_q[11] # !H1_dest_reg[1]) # !M1L122 & (H1_dest_reg[1] & L01_q[11]);


--M1L322 is reg_mux:inst27|dr[11]~348 at LC2_H38
--operation mode is normal

M1L322 = H1_dest_reg[1] & (L6_q[11] # H1_dest_reg[0]) # !H1_dest_reg[1] & L4_q[11] & (!H1_dest_reg[0]);

--M1L332 is reg_mux:inst27|dr[11]~508 at LC2_H38
--operation mode is normal

M1L332 = H1_dest_reg[1] & (L6_q[11] # H1_dest_reg[0]) # !H1_dest_reg[1] & L4_q[11] & (!H1_dest_reg[0]);


--M1L422 is reg_mux:inst27|dr[11]~349 at LC3_H38
--operation mode is normal

M1L422 = M1L322 & (L7_q[11] # !H1_dest_reg[0]) # !M1L322 & (H1_dest_reg[0] & L5_q[11]);

--M1L432 is reg_mux:inst27|dr[11]~509 at LC3_H38
--operation mode is normal

M1L432 = M1L322 & (L7_q[11] # !H1_dest_reg[0]) # !M1L322 & (H1_dest_reg[0] & L5_q[11]);


--M1L522 is reg_mux:inst27|dr[11]~350 at LC2_H40
--operation mode is normal

M1L522 = H1_dest_reg[0] & (L1_q[11] # H1_dest_reg[1]) # !H1_dest_reg[0] & L61_q[11] & (!H1_dest_reg[1]);

--M1L532 is reg_mux:inst27|dr[11]~510 at LC2_H40
--operation mode is normal

M1L532 = H1_dest_reg[0] & (L1_q[11] # H1_dest_reg[1]) # !H1_dest_reg[0] & L61_q[11] & (!H1_dest_reg[1]);


--M1L622 is reg_mux:inst27|dr[11]~351 at LC5_H38
--operation mode is normal

M1L622 = M1L522 & (L3_q[11] # !H1_dest_reg[1]) # !M1L522 & (H1_dest_reg[1] & L2_q[11]);

--M1L632 is reg_mux:inst27|dr[11]~511 at LC5_H38
--operation mode is normal

M1L632 = M1L522 & (L3_q[11] # !H1_dest_reg[1]) # !M1L522 & (H1_dest_reg[1] & L2_q[11]);


--M1L722 is reg_mux:inst27|dr[11]~352 at LC6_H38
--operation mode is normal

M1L722 = H1_dest_reg[2] & (M1L422 # H1_dest_reg[3]) # !H1_dest_reg[2] & M1L622 & (!H1_dest_reg[3]);

--M1L732 is reg_mux:inst27|dr[11]~512 at LC6_H38
--operation mode is normal

M1L732 = H1_dest_reg[2] & (M1L422 # H1_dest_reg[3]) # !H1_dest_reg[2] & M1L622 & (!H1_dest_reg[3]);


--M1L822 is reg_mux:inst27|dr[11]~353 at LC7_H39
--operation mode is normal

M1L822 = H1_dest_reg[1] & (L41_q[11] # H1_dest_reg[0]) # !H1_dest_reg[1] & L21_q[11] & (!H1_dest_reg[0]);

--M1L832 is reg_mux:inst27|dr[11]~513 at LC7_H39
--operation mode is normal

M1L832 = H1_dest_reg[1] & (L41_q[11] # H1_dest_reg[0]) # !H1_dest_reg[1] & L21_q[11] & (!H1_dest_reg[0]);


--M1L922 is reg_mux:inst27|dr[11]~354 at LC1_H39
--operation mode is normal

M1L922 = M1L822 & (L51_q[11] # !H1_dest_reg[0]) # !M1L822 & (H1_dest_reg[0] & L31_q[11]);

--M1L932 is reg_mux:inst27|dr[11]~514 at LC1_H39
--operation mode is normal

M1L932 = M1L822 & (L51_q[11] # !H1_dest_reg[0]) # !M1L822 & (H1_dest_reg[0] & L31_q[11]);


--M1L032 is reg_mux:inst27|dr[11]~355 at LC7_H38
--operation mode is normal

M1L032 = M1L722 & (M1L922 # !H1_dest_reg[3]) # !M1L722 & (H1_dest_reg[3] & M1L222);

--M1L042 is reg_mux:inst27|dr[11]~515 at LC7_H38
--operation mode is normal

M1L042 = M1L722 & (M1L922 # !H1_dest_reg[3]) # !M1L722 & (H1_dest_reg[3] & M1L222);


--N1L78 is bus_mux:inst28|alu_dr[11]~2299 at LC8_H38
--operation mode is normal

N1L78 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L032;

--N1L19 is bus_mux:inst28|alu_dr[11]~2373 at LC8_H38
--operation mode is normal

N1L19 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L032;


--N1L021 is bus_mux:inst28|alu_dr[15]~2300 at LC6_H17
--operation mode is normal

N1L021 = !H1_alu_in_sel[2] & H1_alu_in_sel[1] & H1_alu_in_sel[0];

--N1L521 is bus_mux:inst28|alu_dr[15]~2374 at LC6_H17
--operation mode is normal

N1L521 = !H1_alu_in_sel[2] & H1_alu_in_sel[1] & H1_alu_in_sel[0];


--N1L88 is bus_mux:inst28|alu_dr[11]~2301 at LC4_H38
--operation mode is normal

N1L88 = N1L78 # N1L68 # K1_q[11] & N1L021;

--N1L29 is bus_mux:inst28|alu_dr[11]~2375 at LC4_H38
--operation mode is normal

N1L29 = N1L78 # N1L68 # K1_q[11] & N1L021;


--R1L3 is reg_out:inst33|Mux~587 at LC1_G32
--operation mode is normal

R1L3 = reg_sel[1] & (N1L88 # reg_sel[0]) # !reg_sel[1] & H1_offset[7] & (!reg_sel[0]);

--R1L53 is reg_out:inst33|Mux~619 at LC1_G32
--operation mode is normal

R1L53 = reg_sel[1] & (N1L88 # reg_sel[0]) # !reg_sel[1] & H1_offset[7] & (!reg_sel[0]);


--V9_cs_buffer[13] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC4_G13
--operation mode is arithmetic

V9_cs_buffer[13] = V6_cs_buffer[13] $ !V9_cout[12];

--V9L14 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~300 at LC4_G13
--operation mode is arithmetic

V9L14 = V6_cs_buffer[13] $ !V9_cout[12];

--V9_cout[13] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[13] at LC4_G13
--operation mode is arithmetic

V9_cout[13] = CARRY(V9_cout[12] # !V6_cs_buffer[13]);


--V3_cs_buffer[12] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] at LC1_G23
--operation mode is arithmetic

V3_cs_buffer[12] = N1L88 $ N1L151 $ V3_cout[11];

--V3L44 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~292 at LC1_G23
--operation mode is arithmetic

V3L44 = N1L88 $ N1L151 $ V3_cout[11];

--V3_cout[12] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[12] at LC1_G23
--operation mode is arithmetic

V3_cout[12] = CARRY(N1L88 & (N1L151 # V3_cout[11]) # !N1L88 & N1L151 & V3_cout[11]);


--B1L901 is alu:inst|alu_out[11]~5776 at LC2_G32
--operation mode is normal

B1L901 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[13]) # !H1_alu_func[0] & V3_cs_buffer[12] & (!H1_alu_func[1]);

--B1L411 is alu:inst|alu_out[11]~5854 at LC2_G32
--operation mode is normal

B1L411 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[13]) # !H1_alu_func[0] & V3_cs_buffer[12] & (!H1_alu_func[1]);


--B1L011 is alu:inst|alu_out[11]~5777 at LC3_G32
--operation mode is normal

B1L011 = H1_alu_func[1] & (B1L901 & (N1L88 # N1L151) # !B1L901 & N1L88 & N1L151) # !H1_alu_func[1] & B1L901;

--B1L511 is alu:inst|alu_out[11]~5855 at LC3_G32
--operation mode is normal

B1L511 = H1_alu_func[1] & (B1L901 & (N1L88 # N1L151) # !B1L901 & N1L88 & N1L151) # !H1_alu_func[1] & B1L901;


--B1L111 is alu:inst|alu_out[11]~5778 at LC5_G32
--operation mode is normal

B1L111 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L151 $ N1L88);

--B1L611 is alu:inst|alu_out[11]~5856 at LC5_G32
--operation mode is normal

B1L611 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L151 $ N1L88);


--K1_q[10] is pc:inst10|q[10] at LC3_D25
--operation mode is normal

K1_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
K1_q[10] = DFFEA(K1_q[10]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L32Q is pc:inst10|q[10]~97 at LC3_D25
--operation mode is normal

K1L32Q = K1_q[10];


--N1L87 is bus_mux:inst28|alu_dr[10]~2302 at LC3_G16
--operation mode is normal

N1L87 = N1L811 & (H1_alu_in_sel[0] & (A1L24) # !H1_alu_in_sel[0] & K1_q[10]);

--N1L28 is bus_mux:inst28|alu_dr[10]~2376 at LC3_G16
--operation mode is normal

N1L28 = N1L811 & (H1_alu_in_sel[0] & (A1L24) # !H1_alu_in_sel[0] & K1_q[10]);


--L6_q[10] is reg:inst17|q[10] at LC4_D31
--operation mode is normal

L6_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L6_q[10] = DFFEA(L6_q[10]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L32Q is reg:inst17|q[10]~97 at LC4_D31
--operation mode is normal

L6L32Q = L6_q[10];


--L01_q[10] is reg:inst21|q[10] at LC3_D11
--operation mode is normal

L01_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L01_q[10] = DFFEA(L01_q[10]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L32Q is reg:inst21|q[10]~97 at LC3_D11
--operation mode is normal

L01L32Q = L01_q[10];


--L2_q[10] is reg:inst13|q[10] at LC4_D11
--operation mode is normal

L2_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L2_q[10] = DFFEA(L2_q[10]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L32Q is reg:inst13|q[10]~97 at LC4_D11
--operation mode is normal

L2L32Q = L2_q[10];


--M1L102 is reg_mux:inst27|dr[10]~356 at LC6_D11
--operation mode is normal

M1L102 = H1_dest_reg[3] & (L01_q[10] # H1_dest_reg[2]) # !H1_dest_reg[3] & L2_q[10] & (!H1_dest_reg[2]);

--M1L112 is reg_mux:inst27|dr[10]~516 at LC6_D11
--operation mode is normal

M1L112 = H1_dest_reg[3] & (L01_q[10] # H1_dest_reg[2]) # !H1_dest_reg[3] & L2_q[10] & (!H1_dest_reg[2]);


--L41_q[10] is reg:inst25|q[10] at LC6_D18
--operation mode is normal

L41_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L41_q[10] = DFFEA(L41_q[10]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L32Q is reg:inst25|q[10]~97 at LC6_D18
--operation mode is normal

L41L32Q = L41_q[10];


--M1L202 is reg_mux:inst27|dr[10]~357 at LC1_D11
--operation mode is normal

M1L202 = M1L102 & (L41_q[10] # !H1_dest_reg[2]) # !M1L102 & (H1_dest_reg[2] & L6_q[10]);

--M1L212 is reg_mux:inst27|dr[10]~517 at LC1_D11
--operation mode is normal

M1L212 = M1L102 & (L41_q[10] # !H1_dest_reg[2]) # !M1L102 & (H1_dest_reg[2] & L6_q[10]);


--L9_q[10] is reg:inst20|q[10] at LC3_D18
--operation mode is normal

L9_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L9_q[10] = DFFEA(L9_q[10]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L32Q is reg:inst20|q[10]~97 at LC3_D18
--operation mode is normal

L9L32Q = L9_q[10];


--L5_q[10] is reg:inst16|q[10] at LC3_D31
--operation mode is normal

L5_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L5_q[10] = DFFEA(L5_q[10]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L32Q is reg:inst16|q[10]~97 at LC3_D31
--operation mode is normal

L5L32Q = L5_q[10];


--L1_q[10] is reg:inst12|q[10] at LC2_D18
--operation mode is normal

L1_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L1_q[10] = DFFEA(L1_q[10]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L32Q is reg:inst12|q[10]~97 at LC2_D18
--operation mode is normal

L1L32Q = L1_q[10];


--M1L302 is reg_mux:inst27|dr[10]~358 at LC3_D15
--operation mode is normal

M1L302 = H1_dest_reg[2] & (L5_q[10] # H1_dest_reg[3]) # !H1_dest_reg[2] & L1_q[10] & (!H1_dest_reg[3]);

--M1L312 is reg_mux:inst27|dr[10]~518 at LC3_D15
--operation mode is normal

M1L312 = H1_dest_reg[2] & (L5_q[10] # H1_dest_reg[3]) # !H1_dest_reg[2] & L1_q[10] & (!H1_dest_reg[3]);


--L31_q[10] is reg:inst24|q[10] at LC1_D18
--operation mode is normal

L31_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L31_q[10] = DFFEA(L31_q[10]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L32Q is reg:inst24|q[10]~97 at LC1_D18
--operation mode is normal

L31L32Q = L31_q[10];


--M1L402 is reg_mux:inst27|dr[10]~359 at LC4_D15
--operation mode is normal

M1L402 = M1L302 & (L31_q[10] # !H1_dest_reg[3]) # !M1L302 & (H1_dest_reg[3] & L9_q[10]);

--M1L412 is reg_mux:inst27|dr[10]~519 at LC4_D15
--operation mode is normal

M1L412 = M1L302 & (L31_q[10] # !H1_dest_reg[3]) # !M1L302 & (H1_dest_reg[3] & L9_q[10]);


--L4_q[10] is reg:inst15|q[10] at LC4_D18
--operation mode is normal

L4_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L4_q[10] = DFFEA(L4_q[10]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L32Q is reg:inst15|q[10]~97 at LC4_D18
--operation mode is normal

L4L32Q = L4_q[10];


--L8_q[10] is reg:inst19|q[10] at LC3_D14
--operation mode is normal

L8_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L8_q[10] = DFFEA(L8_q[10]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L32Q is reg:inst19|q[10]~97 at LC3_D14
--operation mode is normal

L8L32Q = L8_q[10];


--L61_q[10] is reg:inst30|q[10] at LC4_D14
--operation mode is normal

L61_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L61_q[10] = DFFEA(L61_q[10]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L32Q is reg:inst30|q[10]~97 at LC4_D14
--operation mode is normal

L61L32Q = L61_q[10];


--M1L502 is reg_mux:inst27|dr[10]~360 at LC2_D14
--operation mode is normal

M1L502 = H1_dest_reg[3] & (L8_q[10] # H1_dest_reg[2]) # !H1_dest_reg[3] & L61_q[10] & (!H1_dest_reg[2]);

--M1L512 is reg_mux:inst27|dr[10]~520 at LC2_D14
--operation mode is normal

M1L512 = H1_dest_reg[3] & (L8_q[10] # H1_dest_reg[2]) # !H1_dest_reg[3] & L61_q[10] & (!H1_dest_reg[2]);


--L21_q[10] is reg:inst23|q[10] at LC3_D23
--operation mode is normal

L21_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L21_q[10] = DFFEA(L21_q[10]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L32Q is reg:inst23|q[10]~97 at LC3_D23
--operation mode is normal

L21L32Q = L21_q[10];


--M1L602 is reg_mux:inst27|dr[10]~361 at LC5_D15
--operation mode is normal

M1L602 = M1L502 & (L21_q[10] # !H1_dest_reg[2]) # !M1L502 & (H1_dest_reg[2] & L4_q[10]);

--M1L612 is reg_mux:inst27|dr[10]~521 at LC5_D15
--operation mode is normal

M1L612 = M1L502 & (L21_q[10] # !H1_dest_reg[2]) # !M1L502 & (H1_dest_reg[2] & L4_q[10]);


--M1L702 is reg_mux:inst27|dr[10]~362 at LC6_D15
--operation mode is normal

M1L702 = H1_dest_reg[0] & (M1L402 # H1_dest_reg[1]) # !H1_dest_reg[0] & M1L602 & (!H1_dest_reg[1]);

--M1L712 is reg_mux:inst27|dr[10]~522 at LC6_D15
--operation mode is normal

M1L712 = H1_dest_reg[0] & (M1L402 # H1_dest_reg[1]) # !H1_dest_reg[0] & M1L602 & (!H1_dest_reg[1]);


--L11_q[10] is reg:inst22|q[10] at LC4_D13
--operation mode is normal

L11_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L11_q[10] = DFFEA(L11_q[10]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L32Q is reg:inst22|q[10]~97 at LC4_D13
--operation mode is normal

L11L32Q = L11_q[10];


--L7_q[10] is reg:inst18|q[10] at LC8_D18
--operation mode is normal

L7_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L7_q[10] = DFFEA(L7_q[10]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L32Q is reg:inst18|q[10]~97 at LC8_D18
--operation mode is normal

L7L32Q = L7_q[10];


--L3_q[10] is reg:inst14|q[10] at LC5_D13
--operation mode is normal

L3_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L3_q[10] = DFFEA(L3_q[10]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L32Q is reg:inst14|q[10]~97 at LC5_D13
--operation mode is normal

L3L32Q = L3_q[10];


--M1L802 is reg_mux:inst27|dr[10]~363 at LC6_D13
--operation mode is normal

M1L802 = H1_dest_reg[2] & (L7_q[10] # H1_dest_reg[3]) # !H1_dest_reg[2] & L3_q[10] & (!H1_dest_reg[3]);

--M1L812 is reg_mux:inst27|dr[10]~523 at LC6_D13
--operation mode is normal

M1L812 = H1_dest_reg[2] & (L7_q[10] # H1_dest_reg[3]) # !H1_dest_reg[2] & L3_q[10] & (!H1_dest_reg[3]);


--L51_q[10] is reg:inst26|q[10] at LC7_D31
--operation mode is normal

L51_q[10]_lut_out = H1_alu_func[2] & B1L001 # !H1_alu_func[2] & (B1L201);
L51_q[10] = DFFEA(L51_q[10]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L32Q is reg:inst26|q[10]~97 at LC7_D31
--operation mode is normal

L51L32Q = L51_q[10];


--M1L902 is reg_mux:inst27|dr[10]~364 at LC1_D13
--operation mode is normal

M1L902 = M1L802 & (L51_q[10] # !H1_dest_reg[3]) # !M1L802 & (H1_dest_reg[3] & L11_q[10]);

--M1L912 is reg_mux:inst27|dr[10]~524 at LC1_D13
--operation mode is normal

M1L912 = M1L802 & (L51_q[10] # !H1_dest_reg[3]) # !M1L802 & (H1_dest_reg[3] & L11_q[10]);


--M1L012 is reg_mux:inst27|dr[10]~365 at LC7_D15
--operation mode is normal

M1L012 = M1L702 & (M1L902 # !H1_dest_reg[1]) # !M1L702 & (H1_dest_reg[1] & M1L202);

--M1L022 is reg_mux:inst27|dr[10]~525 at LC7_D15
--operation mode is normal

M1L022 = M1L702 & (M1L902 # !H1_dest_reg[1]) # !M1L702 & (H1_dest_reg[1] & M1L202);


--N1L97 is bus_mux:inst28|alu_dr[10]~2303 at LC8_D15
--operation mode is normal

N1L97 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L012;

--N1L38 is bus_mux:inst28|alu_dr[10]~2377 at LC8_D15
--operation mode is normal

N1L38 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L012;


--N1L08 is bus_mux:inst28|alu_dr[10]~2304 at LC2_D15
--operation mode is normal

N1L08 = N1L97 # N1L87 # K1_q[10] & N1L021;

--N1L48 is bus_mux:inst28|alu_dr[10]~2378 at LC2_D15
--operation mode is normal

N1L48 = N1L97 # N1L87 # K1_q[10] & N1L021;


--K1_q[12] is pc:inst10|q[12] at LC7_E24
--operation mode is normal

K1_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
K1_q[12] = DFFEA(K1_q[12]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L72Q is pc:inst10|q[12]~98 at LC7_E24
--operation mode is normal

K1L72Q = K1_q[12];


--N1L49 is bus_mux:inst28|alu_dr[12]~2305 at LC5_E12
--operation mode is normal

N1L49 = N1L811 & (H1_alu_in_sel[0] & (A1L04) # !H1_alu_in_sel[0] & K1_q[12]);

--N1L89 is bus_mux:inst28|alu_dr[12]~2379 at LC5_E12
--operation mode is normal

N1L89 = N1L811 & (H1_alu_in_sel[0] & (A1L04) # !H1_alu_in_sel[0] & K1_q[12]);


--L5_q[12] is reg:inst16|q[12] at LC5_E24
--operation mode is normal

L5_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L5_q[12] = DFFEA(L5_q[12]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L72Q is reg:inst16|q[12]~98 at LC5_E24
--operation mode is normal

L5L72Q = L5_q[12];


--L9_q[12] is reg:inst20|q[12] at LC5_D18
--operation mode is normal

L9_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L9_q[12] = DFFEA(L9_q[12]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L72Q is reg:inst20|q[12]~98 at LC5_D18
--operation mode is normal

L9L72Q = L9_q[12];


--L1_q[12] is reg:inst12|q[12] at LC1_E24
--operation mode is normal

L1_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L1_q[12] = DFFEA(L1_q[12]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L72Q is reg:inst12|q[12]~98 at LC1_E24
--operation mode is normal

L1L72Q = L1_q[12];


--M1L142 is reg_mux:inst27|dr[12]~366 at LC2_E10
--operation mode is normal

M1L142 = H1_dest_reg[3] & (L9_q[12] # H1_dest_reg[2]) # !H1_dest_reg[3] & L1_q[12] & (!H1_dest_reg[2]);

--M1L152 is reg_mux:inst27|dr[12]~526 at LC2_E10
--operation mode is normal

M1L152 = H1_dest_reg[3] & (L9_q[12] # H1_dest_reg[2]) # !H1_dest_reg[3] & L1_q[12] & (!H1_dest_reg[2]);


--L31_q[12] is reg:inst24|q[12] at LC6_E24
--operation mode is normal

L31_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L31_q[12] = DFFEA(L31_q[12]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L72Q is reg:inst24|q[12]~98 at LC6_E24
--operation mode is normal

L31L72Q = L31_q[12];


--M1L242 is reg_mux:inst27|dr[12]~367 at LC1_E10
--operation mode is normal

M1L242 = M1L142 & (L31_q[12] # !H1_dest_reg[2]) # !M1L142 & (H1_dest_reg[2] & L5_q[12]);

--M1L252 is reg_mux:inst27|dr[12]~527 at LC1_E10
--operation mode is normal

M1L252 = M1L142 & (L31_q[12] # !H1_dest_reg[2]) # !M1L142 & (H1_dest_reg[2] & L5_q[12]);


--L01_q[12] is reg:inst21|q[12] at LC3_E24
--operation mode is normal

L01_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L01_q[12] = DFFEA(L01_q[12]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L72Q is reg:inst21|q[12]~98 at LC3_E24
--operation mode is normal

L01L72Q = L01_q[12];


--L6_q[12] is reg:inst17|q[12] at LC6_E26
--operation mode is normal

L6_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L6_q[12] = DFFEA(L6_q[12]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L72Q is reg:inst17|q[12]~98 at LC6_E26
--operation mode is normal

L6L72Q = L6_q[12];


--L2_q[12] is reg:inst13|q[12] at LC2_E36
--operation mode is normal

L2_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L2_q[12] = DFFEA(L2_q[12]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L72Q is reg:inst13|q[12]~98 at LC2_E36
--operation mode is normal

L2L72Q = L2_q[12];


--M1L342 is reg_mux:inst27|dr[12]~368 at LC1_E12
--operation mode is normal

M1L342 = H1_dest_reg[2] & (L6_q[12] # H1_dest_reg[3]) # !H1_dest_reg[2] & L2_q[12] & (!H1_dest_reg[3]);

--M1L352 is reg_mux:inst27|dr[12]~528 at LC1_E12
--operation mode is normal

M1L352 = H1_dest_reg[2] & (L6_q[12] # H1_dest_reg[3]) # !H1_dest_reg[2] & L2_q[12] & (!H1_dest_reg[3]);


--L41_q[12] is reg:inst25|q[12] at LC4_E24
--operation mode is normal

L41_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L41_q[12] = DFFEA(L41_q[12]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L72Q is reg:inst25|q[12]~98 at LC4_E24
--operation mode is normal

L41L72Q = L41_q[12];


--M1L442 is reg_mux:inst27|dr[12]~369 at LC2_E12
--operation mode is normal

M1L442 = M1L342 & (L41_q[12] # !H1_dest_reg[3]) # !M1L342 & (H1_dest_reg[3] & L01_q[12]);

--M1L452 is reg_mux:inst27|dr[12]~529 at LC2_E12
--operation mode is normal

M1L452 = M1L342 & (L41_q[12] # !H1_dest_reg[3]) # !M1L342 & (H1_dest_reg[3] & L01_q[12]);


--L8_q[12] is reg:inst19|q[12] at LC2_E26
--operation mode is normal

L8_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L8_q[12] = DFFEA(L8_q[12]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L72Q is reg:inst19|q[12]~98 at LC2_E26
--operation mode is normal

L8L72Q = L8_q[12];


--L4_q[12] is reg:inst15|q[12] at LC7_E26
--operation mode is normal

L4_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L4_q[12] = DFFEA(L4_q[12]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L72Q is reg:inst15|q[12]~98 at LC7_E26
--operation mode is normal

L4L72Q = L4_q[12];


--L61_q[12] is reg:inst30|q[12] at LC8_E26
--operation mode is normal

L61_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L61_q[12] = DFFEA(L61_q[12]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L72Q is reg:inst30|q[12]~98 at LC8_E26
--operation mode is normal

L61L72Q = L61_q[12];


--M1L542 is reg_mux:inst27|dr[12]~370 at LC3_E13
--operation mode is normal

M1L542 = H1_dest_reg[2] & (L4_q[12] # H1_dest_reg[3]) # !H1_dest_reg[2] & L61_q[12] & (!H1_dest_reg[3]);

--M1L552 is reg_mux:inst27|dr[12]~530 at LC3_E13
--operation mode is normal

M1L552 = H1_dest_reg[2] & (L4_q[12] # H1_dest_reg[3]) # !H1_dest_reg[2] & L61_q[12] & (!H1_dest_reg[3]);


--L21_q[12] is reg:inst23|q[12] at LC2_E24
--operation mode is normal

L21_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L21_q[12] = DFFEA(L21_q[12]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L72Q is reg:inst23|q[12]~98 at LC2_E24
--operation mode is normal

L21L72Q = L21_q[12];


--M1L642 is reg_mux:inst27|dr[12]~371 at LC1_E13
--operation mode is normal

M1L642 = M1L542 & (L21_q[12] # !H1_dest_reg[3]) # !M1L542 & (H1_dest_reg[3] & L8_q[12]);

--M1L652 is reg_mux:inst27|dr[12]~531 at LC1_E13
--operation mode is normal

M1L652 = M1L542 & (L21_q[12] # !H1_dest_reg[3]) # !M1L542 & (H1_dest_reg[3] & L8_q[12]);


--M1L742 is reg_mux:inst27|dr[12]~372 at LC4_E12
--operation mode is normal

M1L742 = H1_dest_reg[1] & (M1L442 # H1_dest_reg[0]) # !H1_dest_reg[1] & M1L642 & (!H1_dest_reg[0]);

--M1L752 is reg_mux:inst27|dr[12]~532 at LC4_E12
--operation mode is normal

M1L752 = H1_dest_reg[1] & (M1L442 # H1_dest_reg[0]) # !H1_dest_reg[1] & M1L642 & (!H1_dest_reg[0]);


--L7_q[12] is reg:inst18|q[12] at LC3_E6
--operation mode is normal

L7_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L7_q[12] = DFFEA(L7_q[12]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L72Q is reg:inst18|q[12]~98 at LC3_E6
--operation mode is normal

L7L72Q = L7_q[12];


--L11_q[12] is reg:inst22|q[12] at LC4_E6
--operation mode is normal

L11_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L11_q[12] = DFFEA(L11_q[12]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L72Q is reg:inst22|q[12]~98 at LC4_E6
--operation mode is normal

L11L72Q = L11_q[12];


--L3_q[12] is reg:inst14|q[12] at LC2_E6
--operation mode is normal

L3_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L3_q[12] = DFFEA(L3_q[12]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L72Q is reg:inst14|q[12]~98 at LC2_E6
--operation mode is normal

L3L72Q = L3_q[12];


--M1L842 is reg_mux:inst27|dr[12]~373 at LC1_E6
--operation mode is normal

M1L842 = H1_dest_reg[3] & (L11_q[12] # H1_dest_reg[2]) # !H1_dest_reg[3] & L3_q[12] & (!H1_dest_reg[2]);

--M1L852 is reg_mux:inst27|dr[12]~533 at LC1_E6
--operation mode is normal

M1L852 = H1_dest_reg[3] & (L11_q[12] # H1_dest_reg[2]) # !H1_dest_reg[3] & L3_q[12] & (!H1_dest_reg[2]);


--L51_q[12] is reg:inst26|q[12] at LC5_E6
--operation mode is normal

L51_q[12]_lut_out = H1_alu_func[2] & B1L021 # !H1_alu_func[2] & (B1L221);
L51_q[12] = DFFEA(L51_q[12]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L72Q is reg:inst26|q[12]~98 at LC5_E6
--operation mode is normal

L51L72Q = L51_q[12];


--M1L942 is reg_mux:inst27|dr[12]~374 at LC8_E6
--operation mode is normal

M1L942 = M1L842 & (L51_q[12] # !H1_dest_reg[2]) # !M1L842 & (H1_dest_reg[2] & L7_q[12]);

--M1L952 is reg_mux:inst27|dr[12]~534 at LC8_E6
--operation mode is normal

M1L952 = M1L842 & (L51_q[12] # !H1_dest_reg[2]) # !M1L842 & (H1_dest_reg[2] & L7_q[12]);


--M1L052 is reg_mux:inst27|dr[12]~375 at LC6_E12
--operation mode is normal

M1L052 = M1L742 & (M1L942 # !H1_dest_reg[0]) # !M1L742 & (H1_dest_reg[0] & M1L242);

--M1L062 is reg_mux:inst27|dr[12]~535 at LC6_E12
--operation mode is normal

M1L062 = M1L742 & (M1L942 # !H1_dest_reg[0]) # !M1L742 & (H1_dest_reg[0] & M1L242);


--N1L59 is bus_mux:inst28|alu_dr[12]~2306 at LC7_E12
--operation mode is normal

N1L59 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L052;

--N1L99 is bus_mux:inst28|alu_dr[12]~2380 at LC7_E12
--operation mode is normal

N1L99 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L052;


--N1L69 is bus_mux:inst28|alu_dr[12]~2307 at LC8_E12
--operation mode is normal

N1L69 = N1L59 # N1L49 # K1_q[12] & N1L021;

--N1L001 is bus_mux:inst28|alu_dr[12]~2381 at LC8_E12
--operation mode is normal

N1L001 = N1L59 # N1L49 # K1_q[12] & N1L021;


--B1L211 is alu:inst|alu_out[11]~5779 at LC6_G32
--operation mode is normal

B1L211 = H1_alu_func[0] & !H1_alu_func[1] & (N1L08) # !H1_alu_func[0] & H1_alu_func[1] & N1L69;

--B1L711 is alu:inst|alu_out[11]~5857 at LC6_G32
--operation mode is normal

B1L711 = H1_alu_func[0] & !H1_alu_func[1] & (N1L08) # !H1_alu_func[0] & H1_alu_func[1] & N1L69;


--B1L311 is alu:inst|alu_out[11]~5780 at LC4_G32
--operation mode is normal

B1L311 = H1_alu_func[2] & (B1L211 # B1L111) # !H1_alu_func[2] & (B1L011);

--B1L811 is alu:inst|alu_out[11]~5858 at LC4_G32
--operation mode is normal

B1L811 = H1_alu_func[2] & (B1L211 # B1L111) # !H1_alu_func[2] & (B1L011);


--R1L4 is reg_out:inst33|Mux~588 at LC8_G32
--operation mode is normal

R1L4 = R1L3 & (B1L311 # !reg_sel[0]) # !R1L3 & (reg_sel[0] & N1L151);

--R1L63 is reg_out:inst33|Mux~620 at LC8_G32
--operation mode is normal

R1L63 = R1L3 & (B1L311 # !reg_sel[0]) # !R1L3 & (reg_sel[0] & N1L151);


--R1L441 is reg_out:inst33|reg_data[11]~2744 at LC5_F25
--operation mode is normal

R1L441 = R1L341 # R1L4 & R1L571;

--R1L741 is reg_out:inst33|reg_data[11]~2878 at LC5_F25
--operation mode is normal

R1L741 = R1L341 # R1L4 & R1L571;


--F1_state.s5 is timer:inst6|state.s5 at LC8_H25
--operation mode is normal

F1_state.s5_lut_out = F1_state.s4;
F1_state.s5 = DFFEA(F1_state.s5_lut_out, GLOBAL(clk), reset, , , , );

--F1L91Q is timer:inst6|state.s5~29 at LC8_H25
--operation mode is normal

F1L91Q = F1_state.s5;


--F1_state.s3 is timer:inst6|state.s3 at LC8_H26
--operation mode is normal

F1_state.s3_lut_out = F1_state.s2 & !A1L73;
F1_state.s3 = DFFEA(F1_state.s3_lut_out, GLOBAL(clk), reset, , , , );

--F1L51Q is timer:inst6|state.s3~21 at LC8_H26
--operation mode is normal

F1L51Q = F1_state.s3;


--F1_state.s4 is timer:inst6|state.s4 at LC4_H25
--operation mode is normal

F1_state.s4_lut_out = F1_state.s2 & A1L73;
F1_state.s4 = DFFEA(F1_state.s4_lut_out, GLOBAL(clk), reset, , , , );

--F1L71Q is timer:inst6|state.s4~14 at LC4_H25
--operation mode is normal

F1L71Q = F1_state.s4;


--F1_state.s0 is timer:inst6|state.s0 at LC1_D23
--operation mode is normal

F1_state.s0_lut_out = VCC;
F1_state.s0 = DFFEA(F1_state.s0_lut_out, GLOBAL(clk), reset, , , , );

--F1L9Q is timer:inst6|state.s0~29 at LC1_D23
--operation mode is normal

F1L9Q = F1_state.s0;


--H1L35 is controller:inst8|Mux~4075 at LC5_H25
--operation mode is normal

H1L35 = F1_state.s5 # F1_state.s3 & (F1_state.s4 # !F1_state.s0);

--H1L201 is controller:inst8|Mux~4130 at LC5_H25
--operation mode is normal

H1L201 = F1_state.s5 # F1_state.s3 & (F1_state.s4 # !F1_state.s0);


--G1_q[13] is ir:inst7|q[13] at LC4_H18
--operation mode is normal

G1_q[13]_lut_out = A1L93;
G1_q[13] = DFFEA(G1_q[13]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L13Q is ir:inst7|q[13]~276 at LC4_H18
--operation mode is normal

G1L13Q = G1_q[13];


--G1_q[12] is ir:inst7|q[12] at LC6_H18
--operation mode is normal

G1_q[12]_lut_out = A1L04;
G1_q[12] = DFFEA(G1_q[12]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L92Q is ir:inst7|q[12]~277 at LC6_H18
--operation mode is normal

G1L92Q = G1_q[12];


--H1L45 is controller:inst8|Mux~4076 at LC3_H24
--operation mode is normal

H1L45 = !G1_q[12] & !G1_q[13] & !G1_q[11];

--H1L301 is controller:inst8|Mux~4131 at LC3_H24
--operation mode is normal

H1L301 = !G1_q[12] & !G1_q[13] & !G1_q[11];


--G1_q[14] is ir:inst7|q[14] at LC3_H18
--operation mode is normal

G1_q[14]_lut_out = A1L83;
G1_q[14] = DFFEA(G1_q[14]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L33Q is ir:inst7|q[14]~278 at LC3_H18
--operation mode is normal

G1L33Q = G1_q[14];


--G1_q[10] is ir:inst7|q[10] at LC4_H19
--operation mode is normal

G1_q[10]_lut_out = A1L24;
G1_q[10] = DFFEA(G1_q[10]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L52Q is ir:inst7|q[10]~279 at LC4_H19
--operation mode is normal

G1L52Q = G1_q[10];


--H1L771 is controller:inst8|reduce_nor~581 at LC4_H24
--operation mode is normal

H1L771 = !G1_q[10] & !G1_q[14] & H1L45 & G1_q[15];

--H1L881 is controller:inst8|reduce_nor~592 at LC4_H24
--operation mode is normal

H1L881 = !G1_q[10] & !G1_q[14] & H1L45 & G1_q[15];


--G1_q[9] is ir:inst7|q[9] at LC1_H20
--operation mode is normal

G1_q[9]_lut_out = A1L34;
G1_q[9] = DFFEA(G1_q[9]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L32Q is ir:inst7|q[9]~280 at LC1_H20
--operation mode is normal

G1L32Q = G1_q[9];


--G1_q[8] is ir:inst7|q[8] at LC6_H19
--operation mode is normal

G1_q[8]_lut_out = A1L44;
G1_q[8] = DFFEA(G1_q[8]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L12Q is ir:inst7|q[8]~281 at LC6_H19
--operation mode is normal

G1L12Q = G1_q[8];


--H1L671 is controller:inst8|reduce_nor~27 at LC1_H24
--operation mode is normal

H1L671 = !H1L771 # !G1_q[9] # !G1_q[8];

--H1L981 is controller:inst8|reduce_nor~593 at LC1_H24
--operation mode is normal

H1L981 = !H1L771 # !G1_q[9] # !G1_q[8];


--F1_state.s1 is timer:inst6|state.s1 at LC5_H26
--operation mode is normal

F1_state.s1_lut_out = F1_state.s3 # F1_state.s5 # !F1_state.s0;
F1_state.s1 = DFFEA(F1_state.s1_lut_out, GLOBAL(clk), reset, , , , );

--F1L11Q is timer:inst6|state.s1~14 at LC5_H26
--operation mode is normal

F1L11Q = F1_state.s1;


--H1L55 is controller:inst8|Mux~4077 at LC2_I7
--operation mode is normal

H1L55 = !F1_state.s1 & F1_state.s0 & H1L771 # !H1L35;

--H1L401 is controller:inst8|Mux~4132 at LC2_I7
--operation mode is normal

H1L401 = !F1_state.s1 & F1_state.s0 & H1L771 # !H1L35;


--H1_wr is controller:inst8|wr at LC1_I7
--operation mode is normal

H1_wr = H1L55 & (!H1L671 & H1L35) # !H1L55 & H1_wr;

--H1L862 is controller:inst8|wr~3 at LC1_I7
--operation mode is normal

H1L862 = H1L55 & (!H1L671 & H1L35) # !H1L55 & H1_wr;


--K1_q[13] is pc:inst10|q[13] at LC2_G30
--operation mode is normal

K1_q[13]_lut_out = B1L331;
K1_q[13] = DFFEA(K1_q[13]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L92Q is pc:inst10|q[13]~99 at LC2_G30
--operation mode is normal

K1L92Q = K1_q[13];


--K1_q[9] is pc:inst10|q[9] at LC3_F19
--operation mode is normal

K1_q[9]_lut_out = B1L39;
K1_q[9] = DFFEA(K1_q[9]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L12Q is pc:inst10|q[9]~100 at LC3_F19
--operation mode is normal

K1L12Q = K1_q[9];


--K1_q[8] is pc:inst10|q[8] at LC1_H41
--operation mode is normal

K1_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
K1_q[8] = DFFEA(K1_q[8]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L91Q is pc:inst10|q[8]~101 at LC1_H41
--operation mode is normal

K1L91Q = K1_q[8];


--K1_q[7] is pc:inst10|q[7] at LC1_G47
--operation mode is normal

K1_q[7]_lut_out = B1L37;
K1_q[7] = DFFEA(K1_q[7]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L71Q is pc:inst10|q[7]~102 at LC1_G47
--operation mode is normal

K1L71Q = K1_q[7];


--K1_q[6] is pc:inst10|q[6] at LC4_B45
--operation mode is normal

K1_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
K1_q[6] = DFFEA(K1_q[6]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L51Q is pc:inst10|q[6]~103 at LC4_B45
--operation mode is normal

K1L51Q = K1_q[6];


--K1_q[5] is pc:inst10|q[5] at LC2_G24
--operation mode is normal

K1_q[5]_lut_out = B1L35;
K1_q[5] = DFFEA(K1_q[5]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L31Q is pc:inst10|q[5]~104 at LC2_G24
--operation mode is normal

K1L31Q = K1_q[5];


--K1_q[4] is pc:inst10|q[4] at LC8_H44
--operation mode is normal

K1_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
K1_q[4] = DFFEA(K1_q[4]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L11Q is pc:inst10|q[4]~105 at LC8_H44
--operation mode is normal

K1L11Q = K1_q[4];


--K1_q[3] is pc:inst10|q[3] at LC6_B45
--operation mode is normal

K1_q[3]_lut_out = B1L33;
K1_q[3] = DFFEA(K1_q[3]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L9Q is pc:inst10|q[3]~106 at LC6_B45
--operation mode is normal

K1L9Q = K1_q[3];


--K1_q[2] is pc:inst10|q[2] at LC6_H37
--operation mode is normal

K1_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
K1_q[2] = DFFEA(K1_q[2]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L7Q is pc:inst10|q[2]~107 at LC6_H37
--operation mode is normal

K1L7Q = K1_q[2];


--K1_q[1] is pc:inst10|q[1] at LC5_H49
--operation mode is normal

K1_q[1]_lut_out = B1L31;
K1_q[1] = DFFEA(K1_q[1]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L5Q is pc:inst10|q[1]~108 at LC5_H49
--operation mode is normal

K1L5Q = K1_q[1];


--K1_q[0] is pc:inst10|q[0] at LC6_E51
--operation mode is normal

K1_q[0]_lut_out = B1L4;
K1_q[0] = DFFEA(K1_q[0]_lut_out, GLOBAL(clk), reset, , H1L63, , );

--K1L3Q is pc:inst10|q[0]~109 at LC6_E51
--operation mode is normal

K1L3Q = K1_q[0];


--G1L1 is ir:inst7|Mux~55 at LC2_E46
--operation mode is normal

G1L1 = !H1_rec[0] & H1_rec[1];

--G1L2 is ir:inst7|Mux~56 at LC2_E46
--operation mode is normal

G1L2 = !H1_rec[0] & H1_rec[1];


--G1_q[7] is ir:inst7|q[7] at LC3_I20
--operation mode is normal

G1_q[7]_lut_out = A1L54;
G1_q[7] = DFFEA(G1_q[7]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L91Q is ir:inst7|q[7]~282 at LC3_I20
--operation mode is normal

G1L91Q = G1_q[7];


--H1L65 is controller:inst8|Mux~4078 at LC6_H25
--operation mode is normal

H1L65 = !F1_state.s5 & !F1_state.s4 & F1_state.s3 & F1_state.s0;

--H1L501 is controller:inst8|Mux~4133 at LC6_H25
--operation mode is normal

H1L501 = !F1_state.s5 & !F1_state.s4 & F1_state.s3 & F1_state.s0;


--H1L871 is controller:inst8|reduce_nor~582 at LC1_H19
--operation mode is normal

H1L871 = !G1_q[10] & G1_q[11];

--H1L091 is controller:inst8|reduce_nor~594 at LC1_H19
--operation mode is normal

H1L091 = !G1_q[10] & G1_q[11];


--H1L971 is controller:inst8|reduce_nor~583 at LC5_H19
--operation mode is normal

H1L971 = !G1_q[8] & H1L871 & G1_q[12] & G1_q[13];

--H1L191 is controller:inst8|reduce_nor~595 at LC5_H19
--operation mode is normal

H1L191 = !G1_q[8] & H1L871 & G1_q[12] & G1_q[13];


--H1L202 is controller:inst8|reduce_or~534 at LC2_H19
--operation mode is normal

H1L202 = G1_q[13] # G1_q[9] & !G1_q[10] & !G1_q[8];

--H1L712 is controller:inst8|reduce_or~549 at LC2_H19
--operation mode is normal

H1L712 = G1_q[13] # G1_q[9] & !G1_q[10] & !G1_q[8];


--H1L302 is controller:inst8|reduce_or~535 at LC7_H19
--operation mode is normal

H1L302 = H1L971 # !H1L202 & !G1_q[11] & !G1_q[12];

--H1L812 is controller:inst8|reduce_or~550 at LC7_H19
--operation mode is normal

H1L812 = H1L971 # !H1L202 & !G1_q[11] & !G1_q[12];


--H1L75 is controller:inst8|Mux~4079 at LC8_H15
--operation mode is normal

H1L75 = !G1_q[15] & G1_q[14] & H1L302 & H1L65;

--H1L601 is controller:inst8|Mux~4134 at LC8_H15
--operation mode is normal

H1L601 = !G1_q[15] & G1_q[14] & H1L302 & H1L65;


--H1L85 is controller:inst8|Mux~4080 at LC1_F8
--operation mode is normal

H1L85 = H1L75 & G1_q[7];

--H1L701 is controller:inst8|Mux~4135 at LC1_F8
--operation mode is normal

H1L701 = H1L75 & G1_q[7];


--F1_output[2] is timer:inst6|output[2] at LC3_H25
--operation mode is normal

F1_output[2] = F1_state.s5 # F1_state.s4 # !F1_state.s0;

--F1L5 is timer:inst6|output[2]~78 at LC3_H25
--operation mode is normal

F1L5 = F1_state.s5 # F1_state.s4 # !F1_state.s0;


--H1L081 is controller:inst8|reduce_nor~584 at LC8_H18
--operation mode is normal

H1L081 = H1L971 & G1_q[14];

--H1L291 is controller:inst8|reduce_nor~596 at LC8_H18
--operation mode is normal

H1L291 = H1L971 & G1_q[14];


--H1L181 is controller:inst8|reduce_nor~585 at LC5_H18
--operation mode is normal

H1L181 = !G1_q[12] & !G1_q[13];

--H1L391 is controller:inst8|reduce_nor~597 at LC5_H18
--operation mode is normal

H1L391 = !G1_q[12] & !G1_q[13];


--H1L281 is controller:inst8|reduce_nor~586 at LC8_H19
--operation mode is normal

H1L281 = !G1_q[11] & (G1_q[8] # G1_q[10] # !G1_q[9]);

--H1L491 is controller:inst8|reduce_nor~598 at LC8_H19
--operation mode is normal

H1L491 = !G1_q[11] & (G1_q[8] # G1_q[10] # !G1_q[9]);


--H1L381 is controller:inst8|reduce_nor~587 at LC5_H20
--operation mode is normal

H1L381 = H1L281 # !G1_q[14] & (!G1_q[10] # !G1_q[9]);

--H1L591 is controller:inst8|reduce_nor~599 at LC5_H20
--operation mode is normal

H1L591 = H1L281 # !G1_q[14] & (!G1_q[10] # !G1_q[9]);


--H1L481 is controller:inst8|reduce_nor~588 at LC2_H18
--operation mode is normal

H1L481 = !G1_q[15] & (H1L081 # H1L381 & H1L181);

--H1L691 is controller:inst8|reduce_nor~600 at LC2_H18
--operation mode is normal

H1L691 = !G1_q[15] & (H1L081 # H1L381 & H1L181);


--F1L6 is timer:inst6|output~1 at LC4_H14
--operation mode is normal

F1L6 = F1_state.s1 # !F1_state.s0;

--F1L7 is timer:inst6|output~79 at LC4_H14
--operation mode is normal

F1L7 = F1_state.s1 # !F1_state.s0;


--F1_output[1] is timer:inst6|output[1] at LC1_H26
--operation mode is normal

F1_output[1] = F1_state.s3 # F1_state.s5;

--F1L3 is timer:inst6|output[1]~80 at LC1_H26
--operation mode is normal

F1L3 = F1_state.s3 # F1_state.s5;


--H1L95 is controller:inst8|Mux~4081 at LC1_H14
--operation mode is normal

H1L95 = !F1L6 & (H1L481 # F1_output[2]) # !F1_output[1];

--H1L801 is controller:inst8|Mux~4136 at LC1_H14
--operation mode is normal

H1L801 = !F1L6 & (H1L481 # F1_output[2]) # !F1_output[1];


--H1_offset[7] is controller:inst8|offset[7] at LC7_F8
--operation mode is normal

H1_offset[7] = H1L95 & (H1L85) # !H1L95 & H1_offset[7];

--H1L861 is controller:inst8|offset[7]~24 at LC7_F8
--operation mode is normal

H1L861 = H1L95 & (H1L85) # !H1L95 & H1_offset[7];


--H1L581 is controller:inst8|reduce_nor~589 at LC1_H18
--operation mode is normal

H1L581 = !G1_q[12] & !G1_q[13] & !G1_q[15];

--H1L791 is controller:inst8|reduce_nor~601 at LC1_H18
--operation mode is normal

H1L791 = !G1_q[12] & !G1_q[13] & !G1_q[15];


--H1L06 is controller:inst8|Mux~4082 at LC7_H18
--operation mode is normal

H1L06 = H1L581 & (F1_state.s3 # F1_state.s5);

--H1L901 is controller:inst8|Mux~4137 at LC7_H18
--operation mode is normal

H1L901 = H1L581 & (F1_state.s3 # F1_state.s5);


--H1L402 is controller:inst8|reduce_or~536 at LC2_H20
--operation mode is normal

H1L402 = G1_q[8] & (G1_q[14] # G1_q[9] & G1_q[10]) # !G1_q[8] & G1_q[14] & (G1_q[10] # !G1_q[9]);

--H1L912 is controller:inst8|reduce_or~551 at LC2_H20
--operation mode is normal

H1L912 = G1_q[8] & (G1_q[14] # G1_q[9] & G1_q[10]) # !G1_q[8] & G1_q[14] & (G1_q[10] # !G1_q[9]);


--H1L16 is controller:inst8|Mux~4083 at LC8_H20
--operation mode is normal

H1L16 = !F1_output[2] & !G1_q[11] & H1L402 & H1L06;

--H1L011 is controller:inst8|Mux~4138 at LC8_H20
--operation mode is normal

H1L011 = !F1_output[2] & !G1_q[11] & H1L402 & H1L06;


--H1L26 is controller:inst8|Mux~4084 at LC6_H24
--operation mode is normal

H1L26 = !G1_q[8] & !F1_output[1] & G1_q[9] & H1L771;

--H1L111 is controller:inst8|Mux~4139 at LC6_H24
--operation mode is normal

H1L111 = !G1_q[8] & !F1_output[1] & G1_q[9] & H1L771;


--H1L36 is controller:inst8|Mux~4085 at LC1_H17
--operation mode is normal

H1L36 = H1L16 # H1L35 # H1L26 & F1_output[2];

--H1L211 is controller:inst8|Mux~4140 at LC1_H17
--operation mode is normal

H1L211 = H1L16 # H1L35 # H1L26 & F1_output[2];


--H1L46 is controller:inst8|Mux~4086 at LC4_H17
--operation mode is normal

H1L46 = !F1L6 & (F1_output[2] & (H1L771) # !F1_output[2] & H1L481);

--H1L311 is controller:inst8|Mux~4141 at LC4_H17
--operation mode is normal

H1L311 = !F1L6 & (F1_output[2] & (H1L771) # !F1_output[2] & H1L481);


--H1L56 is controller:inst8|Mux~4087 at LC1_H25
--operation mode is normal

H1L56 = !F1_state.s1 & F1_state.s0 & (F1_state.s5 # F1_state.s4);

--H1L411 is controller:inst8|Mux~4142 at LC1_H25
--operation mode is normal

H1L411 = !F1_state.s1 & F1_state.s0 & (F1_state.s5 # F1_state.s4);


--H1L66 is controller:inst8|Mux~4088 at LC8_H17
--operation mode is normal

H1L66 = H1L46 # !F1_state.s3 & !F1_state.s5 & !H1L56;

--H1L511 is controller:inst8|Mux~4143 at LC8_H17
--operation mode is normal

H1L511 = H1L46 # !F1_state.s3 & !F1_state.s5 & !H1L56;


--H1_alu_in_sel[0] is controller:inst8|alu_in_sel[0] at LC5_H17
--operation mode is normal

H1_alu_in_sel[0] = H1L66 & (!F1L6 & H1L36) # !H1L66 & H1_alu_in_sel[0];

--H1L01 is controller:inst8|alu_in_sel[0]~9 at LC5_H17
--operation mode is normal

H1L01 = H1L66 & (!F1L6 & H1L36) # !H1L66 & H1_alu_in_sel[0];


--H1L502 is controller:inst8|reduce_or~537 at LC3_H20
--operation mode is normal

H1L502 = G1_q[11] & (!G1_q[14]) # !G1_q[11] & G1_q[14] & (G1_q[8] # !G1_q[9]);

--H1L022 is controller:inst8|reduce_or~552 at LC3_H20
--operation mode is normal

H1L022 = G1_q[11] & (!G1_q[14]) # !G1_q[11] & G1_q[14] & (G1_q[8] # !G1_q[9]);


--H1L76 is controller:inst8|Mux~4089 at LC6_H20
--operation mode is normal

H1L76 = G1_q[10] & !G1_q[11] & G1_q[14] # !G1_q[10] & (H1L502);

--H1L611 is controller:inst8|Mux~4144 at LC6_H20
--operation mode is normal

H1L611 = G1_q[10] & !G1_q[11] & G1_q[14] # !G1_q[10] & (H1L502);


--H1L86 is controller:inst8|Mux~4090 at LC1_H37
--operation mode is normal

H1L86 = H1L671 & (H1L76 & H1L06) # !H1L671 & (H1L76 & H1L06 # !F1_output[1]);

--H1L711 is controller:inst8|Mux~4145 at LC1_H37
--operation mode is normal

H1L711 = H1L671 & (H1L76 & H1L06) # !H1L671 & (H1L76 & H1L06 # !F1_output[1]);


--H1L96 is controller:inst8|Mux~4091 at LC7_H37
--operation mode is normal

H1L96 = !F1L6 & H1L86 & (F1_output[1] $ F1_output[2]);

--H1L811 is controller:inst8|Mux~4146 at LC7_H37
--operation mode is normal

H1L811 = !F1L6 & H1L86 & (F1_output[1] $ F1_output[2]);


--H1_alu_in_sel[1] is controller:inst8|alu_in_sel[1] at LC2_H17
--operation mode is normal

H1_alu_in_sel[1] = H1L66 & (H1L96) # !H1L66 & H1_alu_in_sel[1];

--H1L21 is controller:inst8|alu_in_sel[1]~10 at LC2_H17
--operation mode is normal

H1L21 = H1L66 & (H1L96) # !H1L66 & H1_alu_in_sel[1];


--H1L07 is controller:inst8|Mux~4092 at LC4_H26
--operation mode is normal

H1L07 = !F1_state.s3 & !F1_state.s5 & !F1_output[2] & F1L6;

--H1L911 is controller:inst8|Mux~4147 at LC4_H26
--operation mode is normal

H1L911 = !F1_state.s3 & !F1_state.s5 & !F1_output[2] & F1L6;


--H1L17 is controller:inst8|Mux~4093 at LC7_H17
--operation mode is normal

H1L17 = H1L07 # !H1L26 & H1L56 & H1L671;

--H1L021 is controller:inst8|Mux~4148 at LC7_H17
--operation mode is normal

H1L021 = H1L07 # !H1L26 & H1L56 & H1L671;


--H1_alu_in_sel[2] is controller:inst8|alu_in_sel[2] at LC3_H17
--operation mode is normal

H1_alu_in_sel[2] = H1L66 & (H1L17) # !H1L66 & H1_alu_in_sel[2];

--H1L41 is controller:inst8|alu_in_sel[2]~11 at LC3_H17
--operation mode is normal

H1L41 = H1L66 & (H1L17) # !H1L66 & H1_alu_in_sel[2];


--G1_q[1] is ir:inst7|q[1] at LC4_K38
--operation mode is normal

G1_q[1]_lut_out = A1L15;
G1_q[1] = DFFEA(G1_q[1]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L7Q is ir:inst7|q[1]~283 at LC4_K38
--operation mode is normal

G1L7Q = G1_q[1];


--H1L602 is controller:inst8|reduce_or~538 at LC3_H15
--operation mode is normal

H1L602 = !G1_q[15] & G1_q[14] & H1L302;

--H1L122 is controller:inst8|reduce_or~553 at LC3_H15
--operation mode is normal

H1L122 = !G1_q[15] & G1_q[14] & H1L302;


--H1L27 is controller:inst8|Mux~4094 at LC1_H16
--operation mode is normal

H1L27 = G1_q[1] & (F1_output[2] # !H1L602 & F1_output[1]);

--H1L121 is controller:inst8|Mux~4149 at LC1_H16
--operation mode is normal

H1L121 = G1_q[1] & (F1_output[2] # !H1L602 & F1_output[1]);


--H1_sour_reg[1] is controller:inst8|sour_reg[1] at LC2_H16
--operation mode is normal

H1_sour_reg[1] = H1L95 & (!F1L6 & H1L27) # !H1L95 & H1_sour_reg[1];

--H1L752 is controller:inst8|sour_reg[1]~12 at LC2_H16
--operation mode is normal

H1L752 = H1L95 & (!F1L6 & H1L27) # !H1L95 & H1_sour_reg[1];


--G1_q[0] is ir:inst7|q[0] at LC2_E17
--operation mode is normal

G1_q[0]_lut_out = A1L25;
G1_q[0] = DFFEA(G1_q[0]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L5Q is ir:inst7|q[0]~284 at LC2_E17
--operation mode is normal

G1L5Q = G1_q[0];


--H1L37 is controller:inst8|Mux~4095 at LC7_H14
--operation mode is normal

H1L37 = G1_q[0] & (F1_output[2] # !H1L602 & F1_output[1]);

--H1L221 is controller:inst8|Mux~4150 at LC7_H14
--operation mode is normal

H1L221 = G1_q[0] & (F1_output[2] # !H1L602 & F1_output[1]);


--H1_sour_reg[0] is controller:inst8|sour_reg[0] at LC5_H14
--operation mode is normal

H1_sour_reg[0] = H1L95 & (!F1L6 & H1L37) # !H1L95 & H1_sour_reg[0];

--H1L552 is controller:inst8|sour_reg[0]~13 at LC5_H14
--operation mode is normal

H1L552 = H1L95 & (!F1L6 & H1L37) # !H1L95 & H1_sour_reg[0];


--G1_q[3] is ir:inst7|q[3] at LC3_K20
--operation mode is normal

G1_q[3]_lut_out = A1L94;
G1_q[3] = DFFEA(G1_q[3]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L11Q is ir:inst7|q[3]~285 at LC3_K20
--operation mode is normal

G1L11Q = G1_q[3];


--H1L47 is controller:inst8|Mux~4096 at LC7_H15
--operation mode is normal

H1L47 = G1_q[3] & (F1_output[2] # !H1L602 & F1_output[1]);

--H1L321 is controller:inst8|Mux~4151 at LC7_H15
--operation mode is normal

H1L321 = G1_q[3] & (F1_output[2] # !H1L602 & F1_output[1]);


--H1_sour_reg[3] is controller:inst8|sour_reg[3] at LC4_H8
--operation mode is normal

H1_sour_reg[3] = H1L95 & (!F1L6 & H1L47) # !H1L95 & H1_sour_reg[3];

--H1L162 is controller:inst8|sour_reg[3]~14 at LC4_H8
--operation mode is normal

H1L162 = H1L95 & (!F1L6 & H1L47) # !H1L95 & H1_sour_reg[3];


--G1_q[2] is ir:inst7|q[2] at LC3_H32
--operation mode is normal

G1_q[2]_lut_out = A1L05;
G1_q[2] = DFFEA(G1_q[2]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L9Q is ir:inst7|q[2]~286 at LC3_H32
--operation mode is normal

G1L9Q = G1_q[2];


--H1L57 is controller:inst8|Mux~4097 at LC4_H16
--operation mode is normal

H1L57 = G1_q[2] & (F1_output[2] # !H1L602 & F1_output[1]);

--H1L421 is controller:inst8|Mux~4152 at LC4_H16
--operation mode is normal

H1L421 = G1_q[2] & (F1_output[2] # !H1L602 & F1_output[1]);


--H1_sour_reg[2] is controller:inst8|sour_reg[2] at LC3_H16
--operation mode is normal

H1_sour_reg[2] = H1L95 & (!F1L6 & H1L57) # !H1L95 & H1_sour_reg[2];

--H1L952 is controller:inst8|sour_reg[2]~15 at LC3_H16
--operation mode is normal

H1L952 = H1L95 & (!F1L6 & H1L57) # !H1L95 & H1_sour_reg[2];


--H1L67 is controller:inst8|Mux~4098 at LC3_H26
--operation mode is normal

H1L67 = !G1_q[12] & !G1_q[13] & !G1_q[15] & !G1_q[14];

--H1L521 is controller:inst8|Mux~4153 at LC3_H26
--operation mode is normal

H1L521 = !G1_q[12] & !G1_q[13] & !G1_q[15] & !G1_q[14];


--H1L702 is controller:inst8|reduce_or~539 at LC1_G44
--operation mode is normal

H1L702 = G1_q[10] & !G1_q[11] & (G1_q[8] $ G1_q[9]) # !G1_q[10] & G1_q[9] & (G1_q[11] $ !G1_q[8]);

--H1L222 is controller:inst8|reduce_or~554 at LC1_G44
--operation mode is normal

H1L222 = G1_q[10] & !G1_q[11] & (G1_q[8] $ G1_q[9]) # !G1_q[10] & G1_q[9] & (G1_q[11] $ !G1_q[8]);


--H1L802 is controller:inst8|reduce_or~540 at LC2_G44
--operation mode is normal

H1L802 = H1L702 & H1L67;

--H1L322 is controller:inst8|reduce_or~555 at LC2_G44
--operation mode is normal

H1L322 = H1L702 & H1L67;


--H1_alu_func[1] is controller:inst8|alu_func[1] at LC5_G44
--operation mode is normal

H1_alu_func[1] = H1L95 & (H1L65 & H1L802) # !H1L95 & H1_alu_func[1];

--H1L5 is controller:inst8|alu_func[1]~23 at LC5_G44
--operation mode is normal

H1L5 = H1L95 & (H1L65 & H1L802) # !H1L95 & H1_alu_func[1];


--V9_cs_buffer[16] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[16] at LC7_G13
--operation mode is arithmetic

V9_cs_buffer[16] = V6_cs_buffer[16] $ !V9_cout[15];

--V9L74 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]~301 at LC7_G13
--operation mode is arithmetic

V9L74 = V6_cs_buffer[16] $ !V9_cout[15];

--V9_cout[16] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[16] at LC7_G13
--operation mode is arithmetic

V9_cout[16] = CARRY(V9_cout[15] # !V6_cs_buffer[16]);


--T3_unreg_res_node[17] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[17] at LC8_G13
--operation mode is normal

T3_unreg_res_node[17] = V9_cout[16] $ !T2_unreg_res_node[17];

--T3L3 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[17]~34 at LC8_G13
--operation mode is normal

T3L3 = V9_cout[16] $ !T2_unreg_res_node[17];


--H1L902 is controller:inst8|reduce_or~541 at LC7_G44
--operation mode is normal

H1L902 = G1_q[10] & (G1_q[11] & G1_q[8] & !G1_q[9] # !G1_q[11] & !G1_q[8] & G1_q[9]) # !G1_q[10] & (G1_q[11] $ G1_q[8]);

--H1L422 is controller:inst8|reduce_or~556 at LC7_G44
--operation mode is normal

H1L422 = G1_q[10] & (G1_q[11] & G1_q[8] & !G1_q[9] # !G1_q[11] & !G1_q[8] & G1_q[9]) # !G1_q[10] & (G1_q[11] $ G1_q[8]);


--H1L77 is controller:inst8|Mux~4099 at LC2_E35
--operation mode is normal

H1L77 = H1L902 & H1L67 & H1L65;

--H1L621 is controller:inst8|Mux~4154 at LC2_E35
--operation mode is normal

H1L621 = H1L902 & H1L67 & H1L65;


--H1_alu_func[0] is controller:inst8|alu_func[0] at LC1_E35
--operation mode is normal

H1_alu_func[0] = H1L95 & (H1L77) # !H1L95 & H1_alu_func[0];

--H1L3 is controller:inst8|alu_func[0]~24 at LC1_E35
--operation mode is normal

H1L3 = H1L95 & (H1L77) # !H1L95 & H1_alu_func[0];


--V3_cs_buffer[15] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] at LC4_G23
--operation mode is arithmetic

V3_cs_buffer[15] = N1L211 $ N1L751 $ V3_cout[14];

--V3L05 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~293 at LC4_G23
--operation mode is arithmetic

V3L05 = N1L211 $ N1L751 $ V3_cout[14];

--V3_cout[15] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[15] at LC4_G23
--operation mode is arithmetic

V3_cout[15] = CARRY(N1L211 & (N1L751 # V3_cout[14]) # !N1L211 & N1L751 & V3_cout[14]);


--T1_unreg_res_node[16] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[16] at LC5_G23
--operation mode is normal

T1_unreg_res_node[16] = N1L221 $ V3_cout[15] $ !N1L061;

--T1L3 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[16]~33 at LC5_G23
--operation mode is normal

T1L3 = N1L221 $ V3_cout[15] $ !N1L061;


--G1_q[6] is ir:inst7|q[6] at LC8_B15
--operation mode is normal

G1_q[6]_lut_out = A1L64;
G1_q[6] = DFFEA(G1_q[6]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L71Q is ir:inst7|q[6]~287 at LC8_B15
--operation mode is normal

G1L71Q = G1_q[6];


--H1L87 is controller:inst8|Mux~4100 at LC2_H15
--operation mode is normal

H1L87 = G1_q[6] & (F1_output[2] # !H1L602 & F1_output[1]);

--H1L721 is controller:inst8|Mux~4155 at LC2_H15
--operation mode is normal

H1L721 = G1_q[6] & (F1_output[2] # !H1L602 & F1_output[1]);


--H1_dest_reg[2] is controller:inst8|dest_reg[2] at LC6_H15
--operation mode is normal

H1_dest_reg[2] = H1L95 & (!F1L6 & H1L87) # !H1L95 & H1_dest_reg[2];

--H1L62 is controller:inst8|dest_reg[2]~12 at LC6_H15
--operation mode is normal

H1L62 = H1L95 & (!F1L6 & H1L87) # !H1L95 & H1_dest_reg[2];


--H1L97 is controller:inst8|Mux~4101 at LC5_H15
--operation mode is normal

H1L97 = G1_q[7] & (F1_output[2] # !H1L602 & F1_output[1]);

--H1L821 is controller:inst8|Mux~4156 at LC5_H15
--operation mode is normal

H1L821 = G1_q[7] & (F1_output[2] # !H1L602 & F1_output[1]);


--H1_dest_reg[3] is controller:inst8|dest_reg[3] at LC6_H14
--operation mode is normal

H1_dest_reg[3] = H1L95 & (!F1L6 & H1L97) # !H1L95 & H1_dest_reg[3];

--H1L82 is controller:inst8|dest_reg[3]~13 at LC6_H14
--operation mode is normal

H1L82 = H1L95 & (!F1L6 & H1L97) # !H1L95 & H1_dest_reg[3];


--G1_q[5] is ir:inst7|q[5] at LC7_G24
--operation mode is normal

G1_q[5]_lut_out = A1L74;
G1_q[5] = DFFEA(G1_q[5]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L51Q is ir:inst7|q[5]~288 at LC7_G24
--operation mode is normal

G1L51Q = G1_q[5];


--H1L08 is controller:inst8|Mux~4102 at LC4_H15
--operation mode is normal

H1L08 = G1_q[5] & (F1_output[2] # !H1L602 & F1_output[1]);

--H1L921 is controller:inst8|Mux~4157 at LC4_H15
--operation mode is normal

H1L921 = G1_q[5] & (F1_output[2] # !H1L602 & F1_output[1]);


--H1_dest_reg[1] is controller:inst8|dest_reg[1] at LC8_H14
--operation mode is normal

H1_dest_reg[1] = H1L95 & (!F1L6 & H1L08) # !H1L95 & H1_dest_reg[1];

--H1L42 is controller:inst8|dest_reg[1]~14 at LC8_H14
--operation mode is normal

H1L42 = H1L95 & (!F1L6 & H1L08) # !H1L95 & H1_dest_reg[1];


--G1_q[4] is ir:inst7|q[4] at LC2_K16
--operation mode is normal

G1_q[4]_lut_out = A1L84;
G1_q[4] = DFFEA(G1_q[4]_lut_out, GLOBAL(clk), reset, , G1L1, , );

--G1L31Q is ir:inst7|q[4]~289 at LC2_K16
--operation mode is normal

G1L31Q = G1_q[4];


--H1L18 is controller:inst8|Mux~4103 at LC1_H15
--operation mode is normal

H1L18 = G1_q[4] & (F1_output[2] # !H1L602 & F1_output[1]);

--H1L031 is controller:inst8|Mux~4158 at LC1_H15
--operation mode is normal

H1L031 = G1_q[4] & (F1_output[2] # !H1L602 & F1_output[1]);


--H1_dest_reg[0] is controller:inst8|dest_reg[0] at LC3_H14
--operation mode is normal

H1_dest_reg[0] = H1L95 & (!F1L6 & H1L18) # !H1L95 & H1_dest_reg[0];

--H1L22 is controller:inst8|dest_reg[0]~15 at LC3_H14
--operation mode is normal

H1L22 = H1L95 & (!F1L6 & H1L18) # !H1L95 & H1_dest_reg[0];


--H1L012 is controller:inst8|reduce_or~542 at LC6_G44
--operation mode is normal

H1L012 = G1_q[10] & !G1_q[8] & !G1_q[9] & !G1_q[11] # !G1_q[10] & (G1_q[9] & G1_q[11]);

--H1L522 is controller:inst8|reduce_or~557 at LC6_G44
--operation mode is normal

H1L522 = G1_q[10] & !G1_q[8] & !G1_q[9] & !G1_q[11] # !G1_q[10] & (G1_q[9] & G1_q[11]);


--H1L112 is controller:inst8|reduce_or~543 at LC8_G44
--operation mode is normal

H1L112 = H1L012 & H1L67;

--H1L622 is controller:inst8|reduce_or~558 at LC8_G44
--operation mode is normal

H1L622 = H1L012 & H1L67;


--H1_alu_func[2] is controller:inst8|alu_func[2] at LC4_G44
--operation mode is normal

H1_alu_func[2] = H1L95 & (H1L65 & H1L112) # !H1L95 & H1_alu_func[2];

--H1L7 is controller:inst8|alu_func[2]~25 at LC4_G44
--operation mode is normal

H1L7 = H1L95 & (H1L65 & H1L112) # !H1L95 & H1_alu_func[2];


--F1_state.s2 is timer:inst6|state.s2 at LC2_F4
--operation mode is normal

F1_state.s2_lut_out = F1_state.s1;
F1_state.s2 = DFFEA(F1_state.s2_lut_out, GLOBAL(clk), reset, , , , );

--F1L31Q is timer:inst6|state.s2~15 at LC2_F4
--operation mode is normal

F1L31Q = F1_state.s2;


--M1L589 is reg_mux:inst27|sr[14]~356 at LC6_F11
--operation mode is normal

M1L589 = H1_sour_reg[3] & (L01_q[14] # H1_sour_reg[2]) # !H1_sour_reg[3] & L2_q[14] & (!H1_sour_reg[2]);

--M1L599 is reg_mux:inst27|sr[14]~516 at LC6_F11
--operation mode is normal

M1L599 = H1_sour_reg[3] & (L01_q[14] # H1_sour_reg[2]) # !H1_sour_reg[3] & L2_q[14] & (!H1_sour_reg[2]);


--M1L689 is reg_mux:inst27|sr[14]~357 at LC8_F11
--operation mode is normal

M1L689 = M1L589 & (L41_q[14] # !H1_sour_reg[2]) # !M1L589 & (H1_sour_reg[2] & L6_q[14]);

--M1L699 is reg_mux:inst27|sr[14]~517 at LC8_F11
--operation mode is normal

M1L699 = M1L589 & (L41_q[14] # !H1_sour_reg[2]) # !M1L589 & (H1_sour_reg[2] & L6_q[14]);


--M1L789 is reg_mux:inst27|sr[14]~358 at LC2_F12
--operation mode is normal

M1L789 = H1_sour_reg[2] & (L5_q[14] # H1_sour_reg[3]) # !H1_sour_reg[2] & L1_q[14] & (!H1_sour_reg[3]);

--M1L799 is reg_mux:inst27|sr[14]~518 at LC2_F12
--operation mode is normal

M1L799 = H1_sour_reg[2] & (L5_q[14] # H1_sour_reg[3]) # !H1_sour_reg[2] & L1_q[14] & (!H1_sour_reg[3]);


--M1L889 is reg_mux:inst27|sr[14]~359 at LC4_F12
--operation mode is normal

M1L889 = M1L789 & (L31_q[14] # !H1_sour_reg[3]) # !M1L789 & (H1_sour_reg[3] & L9_q[14]);

--M1L899 is reg_mux:inst27|sr[14]~519 at LC4_F12
--operation mode is normal

M1L899 = M1L789 & (L31_q[14] # !H1_sour_reg[3]) # !M1L789 & (H1_sour_reg[3] & L9_q[14]);


--M1L989 is reg_mux:inst27|sr[14]~360 at LC6_F12
--operation mode is normal

M1L989 = H1_sour_reg[3] & (L8_q[14] # H1_sour_reg[2]) # !H1_sour_reg[3] & L61_q[14] & (!H1_sour_reg[2]);

--M1L999 is reg_mux:inst27|sr[14]~520 at LC6_F12
--operation mode is normal

M1L999 = H1_sour_reg[3] & (L8_q[14] # H1_sour_reg[2]) # !H1_sour_reg[3] & L61_q[14] & (!H1_sour_reg[2]);


--M1L099 is reg_mux:inst27|sr[14]~361 at LC7_F12
--operation mode is normal

M1L099 = M1L989 & (L21_q[14] # !H1_sour_reg[2]) # !M1L989 & (H1_sour_reg[2] & L4_q[14]);

--M1L0001 is reg_mux:inst27|sr[14]~521 at LC7_F12
--operation mode is normal

M1L0001 = M1L989 & (L21_q[14] # !H1_sour_reg[2]) # !M1L989 & (H1_sour_reg[2] & L4_q[14]);


--M1L199 is reg_mux:inst27|sr[14]~362 at LC8_F12
--operation mode is normal

M1L199 = H1_sour_reg[0] & (M1L889 # H1_sour_reg[1]) # !H1_sour_reg[0] & M1L099 & (!H1_sour_reg[1]);

--M1L1001 is reg_mux:inst27|sr[14]~522 at LC8_F12
--operation mode is normal

M1L1001 = H1_sour_reg[0] & (M1L889 # H1_sour_reg[1]) # !H1_sour_reg[0] & M1L099 & (!H1_sour_reg[1]);


--M1L299 is reg_mux:inst27|sr[14]~363 at LC6_F7
--operation mode is normal

M1L299 = H1_sour_reg[2] & (L7_q[14] # H1_sour_reg[3]) # !H1_sour_reg[2] & L3_q[14] & (!H1_sour_reg[3]);

--M1L2001 is reg_mux:inst27|sr[14]~523 at LC6_F7
--operation mode is normal

M1L2001 = H1_sour_reg[2] & (L7_q[14] # H1_sour_reg[3]) # !H1_sour_reg[2] & L3_q[14] & (!H1_sour_reg[3]);


--M1L399 is reg_mux:inst27|sr[14]~364 at LC8_F7
--operation mode is normal

M1L399 = M1L299 & (L51_q[14] # !H1_sour_reg[3]) # !M1L299 & (H1_sour_reg[3] & L11_q[14]);

--M1L3001 is reg_mux:inst27|sr[14]~524 at LC8_F7
--operation mode is normal

M1L3001 = M1L299 & (L51_q[14] # !H1_sour_reg[3]) # !M1L299 & (H1_sour_reg[3] & L11_q[14]);


--M1L499 is reg_mux:inst27|sr[14]~365 at LC5_F12
--operation mode is normal

M1L499 = M1L199 & (M1L399 # !H1_sour_reg[1]) # !M1L199 & (H1_sour_reg[1] & M1L689);

--M1L4001 is reg_mux:inst27|sr[14]~525 at LC5_F12
--operation mode is normal

M1L4001 = M1L199 & (M1L399 # !H1_sour_reg[1]) # !M1L199 & (H1_sour_reg[1] & M1L689);


--N1L751 is bus_mux:inst28|alu_sr[14]~638 at LC5_G16
--operation mode is normal

N1L751 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L499;

--N1L851 is bus_mux:inst28|alu_sr[14]~656 at LC5_G16
--operation mode is normal

N1L851 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L499;


--B1L931 is alu:inst|alu_out[14]~5781 at LC2_F27
--operation mode is normal

B1L931 = H1_alu_func[1] & !N1L221 # !H1_alu_func[1] & (N1L751 $ N1L211);

--B1L441 is alu:inst|alu_out[14]~5859 at LC2_F27
--operation mode is normal

B1L441 = H1_alu_func[1] & !N1L221 # !H1_alu_func[1] & (N1L751 $ N1L211);


--N1L201 is bus_mux:inst28|alu_dr[13]~2311 at LC1_C3
--operation mode is normal

N1L201 = N1L811 & (H1_alu_in_sel[0] & (A1L93) # !H1_alu_in_sel[0] & K1_q[13]);

--N1L601 is bus_mux:inst28|alu_dr[13]~2382 at LC1_C3
--operation mode is normal

N1L601 = N1L811 & (H1_alu_in_sel[0] & (A1L93) # !H1_alu_in_sel[0] & K1_q[13]);


--N1L301 is bus_mux:inst28|alu_dr[13]~2312 at LC1_C16
--operation mode is normal

N1L301 = !H1_alu_in_sel[2] & H1_alu_in_sel[1] & H1_alu_in_sel[0] & K1_q[13];

--N1L701 is bus_mux:inst28|alu_dr[13]~2383 at LC1_C16
--operation mode is normal

N1L701 = !H1_alu_in_sel[2] & H1_alu_in_sel[1] & H1_alu_in_sel[0] & K1_q[13];


--L6_q[13] is reg:inst17|q[13] at LC1_C28
--operation mode is normal

L6_q[13]_lut_out = B1L331;
L6_q[13] = DFFEA(L6_q[13]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L92Q is reg:inst17|q[13]~99 at LC1_C28
--operation mode is normal

L6L92Q = L6_q[13];


--L5_q[13] is reg:inst16|q[13] at LC4_C12
--operation mode is normal

L5_q[13]_lut_out = B1L331;
L5_q[13] = DFFEA(L5_q[13]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L92Q is reg:inst16|q[13]~99 at LC4_C12
--operation mode is normal

L5L92Q = L5_q[13];


--L4_q[13] is reg:inst15|q[13] at LC7_B45
--operation mode is normal

L4_q[13]_lut_out = B1L331;
L4_q[13] = DFFEA(L4_q[13]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L92Q is reg:inst15|q[13]~99 at LC7_B45
--operation mode is normal

L4L92Q = L4_q[13];


--M1L162 is reg_mux:inst27|dr[13]~376 at LC5_C12
--operation mode is normal

M1L162 = H1_dest_reg[0] & (L5_q[13] # H1_dest_reg[1]) # !H1_dest_reg[0] & L4_q[13] & (!H1_dest_reg[1]);

--M1L172 is reg_mux:inst27|dr[13]~536 at LC5_C12
--operation mode is normal

M1L172 = H1_dest_reg[0] & (L5_q[13] # H1_dest_reg[1]) # !H1_dest_reg[0] & L4_q[13] & (!H1_dest_reg[1]);


--L7_q[13] is reg:inst18|q[13] at LC4_B25
--operation mode is normal

L7_q[13]_lut_out = B1L331;
L7_q[13] = DFFEA(L7_q[13]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L92Q is reg:inst18|q[13]~99 at LC4_B25
--operation mode is normal

L7L92Q = L7_q[13];


--M1L262 is reg_mux:inst27|dr[13]~377 at LC1_C12
--operation mode is normal

M1L262 = M1L162 & (L7_q[13] # !H1_dest_reg[1]) # !M1L162 & (H1_dest_reg[1] & L6_q[13]);

--M1L272 is reg_mux:inst27|dr[13]~537 at LC1_C12
--operation mode is normal

M1L272 = M1L162 & (L7_q[13] # !H1_dest_reg[1]) # !M1L162 & (H1_dest_reg[1] & L6_q[13]);


--L9_q[13] is reg:inst20|q[13] at LC2_C43
--operation mode is normal

L9_q[13]_lut_out = B1L331;
L9_q[13] = DFFEA(L9_q[13]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L92Q is reg:inst20|q[13]~99 at LC2_C43
--operation mode is normal

L9L92Q = L9_q[13];


--L01_q[13] is reg:inst21|q[13] at LC1_B3
--operation mode is normal

L01_q[13]_lut_out = B1L331;
L01_q[13] = DFFEA(L01_q[13]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L92Q is reg:inst21|q[13]~99 at LC1_B3
--operation mode is normal

L01L92Q = L01_q[13];


--L8_q[13] is reg:inst19|q[13] at LC1_C32
--operation mode is normal

L8_q[13]_lut_out = B1L331;
L8_q[13] = DFFEA(L8_q[13]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L92Q is reg:inst19|q[13]~99 at LC1_C32
--operation mode is normal

L8L92Q = L8_q[13];


--M1L362 is reg_mux:inst27|dr[13]~378 at LC2_C16
--operation mode is normal

M1L362 = H1_dest_reg[1] & (L01_q[13] # H1_dest_reg[0]) # !H1_dest_reg[1] & L8_q[13] & (!H1_dest_reg[0]);

--M1L372 is reg_mux:inst27|dr[13]~538 at LC2_C16
--operation mode is normal

M1L372 = H1_dest_reg[1] & (L01_q[13] # H1_dest_reg[0]) # !H1_dest_reg[1] & L8_q[13] & (!H1_dest_reg[0]);


--L11_q[13] is reg:inst22|q[13] at LC2_C6
--operation mode is normal

L11_q[13]_lut_out = B1L331;
L11_q[13] = DFFEA(L11_q[13]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L92Q is reg:inst22|q[13]~99 at LC2_C6
--operation mode is normal

L11L92Q = L11_q[13];


--M1L462 is reg_mux:inst27|dr[13]~379 at LC3_C16
--operation mode is normal

M1L462 = M1L362 & (L11_q[13] # !H1_dest_reg[0]) # !M1L362 & (H1_dest_reg[0] & L9_q[13]);

--M1L472 is reg_mux:inst27|dr[13]~539 at LC3_C16
--operation mode is normal

M1L472 = M1L362 & (L11_q[13] # !H1_dest_reg[0]) # !M1L362 & (H1_dest_reg[0] & L9_q[13]);


--L1_q[13] is reg:inst12|q[13] at LC4_C15
--operation mode is normal

L1_q[13]_lut_out = B1L331;
L1_q[13] = DFFEA(L1_q[13]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L92Q is reg:inst12|q[13]~99 at LC4_C15
--operation mode is normal

L1L92Q = L1_q[13];


--L2_q[13] is reg:inst13|q[13] at LC3_B25
--operation mode is normal

L2_q[13]_lut_out = B1L331;
L2_q[13] = DFFEA(L2_q[13]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L92Q is reg:inst13|q[13]~99 at LC3_B25
--operation mode is normal

L2L92Q = L2_q[13];


--L61_q[13] is reg:inst30|q[13] at LC5_C15
--operation mode is normal

L61_q[13]_lut_out = B1L331;
L61_q[13] = DFFEA(L61_q[13]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L92Q is reg:inst30|q[13]~99 at LC5_C15
--operation mode is normal

L61L92Q = L61_q[13];


--M1L562 is reg_mux:inst27|dr[13]~380 at LC6_C15
--operation mode is normal

M1L562 = H1_dest_reg[1] & (L2_q[13] # H1_dest_reg[0]) # !H1_dest_reg[1] & L61_q[13] & (!H1_dest_reg[0]);

--M1L572 is reg_mux:inst27|dr[13]~540 at LC6_C15
--operation mode is normal

M1L572 = H1_dest_reg[1] & (L2_q[13] # H1_dest_reg[0]) # !H1_dest_reg[1] & L61_q[13] & (!H1_dest_reg[0]);


--L3_q[13] is reg:inst14|q[13] at LC2_C27
--operation mode is normal

L3_q[13]_lut_out = B1L331;
L3_q[13] = DFFEA(L3_q[13]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L92Q is reg:inst14|q[13]~99 at LC2_C27
--operation mode is normal

L3L92Q = L3_q[13];


--M1L662 is reg_mux:inst27|dr[13]~381 at LC1_C15
--operation mode is normal

M1L662 = M1L562 & (L3_q[13] # !H1_dest_reg[0]) # !M1L562 & (H1_dest_reg[0] & L1_q[13]);

--M1L672 is reg_mux:inst27|dr[13]~541 at LC1_C15
--operation mode is normal

M1L672 = M1L562 & (L3_q[13] # !H1_dest_reg[0]) # !M1L562 & (H1_dest_reg[0] & L1_q[13]);


--M1L762 is reg_mux:inst27|dr[13]~382 at LC4_C16
--operation mode is normal

M1L762 = H1_dest_reg[3] & (M1L462 # H1_dest_reg[2]) # !H1_dest_reg[3] & M1L662 & (!H1_dest_reg[2]);

--M1L772 is reg_mux:inst27|dr[13]~542 at LC4_C16
--operation mode is normal

M1L772 = H1_dest_reg[3] & (M1L462 # H1_dest_reg[2]) # !H1_dest_reg[3] & M1L662 & (!H1_dest_reg[2]);


--L41_q[13] is reg:inst25|q[13] at LC2_C29
--operation mode is normal

L41_q[13]_lut_out = B1L331;
L41_q[13] = DFFEA(L41_q[13]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L92Q is reg:inst25|q[13]~99 at LC2_C29
--operation mode is normal

L41L92Q = L41_q[13];


--L31_q[13] is reg:inst24|q[13] at LC3_C8
--operation mode is normal

L31_q[13]_lut_out = B1L331;
L31_q[13] = DFFEA(L31_q[13]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L92Q is reg:inst24|q[13]~99 at LC3_C8
--operation mode is normal

L31L92Q = L31_q[13];


--L21_q[13] is reg:inst23|q[13] at LC8_B25
--operation mode is normal

L21_q[13]_lut_out = B1L331;
L21_q[13] = DFFEA(L21_q[13]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L92Q is reg:inst23|q[13]~99 at LC8_B25
--operation mode is normal

L21L92Q = L21_q[13];


--M1L862 is reg_mux:inst27|dr[13]~383 at LC4_C8
--operation mode is normal

M1L862 = H1_dest_reg[0] & (L31_q[13] # H1_dest_reg[1]) # !H1_dest_reg[0] & L21_q[13] & (!H1_dest_reg[1]);

--M1L872 is reg_mux:inst27|dr[13]~543 at LC4_C8
--operation mode is normal

M1L872 = H1_dest_reg[0] & (L31_q[13] # H1_dest_reg[1]) # !H1_dest_reg[0] & L21_q[13] & (!H1_dest_reg[1]);


--L51_q[13] is reg:inst26|q[13] at LC1_C33
--operation mode is normal

L51_q[13]_lut_out = B1L331;
L51_q[13] = DFFEA(L51_q[13]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L92Q is reg:inst26|q[13]~99 at LC1_C33
--operation mode is normal

L51L92Q = L51_q[13];


--M1L962 is reg_mux:inst27|dr[13]~384 at LC1_C8
--operation mode is normal

M1L962 = M1L862 & (L51_q[13] # !H1_dest_reg[1]) # !M1L862 & (H1_dest_reg[1] & L41_q[13]);

--M1L972 is reg_mux:inst27|dr[13]~544 at LC1_C8
--operation mode is normal

M1L972 = M1L862 & (L51_q[13] # !H1_dest_reg[1]) # !M1L862 & (H1_dest_reg[1] & L41_q[13]);


--M1L072 is reg_mux:inst27|dr[13]~385 at LC5_C16
--operation mode is normal

M1L072 = M1L762 & (M1L962 # !H1_dest_reg[2]) # !M1L762 & (H1_dest_reg[2] & M1L262);

--M1L082 is reg_mux:inst27|dr[13]~545 at LC5_C16
--operation mode is normal

M1L082 = M1L762 & (M1L962 # !H1_dest_reg[2]) # !M1L762 & (H1_dest_reg[2] & M1L262);


--N1L401 is bus_mux:inst28|alu_dr[13]~2313 at LC8_C16
--operation mode is normal

N1L401 = N1L301 # N1L201 # M1L072 & N1L911;

--N1L801 is bus_mux:inst28|alu_dr[13]~2384 at LC8_C16
--operation mode is normal

N1L801 = N1L301 # N1L201 # M1L072 & N1L911;


--B1L041 is alu:inst|alu_out[14]~5782 at LC6_F27
--operation mode is normal

B1L041 = H1_alu_func[0] & !H1_alu_func[1] & N1L401 # !H1_alu_func[0] & (B1L931);

--B1L541 is alu:inst|alu_out[14]~5860 at LC6_F27
--operation mode is normal

B1L541 = H1_alu_func[0] & !H1_alu_func[1] & N1L401 # !H1_alu_func[0] & (B1L931);


--B1L272 is alu:inst|temp2~14 at LC4_F27
--operation mode is normal

B1L272 = N1L751 & N1L211;

--B1L182 is alu:inst|temp2~1510 at LC4_F27
--operation mode is normal

B1L182 = N1L751 & N1L211;


--B1L141 is alu:inst|alu_out[14]~5783 at LC7_F27
--operation mode is normal

B1L141 = H1_alu_func[1] & (B1L272 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[15] & (!H1_alu_func[0]);

--B1L641 is alu:inst|alu_out[14]~5861 at LC7_F27
--operation mode is normal

B1L641 = H1_alu_func[1] & (B1L272 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[15] & (!H1_alu_func[0]);


--B1L082 is alu:inst|temp2~30 at LC8_F27
--operation mode is normal

B1L082 = N1L751 # N1L211;

--B1L282 is alu:inst|temp2~1511 at LC8_F27
--operation mode is normal

B1L282 = N1L751 # N1L211;


--B1L241 is alu:inst|alu_out[14]~5784 at LC1_F27
--operation mode is normal

B1L241 = B1L141 & (B1L082 # !H1_alu_func[0]) # !B1L141 & (H1_alu_func[0] & !V9_cs_buffer[16]);

--B1L741 is alu:inst|alu_out[14]~5862 at LC1_F27
--operation mode is normal

B1L741 = B1L141 & (B1L082 # !H1_alu_func[0]) # !B1L141 & (H1_alu_func[0] & !V9_cs_buffer[16]);


--B1L341 is alu:inst|alu_out[14]~5785 at LC5_F27
--operation mode is normal

B1L341 = H1_alu_func[2] & (B1L041) # !H1_alu_func[2] & B1L241;

--B1L841 is alu:inst|alu_out[14]~5863 at LC5_F27
--operation mode is normal

B1L841 = H1_alu_func[2] & (B1L041) # !H1_alu_func[2] & B1L241;


--M1L549 is reg_mux:inst27|sr[12]~366 at LC3_E10
--operation mode is normal

M1L549 = H1_sour_reg[3] & (L9_q[12] # H1_sour_reg[2]) # !H1_sour_reg[3] & L1_q[12] & (!H1_sour_reg[2]);

--M1L559 is reg_mux:inst27|sr[12]~526 at LC3_E10
--operation mode is normal

M1L559 = H1_sour_reg[3] & (L9_q[12] # H1_sour_reg[2]) # !H1_sour_reg[3] & L1_q[12] & (!H1_sour_reg[2]);


--M1L649 is reg_mux:inst27|sr[12]~367 at LC4_E10
--operation mode is normal

M1L649 = M1L549 & (L31_q[12] # !H1_sour_reg[2]) # !M1L549 & (H1_sour_reg[2] & L5_q[12]);

--M1L659 is reg_mux:inst27|sr[12]~527 at LC4_E10
--operation mode is normal

M1L659 = M1L549 & (L31_q[12] # !H1_sour_reg[2]) # !M1L549 & (H1_sour_reg[2] & L5_q[12]);


--M1L749 is reg_mux:inst27|sr[12]~368 at LC4_E13
--operation mode is normal

M1L749 = H1_sour_reg[2] & (L6_q[12] # H1_sour_reg[3]) # !H1_sour_reg[2] & L2_q[12] & (!H1_sour_reg[3]);

--M1L759 is reg_mux:inst27|sr[12]~528 at LC4_E13
--operation mode is normal

M1L759 = H1_sour_reg[2] & (L6_q[12] # H1_sour_reg[3]) # !H1_sour_reg[2] & L2_q[12] & (!H1_sour_reg[3]);


--M1L849 is reg_mux:inst27|sr[12]~369 at LC5_E13
--operation mode is normal

M1L849 = M1L749 & (L41_q[12] # !H1_sour_reg[3]) # !M1L749 & (H1_sour_reg[3] & L01_q[12]);

--M1L859 is reg_mux:inst27|sr[12]~529 at LC5_E13
--operation mode is normal

M1L859 = M1L749 & (L41_q[12] # !H1_sour_reg[3]) # !M1L749 & (H1_sour_reg[3] & L01_q[12]);


--M1L949 is reg_mux:inst27|sr[12]~370 at LC6_E13
--operation mode is normal

M1L949 = H1_sour_reg[2] & (L4_q[12] # H1_sour_reg[3]) # !H1_sour_reg[2] & L61_q[12] & (!H1_sour_reg[3]);

--M1L959 is reg_mux:inst27|sr[12]~530 at LC6_E13
--operation mode is normal

M1L959 = H1_sour_reg[2] & (L4_q[12] # H1_sour_reg[3]) # !H1_sour_reg[2] & L61_q[12] & (!H1_sour_reg[3]);


--M1L059 is reg_mux:inst27|sr[12]~371 at LC7_E13
--operation mode is normal

M1L059 = M1L949 & (L21_q[12] # !H1_sour_reg[3]) # !M1L949 & (H1_sour_reg[3] & L8_q[12]);

--M1L069 is reg_mux:inst27|sr[12]~531 at LC7_E13
--operation mode is normal

M1L069 = M1L949 & (L21_q[12] # !H1_sour_reg[3]) # !M1L949 & (H1_sour_reg[3] & L8_q[12]);


--M1L159 is reg_mux:inst27|sr[12]~372 at LC2_E13
--operation mode is normal

M1L159 = H1_sour_reg[1] & (M1L849 # H1_sour_reg[0]) # !H1_sour_reg[1] & M1L059 & (!H1_sour_reg[0]);

--M1L169 is reg_mux:inst27|sr[12]~532 at LC2_E13
--operation mode is normal

M1L169 = H1_sour_reg[1] & (M1L849 # H1_sour_reg[0]) # !H1_sour_reg[1] & M1L059 & (!H1_sour_reg[0]);


--M1L259 is reg_mux:inst27|sr[12]~373 at LC5_E10
--operation mode is normal

M1L259 = H1_sour_reg[3] & (L11_q[12] # H1_sour_reg[2]) # !H1_sour_reg[3] & L3_q[12] & (!H1_sour_reg[2]);

--M1L269 is reg_mux:inst27|sr[12]~533 at LC5_E10
--operation mode is normal

M1L269 = H1_sour_reg[3] & (L11_q[12] # H1_sour_reg[2]) # !H1_sour_reg[3] & L3_q[12] & (!H1_sour_reg[2]);


--M1L359 is reg_mux:inst27|sr[12]~374 at LC6_E10
--operation mode is normal

M1L359 = M1L259 & (L51_q[12] # !H1_sour_reg[2]) # !M1L259 & (H1_sour_reg[2] & L7_q[12]);

--M1L369 is reg_mux:inst27|sr[12]~534 at LC6_E10
--operation mode is normal

M1L369 = M1L259 & (L51_q[12] # !H1_sour_reg[2]) # !M1L259 & (H1_sour_reg[2] & L7_q[12]);


--M1L459 is reg_mux:inst27|sr[12]~375 at LC8_E10
--operation mode is normal

M1L459 = M1L159 & (M1L359 # !H1_sour_reg[0]) # !M1L159 & (H1_sour_reg[0] & M1L649);

--M1L469 is reg_mux:inst27|sr[12]~535 at LC8_E10
--operation mode is normal

M1L469 = M1L159 & (M1L359 # !H1_sour_reg[0]) # !M1L159 & (H1_sour_reg[0] & M1L649);


--N1L351 is bus_mux:inst28|alu_sr[12]~639 at LC7_G16
--operation mode is normal

N1L351 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L459;

--N1L451 is bus_mux:inst28|alu_sr[12]~657 at LC7_G16
--operation mode is normal

N1L451 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L459;


--B1L911 is alu:inst|alu_out[12]~5786 at LC2_G29
--operation mode is normal

B1L911 = H1_alu_func[1] & (N1L401) # !H1_alu_func[1] & (N1L351 $ N1L69);

--B1L421 is alu:inst|alu_out[12]~5864 at LC2_G29
--operation mode is normal

B1L421 = H1_alu_func[1] & (N1L401) # !H1_alu_func[1] & (N1L351 $ N1L69);


--B1L021 is alu:inst|alu_out[12]~5787 at LC4_G26
--operation mode is normal

B1L021 = H1_alu_func[0] & !H1_alu_func[1] & N1L88 # !H1_alu_func[0] & (B1L911);

--B1L521 is alu:inst|alu_out[12]~5865 at LC4_G26
--operation mode is normal

B1L521 = H1_alu_func[0] & !H1_alu_func[1] & N1L88 # !H1_alu_func[0] & (B1L911);


--V9_cs_buffer[14] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] at LC5_G13
--operation mode is arithmetic

V9_cs_buffer[14] = V6_cs_buffer[14] $ !V9_cout[13];

--V9L34 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~302 at LC5_G13
--operation mode is arithmetic

V9L34 = V6_cs_buffer[14] $ !V9_cout[13];

--V9_cout[14] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[14] at LC5_G13
--operation mode is arithmetic

V9_cout[14] = CARRY(V9_cout[13] # !V6_cs_buffer[14]);


--B1L172 is alu:inst|temp2~12 at LC3_G26
--operation mode is normal

B1L172 = N1L351 & N1L69;

--B1L382 is alu:inst|temp2~1512 at LC3_G26
--operation mode is normal

B1L382 = N1L351 & N1L69;


--V3_cs_buffer[13] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC2_G23
--operation mode is arithmetic

V3_cs_buffer[13] = N1L69 $ N1L351 $ V3_cout[12];

--V3L64 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~294 at LC2_G23
--operation mode is arithmetic

V3L64 = N1L69 $ N1L351 $ V3_cout[12];

--V3_cout[13] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13] at LC2_G23
--operation mode is arithmetic

V3_cout[13] = CARRY(N1L69 & (N1L351 # V3_cout[12]) # !N1L69 & N1L351 & V3_cout[12]);


--B1L121 is alu:inst|alu_out[12]~5788 at LC5_G26
--operation mode is normal

B1L121 = H1_alu_func[1] & (B1L172 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[13] & (!H1_alu_func[0]);

--B1L621 is alu:inst|alu_out[12]~5866 at LC5_G26
--operation mode is normal

B1L621 = H1_alu_func[1] & (B1L172 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[13] & (!H1_alu_func[0]);


--B1L972 is alu:inst|temp2~28 at LC6_G26
--operation mode is normal

B1L972 = N1L351 # N1L69;

--B1L482 is alu:inst|temp2~1513 at LC6_G26
--operation mode is normal

B1L482 = N1L351 # N1L69;


--B1L221 is alu:inst|alu_out[12]~5789 at LC1_G26
--operation mode is normal

B1L221 = B1L121 & (B1L972 # !H1_alu_func[0]) # !B1L121 & (H1_alu_func[0] & !V9_cs_buffer[14]);

--B1L721 is alu:inst|alu_out[12]~5867 at LC1_G26
--operation mode is normal

B1L721 = B1L121 & (B1L972 # !H1_alu_func[0]) # !B1L121 & (H1_alu_func[0] & !V9_cs_buffer[14]);


--B1L321 is alu:inst|alu_out[12]~5790 at LC2_E30
--operation mode is normal

B1L321 = H1_alu_func[2] & (B1L021) # !H1_alu_func[2] & B1L221;

--B1L821 is alu:inst|alu_out[12]~5868 at LC2_E30
--operation mode is normal

B1L821 = H1_alu_func[2] & (B1L021) # !H1_alu_func[2] & B1L221;


--M1L509 is reg_mux:inst27|sr[10]~376 at LC7_D11
--operation mode is normal

M1L509 = H1_sour_reg[3] & (L01_q[10] # H1_sour_reg[2]) # !H1_sour_reg[3] & L2_q[10] & (!H1_sour_reg[2]);

--M1L519 is reg_mux:inst27|sr[10]~536 at LC7_D11
--operation mode is normal

M1L519 = H1_sour_reg[3] & (L01_q[10] # H1_sour_reg[2]) # !H1_sour_reg[3] & L2_q[10] & (!H1_sour_reg[2]);


--M1L609 is reg_mux:inst27|sr[10]~377 at LC2_D11
--operation mode is normal

M1L609 = M1L509 & (L41_q[10] # !H1_sour_reg[2]) # !M1L509 & (H1_sour_reg[2] & L6_q[10]);

--M1L619 is reg_mux:inst27|sr[10]~537 at LC2_D11
--operation mode is normal

M1L619 = M1L509 & (L41_q[10] # !H1_sour_reg[2]) # !M1L509 & (H1_sour_reg[2] & L6_q[10]);


--M1L709 is reg_mux:inst27|sr[10]~378 at LC3_D2
--operation mode is normal

M1L709 = H1_sour_reg[2] & (L5_q[10] # H1_sour_reg[3]) # !H1_sour_reg[2] & L1_q[10] & (!H1_sour_reg[3]);

--M1L719 is reg_mux:inst27|sr[10]~538 at LC3_D2
--operation mode is normal

M1L719 = H1_sour_reg[2] & (L5_q[10] # H1_sour_reg[3]) # !H1_sour_reg[2] & L1_q[10] & (!H1_sour_reg[3]);


--M1L809 is reg_mux:inst27|sr[10]~379 at LC1_D2
--operation mode is normal

M1L809 = M1L709 & (L31_q[10] # !H1_sour_reg[3]) # !M1L709 & (H1_sour_reg[3] & L9_q[10]);

--M1L819 is reg_mux:inst27|sr[10]~539 at LC1_D2
--operation mode is normal

M1L819 = M1L709 & (L31_q[10] # !H1_sour_reg[3]) # !M1L709 & (H1_sour_reg[3] & L9_q[10]);


--M1L909 is reg_mux:inst27|sr[10]~380 at LC5_D14
--operation mode is normal

M1L909 = H1_sour_reg[3] & (L8_q[10] # H1_sour_reg[2]) # !H1_sour_reg[3] & L61_q[10] & (!H1_sour_reg[2]);

--M1L919 is reg_mux:inst27|sr[10]~540 at LC5_D14
--operation mode is normal

M1L919 = H1_sour_reg[3] & (L8_q[10] # H1_sour_reg[2]) # !H1_sour_reg[3] & L61_q[10] & (!H1_sour_reg[2]);


--M1L019 is reg_mux:inst27|sr[10]~381 at LC8_D14
--operation mode is normal

M1L019 = M1L909 & (L21_q[10] # !H1_sour_reg[2]) # !M1L909 & (H1_sour_reg[2] & L4_q[10]);

--M1L029 is reg_mux:inst27|sr[10]~541 at LC8_D14
--operation mode is normal

M1L029 = M1L909 & (L21_q[10] # !H1_sour_reg[2]) # !M1L909 & (H1_sour_reg[2] & L4_q[10]);


--M1L119 is reg_mux:inst27|sr[10]~382 at LC2_D7
--operation mode is normal

M1L119 = H1_sour_reg[0] & (M1L809 # H1_sour_reg[1]) # !H1_sour_reg[0] & M1L019 & (!H1_sour_reg[1]);

--M1L129 is reg_mux:inst27|sr[10]~542 at LC2_D7
--operation mode is normal

M1L129 = H1_sour_reg[0] & (M1L809 # H1_sour_reg[1]) # !H1_sour_reg[0] & M1L019 & (!H1_sour_reg[1]);


--M1L219 is reg_mux:inst27|sr[10]~383 at LC7_D13
--operation mode is normal

M1L219 = H1_sour_reg[2] & (L7_q[10] # H1_sour_reg[3]) # !H1_sour_reg[2] & L3_q[10] & (!H1_sour_reg[3]);

--M1L229 is reg_mux:inst27|sr[10]~543 at LC7_D13
--operation mode is normal

M1L229 = H1_sour_reg[2] & (L7_q[10] # H1_sour_reg[3]) # !H1_sour_reg[2] & L3_q[10] & (!H1_sour_reg[3]);


--M1L319 is reg_mux:inst27|sr[10]~384 at LC2_D13
--operation mode is normal

M1L319 = M1L219 & (L51_q[10] # !H1_sour_reg[3]) # !M1L219 & (H1_sour_reg[3] & L11_q[10]);

--M1L329 is reg_mux:inst27|sr[10]~544 at LC2_D13
--operation mode is normal

M1L329 = M1L219 & (L51_q[10] # !H1_sour_reg[3]) # !M1L219 & (H1_sour_reg[3] & L11_q[10]);


--M1L419 is reg_mux:inst27|sr[10]~385 at LC3_D7
--operation mode is normal

M1L419 = M1L119 & (M1L319 # !H1_sour_reg[1]) # !M1L119 & (H1_sour_reg[1] & M1L609);

--M1L429 is reg_mux:inst27|sr[10]~545 at LC3_D7
--operation mode is normal

M1L429 = M1L119 & (M1L319 # !H1_sour_reg[1]) # !M1L119 & (H1_sour_reg[1] & M1L609);


--N1L941 is bus_mux:inst28|alu_sr[10]~640 at LC1_D7
--operation mode is normal

N1L941 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L419;

--N1L051 is bus_mux:inst28|alu_sr[10]~658 at LC1_D7
--operation mode is normal

N1L051 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L419;


--B1L99 is alu:inst|alu_out[10]~5791 at LC7_G26
--operation mode is normal

B1L99 = H1_alu_func[1] & (N1L88) # !H1_alu_func[1] & (N1L941 $ N1L08);

--B1L401 is alu:inst|alu_out[10]~5869 at LC7_G26
--operation mode is normal

B1L401 = H1_alu_func[1] & (N1L88) # !H1_alu_func[1] & (N1L941 $ N1L08);


--N1L07 is bus_mux:inst28|alu_dr[9]~2314 at LC6_H21
--operation mode is normal

N1L07 = N1L811 & (H1_alu_in_sel[0] & (A1L34) # !H1_alu_in_sel[0] & K1_q[9]);

--N1L47 is bus_mux:inst28|alu_dr[9]~2385 at LC6_H21
--operation mode is normal

N1L47 = N1L811 & (H1_alu_in_sel[0] & (A1L34) # !H1_alu_in_sel[0] & K1_q[9]);


--L6_q[9] is reg:inst17|q[9] at LC1_D34
--operation mode is normal

L6_q[9]_lut_out = B1L39;
L6_q[9] = DFFEA(L6_q[9]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L12Q is reg:inst17|q[9]~100 at LC1_D34
--operation mode is normal

L6L12Q = L6_q[9];


--L5_q[9] is reg:inst16|q[9] at LC1_H36
--operation mode is normal

L5_q[9]_lut_out = B1L39;
L5_q[9] = DFFEA(L5_q[9]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L12Q is reg:inst16|q[9]~100 at LC1_H36
--operation mode is normal

L5L12Q = L5_q[9];


--L4_q[9] is reg:inst15|q[9] at LC3_H36
--operation mode is normal

L4_q[9]_lut_out = B1L39;
L4_q[9] = DFFEA(L4_q[9]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L12Q is reg:inst15|q[9]~100 at LC3_H36
--operation mode is normal

L4L12Q = L4_q[9];


--M1L181 is reg_mux:inst27|dr[9]~386 at LC4_H36
--operation mode is normal

M1L181 = H1_dest_reg[0] & (L5_q[9] # H1_dest_reg[1]) # !H1_dest_reg[0] & L4_q[9] & (!H1_dest_reg[1]);

--M1L191 is reg_mux:inst27|dr[9]~546 at LC4_H36
--operation mode is normal

M1L191 = H1_dest_reg[0] & (L5_q[9] # H1_dest_reg[1]) # !H1_dest_reg[0] & L4_q[9] & (!H1_dest_reg[1]);


--L7_q[9] is reg:inst18|q[9] at LC2_G46
--operation mode is normal

L7_q[9]_lut_out = B1L39;
L7_q[9] = DFFEA(L7_q[9]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L12Q is reg:inst18|q[9]~100 at LC2_G46
--operation mode is normal

L7L12Q = L7_q[9];


--M1L281 is reg_mux:inst27|dr[9]~387 at LC2_H36
--operation mode is normal

M1L281 = M1L181 & (L7_q[9] # !H1_dest_reg[1]) # !M1L181 & (H1_dest_reg[1] & L6_q[9]);

--M1L291 is reg_mux:inst27|dr[9]~547 at LC2_H36
--operation mode is normal

M1L291 = M1L181 & (L7_q[9] # !H1_dest_reg[1]) # !M1L181 & (H1_dest_reg[1] & L6_q[9]);


--L9_q[9] is reg:inst20|q[9] at LC2_H48
--operation mode is normal

L9_q[9]_lut_out = B1L39;
L9_q[9] = DFFEA(L9_q[9]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L12Q is reg:inst20|q[9]~100 at LC2_H48
--operation mode is normal

L9L12Q = L9_q[9];


--L01_q[9] is reg:inst21|q[9] at LC8_H48
--operation mode is normal

L01_q[9]_lut_out = B1L39;
L01_q[9] = DFFEA(L01_q[9]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L12Q is reg:inst21|q[9]~100 at LC8_H48
--operation mode is normal

L01L12Q = L01_q[9];


--L8_q[9] is reg:inst19|q[9] at LC3_H48
--operation mode is normal

L8_q[9]_lut_out = B1L39;
L8_q[9] = DFFEA(L8_q[9]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L12Q is reg:inst19|q[9]~100 at LC3_H48
--operation mode is normal

L8L12Q = L8_q[9];


--M1L381 is reg_mux:inst27|dr[9]~388 at LC2_H34
--operation mode is normal

M1L381 = H1_dest_reg[1] & (L01_q[9] # H1_dest_reg[0]) # !H1_dest_reg[1] & L8_q[9] & (!H1_dest_reg[0]);

--M1L391 is reg_mux:inst27|dr[9]~548 at LC2_H34
--operation mode is normal

M1L391 = H1_dest_reg[1] & (L01_q[9] # H1_dest_reg[0]) # !H1_dest_reg[1] & L8_q[9] & (!H1_dest_reg[0]);


--L11_q[9] is reg:inst22|q[9] at LC4_H52
--operation mode is normal

L11_q[9]_lut_out = B1L39;
L11_q[9] = DFFEA(L11_q[9]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L12Q is reg:inst22|q[9]~100 at LC4_H52
--operation mode is normal

L11L12Q = L11_q[9];


--M1L481 is reg_mux:inst27|dr[9]~389 at LC3_H34
--operation mode is normal

M1L481 = M1L381 & (L11_q[9] # !H1_dest_reg[0]) # !M1L381 & (H1_dest_reg[0] & L9_q[9]);

--M1L491 is reg_mux:inst27|dr[9]~549 at LC3_H34
--operation mode is normal

M1L491 = M1L381 & (L11_q[9] # !H1_dest_reg[0]) # !M1L381 & (H1_dest_reg[0] & L9_q[9]);


--L1_q[9] is reg:inst12|q[9] at LC2_G34
--operation mode is normal

L1_q[9]_lut_out = B1L39;
L1_q[9] = DFFEA(L1_q[9]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L12Q is reg:inst12|q[9]~100 at LC2_G34
--operation mode is normal

L1L12Q = L1_q[9];


--L2_q[9] is reg:inst13|q[9] at LC1_H33
--operation mode is normal

L2_q[9]_lut_out = B1L39;
L2_q[9] = DFFEA(L2_q[9]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L12Q is reg:inst13|q[9]~100 at LC1_H33
--operation mode is normal

L2L12Q = L2_q[9];


--L61_q[9] is reg:inst30|q[9] at LC2_H33
--operation mode is normal

L61_q[9]_lut_out = B1L39;
L61_q[9] = DFFEA(L61_q[9]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L12Q is reg:inst30|q[9]~100 at LC2_H33
--operation mode is normal

L61L12Q = L61_q[9];


--M1L581 is reg_mux:inst27|dr[9]~390 at LC4_H33
--operation mode is normal

M1L581 = H1_dest_reg[1] & (L2_q[9] # H1_dest_reg[0]) # !H1_dest_reg[1] & L61_q[9] & (!H1_dest_reg[0]);

--M1L591 is reg_mux:inst27|dr[9]~550 at LC4_H33
--operation mode is normal

M1L591 = H1_dest_reg[1] & (L2_q[9] # H1_dest_reg[0]) # !H1_dest_reg[1] & L61_q[9] & (!H1_dest_reg[0]);


--L3_q[9] is reg:inst14|q[9] at LC1_G34
--operation mode is normal

L3_q[9]_lut_out = B1L39;
L3_q[9] = DFFEA(L3_q[9]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L12Q is reg:inst14|q[9]~100 at LC1_G34
--operation mode is normal

L3L12Q = L3_q[9];


--M1L681 is reg_mux:inst27|dr[9]~391 at LC3_H33
--operation mode is normal

M1L681 = M1L581 & (L3_q[9] # !H1_dest_reg[0]) # !M1L581 & (H1_dest_reg[0] & L1_q[9]);

--M1L691 is reg_mux:inst27|dr[9]~551 at LC3_H33
--operation mode is normal

M1L691 = M1L581 & (L3_q[9] # !H1_dest_reg[0]) # !M1L581 & (H1_dest_reg[0] & L1_q[9]);


--M1L781 is reg_mux:inst27|dr[9]~392 at LC4_H34
--operation mode is normal

M1L781 = H1_dest_reg[3] & (M1L481 # H1_dest_reg[2]) # !H1_dest_reg[3] & M1L681 & (!H1_dest_reg[2]);

--M1L791 is reg_mux:inst27|dr[9]~552 at LC4_H34
--operation mode is normal

M1L791 = H1_dest_reg[3] & (M1L481 # H1_dest_reg[2]) # !H1_dest_reg[3] & M1L681 & (!H1_dest_reg[2]);


--L41_q[9] is reg:inst25|q[9] at LC1_H35
--operation mode is normal

L41_q[9]_lut_out = B1L39;
L41_q[9] = DFFEA(L41_q[9]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L12Q is reg:inst25|q[9]~100 at LC1_H35
--operation mode is normal

L41L12Q = L41_q[9];


--L31_q[9] is reg:inst24|q[9] at LC1_G49
--operation mode is normal

L31_q[9]_lut_out = B1L39;
L31_q[9] = DFFEA(L31_q[9]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L12Q is reg:inst24|q[9]~100 at LC1_G49
--operation mode is normal

L31L12Q = L31_q[9];


--L21_q[9] is reg:inst23|q[9] at LC5_G49
--operation mode is normal

L21_q[9]_lut_out = B1L39;
L21_q[9] = DFFEA(L21_q[9]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L12Q is reg:inst23|q[9]~100 at LC5_G49
--operation mode is normal

L21L12Q = L21_q[9];


--M1L881 is reg_mux:inst27|dr[9]~393 at LC3_H35
--operation mode is normal

M1L881 = H1_dest_reg[0] & (L31_q[9] # H1_dest_reg[1]) # !H1_dest_reg[0] & L21_q[9] & (!H1_dest_reg[1]);

--M1L891 is reg_mux:inst27|dr[9]~553 at LC3_H35
--operation mode is normal

M1L891 = H1_dest_reg[0] & (L31_q[9] # H1_dest_reg[1]) # !H1_dest_reg[0] & L21_q[9] & (!H1_dest_reg[1]);


--L51_q[9] is reg:inst26|q[9] at LC4_H35
--operation mode is normal

L51_q[9]_lut_out = B1L39;
L51_q[9] = DFFEA(L51_q[9]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L12Q is reg:inst26|q[9]~100 at LC4_H35
--operation mode is normal

L51L12Q = L51_q[9];


--M1L981 is reg_mux:inst27|dr[9]~394 at LC2_H35
--operation mode is normal

M1L981 = M1L881 & (L51_q[9] # !H1_dest_reg[1]) # !M1L881 & (H1_dest_reg[1] & L41_q[9]);

--M1L991 is reg_mux:inst27|dr[9]~554 at LC2_H35
--operation mode is normal

M1L991 = M1L881 & (L51_q[9] # !H1_dest_reg[1]) # !M1L881 & (H1_dest_reg[1] & L41_q[9]);


--M1L091 is reg_mux:inst27|dr[9]~395 at LC6_H34
--operation mode is normal

M1L091 = M1L781 & (M1L981 # !H1_dest_reg[2]) # !M1L781 & (H1_dest_reg[2] & M1L281);

--M1L002 is reg_mux:inst27|dr[9]~555 at LC6_H34
--operation mode is normal

M1L002 = M1L781 & (M1L981 # !H1_dest_reg[2]) # !M1L781 & (H1_dest_reg[2] & M1L281);


--N1L17 is bus_mux:inst28|alu_dr[9]~2315 at LC7_H34
--operation mode is normal

N1L17 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L091;

--N1L57 is bus_mux:inst28|alu_dr[9]~2386 at LC7_H34
--operation mode is normal

N1L57 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L091;


--N1L27 is bus_mux:inst28|alu_dr[9]~2316 at LC5_H34
--operation mode is normal

N1L27 = N1L17 # N1L07 # K1_q[9] & N1L021;

--N1L67 is bus_mux:inst28|alu_dr[9]~2387 at LC5_H34
--operation mode is normal

N1L67 = N1L17 # N1L07 # K1_q[9] & N1L021;


--B1L001 is alu:inst|alu_out[10]~5792 at LC2_G26
--operation mode is normal

B1L001 = H1_alu_func[0] & !H1_alu_func[1] & N1L27 # !H1_alu_func[0] & (B1L99);

--B1L501 is alu:inst|alu_out[10]~5870 at LC2_G26
--operation mode is normal

B1L501 = H1_alu_func[0] & !H1_alu_func[1] & N1L27 # !H1_alu_func[0] & (B1L99);


--V9_cs_buffer[12] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] at LC3_G13
--operation mode is arithmetic

V9_cs_buffer[12] = V6_cs_buffer[12] $ !V9_cout[11];

--V9L93 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~303 at LC3_G13
--operation mode is arithmetic

V9L93 = V6_cs_buffer[12] $ !V9_cout[11];

--V9_cout[12] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[12] at LC3_G13
--operation mode is arithmetic

V9_cout[12] = CARRY(V9_cout[11] # !V6_cs_buffer[12]);


--B1L072 is alu:inst|temp2~10 at LC5_D31
--operation mode is normal

B1L072 = N1L941 & N1L08;

--B1L582 is alu:inst|temp2~1514 at LC5_D31
--operation mode is normal

B1L582 = N1L941 & N1L08;


--V3_cs_buffer[11] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC8_G21
--operation mode is arithmetic

V3_cs_buffer[11] = N1L08 $ N1L941 $ V3_cout[10];

--V3L24 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~295 at LC8_G21
--operation mode is arithmetic

V3L24 = N1L08 $ N1L941 $ V3_cout[10];

--V3_cout[11] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[11] at LC8_G21
--operation mode is arithmetic

V3_cout[11] = CARRY(N1L08 & (N1L941 # V3_cout[10]) # !N1L08 & N1L941 & V3_cout[10]);


--B1L101 is alu:inst|alu_out[10]~5793 at LC6_D31
--operation mode is normal

B1L101 = H1_alu_func[1] & (B1L072 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[11] & (!H1_alu_func[0]);

--B1L601 is alu:inst|alu_out[10]~5871 at LC6_D31
--operation mode is normal

B1L601 = H1_alu_func[1] & (B1L072 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[11] & (!H1_alu_func[0]);


--B1L872 is alu:inst|temp2~26 at LC8_D31
--operation mode is normal

B1L872 = N1L941 # N1L08;

--B1L682 is alu:inst|temp2~1515 at LC8_D31
--operation mode is normal

B1L682 = N1L941 # N1L08;


--B1L201 is alu:inst|alu_out[10]~5794 at LC1_D31
--operation mode is normal

B1L201 = B1L101 & (B1L872 # !H1_alu_func[0]) # !B1L101 & (H1_alu_func[0] & !V9_cs_buffer[12]);

--B1L701 is alu:inst|alu_out[10]~5872 at LC1_D31
--operation mode is normal

B1L701 = B1L101 & (B1L872 # !H1_alu_func[0]) # !B1L101 & (H1_alu_func[0] & !V9_cs_buffer[12]);


--B1L301 is alu:inst|alu_out[10]~5795 at LC2_D31
--operation mode is normal

B1L301 = H1_alu_func[2] & (B1L001) # !H1_alu_func[2] & B1L201;

--B1L801 is alu:inst|alu_out[10]~5873 at LC2_D31
--operation mode is normal

B1L801 = H1_alu_func[2] & (B1L001) # !H1_alu_func[2] & B1L201;


--N1L26 is bus_mux:inst28|alu_dr[8]~2317 at LC8_H21
--operation mode is normal

N1L26 = N1L811 & (H1_alu_in_sel[0] & (A1L44) # !H1_alu_in_sel[0] & K1_q[8]);

--N1L66 is bus_mux:inst28|alu_dr[8]~2388 at LC8_H21
--operation mode is normal

N1L66 = N1L811 & (H1_alu_in_sel[0] & (A1L44) # !H1_alu_in_sel[0] & K1_q[8]);


--L5_q[8] is reg:inst16|q[8] at LC7_H41
--operation mode is normal

L5_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L5_q[8] = DFFEA(L5_q[8]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L91Q is reg:inst16|q[8]~101 at LC7_H41
--operation mode is normal

L5L91Q = L5_q[8];


--L9_q[8] is reg:inst20|q[8] at LC1_H30
--operation mode is normal

L9_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L9_q[8] = DFFEA(L9_q[8]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L91Q is reg:inst20|q[8]~101 at LC1_H30
--operation mode is normal

L9L91Q = L9_q[8];


--L1_q[8] is reg:inst12|q[8] at LC2_H30
--operation mode is normal

L1_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L1_q[8] = DFFEA(L1_q[8]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L91Q is reg:inst12|q[8]~101 at LC2_H30
--operation mode is normal

L1L91Q = L1_q[8];


--M1L161 is reg_mux:inst27|dr[8]~396 at LC4_H30
--operation mode is normal

M1L161 = H1_dest_reg[3] & (L9_q[8] # H1_dest_reg[2]) # !H1_dest_reg[3] & L1_q[8] & (!H1_dest_reg[2]);

--M1L171 is reg_mux:inst27|dr[8]~556 at LC4_H30
--operation mode is normal

M1L171 = H1_dest_reg[3] & (L9_q[8] # H1_dest_reg[2]) # !H1_dest_reg[3] & L1_q[8] & (!H1_dest_reg[2]);


--L31_q[8] is reg:inst24|q[8] at LC3_H41
--operation mode is normal

L31_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L31_q[8] = DFFEA(L31_q[8]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L91Q is reg:inst24|q[8]~101 at LC3_H41
--operation mode is normal

L31L91Q = L31_q[8];


--M1L261 is reg_mux:inst27|dr[8]~397 at LC8_H30
--operation mode is normal

M1L261 = M1L161 & (L31_q[8] # !H1_dest_reg[2]) # !M1L161 & (H1_dest_reg[2] & L5_q[8]);

--M1L271 is reg_mux:inst27|dr[8]~557 at LC8_H30
--operation mode is normal

M1L271 = M1L161 & (L31_q[8] # !H1_dest_reg[2]) # !M1L161 & (H1_dest_reg[2] & L5_q[8]);


--L01_q[8] is reg:inst21|q[8] at LC3_H43
--operation mode is normal

L01_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L01_q[8] = DFFEA(L01_q[8]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L91Q is reg:inst21|q[8]~101 at LC3_H43
--operation mode is normal

L01L91Q = L01_q[8];


--L6_q[8] is reg:inst17|q[8] at LC7_H43
--operation mode is normal

L6_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L6_q[8] = DFFEA(L6_q[8]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L91Q is reg:inst17|q[8]~101 at LC7_H43
--operation mode is normal

L6L91Q = L6_q[8];


--L2_q[8] is reg:inst13|q[8] at LC1_H43
--operation mode is normal

L2_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L2_q[8] = DFFEA(L2_q[8]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L91Q is reg:inst13|q[8]~101 at LC1_H43
--operation mode is normal

L2L91Q = L2_q[8];


--M1L361 is reg_mux:inst27|dr[8]~398 at LC2_H29
--operation mode is normal

M1L361 = H1_dest_reg[2] & (L6_q[8] # H1_dest_reg[3]) # !H1_dest_reg[2] & L2_q[8] & (!H1_dest_reg[3]);

--M1L371 is reg_mux:inst27|dr[8]~558 at LC2_H29
--operation mode is normal

M1L371 = H1_dest_reg[2] & (L6_q[8] # H1_dest_reg[3]) # !H1_dest_reg[2] & L2_q[8] & (!H1_dest_reg[3]);


--L41_q[8] is reg:inst25|q[8] at LC6_H43
--operation mode is normal

L41_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L41_q[8] = DFFEA(L41_q[8]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L91Q is reg:inst25|q[8]~101 at LC6_H43
--operation mode is normal

L41L91Q = L41_q[8];


--M1L461 is reg_mux:inst27|dr[8]~399 at LC3_H29
--operation mode is normal

M1L461 = M1L361 & (L41_q[8] # !H1_dest_reg[3]) # !M1L361 & (H1_dest_reg[3] & L01_q[8]);

--M1L471 is reg_mux:inst27|dr[8]~559 at LC3_H29
--operation mode is normal

M1L471 = M1L361 & (L41_q[8] # !H1_dest_reg[3]) # !M1L361 & (H1_dest_reg[3] & L01_q[8]);


--L8_q[8] is reg:inst19|q[8] at LC6_H41
--operation mode is normal

L8_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L8_q[8] = DFFEA(L8_q[8]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L91Q is reg:inst19|q[8]~101 at LC6_H41
--operation mode is normal

L8L91Q = L8_q[8];


--L4_q[8] is reg:inst15|q[8] at LC1_H28
--operation mode is normal

L4_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L4_q[8] = DFFEA(L4_q[8]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L91Q is reg:inst15|q[8]~101 at LC1_H28
--operation mode is normal

L4L91Q = L4_q[8];


--L61_q[8] is reg:inst30|q[8] at LC2_H28
--operation mode is normal

L61_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L61_q[8] = DFFEA(L61_q[8]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L91Q is reg:inst30|q[8]~101 at LC2_H28
--operation mode is normal

L61L91Q = L61_q[8];


--M1L561 is reg_mux:inst27|dr[8]~400 at LC6_H28
--operation mode is normal

M1L561 = H1_dest_reg[2] & (L4_q[8] # H1_dest_reg[3]) # !H1_dest_reg[2] & L61_q[8] & (!H1_dest_reg[3]);

--M1L571 is reg_mux:inst27|dr[8]~560 at LC6_H28
--operation mode is normal

M1L571 = H1_dest_reg[2] & (L4_q[8] # H1_dest_reg[3]) # !H1_dest_reg[2] & L61_q[8] & (!H1_dest_reg[3]);


--L21_q[8] is reg:inst23|q[8] at LC5_H41
--operation mode is normal

L21_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L21_q[8] = DFFEA(L21_q[8]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L91Q is reg:inst23|q[8]~101 at LC5_H41
--operation mode is normal

L21L91Q = L21_q[8];


--M1L661 is reg_mux:inst27|dr[8]~401 at LC5_H29
--operation mode is normal

M1L661 = M1L561 & (L21_q[8] # !H1_dest_reg[3]) # !M1L561 & (H1_dest_reg[3] & L8_q[8]);

--M1L671 is reg_mux:inst27|dr[8]~561 at LC5_H29
--operation mode is normal

M1L671 = M1L561 & (L21_q[8] # !H1_dest_reg[3]) # !M1L561 & (H1_dest_reg[3] & L8_q[8]);


--M1L761 is reg_mux:inst27|dr[8]~402 at LC6_H29
--operation mode is normal

M1L761 = H1_dest_reg[1] & (M1L461 # H1_dest_reg[0]) # !H1_dest_reg[1] & M1L661 & (!H1_dest_reg[0]);

--M1L771 is reg_mux:inst27|dr[8]~562 at LC6_H29
--operation mode is normal

M1L771 = H1_dest_reg[1] & (M1L461 # H1_dest_reg[0]) # !H1_dest_reg[1] & M1L661 & (!H1_dest_reg[0]);


--L7_q[8] is reg:inst18|q[8] at LC1_H31
--operation mode is normal

L7_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L7_q[8] = DFFEA(L7_q[8]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L91Q is reg:inst18|q[8]~101 at LC1_H31
--operation mode is normal

L7L91Q = L7_q[8];


--L11_q[8] is reg:inst22|q[8] at LC2_H31
--operation mode is normal

L11_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L11_q[8] = DFFEA(L11_q[8]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L91Q is reg:inst22|q[8]~101 at LC2_H31
--operation mode is normal

L11L91Q = L11_q[8];


--L3_q[8] is reg:inst14|q[8] at LC4_H41
--operation mode is normal

L3_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L3_q[8] = DFFEA(L3_q[8]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L91Q is reg:inst14|q[8]~101 at LC4_H41
--operation mode is normal

L3L91Q = L3_q[8];


--M1L861 is reg_mux:inst27|dr[8]~403 at LC4_H31
--operation mode is normal

M1L861 = H1_dest_reg[3] & (L11_q[8] # H1_dest_reg[2]) # !H1_dest_reg[3] & L3_q[8] & (!H1_dest_reg[2]);

--M1L871 is reg_mux:inst27|dr[8]~563 at LC4_H31
--operation mode is normal

M1L871 = H1_dest_reg[3] & (L11_q[8] # H1_dest_reg[2]) # !H1_dest_reg[3] & L3_q[8] & (!H1_dest_reg[2]);


--L51_q[8] is reg:inst26|q[8] at LC8_H41
--operation mode is normal

L51_q[8]_lut_out = H1_alu_func[2] & B1L08 # !H1_alu_func[2] & (B1L28);
L51_q[8] = DFFEA(L51_q[8]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L91Q is reg:inst26|q[8]~101 at LC8_H41
--operation mode is normal

L51L91Q = L51_q[8];


--M1L961 is reg_mux:inst27|dr[8]~404 at LC7_H31
--operation mode is normal

M1L961 = M1L861 & (L51_q[8] # !H1_dest_reg[2]) # !M1L861 & (H1_dest_reg[2] & L7_q[8]);

--M1L971 is reg_mux:inst27|dr[8]~564 at LC7_H31
--operation mode is normal

M1L971 = M1L861 & (L51_q[8] # !H1_dest_reg[2]) # !M1L861 & (H1_dest_reg[2] & L7_q[8]);


--M1L071 is reg_mux:inst27|dr[8]~405 at LC7_H29
--operation mode is normal

M1L071 = M1L761 & (M1L961 # !H1_dest_reg[0]) # !M1L761 & (H1_dest_reg[0] & M1L261);

--M1L081 is reg_mux:inst27|dr[8]~565 at LC7_H29
--operation mode is normal

M1L081 = M1L761 & (M1L961 # !H1_dest_reg[0]) # !M1L761 & (H1_dest_reg[0] & M1L261);


--N1L36 is bus_mux:inst28|alu_dr[8]~2318 at LC8_H29
--operation mode is normal

N1L36 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L071;

--N1L76 is bus_mux:inst28|alu_dr[8]~2389 at LC8_H29
--operation mode is normal

N1L76 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L071;


--N1L46 is bus_mux:inst28|alu_dr[8]~2319 at LC4_H29
--operation mode is normal

N1L46 = N1L36 # N1L26 # K1_q[8] & N1L021;

--N1L86 is bus_mux:inst28|alu_dr[8]~2390 at LC4_H29
--operation mode is normal

N1L86 = N1L36 # N1L26 # K1_q[8] & N1L021;


--M1L568 is reg_mux:inst27|sr[8]~386 at LC6_H30
--operation mode is normal

M1L568 = H1_sour_reg[3] & (L9_q[8] # H1_sour_reg[2]) # !H1_sour_reg[3] & L1_q[8] & (!H1_sour_reg[2]);

--M1L578 is reg_mux:inst27|sr[8]~546 at LC6_H30
--operation mode is normal

M1L578 = H1_sour_reg[3] & (L9_q[8] # H1_sour_reg[2]) # !H1_sour_reg[3] & L1_q[8] & (!H1_sour_reg[2]);


--M1L668 is reg_mux:inst27|sr[8]~387 at LC3_H30
--operation mode is normal

M1L668 = M1L568 & (L31_q[8] # !H1_sour_reg[2]) # !M1L568 & (H1_sour_reg[2] & L5_q[8]);

--M1L678 is reg_mux:inst27|sr[8]~547 at LC3_H30
--operation mode is normal

M1L678 = M1L568 & (L31_q[8] # !H1_sour_reg[2]) # !M1L568 & (H1_sour_reg[2] & L5_q[8]);


--M1L768 is reg_mux:inst27|sr[8]~388 at LC4_H43
--operation mode is normal

M1L768 = H1_sour_reg[2] & (L6_q[8] # H1_sour_reg[3]) # !H1_sour_reg[2] & L2_q[8] & (!H1_sour_reg[3]);

--M1L778 is reg_mux:inst27|sr[8]~548 at LC4_H43
--operation mode is normal

M1L778 = H1_sour_reg[2] & (L6_q[8] # H1_sour_reg[3]) # !H1_sour_reg[2] & L2_q[8] & (!H1_sour_reg[3]);


--M1L868 is reg_mux:inst27|sr[8]~389 at LC5_H43
--operation mode is normal

M1L868 = M1L768 & (L41_q[8] # !H1_sour_reg[3]) # !M1L768 & (H1_sour_reg[3] & L01_q[8]);

--M1L878 is reg_mux:inst27|sr[8]~549 at LC5_H43
--operation mode is normal

M1L878 = M1L768 & (L41_q[8] # !H1_sour_reg[3]) # !M1L768 & (H1_sour_reg[3] & L01_q[8]);


--M1L968 is reg_mux:inst27|sr[8]~390 at LC4_H28
--operation mode is normal

M1L968 = H1_sour_reg[2] & (L4_q[8] # H1_sour_reg[3]) # !H1_sour_reg[2] & L61_q[8] & (!H1_sour_reg[3]);

--M1L978 is reg_mux:inst27|sr[8]~550 at LC4_H28
--operation mode is normal

M1L978 = H1_sour_reg[2] & (L4_q[8] # H1_sour_reg[3]) # !H1_sour_reg[2] & L61_q[8] & (!H1_sour_reg[3]);


--M1L078 is reg_mux:inst27|sr[8]~391 at LC5_H28
--operation mode is normal

M1L078 = M1L968 & (L21_q[8] # !H1_sour_reg[3]) # !M1L968 & (H1_sour_reg[3] & L8_q[8]);

--M1L088 is reg_mux:inst27|sr[8]~551 at LC5_H28
--operation mode is normal

M1L088 = M1L968 & (L21_q[8] # !H1_sour_reg[3]) # !M1L968 & (H1_sour_reg[3] & L8_q[8]);


--M1L178 is reg_mux:inst27|sr[8]~392 at LC7_H28
--operation mode is normal

M1L178 = H1_sour_reg[1] & (M1L868 # H1_sour_reg[0]) # !H1_sour_reg[1] & M1L078 & (!H1_sour_reg[0]);

--M1L188 is reg_mux:inst27|sr[8]~552 at LC7_H28
--operation mode is normal

M1L188 = H1_sour_reg[1] & (M1L868 # H1_sour_reg[0]) # !H1_sour_reg[1] & M1L078 & (!H1_sour_reg[0]);


--M1L278 is reg_mux:inst27|sr[8]~393 at LC5_H31
--operation mode is normal

M1L278 = H1_sour_reg[3] & (L11_q[8] # H1_sour_reg[2]) # !H1_sour_reg[3] & L3_q[8] & (!H1_sour_reg[2]);

--M1L288 is reg_mux:inst27|sr[8]~553 at LC5_H31
--operation mode is normal

M1L288 = H1_sour_reg[3] & (L11_q[8] # H1_sour_reg[2]) # !H1_sour_reg[3] & L3_q[8] & (!H1_sour_reg[2]);


--M1L378 is reg_mux:inst27|sr[8]~394 at LC8_H31
--operation mode is normal

M1L378 = M1L278 & (L51_q[8] # !H1_sour_reg[2]) # !M1L278 & (H1_sour_reg[2] & L7_q[8]);

--M1L388 is reg_mux:inst27|sr[8]~554 at LC8_H31
--operation mode is normal

M1L388 = M1L278 & (L51_q[8] # !H1_sour_reg[2]) # !M1L278 & (H1_sour_reg[2] & L7_q[8]);


--M1L478 is reg_mux:inst27|sr[8]~395 at LC1_H21
--operation mode is normal

M1L478 = M1L178 & (M1L378 # !H1_sour_reg[0]) # !M1L178 & (H1_sour_reg[0] & M1L668);

--M1L488 is reg_mux:inst27|sr[8]~555 at LC1_H21
--operation mode is normal

M1L488 = M1L178 & (M1L378 # !H1_sour_reg[0]) # !M1L178 & (H1_sour_reg[0] & M1L668);


--N1L541 is bus_mux:inst28|alu_sr[8]~641 at LC6_G16
--operation mode is normal

N1L541 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L478;

--N1L641 is bus_mux:inst28|alu_sr[8]~659 at LC6_G16
--operation mode is normal

N1L641 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L478;


--B1L97 is alu:inst|alu_out[8]~5796 at LC2_I37
--operation mode is normal

B1L97 = H1_alu_func[1] & (N1L27) # !H1_alu_func[1] & (N1L541 $ N1L46);

--B1L48 is alu:inst|alu_out[8]~5874 at LC2_I37
--operation mode is normal

B1L48 = H1_alu_func[1] & (N1L27) # !H1_alu_func[1] & (N1L541 $ N1L46);


--N1L45 is bus_mux:inst28|alu_dr[7]~2320 at LC2_H21
--operation mode is normal

N1L45 = N1L811 & (H1_alu_in_sel[0] & (A1L54) # !H1_alu_in_sel[0] & K1_q[7]);

--N1L85 is bus_mux:inst28|alu_dr[7]~2391 at LC2_H21
--operation mode is normal

N1L85 = N1L811 & (H1_alu_in_sel[0] & (A1L54) # !H1_alu_in_sel[0] & K1_q[7]);


--L01_q[7] is reg:inst21|q[7] at LC4_I14
--operation mode is normal

L01_q[7]_lut_out = B1L37;
L01_q[7] = DFFEA(L01_q[7]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L71Q is reg:inst21|q[7]~102 at LC4_I14
--operation mode is normal

L01L71Q = L01_q[7];


--L9_q[7] is reg:inst20|q[7] at LC1_K9
--operation mode is normal

L9_q[7]_lut_out = B1L37;
L9_q[7] = DFFEA(L9_q[7]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L71Q is reg:inst20|q[7]~102 at LC1_K9
--operation mode is normal

L9L71Q = L9_q[7];


--L8_q[7] is reg:inst19|q[7] at LC5_I14
--operation mode is normal

L8_q[7]_lut_out = B1L37;
L8_q[7] = DFFEA(L8_q[7]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L71Q is reg:inst19|q[7]~102 at LC5_I14
--operation mode is normal

L8L71Q = L8_q[7];


--M1L141 is reg_mux:inst27|dr[7]~406 at LC6_I14
--operation mode is normal

M1L141 = H1_dest_reg[0] & (L9_q[7] # H1_dest_reg[1]) # !H1_dest_reg[0] & L8_q[7] & (!H1_dest_reg[1]);

--M1L151 is reg_mux:inst27|dr[7]~566 at LC6_I14
--operation mode is normal

M1L151 = H1_dest_reg[0] & (L9_q[7] # H1_dest_reg[1]) # !H1_dest_reg[0] & L8_q[7] & (!H1_dest_reg[1]);


--L11_q[7] is reg:inst22|q[7] at LC2_I40
--operation mode is normal

L11_q[7]_lut_out = B1L37;
L11_q[7] = DFFEA(L11_q[7]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L71Q is reg:inst22|q[7]~102 at LC2_I40
--operation mode is normal

L11L71Q = L11_q[7];


--M1L241 is reg_mux:inst27|dr[7]~407 at LC2_I14
--operation mode is normal

M1L241 = M1L141 & (L11_q[7] # !H1_dest_reg[1]) # !M1L141 & (H1_dest_reg[1] & L01_q[7]);

--M1L251 is reg_mux:inst27|dr[7]~567 at LC2_I14
--operation mode is normal

M1L251 = M1L141 & (L11_q[7] # !H1_dest_reg[1]) # !M1L141 & (H1_dest_reg[1] & L01_q[7]);


--L5_q[7] is reg:inst16|q[7] at LC8_I16
--operation mode is normal

L5_q[7]_lut_out = B1L37;
L5_q[7] = DFFEA(L5_q[7]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L71Q is reg:inst16|q[7]~102 at LC8_I16
--operation mode is normal

L5L71Q = L5_q[7];


--L6_q[7] is reg:inst17|q[7] at LC4_I16
--operation mode is normal

L6_q[7]_lut_out = B1L37;
L6_q[7] = DFFEA(L6_q[7]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L71Q is reg:inst17|q[7]~102 at LC4_I16
--operation mode is normal

L6L71Q = L6_q[7];


--L4_q[7] is reg:inst15|q[7] at LC8_I21
--operation mode is normal

L4_q[7]_lut_out = B1L37;
L4_q[7] = DFFEA(L4_q[7]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L71Q is reg:inst15|q[7]~102 at LC8_I21
--operation mode is normal

L4L71Q = L4_q[7];


--M1L341 is reg_mux:inst27|dr[7]~408 at LC2_I11
--operation mode is normal

M1L341 = H1_dest_reg[1] & (L6_q[7] # H1_dest_reg[0]) # !H1_dest_reg[1] & L4_q[7] & (!H1_dest_reg[0]);

--M1L351 is reg_mux:inst27|dr[7]~568 at LC2_I11
--operation mode is normal

M1L351 = H1_dest_reg[1] & (L6_q[7] # H1_dest_reg[0]) # !H1_dest_reg[1] & L4_q[7] & (!H1_dest_reg[0]);


--L7_q[7] is reg:inst18|q[7] at LC7_I16
--operation mode is normal

L7_q[7]_lut_out = B1L37;
L7_q[7] = DFFEA(L7_q[7]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L71Q is reg:inst18|q[7]~102 at LC7_I16
--operation mode is normal

L7L71Q = L7_q[7];


--M1L441 is reg_mux:inst27|dr[7]~409 at LC3_I11
--operation mode is normal

M1L441 = M1L341 & (L7_q[7] # !H1_dest_reg[0]) # !M1L341 & (H1_dest_reg[0] & L5_q[7]);

--M1L451 is reg_mux:inst27|dr[7]~569 at LC3_I11
--operation mode is normal

M1L451 = M1L341 & (L7_q[7] # !H1_dest_reg[0]) # !M1L341 & (H1_dest_reg[0] & L5_q[7]);


--L2_q[7] is reg:inst13|q[7] at LC1_I38
--operation mode is normal

L2_q[7]_lut_out = B1L37;
L2_q[7] = DFFEA(L2_q[7]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L71Q is reg:inst13|q[7]~102 at LC1_I38
--operation mode is normal

L2L71Q = L2_q[7];


--L1_q[7] is reg:inst12|q[7] at LC3_I10
--operation mode is normal

L1_q[7]_lut_out = B1L37;
L1_q[7] = DFFEA(L1_q[7]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L71Q is reg:inst12|q[7]~102 at LC3_I10
--operation mode is normal

L1L71Q = L1_q[7];


--L61_q[7] is reg:inst30|q[7] at LC5_I10
--operation mode is normal

L61_q[7]_lut_out = B1L37;
L61_q[7] = DFFEA(L61_q[7]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L71Q is reg:inst30|q[7]~102 at LC5_I10
--operation mode is normal

L61L71Q = L61_q[7];


--M1L541 is reg_mux:inst27|dr[7]~410 at LC1_I10
--operation mode is normal

M1L541 = H1_dest_reg[0] & (L1_q[7] # H1_dest_reg[1]) # !H1_dest_reg[0] & L61_q[7] & (!H1_dest_reg[1]);

--M1L551 is reg_mux:inst27|dr[7]~570 at LC1_I10
--operation mode is normal

M1L551 = H1_dest_reg[0] & (L1_q[7] # H1_dest_reg[1]) # !H1_dest_reg[0] & L61_q[7] & (!H1_dest_reg[1]);


--L3_q[7] is reg:inst14|q[7] at LC8_K9
--operation mode is normal

L3_q[7]_lut_out = B1L37;
L3_q[7] = DFFEA(L3_q[7]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L71Q is reg:inst14|q[7]~102 at LC8_K9
--operation mode is normal

L3L71Q = L3_q[7];


--M1L641 is reg_mux:inst27|dr[7]~411 at LC4_I11
--operation mode is normal

M1L641 = M1L541 & (L3_q[7] # !H1_dest_reg[1]) # !M1L541 & (H1_dest_reg[1] & L2_q[7]);

--M1L651 is reg_mux:inst27|dr[7]~571 at LC4_I11
--operation mode is normal

M1L651 = M1L541 & (L3_q[7] # !H1_dest_reg[1]) # !M1L541 & (H1_dest_reg[1] & L2_q[7]);


--M1L741 is reg_mux:inst27|dr[7]~412 at LC5_I11
--operation mode is normal

M1L741 = H1_dest_reg[2] & (M1L441 # H1_dest_reg[3]) # !H1_dest_reg[2] & M1L641 & (!H1_dest_reg[3]);

--M1L751 is reg_mux:inst27|dr[7]~572 at LC5_I11
--operation mode is normal

M1L751 = H1_dest_reg[2] & (M1L441 # H1_dest_reg[3]) # !H1_dest_reg[2] & M1L641 & (!H1_dest_reg[3]);


--L31_q[7] is reg:inst24|q[7] at LC4_I17
--operation mode is normal

L31_q[7]_lut_out = B1L37;
L31_q[7] = DFFEA(L31_q[7]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L71Q is reg:inst24|q[7]~102 at LC4_I17
--operation mode is normal

L31L71Q = L31_q[7];


--L41_q[7] is reg:inst25|q[7] at LC4_K9
--operation mode is normal

L41_q[7]_lut_out = B1L37;
L41_q[7] = DFFEA(L41_q[7]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L71Q is reg:inst25|q[7]~102 at LC4_K9
--operation mode is normal

L41L71Q = L41_q[7];


--L21_q[7] is reg:inst23|q[7] at LC6_K9
--operation mode is normal

L21_q[7]_lut_out = B1L37;
L21_q[7] = DFFEA(L21_q[7]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L71Q is reg:inst23|q[7]~102 at LC6_K9
--operation mode is normal

L21L71Q = L21_q[7];


--M1L841 is reg_mux:inst27|dr[7]~413 at LC5_I17
--operation mode is normal

M1L841 = H1_dest_reg[1] & (L41_q[7] # H1_dest_reg[0]) # !H1_dest_reg[1] & L21_q[7] & (!H1_dest_reg[0]);

--M1L851 is reg_mux:inst27|dr[7]~573 at LC5_I17
--operation mode is normal

M1L851 = H1_dest_reg[1] & (L41_q[7] # H1_dest_reg[0]) # !H1_dest_reg[1] & L21_q[7] & (!H1_dest_reg[0]);


--L51_q[7] is reg:inst26|q[7] at LC6_I17
--operation mode is normal

L51_q[7]_lut_out = B1L37;
L51_q[7] = DFFEA(L51_q[7]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L71Q is reg:inst26|q[7]~102 at LC6_I17
--operation mode is normal

L51L71Q = L51_q[7];


--M1L941 is reg_mux:inst27|dr[7]~414 at LC1_I17
--operation mode is normal

M1L941 = M1L841 & (L51_q[7] # !H1_dest_reg[0]) # !M1L841 & (H1_dest_reg[0] & L31_q[7]);

--M1L951 is reg_mux:inst27|dr[7]~574 at LC1_I17
--operation mode is normal

M1L951 = M1L841 & (L51_q[7] # !H1_dest_reg[0]) # !M1L841 & (H1_dest_reg[0] & L31_q[7]);


--M1L051 is reg_mux:inst27|dr[7]~415 at LC6_I11
--operation mode is normal

M1L051 = M1L741 & (M1L941 # !H1_dest_reg[3]) # !M1L741 & (H1_dest_reg[3] & M1L241);

--M1L061 is reg_mux:inst27|dr[7]~575 at LC6_I11
--operation mode is normal

M1L061 = M1L741 & (M1L941 # !H1_dest_reg[3]) # !M1L741 & (H1_dest_reg[3] & M1L241);


--N1L55 is bus_mux:inst28|alu_dr[7]~2321 at LC8_I11
--operation mode is normal

N1L55 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L051;

--N1L95 is bus_mux:inst28|alu_dr[7]~2392 at LC8_I11
--operation mode is normal

N1L95 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L051;


--N1L65 is bus_mux:inst28|alu_dr[7]~2322 at LC7_I11
--operation mode is normal

N1L65 = N1L55 # N1L45 # K1_q[7] & N1L021;

--N1L06 is bus_mux:inst28|alu_dr[7]~2393 at LC7_I11
--operation mode is normal

N1L06 = N1L55 # N1L45 # K1_q[7] & N1L021;


--B1L08 is alu:inst|alu_out[8]~5797 at LC1_I37
--operation mode is normal

B1L08 = H1_alu_func[0] & !H1_alu_func[1] & N1L65 # !H1_alu_func[0] & (B1L97);

--B1L58 is alu:inst|alu_out[8]~5875 at LC1_I37
--operation mode is normal

B1L58 = H1_alu_func[0] & !H1_alu_func[1] & N1L65 # !H1_alu_func[0] & (B1L97);


--V9_cs_buffer[10] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC1_G13
--operation mode is arithmetic

V9_cs_buffer[10] = V6_cs_buffer[10] $ !V9_cout[9];

--V9L53 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~304 at LC1_G13
--operation mode is arithmetic

V9L53 = V6_cs_buffer[10] $ !V9_cout[9];

--V9_cout[10] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[10] at LC1_G13
--operation mode is arithmetic

V9_cout[10] = CARRY(V9_cout[9] # !V6_cs_buffer[10]);


--B1L962 is alu:inst|temp2~8 at LC1_I33
--operation mode is normal

B1L962 = N1L541 & N1L46;

--B1L782 is alu:inst|temp2~1516 at LC1_I33
--operation mode is normal

B1L782 = N1L541 & N1L46;


--V3_cs_buffer[9] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC6_G21
--operation mode is arithmetic

V3_cs_buffer[9] = N1L46 $ N1L541 $ V3_cout[8];

--V3L83 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~296 at LC6_G21
--operation mode is arithmetic

V3L83 = N1L46 $ N1L541 $ V3_cout[8];

--V3_cout[9] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[9] at LC6_G21
--operation mode is arithmetic

V3_cout[9] = CARRY(N1L46 & (N1L541 # V3_cout[8]) # !N1L46 & N1L541 & V3_cout[8]);


--B1L18 is alu:inst|alu_out[8]~5798 at LC3_I33
--operation mode is normal

B1L18 = H1_alu_func[1] & (B1L962 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[9] & (!H1_alu_func[0]);

--B1L68 is alu:inst|alu_out[8]~5876 at LC3_I33
--operation mode is normal

B1L68 = H1_alu_func[1] & (B1L962 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[9] & (!H1_alu_func[0]);


--B1L772 is alu:inst|temp2~24 at LC5_I33
--operation mode is normal

B1L772 = N1L541 # N1L46;

--B1L882 is alu:inst|temp2~1517 at LC5_I33
--operation mode is normal

B1L882 = N1L541 # N1L46;


--B1L28 is alu:inst|alu_out[8]~5799 at LC4_I33
--operation mode is normal

B1L28 = B1L18 & (B1L772 # !H1_alu_func[0]) # !B1L18 & (H1_alu_func[0] & !V9_cs_buffer[10]);

--B1L78 is alu:inst|alu_out[8]~5877 at LC4_I33
--operation mode is normal

B1L78 = B1L18 & (B1L772 # !H1_alu_func[0]) # !B1L18 & (H1_alu_func[0] & !V9_cs_buffer[10]);


--B1L38 is alu:inst|alu_out[8]~5800 at LC2_I33
--operation mode is normal

B1L38 = H1_alu_func[2] & (B1L08) # !H1_alu_func[2] & B1L28;

--B1L88 is alu:inst|alu_out[8]~5878 at LC2_I33
--operation mode is normal

B1L88 = H1_alu_func[2] & (B1L08) # !H1_alu_func[2] & B1L28;


--B1L552 is alu:inst|reduce_nor~161 at LC1_G36
--operation mode is normal

B1L552 = !B1L38 & !B1L301 & !B1L321 & !B1L341;

--B1L062 is alu:inst|reduce_nor~166 at LC1_G36
--operation mode is normal

B1L062 = !B1L38 & !B1L301 & !B1L321 & !B1L341;


--N1L22 is bus_mux:inst28|alu_dr[3]~2323 at LC1_K20
--operation mode is normal

N1L22 = N1L811 & (H1_alu_in_sel[0] & (A1L94) # !H1_alu_in_sel[0] & K1_q[3]);

--N1L62 is bus_mux:inst28|alu_dr[3]~2394 at LC1_K20
--operation mode is normal

N1L62 = N1L811 & (H1_alu_in_sel[0] & (A1L94) # !H1_alu_in_sel[0] & K1_q[3]);


--L01_q[3] is reg:inst21|q[3] at LC4_K13
--operation mode is normal

L01_q[3]_lut_out = B1L33;
L01_q[3] = DFFEA(L01_q[3]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L9Q is reg:inst21|q[3]~103 at LC4_K13
--operation mode is normal

L01L9Q = L01_q[3];


--L9_q[3] is reg:inst20|q[3] at LC2_K22
--operation mode is normal

L9_q[3]_lut_out = B1L33;
L9_q[3] = DFFEA(L9_q[3]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L9Q is reg:inst20|q[3]~103 at LC2_K22
--operation mode is normal

L9L9Q = L9_q[3];


--L8_q[3] is reg:inst19|q[3] at LC4_K44
--operation mode is normal

L8_q[3]_lut_out = B1L33;
L8_q[3] = DFFEA(L8_q[3]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L9Q is reg:inst19|q[3]~103 at LC4_K44
--operation mode is normal

L8L9Q = L8_q[3];


--M1L16 is reg_mux:inst27|dr[3]~416 at LC5_K13
--operation mode is normal

M1L16 = H1_dest_reg[0] & (L9_q[3] # H1_dest_reg[1]) # !H1_dest_reg[0] & L8_q[3] & (!H1_dest_reg[1]);

--M1L17 is reg_mux:inst27|dr[3]~576 at LC5_K13
--operation mode is normal

M1L17 = H1_dest_reg[0] & (L9_q[3] # H1_dest_reg[1]) # !H1_dest_reg[0] & L8_q[3] & (!H1_dest_reg[1]);


--L11_q[3] is reg:inst22|q[3] at LC6_K13
--operation mode is normal

L11_q[3]_lut_out = B1L33;
L11_q[3] = DFFEA(L11_q[3]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L9Q is reg:inst22|q[3]~103 at LC6_K13
--operation mode is normal

L11L9Q = L11_q[3];


--M1L26 is reg_mux:inst27|dr[3]~417 at LC2_K13
--operation mode is normal

M1L26 = M1L16 & (L11_q[3] # !H1_dest_reg[1]) # !M1L16 & (H1_dest_reg[1] & L01_q[3]);

--M1L27 is reg_mux:inst27|dr[3]~577 at LC2_K13
--operation mode is normal

M1L27 = M1L16 & (L11_q[3] # !H1_dest_reg[1]) # !M1L16 & (H1_dest_reg[1] & L01_q[3]);


--L5_q[3] is reg:inst16|q[3] at LC6_K46
--operation mode is normal

L5_q[3]_lut_out = B1L33;
L5_q[3] = DFFEA(L5_q[3]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L9Q is reg:inst16|q[3]~103 at LC6_K46
--operation mode is normal

L5L9Q = L5_q[3];


--L6_q[3] is reg:inst17|q[3] at LC3_K18
--operation mode is normal

L6_q[3]_lut_out = B1L33;
L6_q[3] = DFFEA(L6_q[3]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L9Q is reg:inst17|q[3]~103 at LC3_K18
--operation mode is normal

L6L9Q = L6_q[3];


--L4_q[3] is reg:inst15|q[3] at LC1_B45
--operation mode is normal

L4_q[3]_lut_out = B1L33;
L4_q[3] = DFFEA(L4_q[3]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L9Q is reg:inst15|q[3]~103 at LC1_B45
--operation mode is normal

L4L9Q = L4_q[3];


--M1L36 is reg_mux:inst27|dr[3]~418 at LC3_K15
--operation mode is normal

M1L36 = H1_dest_reg[1] & (L6_q[3] # H1_dest_reg[0]) # !H1_dest_reg[1] & L4_q[3] & (!H1_dest_reg[0]);

--M1L37 is reg_mux:inst27|dr[3]~578 at LC3_K15
--operation mode is normal

M1L37 = H1_dest_reg[1] & (L6_q[3] # H1_dest_reg[0]) # !H1_dest_reg[1] & L4_q[3] & (!H1_dest_reg[0]);


--L7_q[3] is reg:inst18|q[3] at LC8_K48
--operation mode is normal

L7_q[3]_lut_out = B1L33;
L7_q[3] = DFFEA(L7_q[3]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L9Q is reg:inst18|q[3]~103 at LC8_K48
--operation mode is normal

L7L9Q = L7_q[3];


--M1L46 is reg_mux:inst27|dr[3]~419 at LC4_K15
--operation mode is normal

M1L46 = M1L36 & (L7_q[3] # !H1_dest_reg[0]) # !M1L36 & (H1_dest_reg[0] & L5_q[3]);

--M1L47 is reg_mux:inst27|dr[3]~579 at LC4_K15
--operation mode is normal

M1L47 = M1L36 & (L7_q[3] # !H1_dest_reg[0]) # !M1L36 & (H1_dest_reg[0] & L5_q[3]);


--L2_q[3] is reg:inst13|q[3] at LC1_K50
--operation mode is normal

L2_q[3]_lut_out = B1L33;
L2_q[3] = DFFEA(L2_q[3]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L9Q is reg:inst13|q[3]~103 at LC1_K50
--operation mode is normal

L2L9Q = L2_q[3];


--L1_q[3] is reg:inst12|q[3] at LC2_K7
--operation mode is normal

L1_q[3]_lut_out = B1L33;
L1_q[3] = DFFEA(L1_q[3]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L9Q is reg:inst12|q[3]~103 at LC2_K7
--operation mode is normal

L1L9Q = L1_q[3];


--L61_q[3] is reg:inst30|q[3] at LC4_K47
--operation mode is normal

L61_q[3]_lut_out = B1L33;
L61_q[3] = DFFEA(L61_q[3]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L9Q is reg:inst30|q[3]~103 at LC4_K47
--operation mode is normal

L61L9Q = L61_q[3];


--M1L56 is reg_mux:inst27|dr[3]~420 at LC5_K14
--operation mode is normal

M1L56 = H1_dest_reg[0] & (L1_q[3] # H1_dest_reg[1]) # !H1_dest_reg[0] & L61_q[3] & (!H1_dest_reg[1]);

--M1L57 is reg_mux:inst27|dr[3]~580 at LC5_K14
--operation mode is normal

M1L57 = H1_dest_reg[0] & (L1_q[3] # H1_dest_reg[1]) # !H1_dest_reg[0] & L61_q[3] & (!H1_dest_reg[1]);


--L3_q[3] is reg:inst14|q[3] at LC7_K9
--operation mode is normal

L3_q[3]_lut_out = B1L33;
L3_q[3] = DFFEA(L3_q[3]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L9Q is reg:inst14|q[3]~103 at LC7_K9
--operation mode is normal

L3L9Q = L3_q[3];


--M1L66 is reg_mux:inst27|dr[3]~421 at LC5_K15
--operation mode is normal

M1L66 = M1L56 & (L3_q[3] # !H1_dest_reg[1]) # !M1L56 & (H1_dest_reg[1] & L2_q[3]);

--M1L67 is reg_mux:inst27|dr[3]~581 at LC5_K15
--operation mode is normal

M1L67 = M1L56 & (L3_q[3] # !H1_dest_reg[1]) # !M1L56 & (H1_dest_reg[1] & L2_q[3]);


--M1L76 is reg_mux:inst27|dr[3]~422 at LC6_K15
--operation mode is normal

M1L76 = H1_dest_reg[2] & (M1L46 # H1_dest_reg[3]) # !H1_dest_reg[2] & M1L66 & (!H1_dest_reg[3]);

--M1L77 is reg_mux:inst27|dr[3]~582 at LC6_K15
--operation mode is normal

M1L77 = H1_dest_reg[2] & (M1L46 # H1_dest_reg[3]) # !H1_dest_reg[2] & M1L66 & (!H1_dest_reg[3]);


--L31_q[3] is reg:inst24|q[3] at LC1_K12
--operation mode is normal

L31_q[3]_lut_out = B1L33;
L31_q[3] = DFFEA(L31_q[3]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L9Q is reg:inst24|q[3]~103 at LC1_K12
--operation mode is normal

L31L9Q = L31_q[3];


--L41_q[3] is reg:inst25|q[3] at LC2_K9
--operation mode is normal

L41_q[3]_lut_out = B1L33;
L41_q[3] = DFFEA(L41_q[3]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L9Q is reg:inst25|q[3]~103 at LC2_K9
--operation mode is normal

L41L9Q = L41_q[3];


--L21_q[3] is reg:inst23|q[3] at LC3_K9
--operation mode is normal

L21_q[3]_lut_out = B1L33;
L21_q[3] = DFFEA(L21_q[3]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L9Q is reg:inst23|q[3]~103 at LC3_K9
--operation mode is normal

L21L9Q = L21_q[3];


--M1L86 is reg_mux:inst27|dr[3]~423 at LC3_K12
--operation mode is normal

M1L86 = H1_dest_reg[1] & (L41_q[3] # H1_dest_reg[0]) # !H1_dest_reg[1] & L21_q[3] & (!H1_dest_reg[0]);

--M1L87 is reg_mux:inst27|dr[3]~583 at LC3_K12
--operation mode is normal

M1L87 = H1_dest_reg[1] & (L41_q[3] # H1_dest_reg[0]) # !H1_dest_reg[1] & L21_q[3] & (!H1_dest_reg[0]);


--L51_q[3] is reg:inst26|q[3] at LC6_K12
--operation mode is normal

L51_q[3]_lut_out = B1L33;
L51_q[3] = DFFEA(L51_q[3]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L9Q is reg:inst26|q[3]~103 at LC6_K12
--operation mode is normal

L51L9Q = L51_q[3];


--M1L96 is reg_mux:inst27|dr[3]~424 at LC4_K12
--operation mode is normal

M1L96 = M1L86 & (L51_q[3] # !H1_dest_reg[0]) # !M1L86 & (H1_dest_reg[0] & L31_q[3]);

--M1L97 is reg_mux:inst27|dr[3]~584 at LC4_K12
--operation mode is normal

M1L97 = M1L86 & (L51_q[3] # !H1_dest_reg[0]) # !M1L86 & (H1_dest_reg[0] & L31_q[3]);


--M1L07 is reg_mux:inst27|dr[3]~425 at LC7_K15
--operation mode is normal

M1L07 = M1L76 & (M1L96 # !H1_dest_reg[3]) # !M1L76 & (H1_dest_reg[3] & M1L26);

--M1L08 is reg_mux:inst27|dr[3]~585 at LC7_K15
--operation mode is normal

M1L08 = M1L76 & (M1L96 # !H1_dest_reg[3]) # !M1L76 & (H1_dest_reg[3] & M1L26);


--N1L32 is bus_mux:inst28|alu_dr[3]~2324 at LC8_K15
--operation mode is normal

N1L32 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L07;

--N1L72 is bus_mux:inst28|alu_dr[3]~2395 at LC8_K15
--operation mode is normal

N1L72 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L07;


--N1L42 is bus_mux:inst28|alu_dr[3]~2325 at LC2_K15
--operation mode is normal

N1L42 = N1L32 # N1L22 # K1_q[3] & N1L021;

--N1L82 is bus_mux:inst28|alu_dr[3]~2396 at LC2_K15
--operation mode is normal

N1L82 = N1L32 # N1L22 # K1_q[3] & N1L021;


--N1L41 is bus_mux:inst28|alu_dr[2]~2326 at LC6_H32
--operation mode is normal

N1L41 = N1L811 & (H1_alu_in_sel[0] & (A1L05) # !H1_alu_in_sel[0] & K1_q[2]);

--N1L81 is bus_mux:inst28|alu_dr[2]~2397 at LC6_H32
--operation mode is normal

N1L81 = N1L811 & (H1_alu_in_sel[0] & (A1L05) # !H1_alu_in_sel[0] & K1_q[2]);


--L6_q[2] is reg:inst17|q[2] at LC7_H47
--operation mode is normal

L6_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L6_q[2] = DFFEA(L6_q[2]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L7Q is reg:inst17|q[2]~104 at LC7_H47
--operation mode is normal

L6L7Q = L6_q[2];


--L01_q[2] is reg:inst21|q[2] at LC2_H27
--operation mode is normal

L01_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L01_q[2] = DFFEA(L01_q[2]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L7Q is reg:inst21|q[2]~104 at LC2_H27
--operation mode is normal

L01L7Q = L01_q[2];


--L2_q[2] is reg:inst13|q[2] at LC1_H50
--operation mode is normal

L2_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L2_q[2] = DFFEA(L2_q[2]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L7Q is reg:inst13|q[2]~104 at LC1_H50
--operation mode is normal

L2L7Q = L2_q[2];


--M1L14 is reg_mux:inst27|dr[2]~426 at LC3_H27
--operation mode is normal

M1L14 = H1_dest_reg[3] & (L01_q[2] # H1_dest_reg[2]) # !H1_dest_reg[3] & L2_q[2] & (!H1_dest_reg[2]);

--M1L15 is reg_mux:inst27|dr[2]~586 at LC3_H27
--operation mode is normal

M1L15 = H1_dest_reg[3] & (L01_q[2] # H1_dest_reg[2]) # !H1_dest_reg[3] & L2_q[2] & (!H1_dest_reg[2]);


--L41_q[2] is reg:inst25|q[2] at LC4_H27
--operation mode is normal

L41_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L41_q[2] = DFFEA(L41_q[2]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L7Q is reg:inst25|q[2]~104 at LC4_H27
--operation mode is normal

L41L7Q = L41_q[2];


--M1L24 is reg_mux:inst27|dr[2]~427 at LC6_H27
--operation mode is normal

M1L24 = M1L14 & (L41_q[2] # !H1_dest_reg[2]) # !M1L14 & (H1_dest_reg[2] & L6_q[2]);

--M1L25 is reg_mux:inst27|dr[2]~587 at LC6_H27
--operation mode is normal

M1L25 = M1L14 & (L41_q[2] # !H1_dest_reg[2]) # !M1L14 & (H1_dest_reg[2] & L6_q[2]);


--L9_q[2] is reg:inst20|q[2] at LC5_H22
--operation mode is normal

L9_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L9_q[2] = DFFEA(L9_q[2]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L7Q is reg:inst20|q[2]~104 at LC5_H22
--operation mode is normal

L9L7Q = L9_q[2];


--L5_q[2] is reg:inst16|q[2] at LC6_H22
--operation mode is normal

L5_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L5_q[2] = DFFEA(L5_q[2]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L7Q is reg:inst16|q[2]~104 at LC6_H22
--operation mode is normal

L5L7Q = L5_q[2];


--L1_q[2] is reg:inst12|q[2] at LC8_H22
--operation mode is normal

L1_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L1_q[2] = DFFEA(L1_q[2]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L7Q is reg:inst12|q[2]~104 at LC8_H22
--operation mode is normal

L1L7Q = L1_q[2];


--M1L34 is reg_mux:inst27|dr[2]~428 at LC1_H12
--operation mode is normal

M1L34 = H1_dest_reg[2] & (L5_q[2] # H1_dest_reg[3]) # !H1_dest_reg[2] & L1_q[2] & (!H1_dest_reg[3]);

--M1L35 is reg_mux:inst27|dr[2]~588 at LC1_H12
--operation mode is normal

M1L35 = H1_dest_reg[2] & (L5_q[2] # H1_dest_reg[3]) # !H1_dest_reg[2] & L1_q[2] & (!H1_dest_reg[3]);


--L31_q[2] is reg:inst24|q[2] at LC2_H22
--operation mode is normal

L31_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L31_q[2] = DFFEA(L31_q[2]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L7Q is reg:inst24|q[2]~104 at LC2_H22
--operation mode is normal

L31L7Q = L31_q[2];


--M1L44 is reg_mux:inst27|dr[2]~429 at LC2_H12
--operation mode is normal

M1L44 = M1L34 & (L31_q[2] # !H1_dest_reg[3]) # !M1L34 & (H1_dest_reg[3] & L9_q[2]);

--M1L45 is reg_mux:inst27|dr[2]~589 at LC2_H12
--operation mode is normal

M1L45 = M1L34 & (L31_q[2] # !H1_dest_reg[3]) # !M1L34 & (H1_dest_reg[3] & L9_q[2]);


--L4_q[2] is reg:inst15|q[2] at LC5_H47
--operation mode is normal

L4_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L4_q[2] = DFFEA(L4_q[2]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L7Q is reg:inst15|q[2]~104 at LC5_H47
--operation mode is normal

L4L7Q = L4_q[2];


--L8_q[2] is reg:inst19|q[2] at LC8_H50
--operation mode is normal

L8_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L8_q[2] = DFFEA(L8_q[2]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L7Q is reg:inst19|q[2]~104 at LC8_H50
--operation mode is normal

L8L7Q = L8_q[2];


--L61_q[2] is reg:inst30|q[2] at LC1_H13
--operation mode is normal

L61_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L61_q[2] = DFFEA(L61_q[2]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L7Q is reg:inst30|q[2]~104 at LC1_H13
--operation mode is normal

L61L7Q = L61_q[2];


--M1L54 is reg_mux:inst27|dr[2]~430 at LC2_H13
--operation mode is normal

M1L54 = H1_dest_reg[3] & (L8_q[2] # H1_dest_reg[2]) # !H1_dest_reg[3] & L61_q[2] & (!H1_dest_reg[2]);

--M1L55 is reg_mux:inst27|dr[2]~590 at LC2_H13
--operation mode is normal

M1L55 = H1_dest_reg[3] & (L8_q[2] # H1_dest_reg[2]) # !H1_dest_reg[3] & L61_q[2] & (!H1_dest_reg[2]);


--L21_q[2] is reg:inst23|q[2] at LC7_H51
--operation mode is normal

L21_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L21_q[2] = DFFEA(L21_q[2]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L7Q is reg:inst23|q[2]~104 at LC7_H51
--operation mode is normal

L21L7Q = L21_q[2];


--M1L64 is reg_mux:inst27|dr[2]~431 at LC3_H12
--operation mode is normal

M1L64 = M1L54 & (L21_q[2] # !H1_dest_reg[2]) # !M1L54 & (H1_dest_reg[2] & L4_q[2]);

--M1L65 is reg_mux:inst27|dr[2]~591 at LC3_H12
--operation mode is normal

M1L65 = M1L54 & (L21_q[2] # !H1_dest_reg[2]) # !M1L54 & (H1_dest_reg[2] & L4_q[2]);


--M1L74 is reg_mux:inst27|dr[2]~432 at LC4_H12
--operation mode is normal

M1L74 = H1_dest_reg[0] & (M1L44 # H1_dest_reg[1]) # !H1_dest_reg[0] & M1L64 & (!H1_dest_reg[1]);

--M1L75 is reg_mux:inst27|dr[2]~592 at LC4_H12
--operation mode is normal

M1L75 = H1_dest_reg[0] & (M1L44 # H1_dest_reg[1]) # !H1_dest_reg[0] & M1L64 & (!H1_dest_reg[1]);


--L11_q[2] is reg:inst22|q[2] at LC1_H11
--operation mode is normal

L11_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L11_q[2] = DFFEA(L11_q[2]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L7Q is reg:inst22|q[2]~104 at LC1_H11
--operation mode is normal

L11L7Q = L11_q[2];


--L7_q[2] is reg:inst18|q[2] at LC4_H11
--operation mode is normal

L7_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L7_q[2] = DFFEA(L7_q[2]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L7Q is reg:inst18|q[2]~104 at LC4_H11
--operation mode is normal

L7L7Q = L7_q[2];


--L3_q[2] is reg:inst14|q[2] at LC6_H50
--operation mode is normal

L3_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L3_q[2] = DFFEA(L3_q[2]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L7Q is reg:inst14|q[2]~104 at LC6_H50
--operation mode is normal

L3L7Q = L3_q[2];


--M1L84 is reg_mux:inst27|dr[2]~433 at LC6_H11
--operation mode is normal

M1L84 = H1_dest_reg[2] & (L7_q[2] # H1_dest_reg[3]) # !H1_dest_reg[2] & L3_q[2] & (!H1_dest_reg[3]);

--M1L85 is reg_mux:inst27|dr[2]~593 at LC6_H11
--operation mode is normal

M1L85 = H1_dest_reg[2] & (L7_q[2] # H1_dest_reg[3]) # !H1_dest_reg[2] & L3_q[2] & (!H1_dest_reg[3]);


--L51_q[2] is reg:inst26|q[2] at LC8_H47
--operation mode is normal

L51_q[2]_lut_out = H1_alu_func[2] & B1L02 # !H1_alu_func[2] & (B1L22);
L51_q[2] = DFFEA(L51_q[2]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L7Q is reg:inst26|q[2]~104 at LC8_H47
--operation mode is normal

L51L7Q = L51_q[2];


--M1L94 is reg_mux:inst27|dr[2]~434 at LC5_H11
--operation mode is normal

M1L94 = M1L84 & (L51_q[2] # !H1_dest_reg[3]) # !M1L84 & (H1_dest_reg[3] & L11_q[2]);

--M1L95 is reg_mux:inst27|dr[2]~594 at LC5_H11
--operation mode is normal

M1L95 = M1L84 & (L51_q[2] # !H1_dest_reg[3]) # !M1L84 & (H1_dest_reg[3] & L11_q[2]);


--M1L05 is reg_mux:inst27|dr[2]~435 at LC5_H12
--operation mode is normal

M1L05 = M1L74 & (M1L94 # !H1_dest_reg[1]) # !M1L74 & (H1_dest_reg[1] & M1L24);

--M1L06 is reg_mux:inst27|dr[2]~595 at LC5_H12
--operation mode is normal

M1L06 = M1L74 & (M1L94 # !H1_dest_reg[1]) # !M1L74 & (H1_dest_reg[1] & M1L24);


--N1L51 is bus_mux:inst28|alu_dr[2]~2327 at LC7_H12
--operation mode is normal

N1L51 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L05;

--N1L91 is bus_mux:inst28|alu_dr[2]~2398 at LC7_H12
--operation mode is normal

N1L91 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L05;


--N1L61 is bus_mux:inst28|alu_dr[2]~2328 at LC8_H12
--operation mode is normal

N1L61 = N1L51 # N1L41 # K1_q[2] & N1L021;

--N1L02 is bus_mux:inst28|alu_dr[2]~2399 at LC8_H12
--operation mode is normal

N1L02 = N1L51 # N1L41 # K1_q[2] & N1L021;


--N1L161 is bus_mux:inst28|alu_sr[15]~642 at LC3_H6
--operation mode is normal

N1L161 = !H1_alu_in_sel[1] & !H1_alu_in_sel[2];

--N1L461 is bus_mux:inst28|alu_sr[15]~660 at LC3_H6
--operation mode is normal

N1L461 = !H1_alu_in_sel[1] & !H1_alu_in_sel[2];


--M1L547 is reg_mux:inst27|sr[2]~396 at LC5_H27
--operation mode is normal

M1L547 = H1_sour_reg[3] & (L01_q[2] # H1_sour_reg[2]) # !H1_sour_reg[3] & L2_q[2] & (!H1_sour_reg[2]);

--M1L557 is reg_mux:inst27|sr[2]~556 at LC5_H27
--operation mode is normal

M1L557 = H1_sour_reg[3] & (L01_q[2] # H1_sour_reg[2]) # !H1_sour_reg[3] & L2_q[2] & (!H1_sour_reg[2]);


--M1L647 is reg_mux:inst27|sr[2]~397 at LC8_H27
--operation mode is normal

M1L647 = M1L547 & (L41_q[2] # !H1_sour_reg[2]) # !M1L547 & (H1_sour_reg[2] & L6_q[2]);

--M1L657 is reg_mux:inst27|sr[2]~557 at LC8_H27
--operation mode is normal

M1L657 = M1L547 & (L41_q[2] # !H1_sour_reg[2]) # !M1L547 & (H1_sour_reg[2] & L6_q[2]);


--M1L747 is reg_mux:inst27|sr[2]~398 at LC1_H22
--operation mode is normal

M1L747 = H1_sour_reg[2] & (L5_q[2] # H1_sour_reg[3]) # !H1_sour_reg[2] & L1_q[2] & (!H1_sour_reg[3]);

--M1L757 is reg_mux:inst27|sr[2]~558 at LC1_H22
--operation mode is normal

M1L757 = H1_sour_reg[2] & (L5_q[2] # H1_sour_reg[3]) # !H1_sour_reg[2] & L1_q[2] & (!H1_sour_reg[3]);


--M1L847 is reg_mux:inst27|sr[2]~399 at LC3_H22
--operation mode is normal

M1L847 = M1L747 & (L31_q[2] # !H1_sour_reg[3]) # !M1L747 & (H1_sour_reg[3] & L9_q[2]);

--M1L857 is reg_mux:inst27|sr[2]~559 at LC3_H22
--operation mode is normal

M1L857 = M1L747 & (L31_q[2] # !H1_sour_reg[3]) # !M1L747 & (H1_sour_reg[3] & L9_q[2]);


--M1L947 is reg_mux:inst27|sr[2]~400 at LC3_H13
--operation mode is normal

M1L947 = H1_sour_reg[3] & (L8_q[2] # H1_sour_reg[2]) # !H1_sour_reg[3] & L61_q[2] & (!H1_sour_reg[2]);

--M1L957 is reg_mux:inst27|sr[2]~560 at LC3_H13
--operation mode is normal

M1L957 = H1_sour_reg[3] & (L8_q[2] # H1_sour_reg[2]) # !H1_sour_reg[3] & L61_q[2] & (!H1_sour_reg[2]);


--M1L057 is reg_mux:inst27|sr[2]~401 at LC5_H13
--operation mode is normal

M1L057 = M1L947 & (L21_q[2] # !H1_sour_reg[2]) # !M1L947 & (H1_sour_reg[2] & L4_q[2]);

--M1L067 is reg_mux:inst27|sr[2]~561 at LC5_H13
--operation mode is normal

M1L067 = M1L947 & (L21_q[2] # !H1_sour_reg[2]) # !M1L947 & (H1_sour_reg[2] & L4_q[2]);


--M1L157 is reg_mux:inst27|sr[2]~402 at LC7_H13
--operation mode is normal

M1L157 = H1_sour_reg[0] & (M1L847 # H1_sour_reg[1]) # !H1_sour_reg[0] & M1L057 & (!H1_sour_reg[1]);

--M1L167 is reg_mux:inst27|sr[2]~562 at LC7_H13
--operation mode is normal

M1L167 = H1_sour_reg[0] & (M1L847 # H1_sour_reg[1]) # !H1_sour_reg[0] & M1L057 & (!H1_sour_reg[1]);


--M1L257 is reg_mux:inst27|sr[2]~403 at LC7_H11
--operation mode is normal

M1L257 = H1_sour_reg[2] & (L7_q[2] # H1_sour_reg[3]) # !H1_sour_reg[2] & L3_q[2] & (!H1_sour_reg[3]);

--M1L267 is reg_mux:inst27|sr[2]~563 at LC7_H11
--operation mode is normal

M1L267 = H1_sour_reg[2] & (L7_q[2] # H1_sour_reg[3]) # !H1_sour_reg[2] & L3_q[2] & (!H1_sour_reg[3]);


--M1L357 is reg_mux:inst27|sr[2]~404 at LC2_H11
--operation mode is normal

M1L357 = M1L257 & (L51_q[2] # !H1_sour_reg[3]) # !M1L257 & (H1_sour_reg[3] & L11_q[2]);

--M1L367 is reg_mux:inst27|sr[2]~564 at LC2_H11
--operation mode is normal

M1L367 = M1L257 & (L51_q[2] # !H1_sour_reg[3]) # !M1L257 & (H1_sour_reg[3] & L11_q[2]);


--M1L457 is reg_mux:inst27|sr[2]~405 at LC4_H13
--operation mode is normal

M1L457 = M1L157 & (M1L357 # !H1_sour_reg[1]) # !M1L157 & (H1_sour_reg[1] & M1L647);

--M1L467 is reg_mux:inst27|sr[2]~565 at LC4_H13
--operation mode is normal

M1L467 = M1L157 & (M1L357 # !H1_sour_reg[1]) # !M1L157 & (H1_sour_reg[1] & M1L647);


--N1L331 is bus_mux:inst28|alu_sr[2]~643 at LC1_H6
--operation mode is normal

N1L331 = H1_offset[2] & (N1L021 # M1L457 & N1L161) # !H1_offset[2] & M1L457 & N1L161;

--N1L431 is bus_mux:inst28|alu_sr[2]~661 at LC1_H6
--operation mode is normal

N1L431 = H1_offset[2] & (N1L021 # M1L457 & N1L161) # !H1_offset[2] & M1L457 & N1L161;


--B1L91 is alu:inst|alu_out[2]~5801 at LC1_H51
--operation mode is normal

B1L91 = H1_alu_func[1] & (N1L42) # !H1_alu_func[1] & (N1L331 $ N1L61);

--B1L42 is alu:inst|alu_out[2]~5879 at LC1_H51
--operation mode is normal

B1L42 = H1_alu_func[1] & (N1L42) # !H1_alu_func[1] & (N1L331 $ N1L61);


--N1L6 is bus_mux:inst28|alu_dr[1]~2329 at LC3_H8
--operation mode is normal

N1L6 = N1L811 & (H1_alu_in_sel[0] & (A1L15) # !H1_alu_in_sel[0] & K1_q[1]);

--N1L01 is bus_mux:inst28|alu_dr[1]~2400 at LC3_H8
--operation mode is normal

N1L01 = N1L811 & (H1_alu_in_sel[0] & (A1L15) # !H1_alu_in_sel[0] & K1_q[1]);


--L6_q[1] is reg:inst17|q[1] at LC2_H9
--operation mode is normal

L6_q[1]_lut_out = B1L31;
L6_q[1] = DFFEA(L6_q[1]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L5Q is reg:inst17|q[1]~105 at LC2_H9
--operation mode is normal

L6L5Q = L6_q[1];


--L5_q[1] is reg:inst16|q[1] at LC2_G49
--operation mode is normal

L5_q[1]_lut_out = B1L31;
L5_q[1] = DFFEA(L5_q[1]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L5Q is reg:inst16|q[1]~105 at LC2_G49
--operation mode is normal

L5L5Q = L5_q[1];


--L4_q[1] is reg:inst15|q[1] at LC3_H9
--operation mode is normal

L4_q[1]_lut_out = B1L31;
L4_q[1] = DFFEA(L4_q[1]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L5Q is reg:inst15|q[1]~105 at LC3_H9
--operation mode is normal

L4L5Q = L4_q[1];


--M1L12 is reg_mux:inst27|dr[1]~436 at LC4_H9
--operation mode is normal

M1L12 = H1_dest_reg[0] & (L5_q[1] # H1_dest_reg[1]) # !H1_dest_reg[0] & L4_q[1] & (!H1_dest_reg[1]);

--M1L13 is reg_mux:inst27|dr[1]~596 at LC4_H9
--operation mode is normal

M1L13 = H1_dest_reg[0] & (L5_q[1] # H1_dest_reg[1]) # !H1_dest_reg[0] & L4_q[1] & (!H1_dest_reg[1]);


--L7_q[1] is reg:inst18|q[1] at LC4_E45
--operation mode is normal

L7_q[1]_lut_out = B1L31;
L7_q[1] = DFFEA(L7_q[1]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L5Q is reg:inst18|q[1]~105 at LC4_E45
--operation mode is normal

L7L5Q = L7_q[1];


--M1L22 is reg_mux:inst27|dr[1]~437 at LC1_H9
--operation mode is normal

M1L22 = M1L12 & (L7_q[1] # !H1_dest_reg[1]) # !M1L12 & (H1_dest_reg[1] & L6_q[1]);

--M1L23 is reg_mux:inst27|dr[1]~597 at LC1_H9
--operation mode is normal

M1L23 = M1L12 & (L7_q[1] # !H1_dest_reg[1]) # !M1L12 & (H1_dest_reg[1] & L6_q[1]);


--L9_q[1] is reg:inst20|q[1] at LC6_H2
--operation mode is normal

L9_q[1]_lut_out = B1L31;
L9_q[1] = DFFEA(L9_q[1]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L5Q is reg:inst20|q[1]~105 at LC6_H2
--operation mode is normal

L9L5Q = L9_q[1];


--L01_q[1] is reg:inst21|q[1] at LC7_E38
--operation mode is normal

L01_q[1]_lut_out = B1L31;
L01_q[1] = DFFEA(L01_q[1]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L5Q is reg:inst21|q[1]~105 at LC7_E38
--operation mode is normal

L01L5Q = L01_q[1];


--L8_q[1] is reg:inst19|q[1] at LC8_H51
--operation mode is normal

L8_q[1]_lut_out = B1L31;
L8_q[1] = DFFEA(L8_q[1]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L5Q is reg:inst19|q[1]~105 at LC8_H51
--operation mode is normal

L8L5Q = L8_q[1];


--M1L32 is reg_mux:inst27|dr[1]~438 at LC2_H14
--operation mode is normal

M1L32 = H1_dest_reg[1] & (L01_q[1] # H1_dest_reg[0]) # !H1_dest_reg[1] & L8_q[1] & (!H1_dest_reg[0]);

--M1L33 is reg_mux:inst27|dr[1]~598 at LC2_H14
--operation mode is normal

M1L33 = H1_dest_reg[1] & (L01_q[1] # H1_dest_reg[0]) # !H1_dest_reg[1] & L8_q[1] & (!H1_dest_reg[0]);


--L11_q[1] is reg:inst22|q[1] at LC7_I45
--operation mode is normal

L11_q[1]_lut_out = B1L31;
L11_q[1] = DFFEA(L11_q[1]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L5Q is reg:inst22|q[1]~105 at LC7_I45
--operation mode is normal

L11L5Q = L11_q[1];


--M1L42 is reg_mux:inst27|dr[1]~439 at LC2_H8
--operation mode is normal

M1L42 = M1L32 & (L11_q[1] # !H1_dest_reg[0]) # !M1L32 & (H1_dest_reg[0] & L9_q[1]);

--M1L43 is reg_mux:inst27|dr[1]~599 at LC2_H8
--operation mode is normal

M1L43 = M1L32 & (L11_q[1] # !H1_dest_reg[0]) # !M1L32 & (H1_dest_reg[0] & L9_q[1]);


--L1_q[1] is reg:inst12|q[1] at LC6_E38
--operation mode is normal

L1_q[1]_lut_out = B1L31;
L1_q[1] = DFFEA(L1_q[1]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L5Q is reg:inst12|q[1]~105 at LC6_E38
--operation mode is normal

L1L5Q = L1_q[1];


--L2_q[1] is reg:inst13|q[1] at LC1_H10
--operation mode is normal

L2_q[1]_lut_out = B1L31;
L2_q[1] = DFFEA(L2_q[1]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L5Q is reg:inst13|q[1]~105 at LC1_H10
--operation mode is normal

L2L5Q = L2_q[1];


--L61_q[1] is reg:inst30|q[1] at LC2_H10
--operation mode is normal

L61_q[1]_lut_out = B1L31;
L61_q[1] = DFFEA(L61_q[1]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L5Q is reg:inst30|q[1]~105 at LC2_H10
--operation mode is normal

L61L5Q = L61_q[1];


--M1L52 is reg_mux:inst27|dr[1]~440 at LC4_H10
--operation mode is normal

M1L52 = H1_dest_reg[1] & (L2_q[1] # H1_dest_reg[0]) # !H1_dest_reg[1] & L61_q[1] & (!H1_dest_reg[0]);

--M1L53 is reg_mux:inst27|dr[1]~600 at LC4_H10
--operation mode is normal

M1L53 = H1_dest_reg[1] & (L2_q[1] # H1_dest_reg[0]) # !H1_dest_reg[1] & L61_q[1] & (!H1_dest_reg[0]);


--L3_q[1] is reg:inst14|q[1] at LC2_H51
--operation mode is normal

L3_q[1]_lut_out = B1L31;
L3_q[1] = DFFEA(L3_q[1]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L5Q is reg:inst14|q[1]~105 at LC2_H51
--operation mode is normal

L3L5Q = L3_q[1];


--M1L62 is reg_mux:inst27|dr[1]~441 at LC6_H10
--operation mode is normal

M1L62 = M1L52 & (L3_q[1] # !H1_dest_reg[0]) # !M1L52 & (H1_dest_reg[0] & L1_q[1]);

--M1L63 is reg_mux:inst27|dr[1]~601 at LC6_H10
--operation mode is normal

M1L63 = M1L52 & (L3_q[1] # !H1_dest_reg[0]) # !M1L52 & (H1_dest_reg[0] & L1_q[1]);


--M1L72 is reg_mux:inst27|dr[1]~442 at LC5_H8
--operation mode is normal

M1L72 = H1_dest_reg[3] & (M1L42 # H1_dest_reg[2]) # !H1_dest_reg[3] & M1L62 & (!H1_dest_reg[2]);

--M1L73 is reg_mux:inst27|dr[1]~602 at LC5_H8
--operation mode is normal

M1L73 = H1_dest_reg[3] & (M1L42 # H1_dest_reg[2]) # !H1_dest_reg[3] & M1L62 & (!H1_dest_reg[2]);


--L41_q[1] is reg:inst25|q[1] at LC1_H7
--operation mode is normal

L41_q[1]_lut_out = B1L31;
L41_q[1] = DFFEA(L41_q[1]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L5Q is reg:inst25|q[1]~105 at LC1_H7
--operation mode is normal

L41L5Q = L41_q[1];


--L31_q[1] is reg:inst24|q[1] at LC3_G49
--operation mode is normal

L31_q[1]_lut_out = B1L31;
L31_q[1] = DFFEA(L31_q[1]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L5Q is reg:inst24|q[1]~105 at LC3_G49
--operation mode is normal

L31L5Q = L31_q[1];


--L21_q[1] is reg:inst23|q[1] at LC8_G49
--operation mode is normal

L21_q[1]_lut_out = B1L31;
L21_q[1] = DFFEA(L21_q[1]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L5Q is reg:inst23|q[1]~105 at LC8_G49
--operation mode is normal

L21L5Q = L21_q[1];


--M1L82 is reg_mux:inst27|dr[1]~443 at LC2_H7
--operation mode is normal

M1L82 = H1_dest_reg[0] & (L31_q[1] # H1_dest_reg[1]) # !H1_dest_reg[0] & L21_q[1] & (!H1_dest_reg[1]);

--M1L83 is reg_mux:inst27|dr[1]~603 at LC2_H7
--operation mode is normal

M1L83 = H1_dest_reg[0] & (L31_q[1] # H1_dest_reg[1]) # !H1_dest_reg[0] & L21_q[1] & (!H1_dest_reg[1]);


--L51_q[1] is reg:inst26|q[1] at LC3_H7
--operation mode is normal

L51_q[1]_lut_out = B1L31;
L51_q[1] = DFFEA(L51_q[1]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L5Q is reg:inst26|q[1]~105 at LC3_H7
--operation mode is normal

L51L5Q = L51_q[1];


--M1L92 is reg_mux:inst27|dr[1]~444 at LC6_H7
--operation mode is normal

M1L92 = M1L82 & (L51_q[1] # !H1_dest_reg[1]) # !M1L82 & (H1_dest_reg[1] & L41_q[1]);

--M1L93 is reg_mux:inst27|dr[1]~604 at LC6_H7
--operation mode is normal

M1L93 = M1L82 & (L51_q[1] # !H1_dest_reg[1]) # !M1L82 & (H1_dest_reg[1] & L41_q[1]);


--M1L03 is reg_mux:inst27|dr[1]~445 at LC6_H8
--operation mode is normal

M1L03 = M1L72 & (M1L92 # !H1_dest_reg[2]) # !M1L72 & (H1_dest_reg[2] & M1L22);

--M1L04 is reg_mux:inst27|dr[1]~605 at LC6_H8
--operation mode is normal

M1L04 = M1L72 & (M1L92 # !H1_dest_reg[2]) # !M1L72 & (H1_dest_reg[2] & M1L22);


--N1L7 is bus_mux:inst28|alu_dr[1]~2330 at LC7_H8
--operation mode is normal

N1L7 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L03;

--N1L11 is bus_mux:inst28|alu_dr[1]~2401 at LC7_H8
--operation mode is normal

N1L11 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L03;


--N1L8 is bus_mux:inst28|alu_dr[1]~2331 at LC8_H8
--operation mode is normal

N1L8 = N1L7 # N1L6 # K1_q[1] & N1L021;

--N1L21 is bus_mux:inst28|alu_dr[1]~2402 at LC8_H8
--operation mode is normal

N1L21 = N1L7 # N1L6 # K1_q[1] & N1L021;


--B1L02 is alu:inst|alu_out[2]~5802 at LC4_H51
--operation mode is normal

B1L02 = H1_alu_func[0] & !H1_alu_func[1] & N1L8 # !H1_alu_func[0] & (B1L91);

--B1L52 is alu:inst|alu_out[2]~5880 at LC4_H51
--operation mode is normal

B1L52 = H1_alu_func[0] & !H1_alu_func[1] & N1L8 # !H1_alu_func[0] & (B1L91);


--V9_cs_buffer[4] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC3_G11
--operation mode is arithmetic

V9_cs_buffer[4] = V6_cs_buffer[4] $ !V9_cout[3];

--V9L32 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~305 at LC3_G11
--operation mode is arithmetic

V9L32 = V6_cs_buffer[4] $ !V9_cout[3];

--V9_cout[4] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4] at LC3_G11
--operation mode is arithmetic

V9_cout[4] = CARRY(V9_cout[3] # !V6_cs_buffer[4]);


--B1L662 is alu:inst|temp2~2 at LC2_G19
--operation mode is normal

B1L662 = N1L331 & N1L61;

--B1L982 is alu:inst|temp2~1518 at LC2_G19
--operation mode is normal

B1L982 = N1L331 & N1L61;


--V3_cs_buffer[3] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC8_G19
--operation mode is arithmetic

V3_cs_buffer[3] = N1L61 $ N1L331 $ V3_cout[2];

--V3L62 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~297 at LC8_G19
--operation mode is arithmetic

V3L62 = N1L61 $ N1L331 $ V3_cout[2];

--V3_cout[3] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] at LC8_G19
--operation mode is arithmetic

V3_cout[3] = CARRY(N1L61 & (N1L331 # V3_cout[2]) # !N1L61 & N1L331 & V3_cout[2]);


--B1L12 is alu:inst|alu_out[2]~5803 at LC1_G19
--operation mode is normal

B1L12 = H1_alu_func[1] & (B1L662 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[3] & (!H1_alu_func[0]);

--B1L62 is alu:inst|alu_out[2]~5881 at LC1_G19
--operation mode is normal

B1L62 = H1_alu_func[1] & (B1L662 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[3] & (!H1_alu_func[0]);


--B1L472 is alu:inst|temp2~18 at LC3_H47
--operation mode is normal

B1L472 = N1L331 # N1L61;

--B1L092 is alu:inst|temp2~1519 at LC3_H47
--operation mode is normal

B1L092 = N1L331 # N1L61;


--B1L22 is alu:inst|alu_out[2]~5804 at LC1_H47
--operation mode is normal

B1L22 = B1L12 & (B1L472 # !H1_alu_func[0]) # !B1L12 & (H1_alu_func[0] & !V9_cs_buffer[4]);

--B1L72 is alu:inst|alu_out[2]~5882 at LC1_H47
--operation mode is normal

B1L72 = B1L12 & (B1L472 # !H1_alu_func[0]) # !B1L12 & (H1_alu_func[0] & !V9_cs_buffer[4]);


--B1L32 is alu:inst|alu_out[2]~5805 at LC2_H47
--operation mode is normal

B1L32 = H1_alu_func[2] & (B1L02) # !H1_alu_func[2] & B1L22;

--B1L82 is alu:inst|alu_out[2]~5883 at LC2_H47
--operation mode is normal

B1L82 = H1_alu_func[2] & (B1L02) # !H1_alu_func[2] & B1L22;


--M1L569 is reg_mux:inst27|sr[13]~406 at LC6_C12
--operation mode is normal

M1L569 = H1_sour_reg[0] & (L5_q[13] # H1_sour_reg[1]) # !H1_sour_reg[0] & L4_q[13] & (!H1_sour_reg[1]);

--M1L579 is reg_mux:inst27|sr[13]~566 at LC6_C12
--operation mode is normal

M1L579 = H1_sour_reg[0] & (L5_q[13] # H1_sour_reg[1]) # !H1_sour_reg[0] & L4_q[13] & (!H1_sour_reg[1]);


--M1L669 is reg_mux:inst27|sr[13]~407 at LC2_C12
--operation mode is normal

M1L669 = M1L569 & (L7_q[13] # !H1_sour_reg[1]) # !M1L569 & (H1_sour_reg[1] & L6_q[13]);

--M1L679 is reg_mux:inst27|sr[13]~567 at LC2_C12
--operation mode is normal

M1L679 = M1L569 & (L7_q[13] # !H1_sour_reg[1]) # !M1L569 & (H1_sour_reg[1] & L6_q[13]);


--M1L769 is reg_mux:inst27|sr[13]~408 at LC2_C9
--operation mode is normal

M1L769 = H1_sour_reg[1] & (L01_q[13] # H1_sour_reg[0]) # !H1_sour_reg[1] & L8_q[13] & (!H1_sour_reg[0]);

--M1L779 is reg_mux:inst27|sr[13]~568 at LC2_C9
--operation mode is normal

M1L779 = H1_sour_reg[1] & (L01_q[13] # H1_sour_reg[0]) # !H1_sour_reg[1] & L8_q[13] & (!H1_sour_reg[0]);


--M1L869 is reg_mux:inst27|sr[13]~409 at LC3_C9
--operation mode is normal

M1L869 = M1L769 & (L11_q[13] # !H1_sour_reg[0]) # !M1L769 & (H1_sour_reg[0] & L9_q[13]);

--M1L879 is reg_mux:inst27|sr[13]~569 at LC3_C9
--operation mode is normal

M1L879 = M1L769 & (L11_q[13] # !H1_sour_reg[0]) # !M1L769 & (H1_sour_reg[0] & L9_q[13]);


--M1L969 is reg_mux:inst27|sr[13]~410 at LC7_C15
--operation mode is normal

M1L969 = H1_sour_reg[1] & (L2_q[13] # H1_sour_reg[0]) # !H1_sour_reg[1] & L61_q[13] & (!H1_sour_reg[0]);

--M1L979 is reg_mux:inst27|sr[13]~570 at LC7_C15
--operation mode is normal

M1L979 = H1_sour_reg[1] & (L2_q[13] # H1_sour_reg[0]) # !H1_sour_reg[1] & L61_q[13] & (!H1_sour_reg[0]);


--M1L079 is reg_mux:inst27|sr[13]~411 at LC8_C15
--operation mode is normal

M1L079 = M1L969 & (L3_q[13] # !H1_sour_reg[0]) # !M1L969 & (H1_sour_reg[0] & L1_q[13]);

--M1L089 is reg_mux:inst27|sr[13]~571 at LC8_C15
--operation mode is normal

M1L089 = M1L969 & (L3_q[13] # !H1_sour_reg[0]) # !M1L969 & (H1_sour_reg[0] & L1_q[13]);


--M1L179 is reg_mux:inst27|sr[13]~412 at LC4_C9
--operation mode is normal

M1L179 = H1_sour_reg[3] & (M1L869 # H1_sour_reg[2]) # !H1_sour_reg[3] & M1L079 & (!H1_sour_reg[2]);

--M1L189 is reg_mux:inst27|sr[13]~572 at LC4_C9
--operation mode is normal

M1L189 = H1_sour_reg[3] & (M1L869 # H1_sour_reg[2]) # !H1_sour_reg[3] & M1L079 & (!H1_sour_reg[2]);


--M1L279 is reg_mux:inst27|sr[13]~413 at LC5_C8
--operation mode is normal

M1L279 = H1_sour_reg[0] & (L31_q[13] # H1_sour_reg[1]) # !H1_sour_reg[0] & L21_q[13] & (!H1_sour_reg[1]);

--M1L289 is reg_mux:inst27|sr[13]~573 at LC5_C8
--operation mode is normal

M1L289 = H1_sour_reg[0] & (L31_q[13] # H1_sour_reg[1]) # !H1_sour_reg[0] & L21_q[13] & (!H1_sour_reg[1]);


--M1L379 is reg_mux:inst27|sr[13]~414 at LC2_C8
--operation mode is normal

M1L379 = M1L279 & (L51_q[13] # !H1_sour_reg[1]) # !M1L279 & (H1_sour_reg[1] & L41_q[13]);

--M1L389 is reg_mux:inst27|sr[13]~574 at LC2_C8
--operation mode is normal

M1L389 = M1L279 & (L51_q[13] # !H1_sour_reg[1]) # !M1L279 & (H1_sour_reg[1] & L41_q[13]);


--M1L479 is reg_mux:inst27|sr[13]~415 at LC5_C9
--operation mode is normal

M1L479 = M1L179 & (M1L379 # !H1_sour_reg[2]) # !M1L179 & (H1_sour_reg[2] & M1L669);

--M1L489 is reg_mux:inst27|sr[13]~575 at LC5_C9
--operation mode is normal

M1L489 = M1L179 & (M1L379 # !H1_sour_reg[2]) # !M1L179 & (H1_sour_reg[2] & M1L669);


--N1L551 is bus_mux:inst28|alu_sr[13]~644 at LC8_C9
--operation mode is normal

N1L551 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L479;

--N1L651 is bus_mux:inst28|alu_sr[13]~662 at LC8_C9
--operation mode is normal

N1L651 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L479;


--V9_cs_buffer[15] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] at LC6_G13
--operation mode is arithmetic

V9_cs_buffer[15] = V6_cs_buffer[15] $ !V9_cout[14];

--V9L54 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~306 at LC6_G13
--operation mode is arithmetic

V9L54 = V6_cs_buffer[15] $ !V9_cout[14];

--V9_cout[15] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[15] at LC6_G13
--operation mode is arithmetic

V9_cout[15] = CARRY(V9_cout[14] # !V6_cs_buffer[15]);


--V3_cs_buffer[14] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] at LC3_G23
--operation mode is arithmetic

V3_cs_buffer[14] = N1L401 $ N1L551 $ V3_cout[13];

--V3L84 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~298 at LC3_G23
--operation mode is arithmetic

V3L84 = N1L401 $ N1L551 $ V3_cout[13];

--V3_cout[14] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[14] at LC3_G23
--operation mode is arithmetic

V3_cout[14] = CARRY(N1L401 & (N1L551 # V3_cout[13]) # !N1L401 & N1L551 & V3_cout[13]);


--B1L921 is alu:inst|alu_out[13]~5806 at LC3_G29
--operation mode is normal

B1L921 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[15]) # !H1_alu_func[0] & V3_cs_buffer[14] & (!H1_alu_func[1]);

--B1L431 is alu:inst|alu_out[13]~5884 at LC3_G29
--operation mode is normal

B1L431 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[15]) # !H1_alu_func[0] & V3_cs_buffer[14] & (!H1_alu_func[1]);


--B1L031 is alu:inst|alu_out[13]~5807 at LC4_G29
--operation mode is normal

B1L031 = H1_alu_func[1] & (B1L921 & (N1L401 # N1L551) # !B1L921 & N1L401 & N1L551) # !H1_alu_func[1] & B1L921;

--B1L531 is alu:inst|alu_out[13]~5885 at LC4_G29
--operation mode is normal

B1L531 = H1_alu_func[1] & (B1L921 & (N1L401 # N1L551) # !B1L921 & N1L401 & N1L551) # !H1_alu_func[1] & B1L921;


--B1L131 is alu:inst|alu_out[13]~5808 at LC5_G29
--operation mode is normal

B1L131 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L551 $ N1L401);

--B1L631 is alu:inst|alu_out[13]~5886 at LC5_G29
--operation mode is normal

B1L631 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L551 $ N1L401);


--B1L231 is alu:inst|alu_out[13]~5809 at LC6_G29
--operation mode is normal

B1L231 = H1_alu_func[1] & !H1_alu_func[0] & (N1L211) # !H1_alu_func[1] & H1_alu_func[0] & N1L69;

--B1L731 is alu:inst|alu_out[13]~5887 at LC6_G29
--operation mode is normal

B1L731 = H1_alu_func[1] & !H1_alu_func[0] & (N1L211) # !H1_alu_func[1] & H1_alu_func[0] & N1L69;


--B1L331 is alu:inst|alu_out[13]~5810 at LC1_G29
--operation mode is normal

B1L331 = H1_alu_func[2] & (B1L231 # B1L131) # !H1_alu_func[2] & (B1L031);

--B1L831 is alu:inst|alu_out[13]~5888 at LC1_G29
--operation mode is normal

B1L831 = H1_alu_func[2] & (B1L231 # B1L131) # !H1_alu_func[2] & (B1L031);


--B1L652 is alu:inst|reduce_nor~162 at LC3_G36
--operation mode is normal

B1L652 = !B1L311 & !B1L331 & !B1L32;

--B1L162 is alu:inst|reduce_nor~167 at LC3_G36
--operation mode is normal

B1L162 = !B1L311 & !B1L331 & !B1L32;


--N1L64 is bus_mux:inst28|alu_dr[6]~2332 at LC7_B15
--operation mode is normal

N1L64 = N1L811 & (H1_alu_in_sel[0] & (A1L64) # !H1_alu_in_sel[0] & K1_q[6]);

--N1L05 is bus_mux:inst28|alu_dr[6]~2403 at LC7_B15
--operation mode is normal

N1L05 = N1L811 & (H1_alu_in_sel[0] & (A1L64) # !H1_alu_in_sel[0] & K1_q[6]);


--L6_q[6] is reg:inst17|q[6] at LC3_B13
--operation mode is normal

L6_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L6_q[6] = DFFEA(L6_q[6]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L51Q is reg:inst17|q[6]~106 at LC3_B13
--operation mode is normal

L6L51Q = L6_q[6];


--L01_q[6] is reg:inst21|q[6] at LC8_B45
--operation mode is normal

L01_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L01_q[6] = DFFEA(L01_q[6]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L51Q is reg:inst21|q[6]~106 at LC8_B45
--operation mode is normal

L01L51Q = L01_q[6];


--L2_q[6] is reg:inst13|q[6] at LC1_B25
--operation mode is normal

L2_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L2_q[6] = DFFEA(L2_q[6]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L51Q is reg:inst13|q[6]~106 at LC1_B25
--operation mode is normal

L2L51Q = L2_q[6];


--M1L121 is reg_mux:inst27|dr[6]~446 at LC5_B13
--operation mode is normal

M1L121 = H1_dest_reg[3] & (L01_q[6] # H1_dest_reg[2]) # !H1_dest_reg[3] & L2_q[6] & (!H1_dest_reg[2]);

--M1L131 is reg_mux:inst27|dr[6]~606 at LC5_B13
--operation mode is normal

M1L131 = H1_dest_reg[3] & (L01_q[6] # H1_dest_reg[2]) # !H1_dest_reg[3] & L2_q[6] & (!H1_dest_reg[2]);


--L41_q[6] is reg:inst25|q[6] at LC6_B13
--operation mode is normal

L41_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L41_q[6] = DFFEA(L41_q[6]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L51Q is reg:inst25|q[6]~106 at LC6_B13
--operation mode is normal

L41L51Q = L41_q[6];


--M1L221 is reg_mux:inst27|dr[6]~447 at LC4_B13
--operation mode is normal

M1L221 = M1L121 & (L41_q[6] # !H1_dest_reg[2]) # !M1L121 & (H1_dest_reg[2] & L6_q[6]);

--M1L231 is reg_mux:inst27|dr[6]~607 at LC4_B13
--operation mode is normal

M1L231 = M1L121 & (L41_q[6] # !H1_dest_reg[2]) # !M1L121 & (H1_dest_reg[2] & L6_q[6]);


--L9_q[6] is reg:inst20|q[6] at LC3_B16
--operation mode is normal

L9_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L9_q[6] = DFFEA(L9_q[6]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L51Q is reg:inst20|q[6]~106 at LC3_B16
--operation mode is normal

L9L51Q = L9_q[6];


--L5_q[6] is reg:inst16|q[6] at LC1_B26
--operation mode is normal

L5_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L5_q[6] = DFFEA(L5_q[6]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L51Q is reg:inst16|q[6]~106 at LC1_B26
--operation mode is normal

L5L51Q = L5_q[6];


--L1_q[6] is reg:inst12|q[6] at LC5_B16
--operation mode is normal

L1_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L1_q[6] = DFFEA(L1_q[6]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L51Q is reg:inst12|q[6]~106 at LC5_B16
--operation mode is normal

L1L51Q = L1_q[6];


--M1L321 is reg_mux:inst27|dr[6]~448 at LC2_B12
--operation mode is normal

M1L321 = H1_dest_reg[2] & (L5_q[6] # H1_dest_reg[3]) # !H1_dest_reg[2] & L1_q[6] & (!H1_dest_reg[3]);

--M1L331 is reg_mux:inst27|dr[6]~608 at LC2_B12
--operation mode is normal

M1L331 = H1_dest_reg[2] & (L5_q[6] # H1_dest_reg[3]) # !H1_dest_reg[2] & L1_q[6] & (!H1_dest_reg[3]);


--L31_q[6] is reg:inst24|q[6] at LC4_B16
--operation mode is normal

L31_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L31_q[6] = DFFEA(L31_q[6]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L51Q is reg:inst24|q[6]~106 at LC4_B16
--operation mode is normal

L31L51Q = L31_q[6];


--M1L421 is reg_mux:inst27|dr[6]~449 at LC4_B12
--operation mode is normal

M1L421 = M1L321 & (L31_q[6] # !H1_dest_reg[3]) # !M1L321 & (H1_dest_reg[3] & L9_q[6]);

--M1L431 is reg_mux:inst27|dr[6]~609 at LC4_B12
--operation mode is normal

M1L431 = M1L321 & (L31_q[6] # !H1_dest_reg[3]) # !M1L321 & (H1_dest_reg[3] & L9_q[6]);


--L4_q[6] is reg:inst15|q[6] at LC3_B45
--operation mode is normal

L4_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L4_q[6] = DFFEA(L4_q[6]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L51Q is reg:inst15|q[6]~106 at LC3_B45
--operation mode is normal

L4L51Q = L4_q[6];


--L8_q[6] is reg:inst19|q[6] at LC1_B14
--operation mode is normal

L8_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L8_q[6] = DFFEA(L8_q[6]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L51Q is reg:inst19|q[6]~106 at LC1_B14
--operation mode is normal

L8L51Q = L8_q[6];


--L61_q[6] is reg:inst30|q[6] at LC4_B14
--operation mode is normal

L61_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L61_q[6] = DFFEA(L61_q[6]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L51Q is reg:inst30|q[6]~106 at LC4_B14
--operation mode is normal

L61L51Q = L61_q[6];


--M1L521 is reg_mux:inst27|dr[6]~450 at LC8_B14
--operation mode is normal

M1L521 = H1_dest_reg[3] & (L8_q[6] # H1_dest_reg[2]) # !H1_dest_reg[3] & L61_q[6] & (!H1_dest_reg[2]);

--M1L531 is reg_mux:inst27|dr[6]~610 at LC8_B14
--operation mode is normal

M1L531 = H1_dest_reg[3] & (L8_q[6] # H1_dest_reg[2]) # !H1_dest_reg[3] & L61_q[6] & (!H1_dest_reg[2]);


--L21_q[6] is reg:inst23|q[6] at LC6_B25
--operation mode is normal

L21_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L21_q[6] = DFFEA(L21_q[6]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L51Q is reg:inst23|q[6]~106 at LC6_B25
--operation mode is normal

L21L51Q = L21_q[6];


--M1L621 is reg_mux:inst27|dr[6]~451 at LC5_B12
--operation mode is normal

M1L621 = M1L521 & (L21_q[6] # !H1_dest_reg[2]) # !M1L521 & (H1_dest_reg[2] & L4_q[6]);

--M1L631 is reg_mux:inst27|dr[6]~611 at LC5_B12
--operation mode is normal

M1L631 = M1L521 & (L21_q[6] # !H1_dest_reg[2]) # !M1L521 & (H1_dest_reg[2] & L4_q[6]);


--M1L721 is reg_mux:inst27|dr[6]~452 at LC6_B12
--operation mode is normal

M1L721 = H1_dest_reg[0] & (M1L421 # H1_dest_reg[1]) # !H1_dest_reg[0] & M1L621 & (!H1_dest_reg[1]);

--M1L731 is reg_mux:inst27|dr[6]~612 at LC6_B12
--operation mode is normal

M1L731 = H1_dest_reg[0] & (M1L421 # H1_dest_reg[1]) # !H1_dest_reg[0] & M1L621 & (!H1_dest_reg[1]);


--L11_q[6] is reg:inst22|q[6] at LC4_B19
--operation mode is normal

L11_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L11_q[6] = DFFEA(L11_q[6]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L51Q is reg:inst22|q[6]~106 at LC4_B19
--operation mode is normal

L11L51Q = L11_q[6];


--L7_q[6] is reg:inst18|q[6] at LC2_B25
--operation mode is normal

L7_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L7_q[6] = DFFEA(L7_q[6]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L51Q is reg:inst18|q[6]~106 at LC2_B25
--operation mode is normal

L7L51Q = L7_q[6];


--L3_q[6] is reg:inst14|q[6] at LC4_B10
--operation mode is normal

L3_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L3_q[6] = DFFEA(L3_q[6]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L51Q is reg:inst14|q[6]~106 at LC4_B10
--operation mode is normal

L3L51Q = L3_q[6];


--M1L821 is reg_mux:inst27|dr[6]~453 at LC5_B10
--operation mode is normal

M1L821 = H1_dest_reg[2] & (L7_q[6] # H1_dest_reg[3]) # !H1_dest_reg[2] & L3_q[6] & (!H1_dest_reg[3]);

--M1L831 is reg_mux:inst27|dr[6]~613 at LC5_B10
--operation mode is normal

M1L831 = H1_dest_reg[2] & (L7_q[6] # H1_dest_reg[3]) # !H1_dest_reg[2] & L3_q[6] & (!H1_dest_reg[3]);


--L51_q[6] is reg:inst26|q[6] at LC6_B10
--operation mode is normal

L51_q[6]_lut_out = H1_alu_func[2] & B1L06 # !H1_alu_func[2] & (B1L26);
L51_q[6] = DFFEA(L51_q[6]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L51Q is reg:inst26|q[6]~106 at LC6_B10
--operation mode is normal

L51L51Q = L51_q[6];


--M1L921 is reg_mux:inst27|dr[6]~454 at LC1_B10
--operation mode is normal

M1L921 = M1L821 & (L51_q[6] # !H1_dest_reg[3]) # !M1L821 & (H1_dest_reg[3] & L11_q[6]);

--M1L931 is reg_mux:inst27|dr[6]~614 at LC1_B10
--operation mode is normal

M1L931 = M1L821 & (L51_q[6] # !H1_dest_reg[3]) # !M1L821 & (H1_dest_reg[3] & L11_q[6]);


--M1L031 is reg_mux:inst27|dr[6]~455 at LC7_B12
--operation mode is normal

M1L031 = M1L721 & (M1L921 # !H1_dest_reg[1]) # !M1L721 & (H1_dest_reg[1] & M1L221);

--M1L041 is reg_mux:inst27|dr[6]~615 at LC7_B12
--operation mode is normal

M1L041 = M1L721 & (M1L921 # !H1_dest_reg[1]) # !M1L721 & (H1_dest_reg[1] & M1L221);


--N1L74 is bus_mux:inst28|alu_dr[6]~2333 at LC8_B12
--operation mode is normal

N1L74 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L031;

--N1L15 is bus_mux:inst28|alu_dr[6]~2404 at LC8_B12
--operation mode is normal

N1L15 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L031;


--N1L84 is bus_mux:inst28|alu_dr[6]~2334 at LC3_B12
--operation mode is normal

N1L84 = N1L74 # N1L64 # K1_q[6] & N1L021;

--N1L25 is bus_mux:inst28|alu_dr[6]~2405 at LC3_B12
--operation mode is normal

N1L25 = N1L74 # N1L64 # K1_q[6] & N1L021;


--M1L528 is reg_mux:inst27|sr[6]~416 at LC7_B13
--operation mode is normal

M1L528 = H1_sour_reg[3] & (L01_q[6] # H1_sour_reg[2]) # !H1_sour_reg[3] & L2_q[6] & (!H1_sour_reg[2]);

--M1L538 is reg_mux:inst27|sr[6]~576 at LC7_B13
--operation mode is normal

M1L538 = H1_sour_reg[3] & (L01_q[6] # H1_sour_reg[2]) # !H1_sour_reg[3] & L2_q[6] & (!H1_sour_reg[2]);


--M1L628 is reg_mux:inst27|sr[6]~417 at LC1_B13
--operation mode is normal

M1L628 = M1L528 & (L41_q[6] # !H1_sour_reg[2]) # !M1L528 & (H1_sour_reg[2] & L6_q[6]);

--M1L638 is reg_mux:inst27|sr[6]~577 at LC1_B13
--operation mode is normal

M1L638 = M1L528 & (L41_q[6] # !H1_sour_reg[2]) # !M1L528 & (H1_sour_reg[2] & L6_q[6]);


--M1L728 is reg_mux:inst27|sr[6]~418 at LC6_B16
--operation mode is normal

M1L728 = H1_sour_reg[2] & (L5_q[6] # H1_sour_reg[3]) # !H1_sour_reg[2] & L1_q[6] & (!H1_sour_reg[3]);

--M1L738 is reg_mux:inst27|sr[6]~578 at LC6_B16
--operation mode is normal

M1L738 = H1_sour_reg[2] & (L5_q[6] # H1_sour_reg[3]) # !H1_sour_reg[2] & L1_q[6] & (!H1_sour_reg[3]);


--M1L828 is reg_mux:inst27|sr[6]~419 at LC1_B16
--operation mode is normal

M1L828 = M1L728 & (L31_q[6] # !H1_sour_reg[3]) # !M1L728 & (H1_sour_reg[3] & L9_q[6]);

--M1L838 is reg_mux:inst27|sr[6]~579 at LC1_B16
--operation mode is normal

M1L838 = M1L728 & (L31_q[6] # !H1_sour_reg[3]) # !M1L728 & (H1_sour_reg[3] & L9_q[6]);


--M1L928 is reg_mux:inst27|sr[6]~420 at LC5_B14
--operation mode is normal

M1L928 = H1_sour_reg[3] & (L8_q[6] # H1_sour_reg[2]) # !H1_sour_reg[3] & L61_q[6] & (!H1_sour_reg[2]);

--M1L938 is reg_mux:inst27|sr[6]~580 at LC5_B14
--operation mode is normal

M1L938 = H1_sour_reg[3] & (L8_q[6] # H1_sour_reg[2]) # !H1_sour_reg[3] & L61_q[6] & (!H1_sour_reg[2]);


--M1L038 is reg_mux:inst27|sr[6]~421 at LC6_B14
--operation mode is normal

M1L038 = M1L928 & (L21_q[6] # !H1_sour_reg[2]) # !M1L928 & (H1_sour_reg[2] & L4_q[6]);

--M1L048 is reg_mux:inst27|sr[6]~581 at LC6_B14
--operation mode is normal

M1L048 = M1L928 & (L21_q[6] # !H1_sour_reg[2]) # !M1L928 & (H1_sour_reg[2] & L4_q[6]);


--M1L138 is reg_mux:inst27|sr[6]~422 at LC2_B14
--operation mode is normal

M1L138 = H1_sour_reg[0] & (M1L828 # H1_sour_reg[1]) # !H1_sour_reg[0] & M1L038 & (!H1_sour_reg[1]);

--M1L148 is reg_mux:inst27|sr[6]~582 at LC2_B14
--operation mode is normal

M1L148 = H1_sour_reg[0] & (M1L828 # H1_sour_reg[1]) # !H1_sour_reg[0] & M1L038 & (!H1_sour_reg[1]);


--M1L238 is reg_mux:inst27|sr[6]~423 at LC7_B10
--operation mode is normal

M1L238 = H1_sour_reg[2] & (L7_q[6] # H1_sour_reg[3]) # !H1_sour_reg[2] & L3_q[6] & (!H1_sour_reg[3]);

--M1L248 is reg_mux:inst27|sr[6]~583 at LC7_B10
--operation mode is normal

M1L248 = H1_sour_reg[2] & (L7_q[6] # H1_sour_reg[3]) # !H1_sour_reg[2] & L3_q[6] & (!H1_sour_reg[3]);


--M1L338 is reg_mux:inst27|sr[6]~424 at LC2_B10
--operation mode is normal

M1L338 = M1L238 & (L51_q[6] # !H1_sour_reg[3]) # !M1L238 & (H1_sour_reg[3] & L11_q[6]);

--M1L348 is reg_mux:inst27|sr[6]~584 at LC2_B10
--operation mode is normal

M1L348 = M1L238 & (L51_q[6] # !H1_sour_reg[3]) # !M1L238 & (H1_sour_reg[3] & L11_q[6]);


--M1L438 is reg_mux:inst27|sr[6]~425 at LC1_G8
--operation mode is normal

M1L438 = M1L138 & (M1L338 # !H1_sour_reg[1]) # !M1L138 & (H1_sour_reg[1] & M1L628);

--M1L448 is reg_mux:inst27|sr[6]~585 at LC1_G8
--operation mode is normal

M1L448 = M1L138 & (M1L338 # !H1_sour_reg[1]) # !M1L138 & (H1_sour_reg[1] & M1L628);


--N1L141 is bus_mux:inst28|alu_sr[6]~645 at LC3_G8
--operation mode is normal

N1L141 = H1_offset[6] & (N1L021 # M1L438 & N1L161) # !H1_offset[6] & M1L438 & N1L161;

--N1L241 is bus_mux:inst28|alu_sr[6]~663 at LC3_G8
--operation mode is normal

N1L241 = H1_offset[6] & (N1L021 # M1L438 & N1L161) # !H1_offset[6] & M1L438 & N1L161;


--B1L95 is alu:inst|alu_out[6]~5811 at LC1_G39
--operation mode is normal

B1L95 = H1_alu_func[1] & (N1L65) # !H1_alu_func[1] & (N1L141 $ N1L84);

--B1L46 is alu:inst|alu_out[6]~5889 at LC1_G39
--operation mode is normal

B1L46 = H1_alu_func[1] & (N1L65) # !H1_alu_func[1] & (N1L141 $ N1L84);


--N1L83 is bus_mux:inst28|alu_dr[5]~2335 at LC7_H21
--operation mode is normal

N1L83 = N1L811 & (H1_alu_in_sel[0] & (A1L74) # !H1_alu_in_sel[0] & K1_q[5]);

--N1L24 is bus_mux:inst28|alu_dr[5]~2406 at LC7_H21
--operation mode is normal

N1L24 = N1L811 & (H1_alu_in_sel[0] & (A1L74) # !H1_alu_in_sel[0] & K1_q[5]);


--L6_q[5] is reg:inst17|q[5] at LC1_G5
--operation mode is normal

L6_q[5]_lut_out = B1L35;
L6_q[5] = DFFEA(L6_q[5]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L31Q is reg:inst17|q[5]~107 at LC1_G5
--operation mode is normal

L6L31Q = L6_q[5];


--L5_q[5] is reg:inst16|q[5] at LC6_G49
--operation mode is normal

L5_q[5]_lut_out = B1L35;
L5_q[5] = DFFEA(L5_q[5]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L31Q is reg:inst16|q[5]~107 at LC6_G49
--operation mode is normal

L5L31Q = L5_q[5];


--L4_q[5] is reg:inst15|q[5] at LC2_G5
--operation mode is normal

L4_q[5]_lut_out = B1L35;
L4_q[5] = DFFEA(L4_q[5]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L31Q is reg:inst15|q[5]~107 at LC2_G5
--operation mode is normal

L4L31Q = L4_q[5];


--M1L101 is reg_mux:inst27|dr[5]~456 at LC3_G5
--operation mode is normal

M1L101 = H1_dest_reg[0] & (L5_q[5] # H1_dest_reg[1]) # !H1_dest_reg[0] & L4_q[5] & (!H1_dest_reg[1]);

--M1L111 is reg_mux:inst27|dr[5]~616 at LC3_G5
--operation mode is normal

M1L111 = H1_dest_reg[0] & (L5_q[5] # H1_dest_reg[1]) # !H1_dest_reg[0] & L4_q[5] & (!H1_dest_reg[1]);


--L7_q[5] is reg:inst18|q[5] at LC8_G42
--operation mode is normal

L7_q[5]_lut_out = B1L35;
L7_q[5] = DFFEA(L7_q[5]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L31Q is reg:inst18|q[5]~107 at LC8_G42
--operation mode is normal

L7L31Q = L7_q[5];


--M1L201 is reg_mux:inst27|dr[5]~457 at LC8_G5
--operation mode is normal

M1L201 = M1L101 & (L7_q[5] # !H1_dest_reg[1]) # !M1L101 & (H1_dest_reg[1] & L6_q[5]);

--M1L211 is reg_mux:inst27|dr[5]~617 at LC8_G5
--operation mode is normal

M1L211 = M1L101 & (L7_q[5] # !H1_dest_reg[1]) # !M1L101 & (H1_dest_reg[1] & L6_q[5]);


--L9_q[5] is reg:inst20|q[5] at LC8_G22
--operation mode is normal

L9_q[5]_lut_out = B1L35;
L9_q[5] = DFFEA(L9_q[5]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L31Q is reg:inst20|q[5]~107 at LC8_G22
--operation mode is normal

L9L31Q = L9_q[5];


--L01_q[5] is reg:inst21|q[5] at LC2_E38
--operation mode is normal

L01_q[5]_lut_out = B1L35;
L01_q[5] = DFFEA(L01_q[5]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L31Q is reg:inst21|q[5]~107 at LC2_E38
--operation mode is normal

L01L31Q = L01_q[5];


--L8_q[5] is reg:inst19|q[5] at LC4_G22
--operation mode is normal

L8_q[5]_lut_out = B1L35;
L8_q[5] = DFFEA(L8_q[5]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L31Q is reg:inst19|q[5]~107 at LC4_G22
--operation mode is normal

L8L31Q = L8_q[5];


--M1L301 is reg_mux:inst27|dr[5]~458 at LC1_G6
--operation mode is normal

M1L301 = H1_dest_reg[1] & (L01_q[5] # H1_dest_reg[0]) # !H1_dest_reg[1] & L8_q[5] & (!H1_dest_reg[0]);

--M1L311 is reg_mux:inst27|dr[5]~618 at LC1_G6
--operation mode is normal

M1L311 = H1_dest_reg[1] & (L01_q[5] # H1_dest_reg[0]) # !H1_dest_reg[1] & L8_q[5] & (!H1_dest_reg[0]);


--L11_q[5] is reg:inst22|q[5] at LC3_I42
--operation mode is normal

L11_q[5]_lut_out = B1L35;
L11_q[5] = DFFEA(L11_q[5]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L31Q is reg:inst22|q[5]~107 at LC3_I42
--operation mode is normal

L11L31Q = L11_q[5];


--M1L401 is reg_mux:inst27|dr[5]~459 at LC3_G6
--operation mode is normal

M1L401 = M1L301 & (L11_q[5] # !H1_dest_reg[0]) # !M1L301 & (H1_dest_reg[0] & L9_q[5]);

--M1L411 is reg_mux:inst27|dr[5]~619 at LC3_G6
--operation mode is normal

M1L411 = M1L301 & (L11_q[5] # !H1_dest_reg[0]) # !M1L301 & (H1_dest_reg[0] & L9_q[5]);


--L1_q[5] is reg:inst12|q[5] at LC3_E38
--operation mode is normal

L1_q[5]_lut_out = B1L35;
L1_q[5] = DFFEA(L1_q[5]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L31Q is reg:inst12|q[5]~107 at LC3_E38
--operation mode is normal

L1L31Q = L1_q[5];


--L2_q[5] is reg:inst13|q[5] at LC2_G9
--operation mode is normal

L2_q[5]_lut_out = B1L35;
L2_q[5] = DFFEA(L2_q[5]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L31Q is reg:inst13|q[5]~107 at LC2_G9
--operation mode is normal

L2L31Q = L2_q[5];


--L61_q[5] is reg:inst30|q[5] at LC3_G9
--operation mode is normal

L61_q[5]_lut_out = B1L35;
L61_q[5] = DFFEA(L61_q[5]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L31Q is reg:inst30|q[5]~107 at LC3_G9
--operation mode is normal

L61L31Q = L61_q[5];


--M1L501 is reg_mux:inst27|dr[5]~460 at LC7_G9
--operation mode is normal

M1L501 = H1_dest_reg[1] & (L2_q[5] # H1_dest_reg[0]) # !H1_dest_reg[1] & L61_q[5] & (!H1_dest_reg[0]);

--M1L511 is reg_mux:inst27|dr[5]~620 at LC7_G9
--operation mode is normal

M1L511 = H1_dest_reg[1] & (L2_q[5] # H1_dest_reg[0]) # !H1_dest_reg[1] & L61_q[5] & (!H1_dest_reg[0]);


--L3_q[5] is reg:inst14|q[5] at LC8_G45
--operation mode is normal

L3_q[5]_lut_out = B1L35;
L3_q[5] = DFFEA(L3_q[5]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L31Q is reg:inst14|q[5]~107 at LC8_G45
--operation mode is normal

L3L31Q = L3_q[5];


--M1L601 is reg_mux:inst27|dr[5]~461 at LC4_G6
--operation mode is normal

M1L601 = M1L501 & (L3_q[5] # !H1_dest_reg[0]) # !M1L501 & (H1_dest_reg[0] & L1_q[5]);

--M1L611 is reg_mux:inst27|dr[5]~621 at LC4_G6
--operation mode is normal

M1L611 = M1L501 & (L3_q[5] # !H1_dest_reg[0]) # !M1L501 & (H1_dest_reg[0] & L1_q[5]);


--M1L701 is reg_mux:inst27|dr[5]~462 at LC5_G6
--operation mode is normal

M1L701 = H1_dest_reg[3] & (M1L401 # H1_dest_reg[2]) # !H1_dest_reg[3] & M1L601 & (!H1_dest_reg[2]);

--M1L711 is reg_mux:inst27|dr[5]~622 at LC5_G6
--operation mode is normal

M1L711 = H1_dest_reg[3] & (M1L401 # H1_dest_reg[2]) # !H1_dest_reg[3] & M1L601 & (!H1_dest_reg[2]);


--L41_q[5] is reg:inst25|q[5] at LC1_G4
--operation mode is normal

L41_q[5]_lut_out = B1L35;
L41_q[5] = DFFEA(L41_q[5]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L31Q is reg:inst25|q[5]~107 at LC1_G4
--operation mode is normal

L41L31Q = L41_q[5];


--L31_q[5] is reg:inst24|q[5] at LC7_G49
--operation mode is normal

L31_q[5]_lut_out = B1L35;
L31_q[5] = DFFEA(L31_q[5]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L31Q is reg:inst24|q[5]~107 at LC7_G49
--operation mode is normal

L31L31Q = L31_q[5];


--L21_q[5] is reg:inst23|q[5] at LC4_G49
--operation mode is normal

L21_q[5]_lut_out = B1L35;
L21_q[5] = DFFEA(L21_q[5]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L31Q is reg:inst23|q[5]~107 at LC4_G49
--operation mode is normal

L21L31Q = L21_q[5];


--M1L801 is reg_mux:inst27|dr[5]~463 at LC2_G4
--operation mode is normal

M1L801 = H1_dest_reg[0] & (L31_q[5] # H1_dest_reg[1]) # !H1_dest_reg[0] & L21_q[5] & (!H1_dest_reg[1]);

--M1L811 is reg_mux:inst27|dr[5]~623 at LC2_G4
--operation mode is normal

M1L811 = H1_dest_reg[0] & (L31_q[5] # H1_dest_reg[1]) # !H1_dest_reg[0] & L21_q[5] & (!H1_dest_reg[1]);


--L51_q[5] is reg:inst26|q[5] at LC3_G4
--operation mode is normal

L51_q[5]_lut_out = B1L35;
L51_q[5] = DFFEA(L51_q[5]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L31Q is reg:inst26|q[5]~107 at LC3_G4
--operation mode is normal

L51L31Q = L51_q[5];


--M1L901 is reg_mux:inst27|dr[5]~464 at LC8_G4
--operation mode is normal

M1L901 = M1L801 & (L51_q[5] # !H1_dest_reg[1]) # !M1L801 & (H1_dest_reg[1] & L41_q[5]);

--M1L911 is reg_mux:inst27|dr[5]~624 at LC8_G4
--operation mode is normal

M1L911 = M1L801 & (L51_q[5] # !H1_dest_reg[1]) # !M1L801 & (H1_dest_reg[1] & L41_q[5]);


--M1L011 is reg_mux:inst27|dr[5]~465 at LC6_G6
--operation mode is normal

M1L011 = M1L701 & (M1L901 # !H1_dest_reg[2]) # !M1L701 & (H1_dest_reg[2] & M1L201);

--M1L021 is reg_mux:inst27|dr[5]~625 at LC6_G6
--operation mode is normal

M1L021 = M1L701 & (M1L901 # !H1_dest_reg[2]) # !M1L701 & (H1_dest_reg[2] & M1L201);


--N1L93 is bus_mux:inst28|alu_dr[5]~2336 at LC7_G6
--operation mode is normal

N1L93 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L011;

--N1L34 is bus_mux:inst28|alu_dr[5]~2407 at LC7_G6
--operation mode is normal

N1L34 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L011;


--N1L04 is bus_mux:inst28|alu_dr[5]~2337 at LC2_G6
--operation mode is normal

N1L04 = N1L93 # N1L83 # K1_q[5] & N1L021;

--N1L44 is bus_mux:inst28|alu_dr[5]~2408 at LC2_G6
--operation mode is normal

N1L44 = N1L93 # N1L83 # K1_q[5] & N1L021;


--B1L06 is alu:inst|alu_out[6]~5812 at LC5_G39
--operation mode is normal

B1L06 = H1_alu_func[0] & !H1_alu_func[1] & N1L04 # !H1_alu_func[0] & (B1L95);

--B1L56 is alu:inst|alu_out[6]~5890 at LC5_G39
--operation mode is normal

B1L56 = H1_alu_func[0] & !H1_alu_func[1] & N1L04 # !H1_alu_func[0] & (B1L95);


--V9_cs_buffer[8] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC7_G11
--operation mode is arithmetic

V9_cs_buffer[8] = V6_cs_buffer[8] $ !V9_cout[7];

--V9L13 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~307 at LC7_G11
--operation mode is arithmetic

V9L13 = V6_cs_buffer[8] $ !V9_cout[7];

--V9_cout[8] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[8] at LC7_G11
--operation mode is arithmetic

V9_cout[8] = CARRY(V9_cout[7] # !V6_cs_buffer[8]);


--B1L862 is alu:inst|temp2~6 at LC2_G40
--operation mode is normal

B1L862 = N1L141 & N1L84;

--B1L192 is alu:inst|temp2~1520 at LC2_G40
--operation mode is normal

B1L192 = N1L141 & N1L84;


--V3_cs_buffer[7] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC4_G21
--operation mode is arithmetic

V3_cs_buffer[7] = N1L84 $ N1L141 $ V3_cout[6];

--V3L43 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~299 at LC4_G21
--operation mode is arithmetic

V3L43 = N1L84 $ N1L141 $ V3_cout[6];

--V3_cout[7] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[7] at LC4_G21
--operation mode is arithmetic

V3_cout[7] = CARRY(N1L84 & (N1L141 # V3_cout[6]) # !N1L84 & N1L141 & V3_cout[6]);


--B1L16 is alu:inst|alu_out[6]~5813 at LC4_G40
--operation mode is normal

B1L16 = H1_alu_func[1] & (B1L862 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[7] & (!H1_alu_func[0]);

--B1L66 is alu:inst|alu_out[6]~5891 at LC4_G40
--operation mode is normal

B1L66 = H1_alu_func[1] & (B1L862 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[7] & (!H1_alu_func[0]);


--B1L672 is alu:inst|temp2~22 at LC6_G40
--operation mode is normal

B1L672 = N1L141 # N1L84;

--B1L292 is alu:inst|temp2~1521 at LC6_G40
--operation mode is normal

B1L292 = N1L141 # N1L84;


--B1L26 is alu:inst|alu_out[6]~5814 at LC1_G40
--operation mode is normal

B1L26 = B1L16 & (B1L672 # !H1_alu_func[0]) # !B1L16 & (H1_alu_func[0] & !V9_cs_buffer[8]);

--B1L76 is alu:inst|alu_out[6]~5892 at LC1_G40
--operation mode is normal

B1L76 = B1L16 & (B1L672 # !H1_alu_func[0]) # !B1L16 & (H1_alu_func[0] & !V9_cs_buffer[8]);


--B1L36 is alu:inst|alu_out[6]~5815 at LC5_G40
--operation mode is normal

B1L36 = H1_alu_func[2] & (B1L06) # !H1_alu_func[2] & B1L26;

--B1L86 is alu:inst|alu_out[6]~5893 at LC5_G40
--operation mode is normal

B1L86 = H1_alu_func[2] & (B1L06) # !H1_alu_func[2] & B1L26;


--N1L03 is bus_mux:inst28|alu_dr[4]~2338 at LC3_H21
--operation mode is normal

N1L03 = N1L811 & (H1_alu_in_sel[0] & (A1L84) # !H1_alu_in_sel[0] & K1_q[4]);

--N1L43 is bus_mux:inst28|alu_dr[4]~2409 at LC3_H21
--operation mode is normal

N1L43 = N1L811 & (H1_alu_in_sel[0] & (A1L84) # !H1_alu_in_sel[0] & K1_q[4]);


--L5_q[4] is reg:inst16|q[4] at LC6_H44
--operation mode is normal

L5_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L5_q[4] = DFFEA(L5_q[4]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L11Q is reg:inst16|q[4]~108 at LC6_H44
--operation mode is normal

L5L11Q = L5_q[4];


--L9_q[4] is reg:inst20|q[4] at LC4_H3
--operation mode is normal

L9_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L9_q[4] = DFFEA(L9_q[4]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L11Q is reg:inst20|q[4]~108 at LC4_H3
--operation mode is normal

L9L11Q = L9_q[4];


--L1_q[4] is reg:inst12|q[4] at LC5_H3
--operation mode is normal

L1_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L1_q[4] = DFFEA(L1_q[4]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L11Q is reg:inst12|q[4]~108 at LC5_H3
--operation mode is normal

L1L11Q = L1_q[4];


--M1L18 is reg_mux:inst27|dr[4]~466 at LC6_H3
--operation mode is normal

M1L18 = H1_dest_reg[3] & (L9_q[4] # H1_dest_reg[2]) # !H1_dest_reg[3] & L1_q[4] & (!H1_dest_reg[2]);

--M1L19 is reg_mux:inst27|dr[4]~626 at LC6_H3
--operation mode is normal

M1L19 = H1_dest_reg[3] & (L9_q[4] # H1_dest_reg[2]) # !H1_dest_reg[3] & L1_q[4] & (!H1_dest_reg[2]);


--L31_q[4] is reg:inst24|q[4] at LC1_H52
--operation mode is normal

L31_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L31_q[4] = DFFEA(L31_q[4]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L11Q is reg:inst24|q[4]~108 at LC1_H52
--operation mode is normal

L31L11Q = L31_q[4];


--M1L28 is reg_mux:inst27|dr[4]~467 at LC1_H3
--operation mode is normal

M1L28 = M1L18 & (L31_q[4] # !H1_dest_reg[2]) # !M1L18 & (H1_dest_reg[2] & L5_q[4]);

--M1L29 is reg_mux:inst27|dr[4]~627 at LC1_H3
--operation mode is normal

M1L29 = M1L18 & (L31_q[4] # !H1_dest_reg[2]) # !M1L18 & (H1_dest_reg[2] & L5_q[4]);


--L01_q[4] is reg:inst21|q[4] at LC3_H44
--operation mode is normal

L01_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L01_q[4] = DFFEA(L01_q[4]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L11Q is reg:inst21|q[4]~108 at LC3_H44
--operation mode is normal

L01L11Q = L01_q[4];


--L6_q[4] is reg:inst17|q[4] at LC1_H44
--operation mode is normal

L6_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L6_q[4] = DFFEA(L6_q[4]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L11Q is reg:inst17|q[4]~108 at LC1_H44
--operation mode is normal

L6L11Q = L6_q[4];


--L2_q[4] is reg:inst13|q[4] at LC5_H50
--operation mode is normal

L2_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L2_q[4] = DFFEA(L2_q[4]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L11Q is reg:inst13|q[4]~108 at LC5_H50
--operation mode is normal

L2L11Q = L2_q[4];


--M1L38 is reg_mux:inst27|dr[4]~468 at LC2_H5
--operation mode is normal

M1L38 = H1_dest_reg[2] & (L6_q[4] # H1_dest_reg[3]) # !H1_dest_reg[2] & L2_q[4] & (!H1_dest_reg[3]);

--M1L39 is reg_mux:inst27|dr[4]~628 at LC2_H5
--operation mode is normal

M1L39 = H1_dest_reg[2] & (L6_q[4] # H1_dest_reg[3]) # !H1_dest_reg[2] & L2_q[4] & (!H1_dest_reg[3]);


--L41_q[4] is reg:inst25|q[4] at LC7_H44
--operation mode is normal

L41_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L41_q[4] = DFFEA(L41_q[4]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L11Q is reg:inst25|q[4]~108 at LC7_H44
--operation mode is normal

L41L11Q = L41_q[4];


--M1L48 is reg_mux:inst27|dr[4]~469 at LC3_H5
--operation mode is normal

M1L48 = M1L38 & (L41_q[4] # !H1_dest_reg[3]) # !M1L38 & (H1_dest_reg[3] & L01_q[4]);

--M1L49 is reg_mux:inst27|dr[4]~629 at LC3_H5
--operation mode is normal

M1L49 = M1L38 & (L41_q[4] # !H1_dest_reg[3]) # !M1L38 & (H1_dest_reg[3] & L01_q[4]);


--L8_q[4] is reg:inst19|q[4] at LC1_H48
--operation mode is normal

L8_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L8_q[4] = DFFEA(L8_q[4]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L11Q is reg:inst19|q[4]~108 at LC1_H48
--operation mode is normal

L8L11Q = L8_q[4];


--L4_q[4] is reg:inst15|q[4] at LC1_H4
--operation mode is normal

L4_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L4_q[4] = DFFEA(L4_q[4]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L11Q is reg:inst15|q[4]~108 at LC1_H4
--operation mode is normal

L4L11Q = L4_q[4];


--L61_q[4] is reg:inst30|q[4] at LC2_H4
--operation mode is normal

L61_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L61_q[4] = DFFEA(L61_q[4]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L11Q is reg:inst30|q[4]~108 at LC2_H4
--operation mode is normal

L61L11Q = L61_q[4];


--M1L58 is reg_mux:inst27|dr[4]~470 at LC3_H4
--operation mode is normal

M1L58 = H1_dest_reg[2] & (L4_q[4] # H1_dest_reg[3]) # !H1_dest_reg[2] & L61_q[4] & (!H1_dest_reg[3]);

--M1L59 is reg_mux:inst27|dr[4]~630 at LC3_H4
--operation mode is normal

M1L59 = H1_dest_reg[2] & (L4_q[4] # H1_dest_reg[3]) # !H1_dest_reg[2] & L61_q[4] & (!H1_dest_reg[3]);


--L21_q[4] is reg:inst23|q[4] at LC3_H52
--operation mode is normal

L21_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L21_q[4] = DFFEA(L21_q[4]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L11Q is reg:inst23|q[4]~108 at LC3_H52
--operation mode is normal

L21L11Q = L21_q[4];


--M1L68 is reg_mux:inst27|dr[4]~471 at LC5_H4
--operation mode is normal

M1L68 = M1L58 & (L21_q[4] # !H1_dest_reg[3]) # !M1L58 & (H1_dest_reg[3] & L8_q[4]);

--M1L69 is reg_mux:inst27|dr[4]~631 at LC5_H4
--operation mode is normal

M1L69 = M1L58 & (L21_q[4] # !H1_dest_reg[3]) # !M1L58 & (H1_dest_reg[3] & L8_q[4]);


--M1L78 is reg_mux:inst27|dr[4]~472 at LC5_H5
--operation mode is normal

M1L78 = H1_dest_reg[1] & (M1L48 # H1_dest_reg[0]) # !H1_dest_reg[1] & M1L68 & (!H1_dest_reg[0]);

--M1L79 is reg_mux:inst27|dr[4]~632 at LC5_H5
--operation mode is normal

M1L79 = H1_dest_reg[1] & (M1L48 # H1_dest_reg[0]) # !H1_dest_reg[1] & M1L68 & (!H1_dest_reg[0]);


--L7_q[4] is reg:inst18|q[4] at LC1_H1
--operation mode is normal

L7_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L7_q[4] = DFFEA(L7_q[4]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L11Q is reg:inst18|q[4]~108 at LC1_H1
--operation mode is normal

L7L11Q = L7_q[4];


--L11_q[4] is reg:inst22|q[4] at LC3_H1
--operation mode is normal

L11_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L11_q[4] = DFFEA(L11_q[4]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L11Q is reg:inst22|q[4]~108 at LC3_H1
--operation mode is normal

L11L11Q = L11_q[4];


--L3_q[4] is reg:inst14|q[4] at LC3_H50
--operation mode is normal

L3_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L3_q[4] = DFFEA(L3_q[4]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L11Q is reg:inst14|q[4]~108 at LC3_H50
--operation mode is normal

L3L11Q = L3_q[4];


--M1L88 is reg_mux:inst27|dr[4]~473 at LC4_H1
--operation mode is normal

M1L88 = H1_dest_reg[3] & (L11_q[4] # H1_dest_reg[2]) # !H1_dest_reg[3] & L3_q[4] & (!H1_dest_reg[2]);

--M1L89 is reg_mux:inst27|dr[4]~633 at LC4_H1
--operation mode is normal

M1L89 = H1_dest_reg[3] & (L11_q[4] # H1_dest_reg[2]) # !H1_dest_reg[3] & L3_q[4] & (!H1_dest_reg[2]);


--L51_q[4] is reg:inst26|q[4] at LC5_H44
--operation mode is normal

L51_q[4]_lut_out = H1_alu_func[2] & B1L04 # !H1_alu_func[2] & (B1L24);
L51_q[4] = DFFEA(L51_q[4]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L11Q is reg:inst26|q[4]~108 at LC5_H44
--operation mode is normal

L51L11Q = L51_q[4];


--M1L98 is reg_mux:inst27|dr[4]~474 at LC2_H1
--operation mode is normal

M1L98 = M1L88 & (L51_q[4] # !H1_dest_reg[2]) # !M1L88 & (H1_dest_reg[2] & L7_q[4]);

--M1L99 is reg_mux:inst27|dr[4]~634 at LC2_H1
--operation mode is normal

M1L99 = M1L88 & (L51_q[4] # !H1_dest_reg[2]) # !M1L88 & (H1_dest_reg[2] & L7_q[4]);


--M1L09 is reg_mux:inst27|dr[4]~475 at LC6_H5
--operation mode is normal

M1L09 = M1L78 & (M1L98 # !H1_dest_reg[0]) # !M1L78 & (H1_dest_reg[0] & M1L28);

--M1L001 is reg_mux:inst27|dr[4]~635 at LC6_H5
--operation mode is normal

M1L001 = M1L78 & (M1L98 # !H1_dest_reg[0]) # !M1L78 & (H1_dest_reg[0] & M1L28);


--N1L13 is bus_mux:inst28|alu_dr[4]~2339 at LC7_H5
--operation mode is normal

N1L13 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L09;

--N1L53 is bus_mux:inst28|alu_dr[4]~2410 at LC7_H5
--operation mode is normal

N1L53 = !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L09;


--N1L23 is bus_mux:inst28|alu_dr[4]~2340 at LC4_H5
--operation mode is normal

N1L23 = N1L13 # N1L03 # K1_q[4] & N1L021;

--N1L63 is bus_mux:inst28|alu_dr[4]~2411 at LC4_H5
--operation mode is normal

N1L63 = N1L13 # N1L03 # K1_q[4] & N1L021;


--M1L587 is reg_mux:inst27|sr[4]~426 at LC7_H3
--operation mode is normal

M1L587 = H1_sour_reg[3] & (L9_q[4] # H1_sour_reg[2]) # !H1_sour_reg[3] & L1_q[4] & (!H1_sour_reg[2]);

--M1L597 is reg_mux:inst27|sr[4]~586 at LC7_H3
--operation mode is normal

M1L597 = H1_sour_reg[3] & (L9_q[4] # H1_sour_reg[2]) # !H1_sour_reg[3] & L1_q[4] & (!H1_sour_reg[2]);


--M1L687 is reg_mux:inst27|sr[4]~427 at LC2_H3
--operation mode is normal

M1L687 = M1L587 & (L31_q[4] # !H1_sour_reg[2]) # !M1L587 & (H1_sour_reg[2] & L5_q[4]);

--M1L697 is reg_mux:inst27|sr[4]~587 at LC2_H3
--operation mode is normal

M1L697 = M1L587 & (L31_q[4] # !H1_sour_reg[2]) # !M1L587 & (H1_sour_reg[2] & L5_q[4]);


--M1L787 is reg_mux:inst27|sr[4]~428 at LC1_H23
--operation mode is normal

M1L787 = H1_sour_reg[2] & (L6_q[4] # H1_sour_reg[3]) # !H1_sour_reg[2] & L2_q[4] & (!H1_sour_reg[3]);

--M1L797 is reg_mux:inst27|sr[4]~588 at LC1_H23
--operation mode is normal

M1L797 = H1_sour_reg[2] & (L6_q[4] # H1_sour_reg[3]) # !H1_sour_reg[2] & L2_q[4] & (!H1_sour_reg[3]);


--M1L887 is reg_mux:inst27|sr[4]~429 at LC3_H23
--operation mode is normal

M1L887 = M1L787 & (L41_q[4] # !H1_sour_reg[3]) # !M1L787 & (H1_sour_reg[3] & L01_q[4]);

--M1L897 is reg_mux:inst27|sr[4]~589 at LC3_H23
--operation mode is normal

M1L897 = M1L787 & (L41_q[4] # !H1_sour_reg[3]) # !M1L787 & (H1_sour_reg[3] & L01_q[4]);


--M1L987 is reg_mux:inst27|sr[4]~430 at LC6_H4
--operation mode is normal

M1L987 = H1_sour_reg[2] & (L4_q[4] # H1_sour_reg[3]) # !H1_sour_reg[2] & L61_q[4] & (!H1_sour_reg[3]);

--M1L997 is reg_mux:inst27|sr[4]~590 at LC6_H4
--operation mode is normal

M1L997 = H1_sour_reg[2] & (L4_q[4] # H1_sour_reg[3]) # !H1_sour_reg[2] & L61_q[4] & (!H1_sour_reg[3]);


--M1L097 is reg_mux:inst27|sr[4]~431 at LC4_H4
--operation mode is normal

M1L097 = M1L987 & (L21_q[4] # !H1_sour_reg[3]) # !M1L987 & (H1_sour_reg[3] & L8_q[4]);

--M1L008 is reg_mux:inst27|sr[4]~591 at LC4_H4
--operation mode is normal

M1L008 = M1L987 & (L21_q[4] # !H1_sour_reg[3]) # !M1L987 & (H1_sour_reg[3] & L8_q[4]);


--M1L197 is reg_mux:inst27|sr[4]~432 at LC4_H23
--operation mode is normal

M1L197 = H1_sour_reg[1] & (M1L887 # H1_sour_reg[0]) # !H1_sour_reg[1] & M1L097 & (!H1_sour_reg[0]);

--M1L108 is reg_mux:inst27|sr[4]~592 at LC4_H23
--operation mode is normal

M1L108 = H1_sour_reg[1] & (M1L887 # H1_sour_reg[0]) # !H1_sour_reg[1] & M1L097 & (!H1_sour_reg[0]);


--M1L297 is reg_mux:inst27|sr[4]~433 at LC7_H1
--operation mode is normal

M1L297 = H1_sour_reg[3] & (L11_q[4] # H1_sour_reg[2]) # !H1_sour_reg[3] & L3_q[4] & (!H1_sour_reg[2]);

--M1L208 is reg_mux:inst27|sr[4]~593 at LC7_H1
--operation mode is normal

M1L208 = H1_sour_reg[3] & (L11_q[4] # H1_sour_reg[2]) # !H1_sour_reg[3] & L3_q[4] & (!H1_sour_reg[2]);


--M1L397 is reg_mux:inst27|sr[4]~434 at LC5_H1
--operation mode is normal

M1L397 = M1L297 & (L51_q[4] # !H1_sour_reg[2]) # !M1L297 & (H1_sour_reg[2] & L7_q[4]);

--M1L308 is reg_mux:inst27|sr[4]~594 at LC5_H1
--operation mode is normal

M1L308 = M1L297 & (L51_q[4] # !H1_sour_reg[2]) # !M1L297 & (H1_sour_reg[2] & L7_q[4]);


--M1L497 is reg_mux:inst27|sr[4]~435 at LC6_H23
--operation mode is normal

M1L497 = M1L197 & (M1L397 # !H1_sour_reg[0]) # !M1L197 & (H1_sour_reg[0] & M1L687);

--M1L408 is reg_mux:inst27|sr[4]~595 at LC6_H23
--operation mode is normal

M1L408 = M1L197 & (M1L397 # !H1_sour_reg[0]) # !M1L197 & (H1_sour_reg[0] & M1L687);


--N1L731 is bus_mux:inst28|alu_sr[4]~646 at LC2_H23
--operation mode is normal

N1L731 = H1_offset[4] & (N1L021 # M1L497 & N1L161) # !H1_offset[4] & M1L497 & N1L161;

--N1L831 is bus_mux:inst28|alu_sr[4]~664 at LC2_H23
--operation mode is normal

N1L831 = H1_offset[4] & (N1L021 # M1L497 & N1L161) # !H1_offset[4] & M1L497 & N1L161;


--B1L93 is alu:inst|alu_out[4]~5816 at LC1_G25
--operation mode is normal

B1L93 = H1_alu_func[1] & (N1L04) # !H1_alu_func[1] & (N1L731 $ N1L23);

--B1L44 is alu:inst|alu_out[4]~5894 at LC1_G25
--operation mode is normal

B1L44 = H1_alu_func[1] & (N1L04) # !H1_alu_func[1] & (N1L731 $ N1L23);


--B1L04 is alu:inst|alu_out[4]~5817 at LC5_G25
--operation mode is normal

B1L04 = H1_alu_func[0] & !H1_alu_func[1] & N1L42 # !H1_alu_func[0] & (B1L93);

--B1L54 is alu:inst|alu_out[4]~5895 at LC5_G25
--operation mode is normal

B1L54 = H1_alu_func[0] & !H1_alu_func[1] & N1L42 # !H1_alu_func[0] & (B1L93);


--V9_cs_buffer[6] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC5_G11
--operation mode is arithmetic

V9_cs_buffer[6] = V6_cs_buffer[6] $ !V9_cout[5];

--V9L72 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~308 at LC5_G11
--operation mode is arithmetic

V9L72 = V6_cs_buffer[6] $ !V9_cout[5];

--V9_cout[6] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[6] at LC5_G11
--operation mode is arithmetic

V9_cout[6] = CARRY(V9_cout[5] # !V6_cs_buffer[6]);


--B1L762 is alu:inst|temp2~4 at LC2_G25
--operation mode is normal

B1L762 = N1L731 & N1L23;

--B1L392 is alu:inst|temp2~1522 at LC2_G25
--operation mode is normal

B1L392 = N1L731 & N1L23;


--V3_cs_buffer[5] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC2_G21
--operation mode is arithmetic

V3_cs_buffer[5] = N1L23 $ N1L731 $ V3_cout[4];

--V3L03 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~300 at LC2_G21
--operation mode is arithmetic

V3L03 = N1L23 $ N1L731 $ V3_cout[4];

--V3_cout[5] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] at LC2_G21
--operation mode is arithmetic

V3_cout[5] = CARRY(N1L23 & (N1L731 # V3_cout[4]) # !N1L23 & N1L731 & V3_cout[4]);


--B1L14 is alu:inst|alu_out[4]~5818 at LC3_G25
--operation mode is normal

B1L14 = H1_alu_func[1] & (B1L762 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[5] & (!H1_alu_func[0]);

--B1L64 is alu:inst|alu_out[4]~5896 at LC3_G25
--operation mode is normal

B1L64 = H1_alu_func[1] & (B1L762 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[5] & (!H1_alu_func[0]);


--B1L572 is alu:inst|temp2~20 at LC4_G25
--operation mode is normal

B1L572 = N1L731 # N1L23;

--B1L492 is alu:inst|temp2~1523 at LC4_G25
--operation mode is normal

B1L492 = N1L731 # N1L23;


--B1L24 is alu:inst|alu_out[4]~5819 at LC8_G25
--operation mode is normal

B1L24 = B1L14 & (B1L572 # !H1_alu_func[0]) # !B1L14 & (H1_alu_func[0] & !V9_cs_buffer[6]);

--B1L74 is alu:inst|alu_out[4]~5897 at LC8_G25
--operation mode is normal

B1L74 = B1L14 & (B1L572 # !H1_alu_func[0]) # !B1L14 & (H1_alu_func[0] & !V9_cs_buffer[6]);


--B1L34 is alu:inst|alu_out[4]~5820 at LC2_H44
--operation mode is normal

B1L34 = H1_alu_func[2] & (B1L04) # !H1_alu_func[2] & B1L24;

--B1L84 is alu:inst|alu_out[4]~5898 at LC2_H44
--operation mode is normal

B1L84 = H1_alu_func[2] & (B1L04) # !H1_alu_func[2] & B1L24;


--B1L752 is alu:inst|reduce_nor~163 at LC4_G36
--operation mode is normal

B1L752 = !B1L34 & !B1L36 & B1L652;

--B1L262 is alu:inst|reduce_nor~168 at LC4_G36
--operation mode is normal

B1L262 = !B1L34 & !B1L36 & B1L652;


--M1L588 is reg_mux:inst27|sr[9]~436 at LC6_H36
--operation mode is normal

M1L588 = H1_sour_reg[0] & (L5_q[9] # H1_sour_reg[1]) # !H1_sour_reg[0] & L4_q[9] & (!H1_sour_reg[1]);

--M1L598 is reg_mux:inst27|sr[9]~596 at LC6_H36
--operation mode is normal

M1L598 = H1_sour_reg[0] & (L5_q[9] # H1_sour_reg[1]) # !H1_sour_reg[0] & L4_q[9] & (!H1_sour_reg[1]);


--M1L688 is reg_mux:inst27|sr[9]~437 at LC5_H36
--operation mode is normal

M1L688 = M1L588 & (L7_q[9] # !H1_sour_reg[1]) # !M1L588 & (H1_sour_reg[1] & L6_q[9]);

--M1L698 is reg_mux:inst27|sr[9]~597 at LC5_H36
--operation mode is normal

M1L698 = M1L588 & (L7_q[9] # !H1_sour_reg[1]) # !M1L588 & (H1_sour_reg[1] & L6_q[9]);


--M1L788 is reg_mux:inst27|sr[9]~438 at LC4_H48
--operation mode is normal

M1L788 = H1_sour_reg[1] & (L01_q[9] # H1_sour_reg[0]) # !H1_sour_reg[1] & L8_q[9] & (!H1_sour_reg[0]);

--M1L798 is reg_mux:inst27|sr[9]~598 at LC4_H48
--operation mode is normal

M1L798 = H1_sour_reg[1] & (L01_q[9] # H1_sour_reg[0]) # !H1_sour_reg[1] & L8_q[9] & (!H1_sour_reg[0]);


--M1L888 is reg_mux:inst27|sr[9]~439 at LC6_H48
--operation mode is normal

M1L888 = M1L788 & (L11_q[9] # !H1_sour_reg[0]) # !M1L788 & (H1_sour_reg[0] & L9_q[9]);

--M1L898 is reg_mux:inst27|sr[9]~599 at LC6_H48
--operation mode is normal

M1L898 = M1L788 & (L11_q[9] # !H1_sour_reg[0]) # !M1L788 & (H1_sour_reg[0] & L9_q[9]);


--M1L988 is reg_mux:inst27|sr[9]~440 at LC7_H33
--operation mode is normal

M1L988 = H1_sour_reg[1] & (L2_q[9] # H1_sour_reg[0]) # !H1_sour_reg[1] & L61_q[9] & (!H1_sour_reg[0]);

--M1L998 is reg_mux:inst27|sr[9]~600 at LC7_H33
--operation mode is normal

M1L998 = H1_sour_reg[1] & (L2_q[9] # H1_sour_reg[0]) # !H1_sour_reg[1] & L61_q[9] & (!H1_sour_reg[0]);


--M1L098 is reg_mux:inst27|sr[9]~441 at LC6_H33
--operation mode is normal

M1L098 = M1L988 & (L3_q[9] # !H1_sour_reg[0]) # !M1L988 & (H1_sour_reg[0] & L1_q[9]);

--M1L009 is reg_mux:inst27|sr[9]~601 at LC6_H33
--operation mode is normal

M1L009 = M1L988 & (L3_q[9] # !H1_sour_reg[0]) # !M1L988 & (H1_sour_reg[0] & L1_q[9]);


--M1L198 is reg_mux:inst27|sr[9]~442 at LC2_H45
--operation mode is normal

M1L198 = H1_sour_reg[3] & (M1L888 # H1_sour_reg[2]) # !H1_sour_reg[3] & M1L098 & (!H1_sour_reg[2]);

--M1L109 is reg_mux:inst27|sr[9]~602 at LC2_H45
--operation mode is normal

M1L109 = H1_sour_reg[3] & (M1L888 # H1_sour_reg[2]) # !H1_sour_reg[3] & M1L098 & (!H1_sour_reg[2]);


--M1L298 is reg_mux:inst27|sr[9]~443 at LC6_H35
--operation mode is normal

M1L298 = H1_sour_reg[0] & (L31_q[9] # H1_sour_reg[1]) # !H1_sour_reg[0] & L21_q[9] & (!H1_sour_reg[1]);

--M1L209 is reg_mux:inst27|sr[9]~603 at LC6_H35
--operation mode is normal

M1L209 = H1_sour_reg[0] & (L31_q[9] # H1_sour_reg[1]) # !H1_sour_reg[0] & L21_q[9] & (!H1_sour_reg[1]);


--M1L398 is reg_mux:inst27|sr[9]~444 at LC5_H35
--operation mode is normal

M1L398 = M1L298 & (L51_q[9] # !H1_sour_reg[1]) # !M1L298 & (H1_sour_reg[1] & L41_q[9]);

--M1L309 is reg_mux:inst27|sr[9]~604 at LC5_H35
--operation mode is normal

M1L309 = M1L298 & (L51_q[9] # !H1_sour_reg[1]) # !M1L298 & (H1_sour_reg[1] & L41_q[9]);


--M1L498 is reg_mux:inst27|sr[9]~445 at LC3_H45
--operation mode is normal

M1L498 = M1L198 & (M1L398 # !H1_sour_reg[2]) # !M1L198 & (H1_sour_reg[2] & M1L688);

--M1L409 is reg_mux:inst27|sr[9]~605 at LC3_H45
--operation mode is normal

M1L409 = M1L198 & (M1L398 # !H1_sour_reg[2]) # !M1L198 & (H1_sour_reg[2] & M1L688);


--N1L741 is bus_mux:inst28|alu_sr[9]~647 at LC1_H45
--operation mode is normal

N1L741 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L498;

--N1L841 is bus_mux:inst28|alu_sr[9]~665 at LC1_H45
--operation mode is normal

N1L841 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L498;


--V9_cs_buffer[11] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC2_G13
--operation mode is arithmetic

V9_cs_buffer[11] = V6_cs_buffer[11] $ !V9_cout[10];

--V9L73 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~309 at LC2_G13
--operation mode is arithmetic

V9L73 = V6_cs_buffer[11] $ !V9_cout[10];

--V9_cout[11] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[11] at LC2_G13
--operation mode is arithmetic

V9_cout[11] = CARRY(V9_cout[10] # !V6_cs_buffer[11]);


--V3_cs_buffer[10] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC7_G21
--operation mode is arithmetic

V3_cs_buffer[10] = N1L27 $ N1L741 $ V3_cout[9];

--V3L04 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~301 at LC7_G21
--operation mode is arithmetic

V3L04 = N1L27 $ N1L741 $ V3_cout[9];

--V3_cout[10] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[10] at LC7_G21
--operation mode is arithmetic

V3_cout[10] = CARRY(N1L27 & (N1L741 # V3_cout[9]) # !N1L27 & N1L741 & V3_cout[9]);


--B1L98 is alu:inst|alu_out[9]~5821 at LC3_G34
--operation mode is normal

B1L98 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[11]) # !H1_alu_func[0] & V3_cs_buffer[10] & (!H1_alu_func[1]);

--B1L49 is alu:inst|alu_out[9]~5899 at LC3_G34
--operation mode is normal

B1L49 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[11]) # !H1_alu_func[0] & V3_cs_buffer[10] & (!H1_alu_func[1]);


--B1L09 is alu:inst|alu_out[9]~5822 at LC5_G34
--operation mode is normal

B1L09 = H1_alu_func[1] & (B1L98 & (N1L27 # N1L741) # !B1L98 & N1L27 & N1L741) # !H1_alu_func[1] & B1L98;

--B1L59 is alu:inst|alu_out[9]~5900 at LC5_G34
--operation mode is normal

B1L59 = H1_alu_func[1] & (B1L98 & (N1L27 # N1L741) # !B1L98 & N1L27 & N1L741) # !H1_alu_func[1] & B1L98;


--B1L19 is alu:inst|alu_out[9]~5823 at LC6_G34
--operation mode is normal

B1L19 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L741 $ N1L27);

--B1L69 is alu:inst|alu_out[9]~5901 at LC6_G34
--operation mode is normal

B1L69 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L741 $ N1L27);


--B1L29 is alu:inst|alu_out[9]~5824 at LC7_G34
--operation mode is normal

B1L29 = H1_alu_func[0] & !H1_alu_func[1] & (N1L46) # !H1_alu_func[0] & H1_alu_func[1] & N1L08;

--B1L79 is alu:inst|alu_out[9]~5902 at LC7_G34
--operation mode is normal

B1L79 = H1_alu_func[0] & !H1_alu_func[1] & (N1L46) # !H1_alu_func[0] & H1_alu_func[1] & N1L08;


--B1L39 is alu:inst|alu_out[9]~5825 at LC4_G34
--operation mode is normal

B1L39 = H1_alu_func[2] & (B1L29 # B1L19) # !H1_alu_func[2] & (B1L09);

--B1L89 is alu:inst|alu_out[9]~5903 at LC4_G34
--operation mode is normal

B1L89 = H1_alu_func[2] & (B1L29 # B1L19) # !H1_alu_func[2] & (B1L09);


--M1L548 is reg_mux:inst27|sr[7]~446 at LC7_I14
--operation mode is normal

M1L548 = H1_sour_reg[0] & (L9_q[7] # H1_sour_reg[1]) # !H1_sour_reg[0] & L8_q[7] & (!H1_sour_reg[1]);

--M1L558 is reg_mux:inst27|sr[7]~606 at LC7_I14
--operation mode is normal

M1L558 = H1_sour_reg[0] & (L9_q[7] # H1_sour_reg[1]) # !H1_sour_reg[0] & L8_q[7] & (!H1_sour_reg[1]);


--M1L648 is reg_mux:inst27|sr[7]~447 at LC1_I14
--operation mode is normal

M1L648 = M1L548 & (L11_q[7] # !H1_sour_reg[1]) # !M1L548 & (H1_sour_reg[1] & L01_q[7]);

--M1L658 is reg_mux:inst27|sr[7]~607 at LC1_I14
--operation mode is normal

M1L658 = M1L548 & (L11_q[7] # !H1_sour_reg[1]) # !M1L548 & (H1_sour_reg[1] & L01_q[7]);


--M1L748 is reg_mux:inst27|sr[7]~448 at LC1_I16
--operation mode is normal

M1L748 = H1_sour_reg[1] & (L6_q[7] # H1_sour_reg[0]) # !H1_sour_reg[1] & L4_q[7] & (!H1_sour_reg[0]);

--M1L758 is reg_mux:inst27|sr[7]~608 at LC1_I16
--operation mode is normal

M1L758 = H1_sour_reg[1] & (L6_q[7] # H1_sour_reg[0]) # !H1_sour_reg[1] & L4_q[7] & (!H1_sour_reg[0]);


--M1L848 is reg_mux:inst27|sr[7]~449 at LC6_I16
--operation mode is normal

M1L848 = M1L748 & (L7_q[7] # !H1_sour_reg[0]) # !M1L748 & (H1_sour_reg[0] & L5_q[7]);

--M1L858 is reg_mux:inst27|sr[7]~609 at LC6_I16
--operation mode is normal

M1L858 = M1L748 & (L7_q[7] # !H1_sour_reg[0]) # !M1L748 & (H1_sour_reg[0] & L5_q[7]);


--M1L948 is reg_mux:inst27|sr[7]~450 at LC6_I10
--operation mode is normal

M1L948 = H1_sour_reg[0] & (L1_q[7] # H1_sour_reg[1]) # !H1_sour_reg[0] & L61_q[7] & (!H1_sour_reg[1]);

--M1L958 is reg_mux:inst27|sr[7]~610 at LC6_I10
--operation mode is normal

M1L958 = H1_sour_reg[0] & (L1_q[7] # H1_sour_reg[1]) # !H1_sour_reg[0] & L61_q[7] & (!H1_sour_reg[1]);


--M1L058 is reg_mux:inst27|sr[7]~451 at LC7_I10
--operation mode is normal

M1L058 = M1L948 & (L3_q[7] # !H1_sour_reg[1]) # !M1L948 & (H1_sour_reg[1] & L2_q[7]);

--M1L068 is reg_mux:inst27|sr[7]~611 at LC7_I10
--operation mode is normal

M1L068 = M1L948 & (L3_q[7] # !H1_sour_reg[1]) # !M1L948 & (H1_sour_reg[1] & L2_q[7]);


--M1L158 is reg_mux:inst27|sr[7]~452 at LC4_I10
--operation mode is normal

M1L158 = H1_sour_reg[2] & (M1L848 # H1_sour_reg[3]) # !H1_sour_reg[2] & M1L058 & (!H1_sour_reg[3]);

--M1L168 is reg_mux:inst27|sr[7]~612 at LC4_I10
--operation mode is normal

M1L168 = H1_sour_reg[2] & (M1L848 # H1_sour_reg[3]) # !H1_sour_reg[2] & M1L058 & (!H1_sour_reg[3]);


--M1L258 is reg_mux:inst27|sr[7]~453 at LC7_I17
--operation mode is normal

M1L258 = H1_sour_reg[1] & (L41_q[7] # H1_sour_reg[0]) # !H1_sour_reg[1] & L21_q[7] & (!H1_sour_reg[0]);

--M1L268 is reg_mux:inst27|sr[7]~613 at LC7_I17
--operation mode is normal

M1L268 = H1_sour_reg[1] & (L41_q[7] # H1_sour_reg[0]) # !H1_sour_reg[1] & L21_q[7] & (!H1_sour_reg[0]);


--M1L358 is reg_mux:inst27|sr[7]~454 at LC2_I17
--operation mode is normal

M1L358 = M1L258 & (L51_q[7] # !H1_sour_reg[0]) # !M1L258 & (H1_sour_reg[0] & L31_q[7]);

--M1L368 is reg_mux:inst27|sr[7]~614 at LC2_I17
--operation mode is normal

M1L368 = M1L258 & (L51_q[7] # !H1_sour_reg[0]) # !M1L258 & (H1_sour_reg[0] & L31_q[7]);


--M1L458 is reg_mux:inst27|sr[7]~455 at LC2_G16
--operation mode is normal

M1L458 = M1L158 & (M1L358 # !H1_sour_reg[3]) # !M1L158 & (H1_sour_reg[3] & M1L648);

--M1L468 is reg_mux:inst27|sr[7]~615 at LC2_G16
--operation mode is normal

M1L468 = M1L158 & (M1L358 # !H1_sour_reg[3]) # !M1L158 & (H1_sour_reg[3] & M1L648);


--N1L341 is bus_mux:inst28|alu_sr[7]~648 at LC4_G16
--operation mode is normal

N1L341 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L458;

--N1L441 is bus_mux:inst28|alu_sr[7]~666 at LC4_G16
--operation mode is normal

N1L441 = N1L951 # !H1_alu_in_sel[1] & !H1_alu_in_sel[2] & M1L458;


--V9_cs_buffer[9] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC8_G11
--operation mode is arithmetic

V9_cs_buffer[9] = V6_cs_buffer[9] $ !V9_cout[8];

--V9L33 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~310 at LC8_G11
--operation mode is arithmetic

V9L33 = V6_cs_buffer[9] $ !V9_cout[8];

--V9_cout[9] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[9] at LC8_G11
--operation mode is arithmetic

V9_cout[9] = CARRY(V9_cout[8] # !V6_cs_buffer[9]);


--V3_cs_buffer[8] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC5_G21
--operation mode is arithmetic

V3_cs_buffer[8] = N1L65 $ N1L341 $ V3_cout[7];

--V3L63 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~302 at LC5_G21
--operation mode is arithmetic

V3L63 = N1L65 $ N1L341 $ V3_cout[7];

--V3_cout[8] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[8] at LC5_G21
--operation mode is arithmetic

V3_cout[8] = CARRY(N1L65 & (N1L341 # V3_cout[7]) # !N1L65 & N1L341 & V3_cout[7]);


--B1L96 is alu:inst|alu_out[7]~5826 at LC2_G39
--operation mode is normal

B1L96 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[9]) # !H1_alu_func[0] & V3_cs_buffer[8] & (!H1_alu_func[1]);

--B1L47 is alu:inst|alu_out[7]~5904 at LC2_G39
--operation mode is normal

B1L47 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[9]) # !H1_alu_func[0] & V3_cs_buffer[8] & (!H1_alu_func[1]);


--B1L07 is alu:inst|alu_out[7]~5827 at LC6_G39
--operation mode is normal

B1L07 = H1_alu_func[1] & (B1L96 & (N1L65 # N1L341) # !B1L96 & N1L65 & N1L341) # !H1_alu_func[1] & B1L96;

--B1L57 is alu:inst|alu_out[7]~5905 at LC6_G39
--operation mode is normal

B1L57 = H1_alu_func[1] & (B1L96 & (N1L65 # N1L341) # !B1L96 & N1L65 & N1L341) # !H1_alu_func[1] & B1L96;


--B1L17 is alu:inst|alu_out[7]~5828 at LC7_G39
--operation mode is normal

B1L17 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L341 $ N1L65);

--B1L67 is alu:inst|alu_out[7]~5906 at LC7_G39
--operation mode is normal

B1L67 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L341 $ N1L65);


--B1L27 is alu:inst|alu_out[7]~5829 at LC8_G39
--operation mode is normal

B1L27 = H1_alu_func[0] & !H1_alu_func[1] & (N1L84) # !H1_alu_func[0] & H1_alu_func[1] & N1L46;

--B1L77 is alu:inst|alu_out[7]~5907 at LC8_G39
--operation mode is normal

B1L77 = H1_alu_func[0] & !H1_alu_func[1] & (N1L84) # !H1_alu_func[0] & H1_alu_func[1] & N1L46;


--B1L37 is alu:inst|alu_out[7]~5830 at LC4_G39
--operation mode is normal

B1L37 = H1_alu_func[2] & (B1L27 # B1L17) # !H1_alu_func[2] & (B1L07);

--B1L87 is alu:inst|alu_out[7]~5908 at LC4_G39
--operation mode is normal

B1L87 = H1_alu_func[2] & (B1L27 # B1L17) # !H1_alu_func[2] & (B1L07);


--M1L508 is reg_mux:inst27|sr[5]~456 at LC5_G5
--operation mode is normal

M1L508 = H1_sour_reg[0] & (L5_q[5] # H1_sour_reg[1]) # !H1_sour_reg[0] & L4_q[5] & (!H1_sour_reg[1]);

--M1L518 is reg_mux:inst27|sr[5]~616 at LC5_G5
--operation mode is normal

M1L518 = H1_sour_reg[0] & (L5_q[5] # H1_sour_reg[1]) # !H1_sour_reg[0] & L4_q[5] & (!H1_sour_reg[1]);


--M1L608 is reg_mux:inst27|sr[5]~457 at LC4_G5
--operation mode is normal

M1L608 = M1L508 & (L7_q[5] # !H1_sour_reg[1]) # !M1L508 & (H1_sour_reg[1] & L6_q[5]);

--M1L618 is reg_mux:inst27|sr[5]~617 at LC4_G5
--operation mode is normal

M1L618 = M1L508 & (L7_q[5] # !H1_sour_reg[1]) # !M1L508 & (H1_sour_reg[1] & L6_q[5]);


--M1L708 is reg_mux:inst27|sr[5]~458 at LC1_G22
--operation mode is normal

M1L708 = H1_sour_reg[1] & (L01_q[5] # H1_sour_reg[0]) # !H1_sour_reg[1] & L8_q[5] & (!H1_sour_reg[0]);

--M1L718 is reg_mux:inst27|sr[5]~618 at LC1_G22
--operation mode is normal

M1L718 = H1_sour_reg[1] & (L01_q[5] # H1_sour_reg[0]) # !H1_sour_reg[1] & L8_q[5] & (!H1_sour_reg[0]);


--M1L808 is reg_mux:inst27|sr[5]~459 at LC3_G22
--operation mode is normal

M1L808 = M1L708 & (L11_q[5] # !H1_sour_reg[0]) # !M1L708 & (H1_sour_reg[0] & L9_q[5]);

--M1L818 is reg_mux:inst27|sr[5]~619 at LC3_G22
--operation mode is normal

M1L818 = M1L708 & (L11_q[5] # !H1_sour_reg[0]) # !M1L708 & (H1_sour_reg[0] & L9_q[5]);


--M1L908 is reg_mux:inst27|sr[5]~460 at LC4_G9
--operation mode is normal

M1L908 = H1_sour_reg[1] & (L2_q[5] # H1_sour_reg[0]) # !H1_sour_reg[1] & L61_q[5] & (!H1_sour_reg[0]);

--M1L918 is reg_mux:inst27|sr[5]~620 at LC4_G9
--operation mode is normal

M1L918 = H1_sour_reg[1] & (L2_q[5] # H1_sour_reg[0]) # !H1_sour_reg[1] & L61_q[5] & (!H1_sour_reg[0]);


--M1L018 is reg_mux:inst27|sr[5]~461 at LC5_G9
--operation mode is normal

M1L018 = M1L908 & (L3_q[5] # !H1_sour_reg[0]) # !M1L908 & (H1_sour_reg[0] & L1_q[5]);

--M1L028 is reg_mux:inst27|sr[5]~621 at LC5_G9
--operation mode is normal

M1L028 = M1L908 & (L3_q[5] # !H1_sour_reg[0]) # !M1L908 & (H1_sour_reg[0] & L1_q[5]);


--M1L118 is reg_mux:inst27|sr[5]~462 at LC6_G9
--operation mode is normal

M1L118 = H1_sour_reg[3] & (M1L808 # H1_sour_reg[2]) # !H1_sour_reg[3] & M1L018 & (!H1_sour_reg[2]);

--M1L128 is reg_mux:inst27|sr[5]~622 at LC6_G9
--operation mode is normal

M1L128 = H1_sour_reg[3] & (M1L808 # H1_sour_reg[2]) # !H1_sour_reg[3] & M1L018 & (!H1_sour_reg[2]);


--M1L218 is reg_mux:inst27|sr[5]~463 at LC5_G4
--operation mode is normal

M1L218 = H1_sour_reg[0] & (L31_q[5] # H1_sour_reg[1]) # !H1_sour_reg[0] & L21_q[5] & (!H1_sour_reg[1]);

--M1L228 is reg_mux:inst27|sr[5]~623 at LC5_G4
--operation mode is normal

M1L228 = H1_sour_reg[0] & (L31_q[5] # H1_sour_reg[1]) # !H1_sour_reg[0] & L21_q[5] & (!H1_sour_reg[1]);


--M1L318 is reg_mux:inst27|sr[5]~464 at LC4_G4
--operation mode is normal

M1L318 = M1L218 & (L51_q[5] # !H1_sour_reg[1]) # !M1L218 & (H1_sour_reg[1] & L41_q[5]);

--M1L328 is reg_mux:inst27|sr[5]~624 at LC4_G4
--operation mode is normal

M1L328 = M1L218 & (L51_q[5] # !H1_sour_reg[1]) # !M1L218 & (H1_sour_reg[1] & L41_q[5]);


--M1L418 is reg_mux:inst27|sr[5]~465 at LC4_G8
--operation mode is normal

M1L418 = M1L118 & (M1L318 # !H1_sour_reg[2]) # !M1L118 & (H1_sour_reg[2] & M1L608);

--M1L428 is reg_mux:inst27|sr[5]~625 at LC4_G8
--operation mode is normal

M1L428 = M1L118 & (M1L318 # !H1_sour_reg[2]) # !M1L118 & (H1_sour_reg[2] & M1L608);


--N1L931 is bus_mux:inst28|alu_sr[5]~649 at LC8_G8
--operation mode is normal

N1L931 = H1_offset[5] & (N1L021 # M1L418 & N1L161) # !H1_offset[5] & M1L418 & N1L161;

--N1L041 is bus_mux:inst28|alu_sr[5]~667 at LC8_G8
--operation mode is normal

N1L041 = H1_offset[5] & (N1L021 # M1L418 & N1L161) # !H1_offset[5] & M1L418 & N1L161;


--V9_cs_buffer[7] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC6_G11
--operation mode is arithmetic

V9_cs_buffer[7] = V6_cs_buffer[7] $ !V9_cout[6];

--V9L92 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~311 at LC6_G11
--operation mode is arithmetic

V9L92 = V6_cs_buffer[7] $ !V9_cout[6];

--V9_cout[7] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[7] at LC6_G11
--operation mode is arithmetic

V9_cout[7] = CARRY(V9_cout[6] # !V6_cs_buffer[7]);


--V3_cs_buffer[6] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC3_G21
--operation mode is arithmetic

V3_cs_buffer[6] = N1L04 $ N1L931 $ V3_cout[5];

--V3L23 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~303 at LC3_G21
--operation mode is arithmetic

V3L23 = N1L04 $ N1L931 $ V3_cout[5];

--V3_cout[6] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] at LC3_G21
--operation mode is arithmetic

V3_cout[6] = CARRY(N1L04 & (N1L931 # V3_cout[5]) # !N1L04 & N1L931 & V3_cout[5]);


--B1L94 is alu:inst|alu_out[5]~5831 at LC2_G41
--operation mode is normal

B1L94 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[7]) # !H1_alu_func[0] & V3_cs_buffer[6] & (!H1_alu_func[1]);

--B1L45 is alu:inst|alu_out[5]~5909 at LC2_G41
--operation mode is normal

B1L45 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[7]) # !H1_alu_func[0] & V3_cs_buffer[6] & (!H1_alu_func[1]);


--B1L05 is alu:inst|alu_out[5]~5832 at LC6_G41
--operation mode is normal

B1L05 = H1_alu_func[1] & (B1L94 & (N1L04 # N1L931) # !B1L94 & N1L04 & N1L931) # !H1_alu_func[1] & B1L94;

--B1L55 is alu:inst|alu_out[5]~5910 at LC6_G41
--operation mode is normal

B1L55 = H1_alu_func[1] & (B1L94 & (N1L04 # N1L931) # !B1L94 & N1L04 & N1L931) # !H1_alu_func[1] & B1L94;


--B1L15 is alu:inst|alu_out[5]~5833 at LC7_G41
--operation mode is normal

B1L15 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L931 $ N1L04);

--B1L65 is alu:inst|alu_out[5]~5911 at LC7_G41
--operation mode is normal

B1L65 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L931 $ N1L04);


--B1L25 is alu:inst|alu_out[5]~5834 at LC3_G39
--operation mode is normal

B1L25 = H1_alu_func[0] & !H1_alu_func[1] & (N1L23) # !H1_alu_func[0] & H1_alu_func[1] & N1L84;

--B1L75 is alu:inst|alu_out[5]~5912 at LC3_G39
--operation mode is normal

B1L75 = H1_alu_func[0] & !H1_alu_func[1] & (N1L23) # !H1_alu_func[0] & H1_alu_func[1] & N1L84;


--B1L35 is alu:inst|alu_out[5]~5835 at LC1_G41
--operation mode is normal

B1L35 = H1_alu_func[2] & (B1L25 # B1L15) # !H1_alu_func[2] & (B1L05);

--B1L85 is alu:inst|alu_out[5]~5913 at LC1_G41
--operation mode is normal

B1L85 = H1_alu_func[2] & (B1L25 # B1L15) # !H1_alu_func[2] & (B1L05);


--M1L567 is reg_mux:inst27|sr[3]~466 at LC7_K13
--operation mode is normal

M1L567 = H1_sour_reg[0] & (L9_q[3] # H1_sour_reg[1]) # !H1_sour_reg[0] & L8_q[3] & (!H1_sour_reg[1]);

--M1L577 is reg_mux:inst27|sr[3]~626 at LC7_K13
--operation mode is normal

M1L577 = H1_sour_reg[0] & (L9_q[3] # H1_sour_reg[1]) # !H1_sour_reg[0] & L8_q[3] & (!H1_sour_reg[1]);


--M1L667 is reg_mux:inst27|sr[3]~467 at LC1_K13
--operation mode is normal

M1L667 = M1L567 & (L11_q[3] # !H1_sour_reg[1]) # !M1L567 & (H1_sour_reg[1] & L01_q[3]);

--M1L677 is reg_mux:inst27|sr[3]~627 at LC1_K13
--operation mode is normal

M1L677 = M1L567 & (L11_q[3] # !H1_sour_reg[1]) # !M1L567 & (H1_sour_reg[1] & L01_q[3]);


--M1L767 is reg_mux:inst27|sr[3]~468 at LC5_K18
--operation mode is normal

M1L767 = H1_sour_reg[1] & (L6_q[3] # H1_sour_reg[0]) # !H1_sour_reg[1] & L4_q[3] & (!H1_sour_reg[0]);

--M1L777 is reg_mux:inst27|sr[3]~628 at LC5_K18
--operation mode is normal

M1L777 = H1_sour_reg[1] & (L6_q[3] # H1_sour_reg[0]) # !H1_sour_reg[1] & L4_q[3] & (!H1_sour_reg[0]);


--M1L867 is reg_mux:inst27|sr[3]~469 at LC6_K18
--operation mode is normal

M1L867 = M1L767 & (L7_q[3] # !H1_sour_reg[0]) # !M1L767 & (H1_sour_reg[0] & L5_q[3]);

--M1L877 is reg_mux:inst27|sr[3]~629 at LC6_K18
--operation mode is normal

M1L877 = M1L767 & (L7_q[3] # !H1_sour_reg[0]) # !M1L767 & (H1_sour_reg[0] & L5_q[3]);


--M1L967 is reg_mux:inst27|sr[3]~470 at LC2_K14
--operation mode is normal

M1L967 = H1_sour_reg[0] & (L1_q[3] # H1_sour_reg[1]) # !H1_sour_reg[0] & L61_q[3] & (!H1_sour_reg[1]);

--M1L977 is reg_mux:inst27|sr[3]~630 at LC2_K14
--operation mode is normal

M1L977 = H1_sour_reg[0] & (L1_q[3] # H1_sour_reg[1]) # !H1_sour_reg[0] & L61_q[3] & (!H1_sour_reg[1]);


--M1L077 is reg_mux:inst27|sr[3]~471 at LC3_K14
--operation mode is normal

M1L077 = M1L967 & (L3_q[3] # !H1_sour_reg[1]) # !M1L967 & (H1_sour_reg[1] & L2_q[3]);

--M1L087 is reg_mux:inst27|sr[3]~631 at LC3_K14
--operation mode is normal

M1L087 = M1L967 & (L3_q[3] # !H1_sour_reg[1]) # !M1L967 & (H1_sour_reg[1] & L2_q[3]);


--M1L177 is reg_mux:inst27|sr[3]~472 at LC4_K14
--operation mode is normal

M1L177 = H1_sour_reg[2] & (M1L867 # H1_sour_reg[3]) # !H1_sour_reg[2] & M1L077 & (!H1_sour_reg[3]);

--M1L187 is reg_mux:inst27|sr[3]~632 at LC4_K14
--operation mode is normal

M1L187 = H1_sour_reg[2] & (M1L867 # H1_sour_reg[3]) # !H1_sour_reg[2] & M1L077 & (!H1_sour_reg[3]);


--M1L277 is reg_mux:inst27|sr[3]~473 at LC7_K12
--operation mode is normal

M1L277 = H1_sour_reg[1] & (L41_q[3] # H1_sour_reg[0]) # !H1_sour_reg[1] & L21_q[3] & (!H1_sour_reg[0]);

--M1L287 is reg_mux:inst27|sr[3]~633 at LC7_K12
--operation mode is normal

M1L287 = H1_sour_reg[1] & (L41_q[3] # H1_sour_reg[0]) # !H1_sour_reg[1] & L21_q[3] & (!H1_sour_reg[0]);


--M1L377 is reg_mux:inst27|sr[3]~474 at LC2_K12
--operation mode is normal

M1L377 = M1L277 & (L51_q[3] # !H1_sour_reg[0]) # !M1L277 & (H1_sour_reg[0] & L31_q[3]);

--M1L387 is reg_mux:inst27|sr[3]~634 at LC2_K12
--operation mode is normal

M1L387 = M1L277 & (L51_q[3] # !H1_sour_reg[0]) # !M1L277 & (H1_sour_reg[0] & L31_q[3]);


--M1L477 is reg_mux:inst27|sr[3]~475 at LC6_K14
--operation mode is normal

M1L477 = M1L177 & (M1L377 # !H1_sour_reg[3]) # !M1L177 & (H1_sour_reg[3] & M1L667);

--M1L487 is reg_mux:inst27|sr[3]~635 at LC6_K14
--operation mode is normal

M1L487 = M1L177 & (M1L377 # !H1_sour_reg[3]) # !M1L177 & (H1_sour_reg[3] & M1L667);


--N1L531 is bus_mux:inst28|alu_sr[3]~650 at LC8_K14
--operation mode is normal

N1L531 = H1_offset[3] & (N1L021 # M1L477 & N1L161) # !H1_offset[3] & M1L477 & N1L161;

--N1L631 is bus_mux:inst28|alu_sr[3]~668 at LC8_K14
--operation mode is normal

N1L631 = H1_offset[3] & (N1L021 # M1L477 & N1L161) # !H1_offset[3] & M1L477 & N1L161;


--V9_cs_buffer[5] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC4_G11
--operation mode is arithmetic

V9_cs_buffer[5] = V6_cs_buffer[5] $ !V9_cout[4];

--V9L52 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~312 at LC4_G11
--operation mode is arithmetic

V9L52 = V6_cs_buffer[5] $ !V9_cout[4];

--V9_cout[5] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5] at LC4_G11
--operation mode is arithmetic

V9_cout[5] = CARRY(V9_cout[4] # !V6_cs_buffer[5]);


--V3_cs_buffer[4] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC1_G21
--operation mode is arithmetic

V3_cs_buffer[4] = N1L42 $ N1L531 $ V3_cout[3];

--V3L82 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~304 at LC1_G21
--operation mode is arithmetic

V3L82 = N1L42 $ N1L531 $ V3_cout[3];

--V3_cout[4] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] at LC1_G21
--operation mode is arithmetic

V3_cout[4] = CARRY(N1L42 & (N1L531 # V3_cout[3]) # !N1L42 & N1L531 & V3_cout[3]);


--B1L92 is alu:inst|alu_out[3]~5836 at LC1_K45
--operation mode is normal

B1L92 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[5]) # !H1_alu_func[0] & V3_cs_buffer[4] & (!H1_alu_func[1]);

--B1L43 is alu:inst|alu_out[3]~5914 at LC1_K45
--operation mode is normal

B1L43 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[5]) # !H1_alu_func[0] & V3_cs_buffer[4] & (!H1_alu_func[1]);


--B1L03 is alu:inst|alu_out[3]~5837 at LC2_K45
--operation mode is normal

B1L03 = H1_alu_func[1] & (B1L92 & (N1L42 # N1L531) # !B1L92 & N1L42 & N1L531) # !H1_alu_func[1] & B1L92;

--B1L53 is alu:inst|alu_out[3]~5915 at LC2_K45
--operation mode is normal

B1L53 = H1_alu_func[1] & (B1L92 & (N1L42 # N1L531) # !B1L92 & N1L42 & N1L531) # !H1_alu_func[1] & B1L92;


--B1L13 is alu:inst|alu_out[3]~5838 at LC3_K45
--operation mode is normal

B1L13 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L531 $ N1L42);

--B1L63 is alu:inst|alu_out[3]~5916 at LC3_K45
--operation mode is normal

B1L63 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L531 $ N1L42);


--B1L23 is alu:inst|alu_out[3]~5839 at LC5_K45
--operation mode is normal

B1L23 = H1_alu_func[0] & !H1_alu_func[1] & (N1L61) # !H1_alu_func[0] & H1_alu_func[1] & N1L23;

--B1L73 is alu:inst|alu_out[3]~5917 at LC5_K45
--operation mode is normal

B1L73 = H1_alu_func[0] & !H1_alu_func[1] & (N1L61) # !H1_alu_func[0] & H1_alu_func[1] & N1L23;


--B1L33 is alu:inst|alu_out[3]~5840 at LC4_K45
--operation mode is normal

B1L33 = H1_alu_func[2] & (B1L23 # B1L13) # !H1_alu_func[2] & (B1L03);

--B1L83 is alu:inst|alu_out[3]~5918 at LC4_K45
--operation mode is normal

B1L83 = H1_alu_func[2] & (B1L23 # B1L13) # !H1_alu_func[2] & (B1L03);


--B1L852 is alu:inst|reduce_nor~164 at LC5_G36
--operation mode is normal

B1L852 = !B1L33 & !B1L35 & !B1L37 & !B1L39;

--B1L362 is alu:inst|reduce_nor~169 at LC5_G36
--operation mode is normal

B1L362 = !B1L33 & !B1L35 & !B1L37 & !B1L39;


--M1L527 is reg_mux:inst27|sr[1]~476 at LC5_H9
--operation mode is normal

M1L527 = H1_sour_reg[0] & (L5_q[1] # H1_sour_reg[1]) # !H1_sour_reg[0] & L4_q[1] & (!H1_sour_reg[1]);

--M1L537 is reg_mux:inst27|sr[1]~636 at LC5_H9
--operation mode is normal

M1L537 = H1_sour_reg[0] & (L5_q[1] # H1_sour_reg[1]) # !H1_sour_reg[0] & L4_q[1] & (!H1_sour_reg[1]);


--M1L627 is reg_mux:inst27|sr[1]~477 at LC8_H9
--operation mode is normal

M1L627 = M1L527 & (L7_q[1] # !H1_sour_reg[1]) # !M1L527 & (H1_sour_reg[1] & L6_q[1]);

--M1L637 is reg_mux:inst27|sr[1]~637 at LC8_H9
--operation mode is normal

M1L637 = M1L527 & (L7_q[1] # !H1_sour_reg[1]) # !M1L527 & (H1_sour_reg[1] & L6_q[1]);


--M1L727 is reg_mux:inst27|sr[1]~478 at LC1_H2
--operation mode is normal

M1L727 = H1_sour_reg[1] & (L01_q[1] # H1_sour_reg[0]) # !H1_sour_reg[1] & L8_q[1] & (!H1_sour_reg[0]);

--M1L737 is reg_mux:inst27|sr[1]~638 at LC1_H2
--operation mode is normal

M1L737 = H1_sour_reg[1] & (L01_q[1] # H1_sour_reg[0]) # !H1_sour_reg[1] & L8_q[1] & (!H1_sour_reg[0]);


--M1L827 is reg_mux:inst27|sr[1]~479 at LC2_H2
--operation mode is normal

M1L827 = M1L727 & (L11_q[1] # !H1_sour_reg[0]) # !M1L727 & (H1_sour_reg[0] & L9_q[1]);

--M1L837 is reg_mux:inst27|sr[1]~639 at LC2_H2
--operation mode is normal

M1L837 = M1L727 & (L11_q[1] # !H1_sour_reg[0]) # !M1L727 & (H1_sour_reg[0] & L9_q[1]);


--M1L927 is reg_mux:inst27|sr[1]~480 at LC5_H10
--operation mode is normal

M1L927 = H1_sour_reg[1] & (L2_q[1] # H1_sour_reg[0]) # !H1_sour_reg[1] & L61_q[1] & (!H1_sour_reg[0]);

--M1L937 is reg_mux:inst27|sr[1]~640 at LC5_H10
--operation mode is normal

M1L937 = H1_sour_reg[1] & (L2_q[1] # H1_sour_reg[0]) # !H1_sour_reg[1] & L61_q[1] & (!H1_sour_reg[0]);


--M1L037 is reg_mux:inst27|sr[1]~481 at LC8_H10
--operation mode is normal

M1L037 = M1L927 & (L3_q[1] # !H1_sour_reg[0]) # !M1L927 & (H1_sour_reg[0] & L1_q[1]);

--M1L047 is reg_mux:inst27|sr[1]~641 at LC8_H10
--operation mode is normal

M1L047 = M1L927 & (L3_q[1] # !H1_sour_reg[0]) # !M1L927 & (H1_sour_reg[0] & L1_q[1]);


--M1L137 is reg_mux:inst27|sr[1]~482 at LC7_H2
--operation mode is normal

M1L137 = H1_sour_reg[3] & (M1L827 # H1_sour_reg[2]) # !H1_sour_reg[3] & M1L037 & (!H1_sour_reg[2]);

--M1L147 is reg_mux:inst27|sr[1]~642 at LC7_H2
--operation mode is normal

M1L147 = H1_sour_reg[3] & (M1L827 # H1_sour_reg[2]) # !H1_sour_reg[3] & M1L037 & (!H1_sour_reg[2]);


--M1L237 is reg_mux:inst27|sr[1]~483 at LC7_H7
--operation mode is normal

M1L237 = H1_sour_reg[0] & (L31_q[1] # H1_sour_reg[1]) # !H1_sour_reg[0] & L21_q[1] & (!H1_sour_reg[1]);

--M1L247 is reg_mux:inst27|sr[1]~643 at LC7_H7
--operation mode is normal

M1L247 = H1_sour_reg[0] & (L31_q[1] # H1_sour_reg[1]) # !H1_sour_reg[0] & L21_q[1] & (!H1_sour_reg[1]);


--M1L337 is reg_mux:inst27|sr[1]~484 at LC5_H7
--operation mode is normal

M1L337 = M1L237 & (L51_q[1] # !H1_sour_reg[1]) # !M1L237 & (H1_sour_reg[1] & L41_q[1]);

--M1L347 is reg_mux:inst27|sr[1]~644 at LC5_H7
--operation mode is normal

M1L347 = M1L237 & (L51_q[1] # !H1_sour_reg[1]) # !M1L237 & (H1_sour_reg[1] & L41_q[1]);


--M1L437 is reg_mux:inst27|sr[1]~485 at LC4_H6
--operation mode is normal

M1L437 = M1L137 & (M1L337 # !H1_sour_reg[2]) # !M1L137 & (H1_sour_reg[2] & M1L627);

--M1L447 is reg_mux:inst27|sr[1]~645 at LC4_H6
--operation mode is normal

M1L447 = M1L137 & (M1L337 # !H1_sour_reg[2]) # !M1L137 & (H1_sour_reg[2] & M1L627);


--N1L131 is bus_mux:inst28|alu_sr[1]~651 at LC2_H6
--operation mode is normal

N1L131 = H1_offset[1] & (N1L021 # M1L437 & N1L161) # !H1_offset[1] & M1L437 & N1L161;

--N1L231 is bus_mux:inst28|alu_sr[1]~669 at LC2_H6
--operation mode is normal

N1L231 = H1_offset[1] & (N1L021 # M1L437 & N1L161) # !H1_offset[1] & M1L437 & N1L161;


--V9_cs_buffer[3] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC2_G11
--operation mode is arithmetic

V9_cs_buffer[3] = V6_cs_buffer[3] $ !V9_cout[2];

--V9L12 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~313 at LC2_G11
--operation mode is arithmetic

V9L12 = V6_cs_buffer[3] $ !V9_cout[2];

--V9_cout[3] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3] at LC2_G11
--operation mode is arithmetic

V9_cout[3] = CARRY(V9_cout[2] # !V6_cs_buffer[3]);


--V3_cs_buffer[2] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC7_G19
--operation mode is arithmetic

V3_cs_buffer[2] = N1L8 $ N1L131 $ V3_cout[1];

--V3L42 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~305 at LC7_G19
--operation mode is arithmetic

V3L42 = N1L8 $ N1L131 $ V3_cout[1];

--V3_cout[2] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] at LC7_G19
--operation mode is arithmetic

V3_cout[2] = CARRY(N1L8 & (N1L131 # V3_cout[1]) # !N1L8 & N1L131 & V3_cout[1]);


--B1L9 is alu:inst|alu_out[1]~5841 at LC3_G19
--operation mode is normal

B1L9 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[3]) # !H1_alu_func[0] & V3_cs_buffer[2] & (!H1_alu_func[1]);

--B1L41 is alu:inst|alu_out[1]~5919 at LC3_G19
--operation mode is normal

B1L41 = H1_alu_func[0] & (H1_alu_func[1] # !V9_cs_buffer[3]) # !H1_alu_func[0] & V3_cs_buffer[2] & (!H1_alu_func[1]);


--B1L01 is alu:inst|alu_out[1]~5842 at LC4_G19
--operation mode is normal

B1L01 = H1_alu_func[1] & (B1L9 & (N1L8 # N1L131) # !B1L9 & N1L8 & N1L131) # !H1_alu_func[1] & B1L9;

--B1L51 is alu:inst|alu_out[1]~5920 at LC4_G19
--operation mode is normal

B1L51 = H1_alu_func[1] & (B1L9 & (N1L8 # N1L131) # !B1L9 & N1L8 & N1L131) # !H1_alu_func[1] & B1L9;


--B1L11 is alu:inst|alu_out[1]~5843 at LC3_H51
--operation mode is normal

B1L11 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L131 $ N1L8);

--B1L61 is alu:inst|alu_out[1]~5921 at LC3_H51
--operation mode is normal

B1L61 = !H1_alu_func[0] & !H1_alu_func[1] & (N1L131 $ N1L8);


--B1L21 is alu:inst|alu_out[1]~5844 at LC5_H51
--operation mode is normal

B1L21 = H1_alu_func[0] & !N1L2 & !H1_alu_func[1] # !H1_alu_func[0] & (H1_alu_func[1] & N1L61);

--B1L71 is alu:inst|alu_out[1]~5922 at LC5_H51
--operation mode is normal

B1L71 = H1_alu_func[0] & !N1L2 & !H1_alu_func[1] # !H1_alu_func[0] & (H1_alu_func[1] & N1L61);


--B1L31 is alu:inst|alu_out[1]~5845 at LC6_H51
--operation mode is normal

B1L31 = H1_alu_func[2] & (B1L21 # B1L11) # !H1_alu_func[2] & (B1L01);

--B1L81 is alu:inst|alu_out[1]~5923 at LC6_H51
--operation mode is normal

B1L81 = H1_alu_func[2] & (B1L21 # B1L11) # !H1_alu_func[2] & (B1L01);


--V9_cs_buffer[2] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC1_G11
--operation mode is arithmetic

V9_cs_buffer[2] = V6_cs_buffer[2] $ P1L1;

--V9L91 is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~314 at LC1_G11
--operation mode is arithmetic

V9L91 = V6_cs_buffer[2] $ P1L1;

--V9_cout[2] is alu:inst|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] at LC1_G11
--operation mode is arithmetic

V9_cout[2] = CARRY(V6_cs_buffer[2] # P1L1);


--L5_q[0] is reg:inst16|q[0] at LC2_E14
--operation mode is normal

L5_q[0]_lut_out = B1L4;
L5_q[0] = DFFEA(L5_q[0]_lut_out, GLOBAL(clk), reset, , M1L133, , );

--L5L3Q is reg:inst16|q[0]~109 at LC2_E14
--operation mode is normal

L5L3Q = L5_q[0];


--L9_q[0] is reg:inst20|q[0] at LC5_E14
--operation mode is normal

L9_q[0]_lut_out = B1L4;
L9_q[0] = DFFEA(L9_q[0]_lut_out, GLOBAL(clk), reset, , M1L933, , );

--L9L3Q is reg:inst20|q[0]~109 at LC5_E14
--operation mode is normal

L9L3Q = L9_q[0];


--L1_q[0] is reg:inst12|q[0] at LC4_E38
--operation mode is normal

L1_q[0]_lut_out = B1L4;
L1_q[0] = DFFEA(L1_q[0]_lut_out, GLOBAL(clk), reset, , M1L323, , );

--L1L3Q is reg:inst12|q[0]~109 at LC4_E38
--operation mode is normal

L1L3Q = L1_q[0];


--M1L507 is reg_mux:inst27|sr[0]~486 at LC6_E14
--operation mode is normal

M1L507 = H1_sour_reg[3] & (L9_q[0] # H1_sour_reg[2]) # !H1_sour_reg[3] & L1_q[0] & (!H1_sour_reg[2]);

--M1L517 is reg_mux:inst27|sr[0]~646 at LC6_E14
--operation mode is normal

M1L517 = H1_sour_reg[3] & (L9_q[0] # H1_sour_reg[2]) # !H1_sour_reg[3] & L1_q[0] & (!H1_sour_reg[2]);


--L31_q[0] is reg:inst24|q[0] at LC1_E44
--operation mode is normal

L31_q[0]_lut_out = B1L4;
L31_q[0] = DFFEA(L31_q[0]_lut_out, GLOBAL(clk), reset, , M1L743, , );

--L31L3Q is reg:inst24|q[0]~109 at LC1_E44
--operation mode is normal

L31L3Q = L31_q[0];


--M1L607 is reg_mux:inst27|sr[0]~487 at LC1_E14
--operation mode is normal

M1L607 = M1L507 & (L31_q[0] # !H1_sour_reg[2]) # !M1L507 & (H1_sour_reg[2] & L5_q[0]);

--M1L617 is reg_mux:inst27|sr[0]~647 at LC1_E14
--operation mode is normal

M1L617 = M1L507 & (L31_q[0] # !H1_sour_reg[2]) # !M1L507 & (H1_sour_reg[2] & L5_q[0]);


--L01_q[0] is reg:inst21|q[0] at LC8_E39
--operation mode is normal

L01_q[0]_lut_out = B1L4;
L01_q[0] = DFFEA(L01_q[0]_lut_out, GLOBAL(clk), reset, , M1L143, , );

--L01L3Q is reg:inst21|q[0]~109 at LC8_E39
--operation mode is normal

L01L3Q = L01_q[0];


--L6_q[0] is reg:inst17|q[0] at LC4_E18
--operation mode is normal

L6_q[0]_lut_out = B1L4;
L6_q[0] = DFFEA(L6_q[0]_lut_out, GLOBAL(clk), reset, , M1L333, , );

--L6L3Q is reg:inst17|q[0]~109 at LC4_E18
--operation mode is normal

L6L3Q = L6_q[0];


--L2_q[0] is reg:inst13|q[0] at LC2_E51
--operation mode is normal

L2_q[0]_lut_out = B1L4;
L2_q[0] = DFFEA(L2_q[0]_lut_out, GLOBAL(clk), reset, , M1L523, , );

--L2L3Q is reg:inst13|q[0]~109 at LC2_E51
--operation mode is normal

L2L3Q = L2_q[0];


--M1L707 is reg_mux:inst27|sr[0]~488 at LC1_E9
--operation mode is normal

M1L707 = H1_sour_reg[2] & (L6_q[0] # H1_sour_reg[3]) # !H1_sour_reg[2] & L2_q[0] & (!H1_sour_reg[3]);

--M1L717 is reg_mux:inst27|sr[0]~648 at LC1_E9
--operation mode is normal

M1L717 = H1_sour_reg[2] & (L6_q[0] # H1_sour_reg[3]) # !H1_sour_reg[2] & L2_q[0] & (!H1_sour_reg[3]);


--L41_q[0] is reg:inst25|q[0] at LC3_E26
--operation mode is normal

L41_q[0]_lut_out = B1L4;
L41_q[0] = DFFEA(L41_q[0]_lut_out, GLOBAL(clk), reset, , M1L943, , );

--L41L3Q is reg:inst25|q[0]~109 at LC3_E26
--operation mode is normal

L41L3Q = L41_q[0];


--M1L807 is reg_mux:inst27|sr[0]~489 at LC3_E9
--operation mode is normal

M1L807 = M1L707 & (L41_q[0] # !H1_sour_reg[3]) # !M1L707 & (H1_sour_reg[3] & L01_q[0]);

--M1L817 is reg_mux:inst27|sr[0]~649 at LC3_E9
--operation mode is normal

M1L817 = M1L707 & (L41_q[0] # !H1_sour_reg[3]) # !M1L707 & (H1_sour_reg[3] & L01_q[0]);


--L8_q[0] is reg:inst19|q[0] at LC8_E5
--operation mode is normal

L8_q[0]_lut_out = B1L4;
L8_q[0] = DFFEA(L8_q[0]_lut_out, GLOBAL(clk), reset, , M1L733, , );

--L8L3Q is reg:inst19|q[0]~109 at LC8_E5
--operation mode is normal

L8L3Q = L8_q[0];


--L4_q[0] is reg:inst15|q[0] at LC1_E22
--operation mode is normal

L4_q[0]_lut_out = B1L4;
L4_q[0] = DFFEA(L4_q[0]_lut_out, GLOBAL(clk), reset, , M1L923, , );

--L4L3Q is reg:inst15|q[0]~109 at LC1_E22
--operation mode is normal

L4L3Q = L4_q[0];


--L61_q[0] is reg:inst30|q[0] at LC1_E8
--operation mode is normal

L61_q[0]_lut_out = B1L4;
L61_q[0] = DFFEA(L61_q[0]_lut_out, GLOBAL(clk), reset, , M1L123, , );

--L61L3Q is reg:inst30|q[0]~109 at LC1_E8
--operation mode is normal

L61L3Q = L61_q[0];


--M1L907 is reg_mux:inst27|sr[0]~490 at LC3_E8
--operation mode is normal

M1L907 = H1_sour_reg[2] & (L4_q[0] # H1_sour_reg[3]) # !H1_sour_reg[2] & L61_q[0] & (!H1_sour_reg[3]);

--M1L917 is reg_mux:inst27|sr[0]~650 at LC3_E8
--operation mode is normal

M1L917 = H1_sour_reg[2] & (L4_q[0] # H1_sour_reg[3]) # !H1_sour_reg[2] & L61_q[0] & (!H1_sour_reg[3]);


--L21_q[0] is reg:inst23|q[0] at LC4_E3
--operation mode is normal

L21_q[0]_lut_out = B1L4;
L21_q[0] = DFFEA(L21_q[0]_lut_out, GLOBAL(clk), reset, , M1L543, , );

--L21L3Q is reg:inst23|q[0]~109 at LC4_E3
--operation mode is normal

L21L3Q = L21_q[0];


--M1L017 is reg_mux:inst27|sr[0]~491 at LC8_E8
--operation mode is normal

M1L017 = M1L907 & (L21_q[0] # !H1_sour_reg[3]) # !M1L907 & (H1_sour_reg[3] & L8_q[0]);

--M1L027 is reg_mux:inst27|sr[0]~651 at LC8_E8
--operation mode is normal

M1L027 = M1L907 & (L21_q[0] # !H1_sour_reg[3]) # !M1L907 & (H1_sour_reg[3] & L8_q[0]);


--M1L117 is reg_mux:inst27|sr[0]~492 at LC5_E9
--operation mode is normal

M1L117 = H1_sour_reg[1] & (M1L807 # H1_sour_reg[0]) # !H1_sour_reg[1] & M1L017 & (!H1_sour_reg[0]);

--M1L127 is reg_mux:inst27|sr[0]~652 at LC5_E9
--operation mode is normal

M1L127 = H1_sour_reg[1] & (M1L807 # H1_sour_reg[0]) # !H1_sour_reg[1] & M1L017 & (!H1_sour_reg[0]);


--L7_q[0] is reg:inst18|q[0] at LC1_E47
--operation mode is normal

L7_q[0]_lut_out = B1L4;
L7_q[0] = DFFEA(L7_q[0]_lut_out, GLOBAL(clk), reset, , M1L533, , );

--L7L3Q is reg:inst18|q[0]~109 at LC1_E47
--operation mode is normal

L7L3Q = L7_q[0];


--L11_q[0] is reg:inst22|q[0] at LC1_E11
--operation mode is normal

L11_q[0]_lut_out = B1L4;
L11_q[0] = DFFEA(L11_q[0]_lut_out, GLOBAL(clk), reset, , M1L343, , );

--L11L3Q is reg:inst22|q[0]~109 at LC1_E11
--operation mode is normal

L11L3Q = L11_q[0];


--L3_q[0] is reg:inst14|q[0] at LC3_E11
--operation mode is normal

L3_q[0]_lut_out = B1L4;
L3_q[0] = DFFEA(L3_q[0]_lut_out, GLOBAL(clk), reset, , M1L723, , );

--L3L3Q is reg:inst14|q[0]~109 at LC3_E11
--operation mode is normal

L3L3Q = L3_q[0];


--M1L217 is reg_mux:inst27|sr[0]~493 at LC6_E11
--operation mode is normal

M1L217 = H1_sour_reg[3] & (L11_q[0] # H1_sour_reg[2]) # !H1_sour_reg[3] & L3_q[0] & (!H1_sour_reg[2]);

--M1L227 is reg_mux:inst27|sr[0]~653 at LC6_E11
--operation mode is normal

M1L227 = H1_sour_reg[3] & (L11_q[0] # H1_sour_reg[2]) # !H1_sour_reg[3] & L3_q[0] & (!H1_sour_reg[2]);


--L51_q[0] is reg:inst26|q[0] at LC2_E19
--operation mode is normal

L51_q[0]_lut_out = B1L4;
L51_q[0] = DFFEA(L51_q[0]_lut_out, GLOBAL(clk), reset, , M1L153, , );

--L51L3Q is reg:inst26|q[0]~109 at LC2_E19
--operation mode is normal

L51L3Q = L51_q[0];


--M1L317 is reg_mux:inst27|sr[0]~494 at LC4_E11
--operation mode is normal

M1L317 = M1L217 & (L51_q[0] # !H1_sour_reg[2]) # !M1L217 & (H1_sour_reg[2] & L7_q[0]);

--M1L327 is reg_mux:inst27|sr[0]~654 at LC4_E11
--operation mode is normal

M1L327 = M1L217 & (L51_q[0] # !H1_sour_reg[2]) # !M1L217 & (H1_sour_reg[2] & L7_q[0]);


--M1L417 is reg_mux:inst27|sr[0]~495 at LC6_E9
--operation mode is normal

M1L417 = M1L117 & (M1L317 # !H1_sour_reg[0]) # !M1L117 & (H1_sour_reg[0] & M1L607);

--M1L427 is reg_mux:inst27|sr[0]~655 at LC6_E9
--operation mode is normal

M1L427 = M1L117 & (M1L317 # !H1_sour_reg[0]) # !M1L117 & (H1_sour_reg[0] & M1L607);


--N1L921 is bus_mux:inst28|alu_sr[0]~652 at LC4_E9
--operation mode is normal

N1L921 = H1_offset[0] & (N1L021 # M1L417 & N1L161) # !H1_offset[0] & M1L417 & N1L161;

--N1L031 is bus_mux:inst28|alu_sr[0]~670 at LC4_E9
--operation mode is normal

N1L031 = H1_offset[0] & (N1L021 # M1L417 & N1L161) # !H1_offset[0] & M1L417 & N1L161;


--B1L562 is alu:inst|temp2~0 at LC1_G51
--operation mode is normal

B1L562 = !N1L2 & N1L921;

--B1L592 is alu:inst|temp2~1524 at LC1_G51
--operation mode is normal

B1L592 = !N1L2 & N1L921;


--V3_cs_buffer[1] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC6_G19
--operation mode is arithmetic

V3_cs_buffer[1] = N1L2 $ N1L921 $ !V3_cout[0];

--V3L22 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~306 at LC6_G19
--operation mode is arithmetic

V3L22 = N1L2 $ N1L921 $ !V3_cout[0];

--V3_cout[1] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] at LC6_G19
--operation mode is arithmetic

V3_cout[1] = CARRY(N1L2 & N1L921 & V3_cout[0] # !N1L2 & (N1L921 # V3_cout[0]));


--B1L1 is alu:inst|alu_out[0]~5846 at LC2_G51
--operation mode is normal

B1L1 = H1_alu_func[1] & (B1L562 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[1] & (!H1_alu_func[0]);

--B1L5 is alu:inst|alu_out[0]~5924 at LC2_G51
--operation mode is normal

B1L5 = H1_alu_func[1] & (B1L562 # H1_alu_func[0]) # !H1_alu_func[1] & V3_cs_buffer[1] & (!H1_alu_func[0]);


--B1L372 is alu:inst|temp2~16 at LC3_G51
--operation mode is normal

B1L372 = N1L921 # !N1L2;

--B1L692 is alu:inst|temp2~1525 at LC3_G51
--operation mode is normal

B1L692 = N1L921 # !N1L2;


--B1L2 is alu:inst|alu_out[0]~5847 at LC5_G51
--operation mode is normal

B1L2 = B1L1 & (B1L372 # !H1_alu_func[0]) # !B1L1 & (H1_alu_func[0] & !V9_cs_buffer[2]);

--B1L6 is alu:inst|alu_out[0]~5925 at LC5_G51
--operation mode is normal

B1L6 = B1L1 & (B1L372 # !H1_alu_func[0]) # !B1L1 & (H1_alu_func[0] & !V9_cs_buffer[2]);


--B1L3 is alu:inst|alu_out[0]~5848 at LC6_G51
--operation mode is normal

B1L3 = H1_alu_func[1] & (N1L8) # !H1_alu_func[1] & (N1L921 $ !N1L2);

--B1L7 is alu:inst|alu_out[0]~5926 at LC6_G51
--operation mode is normal

B1L7 = H1_alu_func[1] & (N1L8) # !H1_alu_func[1] & (N1L921 $ !N1L2);


--B1L4 is alu:inst|alu_out[0]~5849 at LC4_G51
--operation mode is normal

B1L4 = H1_alu_func[2] & !H1_alu_func[0] & B1L3 # !H1_alu_func[2] & (B1L2);

--B1L8 is alu:inst|alu_out[0]~5927 at LC4_G51
--operation mode is normal

B1L8 = H1_alu_func[2] & !H1_alu_func[0] & B1L3 # !H1_alu_func[2] & (B1L2);


--B1L952 is alu:inst|reduce_nor~165 at LC6_G36
--operation mode is normal

B1L952 = !B1L4 & !B1L251 & !B1L31 & B1L852;

--B1L462 is alu:inst|reduce_nor~170 at LC6_G36
--operation mode is normal

B1L462 = !B1L4 & !B1L251 & !B1L31 & B1L852;


--D1L9 is flag_reg:inst2|Mux~655 at LC6_G52
--operation mode is normal

D1L9 = !H1_sst[1] & !H1_sst[0];

--D1L91 is flag_reg:inst2|Mux~673 at LC6_G52
--operation mode is normal

D1L91 = !H1_sst[1] & !H1_sst[0];


--B1L792 is alu:inst|v~39 at LC8_G50
--operation mode is normal

B1L792 = H1_alu_func[1] # H1_alu_func[2];

--B1L992 is alu:inst|v~41 at LC8_G50
--operation mode is normal

B1L992 = H1_alu_func[1] # H1_alu_func[2];


--B1L892 is alu:inst|v~40 at LC7_G37
--operation mode is normal

B1L892 = B1L792 # N1L221 & (N1L061 # !B1L251) # !N1L221 & (B1L251 # !N1L061);

--B1L003 is alu:inst|v~42 at LC7_G37
--operation mode is normal

B1L003 = B1L792 # N1L221 & (N1L061 # !B1L251) # !N1L221 & (B1L251 # !N1L061);


--H1L28 is controller:inst8|Mux~4104 at LC1_F28
--operation mode is normal

H1L28 = !H1L771 # !G1_q[9];

--H1L131 is controller:inst8|Mux~4159 at LC1_F28
--operation mode is normal

H1L131 = !H1L771 # !G1_q[9];


--H1L38 is controller:inst8|Mux~4105 at LC5_H37
--operation mode is normal

H1L38 = !F1L6 & !F1_output[1] & (!F1_output[2] # !H1L28);

--H1L231 is controller:inst8|Mux~4160 at LC5_H37
--operation mode is normal

H1L231 = !F1L6 & !F1_output[1] & (!F1_output[2] # !H1L28);


--H1L48 is controller:inst8|Mux~4106 at LC4_H37
--operation mode is normal

H1L48 = F1L6 & !F1_output[1] # !F1L6 & (F1_output[1] # H1L771) # !F1_output[2];

--H1L331 is controller:inst8|Mux~4161 at LC4_H37
--operation mode is normal

H1L331 = F1L6 & !F1_output[1] # !F1L6 & (F1_output[1] # H1L771) # !F1_output[2];


--H1_rec[1] is controller:inst8|rec[1] at LC3_H37
--operation mode is normal

H1_rec[1] = H1L48 & (H1L38) # !H1L48 & H1_rec[1];

--H1L371 is controller:inst8|rec[1]~40 at LC3_H37
--operation mode is normal

H1L371 = H1L48 & (H1L38) # !H1L48 & H1_rec[1];


--H1L54 is controller:inst8|en_reg~749 at LC3_F2
--operation mode is normal

H1L54 = H1L771 & (G1_q[8] $ G1_q[9]);

--H1L94 is controller:inst8|en_reg~754 at LC3_F2
--operation mode is normal

H1L94 = H1L771 & (G1_q[8] $ G1_q[9]);


--H1L212 is controller:inst8|reduce_or~544 at LC4_F2
--operation mode is normal

H1L212 = G1_q[11] & (G1_q[9] & G1_q[10]) # !G1_q[11] & G1_q[8] & (G1_q[9] $ G1_q[10]);

--H1L722 is controller:inst8|reduce_or~559 at LC4_F2
--operation mode is normal

H1L722 = G1_q[11] & (G1_q[9] & G1_q[10]) # !G1_q[11] & G1_q[8] & (G1_q[9] $ G1_q[10]);


--H1L64 is controller:inst8|en_reg~750 at LC5_F2
--operation mode is normal

H1L64 = H1L212 & !H1L481 & (H1_alu_out_sel[0]) # !H1L212 & (H1L67 # !H1L481 & H1_alu_out_sel[0]);

--H1L05 is controller:inst8|en_reg~755 at LC5_F2
--operation mode is normal

H1L05 = H1L212 & !H1L481 & (H1_alu_out_sel[0]) # !H1L212 & (H1L67 # !H1L481 & H1_alu_out_sel[0]);


--H1L74 is controller:inst8|en_reg~751 at LC6_F2
--operation mode is normal

H1L74 = F1_output[1] & (F1_output[2] & (H1L54) # !F1_output[2] & H1L64);

--H1L15 is controller:inst8|en_reg~756 at LC6_F2
--operation mode is normal

H1L15 = F1_output[1] & (F1_output[2] & (H1L54) # !F1_output[2] & H1L64);


--H1L84 is controller:inst8|en_reg~752 at LC1_F2
--operation mode is normal

H1L84 = H1L74 # !H1L771 & H1_alu_out_sel[0] & F1_output[2];

--H1L25 is controller:inst8|en_reg~757 at LC1_F2
--operation mode is normal

H1L25 = H1L74 # !H1L771 & H1_alu_out_sel[0] & F1_output[2];


--M1L353 is reg_mux:inst27|Mux~160 at LC1_E23
--operation mode is normal

M1L353 = H1_dest_reg[3] & H1_dest_reg[2] & !H1_dest_reg[1] & !H1_dest_reg[0];

--M1L963 is reg_mux:inst27|Mux~176 at LC1_E23
--operation mode is normal

M1L963 = H1_dest_reg[3] & H1_dest_reg[2] & !H1_dest_reg[1] & !H1_dest_reg[0];


--M1L543 is reg_mux:inst27|en_c~10 at LC7_E23
--operation mode is normal

M1L543 = !F1_state.s1 & F1_state.s0 & M1L353 & H1L84;

--M1L643 is reg_mux:inst27|en_c~11 at LC7_E23
--operation mode is normal

M1L643 = !F1_state.s1 & F1_state.s0 & M1L353 & H1L84;


--M1L453 is reg_mux:inst27|Mux~161 at LC3_E4
--operation mode is normal

M1L453 = H1_dest_reg[3] & !H1_dest_reg[2] & H1_dest_reg[1] & !H1_dest_reg[0];

--M1L073 is reg_mux:inst27|Mux~177 at LC3_E4
--operation mode is normal

M1L073 = H1_dest_reg[3] & !H1_dest_reg[2] & H1_dest_reg[1] & !H1_dest_reg[0];


--M1L143 is reg_mux:inst27|en_a~10 at LC1_E4
--operation mode is normal

M1L143 = !F1_state.s1 & F1_state.s0 & M1L453 & H1L84;

--M1L243 is reg_mux:inst27|en_a~11 at LC1_E4
--operation mode is normal

M1L243 = !F1_state.s1 & F1_state.s0 & M1L453 & H1L84;


--M1L553 is reg_mux:inst27|Mux~162 at LC4_I5
--operation mode is normal

M1L553 = H1_dest_reg[3] & !H1_dest_reg[2] & !H1_dest_reg[1] & !H1_dest_reg[0];

--M1L173 is reg_mux:inst27|Mux~178 at LC4_I5
--operation mode is normal

M1L173 = H1_dest_reg[3] & !H1_dest_reg[2] & !H1_dest_reg[1] & !H1_dest_reg[0];


--M1L733 is reg_mux:inst27|en_8~10 at LC1_I5
--operation mode is normal

M1L733 = !F1_state.s1 & F1_state.s0 & M1L553 & H1L84;

--M1L833 is reg_mux:inst27|en_8~11 at LC1_I5
--operation mode is normal

M1L833 = !F1_state.s1 & F1_state.s0 & M1L553 & H1L84;


--M1L653 is reg_mux:inst27|Mux~163 at LC2_E23
--operation mode is normal

M1L653 = H1_dest_reg[3] & H1_dest_reg[2] & H1_dest_reg[1] & !H1_dest_reg[0];

--M1L273 is reg_mux:inst27|Mux~179 at LC2_E23
--operation mode is normal

M1L273 = H1_dest_reg[3] & H1_dest_reg[2] & H1_dest_reg[1] & !H1_dest_reg[0];


--M1L943 is reg_mux:inst27|en_e~10 at LC5_E23
--operation mode is normal

M1L943 = !F1_state.s1 & F1_state.s0 & M1L653 & H1L84;

--M1L053 is reg_mux:inst27|en_e~11 at LC5_E23
--operation mode is normal

M1L053 = !F1_state.s1 & F1_state.s0 & M1L653 & H1L84;


--M1L753 is reg_mux:inst27|Mux~164 at LC4_E4
--operation mode is normal

M1L753 = !H1_dest_reg[3] & H1_dest_reg[2] & !H1_dest_reg[1] & H1_dest_reg[0];

--M1L373 is reg_mux:inst27|Mux~180 at LC4_E4
--operation mode is normal

M1L373 = !H1_dest_reg[3] & H1_dest_reg[2] & !H1_dest_reg[1] & H1_dest_reg[0];


--M1L133 is reg_mux:inst27|en_5~10 at LC2_E4
--operation mode is normal

M1L133 = !F1_state.s1 & F1_state.s0 & M1L753 & H1L84;

--M1L233 is reg_mux:inst27|en_5~11 at LC2_E4
--operation mode is normal

M1L233 = !F1_state.s1 & F1_state.s0 & M1L753 & H1L84;


--M1L853 is reg_mux:inst27|Mux~165 at LC7_E4
--operation mode is normal

M1L853 = !H1_dest_reg[3] & !H1_dest_reg[2] & H1_dest_reg[1] & H1_dest_reg[0];

--M1L473 is reg_mux:inst27|Mux~181 at LC7_E4
--operation mode is normal

M1L473 = !H1_dest_reg[3] & !H1_dest_reg[2] & H1_dest_reg[1] & H1_dest_reg[0];


--M1L723 is reg_mux:inst27|en_3~10 at LC5_E4
--operation mode is normal

M1L723 = !F1_state.s1 & F1_state.s0 & M1L853 & H1L84;

--M1L823 is reg_mux:inst27|en_3~11 at LC5_E4
--operation mode is normal

M1L823 = !F1_state.s1 & F1_state.s0 & M1L853 & H1L84;


--M1L953 is reg_mux:inst27|Mux~166 at LC5_I5
--operation mode is normal

M1L953 = !H1_dest_reg[3] & !H1_dest_reg[2] & !H1_dest_reg[1] & H1_dest_reg[0];

--M1L573 is reg_mux:inst27|Mux~182 at LC5_I5
--operation mode is normal

M1L573 = !H1_dest_reg[3] & !H1_dest_reg[2] & !H1_dest_reg[1] & H1_dest_reg[0];


--M1L323 is reg_mux:inst27|en_1~10 at LC6_I5
--operation mode is normal

M1L323 = !F1_state.s1 & F1_state.s0 & M1L953 & H1L84;

--M1L423 is reg_mux:inst27|en_1~11 at LC6_I5
--operation mode is normal

M1L423 = !F1_state.s1 & F1_state.s0 & M1L953 & H1L84;


--M1L063 is reg_mux:inst27|Mux~167 at LC4_E23
--operation mode is normal

M1L063 = !H1_dest_reg[3] & H1_dest_reg[2] & H1_dest_reg[1] & H1_dest_reg[0];

--M1L673 is reg_mux:inst27|Mux~183 at LC4_E23
--operation mode is normal

M1L673 = !H1_dest_reg[3] & H1_dest_reg[2] & H1_dest_reg[1] & H1_dest_reg[0];


--M1L533 is reg_mux:inst27|en_7~10 at LC3_E23
--operation mode is normal

M1L533 = !F1_state.s1 & F1_state.s0 & M1L063 & H1L84;

--M1L633 is reg_mux:inst27|en_7~11 at LC3_E23
--operation mode is normal

M1L633 = !F1_state.s1 & F1_state.s0 & M1L063 & H1L84;


--M1L163 is reg_mux:inst27|Mux~168 at LC7_I5
--operation mode is normal

M1L163 = !H1_dest_reg[3] & H1_dest_reg[2] & !H1_dest_reg[1] & !H1_dest_reg[0];

--M1L773 is reg_mux:inst27|Mux~184 at LC7_I5
--operation mode is normal

M1L773 = !H1_dest_reg[3] & H1_dest_reg[2] & !H1_dest_reg[1] & !H1_dest_reg[0];


--M1L923 is reg_mux:inst27|en_4~10 at LC2_I5
--operation mode is normal

M1L923 = !F1_state.s1 & F1_state.s0 & M1L163 & H1L84;

--M1L033 is reg_mux:inst27|en_4~11 at LC2_I5
--operation mode is normal

M1L033 = !F1_state.s1 & F1_state.s0 & M1L163 & H1L84;


--M1L263 is reg_mux:inst27|Mux~169 at LC8_I5
--operation mode is normal

M1L263 = !H1_dest_reg[3] & !H1_dest_reg[2] & H1_dest_reg[1] & !H1_dest_reg[0];

--M1L873 is reg_mux:inst27|Mux~185 at LC8_I5
--operation mode is normal

M1L873 = !H1_dest_reg[3] & !H1_dest_reg[2] & H1_dest_reg[1] & !H1_dest_reg[0];


--M1L523 is reg_mux:inst27|en_2~10 at LC3_I5
--operation mode is normal

M1L523 = !F1_state.s1 & F1_state.s0 & M1L263 & H1L84;

--M1L623 is reg_mux:inst27|en_2~11 at LC3_I5
--operation mode is normal

M1L623 = !F1_state.s1 & F1_state.s0 & M1L263 & H1L84;


--M1L363 is reg_mux:inst27|Mux~170 at LC1_I12
--operation mode is normal

M1L363 = !H1_dest_reg[3] & !H1_dest_reg[2] & !H1_dest_reg[1] & !H1_dest_reg[0];

--M1L973 is reg_mux:inst27|Mux~186 at LC1_I12
--operation mode is normal

M1L973 = !H1_dest_reg[3] & !H1_dest_reg[2] & !H1_dest_reg[1] & !H1_dest_reg[0];


--M1L123 is reg_mux:inst27|en_0~10 at LC7_I12
--operation mode is normal

M1L123 = !F1_state.s1 & F1_state.s0 & M1L363 & H1L84;

--M1L223 is reg_mux:inst27|en_0~11 at LC7_I12
--operation mode is normal

M1L223 = !F1_state.s1 & F1_state.s0 & M1L363 & H1L84;


--M1L463 is reg_mux:inst27|Mux~171 at LC5_E1
--operation mode is normal

M1L463 = !H1_dest_reg[3] & H1_dest_reg[2] & H1_dest_reg[1] & !H1_dest_reg[0];

--M1L083 is reg_mux:inst27|Mux~187 at LC5_E1
--operation mode is normal

M1L083 = !H1_dest_reg[3] & H1_dest_reg[2] & H1_dest_reg[1] & !H1_dest_reg[0];


--M1L333 is reg_mux:inst27|en_6~10 at LC1_E1
--operation mode is normal

M1L333 = !F1_state.s1 & F1_state.s0 & M1L463 & H1L84;

--M1L433 is reg_mux:inst27|en_6~11 at LC1_E1
--operation mode is normal

M1L433 = !F1_state.s1 & F1_state.s0 & M1L463 & H1L84;


--M1L563 is reg_mux:inst27|Mux~172 at LC6_E1
--operation mode is normal

M1L563 = H1_dest_reg[3] & H1_dest_reg[2] & !H1_dest_reg[1] & H1_dest_reg[0];

--M1L183 is reg_mux:inst27|Mux~188 at LC6_E1
--operation mode is normal

M1L183 = H1_dest_reg[3] & H1_dest_reg[2] & !H1_dest_reg[1] & H1_dest_reg[0];


--M1L743 is reg_mux:inst27|en_d~10 at LC3_E1
--operation mode is normal

M1L743 = !F1_state.s1 & F1_state.s0 & M1L563 & H1L84;

--M1L843 is reg_mux:inst27|en_d~11 at LC3_E1
--operation mode is normal

M1L843 = !F1_state.s1 & F1_state.s0 & M1L563 & H1L84;


--M1L663 is reg_mux:inst27|Mux~173 at LC7_E1
--operation mode is normal

M1L663 = H1_dest_reg[3] & !H1_dest_reg[2] & H1_dest_reg[1] & H1_dest_reg[0];

--M1L283 is reg_mux:inst27|Mux~189 at LC7_E1
--operation mode is normal

M1L283 = H1_dest_reg[3] & !H1_dest_reg[2] & H1_dest_reg[1] & H1_dest_reg[0];


--M1L343 is reg_mux:inst27|en_b~10 at LC2_E1
--operation mode is normal

M1L343 = !F1_state.s1 & F1_state.s0 & M1L663 & H1L84;

--M1L443 is reg_mux:inst27|en_b~11 at LC2_E1
--operation mode is normal

M1L443 = !F1_state.s1 & F1_state.s0 & M1L663 & H1L84;


--M1L763 is reg_mux:inst27|Mux~174 at LC8_E4
--operation mode is normal

M1L763 = H1_dest_reg[3] & !H1_dest_reg[2] & !H1_dest_reg[1] & H1_dest_reg[0];

--M1L383 is reg_mux:inst27|Mux~190 at LC8_E4
--operation mode is normal

M1L383 = H1_dest_reg[3] & !H1_dest_reg[2] & !H1_dest_reg[1] & H1_dest_reg[0];


--M1L933 is reg_mux:inst27|en_9~10 at LC6_E4
--operation mode is normal

M1L933 = !F1_state.s1 & F1_state.s0 & M1L763 & H1L84;

--M1L043 is reg_mux:inst27|en_9~11 at LC6_E4
--operation mode is normal

M1L043 = !F1_state.s1 & F1_state.s0 & M1L763 & H1L84;


--M1L863 is reg_mux:inst27|Mux~175 at LC8_E1
--operation mode is normal

M1L863 = H1_dest_reg[3] & H1_dest_reg[2] & H1_dest_reg[1] & H1_dest_reg[0];

--M1L483 is reg_mux:inst27|Mux~191 at LC8_E1
--operation mode is normal

M1L483 = H1_dest_reg[3] & H1_dest_reg[2] & H1_dest_reg[1] & H1_dest_reg[0];


--M1L153 is reg_mux:inst27|en_f~10 at LC4_E1
--operation mode is normal

M1L153 = !F1_state.s1 & F1_state.s0 & M1L863 & H1L84;

--M1L253 is reg_mux:inst27|en_f~11 at LC4_E1
--operation mode is normal

M1L253 = !F1_state.s1 & F1_state.s0 & M1L863 & H1L84;


--M1L103 is reg_mux:inst27|dr[15]~476 at LC7_K19
--operation mode is normal

M1L103 = H1_dest_reg[0] & (L9_q[15] # H1_dest_reg[1]) # !H1_dest_reg[0] & L8_q[15] & (!H1_dest_reg[1]);

--M1L113 is reg_mux:inst27|dr[15]~636 at LC7_K19
--operation mode is normal

M1L113 = H1_dest_reg[0] & (L9_q[15] # H1_dest_reg[1]) # !H1_dest_reg[0] & L8_q[15] & (!H1_dest_reg[1]);


--M1L203 is reg_mux:inst27|dr[15]~477 at LC2_K19
--operation mode is normal

M1L203 = M1L103 & (L11_q[15] # !H1_dest_reg[1]) # !M1L103 & (H1_dest_reg[1] & L01_q[15]);

--M1L213 is reg_mux:inst27|dr[15]~637 at LC2_K19
--operation mode is normal

M1L213 = M1L103 & (L11_q[15] # !H1_dest_reg[1]) # !M1L103 & (H1_dest_reg[1] & L01_q[15]);


--M1L303 is reg_mux:inst27|dr[15]~478 at LC1_K17
--operation mode is normal

M1L303 = H1_dest_reg[1] & (L6_q[15] # H1_dest_reg[0]) # !H1_dest_reg[1] & L4_q[15] & (!H1_dest_reg[0]);

--M1L313 is reg_mux:inst27|dr[15]~638 at LC1_K17
--operation mode is normal

M1L313 = H1_dest_reg[1] & (L6_q[15] # H1_dest_reg[0]) # !H1_dest_reg[1] & L4_q[15] & (!H1_dest_reg[0]);


--M1L403 is reg_mux:inst27|dr[15]~479 at LC4_K17
--operation mode is normal

M1L403 = M1L303 & (L7_q[15] # !H1_dest_reg[0]) # !M1L303 & (H1_dest_reg[0] & L5_q[15]);

--M1L413 is reg_mux:inst27|dr[15]~639 at LC4_K17
--operation mode is normal

M1L413 = M1L303 & (L7_q[15] # !H1_dest_reg[0]) # !M1L303 & (H1_dest_reg[0] & L5_q[15]);


--M1L503 is reg_mux:inst27|dr[15]~480 at LC1_K18
--operation mode is normal

M1L503 = H1_dest_reg[0] & (L1_q[15] # H1_dest_reg[1]) # !H1_dest_reg[0] & L61_q[15] & (!H1_dest_reg[1]);

--M1L513 is reg_mux:inst27|dr[15]~640 at LC1_K18
--operation mode is normal

M1L513 = H1_dest_reg[0] & (L1_q[15] # H1_dest_reg[1]) # !H1_dest_reg[0] & L61_q[15] & (!H1_dest_reg[1]);


--M1L603 is reg_mux:inst27|dr[15]~481 at LC5_K17
--operation mode is normal

M1L603 = M1L503 & (L3_q[15] # !H1_dest_reg[1]) # !M1L503 & (H1_dest_reg[1] & L2_q[15]);

--M1L613 is reg_mux:inst27|dr[15]~641 at LC5_K17
--operation mode is normal

M1L613 = M1L503 & (L3_q[15] # !H1_dest_reg[1]) # !M1L503 & (H1_dest_reg[1] & L2_q[15]);


--M1L703 is reg_mux:inst27|dr[15]~482 at LC6_K17
--operation mode is normal

M1L703 = H1_dest_reg[2] & (M1L403 # H1_dest_reg[3]) # !H1_dest_reg[2] & M1L603 & (!H1_dest_reg[3]);

--M1L713 is reg_mux:inst27|dr[15]~642 at LC6_K17
--operation mode is normal

M1L713 = H1_dest_reg[2] & (M1L403 # H1_dest_reg[3]) # !H1_dest_reg[2] & M1L603 & (!H1_dest_reg[3]);


--M1L803 is reg_mux:inst27|dr[15]~483 at LC8_K26
--operation mode is normal

M1L803 = H1_dest_reg[1] & (L41_q[15] # H1_dest_reg[0]) # !H1_dest_reg[1] & L21_q[15] & (!H1_dest_reg[0]);

--M1L813 is reg_mux:inst27|dr[15]~643 at LC8_K26
--operation mode is normal

M1L813 = H1_dest_reg[1] & (L41_q[15] # H1_dest_reg[0]) # !H1_dest_reg[1] & L21_q[15] & (!H1_dest_reg[0]);


--M1L903 is reg_mux:inst27|dr[15]~484 at LC1_K26
--operation mode is normal

M1L903 = M1L803 & (L51_q[15] # !H1_dest_reg[0]) # !M1L803 & (H1_dest_reg[0] & L31_q[15]);

--M1L913 is reg_mux:inst27|dr[15]~644 at LC1_K26
--operation mode is normal

M1L913 = M1L803 & (L51_q[15] # !H1_dest_reg[0]) # !M1L803 & (H1_dest_reg[0] & L31_q[15]);


--M1L013 is reg_mux:inst27|dr[15]~485 at LC7_K17
--operation mode is normal

M1L013 = M1L703 & (M1L903 # !H1_dest_reg[3]) # !M1L703 & (H1_dest_reg[3] & M1L203);

--M1L023 is reg_mux:inst27|dr[15]~645 at LC7_K17
--operation mode is normal

M1L023 = M1L703 & (M1L903 # !H1_dest_reg[3]) # !M1L703 & (H1_dest_reg[3] & M1L203);


--N1L121 is bus_mux:inst28|alu_dr[15]~2342 at LC2_K17
--operation mode is normal

N1L121 = N1L911 & !M1L013 & (!K1_q[15] # !N1L021) # !N1L911 & (!K1_q[15] # !N1L021);

--N1L621 is bus_mux:inst28|alu_dr[15]~2412 at LC2_K17
--operation mode is normal

N1L621 = N1L911 & !M1L013 & (!K1_q[15] # !N1L021) # !N1L911 & (!K1_q[15] # !N1L021);

--N1L721 is bus_mux:inst28|alu_dr[15]~2413 at LC2_K17
--operation mode is normal

N1L721 = N1L911 & !M1L013 & (!K1_q[15] # !N1L021) # !N1L911 & (!K1_q[15] # !N1L021);


--N1L221 is bus_mux:inst28|alu_dr[15]~2363 at LC3_K17
--operation mode is normal

N1L221 = (H1_alu_in_sel[0] & !A1L73 # !H1_alu_in_sel[0] & (!K1_q[15]) # !N1L811) & CASCADE(N1L721);

--N1L821 is bus_mux:inst28|alu_dr[15]~2414 at LC3_K17
--operation mode is normal

N1L821 = (H1_alu_in_sel[0] & !A1L73 # !H1_alu_in_sel[0] & (!K1_q[15]) # !N1L811) & CASCADE(N1L721);


--V6_cs_buffer[16] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[16] at LC7_G12
--operation mode is arithmetic

V6_cs_buffer[16] = N1L211 $ N1L751 $ V6_cout[15];

--V6L74 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]~424 at LC7_G12
--operation mode is arithmetic

V6L74 = N1L211 $ N1L751 $ V6_cout[15];

--V6_cout[16] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] at LC7_G12
--operation mode is arithmetic

V6_cout[16] = CARRY(N1L211 & (V6_cout[15] # !N1L751) # !N1L211 & !N1L751 & V6_cout[15]);


--T2_unreg_res_node[17] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[17] at LC8_G12
--operation mode is normal

T2_unreg_res_node[17] = N1L221 $ V6_cout[16] $ !N1L061;

--T2L3 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[17]~33 at LC8_G12
--operation mode is normal

T2L3 = N1L221 $ V6_cout[16] $ !N1L061;


--M1L566 is reg_mux:inst27|reg_out[14]~356 at LC3_F15
--operation mode is normal

M1L566 = reg_sel[1] & (L01_q[14] # reg_sel[2]) # !reg_sel[1] & L8_q[14] & (!reg_sel[2]);

--M1L576 is reg_mux:inst27|reg_out[14]~516 at LC3_F15
--operation mode is normal

M1L576 = reg_sel[1] & (L01_q[14] # reg_sel[2]) # !reg_sel[1] & L8_q[14] & (!reg_sel[2]);


--M1L666 is reg_mux:inst27|reg_out[14]~357 at LC2_F15
--operation mode is normal

M1L666 = M1L566 & (L41_q[14] # !reg_sel[2]) # !M1L566 & (reg_sel[2] & L21_q[14]);

--M1L676 is reg_mux:inst27|reg_out[14]~517 at LC2_F15
--operation mode is normal

M1L676 = M1L566 & (L41_q[14] # !reg_sel[2]) # !M1L566 & (reg_sel[2] & L21_q[14]);


--M1L766 is reg_mux:inst27|reg_out[14]~358 at LC4_F15
--operation mode is normal

M1L766 = reg_sel[1] & (L3_q[14] # reg_sel[2]) # !reg_sel[1] & L1_q[14] & (!reg_sel[2]);

--M1L776 is reg_mux:inst27|reg_out[14]~518 at LC4_F15
--operation mode is normal

M1L776 = reg_sel[1] & (L3_q[14] # reg_sel[2]) # !reg_sel[1] & L1_q[14] & (!reg_sel[2]);


--M1L866 is reg_mux:inst27|reg_out[14]~359 at LC1_F15
--operation mode is normal

M1L866 = M1L766 & (L7_q[14] # !reg_sel[2]) # !M1L766 & (reg_sel[2] & L5_q[14]);

--M1L876 is reg_mux:inst27|reg_out[14]~519 at LC1_F15
--operation mode is normal

M1L876 = M1L766 & (L7_q[14] # !reg_sel[2]) # !M1L766 & (reg_sel[2] & L5_q[14]);


--M1L966 is reg_mux:inst27|reg_out[14]~360 at LC7_F11
--operation mode is normal

M1L966 = reg_sel[1] & (L2_q[14] # reg_sel[2]) # !reg_sel[1] & L61_q[14] & (!reg_sel[2]);

--M1L976 is reg_mux:inst27|reg_out[14]~520 at LC7_F11
--operation mode is normal

M1L976 = reg_sel[1] & (L2_q[14] # reg_sel[2]) # !reg_sel[1] & L61_q[14] & (!reg_sel[2]);


--M1L076 is reg_mux:inst27|reg_out[14]~361 at LC2_F11
--operation mode is normal

M1L076 = M1L966 & (L6_q[14] # !reg_sel[2]) # !M1L966 & (reg_sel[2] & L4_q[14]);

--M1L086 is reg_mux:inst27|reg_out[14]~521 at LC2_F11
--operation mode is normal

M1L086 = M1L966 & (L6_q[14] # !reg_sel[2]) # !M1L966 & (reg_sel[2] & L4_q[14]);


--M1L176 is reg_mux:inst27|reg_out[14]~362 at LC2_F21
--operation mode is normal

M1L176 = reg_sel[0] & (M1L866 # reg_sel[3]) # !reg_sel[0] & M1L076 & (!reg_sel[3]);

--M1L186 is reg_mux:inst27|reg_out[14]~522 at LC2_F21
--operation mode is normal

M1L186 = reg_sel[0] & (M1L866 # reg_sel[3]) # !reg_sel[0] & M1L076 & (!reg_sel[3]);


--M1L276 is reg_mux:inst27|reg_out[14]~363 at LC7_F7
--operation mode is normal

M1L276 = reg_sel[1] & (L11_q[14] # reg_sel[2]) # !reg_sel[1] & L9_q[14] & (!reg_sel[2]);

--M1L286 is reg_mux:inst27|reg_out[14]~523 at LC7_F7
--operation mode is normal

M1L286 = reg_sel[1] & (L11_q[14] # reg_sel[2]) # !reg_sel[1] & L9_q[14] & (!reg_sel[2]);


--M1L376 is reg_mux:inst27|reg_out[14]~364 at LC1_F7
--operation mode is normal

M1L376 = M1L276 & (L51_q[14] # !reg_sel[2]) # !M1L276 & (reg_sel[2] & L31_q[14]);

--M1L386 is reg_mux:inst27|reg_out[14]~524 at LC1_F7
--operation mode is normal

M1L386 = M1L276 & (L51_q[14] # !reg_sel[2]) # !M1L276 & (reg_sel[2] & L31_q[14]);


--M1L476 is reg_mux:inst27|reg_out[14]~365 at LC3_F21
--operation mode is normal

M1L476 = M1L176 & (M1L376 # !reg_sel[3]) # !M1L176 & (reg_sel[3] & M1L666);

--M1L486 is reg_mux:inst27|reg_out[14]~525 at LC3_F21
--operation mode is normal

M1L486 = M1L176 & (M1L376 # !reg_sel[3]) # !M1L176 & (reg_sel[3] & M1L666);


--R1L261 is reg_out:inst33|reg_data[14]~2798 at LC6_F21
--operation mode is normal

R1L261 = R1L271 & (reg_sel[0] & (G1_q[14]) # !reg_sel[0] & K1_q[14]);

--R1L661 is reg_out:inst33|reg_data[14]~2879 at LC6_F21
--operation mode is normal

R1L661 = R1L271 & (reg_sel[0] & (G1_q[14]) # !reg_sel[0] & K1_q[14]);


--R1L361 is reg_out:inst33|reg_data[14]~2799 at LC4_F21
--operation mode is normal

R1L361 = !R1L261 & (sel[1] # sel[0] # !M1L476);

--R1L761 is reg_out:inst33|reg_data[14]~2880 at LC4_F21
--operation mode is normal

R1L761 = !R1L261 & (sel[1] # sel[0] # !M1L476);

--R1L861 is reg_out:inst33|reg_data[14]~2881 at LC4_F21
--operation mode is normal

R1L861 = !R1L261 & (sel[1] # sel[0] # !M1L476);


--C1_q[14] is reg_testa:inst1|q[14] at LC2_H25
--operation mode is normal

C1_q[14]_lut_out = F1_state.s5 # F1_state.s4 # !F1_state.s0;
C1_q[14] = DFFEA(C1_q[14]_lut_out, GLOBAL(clk), reset, , , , );

--C1L92Q is reg_testa:inst1|q[14]~9 at LC2_H25
--operation mode is normal

C1L92Q = C1_q[14];


--R1L771 is reg_out:inst33|reg_data[15]~2800 at LC5_I22
--operation mode is normal

R1L771 = !sel[1] & !reg_sel[3] & sel[0];

--R1L481 is reg_out:inst33|reg_data[15]~2882 at LC5_I22
--operation mode is normal

R1L481 = !sel[1] & !reg_sel[3] & sel[0];


--R1L461 is reg_out:inst33|reg_data[14]~2801 at LC6_I22
--operation mode is normal

R1L461 = !reg_sel[1] & !reg_sel[0] & reg_sel[2] & R1L771;

--R1L961 is reg_out:inst33|reg_data[14]~2883 at LC6_I22
--operation mode is normal

R1L961 = !reg_sel[1] & !reg_sel[0] & reg_sel[2] & R1L771;


--R1L5 is reg_out:inst33|Mux~589 at LC2_F8
--operation mode is normal

R1L5 = reg_sel[0] & (N1L751 # reg_sel[1]) # !reg_sel[0] & H1_offset[7] & (!reg_sel[1]);

--R1L73 is reg_out:inst33|Mux~621 at LC2_F8
--operation mode is normal

R1L73 = reg_sel[0] & (N1L751 # reg_sel[1]) # !reg_sel[0] & H1_offset[7] & (!reg_sel[1]);


--R1L6 is reg_out:inst33|Mux~590 at LC3_F8
--operation mode is normal

R1L6 = R1L5 & (B1L341 # !reg_sel[1]) # !R1L5 & (reg_sel[1] & N1L211);

--R1L83 is reg_out:inst33|Mux~622 at LC3_F8
--operation mode is normal

R1L83 = R1L5 & (B1L341 # !reg_sel[1]) # !R1L5 & (reg_sel[1] & N1L211);


--R1L561 is reg_out:inst33|reg_data[14]~2842 at LC5_F21
--operation mode is normal

R1L561 = (R1L6 & !R1L571 & (!C1_q[14] # !R1L461) # !R1L6 & (!C1_q[14] # !R1L461)) & CASCADE(R1L861);

--R1L071 is reg_out:inst33|reg_data[14]~2884 at LC5_F21
--operation mode is normal

R1L071 = (R1L6 & !R1L571 & (!C1_q[14] # !R1L461) # !R1L6 & (!C1_q[14] # !R1L461)) & CASCADE(R1L861);


--M1L546 is reg_mux:inst27|reg_out[13]~366 at LC8_C6
--operation mode is normal

M1L546 = reg_sel[1] & (L01_q[13] # reg_sel[2]) # !reg_sel[1] & L8_q[13] & (!reg_sel[2]);

--M1L556 is reg_mux:inst27|reg_out[13]~526 at LC8_C6
--operation mode is normal

M1L556 = reg_sel[1] & (L01_q[13] # reg_sel[2]) # !reg_sel[1] & L8_q[13] & (!reg_sel[2]);


--M1L646 is reg_mux:inst27|reg_out[13]~367 at LC6_C8
--operation mode is normal

M1L646 = M1L546 & (L41_q[13] # !reg_sel[2]) # !M1L546 & (reg_sel[2] & L21_q[13]);

--M1L656 is reg_mux:inst27|reg_out[13]~527 at LC6_C8
--operation mode is normal

M1L656 = M1L546 & (L41_q[13] # !reg_sel[2]) # !M1L546 & (reg_sel[2] & L21_q[13]);


--M1L746 is reg_mux:inst27|reg_out[13]~368 at LC3_C15
--operation mode is normal

M1L746 = reg_sel[1] & (L3_q[13] # reg_sel[2]) # !reg_sel[1] & L1_q[13] & (!reg_sel[2]);

--M1L756 is reg_mux:inst27|reg_out[13]~528 at LC3_C15
--operation mode is normal

M1L756 = reg_sel[1] & (L3_q[13] # reg_sel[2]) # !reg_sel[1] & L1_q[13] & (!reg_sel[2]);


--M1L846 is reg_mux:inst27|reg_out[13]~369 at LC7_C12
--operation mode is normal

M1L846 = M1L746 & (L7_q[13] # !reg_sel[2]) # !M1L746 & (reg_sel[2] & L5_q[13]);

--M1L856 is reg_mux:inst27|reg_out[13]~529 at LC7_C12
--operation mode is normal

M1L856 = M1L746 & (L7_q[13] # !reg_sel[2]) # !M1L746 & (reg_sel[2] & L5_q[13]);


--M1L946 is reg_mux:inst27|reg_out[13]~370 at LC2_C15
--operation mode is normal

M1L946 = reg_sel[1] & (L2_q[13] # reg_sel[2]) # !reg_sel[1] & L61_q[13] & (!reg_sel[2]);

--M1L956 is reg_mux:inst27|reg_out[13]~530 at LC2_C15
--operation mode is normal

M1L956 = reg_sel[1] & (L2_q[13] # reg_sel[2]) # !reg_sel[1] & L61_q[13] & (!reg_sel[2]);


--M1L056 is reg_mux:inst27|reg_out[13]~371 at LC8_C12
--operation mode is normal

M1L056 = M1L946 & (L6_q[13] # !reg_sel[2]) # !M1L946 & (reg_sel[2] & L4_q[13]);

--M1L066 is reg_mux:inst27|reg_out[13]~531 at LC8_C12
--operation mode is normal

M1L066 = M1L946 & (L6_q[13] # !reg_sel[2]) # !M1L946 & (reg_sel[2] & L4_q[13]);


--M1L156 is reg_mux:inst27|reg_out[13]~372 at LC3_C12
--operation mode is normal

M1L156 = reg_sel[0] & (M1L846 # reg_sel[3]) # !reg_sel[0] & M1L056 & (!reg_sel[3]);

--M1L166 is reg_mux:inst27|reg_out[13]~532 at LC3_C12
--operation mode is normal

M1L166 = reg_sel[0] & (M1L846 # reg_sel[3]) # !reg_sel[0] & M1L056 & (!reg_sel[3]);


--M1L256 is reg_mux:inst27|reg_out[13]~373 at LC1_C9
--operation mode is normal

M1L256 = reg_sel[1] & (L11_q[13] # reg_sel[2]) # !reg_sel[1] & L9_q[13] & (!reg_sel[2]);

--M1L266 is reg_mux:inst27|reg_out[13]~533 at LC1_C9
--operation mode is normal

M1L266 = reg_sel[1] & (L11_q[13] # reg_sel[2]) # !reg_sel[1] & L9_q[13] & (!reg_sel[2]);


--M1L356 is reg_mux:inst27|reg_out[13]~374 at LC7_C8
--operation mode is normal

M1L356 = M1L256 & (L51_q[13] # !reg_sel[2]) # !M1L256 & (reg_sel[2] & L31_q[13]);

--M1L366 is reg_mux:inst27|reg_out[13]~534 at LC7_C8
--operation mode is normal

M1L366 = M1L256 & (L51_q[13] # !reg_sel[2]) # !M1L256 & (reg_sel[2] & L31_q[13]);


--M1L456 is reg_mux:inst27|reg_out[13]~375 at LC8_C8
--operation mode is normal

M1L456 = M1L156 & (M1L356 # !reg_sel[3]) # !M1L156 & (reg_sel[3] & M1L646);

--M1L466 is reg_mux:inst27|reg_out[13]~535 at LC8_C8
--operation mode is normal

M1L466 = M1L156 & (M1L356 # !reg_sel[3]) # !M1L156 & (reg_sel[3] & M1L646);


--R1L551 is reg_out:inst33|reg_data[13]~2803 at LC7_G30
--operation mode is normal

R1L551 = R1L271 & (reg_sel[0] & (G1_q[13]) # !reg_sel[0] & K1_q[13]);

--R1L851 is reg_out:inst33|reg_data[13]~2885 at LC7_G30
--operation mode is normal

R1L851 = R1L271 & (reg_sel[0] & (G1_q[13]) # !reg_sel[0] & K1_q[13]);


--R1L651 is reg_out:inst33|reg_data[13]~2804 at LC6_H26
--operation mode is normal

R1L651 = !R1L551 & (sel[1] # sel[0] # !M1L456);

--R1L951 is reg_out:inst33|reg_data[13]~2886 at LC6_H26
--operation mode is normal

R1L951 = !R1L551 & (sel[1] # sel[0] # !M1L456);

--R1L061 is reg_out:inst33|reg_data[13]~2887 at LC6_H26
--operation mode is normal

R1L061 = !R1L551 & (sel[1] # sel[0] # !M1L456);


--C1_q[13] is reg_testa:inst1|q[13] at LC2_H26
--operation mode is normal

C1_q[13]_lut_out = F1_state.s3 # F1_state.s5;
C1_q[13] = DFFEA(C1_q[13]_lut_out, GLOBAL(clk), reset, , , , );

--C1L72Q is reg_testa:inst1|q[13]~10 at LC2_H26
--operation mode is normal

C1L72Q = C1_q[13];


--R1L7 is reg_out:inst33|Mux~591 at LC8_G29
--operation mode is normal

R1L7 = reg_sel[1] & (N1L401 # reg_sel[0]) # !reg_sel[1] & H1_offset[7] & (!reg_sel[0]);

--R1L93 is reg_out:inst33|Mux~623 at LC8_G29
--operation mode is normal

R1L93 = reg_sel[1] & (N1L401 # reg_sel[0]) # !reg_sel[1] & H1_offset[7] & (!reg_sel[0]);


--R1L8 is reg_out:inst33|Mux~592 at LC7_G29
--operation mode is normal

R1L8 = R1L7 & (B1L331 # !reg_sel[0]) # !R1L7 & (reg_sel[0] & N1L551);

--R1L04 is reg_out:inst33|Mux~624 at LC7_G29
--operation mode is normal

R1L04 = R1L7 & (B1L331 # !reg_sel[0]) # !R1L7 & (reg_sel[0] & N1L551);


--R1L751 is reg_out:inst33|reg_data[13]~2843 at LC7_H26
--operation mode is normal

R1L751 = (R1L8 & !R1L571 & (!R1L461 # !C1_q[13]) # !R1L8 & (!R1L461 # !C1_q[13])) & CASCADE(R1L061);

--R1L161 is reg_out:inst33|reg_data[13]~2888 at LC7_H26
--operation mode is normal

R1L161 = (R1L8 & !R1L571 & (!R1L461 # !C1_q[13]) # !R1L8 & (!R1L461 # !C1_q[13])) & CASCADE(R1L061);


--M1L526 is reg_mux:inst27|reg_out[12]~376 at LC2_E20
--operation mode is normal

M1L526 = reg_sel[1] & (L01_q[12] # reg_sel[2]) # !reg_sel[1] & L8_q[12] & (!reg_sel[2]);

--M1L536 is reg_mux:inst27|reg_out[12]~536 at LC2_E20
--operation mode is normal

M1L536 = reg_sel[1] & (L01_q[12] # reg_sel[2]) # !reg_sel[1] & L8_q[12] & (!reg_sel[2]);


--M1L626 is reg_mux:inst27|reg_out[12]~377 at LC1_E20
--operation mode is normal

M1L626 = M1L526 & (L41_q[12] # !reg_sel[2]) # !M1L526 & (reg_sel[2] & L21_q[12]);

--M1L636 is reg_mux:inst27|reg_out[12]~537 at LC1_E20
--operation mode is normal

M1L636 = M1L526 & (L41_q[12] # !reg_sel[2]) # !M1L526 & (reg_sel[2] & L21_q[12]);


--M1L726 is reg_mux:inst27|reg_out[12]~378 at LC2_E25
--operation mode is normal

M1L726 = reg_sel[1] & (L3_q[12] # reg_sel[2]) # !reg_sel[1] & L1_q[12] & (!reg_sel[2]);

--M1L736 is reg_mux:inst27|reg_out[12]~538 at LC2_E25
--operation mode is normal

M1L736 = reg_sel[1] & (L3_q[12] # reg_sel[2]) # !reg_sel[1] & L1_q[12] & (!reg_sel[2]);


--M1L826 is reg_mux:inst27|reg_out[12]~379 at LC1_E25
--operation mode is normal

M1L826 = M1L726 & (L7_q[12] # !reg_sel[2]) # !M1L726 & (reg_sel[2] & L5_q[12]);

--M1L836 is reg_mux:inst27|reg_out[12]~539 at LC1_E25
--operation mode is normal

M1L836 = M1L726 & (L7_q[12] # !reg_sel[2]) # !M1L726 & (reg_sel[2] & L5_q[12]);


--M1L926 is reg_mux:inst27|reg_out[12]~380 at LC4_E26
--operation mode is normal

M1L926 = reg_sel[1] & (L2_q[12] # reg_sel[2]) # !reg_sel[1] & L61_q[12] & (!reg_sel[2]);

--M1L936 is reg_mux:inst27|reg_out[12]~540 at LC4_E26
--operation mode is normal

M1L936 = reg_sel[1] & (L2_q[12] # reg_sel[2]) # !reg_sel[1] & L61_q[12] & (!reg_sel[2]);


--M1L036 is reg_mux:inst27|reg_out[12]~381 at LC1_E26
--operation mode is normal

M1L036 = M1L926 & (L6_q[12] # !reg_sel[2]) # !M1L926 & (reg_sel[2] & L4_q[12]);

--M1L046 is reg_mux:inst27|reg_out[12]~541 at LC1_E26
--operation mode is normal

M1L046 = M1L926 & (L6_q[12] # !reg_sel[2]) # !M1L926 & (reg_sel[2] & L4_q[12]);


--M1L136 is reg_mux:inst27|reg_out[12]~382 at LC2_E7
--operation mode is normal

M1L136 = reg_sel[0] & (M1L826 # reg_sel[3]) # !reg_sel[0] & M1L036 & (!reg_sel[3]);

--M1L146 is reg_mux:inst27|reg_out[12]~542 at LC2_E7
--operation mode is normal

M1L146 = reg_sel[0] & (M1L826 # reg_sel[3]) # !reg_sel[0] & M1L036 & (!reg_sel[3]);


--M1L236 is reg_mux:inst27|reg_out[12]~383 at LC7_E6
--operation mode is normal

M1L236 = reg_sel[1] & (L11_q[12] # reg_sel[2]) # !reg_sel[1] & L9_q[12] & (!reg_sel[2]);

--M1L246 is reg_mux:inst27|reg_out[12]~543 at LC7_E6
--operation mode is normal

M1L246 = reg_sel[1] & (L11_q[12] # reg_sel[2]) # !reg_sel[1] & L9_q[12] & (!reg_sel[2]);


--M1L336 is reg_mux:inst27|reg_out[12]~384 at LC6_E6
--operation mode is normal

M1L336 = M1L236 & (L51_q[12] # !reg_sel[2]) # !M1L236 & (reg_sel[2] & L31_q[12]);

--M1L346 is reg_mux:inst27|reg_out[12]~544 at LC6_E6
--operation mode is normal

M1L346 = M1L236 & (L51_q[12] # !reg_sel[2]) # !M1L236 & (reg_sel[2] & L31_q[12]);


--M1L436 is reg_mux:inst27|reg_out[12]~385 at LC1_E7
--operation mode is normal

M1L436 = M1L136 & (M1L336 # !reg_sel[3]) # !M1L136 & (reg_sel[3] & M1L626);

--M1L446 is reg_mux:inst27|reg_out[12]~545 at LC1_E7
--operation mode is normal

M1L446 = M1L136 & (M1L336 # !reg_sel[3]) # !M1L136 & (reg_sel[3] & M1L626);


--R1L841 is reg_out:inst33|reg_data[12]~2806 at LC1_E21
--operation mode is normal

R1L841 = R1L271 & (reg_sel[0] & (G1_q[12]) # !reg_sel[0] & K1_q[12]);

--R1L151 is reg_out:inst33|reg_data[12]~2889 at LC1_E21
--operation mode is normal

R1L151 = R1L271 & (reg_sel[0] & (G1_q[12]) # !reg_sel[0] & K1_q[12]);


--R1L941 is reg_out:inst33|reg_data[12]~2807 at LC2_E21
--operation mode is normal

R1L941 = !R1L841 & (sel[1] # sel[0] # !M1L436);

--R1L251 is reg_out:inst33|reg_data[12]~2890 at LC2_E21
--operation mode is normal

R1L251 = !R1L841 & (sel[1] # sel[0] # !M1L436);

--R1L351 is reg_out:inst33|reg_data[12]~2891 at LC2_E21
--operation mode is normal

R1L351 = !R1L841 & (sel[1] # sel[0] # !M1L436);


--C1_q[12] is reg_testa:inst1|q[12] at LC4_E21
--operation mode is normal

C1_q[12]_lut_out = F1_state.s0 & !F1_state.s1;
C1_q[12] = DFFEA(C1_q[12]_lut_out, GLOBAL(clk), reset, , , , );

--C1L52Q is reg_testa:inst1|q[12]~11 at LC4_E21
--operation mode is normal

C1L52Q = C1_q[12];


--R1L9 is reg_out:inst33|Mux~593 at LC5_E21
--operation mode is normal

R1L9 = reg_sel[0] & (N1L351 # reg_sel[1]) # !reg_sel[0] & H1_offset[7] & (!reg_sel[1]);

--R1L14 is reg_out:inst33|Mux~625 at LC5_E21
--operation mode is normal

R1L14 = reg_sel[0] & (N1L351 # reg_sel[1]) # !reg_sel[0] & H1_offset[7] & (!reg_sel[1]);


--R1L01 is reg_out:inst33|Mux~594 at LC6_E21
--operation mode is normal

R1L01 = R1L9 & (B1L321 # !reg_sel[1]) # !R1L9 & (reg_sel[1] & N1L69);

--R1L24 is reg_out:inst33|Mux~626 at LC6_E21
--operation mode is normal

R1L24 = R1L9 & (B1L321 # !reg_sel[1]) # !R1L9 & (reg_sel[1] & N1L69);


--R1L051 is reg_out:inst33|reg_data[12]~2844 at LC3_E21
--operation mode is normal

R1L051 = (R1L01 & !R1L571 & (!R1L461 # !C1_q[12]) # !R1L01 & (!R1L461 # !C1_q[12])) & CASCADE(R1L351);

--R1L451 is reg_out:inst33|reg_data[12]~2892 at LC3_E21
--operation mode is normal

R1L451 = (R1L01 & !R1L571 & (!R1L461 # !C1_q[12]) # !R1L01 & (!R1L461 # !C1_q[12])) & CASCADE(R1L351);


--V6_cs_buffer[13] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC4_G12
--operation mode is arithmetic

V6_cs_buffer[13] = N1L88 $ N1L151 $ V6_cout[12];

--V6L14 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~425 at LC4_G12
--operation mode is arithmetic

V6L14 = N1L88 $ N1L151 $ V6_cout[12];

--V6_cout[13] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] at LC4_G12
--operation mode is arithmetic

V6_cout[13] = CARRY(N1L88 & (V6_cout[12] # !N1L151) # !N1L88 & !N1L151 & V6_cout[12]);


--M1L585 is reg_mux:inst27|reg_out[10]~386 at LC4_D2
--operation mode is normal

M1L585 = reg_sel[2] & (L5_q[10] # reg_sel[3]) # !reg_sel[2] & L1_q[10] & (!reg_sel[3]);

--M1L595 is reg_mux:inst27|reg_out[10]~546 at LC4_D2
--operation mode is normal

M1L595 = reg_sel[2] & (L5_q[10] # reg_sel[3]) # !reg_sel[2] & L1_q[10] & (!reg_sel[3]);


--M1L685 is reg_mux:inst27|reg_out[10]~387 at LC5_D2
--operation mode is normal

M1L685 = M1L585 & (L31_q[10] # !reg_sel[3]) # !M1L585 & (reg_sel[3] & L9_q[10]);

--M1L695 is reg_mux:inst27|reg_out[10]~547 at LC5_D2
--operation mode is normal

M1L695 = M1L585 & (L31_q[10] # !reg_sel[3]) # !M1L585 & (reg_sel[3] & L9_q[10]);


--M1L785 is reg_mux:inst27|reg_out[10]~388 at LC8_D11
--operation mode is normal

M1L785 = reg_sel[2] & (L6_q[10] # reg_sel[3]) # !reg_sel[2] & L2_q[10] & (!reg_sel[3]);

--M1L795 is reg_mux:inst27|reg_out[10]~548 at LC8_D11
--operation mode is normal

M1L795 = reg_sel[2] & (L6_q[10] # reg_sel[3]) # !reg_sel[2] & L2_q[10] & (!reg_sel[3]);


--M1L885 is reg_mux:inst27|reg_out[10]~389 at LC5_D11
--operation mode is normal

M1L885 = M1L785 & (L41_q[10] # !reg_sel[3]) # !M1L785 & (reg_sel[3] & L01_q[10]);

--M1L895 is reg_mux:inst27|reg_out[10]~549 at LC5_D11
--operation mode is normal

M1L895 = M1L785 & (L41_q[10] # !reg_sel[3]) # !M1L785 & (reg_sel[3] & L01_q[10]);


--M1L985 is reg_mux:inst27|reg_out[10]~390 at LC6_D14
--operation mode is normal

M1L985 = reg_sel[2] & (L4_q[10] # reg_sel[3]) # !reg_sel[2] & L61_q[10] & (!reg_sel[3]);

--M1L995 is reg_mux:inst27|reg_out[10]~550 at LC6_D14
--operation mode is normal

M1L995 = reg_sel[2] & (L4_q[10] # reg_sel[3]) # !reg_sel[2] & L61_q[10] & (!reg_sel[3]);


--M1L095 is reg_mux:inst27|reg_out[10]~391 at LC1_D14
--operation mode is normal

M1L095 = M1L985 & (L21_q[10] # !reg_sel[3]) # !M1L985 & (reg_sel[3] & L8_q[10]);

--M1L006 is reg_mux:inst27|reg_out[10]~551 at LC1_D14
--operation mode is normal

M1L006 = M1L985 & (L21_q[10] # !reg_sel[3]) # !M1L985 & (reg_sel[3] & L8_q[10]);


--M1L195 is reg_mux:inst27|reg_out[10]~392 at LC6_D2
--operation mode is normal

M1L195 = reg_sel[1] & (M1L885 # reg_sel[0]) # !reg_sel[1] & M1L095 & (!reg_sel[0]);

--M1L106 is reg_mux:inst27|reg_out[10]~552 at LC6_D2
--operation mode is normal

M1L106 = reg_sel[1] & (M1L885 # reg_sel[0]) # !reg_sel[1] & M1L095 & (!reg_sel[0]);


--M1L295 is reg_mux:inst27|reg_out[10]~393 at LC8_D13
--operation mode is normal

M1L295 = reg_sel[2] & (L7_q[10] # reg_sel[3]) # !reg_sel[2] & L3_q[10] & (!reg_sel[3]);

--M1L206 is reg_mux:inst27|reg_out[10]~553 at LC8_D13
--operation mode is normal

M1L206 = reg_sel[2] & (L7_q[10] # reg_sel[3]) # !reg_sel[2] & L3_q[10] & (!reg_sel[3]);


--M1L395 is reg_mux:inst27|reg_out[10]~394 at LC3_D13
--operation mode is normal

M1L395 = M1L295 & (L51_q[10] # !reg_sel[3]) # !M1L295 & (reg_sel[3] & L11_q[10]);

--M1L306 is reg_mux:inst27|reg_out[10]~554 at LC3_D13
--operation mode is normal

M1L306 = M1L295 & (L51_q[10] # !reg_sel[3]) # !M1L295 & (reg_sel[3] & L11_q[10]);


--M1L495 is reg_mux:inst27|reg_out[10]~395 at LC2_D2
--operation mode is normal

M1L495 = M1L195 & (M1L395 # !reg_sel[0]) # !M1L195 & (reg_sel[0] & M1L685);

--M1L406 is reg_mux:inst27|reg_out[10]~555 at LC2_D2
--operation mode is normal

M1L406 = M1L195 & (M1L395 # !reg_sel[0]) # !M1L195 & (reg_sel[0] & M1L685);


--R1L531 is reg_out:inst33|reg_data[10]~2809 at LC1_D25
--operation mode is normal

R1L531 = R1L271 & (reg_sel[0] & (G1_q[10]) # !reg_sel[0] & K1_q[10]);

--R1L831 is reg_out:inst33|reg_data[10]~2893 at LC1_D25
--operation mode is normal

R1L831 = R1L271 & (reg_sel[0] & (G1_q[10]) # !reg_sel[0] & K1_q[10]);


--R1L631 is reg_out:inst33|reg_data[10]~2810 at LC6_D25
--operation mode is normal

R1L631 = !R1L531 & (sel[1] # sel[0] # !M1L495);

--R1L931 is reg_out:inst33|reg_data[10]~2894 at LC6_D25
--operation mode is normal

R1L931 = !R1L531 & (sel[1] # sel[0] # !M1L495);

--R1L041 is reg_out:inst33|reg_data[10]~2895 at LC6_D25
--operation mode is normal

R1L041 = !R1L531 & (sel[1] # sel[0] # !M1L495);


--C1_q[10] is reg_testa:inst1|q[10] at LC2_D25
--operation mode is normal

C1_q[10]_lut_out = H1_alu_func[2];
C1_q[10] = DFFEA(C1_q[10]_lut_out, GLOBAL(clk), reset, , , , );

--C1L32Q is reg_testa:inst1|q[10]~12 at LC2_D25
--operation mode is normal

C1L32Q = C1_q[10];


--R1L11 is reg_out:inst33|Mux~595 at LC4_D25
--operation mode is normal

R1L11 = reg_sel[0] & (N1L941 # reg_sel[1]) # !reg_sel[0] & H1_offset[7] & (!reg_sel[1]);

--R1L34 is reg_out:inst33|Mux~627 at LC4_D25
--operation mode is normal

R1L34 = reg_sel[0] & (N1L941 # reg_sel[1]) # !reg_sel[0] & H1_offset[7] & (!reg_sel[1]);


--R1L21 is reg_out:inst33|Mux~596 at LC5_D25
--operation mode is normal

R1L21 = R1L11 & (B1L301 # !reg_sel[1]) # !R1L11 & (reg_sel[1] & N1L08);

--R1L44 is reg_out:inst33|Mux~628 at LC5_D25
--operation mode is normal

R1L44 = R1L11 & (B1L301 # !reg_sel[1]) # !R1L11 & (reg_sel[1] & N1L08);


--R1L731 is reg_out:inst33|reg_data[10]~2845 at LC7_D25
--operation mode is normal

R1L731 = (R1L21 & !R1L571 & (!R1L461 # !C1_q[10]) # !R1L21 & (!R1L461 # !C1_q[10])) & CASCADE(R1L041);

--R1L141 is reg_out:inst33|reg_data[10]~2896 at LC7_D25
--operation mode is normal

R1L141 = (R1L21 & !R1L571 & (!R1L461 # !C1_q[10]) # !R1L21 & (!R1L461 # !C1_q[10])) & CASCADE(R1L041);


--M1L565 is reg_mux:inst27|reg_out[9]~396 at LC5_H48
--operation mode is normal

M1L565 = reg_sel[1] & (L01_q[9] # reg_sel[0]) # !reg_sel[1] & L8_q[9] & (!reg_sel[0]);

--M1L575 is reg_mux:inst27|reg_out[9]~556 at LC5_H48
--operation mode is normal

M1L575 = reg_sel[1] & (L01_q[9] # reg_sel[0]) # !reg_sel[1] & L8_q[9] & (!reg_sel[0]);


--M1L665 is reg_mux:inst27|reg_out[9]~397 at LC7_H48
--operation mode is normal

M1L665 = M1L565 & (L11_q[9] # !reg_sel[0]) # !M1L565 & (reg_sel[0] & L9_q[9]);

--M1L675 is reg_mux:inst27|reg_out[9]~557 at LC7_H48
--operation mode is normal

M1L675 = M1L565 & (L11_q[9] # !reg_sel[0]) # !M1L565 & (reg_sel[0] & L9_q[9]);


--M1L765 is reg_mux:inst27|reg_out[9]~398 at LC8_H36
--operation mode is normal

M1L765 = reg_sel[1] & (L6_q[9] # reg_sel[0]) # !reg_sel[1] & L4_q[9] & (!reg_sel[0]);

--M1L775 is reg_mux:inst27|reg_out[9]~558 at LC8_H36
--operation mode is normal

M1L775 = reg_sel[1] & (L6_q[9] # reg_sel[0]) # !reg_sel[1] & L4_q[9] & (!reg_sel[0]);


--M1L865 is reg_mux:inst27|reg_out[9]~399 at LC7_H36
--operation mode is normal

M1L865 = M1L765 & (L7_q[9] # !reg_sel[0]) # !M1L765 & (reg_sel[0] & L5_q[9]);

--M1L875 is reg_mux:inst27|reg_out[9]~559 at LC7_H36
--operation mode is normal

M1L875 = M1L765 & (L7_q[9] # !reg_sel[0]) # !M1L765 & (reg_sel[0] & L5_q[9]);


--M1L965 is reg_mux:inst27|reg_out[9]~400 at LC8_H33
--operation mode is normal

M1L965 = reg_sel[1] & (L2_q[9] # reg_sel[0]) # !reg_sel[1] & L61_q[9] & (!reg_sel[0]);

--M1L975 is reg_mux:inst27|reg_out[9]~560 at LC8_H33
--operation mode is normal

M1L975 = reg_sel[1] & (L2_q[9] # reg_sel[0]) # !reg_sel[1] & L61_q[9] & (!reg_sel[0]);


--M1L075 is reg_mux:inst27|reg_out[9]~401 at LC5_H33
--operation mode is normal

M1L075 = M1L965 & (L3_q[9] # !reg_sel[0]) # !M1L965 & (reg_sel[0] & L1_q[9]);

--M1L085 is reg_mux:inst27|reg_out[9]~561 at LC5_H33
--operation mode is normal

M1L085 = M1L965 & (L3_q[9] # !reg_sel[0]) # !M1L965 & (reg_sel[0] & L1_q[9]);


--M1L175 is reg_mux:inst27|reg_out[9]~402 at LC1_F19
--operation mode is normal

M1L175 = reg_sel[2] & (M1L865 # reg_sel[3]) # !reg_sel[2] & M1L075 & (!reg_sel[3]);

--M1L185 is reg_mux:inst27|reg_out[9]~562 at LC1_F19
--operation mode is normal

M1L185 = reg_sel[2] & (M1L865 # reg_sel[3]) # !reg_sel[2] & M1L075 & (!reg_sel[3]);


--M1L275 is reg_mux:inst27|reg_out[9]~403 at LC7_H35
--operation mode is normal

M1L275 = reg_sel[1] & (L41_q[9] # reg_sel[0]) # !reg_sel[1] & L21_q[9] & (!reg_sel[0]);

--M1L285 is reg_mux:inst27|reg_out[9]~563 at LC7_H35
--operation mode is normal

M1L285 = reg_sel[1] & (L41_q[9] # reg_sel[0]) # !reg_sel[1] & L21_q[9] & (!reg_sel[0]);


--M1L375 is reg_mux:inst27|reg_out[9]~404 at LC8_H35
--operation mode is normal

M1L375 = M1L275 & (L51_q[9] # !reg_sel[0]) # !M1L275 & (reg_sel[0] & L31_q[9]);

--M1L385 is reg_mux:inst27|reg_out[9]~564 at LC8_H35
--operation mode is normal

M1L385 = M1L275 & (L51_q[9] # !reg_sel[0]) # !M1L275 & (reg_sel[0] & L31_q[9]);


--M1L475 is reg_mux:inst27|reg_out[9]~405 at LC2_F19
--operation mode is normal

M1L475 = M1L175 & (M1L375 # !reg_sel[3]) # !M1L175 & (reg_sel[3] & M1L665);

--M1L485 is reg_mux:inst27|reg_out[9]~565 at LC2_F19
--operation mode is normal

M1L485 = M1L175 & (M1L375 # !reg_sel[3]) # !M1L175 & (reg_sel[3] & M1L665);


--R1L821 is reg_out:inst33|reg_data[9]~2812 at LC4_F19
--operation mode is normal

R1L821 = R1L271 & (reg_sel[0] & (G1_q[9]) # !reg_sel[0] & K1_q[9]);

--R1L131 is reg_out:inst33|reg_data[9]~2897 at LC4_F19
--operation mode is normal

R1L131 = R1L271 & (reg_sel[0] & (G1_q[9]) # !reg_sel[0] & K1_q[9]);


--R1L921 is reg_out:inst33|reg_data[9]~2813 at LC8_F19
--operation mode is normal

R1L921 = !R1L821 & (sel[1] # sel[0] # !M1L475);

--R1L231 is reg_out:inst33|reg_data[9]~2898 at LC8_F19
--operation mode is normal

R1L231 = !R1L821 & (sel[1] # sel[0] # !M1L475);

--R1L331 is reg_out:inst33|reg_data[9]~2899 at LC8_F19
--operation mode is normal

R1L331 = !R1L821 & (sel[1] # sel[0] # !M1L475);


--C1_q[9] is reg_testa:inst1|q[9] at LC7_F21
--operation mode is normal

C1_q[9]_lut_out = H1_alu_func[1];
C1_q[9] = DFFEA(C1_q[9]_lut_out, GLOBAL(clk), reset, , , , );

--C1L12Q is reg_testa:inst1|q[9]~13 at LC7_F21
--operation mode is normal

C1L12Q = C1_q[9];


--R1L31 is reg_out:inst33|Mux~597 at LC5_F8
--operation mode is normal

R1L31 = reg_sel[1] & (N1L27 # reg_sel[0]) # !reg_sel[1] & H1_offset[7] & (!reg_sel[0]);

--R1L54 is reg_out:inst33|Mux~629 at LC5_F8
--operation mode is normal

R1L54 = reg_sel[1] & (N1L27 # reg_sel[0]) # !reg_sel[1] & H1_offset[7] & (!reg_sel[0]);


--R1L41 is reg_out:inst33|Mux~598 at LC8_F21
--operation mode is normal

R1L41 = R1L31 & (B1L39 # !reg_sel[0]) # !R1L31 & (reg_sel[0] & N1L741);

--R1L64 is reg_out:inst33|Mux~630 at LC8_F21
--operation mode is normal

R1L64 = R1L31 & (B1L39 # !reg_sel[0]) # !R1L31 & (reg_sel[0] & N1L741);


--R1L031 is reg_out:inst33|reg_data[9]~2846 at LC1_F21
--operation mode is normal

R1L031 = (R1L41 & !R1L571 & (!R1L461 # !C1_q[9]) # !R1L41 & (!R1L461 # !C1_q[9])) & CASCADE(R1L331);

--R1L431 is reg_out:inst33|reg_data[9]~2900 at LC1_F21
--operation mode is normal

R1L431 = (R1L41 & !R1L571 & (!R1L461 # !C1_q[9]) # !R1L41 & (!R1L461 # !C1_q[9])) & CASCADE(R1L331);


--M1L545 is reg_mux:inst27|reg_out[8]~406 at LC7_H30
--operation mode is normal

M1L545 = reg_sel[2] & (L5_q[8] # reg_sel[3]) # !reg_sel[2] & L1_q[8] & (!reg_sel[3]);

--M1L555 is reg_mux:inst27|reg_out[8]~566 at LC7_H30
--operation mode is normal

M1L555 = reg_sel[2] & (L5_q[8] # reg_sel[3]) # !reg_sel[2] & L1_q[8] & (!reg_sel[3]);


--M1L645 is reg_mux:inst27|reg_out[8]~407 at LC5_H30
--operation mode is normal

M1L645 = M1L545 & (L31_q[8] # !reg_sel[3]) # !M1L545 & (reg_sel[3] & L9_q[8]);

--M1L655 is reg_mux:inst27|reg_out[8]~567 at LC5_H30
--operation mode is normal

M1L655 = M1L545 & (L31_q[8] # !reg_sel[3]) # !M1L545 & (reg_sel[3] & L9_q[8]);


--M1L745 is reg_mux:inst27|reg_out[8]~408 at LC8_H43
--operation mode is normal

M1L745 = reg_sel[2] & (L6_q[8] # reg_sel[3]) # !reg_sel[2] & L2_q[8] & (!reg_sel[3]);

--M1L755 is reg_mux:inst27|reg_out[8]~568 at LC8_H43
--operation mode is normal

M1L755 = reg_sel[2] & (L6_q[8] # reg_sel[3]) # !reg_sel[2] & L2_q[8] & (!reg_sel[3]);


--M1L845 is reg_mux:inst27|reg_out[8]~409 at LC2_H43
--operation mode is normal

M1L845 = M1L745 & (L41_q[8] # !reg_sel[3]) # !M1L745 & (reg_sel[3] & L01_q[8]);

--M1L855 is reg_mux:inst27|reg_out[8]~569 at LC2_H43
--operation mode is normal

M1L855 = M1L745 & (L41_q[8] # !reg_sel[3]) # !M1L745 & (reg_sel[3] & L01_q[8]);


--M1L945 is reg_mux:inst27|reg_out[8]~410 at LC8_H28
--operation mode is normal

M1L945 = reg_sel[2] & (L4_q[8] # reg_sel[3]) # !reg_sel[2] & L61_q[8] & (!reg_sel[3]);

--M1L955 is reg_mux:inst27|reg_out[8]~570 at LC8_H28
--operation mode is normal

M1L955 = reg_sel[2] & (L4_q[8] # reg_sel[3]) # !reg_sel[2] & L61_q[8] & (!reg_sel[3]);


--M1L055 is reg_mux:inst27|reg_out[8]~411 at LC3_H28
--operation mode is normal

M1L055 = M1L945 & (L21_q[8] # !reg_sel[3]) # !M1L945 & (reg_sel[3] & L8_q[8]);

--M1L065 is reg_mux:inst27|reg_out[8]~571 at LC3_H28
--operation mode is normal

M1L065 = M1L945 & (L21_q[8] # !reg_sel[3]) # !M1L945 & (reg_sel[3] & L8_q[8]);


--M1L155 is reg_mux:inst27|reg_out[8]~412 at LC1_G35
--operation mode is normal

M1L155 = reg_sel[1] & (M1L845 # reg_sel[0]) # !reg_sel[1] & M1L055 & (!reg_sel[0]);

--M1L165 is reg_mux:inst27|reg_out[8]~572 at LC1_G35
--operation mode is normal

M1L165 = reg_sel[1] & (M1L845 # reg_sel[0]) # !reg_sel[1] & M1L055 & (!reg_sel[0]);


--M1L255 is reg_mux:inst27|reg_out[8]~413 at LC6_H31
--operation mode is normal

M1L255 = reg_sel[2] & (L7_q[8] # reg_sel[3]) # !reg_sel[2] & L3_q[8] & (!reg_sel[3]);

--M1L265 is reg_mux:inst27|reg_out[8]~573 at LC6_H31
--operation mode is normal

M1L265 = reg_sel[2] & (L7_q[8] # reg_sel[3]) # !reg_sel[2] & L3_q[8] & (!reg_sel[3]);


--M1L355 is reg_mux:inst27|reg_out[8]~414 at LC3_H31
--operation mode is normal

M1L355 = M1L255 & (L51_q[8] # !reg_sel[3]) # !M1L255 & (reg_sel[3] & L11_q[8]);

--M1L365 is reg_mux:inst27|reg_out[8]~574 at LC3_H31
--operation mode is normal

M1L365 = M1L255 & (L51_q[8] # !reg_sel[3]) # !M1L255 & (reg_sel[3] & L11_q[8]);


--M1L455 is reg_mux:inst27|reg_out[8]~415 at LC2_G35
--operation mode is normal

M1L455 = M1L155 & (M1L355 # !reg_sel[0]) # !M1L155 & (reg_sel[0] & M1L645);

--M1L465 is reg_mux:inst27|reg_out[8]~575 at LC2_G35
--operation mode is normal

M1L465 = M1L155 & (M1L355 # !reg_sel[0]) # !M1L155 & (reg_sel[0] & M1L645);


--R1L121 is reg_out:inst33|reg_data[8]~2815 at LC3_G35
--operation mode is normal

R1L121 = R1L271 & (reg_sel[0] & (G1_q[8]) # !reg_sel[0] & K1_q[8]);

--R1L421 is reg_out:inst33|reg_data[8]~2901 at LC3_G35
--operation mode is normal

R1L421 = R1L271 & (reg_sel[0] & (G1_q[8]) # !reg_sel[0] & K1_q[8]);


--R1L221 is reg_out:inst33|reg_data[8]~2816 at LC4_G35
--operation mode is normal

R1L221 = !R1L121 & (sel[1] # sel[0] # !M1L455);

--R1L521 is reg_out:inst33|reg_data[8]~2902 at LC4_G35
--operation mode is normal

R1L521 = !R1L121 & (sel[1] # sel[0] # !M1L455);

--R1L621 is reg_out:inst33|reg_data[8]~2903 at LC4_G35
--operation mode is normal

R1L621 = !R1L121 & (sel[1] # sel[0] # !M1L455);


--C1_q[8] is reg_testa:inst1|q[8] at LC6_G35
--operation mode is normal

C1_q[8]_lut_out = H1_alu_func[0];
C1_q[8] = DFFEA(C1_q[8]_lut_out, GLOBAL(clk), reset, , , , );

--C1L91Q is reg_testa:inst1|q[8]~14 at LC6_G35
--operation mode is normal

C1L91Q = C1_q[8];


--R1L51 is reg_out:inst33|Mux~599 at LC4_F8
--operation mode is normal

R1L51 = reg_sel[0] & (N1L541 # reg_sel[1]) # !reg_sel[0] & H1_offset[7] & (!reg_sel[1]);

--R1L74 is reg_out:inst33|Mux~631 at LC4_F8
--operation mode is normal

R1L74 = reg_sel[0] & (N1L541 # reg_sel[1]) # !reg_sel[0] & H1_offset[7] & (!reg_sel[1]);


--R1L61 is reg_out:inst33|Mux~600 at LC6_F8
--operation mode is normal

R1L61 = R1L51 & (B1L38 # !reg_sel[1]) # !R1L51 & (reg_sel[1] & N1L46);

--R1L84 is reg_out:inst33|Mux~632 at LC6_F8
--operation mode is normal

R1L84 = R1L51 & (B1L38 # !reg_sel[1]) # !R1L51 & (reg_sel[1] & N1L46);


--R1L321 is reg_out:inst33|reg_data[8]~2847 at LC5_G35
--operation mode is normal

R1L321 = (R1L61 & !R1L571 & (!R1L461 # !C1_q[8]) # !R1L61 & (!R1L461 # !C1_q[8])) & CASCADE(R1L621);

--R1L721 is reg_out:inst33|reg_data[8]~2904 at LC5_G35
--operation mode is normal

R1L721 = (R1L61 & !R1L571 & (!R1L461 # !C1_q[8]) # !R1L61 & (!R1L461 # !C1_q[8])) & CASCADE(R1L621);


--M1L525 is reg_mux:inst27|reg_out[7]~416 at LC3_I14
--operation mode is normal

M1L525 = reg_sel[1] & (L01_q[7] # reg_sel[0]) # !reg_sel[1] & L8_q[7] & (!reg_sel[0]);

--M1L535 is reg_mux:inst27|reg_out[7]~576 at LC3_I14
--operation mode is normal

M1L535 = reg_sel[1] & (L01_q[7] # reg_sel[0]) # !reg_sel[1] & L8_q[7] & (!reg_sel[0]);


--M1L625 is reg_mux:inst27|reg_out[7]~417 at LC1_I20
--operation mode is normal

M1L625 = M1L525 & (L11_q[7] # !reg_sel[0]) # !M1L525 & (reg_sel[0] & L9_q[7]);

--M1L635 is reg_mux:inst27|reg_out[7]~577 at LC1_I20
--operation mode is normal

M1L635 = M1L525 & (L11_q[7] # !reg_sel[0]) # !M1L525 & (reg_sel[0] & L9_q[7]);


--M1L725 is reg_mux:inst27|reg_out[7]~418 at LC3_I16
--operation mode is normal

M1L725 = reg_sel[1] & (L6_q[7] # reg_sel[0]) # !reg_sel[1] & L4_q[7] & (!reg_sel[0]);

--M1L735 is reg_mux:inst27|reg_out[7]~578 at LC3_I16
--operation mode is normal

M1L735 = reg_sel[1] & (L6_q[7] # reg_sel[0]) # !reg_sel[1] & L4_q[7] & (!reg_sel[0]);


--M1L825 is reg_mux:inst27|reg_out[7]~419 at LC2_I16
--operation mode is normal

M1L825 = M1L725 & (L7_q[7] # !reg_sel[0]) # !M1L725 & (reg_sel[0] & L5_q[7]);

--M1L835 is reg_mux:inst27|reg_out[7]~579 at LC2_I16
--operation mode is normal

M1L835 = M1L725 & (L7_q[7] # !reg_sel[0]) # !M1L725 & (reg_sel[0] & L5_q[7]);


--M1L925 is reg_mux:inst27|reg_out[7]~420 at LC8_I10
--operation mode is normal

M1L925 = reg_sel[1] & (L2_q[7] # reg_sel[0]) # !reg_sel[1] & L61_q[7] & (!reg_sel[0]);

--M1L935 is reg_mux:inst27|reg_out[7]~580 at LC8_I10
--operation mode is normal

M1L935 = reg_sel[1] & (L2_q[7] # reg_sel[0]) # !reg_sel[1] & L61_q[7] & (!reg_sel[0]);


--M1L035 is reg_mux:inst27|reg_out[7]~421 at LC2_I10
--operation mode is normal

M1L035 = M1L925 & (L3_q[7] # !reg_sel[0]) # !M1L925 & (reg_sel[0] & L1_q[7]);

--M1L045 is reg_mux:inst27|reg_out[7]~581 at LC2_I10
--operation mode is normal

M1L045 = M1L925 & (L3_q[7] # !reg_sel[0]) # !M1L925 & (reg_sel[0] & L1_q[7]);


--M1L135 is reg_mux:inst27|reg_out[7]~422 at LC2_I20
--operation mode is normal

M1L135 = reg_sel[2] & (M1L825 # reg_sel[3]) # !reg_sel[2] & M1L035 & (!reg_sel[3]);

--M1L145 is reg_mux:inst27|reg_out[7]~582 at LC2_I20
--operation mode is normal

M1L145 = reg_sel[2] & (M1L825 # reg_sel[3]) # !reg_sel[2] & M1L035 & (!reg_sel[3]);


--M1L235 is reg_mux:inst27|reg_out[7]~423 at LC8_I17
--operation mode is normal

M1L235 = reg_sel[1] & (L41_q[7] # reg_sel[0]) # !reg_sel[1] & L21_q[7] & (!reg_sel[0]);

--M1L245 is reg_mux:inst27|reg_out[7]~583 at LC8_I17
--operation mode is normal

M1L245 = reg_sel[1] & (L41_q[7] # reg_sel[0]) # !reg_sel[1] & L21_q[7] & (!reg_sel[0]);


--M1L335 is reg_mux:inst27|reg_out[7]~424 at LC3_I17
--operation mode is normal

M1L335 = M1L235 & (L51_q[7] # !reg_sel[0]) # !M1L235 & (reg_sel[0] & L31_q[7]);

--M1L345 is reg_mux:inst27|reg_out[7]~584 at LC3_I17
--operation mode is normal

M1L345 = M1L235 & (L51_q[7] # !reg_sel[0]) # !M1L235 & (reg_sel[0] & L31_q[7]);


--M1L435 is reg_mux:inst27|reg_out[7]~425 at LC4_I20
--operation mode is normal

M1L435 = M1L135 & (M1L335 # !reg_sel[3]) # !M1L135 & (reg_sel[3] & M1L625);

--M1L445 is reg_mux:inst27|reg_out[7]~585 at LC4_I20
--operation mode is normal

M1L445 = M1L135 & (M1L335 # !reg_sel[3]) # !M1L135 & (reg_sel[3] & M1L625);


--R1L411 is reg_out:inst33|reg_data[7]~2818 at LC5_I20
--operation mode is normal

R1L411 = R1L271 & (reg_sel[0] & (G1_q[7]) # !reg_sel[0] & K1_q[7]);

--R1L711 is reg_out:inst33|reg_data[7]~2905 at LC5_I20
--operation mode is normal

R1L711 = R1L271 & (reg_sel[0] & (G1_q[7]) # !reg_sel[0] & K1_q[7]);


--R1L511 is reg_out:inst33|reg_data[7]~2819 at LC8_I20
--operation mode is normal

R1L511 = !R1L411 & (sel[1] # sel[0] # !M1L435);

--R1L811 is reg_out:inst33|reg_data[7]~2906 at LC8_I20
--operation mode is normal

R1L811 = !R1L411 & (sel[1] # sel[0] # !M1L435);

--R1L911 is reg_out:inst33|reg_data[7]~2907 at LC8_I20
--operation mode is normal

R1L911 = !R1L411 & (sel[1] # sel[0] # !M1L435);


--C1_q[7] is reg_testa:inst1|q[7] at LC8_G43
--operation mode is normal

C1_q[7]_lut_out = H1_sci[0] & (!H1_sci[1]) # !H1_sci[0] & D1_flag_c & H1_sci[1];
C1_q[7] = DFFEA(C1_q[7]_lut_out, GLOBAL(clk), reset, , , , );

--C1L71Q is reg_testa:inst1|q[7]~15 at LC8_G43
--operation mode is normal

C1L71Q = C1_q[7];


--R1L71 is reg_out:inst33|Mux~601 at LC7_I22
--operation mode is normal

R1L71 = reg_sel[1] & (N1L65 # reg_sel[0]) # !reg_sel[1] & H1_offset[7] & (!reg_sel[0]);

--R1L94 is reg_out:inst33|Mux~633 at LC7_I22
--operation mode is normal

R1L94 = reg_sel[1] & (N1L65 # reg_sel[0]) # !reg_sel[1] & H1_offset[7] & (!reg_sel[0]);


--R1L81 is reg_out:inst33|Mux~602 at LC8_I22
--operation mode is normal

R1L81 = R1L71 & (B1L37 # !reg_sel[0]) # !R1L71 & (reg_sel[0] & N1L341);

--R1L05 is reg_out:inst33|Mux~634 at LC8_I22
--operation mode is normal

R1L05 = R1L71 & (B1L37 # !reg_sel[0]) # !R1L71 & (reg_sel[0] & N1L341);


--R1L611 is reg_out:inst33|reg_data[7]~2848 at LC1_I22
--operation mode is normal

R1L611 = (R1L81 & !R1L571 & (!R1L461 # !C1_q[7]) # !R1L81 & (!R1L461 # !C1_q[7])) & CASCADE(R1L911);

--R1L021 is reg_out:inst33|reg_data[7]~2908 at LC1_I22
--operation mode is normal

R1L021 = (R1L81 & !R1L571 & (!R1L461 # !C1_q[7]) # !R1L81 & (!R1L461 # !C1_q[7])) & CASCADE(R1L911);


--M1L505 is reg_mux:inst27|reg_out[6]~426 at LC7_B16
--operation mode is normal

M1L505 = reg_sel[2] & (L5_q[6] # reg_sel[3]) # !reg_sel[2] & L1_q[6] & (!reg_sel[3]);

--M1L515 is reg_mux:inst27|reg_out[6]~586 at LC7_B16
--operation mode is normal

M1L515 = reg_sel[2] & (L5_q[6] # reg_sel[3]) # !reg_sel[2] & L1_q[6] & (!reg_sel[3]);


--M1L605 is reg_mux:inst27|reg_out[6]~427 at LC2_B16
--operation mode is normal

M1L605 = M1L505 & (L31_q[6] # !reg_sel[3]) # !M1L505 & (reg_sel[3] & L9_q[6]);

--M1L615 is reg_mux:inst27|reg_out[6]~587 at LC2_B16
--operation mode is normal

M1L615 = M1L505 & (L31_q[6] # !reg_sel[3]) # !M1L505 & (reg_sel[3] & L9_q[6]);


--M1L705 is reg_mux:inst27|reg_out[6]~428 at LC8_B13
--operation mode is normal

M1L705 = reg_sel[2] & (L6_q[6] # reg_sel[3]) # !reg_sel[2] & L2_q[6] & (!reg_sel[3]);

--M1L715 is reg_mux:inst27|reg_out[6]~588 at LC8_B13
--operation mode is normal

M1L715 = reg_sel[2] & (L6_q[6] # reg_sel[3]) # !reg_sel[2] & L2_q[6] & (!reg_sel[3]);


--M1L805 is reg_mux:inst27|reg_out[6]~429 at LC2_B13
--operation mode is normal

M1L805 = M1L705 & (L41_q[6] # !reg_sel[3]) # !M1L705 & (reg_sel[3] & L01_q[6]);

--M1L815 is reg_mux:inst27|reg_out[6]~589 at LC2_B13
--operation mode is normal

M1L815 = M1L705 & (L41_q[6] # !reg_sel[3]) # !M1L705 & (reg_sel[3] & L01_q[6]);


--M1L905 is reg_mux:inst27|reg_out[6]~430 at LC7_B14
--operation mode is normal

M1L905 = reg_sel[2] & (L4_q[6] # reg_sel[3]) # !reg_sel[2] & L61_q[6] & (!reg_sel[3]);

--M1L915 is reg_mux:inst27|reg_out[6]~590 at LC7_B14
--operation mode is normal

M1L915 = reg_sel[2] & (L4_q[6] # reg_sel[3]) # !reg_sel[2] & L61_q[6] & (!reg_sel[3]);


--M1L015 is reg_mux:inst27|reg_out[6]~431 at LC3_B14
--operation mode is normal

M1L015 = M1L905 & (L21_q[6] # !reg_sel[3]) # !M1L905 & (reg_sel[3] & L8_q[6]);

--M1L025 is reg_mux:inst27|reg_out[6]~591 at LC3_B14
--operation mode is normal

M1L025 = M1L905 & (L21_q[6] # !reg_sel[3]) # !M1L905 & (reg_sel[3] & L8_q[6]);


--M1L115 is reg_mux:inst27|reg_out[6]~432 at LC1_B15
--operation mode is normal

M1L115 = reg_sel[1] & (M1L805 # reg_sel[0]) # !reg_sel[1] & M1L015 & (!reg_sel[0]);

--M1L125 is reg_mux:inst27|reg_out[6]~592 at LC1_B15
--operation mode is normal

M1L125 = reg_sel[1] & (M1L805 # reg_sel[0]) # !reg_sel[1] & M1L015 & (!reg_sel[0]);


--M1L215 is reg_mux:inst27|reg_out[6]~433 at LC8_B10
--operation mode is normal

M1L215 = reg_sel[2] & (L7_q[6] # reg_sel[3]) # !reg_sel[2] & L3_q[6] & (!reg_sel[3]);

--M1L225 is reg_mux:inst27|reg_out[6]~593 at LC8_B10
--operation mode is normal

M1L225 = reg_sel[2] & (L7_q[6] # reg_sel[3]) # !reg_sel[2] & L3_q[6] & (!reg_sel[3]);


--M1L315 is reg_mux:inst27|reg_out[6]~434 at LC3_B10
--operation mode is normal

M1L315 = M1L215 & (L51_q[6] # !reg_sel[3]) # !M1L215 & (reg_sel[3] & L11_q[6]);

--M1L325 is reg_mux:inst27|reg_out[6]~594 at LC3_B10
--operation mode is normal

M1L325 = M1L215 & (L51_q[6] # !reg_sel[3]) # !M1L215 & (reg_sel[3] & L11_q[6]);


--M1L415 is reg_mux:inst27|reg_out[6]~435 at LC2_B15
--operation mode is normal

M1L415 = M1L115 & (M1L315 # !reg_sel[0]) # !M1L115 & (reg_sel[0] & M1L605);

--M1L425 is reg_mux:inst27|reg_out[6]~595 at LC2_B15
--operation mode is normal

M1L425 = M1L115 & (M1L315 # !reg_sel[0]) # !M1L115 & (reg_sel[0] & M1L605);


--R1L701 is reg_out:inst33|reg_data[6]~2821 at LC3_B15
--operation mode is normal

R1L701 = R1L271 & (reg_sel[0] & (G1_q[6]) # !reg_sel[0] & K1_q[6]);

--R1L011 is reg_out:inst33|reg_data[6]~2909 at LC3_B15
--operation mode is normal

R1L011 = R1L271 & (reg_sel[0] & (G1_q[6]) # !reg_sel[0] & K1_q[6]);


--R1L801 is reg_out:inst33|reg_data[6]~2822 at LC4_B15
--operation mode is normal

R1L801 = !R1L701 & (sel[1] # sel[0] # !M1L415);

--R1L111 is reg_out:inst33|reg_data[6]~2910 at LC4_B15
--operation mode is normal

R1L111 = !R1L701 & (sel[1] # sel[0] # !M1L415);

--R1L211 is reg_out:inst33|reg_data[6]~2911 at LC4_B15
--operation mode is normal

R1L211 = !R1L701 & (sel[1] # sel[0] # !M1L415);


--C1_q[6] is reg_testa:inst1|q[6] at LC6_B15
--operation mode is normal

C1_q[6]_lut_out = H1_alu_in_sel[2];
C1_q[6] = DFFEA(C1_q[6]_lut_out, GLOBAL(clk), reset, , , , );

--C1L51Q is reg_testa:inst1|q[6]~16 at LC6_B15
--operation mode is normal

C1L51Q = C1_q[6];


--R1L91 is reg_out:inst33|Mux~603 at LC2_G1
--operation mode is normal

R1L91 = reg_sel[0] & (N1L141 # reg_sel[1]) # !reg_sel[0] & H1_offset[6] & (!reg_sel[1]);

--R1L15 is reg_out:inst33|Mux~635 at LC2_G1
--operation mode is normal

R1L15 = reg_sel[0] & (N1L141 # reg_sel[1]) # !reg_sel[0] & H1_offset[6] & (!reg_sel[1]);


--R1L02 is reg_out:inst33|Mux~604 at LC1_G1
--operation mode is normal

R1L02 = R1L91 & (B1L36 # !reg_sel[1]) # !R1L91 & (reg_sel[1] & N1L84);

--R1L25 is reg_out:inst33|Mux~636 at LC1_G1
--operation mode is normal

R1L25 = R1L91 & (B1L36 # !reg_sel[1]) # !R1L91 & (reg_sel[1] & N1L84);


--R1L901 is reg_out:inst33|reg_data[6]~2849 at LC5_B15
--operation mode is normal

R1L901 = (R1L02 & !R1L571 & (!R1L461 # !C1_q[6]) # !R1L02 & (!R1L461 # !C1_q[6])) & CASCADE(R1L211);

--R1L311 is reg_out:inst33|reg_data[6]~2912 at LC5_B15
--operation mode is normal

R1L311 = (R1L02 & !R1L571 & (!R1L461 # !C1_q[6]) # !R1L02 & (!R1L461 # !C1_q[6])) & CASCADE(R1L211);


--M1L584 is reg_mux:inst27|reg_out[5]~436 at LC2_G22
--operation mode is normal

M1L584 = reg_sel[1] & (L01_q[5] # reg_sel[0]) # !reg_sel[1] & L8_q[5] & (!reg_sel[0]);

--M1L594 is reg_mux:inst27|reg_out[5]~596 at LC2_G22
--operation mode is normal

M1L594 = reg_sel[1] & (L01_q[5] # reg_sel[0]) # !reg_sel[1] & L8_q[5] & (!reg_sel[0]);


--M1L684 is reg_mux:inst27|reg_out[5]~437 at LC5_G22
--operation mode is normal

M1L684 = M1L584 & (L11_q[5] # !reg_sel[0]) # !M1L584 & (reg_sel[0] & L9_q[5]);

--M1L694 is reg_mux:inst27|reg_out[5]~597 at LC5_G22
--operation mode is normal

M1L694 = M1L584 & (L11_q[5] # !reg_sel[0]) # !M1L584 & (reg_sel[0] & L9_q[5]);


--M1L784 is reg_mux:inst27|reg_out[5]~438 at LC7_G5
--operation mode is normal

M1L784 = reg_sel[1] & (L6_q[5] # reg_sel[0]) # !reg_sel[1] & L4_q[5] & (!reg_sel[0]);

--M1L794 is reg_mux:inst27|reg_out[5]~598 at LC7_G5
--operation mode is normal

M1L794 = reg_sel[1] & (L6_q[5] # reg_sel[0]) # !reg_sel[1] & L4_q[5] & (!reg_sel[0]);


--M1L884 is reg_mux:inst27|reg_out[5]~439 at LC6_G5
--operation mode is normal

M1L884 = M1L784 & (L7_q[5] # !reg_sel[0]) # !M1L784 & (reg_sel[0] & L5_q[5]);

--M1L894 is reg_mux:inst27|reg_out[5]~599 at LC6_G5
--operation mode is normal

M1L894 = M1L784 & (L7_q[5] # !reg_sel[0]) # !M1L784 & (reg_sel[0] & L5_q[5]);


--M1L984 is reg_mux:inst27|reg_out[5]~440 at LC8_G9
--operation mode is normal

M1L984 = reg_sel[1] & (L2_q[5] # reg_sel[0]) # !reg_sel[1] & L61_q[5] & (!reg_sel[0]);

--M1L994 is reg_mux:inst27|reg_out[5]~600 at LC8_G9
--operation mode is normal

M1L994 = reg_sel[1] & (L2_q[5] # reg_sel[0]) # !reg_sel[1] & L61_q[5] & (!reg_sel[0]);


--M1L094 is reg_mux:inst27|reg_out[5]~441 at LC1_G9
--operation mode is normal

M1L094 = M1L984 & (L3_q[5] # !reg_sel[0]) # !M1L984 & (reg_sel[0] & L1_q[5]);

--M1L005 is reg_mux:inst27|reg_out[5]~601 at LC1_G9
--operation mode is normal

M1L005 = M1L984 & (L3_q[5] # !reg_sel[0]) # !M1L984 & (reg_sel[0] & L1_q[5]);


--M1L194 is reg_mux:inst27|reg_out[5]~442 at LC7_G22
--operation mode is normal

M1L194 = reg_sel[2] & (M1L884 # reg_sel[3]) # !reg_sel[2] & M1L094 & (!reg_sel[3]);

--M1L105 is reg_mux:inst27|reg_out[5]~602 at LC7_G22
--operation mode is normal

M1L105 = reg_sel[2] & (M1L884 # reg_sel[3]) # !reg_sel[2] & M1L094 & (!reg_sel[3]);


--M1L294 is reg_mux:inst27|reg_out[5]~443 at LC7_G4
--operation mode is normal

M1L294 = reg_sel[1] & (L41_q[5] # reg_sel[0]) # !reg_sel[1] & L21_q[5] & (!reg_sel[0]);

--M1L205 is reg_mux:inst27|reg_out[5]~603 at LC7_G4
--operation mode is normal

M1L205 = reg_sel[1] & (L41_q[5] # reg_sel[0]) # !reg_sel[1] & L21_q[5] & (!reg_sel[0]);


--M1L394 is reg_mux:inst27|reg_out[5]~444 at LC6_G4
--operation mode is normal

M1L394 = M1L294 & (L51_q[5] # !reg_sel[0]) # !M1L294 & (reg_sel[0] & L31_q[5]);

--M1L305 is reg_mux:inst27|reg_out[5]~604 at LC6_G4
--operation mode is normal

M1L305 = M1L294 & (L51_q[5] # !reg_sel[0]) # !M1L294 & (reg_sel[0] & L31_q[5]);


--M1L494 is reg_mux:inst27|reg_out[5]~445 at LC6_G22
--operation mode is normal

M1L494 = M1L194 & (M1L394 # !reg_sel[3]) # !M1L194 & (reg_sel[3] & M1L684);

--M1L405 is reg_mux:inst27|reg_out[5]~605 at LC6_G22
--operation mode is normal

M1L405 = M1L194 & (M1L394 # !reg_sel[3]) # !M1L194 & (reg_sel[3] & M1L684);


--R1L001 is reg_out:inst33|reg_data[5]~2824 at LC1_G24
--operation mode is normal

R1L001 = R1L271 & (reg_sel[0] & (G1_q[5]) # !reg_sel[0] & K1_q[5]);

--R1L301 is reg_out:inst33|reg_data[5]~2913 at LC1_G24
--operation mode is normal

R1L301 = R1L271 & (reg_sel[0] & (G1_q[5]) # !reg_sel[0] & K1_q[5]);


--R1L101 is reg_out:inst33|reg_data[5]~2825 at LC4_G24
--operation mode is normal

R1L101 = !R1L001 & (sel[1] # sel[0] # !M1L494);

--R1L401 is reg_out:inst33|reg_data[5]~2914 at LC4_G24
--operation mode is normal

R1L401 = !R1L001 & (sel[1] # sel[0] # !M1L494);

--R1L501 is reg_out:inst33|reg_data[5]~2915 at LC4_G24
--operation mode is normal

R1L501 = !R1L001 & (sel[1] # sel[0] # !M1L494);


--C1_q[5] is reg_testa:inst1|q[5] at LC3_G24
--operation mode is normal

C1_q[5]_lut_out = H1_alu_in_sel[1];
C1_q[5] = DFFEA(C1_q[5]_lut_out, GLOBAL(clk), reset, , , , );

--C1L31Q is reg_testa:inst1|q[5]~17 at LC3_G24
--operation mode is normal

C1L31Q = C1_q[5];


--R1L12 is reg_out:inst33|Mux~605 at LC6_G24
--operation mode is normal

R1L12 = reg_sel[1] & (N1L04 # reg_sel[0]) # !reg_sel[1] & H1_offset[5] & (!reg_sel[0]);

--R1L35 is reg_out:inst33|Mux~637 at LC6_G24
--operation mode is normal

R1L35 = reg_sel[1] & (N1L04 # reg_sel[0]) # !reg_sel[1] & H1_offset[5] & (!reg_sel[0]);


--R1L22 is reg_out:inst33|Mux~606 at LC8_G24
--operation mode is normal

R1L22 = R1L12 & (B1L35 # !reg_sel[0]) # !R1L12 & (reg_sel[0] & N1L931);

--R1L45 is reg_out:inst33|Mux~638 at LC8_G24
--operation mode is normal

R1L45 = R1L12 & (B1L35 # !reg_sel[0]) # !R1L12 & (reg_sel[0] & N1L931);


--R1L201 is reg_out:inst33|reg_data[5]~2850 at LC5_G24
--operation mode is normal

R1L201 = (R1L22 & !R1L571 & (!R1L461 # !C1_q[5]) # !R1L22 & (!R1L461 # !C1_q[5])) & CASCADE(R1L501);

--R1L601 is reg_out:inst33|reg_data[5]~2916 at LC5_G24
--operation mode is normal

R1L601 = (R1L22 & !R1L571 & (!R1L461 # !C1_q[5]) # !R1L22 & (!R1L461 # !C1_q[5])) & CASCADE(R1L501);


--M1L564 is reg_mux:inst27|reg_out[4]~446 at LC7_H23
--operation mode is normal

M1L564 = reg_sel[2] & (L6_q[4] # reg_sel[3]) # !reg_sel[2] & L2_q[4] & (!reg_sel[3]);

--M1L574 is reg_mux:inst27|reg_out[4]~606 at LC7_H23
--operation mode is normal

M1L574 = reg_sel[2] & (L6_q[4] # reg_sel[3]) # !reg_sel[2] & L2_q[4] & (!reg_sel[3]);


--M1L664 is reg_mux:inst27|reg_out[4]~447 at LC5_H23
--operation mode is normal

M1L664 = M1L564 & (L41_q[4] # !reg_sel[3]) # !M1L564 & (reg_sel[3] & L01_q[4]);

--M1L674 is reg_mux:inst27|reg_out[4]~607 at LC5_H23
--operation mode is normal

M1L674 = M1L564 & (L41_q[4] # !reg_sel[3]) # !M1L564 & (reg_sel[3] & L01_q[4]);


--M1L764 is reg_mux:inst27|reg_out[4]~448 at LC8_H3
--operation mode is normal

M1L764 = reg_sel[2] & (L5_q[4] # reg_sel[3]) # !reg_sel[2] & L1_q[4] & (!reg_sel[3]);

--M1L774 is reg_mux:inst27|reg_out[4]~608 at LC8_H3
--operation mode is normal

M1L774 = reg_sel[2] & (L5_q[4] # reg_sel[3]) # !reg_sel[2] & L1_q[4] & (!reg_sel[3]);


--M1L864 is reg_mux:inst27|reg_out[4]~449 at LC3_H3
--operation mode is normal

M1L864 = M1L764 & (L31_q[4] # !reg_sel[3]) # !M1L764 & (reg_sel[3] & L9_q[4]);

--M1L874 is reg_mux:inst27|reg_out[4]~609 at LC3_H3
--operation mode is normal

M1L874 = M1L764 & (L31_q[4] # !reg_sel[3]) # !M1L764 & (reg_sel[3] & L9_q[4]);


--M1L964 is reg_mux:inst27|reg_out[4]~450 at LC7_H4
--operation mode is normal

M1L964 = reg_sel[2] & (L4_q[4] # reg_sel[3]) # !reg_sel[2] & L61_q[4] & (!reg_sel[3]);

--M1L974 is reg_mux:inst27|reg_out[4]~610 at LC7_H4
--operation mode is normal

M1L974 = reg_sel[2] & (L4_q[4] # reg_sel[3]) # !reg_sel[2] & L61_q[4] & (!reg_sel[3]);


--M1L074 is reg_mux:inst27|reg_out[4]~451 at LC8_H4
--operation mode is normal

M1L074 = M1L964 & (L21_q[4] # !reg_sel[3]) # !M1L964 & (reg_sel[3] & L8_q[4]);

--M1L084 is reg_mux:inst27|reg_out[4]~611 at LC8_H4
--operation mode is normal

M1L084 = M1L964 & (L21_q[4] # !reg_sel[3]) # !M1L964 & (reg_sel[3] & L8_q[4]);


--M1L174 is reg_mux:inst27|reg_out[4]~452 at LC1_K10
--operation mode is normal

M1L174 = reg_sel[0] & (M1L864 # reg_sel[1]) # !reg_sel[0] & M1L074 & (!reg_sel[1]);

--M1L184 is reg_mux:inst27|reg_out[4]~612 at LC1_K10
--operation mode is normal

M1L184 = reg_sel[0] & (M1L864 # reg_sel[1]) # !reg_sel[0] & M1L074 & (!reg_sel[1]);


--M1L274 is reg_mux:inst27|reg_out[4]~453 at LC8_H1
--operation mode is normal

M1L274 = reg_sel[2] & (L7_q[4] # reg_sel[3]) # !reg_sel[2] & L3_q[4] & (!reg_sel[3]);

--M1L284 is reg_mux:inst27|reg_out[4]~613 at LC8_H1
--operation mode is normal

M1L284 = reg_sel[2] & (L7_q[4] # reg_sel[3]) # !reg_sel[2] & L3_q[4] & (!reg_sel[3]);


--M1L374 is reg_mux:inst27|reg_out[4]~454 at LC6_H1
--operation mode is normal

M1L374 = M1L274 & (L51_q[4] # !reg_sel[3]) # !M1L274 & (reg_sel[3] & L11_q[4]);

--M1L384 is reg_mux:inst27|reg_out[4]~614 at LC6_H1
--operation mode is normal

M1L384 = M1L274 & (L51_q[4] # !reg_sel[3]) # !M1L274 & (reg_sel[3] & L11_q[4]);


--M1L474 is reg_mux:inst27|reg_out[4]~455 at LC1_K16
--operation mode is normal

M1L474 = M1L174 & (M1L374 # !reg_sel[1]) # !M1L174 & (reg_sel[1] & M1L664);

--M1L484 is reg_mux:inst27|reg_out[4]~615 at LC1_K16
--operation mode is normal

M1L484 = M1L174 & (M1L374 # !reg_sel[1]) # !M1L174 & (reg_sel[1] & M1L664);


--R1L39 is reg_out:inst33|reg_data[4]~2827 at LC3_K16
--operation mode is normal

R1L39 = R1L271 & (reg_sel[0] & (G1_q[4]) # !reg_sel[0] & K1_q[4]);

--R1L69 is reg_out:inst33|reg_data[4]~2917 at LC3_K16
--operation mode is normal

R1L69 = R1L271 & (reg_sel[0] & (G1_q[4]) # !reg_sel[0] & K1_q[4]);


--R1L49 is reg_out:inst33|reg_data[4]~2828 at LC4_K16
--operation mode is normal

R1L49 = !R1L39 & (sel[1] # sel[0] # !M1L474);

--R1L79 is reg_out:inst33|reg_data[4]~2918 at LC4_K16
--operation mode is normal

R1L79 = !R1L39 & (sel[1] # sel[0] # !M1L474);

--R1L89 is reg_out:inst33|reg_data[4]~2919 at LC4_K16
--operation mode is normal

R1L89 = !R1L39 & (sel[1] # sel[0] # !M1L474);


--C1_q[4] is reg_testa:inst1|q[4] at LC6_K16
--operation mode is normal

C1_q[4]_lut_out = H1_alu_in_sel[0];
C1_q[4] = DFFEA(C1_q[4]_lut_out, GLOBAL(clk), reset, , , , );

--C1L11Q is reg_testa:inst1|q[4]~18 at LC6_K16
--operation mode is normal

C1L11Q = C1_q[4];


--R1L32 is reg_out:inst33|Mux~607 at LC7_K16
--operation mode is normal

R1L32 = reg_sel[0] & (N1L731 # reg_sel[1]) # !reg_sel[0] & H1_offset[4] & (!reg_sel[1]);

--R1L55 is reg_out:inst33|Mux~639 at LC7_K16
--operation mode is normal

R1L55 = reg_sel[0] & (N1L731 # reg_sel[1]) # !reg_sel[0] & H1_offset[4] & (!reg_sel[1]);


--R1L42 is reg_out:inst33|Mux~608 at LC8_K16
--operation mode is normal

R1L42 = R1L32 & (B1L34 # !reg_sel[1]) # !R1L32 & (reg_sel[1] & N1L23);

--R1L65 is reg_out:inst33|Mux~640 at LC8_K16
--operation mode is normal

R1L65 = R1L32 & (B1L34 # !reg_sel[1]) # !R1L32 & (reg_sel[1] & N1L23);


--R1L59 is reg_out:inst33|reg_data[4]~2851 at LC5_K16
--operation mode is normal

R1L59 = (R1L42 & !R1L571 & (!R1L461 # !C1_q[4]) # !R1L42 & (!R1L461 # !C1_q[4])) & CASCADE(R1L89);

--R1L99 is reg_out:inst33|reg_data[4]~2920 at LC5_K16
--operation mode is normal

R1L99 = (R1L42 & !R1L571 & (!R1L461 # !C1_q[4]) # !R1L42 & (!R1L461 # !C1_q[4])) & CASCADE(R1L89);


--M1L544 is reg_mux:inst27|reg_out[3]~456 at LC8_K13
--operation mode is normal

M1L544 = reg_sel[1] & (L01_q[3] # reg_sel[0]) # !reg_sel[1] & L8_q[3] & (!reg_sel[0]);

--M1L554 is reg_mux:inst27|reg_out[3]~616 at LC8_K13
--operation mode is normal

M1L554 = reg_sel[1] & (L01_q[3] # reg_sel[0]) # !reg_sel[1] & L8_q[3] & (!reg_sel[0]);


--M1L644 is reg_mux:inst27|reg_out[3]~457 at LC3_K13
--operation mode is normal

M1L644 = M1L544 & (L11_q[3] # !reg_sel[0]) # !M1L544 & (reg_sel[0] & L9_q[3]);

--M1L654 is reg_mux:inst27|reg_out[3]~617 at LC3_K13
--operation mode is normal

M1L654 = M1L544 & (L11_q[3] # !reg_sel[0]) # !M1L544 & (reg_sel[0] & L9_q[3]);


--M1L744 is reg_mux:inst27|reg_out[3]~458 at LC2_K20
--operation mode is normal

M1L744 = reg_sel[0] & (L5_q[3] # reg_sel[1]) # !reg_sel[0] & L4_q[3] & (!reg_sel[1]);

--M1L754 is reg_mux:inst27|reg_out[3]~618 at LC2_K20
--operation mode is normal

M1L754 = reg_sel[0] & (L5_q[3] # reg_sel[1]) # !reg_sel[0] & L4_q[3] & (!reg_sel[1]);


--M1L844 is reg_mux:inst27|reg_out[3]~459 at LC4_K20
--operation mode is normal

M1L844 = M1L744 & (L7_q[3] # !reg_sel[1]) # !M1L744 & (reg_sel[1] & L6_q[3]);

--M1L854 is reg_mux:inst27|reg_out[3]~619 at LC4_K20
--operation mode is normal

M1L854 = M1L744 & (L7_q[3] # !reg_sel[1]) # !M1L744 & (reg_sel[1] & L6_q[3]);


--M1L944 is reg_mux:inst27|reg_out[3]~460 at LC7_K14
--operation mode is normal

M1L944 = reg_sel[1] & (L2_q[3] # reg_sel[0]) # !reg_sel[1] & L61_q[3] & (!reg_sel[0]);

--M1L954 is reg_mux:inst27|reg_out[3]~620 at LC7_K14
--operation mode is normal

M1L954 = reg_sel[1] & (L2_q[3] # reg_sel[0]) # !reg_sel[1] & L61_q[3] & (!reg_sel[0]);


--M1L054 is reg_mux:inst27|reg_out[3]~461 at LC1_K14
--operation mode is normal

M1L054 = M1L944 & (L3_q[3] # !reg_sel[0]) # !M1L944 & (reg_sel[0] & L1_q[3]);

--M1L064 is reg_mux:inst27|reg_out[3]~621 at LC1_K14
--operation mode is normal

M1L064 = M1L944 & (L3_q[3] # !reg_sel[0]) # !M1L944 & (reg_sel[0] & L1_q[3]);


--M1L154 is reg_mux:inst27|reg_out[3]~462 at LC5_K20
--operation mode is normal

M1L154 = reg_sel[2] & (M1L844 # reg_sel[3]) # !reg_sel[2] & M1L054 & (!reg_sel[3]);

--M1L164 is reg_mux:inst27|reg_out[3]~622 at LC5_K20
--operation mode is normal

M1L164 = reg_sel[2] & (M1L844 # reg_sel[3]) # !reg_sel[2] & M1L054 & (!reg_sel[3]);


--M1L254 is reg_mux:inst27|reg_out[3]~463 at LC8_K12
--operation mode is normal

M1L254 = reg_sel[0] & (L31_q[3] # reg_sel[1]) # !reg_sel[0] & L21_q[3] & (!reg_sel[1]);

--M1L264 is reg_mux:inst27|reg_out[3]~623 at LC8_K12
--operation mode is normal

M1L264 = reg_sel[0] & (L31_q[3] # reg_sel[1]) # !reg_sel[0] & L21_q[3] & (!reg_sel[1]);


--M1L354 is reg_mux:inst27|reg_out[3]~464 at LC5_K12
--operation mode is normal

M1L354 = M1L254 & (L51_q[3] # !reg_sel[1]) # !M1L254 & (reg_sel[1] & L41_q[3]);

--M1L364 is reg_mux:inst27|reg_out[3]~624 at LC5_K12
--operation mode is normal

M1L364 = M1L254 & (L51_q[3] # !reg_sel[1]) # !M1L254 & (reg_sel[1] & L41_q[3]);


--M1L454 is reg_mux:inst27|reg_out[3]~465 at LC6_K20
--operation mode is normal

M1L454 = M1L154 & (M1L354 # !reg_sel[3]) # !M1L154 & (reg_sel[3] & M1L644);

--M1L464 is reg_mux:inst27|reg_out[3]~625 at LC6_K20
--operation mode is normal

M1L464 = M1L154 & (M1L354 # !reg_sel[3]) # !M1L154 & (reg_sel[3] & M1L644);


--R1L68 is reg_out:inst33|reg_data[3]~2830 at LC7_K20
--operation mode is normal

R1L68 = R1L271 & (reg_sel[0] & (G1_q[3]) # !reg_sel[0] & K1_q[3]);

--R1L98 is reg_out:inst33|reg_data[3]~2921 at LC7_K20
--operation mode is normal

R1L98 = R1L271 & (reg_sel[0] & (G1_q[3]) # !reg_sel[0] & K1_q[3]);


--R1L78 is reg_out:inst33|reg_data[3]~2831 at LC8_K20
--operation mode is normal

R1L78 = !R1L68 & (sel[1] # sel[0] # !M1L454);

--R1L09 is reg_out:inst33|reg_data[3]~2922 at LC8_K20
--operation mode is normal

R1L09 = !R1L68 & (sel[1] # sel[0] # !M1L454);

--R1L19 is reg_out:inst33|reg_data[3]~2923 at LC8_K20
--operation mode is normal

R1L19 = !R1L68 & (sel[1] # sel[0] # !M1L454);


--C1_q[3] is reg_testa:inst1|q[3] at LC3_K22
--operation mode is normal

C1_q[3]_lut_out = H1_rec[1];
C1_q[3] = DFFEA(C1_q[3]_lut_out, GLOBAL(clk), reset, , , , );

--C1L9Q is reg_testa:inst1|q[3]~19 at LC3_K22
--operation mode is normal

C1L9Q = C1_q[3];


--R1L52 is reg_out:inst33|Mux~609 at LC6_K45
--operation mode is normal

R1L52 = reg_sel[1] & (N1L42 # reg_sel[0]) # !reg_sel[1] & H1_offset[3] & (!reg_sel[0]);

--R1L75 is reg_out:inst33|Mux~641 at LC6_K45
--operation mode is normal

R1L75 = reg_sel[1] & (N1L42 # reg_sel[0]) # !reg_sel[1] & H1_offset[3] & (!reg_sel[0]);


--R1L62 is reg_out:inst33|Mux~610 at LC8_K45
--operation mode is normal

R1L62 = R1L52 & (B1L33 # !reg_sel[0]) # !R1L52 & (reg_sel[0] & N1L531);

--R1L85 is reg_out:inst33|Mux~642 at LC8_K45
--operation mode is normal

R1L85 = R1L52 & (B1L33 # !reg_sel[0]) # !R1L52 & (reg_sel[0] & N1L531);


--R1L88 is reg_out:inst33|reg_data[3]~2852 at LC1_K22
--operation mode is normal

R1L88 = (R1L62 & !R1L571 & (!R1L461 # !C1_q[3]) # !R1L62 & (!R1L461 # !C1_q[3])) & CASCADE(R1L19);

--R1L29 is reg_out:inst33|reg_data[3]~2924 at LC1_K22
--operation mode is normal

R1L29 = (R1L62 & !R1L571 & (!R1L461 # !C1_q[3]) # !R1L62 & (!R1L461 # !C1_q[3])) & CASCADE(R1L19);


--M1L524 is reg_mux:inst27|reg_out[2]~466 at LC4_H22
--operation mode is normal

M1L524 = reg_sel[2] & (L5_q[2] # reg_sel[3]) # !reg_sel[2] & L1_q[2] & (!reg_sel[3]);

--M1L534 is reg_mux:inst27|reg_out[2]~626 at LC4_H22
--operation mode is normal

M1L534 = reg_sel[2] & (L5_q[2] # reg_sel[3]) # !reg_sel[2] & L1_q[2] & (!reg_sel[3]);


--M1L624 is reg_mux:inst27|reg_out[2]~467 at LC7_H22
--operation mode is normal

M1L624 = M1L524 & (L31_q[2] # !reg_sel[3]) # !M1L524 & (reg_sel[3] & L9_q[2]);

--M1L634 is reg_mux:inst27|reg_out[2]~627 at LC7_H22
--operation mode is normal

M1L634 = M1L524 & (L31_q[2] # !reg_sel[3]) # !M1L524 & (reg_sel[3] & L9_q[2]);


--M1L724 is reg_mux:inst27|reg_out[2]~468 at LC7_H27
--operation mode is normal

M1L724 = reg_sel[2] & (L6_q[2] # reg_sel[3]) # !reg_sel[2] & L2_q[2] & (!reg_sel[3]);

--M1L734 is reg_mux:inst27|reg_out[2]~628 at LC7_H27
--operation mode is normal

M1L734 = reg_sel[2] & (L6_q[2] # reg_sel[3]) # !reg_sel[2] & L2_q[2] & (!reg_sel[3]);


--M1L824 is reg_mux:inst27|reg_out[2]~469 at LC1_H27
--operation mode is normal

M1L824 = M1L724 & (L41_q[2] # !reg_sel[3]) # !M1L724 & (reg_sel[3] & L01_q[2]);

--M1L834 is reg_mux:inst27|reg_out[2]~629 at LC1_H27
--operation mode is normal

M1L834 = M1L724 & (L41_q[2] # !reg_sel[3]) # !M1L724 & (reg_sel[3] & L01_q[2]);


--M1L924 is reg_mux:inst27|reg_out[2]~470 at LC8_H13
--operation mode is normal

M1L924 = reg_sel[2] & (L4_q[2] # reg_sel[3]) # !reg_sel[2] & L61_q[2] & (!reg_sel[3]);

--M1L934 is reg_mux:inst27|reg_out[2]~630 at LC8_H13
--operation mode is normal

M1L934 = reg_sel[2] & (L4_q[2] # reg_sel[3]) # !reg_sel[2] & L61_q[2] & (!reg_sel[3]);


--M1L034 is reg_mux:inst27|reg_out[2]~471 at LC6_H13
--operation mode is normal

M1L034 = M1L924 & (L21_q[2] # !reg_sel[3]) # !M1L924 & (reg_sel[3] & L8_q[2]);

--M1L044 is reg_mux:inst27|reg_out[2]~631 at LC6_H13
--operation mode is normal

M1L044 = M1L924 & (L21_q[2] # !reg_sel[3]) # !M1L924 & (reg_sel[3] & L8_q[2]);


--M1L134 is reg_mux:inst27|reg_out[2]~472 at LC1_H32
--operation mode is normal

M1L134 = reg_sel[1] & (M1L824 # reg_sel[0]) # !reg_sel[1] & M1L034 & (!reg_sel[0]);

--M1L144 is reg_mux:inst27|reg_out[2]~632 at LC1_H32
--operation mode is normal

M1L144 = reg_sel[1] & (M1L824 # reg_sel[0]) # !reg_sel[1] & M1L034 & (!reg_sel[0]);


--M1L234 is reg_mux:inst27|reg_out[2]~473 at LC8_H11
--operation mode is normal

M1L234 = reg_sel[2] & (L7_q[2] # reg_sel[3]) # !reg_sel[2] & L3_q[2] & (!reg_sel[3]);

--M1L244 is reg_mux:inst27|reg_out[2]~633 at LC8_H11
--operation mode is normal

M1L244 = reg_sel[2] & (L7_q[2] # reg_sel[3]) # !reg_sel[2] & L3_q[2] & (!reg_sel[3]);


--M1L334 is reg_mux:inst27|reg_out[2]~474 at LC3_H11
--operation mode is normal

M1L334 = M1L234 & (L51_q[2] # !reg_sel[3]) # !M1L234 & (reg_sel[3] & L11_q[2]);

--M1L344 is reg_mux:inst27|reg_out[2]~634 at LC3_H11
--operation mode is normal

M1L344 = M1L234 & (L51_q[2] # !reg_sel[3]) # !M1L234 & (reg_sel[3] & L11_q[2]);


--M1L434 is reg_mux:inst27|reg_out[2]~475 at LC2_H32
--operation mode is normal

M1L434 = M1L134 & (M1L334 # !reg_sel[0]) # !M1L134 & (reg_sel[0] & M1L624);

--M1L444 is reg_mux:inst27|reg_out[2]~635 at LC2_H32
--operation mode is normal

M1L444 = M1L134 & (M1L334 # !reg_sel[0]) # !M1L134 & (reg_sel[0] & M1L624);


--R1L97 is reg_out:inst33|reg_data[2]~2833 at LC7_H32
--operation mode is normal

R1L97 = R1L271 & (reg_sel[0] & (G1_q[2]) # !reg_sel[0] & K1_q[2]);

--R1L28 is reg_out:inst33|reg_data[2]~2925 at LC7_H32
--operation mode is normal

R1L28 = R1L271 & (reg_sel[0] & (G1_q[2]) # !reg_sel[0] & K1_q[2]);


--R1L08 is reg_out:inst33|reg_data[2]~2834 at LC4_H32
--operation mode is normal

R1L08 = !R1L97 & (sel[1] # sel[0] # !M1L434);

--R1L38 is reg_out:inst33|reg_data[2]~2926 at LC4_H32
--operation mode is normal

R1L38 = !R1L97 & (sel[1] # sel[0] # !M1L434);

--R1L48 is reg_out:inst33|reg_data[2]~2927 at LC4_H32
--operation mode is normal

R1L48 = !R1L97 & (sel[1] # sel[0] # !M1L434);


--C1_q[2] is reg_testa:inst1|q[2] at LC8_H32
--operation mode is normal

C1_q[2]_lut_out = H1_rec[0];
C1_q[2] = DFFEA(C1_q[2]_lut_out, GLOBAL(clk), reset, , , , );

--C1L7Q is reg_testa:inst1|q[2]~20 at LC8_H32
--operation mode is normal

C1L7Q = C1_q[2];


--R1L72 is reg_out:inst33|Mux~611 at LC1_K3
--operation mode is normal

R1L72 = reg_sel[0] & (N1L331 # reg_sel[1]) # !reg_sel[0] & H1_offset[2] & (!reg_sel[1]);

--R1L95 is reg_out:inst33|Mux~643 at LC1_K3
--operation mode is normal

R1L95 = reg_sel[0] & (N1L331 # reg_sel[1]) # !reg_sel[0] & H1_offset[2] & (!reg_sel[1]);


--R1L82 is reg_out:inst33|Mux~612 at LC4_K3
--operation mode is normal

R1L82 = R1L72 & (B1L32 # !reg_sel[1]) # !R1L72 & (reg_sel[1] & N1L61);

--R1L06 is reg_out:inst33|Mux~644 at LC4_K3
--operation mode is normal

R1L06 = R1L72 & (B1L32 # !reg_sel[1]) # !R1L72 & (reg_sel[1] & N1L61);


--R1L18 is reg_out:inst33|reg_data[2]~2853 at LC5_H32
--operation mode is normal

R1L18 = (R1L82 & !R1L571 & (!R1L461 # !C1_q[2]) # !R1L82 & (!R1L461 # !C1_q[2])) & CASCADE(R1L48);

--R1L58 is reg_out:inst33|reg_data[2]~2928 at LC5_H32
--operation mode is normal

R1L58 = (R1L82 & !R1L571 & (!R1L461 # !C1_q[2]) # !R1L82 & (!R1L461 # !C1_q[2])) & CASCADE(R1L48);


--M1L504 is reg_mux:inst27|reg_out[1]~476 at LC4_H2
--operation mode is normal

M1L504 = reg_sel[0] & (L9_q[1] # reg_sel[1]) # !reg_sel[0] & L8_q[1] & (!reg_sel[1]);

--M1L514 is reg_mux:inst27|reg_out[1]~636 at LC4_H2
--operation mode is normal

M1L514 = reg_sel[0] & (L9_q[1] # reg_sel[1]) # !reg_sel[0] & L8_q[1] & (!reg_sel[1]);


--M1L604 is reg_mux:inst27|reg_out[1]~477 at LC5_H2
--operation mode is normal

M1L604 = M1L504 & (L11_q[1] # !reg_sel[1]) # !M1L504 & (reg_sel[1] & L01_q[1]);

--M1L614 is reg_mux:inst27|reg_out[1]~637 at LC5_H2
--operation mode is normal

M1L614 = M1L504 & (L11_q[1] # !reg_sel[1]) # !M1L504 & (reg_sel[1] & L01_q[1]);


--M1L704 is reg_mux:inst27|reg_out[1]~478 at LC7_H9
--operation mode is normal

M1L704 = reg_sel[1] & (L6_q[1] # reg_sel[0]) # !reg_sel[1] & L4_q[1] & (!reg_sel[0]);

--M1L714 is reg_mux:inst27|reg_out[1]~638 at LC7_H9
--operation mode is normal

M1L714 = reg_sel[1] & (L6_q[1] # reg_sel[0]) # !reg_sel[1] & L4_q[1] & (!reg_sel[0]);


--M1L804 is reg_mux:inst27|reg_out[1]~479 at LC6_H9
--operation mode is normal

M1L804 = M1L704 & (L7_q[1] # !reg_sel[0]) # !M1L704 & (reg_sel[0] & L5_q[1]);

--M1L814 is reg_mux:inst27|reg_out[1]~639 at LC6_H9
--operation mode is normal

M1L814 = M1L704 & (L7_q[1] # !reg_sel[0]) # !M1L704 & (reg_sel[0] & L5_q[1]);


--M1L904 is reg_mux:inst27|reg_out[1]~480 at LC7_H10
--operation mode is normal

M1L904 = reg_sel[0] & (L1_q[1] # reg_sel[1]) # !reg_sel[0] & L61_q[1] & (!reg_sel[1]);

--M1L914 is reg_mux:inst27|reg_out[1]~640 at LC7_H10
--operation mode is normal

M1L914 = reg_sel[0] & (L1_q[1] # reg_sel[1]) # !reg_sel[0] & L61_q[1] & (!reg_sel[1]);


--M1L014 is reg_mux:inst27|reg_out[1]~481 at LC3_H10
--operation mode is normal

M1L014 = M1L904 & (L3_q[1] # !reg_sel[1]) # !M1L904 & (reg_sel[1] & L2_q[1]);

--M1L024 is reg_mux:inst27|reg_out[1]~641 at LC3_H10
--operation mode is normal

M1L024 = M1L904 & (L3_q[1] # !reg_sel[1]) # !M1L904 & (reg_sel[1] & L2_q[1]);


--M1L114 is reg_mux:inst27|reg_out[1]~482 at LC8_H2
--operation mode is normal

M1L114 = reg_sel[2] & (M1L804 # reg_sel[3]) # !reg_sel[2] & M1L014 & (!reg_sel[3]);

--M1L124 is reg_mux:inst27|reg_out[1]~642 at LC8_H2
--operation mode is normal

M1L124 = reg_sel[2] & (M1L804 # reg_sel[3]) # !reg_sel[2] & M1L014 & (!reg_sel[3]);


--M1L214 is reg_mux:inst27|reg_out[1]~483 at LC8_H7
--operation mode is normal

M1L214 = reg_sel[1] & (L41_q[1] # reg_sel[0]) # !reg_sel[1] & L21_q[1] & (!reg_sel[0]);

--M1L224 is reg_mux:inst27|reg_out[1]~643 at LC8_H7
--operation mode is normal

M1L224 = reg_sel[1] & (L41_q[1] # reg_sel[0]) # !reg_sel[1] & L21_q[1] & (!reg_sel[0]);


--M1L314 is reg_mux:inst27|reg_out[1]~484 at LC4_H7
--operation mode is normal

M1L314 = M1L214 & (L51_q[1] # !reg_sel[0]) # !M1L214 & (reg_sel[0] & L31_q[1]);

--M1L324 is reg_mux:inst27|reg_out[1]~644 at LC4_H7
--operation mode is normal

M1L324 = M1L214 & (L51_q[1] # !reg_sel[0]) # !M1L214 & (reg_sel[0] & L31_q[1]);


--M1L414 is reg_mux:inst27|reg_out[1]~485 at LC3_H2
--operation mode is normal

M1L414 = M1L114 & (M1L314 # !reg_sel[3]) # !M1L114 & (reg_sel[3] & M1L604);

--M1L424 is reg_mux:inst27|reg_out[1]~645 at LC3_H2
--operation mode is normal

M1L424 = M1L114 & (M1L314 # !reg_sel[3]) # !M1L114 & (reg_sel[3] & M1L604);


--R1L27 is reg_out:inst33|reg_data[1]~2836 at LC1_H49
--operation mode is normal

R1L27 = R1L271 & (reg_sel[0] & (G1_q[1]) # !reg_sel[0] & K1_q[1]);

--R1L57 is reg_out:inst33|reg_data[1]~2929 at LC1_H49
--operation mode is normal

R1L57 = R1L271 & (reg_sel[0] & (G1_q[1]) # !reg_sel[0] & K1_q[1]);


--R1L37 is reg_out:inst33|reg_data[1]~2837 at LC3_H49
--operation mode is normal

R1L37 = !R1L27 & (sel[1] # sel[0] # !M1L414);

--R1L67 is reg_out:inst33|reg_data[1]~2930 at LC3_H49
--operation mode is normal

R1L67 = !R1L27 & (sel[1] # sel[0] # !M1L414);

--R1L77 is reg_out:inst33|reg_data[1]~2931 at LC3_H49
--operation mode is normal

R1L77 = !R1L27 & (sel[1] # sel[0] # !M1L414);


--C1_q[1] is reg_testa:inst1|q[1] at LC2_H49
--operation mode is normal

C1_q[1]_lut_out = !H1L33;
C1_q[1] = DFFEA(C1_q[1]_lut_out, GLOBAL(clk), reset, , , , );

--C1L5Q is reg_testa:inst1|q[1]~21 at LC2_H49
--operation mode is normal

C1L5Q = C1_q[1];


--R1L92 is reg_out:inst33|Mux~613 at LC6_H49
--operation mode is normal

R1L92 = reg_sel[1] & (N1L8 # reg_sel[0]) # !reg_sel[1] & H1_offset[1] & (!reg_sel[0]);

--R1L16 is reg_out:inst33|Mux~645 at LC6_H49
--operation mode is normal

R1L16 = reg_sel[1] & (N1L8 # reg_sel[0]) # !reg_sel[1] & H1_offset[1] & (!reg_sel[0]);


--R1L03 is reg_out:inst33|Mux~614 at LC7_H49
--operation mode is normal

R1L03 = R1L92 & (B1L31 # !reg_sel[0]) # !R1L92 & (reg_sel[0] & N1L131);

--R1L26 is reg_out:inst33|Mux~646 at LC7_H49
--operation mode is normal

R1L26 = R1L92 & (B1L31 # !reg_sel[0]) # !R1L92 & (reg_sel[0] & N1L131);


--R1L47 is reg_out:inst33|reg_data[1]~2854 at LC4_H49
--operation mode is normal

R1L47 = (R1L03 & !R1L571 & (!R1L461 # !C1_q[1]) # !R1L03 & (!R1L461 # !C1_q[1])) & CASCADE(R1L77);

--R1L87 is reg_out:inst33|reg_data[1]~2932 at LC4_H49
--operation mode is normal

R1L87 = (R1L03 & !R1L571 & (!R1L461 # !C1_q[1]) # !R1L03 & (!R1L461 # !C1_q[1])) & CASCADE(R1L77);


--M1L583 is reg_mux:inst27|reg_out[0]~486 at LC2_E9
--operation mode is normal

M1L583 = reg_sel[2] & (L6_q[0] # reg_sel[3]) # !reg_sel[2] & L2_q[0] & (!reg_sel[3]);

--M1L593 is reg_mux:inst27|reg_out[0]~646 at LC2_E9
--operation mode is normal

M1L593 = reg_sel[2] & (L6_q[0] # reg_sel[3]) # !reg_sel[2] & L2_q[0] & (!reg_sel[3]);


--M1L683 is reg_mux:inst27|reg_out[0]~487 at LC4_E8
--operation mode is normal

M1L683 = M1L583 & (L41_q[0] # !reg_sel[3]) # !M1L583 & (reg_sel[3] & L01_q[0]);

--M1L693 is reg_mux:inst27|reg_out[0]~647 at LC4_E8
--operation mode is normal

M1L693 = M1L583 & (L41_q[0] # !reg_sel[3]) # !M1L583 & (reg_sel[3] & L01_q[0]);


--M1L783 is reg_mux:inst27|reg_out[0]~488 at LC7_E14
--operation mode is normal

M1L783 = reg_sel[2] & (L5_q[0] # reg_sel[3]) # !reg_sel[2] & L1_q[0] & (!reg_sel[3]);

--M1L793 is reg_mux:inst27|reg_out[0]~648 at LC7_E14
--operation mode is normal

M1L793 = reg_sel[2] & (L5_q[0] # reg_sel[3]) # !reg_sel[2] & L1_q[0] & (!reg_sel[3]);


--M1L883 is reg_mux:inst27|reg_out[0]~489 at LC3_E14
--operation mode is normal

M1L883 = M1L783 & (L31_q[0] # !reg_sel[3]) # !M1L783 & (reg_sel[3] & L9_q[0]);

--M1L893 is reg_mux:inst27|reg_out[0]~649 at LC3_E14
--operation mode is normal

M1L893 = M1L783 & (L31_q[0] # !reg_sel[3]) # !M1L783 & (reg_sel[3] & L9_q[0]);


--M1L983 is reg_mux:inst27|reg_out[0]~490 at LC5_E8
--operation mode is normal

M1L983 = reg_sel[2] & (L4_q[0] # reg_sel[3]) # !reg_sel[2] & L61_q[0] & (!reg_sel[3]);

--M1L993 is reg_mux:inst27|reg_out[0]~650 at LC5_E8
--operation mode is normal

M1L993 = reg_sel[2] & (L4_q[0] # reg_sel[3]) # !reg_sel[2] & L61_q[0] & (!reg_sel[3]);


--M1L093 is reg_mux:inst27|reg_out[0]~491 at LC6_E8
--operation mode is normal

M1L093 = M1L983 & (L21_q[0] # !reg_sel[3]) # !M1L983 & (reg_sel[3] & L8_q[0]);

--M1L004 is reg_mux:inst27|reg_out[0]~651 at LC6_E8
--operation mode is normal

M1L004 = M1L983 & (L21_q[0] # !reg_sel[3]) # !M1L983 & (reg_sel[3] & L8_q[0]);


--M1L193 is reg_mux:inst27|reg_out[0]~492 at LC7_E8
--operation mode is normal

M1L193 = reg_sel[0] & (M1L883 # reg_sel[1]) # !reg_sel[0] & M1L093 & (!reg_sel[1]);

--M1L104 is reg_mux:inst27|reg_out[0]~652 at LC7_E8
--operation mode is normal

M1L104 = reg_sel[0] & (M1L883 # reg_sel[1]) # !reg_sel[0] & M1L093 & (!reg_sel[1]);


--M1L293 is reg_mux:inst27|reg_out[0]~493 at LC7_E11
--operation mode is normal

M1L293 = reg_sel[2] & (L7_q[0] # reg_sel[3]) # !reg_sel[2] & L3_q[0] & (!reg_sel[3]);

--M1L204 is reg_mux:inst27|reg_out[0]~653 at LC7_E11
--operation mode is normal

M1L204 = reg_sel[2] & (L7_q[0] # reg_sel[3]) # !reg_sel[2] & L3_q[0] & (!reg_sel[3]);


--M1L393 is reg_mux:inst27|reg_out[0]~494 at LC5_E11
--operation mode is normal

M1L393 = M1L293 & (L51_q[0] # !reg_sel[3]) # !M1L293 & (reg_sel[3] & L11_q[0]);

--M1L304 is reg_mux:inst27|reg_out[0]~654 at LC5_E11
--operation mode is normal

M1L304 = M1L293 & (L51_q[0] # !reg_sel[3]) # !M1L293 & (reg_sel[3] & L11_q[0]);


--M1L493 is reg_mux:inst27|reg_out[0]~495 at LC2_E8
--operation mode is normal

M1L493 = M1L193 & (M1L393 # !reg_sel[1]) # !M1L193 & (reg_sel[1] & M1L683);

--M1L404 is reg_mux:inst27|reg_out[0]~655 at LC2_E8
--operation mode is normal

M1L404 = M1L193 & (M1L393 # !reg_sel[1]) # !M1L193 & (reg_sel[1] & M1L683);


--R1L56 is reg_out:inst33|reg_data[0]~2839 at LC1_E17
--operation mode is normal

R1L56 = R1L271 & (reg_sel[0] & (G1_q[0]) # !reg_sel[0] & K1_q[0]);

--R1L86 is reg_out:inst33|reg_data[0]~2933 at LC1_E17
--operation mode is normal

R1L86 = R1L271 & (reg_sel[0] & (G1_q[0]) # !reg_sel[0] & K1_q[0]);


--R1L66 is reg_out:inst33|reg_data[0]~2840 at LC4_E17
--operation mode is normal

R1L66 = !R1L56 & (sel[1] # sel[0] # !M1L493);

--R1L96 is reg_out:inst33|reg_data[0]~2934 at LC4_E17
--operation mode is normal

R1L96 = !R1L56 & (sel[1] # sel[0] # !M1L493);

--R1L07 is reg_out:inst33|reg_data[0]~2935 at LC4_E17
--operation mode is normal

R1L07 = !R1L56 & (sel[1] # sel[0] # !M1L493);


--C1_q[0] is reg_testa:inst1|q[0] at LC7_E17
--operation mode is normal

C1_q[0]_lut_out = !F1_state.s1 & F1_state.s0 & H1L84;
C1_q[0] = DFFEA(C1_q[0]_lut_out, GLOBAL(clk), reset, , , , );

--C1L3Q is reg_testa:inst1|q[0]~22 at LC7_E17
--operation mode is normal

C1L3Q = C1_q[0];


--R1L13 is reg_out:inst33|Mux~615 at LC8_E9
--operation mode is normal

R1L13 = reg_sel[0] & (N1L921 # reg_sel[1]) # !reg_sel[0] & H1_offset[0] & (!reg_sel[1]);

--R1L36 is reg_out:inst33|Mux~647 at LC8_E9
--operation mode is normal

R1L36 = reg_sel[0] & (N1L921 # reg_sel[1]) # !reg_sel[0] & H1_offset[0] & (!reg_sel[1]);


--R1L23 is reg_out:inst33|Mux~616 at LC8_G51
--operation mode is normal

R1L23 = R1L13 & (B1L4 # !reg_sel[1]) # !R1L13 & (reg_sel[1] & !N1L2);

--R1L46 is reg_out:inst33|Mux~648 at LC8_G51
--operation mode is normal

R1L46 = R1L13 & (B1L4 # !reg_sel[1]) # !R1L13 & (reg_sel[1] & !N1L2);


--R1L76 is reg_out:inst33|reg_data[0]~2855 at LC5_E17
--operation mode is normal

R1L76 = (R1L23 & !R1L571 & (!R1L461 # !C1_q[0]) # !R1L23 & (!R1L461 # !C1_q[0])) & CASCADE(R1L07);

--R1L17 is reg_out:inst33|reg_data[0]~2936 at LC5_E17
--operation mode is normal

R1L17 = (R1L23 & !R1L571 & (!R1L461 # !C1_q[0]) # !R1L23 & (!R1L461 # !C1_q[0])) & CASCADE(R1L07);


--D1L01 is flag_reg:inst2|Mux~657 at LC5_G28
--operation mode is normal

D1L01 = !H1_sst[0] & !H1_alu_func[2] & !H1_alu_func[1] & H1_alu_func[0];

--D1L02 is flag_reg:inst2|Mux~674 at LC5_G28
--operation mode is normal

D1L02 = !H1_sst[0] & !H1_alu_func[2] & !H1_alu_func[1] & H1_alu_func[0];


--D1L71 is flag_reg:inst2|Mux~669 at LC8_G33
--operation mode is normal

D1L71 = (B1L491 # N1L221 $ !N1L061 # !D1L01) & CASCADE(D1L03);

--D1L12 is flag_reg:inst2|Mux~675 at LC8_G33
--operation mode is normal

D1L12 = (B1L491 # N1L221 $ !N1L061 # !D1L01) & CASCADE(D1L03);


--H1L58 is controller:inst8|Mux~4107 at LC5_H6
--operation mode is normal

H1L58 = H1L75 & G1_q[2];

--H1L431 is controller:inst8|Mux~4162 at LC5_H6
--operation mode is normal

H1L431 = H1L75 & G1_q[2];


--H1_offset[2] is controller:inst8|offset[2] at LC6_H6
--operation mode is normal

H1_offset[2] = H1L95 & (H1L58) # !H1L95 & H1_offset[2];

--H1L851 is controller:inst8|offset[2]~25 at LC6_H6
--operation mode is normal

H1L851 = H1L95 & (H1L58) # !H1L95 & H1_offset[2];


--H1L68 is controller:inst8|Mux~4108 at LC6_G8
--operation mode is normal

H1L68 = H1L75 & G1_q[6];

--H1L531 is controller:inst8|Mux~4163 at LC6_G8
--operation mode is normal

H1L531 = H1L75 & G1_q[6];


--H1_offset[6] is controller:inst8|offset[6] at LC2_G8
--operation mode is normal

H1_offset[6] = H1L95 & (H1L68) # !H1L95 & H1_offset[6];

--H1L661 is controller:inst8|offset[6]~26 at LC2_G8
--operation mode is normal

H1L661 = H1L95 & (H1L68) # !H1L95 & H1_offset[6];


--H1L78 is controller:inst8|Mux~4109 at LC8_E17
--operation mode is normal

H1L78 = H1L75 & G1_q[4];

--H1L631 is controller:inst8|Mux~4164 at LC8_E17
--operation mode is normal

H1L631 = H1L75 & G1_q[4];


--H1_offset[4] is controller:inst8|offset[4] at LC6_E17
--operation mode is normal

H1_offset[4] = H1L95 & (H1L78) # !H1L95 & H1_offset[4];

--H1L261 is controller:inst8|offset[4]~27 at LC6_E17
--operation mode is normal

H1L261 = H1L95 & (H1L78) # !H1L95 & H1_offset[4];


--H1L88 is controller:inst8|Mux~4110 at LC7_G8
--operation mode is normal

H1L88 = H1L75 & G1_q[5];

--H1L731 is controller:inst8|Mux~4165 at LC7_G8
--operation mode is normal

H1L731 = H1L75 & G1_q[5];


--H1_offset[5] is controller:inst8|offset[5] at LC5_G8
--operation mode is normal

H1_offset[5] = H1L95 & (H1L88) # !H1L95 & H1_offset[5];

--H1L461 is controller:inst8|offset[5]~28 at LC5_G8
--operation mode is normal

H1L461 = H1L95 & (H1L88) # !H1L95 & H1_offset[5];


--H1L98 is controller:inst8|Mux~4111 at LC2_K8
--operation mode is normal

H1L98 = H1L75 & G1_q[3];

--H1L831 is controller:inst8|Mux~4166 at LC2_K8
--operation mode is normal

H1L831 = H1L75 & G1_q[3];


--H1_offset[3] is controller:inst8|offset[3] at LC1_K8
--operation mode is normal

H1_offset[3] = H1L95 & (H1L98) # !H1L95 & H1_offset[3];

--H1L061 is controller:inst8|offset[3]~29 at LC1_K8
--operation mode is normal

H1L061 = H1L95 & (H1L98) # !H1L95 & H1_offset[3];


--H1L09 is controller:inst8|Mux~4112 at LC7_H6
--operation mode is normal

H1L09 = H1L75 & G1_q[1];

--H1L931 is controller:inst8|Mux~4167 at LC7_H6
--operation mode is normal

H1L931 = H1L75 & G1_q[1];


--H1_offset[1] is controller:inst8|offset[1] at LC8_H6
--operation mode is normal

H1_offset[1] = H1L95 & (H1L09) # !H1L95 & H1_offset[1];

--H1L651 is controller:inst8|offset[1]~30 at LC8_H6
--operation mode is normal

H1L651 = H1L95 & (H1L09) # !H1L95 & H1_offset[1];


--H1L19 is controller:inst8|Mux~4113 at LC3_E17
--operation mode is normal

H1L19 = H1L75 & G1_q[0];

--H1L041 is controller:inst8|Mux~4168 at LC3_E17
--operation mode is normal

H1L041 = H1L75 & G1_q[0];


--H1_offset[0] is controller:inst8|offset[0] at LC7_E9
--operation mode is normal

H1_offset[0] = H1L95 & (H1L19) # !H1L95 & H1_offset[0];

--H1L451 is controller:inst8|offset[0]~31 at LC7_E9
--operation mode is normal

H1L451 = H1L95 & (H1L19) # !H1L95 & H1_offset[0];


--H1L312 is controller:inst8|reduce_or~545 at LC7_H20
--operation mode is normal

H1L312 = !G1_q[12] & !G1_q[13] & !G1_q[11] & H1L402;

--H1L822 is controller:inst8|reduce_or~560 at LC7_H20
--operation mode is normal

H1L822 = !G1_q[12] & !G1_q[13] & !G1_q[11] & H1L402;


--H1L412 is controller:inst8|reduce_or~546 at LC1_G52
--operation mode is normal

H1L412 = !G1_q[15] & (H1L312 # !G1_q[9] & H1L081);

--H1L922 is controller:inst8|reduce_or~561 at LC1_G52
--operation mode is normal

H1L922 = !G1_q[15] & (H1L312 # !G1_q[9] & H1L081);


--H1_sst[0] is controller:inst8|sst[0] at LC8_G52
--operation mode is normal

H1_sst[0] = H1L95 & (H1L412 # !H1L65) # !H1L95 & H1_sst[0];

--H1L462 is controller:inst8|sst[0]~23 at LC8_G52
--operation mode is normal

H1L462 = H1L95 & (H1L412 # !H1L65) # !H1L95 & H1_sst[0];


--H1L512 is controller:inst8|reduce_or~547 at LC3_G52
--operation mode is normal

H1L512 = !G1_q[15] & (H1L312 # H1L081 & G1_q[9]);

--H1L032 is controller:inst8|reduce_or~562 at LC3_G52
--operation mode is normal

H1L032 = !G1_q[15] & (H1L312 # H1L081 & G1_q[9]);


--H1_sst[1] is controller:inst8|sst[1] at LC2_G52
--operation mode is normal

H1_sst[1] = H1L95 & (H1L512 # !H1L65) # !H1L95 & H1_sst[1];

--H1L662 is controller:inst8|sst[1]~24 at LC2_G52
--operation mode is normal

H1L662 = H1L95 & (H1L512 # !H1L65) # !H1L95 & H1_sst[1];


--H1L29 is controller:inst8|Mux~4114 at LC7_H25
--operation mode is normal

H1L29 = F1_state.s0 & (F1_state.s1 $ (F1_state.s5 # F1_state.s4));

--H1L141 is controller:inst8|Mux~4169 at LC7_H25
--operation mode is normal

H1L141 = F1_state.s0 & (F1_state.s1 $ (F1_state.s5 # F1_state.s4));


--H1_rec[0] is controller:inst8|rec[0] at LC6_H47
--operation mode is normal

H1_rec[0] = H1L48 & (!F1_output[1] & H1L29) # !H1L48 & H1_rec[0];

--H1L171 is controller:inst8|rec[0]~41 at LC6_H47
--operation mode is normal

H1L171 = H1L48 & (!F1_output[1] & H1L29) # !H1L48 & H1_rec[0];


--H1L612 is controller:inst8|reduce_or~548 at LC5_H24
--operation mode is normal

H1L612 = G1_q[8] & (G1_q[14] # G1_q[9] $ G1_q[10]) # !G1_q[8] & G1_q[14] & (G1_q[10] # !G1_q[9]);

--H1L132 is controller:inst8|reduce_or~563 at LC5_H24
--operation mode is normal

H1L132 = G1_q[8] & (G1_q[14] # G1_q[9] $ G1_q[10]) # !G1_q[8] & G1_q[14] & (G1_q[10] # !G1_q[9]);


--H1L39 is controller:inst8|Mux~4115 at LC7_H24
--operation mode is normal

H1L39 = H1L612 & (H1L45 # H1L971 & G1_q[14]) # !H1L612 & H1L971 & G1_q[14];

--H1L241 is controller:inst8|Mux~4170 at LC7_H24
--operation mode is normal

H1L241 = H1L612 & (H1L45 # H1L971 & G1_q[14]) # !H1L612 & H1L971 & G1_q[14];


--H1L49 is controller:inst8|Mux~4116 at LC2_H24
--operation mode is normal

H1L49 = !F1_output[2] & !G1_q[15] & H1L39;

--H1L341 is controller:inst8|Mux~4171 at LC2_H24
--operation mode is normal

H1L341 = !F1_output[2] & !G1_q[15] & H1L39;


--H1L571 is controller:inst8|reduce_nor~24 at LC2_F2
--operation mode is normal

H1L571 = G1_q[8] # G1_q[9] # !H1L771;

--H1L891 is controller:inst8|reduce_nor~602 at LC2_F2
--operation mode is normal

H1L891 = G1_q[8] # G1_q[9] # !H1L771;


--H1L59 is controller:inst8|Mux~4117 at LC7_F2
--operation mode is normal

H1L59 = H1L49 # F1_output[2] & (!H1L671 # !H1L571);

--H1L441 is controller:inst8|Mux~4172 at LC7_F2
--operation mode is normal

H1L441 = H1L49 # F1_output[2] & (!H1L671 # !H1L571);


--H1_alu_out_sel[0] is controller:inst8|alu_out_sel[0] at LC8_F2
--operation mode is normal

H1_alu_out_sel[0] = H1L66 & (F1_output[1] & !H1L59) # !H1L66 & H1_alu_out_sel[0];

--H1L71 is controller:inst8|alu_out_sel[0]~20 at LC8_F2
--operation mode is normal

H1L71 = H1L66 & (F1_output[1] & !H1L59) # !H1L66 & H1_alu_out_sel[0];


--P1L1 is t1:inst31|alu_cin~65 at LC5_G43
--operation mode is normal

P1L1 = H1_sci[0] & (H1_sci[1]) # !H1_sci[0] & (!H1_sci[1] # !D1_flag_c);

--P1L4 is t1:inst31|alu_cin~69 at LC5_G43
--operation mode is normal

P1L4 = H1_sci[0] & (H1_sci[1]) # !H1_sci[0] & (!H1_sci[1] # !D1_flag_c);


--V6_cs_buffer[14] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] at LC5_G12
--operation mode is arithmetic

V6_cs_buffer[14] = N1L69 $ N1L351 $ V6_cout[13];

--V6L34 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~426 at LC5_G12
--operation mode is arithmetic

V6L34 = N1L69 $ N1L351 $ V6_cout[13];

--V6_cout[14] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] at LC5_G12
--operation mode is arithmetic

V6_cout[14] = CARRY(N1L69 & (V6_cout[13] # !N1L351) # !N1L69 & !N1L351 & V6_cout[13]);


--V6_cs_buffer[12] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] at LC3_G12
--operation mode is arithmetic

V6_cs_buffer[12] = N1L08 $ N1L941 $ V6_cout[11];

--V6L93 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~427 at LC3_G12
--operation mode is arithmetic

V6L93 = N1L08 $ N1L941 $ V6_cout[11];

--V6_cout[12] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] at LC3_G12
--operation mode is arithmetic

V6_cout[12] = CARRY(N1L08 & (V6_cout[11] # !N1L941) # !N1L08 & !N1L941 & V6_cout[11]);


--V6_cs_buffer[10] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC1_G12
--operation mode is arithmetic

V6_cs_buffer[10] = N1L46 $ N1L541 $ V6_cout[9];

--V6L53 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~428 at LC1_G12
--operation mode is arithmetic

V6L53 = N1L46 $ N1L541 $ V6_cout[9];

--V6_cout[10] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] at LC1_G12
--operation mode is arithmetic

V6_cout[10] = CARRY(N1L46 & (V6_cout[9] # !N1L541) # !N1L46 & !N1L541 & V6_cout[9]);


--V6_cs_buffer[4] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC3_G10
--operation mode is arithmetic

V6_cs_buffer[4] = N1L61 $ N1L331 $ V6_cout[3];

--V6L32 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~429 at LC3_G10
--operation mode is arithmetic

V6L32 = N1L61 $ N1L331 $ V6_cout[3];

--V6_cout[4] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] at LC3_G10
--operation mode is arithmetic

V6_cout[4] = CARRY(N1L61 & (V6_cout[3] # !N1L331) # !N1L61 & !N1L331 & V6_cout[3]);


--V6_cs_buffer[15] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] at LC6_G12
--operation mode is arithmetic

V6_cs_buffer[15] = N1L401 $ N1L551 $ V6_cout[14];

--V6L54 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~430 at LC6_G12
--operation mode is arithmetic

V6L54 = N1L401 $ N1L551 $ V6_cout[14];

--V6_cout[15] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] at LC6_G12
--operation mode is arithmetic

V6_cout[15] = CARRY(N1L401 & (V6_cout[14] # !N1L551) # !N1L401 & !N1L551 & V6_cout[14]);


--V6_cs_buffer[8] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC7_G10
--operation mode is arithmetic

V6_cs_buffer[8] = N1L84 $ N1L141 $ V6_cout[7];

--V6L13 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~431 at LC7_G10
--operation mode is arithmetic

V6L13 = N1L84 $ N1L141 $ V6_cout[7];

--V6_cout[8] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] at LC7_G10
--operation mode is arithmetic

V6_cout[8] = CARRY(N1L84 & (V6_cout[7] # !N1L141) # !N1L84 & !N1L141 & V6_cout[7]);


--V6_cs_buffer[6] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC5_G10
--operation mode is arithmetic

V6_cs_buffer[6] = N1L23 $ N1L731 $ V6_cout[5];

--V6L72 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~432 at LC5_G10
--operation mode is arithmetic

V6L72 = N1L23 $ N1L731 $ V6_cout[5];

--V6_cout[6] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] at LC5_G10
--operation mode is arithmetic

V6_cout[6] = CARRY(N1L23 & (V6_cout[5] # !N1L731) # !N1L23 & !N1L731 & V6_cout[5]);


--V6_cs_buffer[11] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC2_G12
--operation mode is arithmetic

V6_cs_buffer[11] = N1L27 $ N1L741 $ V6_cout[10];

--V6L73 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~433 at LC2_G12
--operation mode is arithmetic

V6L73 = N1L27 $ N1L741 $ V6_cout[10];

--V6_cout[11] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] at LC2_G12
--operation mode is arithmetic

V6_cout[11] = CARRY(N1L27 & (V6_cout[10] # !N1L741) # !N1L27 & !N1L741 & V6_cout[10]);


--V6_cs_buffer[9] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC8_G10
--operation mode is arithmetic

V6_cs_buffer[9] = N1L65 $ N1L341 $ V6_cout[8];

--V6L33 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~434 at LC8_G10
--operation mode is arithmetic

V6L33 = N1L65 $ N1L341 $ V6_cout[8];

--V6_cout[9] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] at LC8_G10
--operation mode is arithmetic

V6_cout[9] = CARRY(N1L65 & (V6_cout[8] # !N1L341) # !N1L65 & !N1L341 & V6_cout[8]);


--V6_cs_buffer[7] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC6_G10
--operation mode is arithmetic

V6_cs_buffer[7] = N1L04 $ N1L931 $ V6_cout[6];

--V6L92 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~435 at LC6_G10
--operation mode is arithmetic

V6L92 = N1L04 $ N1L931 $ V6_cout[6];

--V6_cout[7] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] at LC6_G10
--operation mode is arithmetic

V6_cout[7] = CARRY(N1L04 & (V6_cout[6] # !N1L931) # !N1L04 & !N1L931 & V6_cout[6]);


--V6_cs_buffer[5] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC4_G10
--operation mode is arithmetic

V6_cs_buffer[5] = N1L42 $ N1L531 $ V6_cout[4];

--V6L52 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~436 at LC4_G10
--operation mode is arithmetic

V6L52 = N1L42 $ N1L531 $ V6_cout[4];

--V6_cout[5] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] at LC4_G10
--operation mode is arithmetic

V6_cout[5] = CARRY(N1L42 & (V6_cout[4] # !N1L531) # !N1L42 & !N1L531 & V6_cout[4]);


--V6_cs_buffer[3] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC2_G10
--operation mode is arithmetic

V6_cs_buffer[3] = N1L8 $ N1L131 $ V6_cout[2];

--V6L12 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~437 at LC2_G10
--operation mode is arithmetic

V6L12 = N1L8 $ N1L131 $ V6_cout[2];

--V6_cout[3] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] at LC2_G10
--operation mode is arithmetic

V6_cout[3] = CARRY(N1L8 & (V6_cout[2] # !N1L131) # !N1L8 & !N1L131 & V6_cout[2]);


--M1L1 is reg_mux:inst27|dr[0]~486 at LC8_E14
--operation mode is normal

M1L1 = H1_dest_reg[3] & (L9_q[0] # H1_dest_reg[2]) # !H1_dest_reg[3] & L1_q[0] & (!H1_dest_reg[2]);

--M1L11 is reg_mux:inst27|dr[0]~646 at LC8_E14
--operation mode is normal

M1L11 = H1_dest_reg[3] & (L9_q[0] # H1_dest_reg[2]) # !H1_dest_reg[3] & L1_q[0] & (!H1_dest_reg[2]);


--M1L2 is reg_mux:inst27|dr[0]~487 at LC4_E14
--operation mode is normal

M1L2 = M1L1 & (L31_q[0] # !H1_dest_reg[2]) # !M1L1 & (H1_dest_reg[2] & L5_q[0]);

--M1L21 is reg_mux:inst27|dr[0]~647 at LC4_E14
--operation mode is normal

M1L21 = M1L1 & (L31_q[0] # !H1_dest_reg[2]) # !M1L1 & (H1_dest_reg[2] & L5_q[0]);


--M1L3 is reg_mux:inst27|dr[0]~488 at LC1_E15
--operation mode is normal

M1L3 = H1_dest_reg[2] & (L6_q[0] # H1_dest_reg[3]) # !H1_dest_reg[2] & L2_q[0] & (!H1_dest_reg[3]);

--M1L31 is reg_mux:inst27|dr[0]~648 at LC1_E15
--operation mode is normal

M1L31 = H1_dest_reg[2] & (L6_q[0] # H1_dest_reg[3]) # !H1_dest_reg[2] & L2_q[0] & (!H1_dest_reg[3]);


--M1L4 is reg_mux:inst27|dr[0]~489 at LC2_E15
--operation mode is normal

M1L4 = M1L3 & (L41_q[0] # !H1_dest_reg[3]) # !M1L3 & (H1_dest_reg[3] & L01_q[0]);

--M1L41 is reg_mux:inst27|dr[0]~649 at LC2_E15
--operation mode is normal

M1L41 = M1L3 & (L41_q[0] # !H1_dest_reg[3]) # !M1L3 & (H1_dest_reg[3] & L01_q[0]);


--M1L5 is reg_mux:inst27|dr[0]~490 at LC3_E15
--operation mode is normal

M1L5 = H1_dest_reg[2] & (L4_q[0] # H1_dest_reg[3]) # !H1_dest_reg[2] & L61_q[0] & (!H1_dest_reg[3]);

--M1L51 is reg_mux:inst27|dr[0]~650 at LC3_E15
--operation mode is normal

M1L51 = H1_dest_reg[2] & (L4_q[0] # H1_dest_reg[3]) # !H1_dest_reg[2] & L61_q[0] & (!H1_dest_reg[3]);


--M1L6 is reg_mux:inst27|dr[0]~491 at LC4_E15
--operation mode is normal

M1L6 = M1L5 & (L21_q[0] # !H1_dest_reg[3]) # !M1L5 & (H1_dest_reg[3] & L8_q[0]);

--M1L61 is reg_mux:inst27|dr[0]~651 at LC4_E15
--operation mode is normal

M1L61 = M1L5 & (L21_q[0] # !H1_dest_reg[3]) # !M1L5 & (H1_dest_reg[3] & L8_q[0]);


--M1L7 is reg_mux:inst27|dr[0]~492 at LC7_E15
--operation mode is normal

M1L7 = H1_dest_reg[1] & (M1L4 # H1_dest_reg[0]) # !H1_dest_reg[1] & M1L6 & (!H1_dest_reg[0]);

--M1L71 is reg_mux:inst27|dr[0]~652 at LC7_E15
--operation mode is normal

M1L71 = H1_dest_reg[1] & (M1L4 # H1_dest_reg[0]) # !H1_dest_reg[1] & M1L6 & (!H1_dest_reg[0]);


--M1L8 is reg_mux:inst27|dr[0]~493 at LC8_E11
--operation mode is normal

M1L8 = H1_dest_reg[3] & (L11_q[0] # H1_dest_reg[2]) # !H1_dest_reg[3] & L3_q[0] & (!H1_dest_reg[2]);

--M1L81 is reg_mux:inst27|dr[0]~653 at LC8_E11
--operation mode is normal

M1L81 = H1_dest_reg[3] & (L11_q[0] # H1_dest_reg[2]) # !H1_dest_reg[3] & L3_q[0] & (!H1_dest_reg[2]);


--M1L9 is reg_mux:inst27|dr[0]~494 at LC2_E11
--operation mode is normal

M1L9 = M1L8 & (L51_q[0] # !H1_dest_reg[2]) # !M1L8 & (H1_dest_reg[2] & L7_q[0]);

--M1L91 is reg_mux:inst27|dr[0]~654 at LC2_E11
--operation mode is normal

M1L91 = M1L8 & (L51_q[0] # !H1_dest_reg[2]) # !M1L8 & (H1_dest_reg[2] & L7_q[0]);


--M1L01 is reg_mux:inst27|dr[0]~495 at LC8_E15
--operation mode is normal

M1L01 = M1L7 & (M1L9 # !H1_dest_reg[0]) # !M1L7 & (H1_dest_reg[0] & M1L2);

--M1L02 is reg_mux:inst27|dr[0]~655 at LC8_E15
--operation mode is normal

M1L02 = M1L7 & (M1L9 # !H1_dest_reg[0]) # !M1L7 & (H1_dest_reg[0] & M1L2);


--N1L1 is bus_mux:inst28|alu_dr[0]~2347 at LC5_E15
--operation mode is normal

N1L1 = M1L01 & !N1L911 & (!N1L021 # !K1_q[0]) # !M1L01 & (!N1L021 # !K1_q[0]);

--N1L3 is bus_mux:inst28|alu_dr[0]~2415 at LC5_E15
--operation mode is normal

N1L3 = M1L01 & !N1L911 & (!N1L021 # !K1_q[0]) # !M1L01 & (!N1L021 # !K1_q[0]);

--N1L4 is bus_mux:inst28|alu_dr[0]~2416 at LC5_E15
--operation mode is normal

N1L4 = M1L01 & !N1L911 & (!N1L021 # !K1_q[0]) # !M1L01 & (!N1L021 # !K1_q[0]);


--N1L2 is bus_mux:inst28|alu_dr[0]~2364 at LC6_E15
--operation mode is normal

N1L2 = (H1_alu_in_sel[0] & !A1L25 # !H1_alu_in_sel[0] & (!K1_q[0]) # !N1L811) & CASCADE(N1L4);

--N1L5 is bus_mux:inst28|alu_dr[0]~2417 at LC6_E15
--operation mode is normal

N1L5 = (H1_alu_in_sel[0] & !A1L25 # !H1_alu_in_sel[0] & (!K1_q[0]) # !N1L811) & CASCADE(N1L4);


--V6_cs_buffer[2] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC1_G10
--operation mode is arithmetic

V6_cs_buffer[2] = N1L921 $ !N1L2;

--V6L91 is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~438 at LC1_G10
--operation mode is arithmetic

V6L91 = N1L921 $ !N1L2;

--V6_cout[2] is alu:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] at LC1_G10
--operation mode is arithmetic

V6_cout[2] = CARRY(!N1L2 # !N1L921);


--V3_cs_buffer[0] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] at LC5_G19
--operation mode is arithmetic

V3_cs_buffer[0] = P1L2 # !P1L3;

--V3L02 is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~307 at LC5_G19
--operation mode is arithmetic

V3L02 = P1L2 # !P1L3;

--V3_cout[0] is alu:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] at LC5_G19
--operation mode is arithmetic

V3_cout[0] = CARRY(P1L3 & !P1L2);


--H1L732 is controller:inst8|Select~320 at LC8_F9
--operation mode is normal

H1L732 = !G1_q[11] & H1L581 & G1_q[14] & G1_q[10];

--H1L442 is controller:inst8|Select~331 at LC8_F9
--operation mode is normal

H1L442 = !G1_q[11] & H1L581 & G1_q[14] & G1_q[10];


--H1L832 is controller:inst8|Select~321 at LC3_F18
--operation mode is normal

H1L832 = !G1_q[9] & !D1_flag_c & G1_q[8] & H1L732;

--H1L542 is controller:inst8|Select~332 at LC3_F18
--operation mode is normal

H1L542 = !G1_q[9] & !D1_flag_c & G1_q[8] & H1L732;


--H1L932 is controller:inst8|Select~322 at LC6_F18
--operation mode is normal

H1L932 = !G1_q[8] & G1_q[9] & D1_flag_z & H1L732;

--H1L642 is controller:inst8|Select~333 at LC6_F18
--operation mode is normal

H1L642 = !G1_q[8] & G1_q[9] & D1_flag_z & H1L732;


--H1L92 is controller:inst8|en_pc~412 at LC8_F18
--operation mode is normal

H1L92 = !H1L932 & !H1L832 & H1L53 & H1L43;

--H1L73 is controller:inst8|en_pc~428 at LC8_F18
--operation mode is normal

H1L73 = !H1L932 & !H1L832 & H1L53 & H1L43;


--H1L03 is controller:inst8|en_pc~413 at LC5_H16
--operation mode is normal

H1L03 = F1_output[1] & H1L92 & (H1L481 # !H1_alu_out_sel[1]);

--H1L83 is controller:inst8|en_pc~429 at LC5_H16
--operation mode is normal

H1L83 = F1_output[1] & H1L92 & (H1L481 # !H1_alu_out_sel[1]);


--H1L13 is controller:inst8|en_pc~414 at LC6_H16
--operation mode is normal

H1L13 = F1_output[2] # H1L03 # F1L6 $ !F1_output[1];

--H1L93 is controller:inst8|en_pc~430 at LC6_H16
--operation mode is normal

H1L93 = F1_output[2] # H1L03 # F1L6 $ !F1_output[1];

--H1L04 is controller:inst8|en_pc~431 at LC6_H16
--operation mode is normal

H1L04 = F1_output[2] # H1L03 # F1L6 $ !F1_output[1];


--H1L23 is controller:inst8|en_pc~415 at LC8_H16
--operation mode is normal

H1L23 = !G1_q[9] & H1L771 & (!G1_q[8] # !F1_output[1]);

--H1L14 is controller:inst8|en_pc~432 at LC8_H16
--operation mode is normal

H1L14 = !G1_q[9] & H1L771 & (!G1_q[8] # !F1_output[1]);


--H1L33 is controller:inst8|en_pc~423 at LC7_H16
--operation mode is normal

H1L33 = (!H1L23 & (H1L771 # !H1_alu_out_sel[1]) # !H1L56) & CASCADE(H1L04);

--H1L24 is controller:inst8|en_pc~433 at LC7_H16
--operation mode is normal

H1L24 = (!H1L23 & (H1L771 # !H1_alu_out_sel[1]) # !H1L56) & CASCADE(H1L04);


--H1L471 is controller:inst8|reduce_nor~12 at LC3_G44
--operation mode is normal

H1L471 = !G1_q[9] & G1_q[11] & H1L67 & G1_q[10];

--H1L991 is controller:inst8|reduce_nor~603 at LC3_G44
--operation mode is normal

H1L991 = !G1_q[9] & G1_q[11] & H1L67 & G1_q[10];


--H1L69 is controller:inst8|Mux~4118 at LC8_H37
--operation mode is normal

H1L69 = !F1L6 & F1_output[1] & (H1L481 # F1_output[2]);

--H1L541 is controller:inst8|Mux~4173 at LC8_H37
--operation mode is normal

H1L541 = !F1L6 & F1_output[1] & (H1L481 # F1_output[2]);


--H1L79 is controller:inst8|Mux~4119 at LC2_H37
--operation mode is normal

H1L79 = H1L69 # !F1_output[1] & (H1L771 # !H1L56);

--H1L641 is controller:inst8|Mux~4174 at LC2_H37
--operation mode is normal

H1L641 = H1L69 # !F1_output[1] & (H1L771 # !H1L56);


--H1_sci[1] is controller:inst8|sci[1] at LC1_G43
--operation mode is normal

H1_sci[1] = H1L79 & (H1L65 & H1L471) # !H1L79 & H1_sci[1];

--H1L632 is controller:inst8|sci[1]~23 at LC1_G43
--operation mode is normal

H1L632 = H1L79 & (H1L65 & H1L471) # !H1L79 & H1_sci[1];


--H1L681 is controller:inst8|reduce_nor~590 at LC4_G48
--operation mode is normal

H1L681 = !G1_q[9] & G1_q[11] & H1L67;

--H1L002 is controller:inst8|reduce_nor~604 at LC4_G48
--operation mode is normal

H1L002 = !G1_q[9] & G1_q[11] & H1L67;


--H1L89 is controller:inst8|Mux~4120 at LC2_G43
--operation mode is normal

H1L89 = F1_output[1] & !G1_q[10] & H1L681 # !F1_output[1] & (H1L28);

--H1L741 is controller:inst8|Mux~4175 at LC2_G43
--operation mode is normal

H1L741 = F1_output[1] & !G1_q[10] & H1L681 # !F1_output[1] & (H1L28);


--H1L99 is controller:inst8|Mux~4121 at LC3_G43
--operation mode is normal

H1L99 = F1L6 & !F1_output[1] & !F1_output[2] # !F1L6 & H1L89 & (F1_output[1] $ F1_output[2]);

--H1L841 is controller:inst8|Mux~4176 at LC3_G43
--operation mode is normal

H1L841 = F1L6 & !F1_output[1] & !F1_output[2] # !F1L6 & H1L89 & (F1_output[1] $ F1_output[2]);


--H1_sci[0] is controller:inst8|sci[0] at LC6_G43
--operation mode is normal

H1_sci[0] = H1L79 & (H1L99) # !H1L79 & H1_sci[0];

--H1L432 is controller:inst8|sci[0]~24 at LC6_G43
--operation mode is normal

H1L432 = H1L79 & (H1L99) # !H1L79 & H1_sci[0];


--D1L11 is flag_reg:inst2|Mux~662 at LC1_G33
--operation mode is normal

D1L11 = H1_alu_func[1] & !N1L2 & (!H1_alu_func[0]) # !H1_alu_func[1] & (!N1L221 & H1_alu_func[0]);

--D1L22 is flag_reg:inst2|Mux~676 at LC1_G33
--operation mode is normal

D1L22 = H1_alu_func[1] & !N1L2 & (!H1_alu_func[0]) # !H1_alu_func[1] & (!N1L221 & H1_alu_func[0]);


--D1L21 is flag_reg:inst2|Mux~663 at LC8_G27
--operation mode is normal

D1L21 = !H1_sst[0] & !H1_alu_func[2] & !H1_alu_func[1] & N1L061;

--D1L32 is flag_reg:inst2|Mux~677 at LC8_G27
--operation mode is normal

D1L32 = !H1_sst[0] & !H1_alu_func[2] & !H1_alu_func[1] & N1L061;


--D1L31 is flag_reg:inst2|Mux~664 at LC2_G27
--operation mode is normal

D1L31 = D1L21 & (H1_alu_func[0] & (N1L221) # !H1_alu_func[0] & !T4_unreg_res_node[16]);

--D1L42 is flag_reg:inst2|Mux~678 at LC2_G27
--operation mode is normal

D1L42 = D1L21 & (H1_alu_func[0] & (N1L221) # !H1_alu_func[0] & !T4_unreg_res_node[16]);


--D1L41 is flag_reg:inst2|Mux~665 at LC2_G33
--operation mode is normal

D1L41 = D1L31 # H1_sst[1] & (D1_flag_c # !H1_sst[0]);

--D1L52 is flag_reg:inst2|Mux~679 at LC2_G33
--operation mode is normal

D1L52 = D1L31 # H1_sst[1] & (D1_flag_c # !H1_sst[0]);


--D1L51 is flag_reg:inst2|Mux~666 at LC6_G33
--operation mode is normal

D1L51 = !D1L41 & (H1_sst[0] # !D1L11 # !H1_alu_func[2]);

--D1L62 is flag_reg:inst2|Mux~680 at LC6_G33
--operation mode is normal

D1L62 = !D1L41 & (H1_sst[0] # !D1L11 # !H1_alu_func[2]);

--D1L72 is flag_reg:inst2|Mux~681 at LC6_G33
--operation mode is normal

D1L72 = !D1L41 & (H1_sst[0] # !D1L11 # !H1_alu_func[2]);


--V21_cs_buffer[14] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] at LC6_G17
--operation mode is arithmetic

V21_cs_buffer[14] = V21_cout[13] $ (N1L501 # N1L201);

--V21L54 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~356 at LC6_G17
--operation mode is arithmetic

V21L54 = V21_cout[13] $ (N1L501 # N1L201);

--V21_cout[14] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14] at LC6_G17
--operation mode is arithmetic

V21_cout[14] = CARRY(V21_cout[13] # !N1L501 & !N1L201);


--V21_cs_buffer[15] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] at LC7_G17
--operation mode is arithmetic

V21_cs_buffer[15] = V21_cout[14] $ (N1L311 # N1L011);

--V21L74 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~357 at LC7_G17
--operation mode is arithmetic

V21L74 = V21_cout[14] $ (N1L311 # N1L011);

--V21_cout[15] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15] at LC7_G17
--operation mode is arithmetic

V21_cout[15] = CARRY(V21_cout[14] # !N1L311 & !N1L011);


--B1L751 is alu:inst|LessThan~3009 at LC1_G18
--operation mode is normal

B1L751 = V21_cs_buffer[15] & N1L751 & (V21_cs_buffer[14] $ !N1L551) # !V21_cs_buffer[15] & !N1L751 & (V21_cs_buffer[14] $ !N1L551);

--B1L202 is alu:inst|LessThan~3098 at LC1_G18
--operation mode is normal

B1L202 = V21_cs_buffer[15] & N1L751 & (V21_cs_buffer[14] $ !N1L551) # !V21_cs_buffer[15] & !N1L751 & (V21_cs_buffer[14] $ !N1L551);


--V21_cs_buffer[13] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC5_G17
--operation mode is arithmetic

V21_cs_buffer[13] = V21_cout[12] $ (N1L79 # N1L49);

--V21L34 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~358 at LC5_G17
--operation mode is arithmetic

V21L34 = V21_cout[12] $ (N1L79 # N1L49);

--V21_cout[13] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13] at LC5_G17
--operation mode is arithmetic

V21_cout[13] = CARRY(V21_cout[12] # !N1L79 & !N1L49);


--B1L851 is alu:inst|LessThan~3010 at LC4_G18
--operation mode is normal

B1L851 = B1L751 & (V21_cs_buffer[13] $ !N1L351);

--B1L302 is alu:inst|LessThan~3099 at LC4_G18
--operation mode is normal

B1L302 = B1L751 & (V21_cs_buffer[13] $ !N1L351);


--V21_cs_buffer[12] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] at LC4_G17
--operation mode is arithmetic

V21_cs_buffer[12] = V21_cout[11] $ (N1L98 # N1L68);

--V21L14 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~359 at LC4_G17
--operation mode is arithmetic

V21L14 = V21_cout[11] $ (N1L98 # N1L68);

--V21_cout[12] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12] at LC4_G17
--operation mode is arithmetic

V21_cout[12] = CARRY(V21_cout[11] # !N1L98 & !N1L68);


--B1L951 is alu:inst|LessThan~3011 at LC5_G18
--operation mode is normal

B1L951 = B1L851 & (V21_cs_buffer[12] $ !N1L151);

--B1L402 is alu:inst|LessThan~3100 at LC5_G18
--operation mode is normal

B1L402 = B1L851 & (V21_cs_buffer[12] $ !N1L151);


--V21_cs_buffer[11] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC3_G17
--operation mode is arithmetic

V21_cs_buffer[11] = V21_cout[10] $ (N1L18 # N1L87);

--V21L93 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~360 at LC3_G17
--operation mode is arithmetic

V21L93 = V21_cout[10] $ (N1L18 # N1L87);

--V21_cout[11] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11] at LC3_G17
--operation mode is arithmetic

V21_cout[11] = CARRY(V21_cout[10] # !N1L18 & !N1L87);


--B1L061 is alu:inst|LessThan~3012 at LC6_G18
--operation mode is normal

B1L061 = B1L951 & (V21_cs_buffer[11] $ !N1L941);

--B1L502 is alu:inst|LessThan~3101 at LC6_G18
--operation mode is normal

B1L502 = B1L951 & (V21_cs_buffer[11] $ !N1L941);


--V21_cs_buffer[10] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC2_G17
--operation mode is arithmetic

V21_cs_buffer[10] = V21_cout[9] $ (N1L37 # N1L07);

--V21L73 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~361 at LC2_G17
--operation mode is arithmetic

V21L73 = V21_cout[9] $ (N1L37 # N1L07);

--V21_cout[10] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10] at LC2_G17
--operation mode is arithmetic

V21_cout[10] = CARRY(V21_cout[9] # !N1L37 & !N1L07);


--B1L161 is alu:inst|LessThan~3013 at LC3_G18
--operation mode is normal

B1L161 = B1L061 & (V21_cs_buffer[10] $ !N1L741);

--B1L602 is alu:inst|LessThan~3102 at LC3_G18
--operation mode is normal

B1L602 = B1L061 & (V21_cs_buffer[10] $ !N1L741);


--V21_cs_buffer[9] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC1_G17
--operation mode is arithmetic

V21_cs_buffer[9] = V21_cout[8] $ (N1L56 # N1L26);

--V21L53 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~362 at LC1_G17
--operation mode is arithmetic

V21L53 = V21_cout[8] $ (N1L56 # N1L26);

--V21_cout[9] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9] at LC1_G17
--operation mode is arithmetic

V21_cout[9] = CARRY(V21_cout[8] # !N1L56 & !N1L26);


--B1L261 is alu:inst|LessThan~3015 at LC4_G33
--operation mode is normal

B1L261 = B1L161 & (V21_cs_buffer[9] & !B1L591 & N1L541 # !V21_cs_buffer[9] & (N1L541 # !B1L591));

--B1L702 is alu:inst|LessThan~3103 at LC4_G33
--operation mode is normal

B1L702 = B1L161 & (V21_cs_buffer[9] & !B1L591 & N1L541 # !V21_cs_buffer[9] & (N1L541 # !B1L591));


--B1L361 is alu:inst|LessThan~3016 at LC8_G18
--operation mode is normal

B1L361 = !V21_cs_buffer[11] & N1L941 & B1L951;

--B1L802 is alu:inst|LessThan~3104 at LC8_G18
--operation mode is normal

B1L802 = !V21_cs_buffer[11] & N1L941 & B1L951;


--B1L461 is alu:inst|LessThan~3017 at LC2_G18
--operation mode is normal

B1L461 = B1L361 # !V21_cs_buffer[10] & N1L741 & B1L061;

--B1L902 is alu:inst|LessThan~3105 at LC2_G18
--operation mode is normal

B1L902 = B1L361 # !V21_cs_buffer[10] & N1L741 & B1L061;


--B1L561 is alu:inst|LessThan~3018 at LC7_G18
--operation mode is normal

B1L561 = !V21_cs_buffer[13] & N1L351 & B1L751;

--B1L012 is alu:inst|LessThan~3106 at LC7_G18
--operation mode is normal

B1L012 = !V21_cs_buffer[13] & N1L351 & B1L751;


--B1L661 is alu:inst|LessThan~3019 at LC1_G20
--operation mode is normal

B1L661 = !V21_cs_buffer[14] & N1L551 & (V21_cs_buffer[15] $ !N1L751);

--B1L112 is alu:inst|LessThan~3107 at LC1_G20
--operation mode is normal

B1L112 = !V21_cs_buffer[14] & N1L551 & (V21_cs_buffer[15] $ !N1L751);


--B1L761 is alu:inst|LessThan~3020 at LC4_G20
--operation mode is normal

B1L761 = B1L661 # B1L561 # !V21_cs_buffer[15] & N1L751;

--B1L212 is alu:inst|LessThan~3108 at LC4_G20
--operation mode is normal

B1L212 = B1L661 # B1L561 # !V21_cs_buffer[15] & N1L751;


--B1L861 is alu:inst|LessThan~3021 at LC5_G20
--operation mode is normal

B1L861 = B1L761 # !V21_cs_buffer[12] & N1L151 & B1L851;

--B1L312 is alu:inst|LessThan~3109 at LC5_G20
--operation mode is normal

B1L312 = B1L761 # !V21_cs_buffer[12] & N1L151 & B1L851;


--B1L961 is alu:inst|LessThan~3022 at LC5_G33
--operation mode is normal

B1L961 = B1L861 # B1L461 # B1L261;

--B1L412 is alu:inst|LessThan~3110 at LC5_G33
--operation mode is normal

B1L412 = B1L861 # B1L461 # B1L261;


--D1L61 is flag_reg:inst2|Mux~667 at LC8_G28
--operation mode is normal

D1L61 = !H1_sst[0] & !H1_alu_func[2] & !H1_alu_func[0] & !H1_alu_func[1];

--D1L82 is flag_reg:inst2|Mux~682 at LC8_G28
--operation mode is normal

D1L82 = !H1_sst[0] & !H1_alu_func[2] & !H1_alu_func[0] & !H1_alu_func[1];


--D1L81 is flag_reg:inst2|Mux~670 at LC7_G33
--operation mode is normal

D1L81 = (T4_unreg_res_node[16] $ N1L061 # !B1L961 # !D1L61) & CASCADE(D1L72);

--D1L92 is flag_reg:inst2|Mux~683 at LC7_G33
--operation mode is normal

D1L92 = (T4_unreg_res_node[16] $ N1L061 # !B1L961 # !D1L61) & CASCADE(D1L72);

--D1L03 is flag_reg:inst2|Mux~684 at LC7_G33
--operation mode is normal

D1L03 = (T4_unreg_res_node[16] $ N1L061 # !B1L961 # !D1L61) & CASCADE(D1L72);


--B1L071 is alu:inst|LessThan~3025 at LC7_G20
--operation mode is normal

B1L071 = N1L751 & N1L211 & (N1L551 $ !N1L401) # !N1L751 & !N1L211 & (N1L551 $ !N1L401);

--B1L512 is alu:inst|LessThan~3111 at LC7_G20
--operation mode is normal

B1L512 = N1L751 & N1L211 & (N1L551 $ !N1L401) # !N1L751 & !N1L211 & (N1L551 $ !N1L401);


--B1L171 is alu:inst|LessThan~3026 at LC6_G20
--operation mode is normal

B1L171 = B1L071 & (N1L351 $ !N1L69);

--B1L612 is alu:inst|LessThan~3112 at LC6_G20
--operation mode is normal

B1L612 = B1L071 & (N1L351 $ !N1L69);


--B1L271 is alu:inst|LessThan~3027 at LC4_G38
--operation mode is normal

B1L271 = B1L171 & (N1L151 $ !N1L88);

--B1L712 is alu:inst|LessThan~3113 at LC4_G38
--operation mode is normal

B1L712 = B1L171 & (N1L151 $ !N1L88);


--B1L371 is alu:inst|LessThan~3028 at LC5_G38
--operation mode is normal

B1L371 = B1L271 & (N1L941 $ !N1L08);

--B1L812 is alu:inst|LessThan~3114 at LC5_G38
--operation mode is normal

B1L812 = B1L271 & (N1L941 $ !N1L08);


--B1L471 is alu:inst|LessThan~3029 at LC6_G38
--operation mode is normal

B1L471 = B1L371 & (N1L741 $ !N1L27);

--B1L912 is alu:inst|LessThan~3115 at LC6_G38
--operation mode is normal

B1L912 = B1L371 & (N1L741 $ !N1L27);


--B1L491 is alu:inst|LessThan~3082 at LC3_G38
--operation mode is normal

B1L491 = (B1L791 # N1L541 $ N1L46 # !B1L471) & CASCADE(B1L332);

--B1L022 is alu:inst|LessThan~3116 at LC3_G38
--operation mode is normal

B1L022 = (B1L791 # N1L541 $ N1L46 # !B1L471) & CASCADE(B1L332);


--H1_alu_out_sel[1] is controller:inst8|alu_out_sel[1] at LC7_F18
--operation mode is normal

H1_alu_out_sel[1] = H1L66 & (!H1L101) # !H1L66 & H1_alu_out_sel[1];

--H1L91 is controller:inst8|alu_out_sel[1]~21 at LC7_F18
--operation mode is normal

H1L91 = H1L66 & (!H1L101) # !H1L66 & H1_alu_out_sel[1];


--T4_unreg_res_node[16] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[16] at LC8_G17
--operation mode is normal

T4_unreg_res_node[16] = V21_cout[15] $ !N1L221;

--T4L3 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[16]~33 at LC8_G17
--operation mode is normal

T4L3 = V21_cout[15] $ !N1L221;


--P1L2 is t1:inst31|alu_cin~66 at LC4_G43
--operation mode is normal

P1L2 = !D1_flag_c & H1_sci[1];

--P1L5 is t1:inst31|alu_cin~70 at LC4_G43
--operation mode is normal

P1L5 = !D1_flag_c & H1_sci[1];


--P1L3 is t1:inst31|alu_cin~67 at LC7_G43
--operation mode is normal

P1L3 = H1_sci[0] $ H1_sci[1];

--P1L6 is t1:inst31|alu_cin~71 at LC7_G43
--operation mode is normal

P1L6 = H1_sci[0] $ H1_sci[1];


--H1L042 is controller:inst8|Select~325 at LC1_F18
--operation mode is normal

H1L042 = D1_flag_z # !H1L732 # !G1_q[9] # !G1_q[8];

--H1L742 is controller:inst8|Select~334 at LC1_F18
--operation mode is normal

H1L742 = D1_flag_z # !H1L732 # !G1_q[9] # !G1_q[8];

--H1L842 is controller:inst8|Select~335 at LC1_F18
--operation mode is normal

H1L842 = D1_flag_z # !H1L732 # !G1_q[9] # !G1_q[8];


--H1L43 is controller:inst8|en_pc~424 at LC2_F18
--operation mode is normal

H1L43 = (G1_q[8] # G1_q[9] # !H1L732 # !D1_flag_c) & CASCADE(H1L842);

--H1L34 is controller:inst8|en_pc~434 at LC2_F18
--operation mode is normal

H1L34 = (G1_q[8] # G1_q[9] # !H1L732 # !D1_flag_c) & CASCADE(H1L842);


--H1L781 is controller:inst8|reduce_nor~591 at LC3_F3
--operation mode is normal

H1L781 = !G1_q[11] & !G1_q[10] & H1L581 & G1_q[14];

--H1L102 is controller:inst8|reduce_nor~605 at LC3_F3
--operation mode is normal

H1L102 = !G1_q[11] & !G1_q[10] & H1L581 & G1_q[14];


--H1L142 is controller:inst8|Select~326 at LC1_F3
--operation mode is normal

H1L142 = G1_q[9] # !H1L781 # !D1_flag_s # !G1_q[8];

--H1L942 is controller:inst8|Select~336 at LC1_F3
--operation mode is normal

H1L942 = G1_q[9] # !H1L781 # !D1_flag_s # !G1_q[8];

--H1L052 is controller:inst8|Select~337 at LC1_F3
--operation mode is normal

H1L052 = G1_q[9] # !H1L781 # !D1_flag_s # !G1_q[8];


--H1L242 is controller:inst8|Select~327 at LC4_F3
--operation mode is normal

H1L242 = !G1_q[10] & !D1_flag_s & G1_q[9] & G1_q[8];

--H1L152 is controller:inst8|Select~338 at LC4_F3
--operation mode is normal

H1L152 = !G1_q[10] & !D1_flag_s & G1_q[9] & G1_q[8];


--H1L342 is controller:inst8|Select~328 at LC5_F3
--operation mode is normal

H1L342 = !G1_q[11] & H1L242 & H1L581 & G1_q[14];

--H1L252 is controller:inst8|Select~339 at LC5_F3
--operation mode is normal

H1L252 = !G1_q[11] & H1L242 & H1L581 & G1_q[14];


--H1L53 is controller:inst8|en_pc~425 at LC2_F3
--operation mode is normal

H1L53 = (!H1L342 & (G1_q[8] # G1_q[9] # !H1L781)) & CASCADE(H1L052);

--H1L44 is controller:inst8|en_pc~435 at LC2_F3
--operation mode is normal

H1L44 = (!H1L342 & (G1_q[8] # G1_q[9] # !H1L781)) & CASCADE(H1L052);


--N1L501 is bus_mux:inst28|alu_dr[13]~2349 at LC7_C16
--operation mode is normal

N1L501 = N1L301 # !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L072;

--N1L901 is bus_mux:inst28|alu_dr[13]~2418 at LC7_C16
--operation mode is normal

N1L901 = N1L301 # !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L072;


--N1L311 is bus_mux:inst28|alu_dr[14]~2350 at LC1_F10
--operation mode is normal

N1L311 = N1L111 # !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L092;

--N1L711 is bus_mux:inst28|alu_dr[14]~2419 at LC1_F10
--operation mode is normal

N1L711 = N1L111 # !H1_alu_in_sel[0] & !H1_alu_in_sel[2] & M1L092;


--N1L79 is bus_mux:inst28|alu_dr[12]~2351 at LC3_E12
--operation mode is normal

N1L79 = N1L59 # K1_q[12] & N1L021;

--N1L101 is bus_mux:inst28|alu_dr[12]~2420 at LC3_E12
--operation mode is normal

N1L101 = N1L59 # K1_q[12] & N1L021;


--N1L98 is bus_mux:inst28|alu_dr[11]~2352 at LC1_H38
--operation mode is normal

N1L98 = N1L78 # K1_q[11] & N1L021;

--N1L39 is bus_mux:inst28|alu_dr[11]~2421 at LC1_H38
--operation mode is normal

N1L39 = N1L78 # K1_q[11] & N1L021;


--N1L18 is bus_mux:inst28|alu_dr[10]~2353 at LC1_D15
--operation mode is normal

N1L18 = N1L97 # K1_q[10] & N1L021;

--N1L58 is bus_mux:inst28|alu_dr[10]~2422 at LC1_D15
--operation mode is normal

N1L58 = N1L97 # K1_q[10] & N1L021;


--N1L37 is bus_mux:inst28|alu_dr[9]~2354 at LC1_H34
--operation mode is normal

N1L37 = N1L17 # K1_q[9] & N1L021;

--N1L77 is bus_mux:inst28|alu_dr[9]~2423 at LC1_H34
--operation mode is normal

N1L77 = N1L17 # K1_q[9] & N1L021;


--V21_cs_buffer[5] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC5_G15
--operation mode is arithmetic

V21_cs_buffer[5] = V21_cout[4] $ (N1L33 # N1L03);

--V21L72 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~363 at LC5_G15
--operation mode is arithmetic

V21L72 = V21_cout[4] $ (N1L33 # N1L03);

--V21_cout[5] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5] at LC5_G15
--operation mode is arithmetic

V21_cout[5] = CARRY(V21_cout[4] # !N1L33 & !N1L03);


--V21_cs_buffer[7] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC7_G15
--operation mode is arithmetic

V21_cs_buffer[7] = V21_cout[6] $ (N1L94 # N1L64);

--V21L13 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~364 at LC7_G15
--operation mode is arithmetic

V21L13 = V21_cout[6] $ (N1L94 # N1L64);

--V21_cout[7] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7] at LC7_G15
--operation mode is arithmetic

V21_cout[7] = CARRY(V21_cout[6] # !N1L94 & !N1L64);


--V21_cs_buffer[8] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC8_G15
--operation mode is arithmetic

V21_cs_buffer[8] = V21_cout[7] $ (N1L75 # N1L45);

--V21L33 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~365 at LC8_G15
--operation mode is arithmetic

V21L33 = V21_cout[7] $ (N1L75 # N1L45);

--V21_cout[8] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8] at LC8_G15
--operation mode is arithmetic

V21_cout[8] = CARRY(V21_cout[7] # !N1L75 & !N1L45);


--B1L571 is alu:inst|LessThan~3040 at LC1_G14
--operation mode is normal

B1L571 = V21_cs_buffer[8] & N1L341 & (V21_cs_buffer[7] $ !N1L141) # !V21_cs_buffer[8] & !N1L341 & (V21_cs_buffer[7] $ !N1L141);

--B1L122 is alu:inst|LessThan~3117 at LC1_G14
--operation mode is normal

B1L122 = V21_cs_buffer[8] & N1L341 & (V21_cs_buffer[7] $ !N1L141) # !V21_cs_buffer[8] & !N1L341 & (V21_cs_buffer[7] $ !N1L141);


--V21_cs_buffer[6] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC6_G15
--operation mode is arithmetic

V21_cs_buffer[6] = V21_cout[5] $ (N1L14 # N1L83);

--V21L92 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~366 at LC6_G15
--operation mode is arithmetic

V21L92 = V21_cout[5] $ (N1L14 # N1L83);

--V21_cout[6] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6] at LC6_G15
--operation mode is arithmetic

V21_cout[6] = CARRY(V21_cout[5] # !N1L14 & !N1L83);


--B1L671 is alu:inst|LessThan~3041 at LC2_G14
--operation mode is normal

B1L671 = B1L571 & (V21_cs_buffer[6] $ !N1L931);

--B1L222 is alu:inst|LessThan~3118 at LC2_G14
--operation mode is normal

B1L222 = B1L571 & (V21_cs_buffer[6] $ !N1L931);


--B1L771 is alu:inst|LessThan~3042 at LC3_G14
--operation mode is normal

B1L771 = !V21_cs_buffer[6] & N1L931 & B1L571;

--B1L322 is alu:inst|LessThan~3119 at LC3_G14
--operation mode is normal

B1L322 = !V21_cs_buffer[6] & N1L931 & B1L571;


--B1L871 is alu:inst|LessThan~3043 at LC4_G14
--operation mode is normal

B1L871 = !V21_cs_buffer[7] & N1L141 & (V21_cs_buffer[8] $ !N1L341);

--B1L422 is alu:inst|LessThan~3120 at LC4_G14
--operation mode is normal

B1L422 = !V21_cs_buffer[7] & N1L141 & (V21_cs_buffer[8] $ !N1L341);


--B1L971 is alu:inst|LessThan~3044 at LC5_G14
--operation mode is normal

B1L971 = B1L871 # B1L771 # !V21_cs_buffer[8] & N1L341;

--B1L522 is alu:inst|LessThan~3121 at LC5_G14
--operation mode is normal

B1L522 = B1L871 # B1L771 # !V21_cs_buffer[8] & N1L341;


--B1L081 is alu:inst|LessThan~3045 at LC7_G14
--operation mode is normal

B1L081 = !B1L971 & (V21_cs_buffer[5] # !B1L671 # !N1L731);

--B1L622 is alu:inst|LessThan~3122 at LC7_G14
--operation mode is normal

B1L622 = !B1L971 & (V21_cs_buffer[5] # !B1L671 # !N1L731);

--B1L722 is alu:inst|LessThan~3123 at LC7_G14
--operation mode is normal

B1L722 = !B1L971 & (V21_cs_buffer[5] # !B1L671 # !N1L731);


--B1L591 is alu:inst|LessThan~3083 at LC8_G14
--operation mode is normal

B1L591 = (B1L891 # V21_cs_buffer[5] $ N1L731 # !B1L671) & CASCADE(B1L722);

--B1L822 is alu:inst|LessThan~3124 at LC8_G14
--operation mode is normal

B1L822 = (B1L891 # V21_cs_buffer[5] $ N1L731 # !B1L671) & CASCADE(B1L722);


--N1L56 is bus_mux:inst28|alu_dr[8]~2355 at LC1_H29
--operation mode is normal

N1L56 = N1L36 # K1_q[8] & N1L021;

--N1L96 is bus_mux:inst28|alu_dr[8]~2424 at LC1_H29
--operation mode is normal

N1L96 = N1L36 # K1_q[8] & N1L021;


--B1L181 is alu:inst|LessThan~3048 at LC7_G38
--operation mode is normal

B1L181 = !N1L46 & N1L541;

--B1L922 is alu:inst|LessThan~3125 at LC7_G38
--operation mode is normal

B1L922 = !N1L46 & N1L541;


--B1L281 is alu:inst|LessThan~3049 at LC1_G38
--operation mode is normal

B1L281 = N1L741 & !B1L181 & N1L27 # !N1L741 & (N1L27 # !B1L181) # !B1L371;

--B1L032 is alu:inst|LessThan~3126 at LC1_G38
--operation mode is normal

B1L032 = N1L741 & !B1L181 & N1L27 # !N1L741 & (N1L27 # !B1L181) # !B1L371;

--B1L132 is alu:inst|LessThan~3127 at LC1_G38
--operation mode is normal

B1L132 = N1L741 & !B1L181 & N1L27 # !N1L741 & (N1L27 # !B1L181) # !B1L371;


--B1L691 is alu:inst|LessThan~3084 at LC2_G38
--operation mode is normal

B1L691 = (B1L991 & (N1L08 # !B1L271 # !N1L941)) & CASCADE(B1L132);

--B1L232 is alu:inst|LessThan~3128 at LC2_G38
--operation mode is normal

B1L232 = (B1L991 & (N1L08 # !B1L271 # !N1L941)) & CASCADE(B1L132);

--B1L332 is alu:inst|LessThan~3129 at LC2_G38
--operation mode is normal

B1L332 = (B1L991 & (N1L08 # !B1L271 # !N1L941)) & CASCADE(B1L132);


--B1L381 is alu:inst|LessThan~3054 at LC1_G7
--operation mode is normal

B1L381 = N1L42 & !N1L61 & N1L331 & N1L531 # !N1L42 & (N1L531 # !N1L61 & N1L331);

--B1L432 is alu:inst|LessThan~3130 at LC1_G7
--operation mode is normal

B1L432 = N1L42 & !N1L61 & N1L331 & N1L531 # !N1L42 & (N1L531 # !N1L61 & N1L331);


--B1L481 is alu:inst|LessThan~3055 at LC6_G7
--operation mode is normal

B1L481 = B1L381 & (N1L731 $ !N1L23) # !B1L381 & B1L102 & (N1L731 $ !N1L23);

--B1L532 is alu:inst|LessThan~3131 at LC6_G7
--operation mode is normal

B1L532 = B1L381 & (N1L731 $ !N1L23) # !B1L381 & B1L102 & (N1L731 $ !N1L23);


--B1L581 is alu:inst|LessThan~3056 at LC8_G41
--operation mode is normal

B1L581 = N1L341 & N1L65 & (N1L141 $ !N1L84) # !N1L341 & !N1L65 & (N1L141 $ !N1L84);

--B1L632 is alu:inst|LessThan~3132 at LC8_G41
--operation mode is normal

B1L632 = N1L341 & N1L65 & (N1L141 $ !N1L84) # !N1L341 & !N1L65 & (N1L141 $ !N1L84);


--B1L791 is alu:inst|LessThan~3085 at LC5_G41
--operation mode is normal

B1L791 = (N1L931 $ N1L04 # !B1L481 # !B1L581) & CASCADE(B1L152);

--B1L732 is alu:inst|LessThan~3133 at LC5_G41
--operation mode is normal

B1L732 = (N1L931 $ N1L04 # !B1L481 # !B1L581) & CASCADE(B1L152);


--H1L001 is controller:inst8|Mux~4126 at LC4_F18
--operation mode is normal

H1L001 = F1_output[2] # F1L6 & (F1_output[1]) # !F1L6 & (H1L92 # !F1_output[1]);

--H1L941 is controller:inst8|Mux~4177 at LC4_F18
--operation mode is normal

H1L941 = F1_output[2] # F1L6 & (F1_output[1]) # !F1L6 & (H1L92 # !F1_output[1]);

--H1L051 is controller:inst8|Mux~4178 at LC4_F18
--operation mode is normal

H1L051 = F1_output[2] # F1L6 & (F1_output[1]) # !F1L6 & (H1L92 # !F1_output[1]);


--H1L101 is controller:inst8|Mux~4128 at LC5_F18
--operation mode is normal

H1L101 = (F1_output[1] & (H1L571) # !F1_output[1] & !H1L28 # !H1L56) & CASCADE(H1L051);

--H1L151 is controller:inst8|Mux~4179 at LC5_F18
--operation mode is normal

H1L151 = (F1_output[1] & (H1L571) # !F1_output[1] & !H1L28 # !H1L56) & CASCADE(H1L051);


--N1L33 is bus_mux:inst28|alu_dr[4]~2356 at LC1_H5
--operation mode is normal

N1L33 = N1L13 # K1_q[4] & N1L021;

--N1L73 is bus_mux:inst28|alu_dr[4]~2425 at LC1_H5
--operation mode is normal

N1L73 = N1L13 # K1_q[4] & N1L021;


--V21_cs_buffer[4] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC4_G15
--operation mode is arithmetic

V21_cs_buffer[4] = V21_cout[3] $ (N1L52 # N1L22);

--V21L52 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~367 at LC4_G15
--operation mode is arithmetic

V21L52 = V21_cout[3] $ (N1L52 # N1L22);

--V21_cout[4] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4] at LC4_G15
--operation mode is arithmetic

V21_cout[4] = CARRY(V21_cout[3] # !N1L52 & !N1L22);


--N1L94 is bus_mux:inst28|alu_dr[6]~2357 at LC1_B12
--operation mode is normal

N1L94 = N1L74 # K1_q[6] & N1L021;

--N1L35 is bus_mux:inst28|alu_dr[6]~2426 at LC1_B12
--operation mode is normal

N1L35 = N1L74 # K1_q[6] & N1L021;


--N1L75 is bus_mux:inst28|alu_dr[7]~2358 at LC1_I11
--operation mode is normal

N1L75 = N1L55 # K1_q[7] & N1L021;

--N1L16 is bus_mux:inst28|alu_dr[7]~2427 at LC1_I11
--operation mode is normal

N1L16 = N1L55 # K1_q[7] & N1L021;


--N1L14 is bus_mux:inst28|alu_dr[5]~2359 at LC8_G6
--operation mode is normal

N1L14 = N1L93 # K1_q[5] & N1L021;

--N1L54 is bus_mux:inst28|alu_dr[5]~2428 at LC8_G6
--operation mode is normal

N1L54 = N1L93 # K1_q[5] & N1L021;


--B1L681 is alu:inst|LessThan~3070 at LC2_G7
--operation mode is normal

B1L681 = V21_cs_buffer[4] $ N1L531;

--B1L832 is alu:inst|LessThan~3134 at LC2_G7
--operation mode is normal

B1L832 = V21_cs_buffer[4] $ N1L531;


--V21_cs_buffer[3] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC3_G15
--operation mode is arithmetic

V21_cs_buffer[3] = V21_cout[2] $ (N1L71 # N1L41);

--V21L32 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~368 at LC3_G15
--operation mode is arithmetic

V21L32 = V21_cout[2] $ (N1L71 # N1L41);

--V21_cout[3] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3] at LC3_G15
--operation mode is arithmetic

V21_cout[3] = CARRY(V21_cout[2] # !N1L71 & !N1L41);


--V21_cs_buffer[1] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC1_G15
--operation mode is arithmetic

V21_cs_buffer[1] = P1L1 $ !N1L2;

--V21L91 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~369 at LC1_G15
--operation mode is arithmetic

V21L91 = P1L1 $ !N1L2;

--V21_cout[1] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[1] at LC1_G15
--operation mode is arithmetic

V21_cout[1] = CARRY(P1L1 # N1L2);


--V21_cs_buffer[2] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC2_G15
--operation mode is arithmetic

V21_cs_buffer[2] = V21_cout[1] $ (N1L9 # N1L6);

--V21L12 is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~370 at LC2_G15
--operation mode is arithmetic

V21L12 = V21_cout[1] $ (N1L9 # N1L6);

--V21_cout[2] is alu:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[2] at LC2_G15
--operation mode is arithmetic

V21_cout[2] = CARRY(V21_cout[1] # !N1L9 & !N1L6);


--B1L781 is alu:inst|LessThan~3071 at LC5_G7
--operation mode is normal

B1L781 = V21_cs_buffer[2] & !V21_cs_buffer[1] & N1L921 & N1L131 # !V21_cs_buffer[2] & (N1L131 # !V21_cs_buffer[1] & N1L921);

--B1L932 is alu:inst|LessThan~3135 at LC5_G7
--operation mode is normal

B1L932 = V21_cs_buffer[2] & !V21_cs_buffer[1] & N1L921 & N1L131 # !V21_cs_buffer[2] & (N1L131 # !V21_cs_buffer[1] & N1L921);


--B1L881 is alu:inst|LessThan~3072 at LC7_G7
--operation mode is normal

B1L881 = B1L681 # V21_cs_buffer[3] $ N1L331 # !B1L781;

--B1L042 is alu:inst|LessThan~3136 at LC7_G7
--operation mode is normal

B1L042 = B1L681 # V21_cs_buffer[3] $ N1L331 # !B1L781;

--B1L142 is alu:inst|LessThan~3137 at LC7_G7
--operation mode is normal

B1L142 = B1L681 # V21_cs_buffer[3] $ N1L331 # !B1L781;


--B1L891 is alu:inst|LessThan~3086 at LC8_G7
--operation mode is normal

B1L891 = (N1L531 & V21_cs_buffer[4] & (V21_cs_buffer[3] # !N1L331) # !N1L531 & (V21_cs_buffer[3] # V21_cs_buffer[4] # !N1L331)) & CASCADE(B1L142);

--B1L242 is alu:inst|LessThan~3138 at LC8_G7
--operation mode is normal

B1L242 = (N1L531 & V21_cs_buffer[4] & (V21_cs_buffer[3] # !N1L331) # !N1L531 & (V21_cs_buffer[3] # V21_cs_buffer[4] # !N1L331)) & CASCADE(B1L142);


--B1L981 is alu:inst|LessThan~3074 at LC8_G20
--operation mode is normal

B1L981 = !N1L88 & N1L151;

--B1L342 is alu:inst|LessThan~3139 at LC8_G20
--operation mode is normal

B1L342 = !N1L88 & N1L151;


--B1L091 is alu:inst|LessThan~3075 at LC2_G20
--operation mode is normal

B1L091 = N1L351 & !B1L981 & N1L69 # !N1L351 & (N1L69 # !B1L981) # !B1L071;

--B1L442 is alu:inst|LessThan~3140 at LC2_G20
--operation mode is normal

B1L442 = N1L351 & !B1L981 & N1L69 # !N1L351 & (N1L69 # !B1L981) # !B1L071;

--B1L542 is alu:inst|LessThan~3141 at LC2_G20
--operation mode is normal

B1L542 = N1L351 & !B1L981 & N1L69 # !N1L351 & (N1L69 # !B1L981) # !B1L071;


--B1L991 is alu:inst|LessThan~3087 at LC3_G20
--operation mode is normal

B1L991 = (N1L751 & N1L211 & (N1L401 # !N1L551) # !N1L751 & (N1L401 # N1L211 # !N1L551)) & CASCADE(B1L542);

--B1L642 is alu:inst|LessThan~3142 at LC3_G20
--operation mode is normal

B1L642 = (N1L751 & N1L211 & (N1L401 # !N1L551) # !N1L751 & (N1L401 # N1L211 # !N1L551)) & CASCADE(B1L542);


--B1L191 is alu:inst|LessThan~3077 at LC3_G41
--operation mode is normal

B1L191 = N1L341 & N1L65 & (N1L84 # !N1L141) # !N1L341 & (N1L84 # N1L65 # !N1L141);

--B1L742 is alu:inst|LessThan~3143 at LC3_G41
--operation mode is normal

B1L742 = N1L341 & N1L65 & (N1L84 # !N1L141) # !N1L341 & (N1L84 # N1L65 # !N1L141);

--B1L842 is alu:inst|LessThan~3144 at LC3_G41
--operation mode is normal

B1L842 = N1L341 & N1L65 & (N1L84 # !N1L141) # !N1L341 & (N1L84 # N1L65 # !N1L141);


--B1L291 is alu:inst|LessThan~3078 at LC7_G25
--operation mode is normal

B1L291 = !N1L23 & N1L731;

--B1L942 is alu:inst|LessThan~3145 at LC7_G25
--operation mode is normal

B1L942 = !N1L23 & N1L731;


--B1L002 is alu:inst|LessThan~3088 at LC4_G41
--operation mode is normal

B1L002 = (N1L931 & !B1L291 & N1L04 # !N1L931 & (N1L04 # !B1L291) # !B1L581) & CASCADE(B1L842);

--B1L052 is alu:inst|LessThan~3146 at LC4_G41
--operation mode is normal

B1L052 = (N1L931 & !B1L291 & N1L04 # !N1L931 & (N1L04 # !B1L291) # !B1L581) & CASCADE(B1L842);

--B1L152 is alu:inst|LessThan~3147 at LC4_G41
--operation mode is normal

B1L152 = (N1L931 & !B1L291 & N1L04 # !N1L931 & (N1L04 # !B1L291) # !B1L581) & CASCADE(B1L842);


--B1L391 is alu:inst|LessThan~3080 at LC3_G7
--operation mode is normal

B1L391 = N1L531 & N1L42 & (N1L331 $ !N1L61) # !N1L531 & !N1L42 & (N1L331 $ !N1L61);

--B1L252 is alu:inst|LessThan~3148 at LC3_G7
--operation mode is normal

B1L252 = N1L531 & N1L42 & (N1L331 $ !N1L61) # !N1L531 & !N1L42 & (N1L331 $ !N1L61);

--B1L352 is alu:inst|LessThan~3149 at LC3_G7
--operation mode is normal

B1L352 = N1L531 & N1L42 & (N1L331 $ !N1L61) # !N1L531 & !N1L42 & (N1L331 $ !N1L61);


--B1L102 is alu:inst|LessThan~3089 at LC4_G7
--operation mode is normal

B1L102 = (N1L8 & N1L921 & N1L2 & N1L131 # !N1L8 & (N1L131 # N1L921 & N1L2)) & CASCADE(B1L352);

--B1L452 is alu:inst|LessThan~3150 at LC4_G7
--operation mode is normal

B1L452 = (N1L8 & N1L921 & N1L2 & N1L131 # !N1L8 & (N1L131 # N1L921 & N1L2)) & CASCADE(B1L352);


--N1L52 is bus_mux:inst28|alu_dr[3]~2360 at LC1_K15
--operation mode is normal

N1L52 = N1L32 # K1_q[3] & N1L021;

--N1L92 is bus_mux:inst28|alu_dr[3]~2429 at LC1_K15
--operation mode is normal

N1L92 = N1L32 # K1_q[3] & N1L021;


--N1L71 is bus_mux:inst28|alu_dr[2]~2361 at LC6_H12
--operation mode is normal

N1L71 = N1L51 # K1_q[2] & N1L021;

--N1L12 is bus_mux:inst28|alu_dr[2]~2430 at LC6_H12
--operation mode is normal

N1L12 = N1L51 # K1_q[2] & N1L021;


--N1L9 is bus_mux:inst28|alu_dr[1]~2362 at LC1_H8
--operation mode is normal

N1L9 = N1L7 # K1_q[1] & N1L021;

--N1L31 is bus_mux:inst28|alu_dr[1]~2431 at LC1_H8
--operation mode is normal

N1L31 = N1L7 # K1_q[1] & N1L021;


--reg_sel[1] is reg_sel[1] at PIN_94
--operation mode is input

reg_sel[1] = INPUT();


--reg_sel[2] is reg_sel[2] at PIN_95
--operation mode is input

reg_sel[2] = INPUT();


--reg_sel[3] is reg_sel[3] at PIN_96
--operation mode is input

reg_sel[3] = INPUT();


--sel[0] is sel[0] at PIN_97
--operation mode is input

sel[0] = INPUT();


--sel[1] is sel[1] at PIN_99
--operation mode is input

sel[1] = INPUT();


--reg_sel[0] is reg_sel[0] at PIN_93
--operation mode is input

reg_sel[0] = INPUT();


--clk is clk at PIN_79
--operation mode is input

clk = INPUT();


--reset is reset at PIN_83
--operation mode is input

reset = INPUT();


--wr is wr at PIN_44
--operation mode is output

wr = OUTPUT(!A1L28);


--c is c at PIN_190
--operation mode is output

c = OUTPUT(D1_flag_c);


--z is z at PIN_191
--operation mode is output

z = OUTPUT(D1_flag_z);


--v is v at PIN_192
--operation mode is output

v = OUTPUT(D1_flag_v);


--s is s at PIN_193
--operation mode is output

s = OUTPUT(D1_flag_s);


--address_bus[15] is address_bus[15] at PIN_29
--operation mode is output

address_bus[15] = OUTPUT(J1_q[15]);


--address_bus[14] is address_bus[14] at PIN_28
--operation mode is output

address_bus[14] = OUTPUT(J1_q[14]);


--address_bus[13] is address_bus[13] at PIN_27
--operation mode is output

address_bus[13] = OUTPUT(J1_q[13]);


--address_bus[12] is address_bus[12] at PIN_26
--operation mode is output

address_bus[12] = OUTPUT(J1_q[12]);


--address_bus[11] is address_bus[11] at PIN_25
--operation mode is output

address_bus[11] = OUTPUT(J1_q[11]);


--address_bus[10] is address_bus[10] at PIN_24
--operation mode is output

address_bus[10] = OUTPUT(J1_q[10]);


--address_bus[9] is address_bus[9] at PIN_18
--operation mode is output

address_bus[9] = OUTPUT(J1_q[9]);


--address_bus[8] is address_bus[8] at PIN_17
--operation mode is output

address_bus[8] = OUTPUT(J1_q[8]);


--address_bus[7] is address_bus[7] at PIN_15
--operation mode is output

address_bus[7] = OUTPUT(J1_q[7]);


--address_bus[6] is address_bus[6] at PIN_14
--operation mode is output

address_bus[6] = OUTPUT(J1_q[6]);


--address_bus[5] is address_bus[5] at PIN_13
--operation mode is output

address_bus[5] = OUTPUT(J1_q[5]);


--address_bus[4] is address_bus[4] at PIN_12
--operation mode is output

address_bus[4] = OUTPUT(J1_q[4]);


--address_bus[3] is address_bus[3] at PIN_11
--operation mode is output

address_bus[3] = OUTPUT(J1_q[3]);


--address_bus[2] is address_bus[2] at PIN_9
--operation mode is output

address_bus[2] = OUTPUT(J1_q[2]);


--address_bus[1] is address_bus[1] at PIN_8
--operation mode is output

address_bus[1] = OUTPUT(J1_q[1]);


--address_bus[0] is address_bus[0] at PIN_7
--operation mode is output

address_bus[0] = OUTPUT(J1_q[0]);


--reg_data[15] is reg_data[15] at PIN_132
--operation mode is output

reg_data[15] = OUTPUT(R1L671);


--reg_data[14] is reg_data[14] at PIN_131
--operation mode is output

reg_data[14] = OUTPUT(!R1L561);


--reg_data[13] is reg_data[13] at PIN_128
--operation mode is output

reg_data[13] = OUTPUT(!R1L751);


--reg_data[12] is reg_data[12] at PIN_127
--operation mode is output

reg_data[12] = OUTPUT(!R1L051);


--reg_data[11] is reg_data[11] at PIN_126
--operation mode is output

reg_data[11] = OUTPUT(R1L441);


--reg_data[10] is reg_data[10] at PIN_125
--operation mode is output

reg_data[10] = OUTPUT(!R1L731);


--reg_data[9] is reg_data[9] at PIN_122
--operation mode is output

reg_data[9] = OUTPUT(!R1L031);


--reg_data[8] is reg_data[8] at PIN_121
--operation mode is output

reg_data[8] = OUTPUT(!R1L321);


--reg_data[7] is reg_data[7] at PIN_120
--operation mode is output

reg_data[7] = OUTPUT(!R1L611);


--reg_data[6] is reg_data[6] at PIN_119
--operation mode is output

reg_data[6] = OUTPUT(!R1L901);


--reg_data[5] is reg_data[5] at PIN_116
--operation mode is output

reg_data[5] = OUTPUT(!R1L201);


--reg_data[4] is reg_data[4] at PIN_115
--operation mode is output

reg_data[4] = OUTPUT(!R1L59);


--reg_data[3] is reg_data[3] at PIN_114
--operation mode is output

reg_data[3] = OUTPUT(!R1L88);


--reg_data[2] is reg_data[2] at PIN_113
--operation mode is output

reg_data[2] = OUTPUT(!R1L18);


--reg_data[1] is reg_data[1] at PIN_112
--operation mode is output

reg_data[1] = OUTPUT(!R1L47);


--reg_data[0] is reg_data[0] at PIN_111
--operation mode is output

reg_data[0] = OUTPUT(!R1L76);


--A1L73 is data_bus~0 at PIN_75
--operation mode is bidir

A1L73 = data_bus[15];

--data_bus[15] is data_bus[15] at PIN_75
--operation mode is bidir

data_bus[15]_tri_out = TRI(B1L251, H1_wr);
data_bus[15] = BIDIR(data_bus[15]_tri_out);


--A1L83 is data_bus~1 at PIN_74
--operation mode is bidir

A1L83 = data_bus[14];

--data_bus[14] is data_bus[14] at PIN_74
--operation mode is bidir

data_bus[14]_tri_out = TRI(B1L341, H1_wr);
data_bus[14] = BIDIR(data_bus[14]_tri_out);


--A1L93 is data_bus~2 at PIN_73
--operation mode is bidir

A1L93 = data_bus[13];

--data_bus[13] is data_bus[13] at PIN_73
--operation mode is bidir

data_bus[13]_tri_out = TRI(B1L331, H1_wr);
data_bus[13] = BIDIR(data_bus[13]_tri_out);


--A1L04 is data_bus~3 at PIN_71
--operation mode is bidir

A1L04 = data_bus[12];

--data_bus[12] is data_bus[12] at PIN_71
--operation mode is bidir

data_bus[12]_tri_out = TRI(B1L321, H1_wr);
data_bus[12] = BIDIR(data_bus[12]_tri_out);


--A1L14 is data_bus~4 at PIN_70
--operation mode is bidir

A1L14 = data_bus[11];

--data_bus[11] is data_bus[11] at PIN_70
--operation mode is bidir

data_bus[11]_tri_out = TRI(B1L311, H1_wr);
data_bus[11] = BIDIR(data_bus[11]_tri_out);


--A1L24 is data_bus~5 at PIN_69
--operation mode is bidir

A1L24 = data_bus[10];

--data_bus[10] is data_bus[10] at PIN_69
--operation mode is bidir

data_bus[10]_tri_out = TRI(B1L301, H1_wr);
data_bus[10] = BIDIR(data_bus[10]_tri_out);


--A1L34 is data_bus~6 at PIN_68
--operation mode is bidir

A1L34 = data_bus[9];

--data_bus[9] is data_bus[9] at PIN_68
--operation mode is bidir

data_bus[9]_tri_out = TRI(B1L39, H1_wr);
data_bus[9] = BIDIR(data_bus[9]_tri_out);


--A1L44 is data_bus~7 at PIN_67
--operation mode is bidir

A1L44 = data_bus[8];

--data_bus[8] is data_bus[8] at PIN_67
--operation mode is bidir

data_bus[8]_tri_out = TRI(B1L38, H1_wr);
data_bus[8] = BIDIR(data_bus[8]_tri_out);


--A1L54 is data_bus~8 at PIN_61
--operation mode is bidir

A1L54 = data_bus[7];

--data_bus[7] is data_bus[7] at PIN_61
--operation mode is bidir

data_bus[7]_tri_out = TRI(B1L37, H1_wr);
data_bus[7] = BIDIR(data_bus[7]_tri_out);


--A1L64 is data_bus~9 at PIN_60
--operation mode is bidir

A1L64 = data_bus[6];

--data_bus[6] is data_bus[6] at PIN_60
--operation mode is bidir

data_bus[6]_tri_out = TRI(B1L36, H1_wr);
data_bus[6] = BIDIR(data_bus[6]_tri_out);


--A1L74 is data_bus~10 at PIN_58
--operation mode is bidir

A1L74 = data_bus[5];

--data_bus[5] is data_bus[5] at PIN_58
--operation mode is bidir

data_bus[5]_tri_out = TRI(B1L35, H1_wr);
data_bus[5] = BIDIR(data_bus[5]_tri_out);


--A1L84 is data_bus~11 at PIN_57
--operation mode is bidir

A1L84 = data_bus[4];

--data_bus[4] is data_bus[4] at PIN_57
--operation mode is bidir

data_bus[4]_tri_out = TRI(B1L34, H1_wr);
data_bus[4] = BIDIR(data_bus[4]_tri_out);


--A1L94 is data_bus~12 at PIN_56
--operation mode is bidir

A1L94 = data_bus[3];

--data_bus[3] is data_bus[3] at PIN_56
--operation mode is bidir

data_bus[3]_tri_out = TRI(B1L33, H1_wr);
data_bus[3] = BIDIR(data_bus[3]_tri_out);


--A1L05 is data_bus~13 at PIN_55
--operation mode is bidir

A1L05 = data_bus[2];

--data_bus[2] is data_bus[2] at PIN_55
--operation mode is bidir

data_bus[2]_tri_out = TRI(B1L32, H1_wr);
data_bus[2] = BIDIR(data_bus[2]_tri_out);


--A1L15 is data_bus~14 at PIN_54
--operation mode is bidir

A1L15 = data_bus[1];

--data_bus[1] is data_bus[1] at PIN_54
--operation mode is bidir

data_bus[1]_tri_out = TRI(B1L31, H1_wr);
data_bus[1] = BIDIR(data_bus[1]_tri_out);


--A1L25 is data_bus~15 at PIN_53
--operation mode is bidir

A1L25 = data_bus[0];

--data_bus[0] is data_bus[0] at PIN_53
--operation mode is bidir

data_bus[0]_tri_out = TRI(B1L4, H1_wr);
data_bus[0] = BIDIR(data_bus[0]_tri_out);


--H1L63 is controller:inst8|en_pc~427 at LC8_H49
--operation mode is normal

H1L63 = !H1L33;


--A1L28 is wr~103 at LC8_K37
--operation mode is normal

A1L28 = H1_wr;