-
Notifications
You must be signed in to change notification settings - Fork 0
/
regfile.vhd.bak
78 lines (65 loc) · 2.01 KB
/
regfile.vhd.bak
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
library ieee;
use ieee.std_logic_1164.all;
entity regfile is port(
DR : in std_logic_vector(1 downto 0);
SR : in std_logic_vector(1 downto 0);
reset : in std_logic;
write : in std_logic;
clk : in std_logic;
d_input : in std_logic_vector(7 downto 0);
reg_sel : in std_logic_vector(1 downto 0);
output_SR : out std_logic_vector(7 downto 0);
output_DR : out std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0)
);
end regfile;
architecture struct of regfile is
component reg is port(
reset : in std_logic;
d : in std_logic_vector(7 downto 0);
clk : in std_logic;
en : in std_logic;
sel : in std_logic;
q : out std_logic_vector(7 downto 0)
);
end component;
component mux_4_to_1 is port(
input0,
input1,
input2,
input3 : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(1 downto 0);
out_put : out std_logic_vector(7 downto 0)
);
end component;
component decoder_2_to_4 is port(
sel : in std_logic_vector(1 downto 0);
sel00 : out std_logic;
sel01 : out std_logic;
sel02 : out std_logic;
sel03 : out std_logic
);
end component;
signal reg00,reg01,reg02,reg03:std_logic_vector(7 downto 0);
signal sel00,sel01,sel02,sel03:std_logic;
begin
Areg00: reg port map( --¼Ä´æÆ÷R0
reset =>reset,
d =>d_input,
clk =>clk,
en =>write,
sel =>sel00,
q =>reg00
);
Areg01: reg port map( --¼Ä´æÆ÷R1
reset =>reset,
d =>d_input,
clk =>clk,
en =>write,
sel =>sel01,
q =>reg01
);
Areg02: reg port map( --¼Ä´æÆ÷R2
reset =>reset,
d =>d_input,
clk =>clk,