From 0448cfdd83bbfab64378646ed6ecf9a78f89162b Mon Sep 17 00:00:00 2001 From: Jiaqi Gao Date: Mon, 16 Sep 2024 09:08:31 -0400 Subject: [PATCH] ResetVector: remove 5-level paging 5-level paging is not necessary in td-shim, remove the related code and page table entry in reset vector. td-shim checks the CR4.LA57 before setting the new page table, it will panic if the bit is set. Signed-off-by: Jiaqi Gao --- td-shim/ResetVector/Ia32/Flat32ToFlat64.asm | 20 +------------------- td-shim/src/bin/td-shim/memory.rs | 6 ++++++ 2 files changed, 7 insertions(+), 19 deletions(-) diff --git a/td-shim/ResetVector/Ia32/Flat32ToFlat64.asm b/td-shim/ResetVector/Ia32/Flat32ToFlat64.asm index 99d2b26d..3a80f7dd 100644 --- a/td-shim/ResetVector/Ia32/Flat32ToFlat64.asm +++ b/td-shim/ResetVector/Ia32/Flat32ToFlat64.asm @@ -16,29 +16,11 @@ Transition32FlatTo64Flat: mov eax, cr4 bts eax, 5 ; enable PAE - - ; - ; esp [6:0] holds gpaw, if it is at least 52 bits, need to set - ; LA57 and use 5-level paging - ; - mov ecx, esp - and ecx, 0x2f - cmp ecx, 52 - jl .set_cr4 - bts eax, 12 -.set_cr4: mov cr4, eax mov ecx, ADDR_OF(TopLevelPageDirectory) - ; - ; if we just set la57, we are ok, if using 4-level paging, adjust top-level page directory - ; - bt eax, 12 - jc .set_cr3 - add ecx, 0x1000 -.set_cr3: + add ecx, 0x1000 ; point to level-4 page table entry mov cr3, ecx - mov eax, cr0 bts eax, 31 ; set PG mov cr0, eax ; enable paging diff --git a/td-shim/src/bin/td-shim/memory.rs b/td-shim/src/bin/td-shim/memory.rs index 2283b86d..d90cb8da 100644 --- a/td-shim/src/bin/td-shim/memory.rs +++ b/td-shim/src/bin/td-shim/memory.rs @@ -14,6 +14,7 @@ use td_shim_interface::td_uefi_pi::pi::hob::{ RESOURCE_SYSTEM_MEMORY, }; use x86_64::{ + registers::control::{Cr4, Cr4Flags}, structures::paging::PageTableFlags as Flags, structures::paging::{OffsetPageTable, PageTable}, PhysAddr, VirtAddr, @@ -125,6 +126,11 @@ impl<'a> Memory<'a> { } } + if Cr4::read().contains(Cr4Flags::L5_PAGING) { + panic!( + "5-Level paging is not supported by td-shim but it is enabled in CR4 unexpectedly" + ); + } td_paging::cr3_write( self.get_layout_region(SliceType::PayloadPageTable) .base_address as u64,