Skip to content

Commit b9e1be7

Browse files
authored
Add load register subset. (#37)
1 parent ddaba6b commit b9e1be7

File tree

2 files changed

+79
-0
lines changed

2 files changed

+79
-0
lines changed

chip8/cpu.py

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,8 @@ def misc_routines(self):
258258
sub_operation = self.operand & 0x000F
259259
if sub_operation == 0x2:
260260
self.store_subset_regs_in_memory()
261+
elif sub_operation == 0x3:
262+
self.read_subset_regs_in_memory()
261263
else:
262264
try:
263265
self.misc_routine_lookup[operation]()
@@ -867,6 +869,32 @@ def store_subset_regs_in_memory(self):
867869

868870
self.last_op = f"STORSUB [I], {x:01X}, {y:01X}"
869871

872+
def read_subset_regs_in_memory(self):
873+
"""
874+
Fxy3 - LOADSUB [I], Vx, Vy
875+
876+
Load a subset of registers from x to y in memory starting at index.
877+
The x and y calculation is as follows:
878+
879+
Bits: 15-12 11-8 7-4 3-0
880+
F x y 2
881+
882+
If x is larger than y, then they will be loaded in reverse order.
883+
"""
884+
x = (self.operand & 0x0F00) >> 8
885+
y = (self.operand & 0x00F0) >> 4
886+
pointer = 0
887+
if y >= x:
888+
for z in range(x, y+1):
889+
self.v[z] = self.memory[self.index + pointer]
890+
pointer += 1
891+
else:
892+
for z in range(x, y-1, -1):
893+
self.v[z] = self.memory[self.index + pointer]
894+
pointer += 1
895+
896+
self.last_op = f"LOADSUB [I], {x:01X}, {y:01X}"
897+
870898
def move_delay_timer_into_reg(self):
871899
"""
872900
Fx07 - LOAD Vx, DELAY

test/test_chip8cpu.py

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -955,6 +955,57 @@ def test_store_subset_regs_integration(self):
955955
self.assertEqual(6, self.cpu.memory[0x5001])
956956
self.assertEqual(5, self.cpu.memory[0x5002])
957957

958+
def test_readsubset_regs_one_two(self):
959+
self.cpu.v[1] = 5
960+
self.cpu.v[2] = 6
961+
self.cpu.index = 0x5000
962+
self.cpu.operand = 0xF123
963+
self.cpu.memory[0x5000] = 7
964+
self.cpu.memory[0x5001] = 8
965+
self.cpu.read_subset_regs_in_memory()
966+
self.assertEqual(7, self.cpu.v[1])
967+
self.assertEqual(8, self.cpu.v[2])
968+
969+
def test_read_subset_regs_one_one(self):
970+
self.cpu.v[1] = 5
971+
self.cpu.v[2] = 6
972+
self.cpu.index = 0x5000
973+
self.cpu.operand = 0xF113
974+
self.cpu.memory[0x5000] = 7
975+
self.cpu.memory[0x5001] = 8
976+
self.cpu.read_subset_regs_in_memory()
977+
self.assertEqual(7, self.cpu.v[1])
978+
self.assertEqual(6, self.cpu.v[2])
979+
980+
def test_read_subset_regs_three_one(self):
981+
self.cpu.v[1] = 5
982+
self.cpu.v[2] = 6
983+
self.cpu.v[3] = 7
984+
self.cpu.index = 0x5000
985+
self.cpu.operand = 0xF313
986+
self.cpu.memory[0x5000] = 8
987+
self.cpu.memory[0x5001] = 9
988+
self.cpu.memory[0x5002] = 10
989+
self.cpu.read_subset_regs_in_memory()
990+
self.assertEqual(10, self.cpu.v[1])
991+
self.assertEqual(9, self.cpu.v[2])
992+
self.assertEqual(8, self.cpu.v[3])
993+
994+
def test_read_subset_regs_integration(self):
995+
self.cpu.v[1] = 5
996+
self.cpu.v[2] = 6
997+
self.cpu.v[3] = 7
998+
self.cpu.index = 0x5000
999+
self.cpu.memory[0x0200] = 0xF3
1000+
self.cpu.memory[0x0201] = 0x13
1001+
self.cpu.memory[0x5000] = 8
1002+
self.cpu.memory[0x5001] = 9
1003+
self.cpu.memory[0x5002] = 10
1004+
self.cpu.execute_instruction()
1005+
self.assertEqual(10, self.cpu.v[1])
1006+
self.assertEqual(9, self.cpu.v[2])
1007+
self.assertEqual(8, self.cpu.v[3])
1008+
9581009
# M A I N #####################################################################
9591010

9601011

0 commit comments

Comments
 (0)