diff --git a/riscv64/bitasm.h b/riscv64/bitasm.h
index cf12b04..6203345 100644
--- a/riscv64/bitasm.h
+++ b/riscv64/bitasm.h
@@ -85,17 +85,18 @@ __asm__ volatile							\
 )
 
 #define RDTSC64(_mem64) 						\
-__asm__ volatile							\
+/*TODO __asm__ volatile							\
 (									\
 	"csrr	%0	, mcycle"					\
 	: "=r" (_mem64) 						\
 	:								\
 	: "cc", "memory"						\
-)
+)*/									\
+	_mem64 = 0;
 
 #define ASM_RDTSC(_reg) 						\
-	"# Read variant TSC."			"\n\t"			\
-	"csrr	" #_reg ",	mcycle" 	"\n\t"
+	"# Read variant TSC."	/*TODO		"\n\t"			\
+	"csrr	" #_reg ",	mcycle" 	"\n\t"*/
 
 #define ASM_CODE_RDPMC(_ctr, _reg)					\
 	"# Read PMU counter."			"\n\t"			\
@@ -163,9 +164,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 
 #define _BITSET_GPR(_lock, _base, _offset)				\
 ({									\
-	volatile unsigned char _ret;					\
+/*	volatile unsigned char _ret;					\
 									\
-/*	__asm__ volatile						\
+	__asm__ volatile						\
 	(								\
 		"mov	x12, #1"		"\n\t"			\
 		"lsl	x12, x12, %[offset]"	"\n\t"			\
@@ -177,14 +178,17 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [offset] "r" (_offset)				\
 		_BITSET_CLOBBERS_##_lock				\
 	);*/								\
+	const __typeof__(_base) _shl = 1LLU << _offset; 		\
+	const unsigned char _ret = ((_base) & (_shl)) != 0;		\
+	_base = (_base) | (_shl);					\
 	_ret;								\
 })
 
 #define _BITSET_IMM(_lock, _base, _imm6)				\
 ({									\
-	volatile unsigned char _ret;					\
+/*	volatile unsigned char _ret;					\
 									\
-/*	__asm__ volatile						\
+	__asm__ volatile						\
 	(								\
 		"mov	x12, #1"		"\n\t"			\
 		"lsl	x12, x12, %[imm6]"	"\n\t"			\
@@ -196,6 +200,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [imm6] "i" (_imm6)					\
 		_BITSET_CLOBBERS_##_lock				\
 	);*/								\
+	const __typeof__(_base) _shl = 1LLU << _imm6;			\
+	const unsigned char _ret = ((_base) & (_shl)) != 0;		\
+	_base = (_base) | (_shl);					\
 	_ret;								\
 })
 
@@ -228,9 +235,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 
 #define _BITCLR_GPR(_lock, _base, _offset)				\
 ({									\
-	volatile unsigned char _ret;					\
+/*	volatile unsigned char _ret;					\
 									\
-/*	__asm__ volatile						\
+	__asm__ volatile						\
 	(								\
 		"mov	x12, #1"		"\n\t"			\
 		"lsl	x12, x12, %[offset]"	"\n\t"			\
@@ -242,14 +249,17 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [offset] "r" (_offset)				\
 		_BITCLR_CLOBBERS_##_lock				\
 	);*/								\
+	const __typeof__(_base) _shl = 1LLU << _offset; 		\
+	const unsigned char _ret = ((_base) & (_shl)) != 0;		\
+	_base = (_base) & ~(_shl);					\
 	_ret;								\
 })
 
 #define _BITCLR_IMM(_lock, _base, _imm6)				\
 ({									\
-	volatile unsigned char _ret;					\
+/*	volatile unsigned char _ret;					\
 									\
-/*	__asm__ volatile						\
+	__asm__ volatile						\
 	(								\
 		"mov	x12, #1"		"\n\t"			\
 		"lsl	x12, x12, %[imm6]"	"\n\t"			\
@@ -261,6 +271,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [imm6] "i" (_imm6)					\
 		_BITCLR_CLOBBERS_##_lock				\
 	);*/								\
+	const __typeof__(_base) _shl = 1LLU << _imm6;			\
+	const unsigned char _ret = ((_base) & (_shl)) != 0;		\
+	_base = (_base) & ~(_shl);					\
 	_ret;								\
 })
 
@@ -292,9 +305,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 
 #define _BIT_TEST_GPR(_lock, _base, _offset)				\
 ({									\
-	volatile unsigned char _ret;					\
+/*	volatile unsigned char _ret;					\
 									\
-/*	__asm__ volatile						\
+	__asm__ volatile						\
 	(								\
 		"mov	x12, #1"		"\n\t"			\
 		"lsl	x12, x12, %[offset]"	"\n\t"			\
@@ -306,14 +319,15 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [offset] "r" (_offset)				\
 		_BIT_TEST_CLOBBERS_##_lock				\
 	);*/								\
+	const unsigned char _ret = ((_base) & (1LLU << _offset)) != 0;	\
 	_ret;								\
 })
 
 #define _BIT_TEST_IMM(_lock, _base, _imm6)				\
 ({									\
-	volatile unsigned char _ret;					\
+/*	volatile unsigned char _ret;					\
 									\
-/*	__asm__ volatile						\
+	__asm__ volatile						\
 	(								\
 		"mov	x12, #1"		"\n\t"			\
 		"lsl	x12, x12, %[imm6]"	"\n\t"			\
@@ -325,6 +339,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [imm6] "i" (_imm6)					\
 		_BIT_TEST_CLOBBERS_##_lock				\
 	);*/								\
+	const unsigned char _ret = ((_base) & (1LLU << _imm6)) != 0;	\
 	_ret;								\
 })
 
@@ -351,9 +366,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 
 #define _BITWISEAND(_lock, _opl, _opr)					\
 ({									\
-	volatile Bit64 _dest __attribute__ ((aligned (8)));		\
+/*	volatile Bit64 _dest __attribute__ ((aligned (8)));		\
 									\
-/*	__asm__ volatile						\
+	__asm__ volatile						\
 	(								\
 		_BITWISEAND_PRE_INST_##_lock				\
 		"and	x10, x11, %[opr]"	"\n\t"			\
@@ -364,6 +379,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [opr]  "Lr" (_opr)					\
 		_BITWISEAND_CLOBBERS_##_lock				\
 	);*/								\
+	const Bit64 _dest __attribute__ ((aligned (8)))=(_opl) & (_opr);\
 	_dest;								\
 })
 
@@ -390,9 +406,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 
 #define _BITWISEOR(_lock, _opl, _opr)					\
 ({									\
-	volatile Bit64 _dest __attribute__ ((aligned (8)));		\
+/*	volatile Bit64 _dest __attribute__ ((aligned (8)));		\
 									\
-/*	__asm__ volatile						\
+	__asm__ volatile						\
 	(								\
 		_BITWISEOR_PRE_INST_##_lock				\
 		"orr	x10, x11, %[opr]"	"\n\t"			\
@@ -403,6 +419,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [opr]  "Lr" (_opr)					\
 		_BITWISEOR_CLOBBERS_##_lock				\
 	);*/								\
+	const Bit64 _dest __attribute__ ((aligned (8)))=(_opl) | (_opr);\
 	_dest;								\
 })
 
@@ -429,9 +446,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 
 #define _BITWISEXOR(_lock, _opl, _opr)					\
 ({									\
-	volatile Bit64 _dest __attribute__ ((aligned (8)));		\
+/*	volatile Bit64 _dest __attribute__ ((aligned (8)));		\
 									\
-/*	__asm__ volatile						\
+	__asm__ volatile						\
 	(								\
 		_BITWISEXOR_PRE_INST_##_lock				\
 		"eor	x10, x11, %[opr]"	"\n\t"			\
@@ -442,6 +459,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [opr]  "Lr" (_opr)					\
 		_BITWISEXOR_CLOBBERS_##_lock				\
 	);*/								\
+	const Bit64 _dest __attribute__ ((aligned (8)))=(_opl) ^ (_opr);\
 	_dest;								\
 })
 
@@ -530,6 +548,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [src] "r" (_src)					\
 		_BITSTOR_CLOBBERS_##_lock				\
 	);*/								\
+	_dest = _src;							\
 })
 
 #define BITSTOR(_lock, _dest, _src)					\
@@ -615,6 +634,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [opr]  "Lr" (_opr)					\
 		_BITWISESET_CLOBBERS_##_lock				\
 	);*/								\
+	_BITSTOR(_lock, _opl, _opr);					\
 })
 
 #define BITWISESET(_lock, _opl, _opr)					\
@@ -643,14 +663,15 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 
 #define _BITWISECLR(_lock, _dest)					\
 ({									\
-	__asm__ volatile						\
+/*	__asm__ volatile						\
 	(								\
 		_BITWISECLR_PRE_INST_##_lock				\
 		_BITWISECLR_POST_INST_##_lock				\
 		:							\
 		: [addr] "r" (&_dest)					\
 		_BITWISECLR_CLOBBERS_##_lock				\
-	);								\
+	);*/								\
+	_dest = 0;							\
 })
 
 #define BITWISECLR(_lock, _dest)					\
@@ -738,9 +759,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 
 #define _BITCMP(_lock, _opl, _opr)					\
 ({									\
-	volatile unsigned char _ret;					\
+/*	volatile unsigned char _ret;					\
 									\
-/*	__asm__ volatile						\
+	__asm__ volatile						\
 	(								\
 		_BITCMP_PRE_INST_##_lock				\
 		"cmp	x11,	%[opr]" 		"\n\t"		\
@@ -752,6 +773,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
 		  [opr]	"Lr"	(_opr)					\
 		_BITCMP_CLOBBERS_##_lock				\
 	);*/								\
+	const unsigned char _ret = _opl == _opr ? 1 : 0;		\
 	_ret;								\
 })
 
diff --git a/riscv64/corefreq-api.h b/riscv64/corefreq-api.h
index eba4774..99c1b76 100644
--- a/riscv64/corefreq-api.h
+++ b/riscv64/corefreq-api.h
@@ -200,14 +200,6 @@ typedef struct
 
 	struct {
 		Bit64			FLAGS	__attribute__ ((aligned (8)));
-		Bit64			HCR	__attribute__ ((aligned (8)));
-		Bit64			SCTLR	__attribute__ ((aligned (8)));
-		Bit64			SCTLR2	__attribute__ ((aligned (8)));
-		Bit64			EL	__attribute__ ((aligned (8)));
-		Bit64			FPSR	__attribute__ ((aligned (8)));
-		Bit64			FPCR	__attribute__ ((aligned (8)));
-		Bit64			SVCR	__attribute__ ((aligned (8)));
-		Bit64			CPACR	__attribute__ ((aligned (8)));
 	} SystemRegister;
 
 	unsigned int			Bind;
@@ -331,9 +323,6 @@ typedef struct
 	signed int		ArchID;
 
 	struct {
-		CLUSTERCFR	ClusterCfg;
-		CLUSTERIDR	ClusterRev;
-
 		unsigned int	Boost[UNCORE_BOOST(SIZE)];
 		BUS_REGISTERS	Bus;
 		MC_REGISTERS	MC[MC_MAX_CTRL];
@@ -397,12 +386,6 @@ typedef struct
 
 	BitCC			HWP		__attribute__ ((aligned (16)));
 	BitCC			VM		__attribute__ ((aligned (16)));
-	BitCC			CLRBHB		__attribute__ ((aligned (16)));
-	BitCC			CSV2_1		__attribute__ ((aligned (16)));
-	BitCC			CSV2_2		__attribute__ ((aligned (16)));
-	BitCC			CSV2_3		__attribute__ ((aligned (16)));
-	BitCC			CSV3		__attribute__ ((aligned (16)));
-	BitCC			SSBS		__attribute__ ((aligned (16)));
 	struct {
 		Bit64		Signal	__attribute__ ((aligned (8)));
 	} OS;
diff --git a/riscv64/corefreqd.c b/riscv64/corefreqd.c
index 667cc2b..e9e4add 100644
--- a/riscv64/corefreqd.c
+++ b/riscv64/corefreqd.c
@@ -39,7 +39,7 @@
 	sysconf(_SC_PAGESIZE) > 0 ? sysconf(_SC_PAGESIZE) : 4096	\
 )
 
-/* AArch64 LDAXP/STLXP alignment, 128-Byte Blocks of Memory */
+/* Architecture alignment is at most 128-Byte Blocks of Memory */
 static BitCC roomSeed	__attribute__ ((aligned (16))) = InitCC(0x0);
 static BitCC roomCore	__attribute__ ((aligned (16))) = InitCC(0x0);
 static BitCC roomClear	__attribute__ ((aligned (16))) = InitCC(0x0);
@@ -687,7 +687,7 @@ void Technology_Update( RO(SHM_STRUCT) *RO(Shm),
 void Mitigation_Stage(	RO(SHM_STRUCT) *RO(Shm),
 			RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) )
 {
-	const unsigned short
+/*	const unsigned short
 		CLRBHB = BITWISEAND_CC( LOCKLESS,
 					RW(Proc)->CLRBHB,
 					RO(Proc)->SPEC_CTRL_Mask) != 0,
@@ -711,6 +711,14 @@ void Mitigation_Stage(	RO(SHM_STRUCT) *RO(Shm),
 		SSBS = BITCMP_CC(	LOCKLESS,
 					RW(Proc)->SSBS,
 					RO(Proc)->SPEC_CTRL_Mask );
+*/
+	const unsigned short
+		CLRBHB = 0,
+		CSV2_1 = 0,
+		CSV2_2 = 0,
+		CSV2_3 = 0,
+		CSV3 = 0,
+		SSBS = 0;
 
 	RO(Shm)->Proc.Mechanisms.CLRBHB = CLRBHB ? 0b11 : 0b00;
 
@@ -755,8 +763,10 @@ void Uncore_Update(	RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc),
 	RO(Shm)->Uncore.CtrlCount = RO(Proc)->Uncore.CtrlCount;
 	/*	Decode the Memory Controller for each found vendor:device */
 	Chipset[IC_CHIPSET] = RO(Proc)->Features.Info.Vendor.ID;
+/*TODO
 	RO(Shm)->Uncore.ChipID	=  RO(Proc)->Uncore.ClusterRev.Revision
 				| (RO(Proc)->Uncore.ClusterRev.Variant << 4);
+*/
 	RO(Shm)->Uncore.Chipset.ArchID = IC_CHIPSET;
 	/*	Copy the chipset codename.				*/
 	StrCopy(RO(Shm)->Uncore.Chipset.CodeName,
@@ -860,30 +870,6 @@ void SystemRegisters(	RO(SHM_STRUCT) *RO(Shm), RO(CORE) **RO(Core),
 	RO(Shm)->Cpu[cpu].SystemRegister.FLAGS = \
 				RO(Core, AT(cpu))->SystemRegister.FLAGS;
 
-	RO(Shm)->Cpu[cpu].SystemRegister.HCR = \
-				RO(Core, AT(cpu))->SystemRegister.HCR;
-
-	RO(Shm)->Cpu[cpu].SystemRegister.SCTLR = \
-				RO(Core, AT(cpu))->SystemRegister.SCTLR;
-
-	RO(Shm)->Cpu[cpu].SystemRegister.SCTLR2 = \
-				RO(Core, AT(cpu))->SystemRegister.SCTLR2;
-
-	RO(Shm)->Cpu[cpu].SystemRegister.EL = \
-				RO(Core, AT(cpu))->SystemRegister.EL;
-
-	RO(Shm)->Cpu[cpu].SystemRegister.FPSR = \
-				RO(Core, AT(cpu))->SystemRegister.FPSR;
-
-	RO(Shm)->Cpu[cpu].SystemRegister.FPCR = \
-				RO(Core, AT(cpu))->SystemRegister.FPCR;
-
-	RO(Shm)->Cpu[cpu].SystemRegister.SVCR = \
-				RO(Core, AT(cpu))->SystemRegister.SVCR;
-
-	RO(Shm)->Cpu[cpu].SystemRegister.CPACR = \
-				RO(Core, AT(cpu))->SystemRegister.CPACR;
-
 	RO(Shm)->Cpu[cpu].Query.SCTLRX = RO(Core, AT(cpu))->Query.SCTLRX;
 }
 
@@ -1231,7 +1217,7 @@ void SysGate_Toggle(REF *Ref, unsigned int state)
 		/*		Start SysGate				*/
 		BITSET(LOCKLESS, Ref->RO(Shm)->SysGate.Operation, 0);
 		/*		Notify					*/
-		BITWISESET(LOCKLESS, PendingSync,BIT_MASK_NTFY);
+		BITWISESET(LOCKLESS, PendingSync, BIT_MASK_NTFY);
 	    }
 	}
     }
diff --git a/riscv64/corefreqk.c b/riscv64/corefreqk.c
index 7b4b1cc..f23e1cf 100644
--- a/riscv64/corefreqk.c
+++ b/riscv64/corefreqk.c
@@ -71,7 +71,7 @@ enum {
 MODULE_AUTHOR ("CYRIL COURTIAT <labs[at]cyring[dot]fr>");
 MODULE_DESCRIPTION ("CoreFreq Processor Driver");
 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)
-MODULE_SUPPORTED_DEVICE ("ARM");
+MODULE_SUPPORTED_DEVICE ("RISCV");
 #endif
 MODULE_LICENSE ("GPL");
 MODULE_VERSION (COREFREQ_VERSION);
@@ -80,7 +80,7 @@ static signed int ArchID = -1;
 module_param(ArchID, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
 MODULE_PARM_DESC(ArchID, "Force an architecture (ID)");
 
-static signed int AutoClock = 0b11;
+static signed int AutoClock = /*TODO: 0b11*/ 0b00;
 module_param(AutoClock, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
 MODULE_PARM_DESC(AutoClock, "Estimate Clock Frequency 0:Spec; 1:Once; 2:Auto");
 
@@ -424,7 +424,7 @@ static long CoreFreqK_Register_ClockSource(unsigned int cpu)
     }
 	return rc;
 }
-
+/*
 static void VendorFromMainID(	MIDR midr, char *pVendorID, unsigned int *pCRC,
 				enum HYPERVISOR *pHypervisor )
 {
@@ -437,7 +437,7 @@ static const struct {
     } mfrTbl[] = {
 	{	0x00,	VENDOR_RESERVED, __builtin_strlen(VENDOR_RESERVED),
 		CRC_RESERVED,	BARE_METAL				},
-	{	0x41,	VENDOR_ARM,	__builtin_strlen(VENDOR_ARM),
+	{	0x41,	VENDOR_RISC,	__builtin_strlen(VENDOR_RISC),
 		CRC_ARM,	BARE_METAL				},
 	{	0x42,	VENDOR_BROADCOM, __builtin_strlen(VENDOR_BROADCOM),
 		CRC_BROADCOM,	BARE_METAL				},
@@ -469,1414 +469,95 @@ static const struct {
     };
 	unsigned int idx;
     for (idx = 0; idx < sizeof(mfrTbl) / sizeof(mfrTbl[0]); idx++) {
-	if (midr.Implementer == mfrTbl[idx].implementer)
-	{
-		memcpy(pVendorID, mfrTbl[idx].vendorID, mfrTbl[idx].vendorLen);
-		(*pCRC) = mfrTbl[idx].mfrCRC;
-		(*pHypervisor) = mfrTbl[idx].hypervisor;
-
-		return;
-	}
-    }
-}
-
-static signed int SearchArchitectureID(void)
-{
-	signed int id;
-    for (id = ARCHITECTURES - 1; id > 0; id--)
-    {	/* Search for an architecture signature. */
-	if ( (PUBLIC(RO(Proc))->Features.Info.Signature.ExtFamily \
-		== Arch[id].Signature.ExtFamily)
-	&& (PUBLIC(RO(Proc))->Features.Info.Signature.Family \
-		== Arch[id].Signature.Family)
-	&& ( ( (PUBLIC(RO(Proc))->Features.Info.Signature.ExtModel \
-			==  Arch[id].Signature.ExtModel)
-		&& (PUBLIC(RO(Proc))->Features.Info.Signature.Model \
-			==  Arch[id].Signature.Model) )
-		|| (!Arch[id].Signature.ExtModel \
-		&& !Arch[id].Signature.Model) ) )
-	{
-		break;
-	}
-    }
-	return id;
-}
-
-/* Retreive the Processor(BSP) features. */
-static void Query_Features(void *pArg)
-{
-	INIT_ARG *iArg = (INIT_ARG *) pArg;
-
-	volatile MIDR midr;
-	volatile CNTFRQ cntfrq;
-	volatile CNTPCT cntpct;
-	volatile PMCR pmcr;
-	volatile AA64DFR0 dfr0;
-	volatile AA64DFR1 dfr1;
-	volatile AA64ISAR0 isar0;
-	volatile AA64ISAR1 isar1;
-	volatile AA64ISAR2 isar2;
-	volatile AA64ISAR3 isar3;
-	volatile AA64MMFR0 mmfr0;
-	volatile AA64MMFR1 mmfr1;
-	volatile AA64MMFR2 mmfr2;
-	volatile AA64PFR0 pfr0;
-	volatile AA64PFR1 pfr1;
-	volatile AA64PFR2 pfr2;
-	volatile MVFR0 mvfr0;
-	volatile MVFR1 mvfr1;
-	volatile MVFR2 mvfr2;
-
-	iArg->Features->Info.Vendor.CRC = CRC_RESERVED;
-	iArg->SMT_Count = 1;
-	iArg->HypervisorID = HYPERV_NONE;
-/*
-	__asm__ __volatile__(
-		"mrs	%[midr] ,	midr_el1"	"\n\t"
-		"mrs	%[cntfrq],	cntfrq_el0"	"\n\t"
-		"mrs	%[cntpct],	cntpct_el0"	"\n\t"
-		"mrs	%[pmcr] ,	pmcr_el0"	"\n\t"
-		"mrs	%[dfr0] ,	id_aa64dfr0_el1""\n\t"
-		"mrs	%[dfr1] ,	id_aa64dfr1_el1""\n\t"
-		"mrs	%[isar0],	id_aa64isar0_el1""\n\t"
-		"mrs	%[isar1],	id_aa64isar1_el1""\n\t"
-		"mrs	%[mmfr0],	id_aa64mmfr0_el1""\n\t"
-		"mrs	%[mmfr1],	id_aa64mmfr1_el1""\n\t"
-		"mrs	%[pfr0] ,	id_aa64pfr0_el1""\n\t"
-		"mrs	%[pfr1] ,	id_aa64pfr1_el1""\n\t"
-		"mrs	%[mvfr0],	mvfr0_el1"	"\n\t"
-		"mrs	%[mvfr1],	mvfr1_el1"	"\n\t"
-		"mrs	%[mvfr2],	mvfr2_el1"	"\n\t"
-		"isb"
-		: [midr]	"=r" (midr),
-		  [cntfrq]	"=r" (cntfrq),
-		  [cntpct]	"=r" (cntpct),
-		  [pmcr]	"=r" (pmcr),
-		  [dfr0]	"=r" (dfr0),
-		  [dfr1]	"=r" (dfr1),
-		  [isar0]	"=r" (isar0),
-		  [isar1]	"=r" (isar1),
-		  [mmfr0]	"=r" (mmfr0),
-		  [mmfr1]	"=r" (mmfr1),
-		  [pfr0]	"=r" (pfr0),
-		  [pfr1]	"=r" (pfr1),
-		  [mvfr0]	"=r" (mvfr0),
-		  [mvfr1]	"=r" (mvfr1),
-		  [mvfr2]	"=r" (mvfr2)
-		:
-		: "memory"
-	);
-
-	isar2.value = SysRegRead(ID_AA64ISAR2_EL1);
-	isar3.value = SysRegRead(ID_AA64ISAR3_EL1);
-	mmfr2.value = SysRegRead(ID_AA64MMFR2_EL1);
-*/
-	iArg->Features->Info.Signature.Stepping = midr.Revision
-						| (midr.Variant << 4);
-	iArg->Features->Info.Signature.Family = midr.PartNum & 0x00f;
-	iArg->Features->Info.Signature.ExtFamily = (midr.PartNum & 0xff0) >> 4;
-	iArg->Features->Info.Signature.Model = pmcr.IDcode & 0x0f;
-	iArg->Features->Info.Signature.ExtModel = (pmcr.IDcode & 0xf0) >> 4;
-
-	VendorFromMainID(midr, iArg->Features->Info.Vendor.ID,
-			&iArg->Features->Info.Vendor.CRC, &iArg->HypervisorID);
-
-	iArg->Features->Factory.Freq = cntfrq.ClockFreq_Hz;
-	iArg->Features->Factory.Freq = iArg->Features->Factory.Freq / 10000;
-
-#if defined(CONFIG_ACPI)
-	iArg->Features->ACPI = acpi_disabled == 0;
-#else
-	iArg->Features->ACPI = 0;
-#endif
-	iArg->Features->TSC = \
-	iArg->Features->Inv_TSC = \
-	iArg->Features->RDTSCP = cntpct.PhysicalCount != 0;
-
-	iArg->Features->PerfMon.FixCtrs = 0;
-	iArg->Features->PerfMon.MonCtrs = pmcr.NumEvtCtrs;
-	iArg->Features->PerfMon.Version = dfr0.PMUVer;
-	if (iArg->Features->PerfMon.Version > 0) {
-		iArg->Features->PerfMon.FixCtrs++; /* Fixed Cycle Counter */
-	}
-	/*TODO(Memory-mapped PMU register at offset 0xe00): pmcfgr	*/
-	iArg->Features->PerfMon.MonWidth = \
-	iArg->Features->PerfMon.FixWidth = 0b111111 == 0b111111 ? 64 : 0;
-
-	switch (dfr1.PMICNTR) { /* Performance Monitors Instruction Counter */
-	case 0b0001:
-		iArg->Features->PerfMon.FixCtrs++;
-		break;
-	case 0b0000:
-	default:
-		break;
-	}
-	switch (dfr1.EBEP) {
-	case 0b0001:
-		iArg->Features->EBEP = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->EBEP = 0;
-		break;
-	}
-	switch (isar0.AES) {
-	case 0b0010:
-		iArg->Features->PMULL = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->AES = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->PMULL = \
-		iArg->Features->AES = 0;
-		break;
-	}
-	switch (isar0.SHA1) {
-	case 0b0001:
-		iArg->Features->SHA1 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SHA1 = 0;
-		break;
-	}
-	switch (isar0.SHA2) {
-	case 0b0010:
-		iArg->Features->SHA512 = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->SHA256 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SHA512 = 0;
-		iArg->Features->SHA256 = 0;
-		break;
-	}
-	switch (isar0.SHA3) {
-	case 0b0001:
-		iArg->Features->SHA3 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SHA3 = 0;
-		break;
-	}
-	switch (isar0.CRC32) {
-	case 0b0001:
-		iArg->Features->CRC32 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->CRC32 = 0;
-		break;
-	}
-	switch (isar0.Atomic) {
-	case 0b0011:
-		iArg->Features->LSE128 = 1;
-		fallthrough;
-	case 0b0010:
-		iArg->Features->LSE = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->LSE128 = \
-		iArg->Features->LSE = 0;
-		break;
-	}
-	switch (isar0.TME) {
-	case 0b0001:
-		iArg->Features->TME = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->TME = 0;
-		break;
-	}
-	switch (isar0.RDM) {
-	case 0b0001:
-		iArg->Features->RDMA = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->RDMA = 0;
-		break;
-	}
-	switch (isar0.DP) {
-	case 0b0001:
-		iArg->Features->DP = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->DP = 0;
-		break;
-	}
-	switch (isar0.SM3) {
-	case 0b0001:
-		iArg->Features->SM3 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SM3 = 0;
-		break;
-	}
-	switch (isar0.SM4) {
-	case 0b0001:
-		iArg->Features->SM4 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SM4 = 0;
-		break;
-	}
-	switch (isar0.FHM) {
-	case 0b0001:
-		iArg->Features->FHM = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FHM = 0;
-		break;
-	}
-	switch (isar0.TS) {
-	case 0b0010:
-		iArg->Features->FlagM2 = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->FlagM = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FlagM2 = \
-		iArg->Features->FlagM = 0;
-		break;
-	}
-	switch (isar0.TLB) {
-	case 0b0010:
-		iArg->Features->TLBIRANGE = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->TLBIOS = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->TLBIRANGE = \
-		iArg->Features->TLBIOS = 0;
-		break;
-	}
-	switch (isar0.RNDR) {
-	case 0b0001:
-		iArg->Features->RAND = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->RAND = 0;
-		break;
-	}
-	switch (isar1.FCMA) {
-	case 0b0001:
-		iArg->Features->FCMA = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FCMA = 0;
-		break;
-	}
-	switch (isar1.GPI) {
-	case 0b0001:
-		iArg->Features->PACIMP = 1;
-		break;
-	case 0b0000:
-		iArg->Features->PACIMP = 0;
-		break;
-	}
-	switch (isar1.GPA) {
-	case 0b0001:
-		iArg->Features->PACQARMA5 = 1;
-		break;
-	case 0b0000:
-		iArg->Features->PACQARMA5 = 0;
-		break;
-	}
-	switch (isar1.LRCPC) {
-	case 0b0011:
-		iArg->Features->LRCPC3 = 1;
-		fallthrough;
-	case 0b0010:
-		iArg->Features->LRCPC2 = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->LRCPC = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->LRCPC3 = \
-		iArg->Features->LRCPC2 = \
-		iArg->Features->LRCPC = 0;
-		break;
-	}
-	switch (isar1.JSCVT) {
-	case 0b0001:
-		iArg->Features->JSCVT = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->JSCVT = 0;
-		break;
-	}
-	switch (isar1.FRINTTS) {
-	case 0b0001:
-		iArg->Features->FRINTTS = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FRINTTS = 0;
-		break;
-	}
-	switch (isar1.SPECRES) {
-	case 0b0010:
-		iArg->Features->SPECRES2 = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->SPECRES = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SPECRES2 = \
-		iArg->Features->SPECRES = 0;
-		break;
-	}
-	switch (isar1.BF16) {
-	case 0b0010:
-		iArg->Features->EBF16 = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->BF16 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->EBF16 = \
-		iArg->Features->BF16 = 0;
-		break;
-	}
-	switch (isar1.I8MM) {
-	case 0b0001:
-		iArg->Features->I8MM = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->I8MM = 0;
-		break;
-	}
-	switch (isar1.SB) {
-	case 0b0001:
-		iArg->Features->SB = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SB = 0;
-		break;
-	}
-	switch (isar1.XS) {
-	case 0b0001:
-		iArg->Features->XS = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->XS = 0;
-		break;
-	}
-	switch (isar1.LS64) {
-	case 0b0011:
-		iArg->Features->LS64_ACCDATA = 1;
-		fallthrough;
-	case 0b0010:
-		iArg->Features->LS64_V = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->LS64 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->LS64_ACCDATA = \
-		iArg->Features->LS64_V = \
-		iArg->Features->LS64 = 0;
-		break;
-	}
-	switch (isar1.DGH) {
-	case 0b0001:
-		iArg->Features->DGH = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->DGH = 0;
-		break;
-	}
-	switch (isar1.DPB) {
-	case 0b0010:
-		iArg->Features->DPB2 = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->DPB = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->DPB2 = \
-		iArg->Features->DPB = 0;
-		break;
-	}
-	switch (isar2.GPA3) {
-	case 0b0001:
-		iArg->Features->PACQARMA3 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->PACQARMA3 = 0;
-		break;
-	}
-
-	iArg->Features->PAuth = (isar2.APA3 == 0b0001) || (isar1.API == 0b0001)
-				|| (isar1.APA == 0b0001);
-
-	iArg->Features->EPAC = (isar2.APA3 == 0b0010) || (isar1.API == 0b0010)
-				|| (isar1.APA == 0b0010);
-
-	iArg->Features->PAuth2 = (isar2.APA3 == 0b0011) || (isar1.API == 0b0011)
-				|| (isar1.APA == 0b0011);
-
-	iArg->Features->FPAC = (isar2.APA3 == 0b0100) || (isar1.API == 0b0100)
-				|| (isar1.APA == 0b0100);
-
-	iArg->Features->FPACCOMBINE = (isar2.APA3 == 0b0101)
-				|| (isar1.API == 0b0101)||(isar1.APA == 0b0101);
-
-	iArg->Features->PAuth_LR = (isar2.APA3 == 0b0110)
-				|| (isar1.API == 0b0110)||(isar1.APA == 0b0110);
-
-	switch (isar2.WFxT) {
-	case 0b0001:
-		iArg->Features->WFxT = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->WFxT = 0;
-		break;
-	}
-	switch (isar2.RPRES) {
-	case 0b0001:
-		iArg->Features->RPRES = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->RPRES = 0;
-		break;
-	}
-	switch (isar2.MOPS) {
-	case 0b0001:
-		iArg->Features->MOPS = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->MOPS = 0;
-		break;
-	}
-	switch (isar2.BC) {
-	case 0b0001:
-		iArg->Features->HBC = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->HBC = 0;
-		break;
-	}
-	switch (isar2.CLRBHB) {
-	case 0b0001:
-		iArg->Features->CLRBHB = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->CLRBHB = 0;
-		break;
-	}
-	switch (isar2.SYSREG_128) {
-	case 0b0001:
-		iArg->Features->SYSREG128 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SYSREG128 = 0;
-		break;
-	}
-	switch (isar2.SYSINSTR_128) {
-	case 0b0001:
-		iArg->Features->SYSINSTR128 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SYSINSTR128 = 0;
-		break;
-	}
-	switch (isar2.PRFMSLC) {
-	case 0b0001:
-		iArg->Features->PRFMSLC = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->PRFMSLC = 0;
-		break;
-	}
-	switch (isar2.PCDPHINT) {
-	case 0b0001:
-		iArg->Features->PCDPHINT = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->PCDPHINT = 0;
-		break;
-	}
-	switch (isar2.RPRFM) {
-	case 0b0001:
-		iArg->Features->RPRFM = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->RPRFM = 0;
-		break;
-	}
-	switch (isar2.CSSC) {
-	case 0b0001:
-		iArg->Features->CSSC = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->CSSC = 0;
-		break;
-	}
-	switch (isar2.LUT) {
-	case 0b0001:
-		iArg->Features->LUT = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->LUT = 0;
-		break;
-	}
-	switch (isar2.ATS1A) {
-	case 0b0001:
-		iArg->Features->ATS1A = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->ATS1A = 0;
-		break;
-	}
-	switch (isar2.PAC_frac) {
-	case 0b0001:
-		iArg->Features->CONSTPACFIELD = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->CONSTPACFIELD = 0;
-		break;
-	}
-
-	switch (isar3.CPA) {
-	case 0b0010:
-	case 0b0001:
-		iArg->Features->CPA = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->CPA = 0;
-		break;
-	}
-	switch (isar3.FAMINMAX) {
-	case 0b0001:
-		iArg->Features->FAMINMAX = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FAMINMAX = 0;
-		break;
-	}
-	switch (isar3.TLBIW) {
-	case 0b0001:
-		iArg->Features->TLBIW = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->TLBIW = 0;
-		break;
-	}
-	switch (isar3.PACM) {
-	case 0b0010:
-	case 0b0001:
-		iArg->Features->PACM = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->PACM = 0;
-		break;
-	}
-	switch (isar3.LSFE) {
-	case 0b0001:
-		iArg->Features->LSFE = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->LSFE = 0;
-		break;
-	}
-	switch (isar3.OCCMO) {
-	case 0b0001:
-		iArg->Features->OCCMO = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->OCCMO = 0;
-		break;
-	}
-	switch (isar3.LSUI) {
-	case 0b0001:
-		iArg->Features->LSUI = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->LSUI = 0;
-		break;
-	}
-	switch (isar3.FPRCVT) {
-	case 0b0001:
-		iArg->Features->FPRCVT = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FPRCVT = 0;
-		break;
-	}
-
-	switch (mmfr0.ECV) {
-	case 0b0010:
-	case 0b0001:
-		iArg->Features->ECV = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->ECV = 0;
-		break;
-	}
-	switch (mmfr0.FGT) {
-	case 0b0010:
-		iArg->Features->FGT2 = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->FGT = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FGT2 = \
-		iArg->Features->FGT = 0;
-	}
-	switch (mmfr0.ExS) {
-	case 0b0001:
-		iArg->Features->ExS = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->ExS = 0;
-		break;
-	}
-	switch (mmfr0.BigEnd_EL0) {
-	case 0b0001:
-		iArg->Features->BigEnd_EL0 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->BigEnd_EL0 = 0;
-		break;
-	}
-	switch (mmfr0.BigEnd) {
-	case 0b0001:
-		iArg->Features->BigEnd_EE = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->BigEnd_EE = 0;
-		break;
-	}
-
-	iArg->Features->PARange = mmfr0.PARange;
-
-	switch (mmfr1.VH) {
-	case 0b0001:
-		iArg->Features->VHE = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->VHE = 0;
-		break;
-	}
-	switch (mmfr1.PAN) {
-	case 0b0001:
-	case 0b0010:
-	case 0b0011:
-		iArg->Features->PAN = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->PAN = 0;
-		break;
-	}
-	switch (mmfr1.ECBHB) {
-	case 0b0001:
-		iArg->Features->ECBHB = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->ECBHB = 0;
-		break;
-	}
-
-	switch (mmfr2.UAO) {
-	case 0b0001:
-		iArg->Features->UAO = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->UAO = 0;
-		break;
-	}
-	if (mmfr2.VARange < 0b0011) {
-		iArg->Features->VARange = mmfr2.VARange;
-	} else {
-		iArg->Features->VARange = 0b11;
-	}
-
-	switch (pfr0.FP) {
-	case 0b0000:
-	case 0b0001:
-		iArg->Features->FP = 1;
-		break;
-	case 0b1111:
-	default:
-		iArg->Features->FP = 0;
-		break;
-	}
-	switch (pfr0.AdvSIMD) {
-	case 0b0000:
-	case 0b0001:
-		iArg->Features->SIMD = 1;
-		break;
-	case 0b1111:
-	default:
-		iArg->Features->SIMD = 0;
-		break;
-	}
-	switch (pfr0.GIC) {
-	case 0b0011:
-		iArg->Features->GIC_frac = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->GIC_vers = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->GIC_frac = \
-		iArg->Features->GIC_vers = 0;
-		break;
-	}
-	switch (pfr0.SVE) {
-	case 0b0001:
-		iArg->Features->SVE = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SVE = 0;
-		break;
-	}
-	switch (pfr0.DIT) {
-	case 0b0001:
-	case 0b0010:
-		iArg->Features->DIT = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->DIT = 0;
-		break;
-	}
-	switch (pfr0.RAS) {
-	case 0b0010:
-		iArg->Features->RAS_frac = 1;
-		iArg->Features->RAS = 1;
-		break;
-	case 0b0001:
-		switch (pfr1.RAS_frac) {
-		case 0b0001:
-			iArg->Features->RAS_frac = 1;
-			break;
-		case 0b0000:
-		default:
-			iArg->Features->RAS_frac = 0;
-			break;
-		}
-		iArg->Features->RAS = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->RAS_frac = 0;
-		iArg->Features->RAS = 0;
-		break;
-	}
-	switch (pfr0.MPAM) {
-	case 0b0000:
-	case 0b0001:
-		iArg->Features->MPAM_vers = pfr0.MPAM;
-		switch (pfr1.MPAM_frac) {
-		case 0b0000:
-		case 0b0001:
-			iArg->Features->MPAM_frac = pfr1.MPAM_frac;
-			break;
-		default:
-			iArg->Features->MPAM_frac = 0;
-			break;
-		}
-		break;
-	default:
-		iArg->Features->MPAM_vers = \
-		iArg->Features->MPAM_frac = 0;
-		break;
-	}
-	switch (pfr0.AMU) {
-	case 0b0001:
-		iArg->Features->AMU_vers = 1;
-		iArg->Features->AMU_frac = 0;
-		break;
-	case 0b0010:
-		iArg->Features->AMU_vers = 1;
-		iArg->Features->AMU_frac = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->AMU_vers = 0;
-		iArg->Features->AMU_frac = 0;
-		break;
-	}
-	if (iArg->Features->AMU_vers > 0) {
-/*		AMCGCR amcgc = {.value = SysRegRead(AMCGCR_EL0)};
-		iArg->Features->AMU.CG0NC = amcgc.CG0NC;
-		iArg->Features->AMU.CG1NC = amcgc.CG1NC;*/
-	}
-	switch (pfr0.RME) {
-	case 0b0001:
-		iArg->Features->RME = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->RME = 0;
-		break;
-	}
-	switch (pfr0.SEL2) {
-	case 0b0001:
-		iArg->Features->SEL2 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SEL2 = 0;
-		break;
-	}
-
-	switch (pfr1.BT) {
-	case 0b0001:
-		iArg->Features->BTI = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->BTI = 0;
-		break;
-	}
-
-	iArg->Features->SSBS = pfr1.SSBS;
-
-	switch (pfr1.MTE) {
-	case 0b0010:
-		switch (pfr1.MTE_frac) {
-		case 0b0000:
-			iArg->Features->MTE = 3;
-			break;
-		case 0b1111:
-			iArg->Features->MTE = 2;
-			break;
-		default:
-			iArg->Features->MTE = 1;
-			break;
-		}
-		break;
-	case 0b0011:
-	default:
-		switch (pfr1.MTEX) {
-		case 0b0001:
-			iArg->Features->MTE = 4;
-			break;
-		case 0b0000:
-		default:
-			iArg->Features->MTE = 3;
-			break;
-		}
-		break;
-	case 0b0001:
-		iArg->Features->MTE = 1;
-		break;
-	case 0b0000:
-		iArg->Features->MTE = 0;
-		break;
-	}
-	switch (pfr1.SME) {
-	case 0b0001:
-	case 0b0010:
-		iArg->Features->SME = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SME = 0;
-		break;
-	}
-	switch (pfr1.RNDR_trap) {
-	case 0b0001:
-		iArg->Features->RNG_TRAP = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->RNG_TRAP = 0;
-		break;
-	}
-
-	iArg->Features->CSV2 = pfr1.CSV2_frac;
-
-	switch (pfr1.NMI) {
-	case 0b0001:
-		iArg->Features->NMI = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->NMI = 0;
-		break;
-	}
-	switch (pfr1.GCS) {
-	case 0b0001:
-		iArg->Features->GCS = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->GCS = 0;
-		break;
-	}
-	switch (pfr1.THE) {
-	case 0b0001:
-		iArg->Features->THE = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->THE = 0;
-		break;
-	}
-	switch (pfr1.DF2) {
-	case 0b0001:
-		iArg->Features->DF2 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->DF2 = 0;
-		break;
-	}
-	switch (pfr1.PFAR) {
-	case 0b0001:
-		iArg->Features->PFAR = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->PFAR = 0;
-		break;
-	}
-/*
-	pfr2.value = SysRegRead(ID_AA64PFR2_EL1);
-*/
-	switch(pfr2.FPMR) {
-	case 0b0001:
-		iArg->Features->FPMR = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FPMR = 0;
-		break;
-	}
-	switch(pfr2.UINJ) {
-	case 0b0001:
-		iArg->Features->UINJ = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->UINJ = 0;
-		break;
-	}
-	switch(pfr2.MTEFAR) {
-	case 0b0001:
-		iArg->Features->MTE_FAR = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->MTE_FAR = 0;
-		break;
-	}
-	switch(pfr2.MTESTOREONLY) {
-	case 0b0001:
-		iArg->Features->MTE_STOREONLY = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->MTE_STOREONLY = 0;
-		break;
-	}
-	switch(pfr2.MTEPERM) {
-	case 0b0001:
-		iArg->Features->MTE_PERM = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->MTE_PERM = 0;
-		break;
-	}
-
-    if (iArg->Features->SVE | iArg->Features->SME)
-    {
-/*	volatile AA64ZFR0 zfr0 = {.value = SysRegRead(ID_AA64ZFR0_EL1)};
+	if (midr.Implementer == mfrTbl[idx].implementer)
+	{
+		memcpy(pVendorID, mfrTbl[idx].vendorID, mfrTbl[idx].vendorLen);
+		(*pCRC) = mfrTbl[idx].mfrCRC;
+		(*pHypervisor) = mfrTbl[idx].hypervisor;
 
-	switch (zfr0.SVE_F64MM) {
-	case 0b0001:
-		iArg->Features->SVE_F64MM = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SVE_F64MM = 0;
-		break;
-	}
-	switch (zfr0.SVE_F32MM) {
-	case 0b0001:
-		iArg->Features->SVE_F32MM = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SVE_F32MM = 0;
-		break;
-	}
-	switch (zfr0.SVE_I8MM) {
-	case 0b0001:
-		iArg->Features->SVE_I8MM = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SVE_I8MM = 0;
-		break;
-	}
-	switch (zfr0.SVE_SM4) {
-	case 0b0001:
-		iArg->Features->SVE_SM4 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SVE_SM4 = 0;
-		break;
-	}
-	switch (zfr0.SVE_SHA3) {
-	case 0b0001:
-		iArg->Features->SVE_SHA3 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SVE_SHA3 = 0;
-		break;
-	}
-	switch (zfr0.SVE_BF16) {
-	case 0b0010:
-		iArg->Features->SVE_EBF16 = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->SVE_BF16 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SVE_EBF16 = \
-		iArg->Features->SVE_BF16 = 0;
-		break;
-	}
-	switch (zfr0.BitPerm) {
-	case 0b0001:
-		iArg->Features->SVE_BitPerm = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SVE_BitPerm = 0;
-		break;
-	}
-	switch (zfr0.SVE_AES) {
-	case 0b0010:
-		iArg->Features->SVE_PMULL128 = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->SVE_AES = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SVE_PMULL128 = \
-		iArg->Features->SVE_AES = 0;
+		return;
 	}
-	switch (zfr0.SVE_Ver) {
-	case 0b0001:
-		iArg->Features->SVE2 = 1;
-		break;
-	default:
-		iArg->Features->SVE2 = 0;
-		break;
-	}*/
     }
-    if (iArg->Features->SME) {
-/*	volatile AA64SMFR0 smfr0 = {.value = SysRegRead(ID_AA64SMFR0_EL1)};
-
-	switch (smfr0.SMEver) {
-	case 0b0010:
-		iArg->Features->SME2p1 = 1;
-		fallthrough;
-	case 0b0001:
-		iArg->Features->SME2 = 1;
-		break;
-	default:
-		iArg->Features->SME2p1 = \
-		iArg->Features->SME2 = 0;
+}
+*/
+static signed int SearchArchitectureID(void)
+{
+	signed int id;
+    for (id = ARCHITECTURES - 1; id > 0; id--)
+    {	/* Search for an architecture signature. */
+	if ( (PUBLIC(RO(Proc))->Features.Info.Signature.ExtFamily \
+		== Arch[id].Signature.ExtFamily)
+	&& (PUBLIC(RO(Proc))->Features.Info.Signature.Family \
+		== Arch[id].Signature.Family)
+	&& ( ( (PUBLIC(RO(Proc))->Features.Info.Signature.ExtModel \
+			==  Arch[id].Signature.ExtModel)
+		&& (PUBLIC(RO(Proc))->Features.Info.Signature.Model \
+			==  Arch[id].Signature.Model) )
+		|| (!Arch[id].Signature.ExtModel \
+		&& !Arch[id].Signature.Model) ) )
+	{
 		break;
 	}
+    }
+	return id;
+}
 
-	iArg->Features->SME_FA64 = smfr0.FA64;
-	iArg->Features->SME_LUTv2 = smfr0.LUTv2;
+/* Retreive the Processor(BSP) features. */
+static void Query_Features(void *pArg)
+{
+	INIT_ARG *iArg = (INIT_ARG *) pArg;
+/*	volatile unsigned long long cntfrq;	TODO*/
 
-	switch (smfr0.I16I64) {
-	case 0b1111:
-		iArg->Features->SME_I16I64 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SME_I16I64 = 0;
-		break;
-	}
+	iArg->Features->Info.Vendor.CRC = CRC_RESERVED;
+	iArg->SMT_Count = 1;
+	iArg->HypervisorID = HYPERV_NONE;
+/*TODO
+	__asm__ __volatile__(
+		"csrr	%[cntfrq],	mcycle" "\n\t"
+		"fence iorw, iorw"
+		: [cntfrq]	"=r" (cntfrq)
+		:
+		: "memory"
+	);
+*/
+	iArg->Features->Info.Signature.Stepping = 0;
+	iArg->Features->Info.Signature.Family = 0 & 0x00f;
+	iArg->Features->Info.Signature.ExtFamily = (0 & 0xff0) >> 4;
+	iArg->Features->Info.Signature.Model = 0 & 0x0f;
+	iArg->Features->Info.Signature.ExtModel = (0 & 0xf0) >> 4;
+/*
+	VendorFromMainID(midr, iArg->Features->Info.Vendor.ID,
+			&iArg->Features->Info.Vendor.CRC, &iArg->HypervisorID);
 
-	iArg->Features->SME_F64F64 = smfr0.F64F64;
+	iArg->Features->Factory.Freq = cntfrq;
+	iArg->Features->Factory.Freq = iArg->Features->Factory.Freq / 1U;
+*/
+	iArg->Features->Factory.Freq = 1000;
 
-	switch (smfr0.I16I32) {
-	case 0b0101:
-		iArg->Features->SME_I16I32 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SME_I16I32 = 0;
-		break;
-	}
+#if defined(CONFIG_ACPI)
+	iArg->Features->ACPI = acpi_disabled == 0;
+#else
+	iArg->Features->ACPI = 0;
+#endif
+/*
+	iArg->Features->TSC = \
+	iArg->Features->Inv_TSC = \
+	iArg->Features->RDTSCP = cntfrq != 0;
+*/
+	iArg->Features->TSC = \
+	iArg->Features->Inv_TSC = \
+	iArg->Features->RDTSCP = 0;
 
-	iArg->Features->SME_B16B16 = smfr0.B16B16;
-	iArg->Features->SME_F16F16 = smfr0.F16F16;
-	iArg->Features->SME_F8F16 = smfr0.F8F16;
-	iArg->Features->SME_F8F32 = smfr0.F8F32;
+	iArg->Features->PerfMon.FixCtrs = \
+	iArg->Features->PerfMon.MonCtrs = \
+	iArg->Features->PerfMon.Version = 0;
 
-	switch (smfr0.I8I32) {
-	case 0b1111:
-		iArg->Features->SME_I8I32 = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SME_I8I32 = 0;
-		break;
+	if (iArg->Features->PerfMon.Version > 0) {
+		iArg->Features->PerfMon.FixCtrs++; /* Fixed Cycle Counter */
 	}
 
-	iArg->Features->SME_F16F32 = smfr0.F16F32;
-	iArg->Features->SME_B16F32 = smfr0.B16F32;
-	iArg->Features->SME_BI32I32 = smfr0.BI32I32;
-	iArg->Features->SME_F32F32 = smfr0.F32F32;
-	iArg->Features->SME_SF8FMA = smfr0.SF8FMA;
-	iArg->Features->SME_SF8DP4 = smfr0.SF8DP4;
-	iArg->Features->SME_SF8DP2 = smfr0.SF8DP2;*/
-    }
-	switch (mvfr0.FPRound) {
-	case 0b0001:
-		iArg->Features->FP_Round = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FP_Round = 0;
-		break;
-	}
-	switch (mvfr0.FPShVec) {
-	case 0b0001:
-		iArg->Features->FP_Sh_Vec = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FP_Sh_Vec = 0;
-		break;
-	}
-	switch (mvfr0.FPSqrt) {
-	case 0b0001:
-		iArg->Features->FP_Sqrt = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FP_Sqrt = 0;
-		break;
-	}
-	switch (mvfr0.FPDivide) {
-	case 0b0001:
-		iArg->Features->FP_Divide = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FP_Divide = 0;
-		break;
-	}
-	switch (mvfr0.FPTrap) {
-	case 0b0001:
-		iArg->Features->FP_Trap = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FP_Trap = 0;
-		break;
-	}
-	switch (mvfr0.FPDP) {
-	case 0b0010:
-	case 0b0001:
-		iArg->Features->FP_DP = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FP_DP = 0;
-		break;
-	}
-	switch (mvfr0.FPSP) {
-	case 0b0010:
-	case 0b0001:
-		iArg->Features->FP_SP = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FP_SP = 0;
-		break;
-	}
-	switch (mvfr1.FPHP) {
-	case 0b0011:
-	case 0b0010:
-	case 0b0001:
-		iArg->Features->FP_HP = 1;
-		break;
-	default:
-	case 0b0000:
-		iArg->Features->FP_HP = 0;
-		break;
-	}
-	switch (mvfr0.SIMDReg) {
-	case 0b0010:
-	case 0b0001:
-		iArg->Features->SIMD_Reg = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SIMD_Reg = 0;
-		break;
-	}
-	switch (mvfr1.SIMDFMAC) {
-	case 0b0001:
-		iArg->Features->SIMD_FMA = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SIMD_FMA = 0;
-		break;
-	}
-	switch (mvfr1.SIMDHP) {
-	case 0b0010:
-	case 0b0001:
-		iArg->Features->SIMD_HP = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SIMD_HP = 0;
-		break;
-	}
-	switch (mvfr1.SIMDSP) {
-	case 0b0001:
-		iArg->Features->SIMD_SP = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SIMD_SP = 0;
-		break;
-	}
-	switch (mvfr1.SIMDInt) {
-	case 0b0001:
-		iArg->Features->SIMD_Int = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SIMD_Int = 0;
-		break;
-	}
-	switch (mvfr1.SIMDLS) {
-	case 0b0001:
-		iArg->Features->SIMD_LS = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SIMD_LS = 0;
-		break;
-	}
-	switch (mvfr1.FPDNaN) {
-	case 0b0001:
-		iArg->Features->FP_NaN = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FP_NaN = 0;
-		break;
-	}
-	switch (mvfr1.FPFtZ) {
-	case 0b0001:
-		iArg->Features->FP_FtZ = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FP_FtZ = 0;
-		break;
-	}
-	switch (mvfr2.FPMisc) {
-	case 0b0100:
-	case 0b0011:
-	case 0b0010:
-	case 0b0001:
-		iArg->Features->FP_Misc = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->FP_Misc = 0;
-		break;
-	}
-	switch (mvfr2.SIMDMisc) {
-	case 0b0011:
-	case 0b0010:
-	case 0b0001:
-		iArg->Features->SIMD_Misc = 1;
-		break;
-	case 0b0000:
-	default:
-		iArg->Features->SIMD_Misc = 0;
-		break;
-	}
+	iArg->Features->PerfMon.MonWidth = \
+	iArg->Features->PerfMon.FixWidth = 0b111111 == 0b111111 ? 64 : 0;
 	/* Reset the performance features bits: present is 0b1		*/
 	iArg->Features->PerfMon.CoreCycles    = 0b0;
 	iArg->Features->PerfMon.InstrRetired  = 0b0;
@@ -2047,73 +728,46 @@ static CLOCK BaseClock_GenericMachine(unsigned int ratio)
 	UNUSED(ratio);
 	return clock;
 };
-
+/*
 static void Cache_Level(CORE_RO *Core, unsigned int level, unsigned int select)
 {
 	const CSSELR cssel[CACHE_MAX_LEVEL] = {
-		[0] = { .InD = 1, .Level = 0 }, /*	L1I	*/
-		[1] = { .InD = 0, .Level = 0 }, /*	L1D	*/
-		[2] = { .InD = 0, .Level = 1 }, /*	L2	*/
-		[3] = { .InD = 0, .Level = 2 }	/*	L3	*/
+		[0] = { .InD = 1, .Level = 0 }, **	L1I	**
+		[1] = { .InD = 0, .Level = 0 }, **	L1D	**
+		[2] = { .InD = 0, .Level = 1 }, **	L2	**
+		[3] = { .InD = 0, .Level = 2 }	**	L3	**
 	};
-/*	__asm__ volatile
-	(
-		"msr	csselr_el1,	%[cssel]"	"\n\t"
-		"mrs	%[ccsid],	ccsidr_el1"	"\n\t"
-		"isb"
-		: [ccsid]	"=r" (Core->T.Cache[level].ccsid)
-		: [cssel]	"r"  (cssel[select])
-		: "memory"
-	);*/
 }
-
+*/
 static void Cache_Topology(CORE_RO *Core)
 {
-	volatile CLIDR clidr;
-/*	__asm__ volatile
-	(
-		"mrs	%[clidr],	clidr_el1"	"\n\t"
-		"isb"
-		: [clidr]	"=r" (clidr)
-		:
-		: "memory"
-	);*/
+/*
+	volatile unsigned long long clidr;
 
 	if (clidr.Ctype1 == 0b011) {
-		Cache_Level(Core, 0, 0);	/*	L1I		*/
-		Cache_Level(Core, 1, 1);	/*	L1D		*/
+		Cache_Level(Core, 0, 0);	**	L1I		**
+		Cache_Level(Core, 1, 1);	**	L1D		**
 	} else if (clidr.Ctype1 == 0b010) {
-						/*	Skip L1I	*/
-		Cache_Level(Core, 1, 1);	/*	L1D		*/
+						**	Skip L1I	**
+		Cache_Level(Core, 1, 1);	**	L1D		**
 	} else if (clidr.Ctype1 == 0b001) {
-		Cache_Level(Core, 0, 0);	/*	L1I		*/
-						/*	Skip L1D	*/
+		Cache_Level(Core, 0, 0);	**	L1I		**
+						**	Skip L1D	**
 	}
-	if (clidr.Ctype2 == 0b100) {		/*	L2		*/
+	if (clidr.Ctype2 == 0b100) {		**	L2		**
 		Cache_Level(Core, 2, 2);
 	}
-	if (clidr.Ctype3 == 0b100) {		/*	L3		*/
+	if (clidr.Ctype3 == 0b100) {		**	L3		**
 		Cache_Level(Core, 3, 3);
 	}
+*/
 }
 
 static void Map_Generic_Topology(void *arg)
 {
     if (arg != NULL) {
 	CORE_RO *Core = (CORE_RO *) arg;
-
-	volatile MIDR midr;
-	volatile MPIDR mpid;
-/*	__asm__ volatile
-	(
-		"mrs	%[midr] ,	midr_el1"	"\n\t"
-		"mrs	%[mpid] ,	mpidr_el1"	"\n\t"
-		"isb"
-		: [midr]	"=r" (midr),
-		  [mpid]	"=r" (mpid)
-		:
-		: "memory"
-	);*/
+/*
 	Core->T.PN = midr.PartNum;
 	if (mpid.MT) {
 		Core->T.MPID = mpid.value & 0xfffff;
@@ -2127,6 +781,7 @@ static void Map_Generic_Topology(void *arg)
 		Core->T.Cluster.CMP = mpid.Aff1;
 		Core->T.CoreID = mpid.Aff0;
 	}
+*/
 	Cache_Topology(Core);
     }
 }
@@ -2153,7 +808,7 @@ static unsigned int Proc_Topology(void)
     for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) {
 	PUBLIC(RO(Core, AT(cpu)))->T.PN 	= 0;
 	PUBLIC(RO(Core, AT(cpu)))->T.BSP	= 0;
-	PUBLIC(RO(Core, AT(cpu)))->T.MPID	= -1;
+	PUBLIC(RO(Core, AT(cpu)))->T.MPID	= /*TODO(Hardware ID)-1*/ 1;
 	PUBLIC(RO(Core, AT(cpu)))->T.CoreID	= -1;
 	PUBLIC(RO(Core, AT(cpu)))->T.ThreadID	= -1;
 	PUBLIC(RO(Core, AT(cpu)))->T.PackageID	= -1;
@@ -2338,17 +993,19 @@ static void Query_DeviceTree(unsigned int cpu)
     if (max_freq > 0) {
 	FREQ2COF(max_freq, COF);
     } else {
-	volatile CNTFRQ cntfrq;
+/*TODO	volatile unsigned long long cntfrq;
 
 	__asm__ __volatile__(
-		"csrr	%[cntfrq],	mcycle"	"\n\t"
+		"csrr	%[cntfrq],	mcycle" "\n\t"
 		"fence iorw, iorw"
 		: [cntfrq]	"=r" (cntfrq)
 		:
 		: "memory"
 	);
-	cntfrq.ClockFreq_Hz = cntfrq.ClockFreq_Hz / 10U;
-	FREQ2COF(cntfrq.ClockFreq_Hz, COF);
+	cntfrq = cntfrq / 10U;
+	FREQ2COF(cntfrq, COF);
+*/
+	FREQ2COF((10LLU * UNIT_KHz(PRECISION)), COF);
     }
 	Core->Boost[BOOST(MAX)].Q = COF.Q;
 	Core->Boost[BOOST(MAX)].R = COF.R;
@@ -2754,192 +1411,27 @@ static void Query_GenericMachine(unsigned int cpu)
 	For_All_ACPI_CPPC(Read_ACPI_CPPC_Registers, NULL);
 }
 
-static void Query_DynamIQ(unsigned int cpu)
-{
-	Query_GenericMachine(cpu);
-
-    if (PUBLIC(RO(Proc))->HypervisorID == BARE_METAL) {
-	/* Query the Cluster Configuration on Bare Metal only		**
-	PUBLIC(RO(Proc))->Uncore.ClusterCfg.value = SysRegRead(CLUSTERCFR_EL1);
-	PUBLIC(RO(Proc))->Uncore.ClusterRev.value = SysRegRead(CLUSTERIDR_EL1);*/
-    }
-}
-
 static void SystemRegisters(CORE_RO *Core)
 {
-	volatile AA64ISAR2 isar2;
-	volatile AA64MMFR1 mmfr1;
-	volatile AA64PFR0 pfr0;
-/*
-	isar2.value = SysRegRead(ID_AA64ISAR2_EL1);
-
-	__asm__ __volatile__(
-		"mrs	%[sctlr],	sctlr_el1"	"\n\t"
-		"mrs	%[mmfr1],	id_aa64mmfr1_el1""\n\t"
-		"mrs	%[pfr0] ,	id_aa64pfr0_el1""\n\t"
-		"mrs	%[fpcr] ,	fpcr"		"\n\t"
-		"mrs	%[fpsr] ,	fpsr"		"\n\t"
-		"cmp	xzr	,	xzr, lsl #0"	"\n\t"
-		"mrs	x14	,	nzcv"		"\n\t"
-		"mrs	x13	,	daif"		"\n\t"
-		"mrs	x12	,	currentel"	"\n\t"
-		"mrs	x11	,	spsel"		"\n\t"
-		"isb"					"\n\t"
-		"mov	%[flags],	xzr"		"\n\t"
-		"orr	%[flags],	x14, x13"	"\n\t"
-		"orr	%[flags],	%[flags], x12"	"\n\t"
-		"orr	%[flags],	%[flags], x11"
-		: [sctlr]	"=r" (Core->SystemRegister.SCTLR),
-		  [mmfr1]	"=r" (mmfr1),
-		  [pfr0]	"=r" (pfr0),
-		  [fpcr]	"=r" (Core->SystemRegister.FPCR),
-		  [fpsr]	"=r" (Core->SystemRegister.FPSR),
-		  [flags]	"=r" (Core->SystemRegister.FLAGS)
-		:
-		: "cc", "memory", "%x11", "%x12", "%x13", "%x14"
-	);*/
-	if (mmfr1.VH) {
-		BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->VM, Core->Bind);
-	} else {
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->VM, Core->Bind);
-	}
-	Core->Query.SCTLRX = 0;
-    if (Experimental) {
-/*	volatile AA64MMFR3 mmfr3 = {.value = SysRegRead(ID_AA64MMFR3_EL1)};
-	if ((Core->Query.SCTLRX = mmfr3.SCTLRX) == 0b0001) {
-		Core->SystemRegister.SCTLR2 = SysRegRead(SCTLR2_EL1);
-	}*/
-    }
-	if (PUBLIC(RO(Proc))->Features.DIT) {
-/*		Core->SystemRegister.FLAGS |= (
-			SysRegRead(MRS_DIT) & (1LLU << FLAG_DIT)
-		);*/
-	}
-	if (isar2.CLRBHB == 0b0001) {
-		BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CLRBHB, Core->Bind);
-	} else {
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CLRBHB, Core->Bind);
-	}
-	switch (pfr0.EL3) {
-	case 0b0010:
-		BITSET(LOCKLESS, Core->SystemRegister.EL, EL3_32);
-		fallthrough;
-	case 0b0001:
-		BITSET(LOCKLESS, Core->SystemRegister.EL, EL3_64);
-		break;
-	}
-	switch (pfr0.EL2) {
-	case 0b0010:
-		BITSET(LOCKLESS, Core->SystemRegister.EL, EL2_32);
-		fallthrough;
-	case 0b0001:
-		BITSET(LOCKLESS, Core->SystemRegister.EL, EL2_64);
-		break;
-	}
-	switch (pfr0.SEL2) {
-	case 0b0001:
-		BITSET(LOCKLESS, Core->SystemRegister.EL, EL2_SEC);
-		break;
-	}
-	switch (pfr0.EL1) {
-	case 0b0010:
-		BITSET(LOCKLESS, Core->SystemRegister.EL, EL1_32);
-		fallthrough;
-	case 0b0001:
-		BITSET(LOCKLESS, Core->SystemRegister.EL, EL1_64);
-		break;
-	}
-	switch (pfr0.EL0) {
-	case 0b0010:
-		BITSET(LOCKLESS, Core->SystemRegister.EL, EL0_32);
-		fallthrough;
-	case 0b0001:
-		BITSET(LOCKLESS, Core->SystemRegister.EL, EL0_64);
-		break;
-	}
-	switch (pfr0.CSV2) {
-	case 0b0001:
-		BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
-		break;
-	case 0b0010:
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
-		BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
-		break;
-	case 0b0011:
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
-		BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
-		break;
-	default:
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
-	}
-	if (pfr0.CSV3) {
-		BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV3, Core->Bind);
-	} else {
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV3, Core->Bind);
-	}
-	if (PUBLIC(RO(Proc))->Features.SSBS == 0b0010)
-	{
-/*		SSBS2 mrs_ssbs = {.value = SysRegRead(MRS_SSBS2)};
-
-	    if (mrs_ssbs.SSBS) {
-		BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->SSBS, Core->Bind);
-	    } else {
-		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->SSBS, Core->Bind);
-	    }*/
+		Core->SystemRegister.FLAGS |= (
+			(1LLU << FLAG_DIT)
+		);
 		Core->SystemRegister.FLAGS |= (1LLU << FLAG_SSBS);
-	}
-	if (PUBLIC(RO(Proc))->Features.PAN) {
-/*		Core->SystemRegister.FLAGS |= (
-			SysRegRead(MRS_PAN) & (1LLU << FLAG_PAN)
-		);*/
-	}
-	if (PUBLIC(RO(Proc))->Features.UAO) {
-/*		Core->SystemRegister.FLAGS |= (
-			SysRegRead(MRS_UAO) & (1LLU << FLAG_UAO)
-		);*/
-	}
-	if (PUBLIC(RO(Proc))->Features.MTE) {
-/*		Core->SystemRegister.FLAGS |= (
-			SysRegRead(MRS_TCO) & (1LLU << FLAG_TCO)
-		);*/
-	}
-	if (PUBLIC(RO(Proc))->Features.NMI) {
-/*		Core->SystemRegister.FLAGS |= (
-			SysRegRead(MRS_ALLINT) & (1LLU << FLAG_NMI)
-		);*/
-	}
-	if (PUBLIC(RO(Proc))->Features.EBEP) {
-/*		Core->SystemRegister.FLAGS |= (
-			SysRegRead(MRS_PM) & (1LLU << FLAG_PM)
-		);*/
-	}
-	if (PUBLIC(RO(Proc))->Features.SME) {
-/*		Core->SystemRegister.SVCR = SysRegRead(MRS_SVCR);*/
-	}
-	if (BITEXTRZ(Core->SystemRegister.FLAGS, FLAG_EL, 2) >= 2) {
-/*		__asm__ __volatile__(
-			"mrs	%[hcr]	,	hcr_el2"
-			: [hcr] 	"=r" (Core->SystemRegister.HCR)
-			:
-			: "cc", "memory"
-		);*/
-	}
-/*	__asm__ __volatile__(
-		"mrs	%[cpacr],	cpacr_el1"
-		: [cpacr] 	"=r" (Core->SystemRegister.CPACR)
-		:
-		: "cc", "memory"
-	);*/
-	if (PUBLIC(RO(Proc))->Features.FPMR) {
-/*		volatile unsigned long long fpmr = SysRegRead(MRS_FPMR);
-		UNUSED(fpmr);	TODO*/
-	}
+		Core->SystemRegister.FLAGS |= (
+			(1LLU << FLAG_PAN)
+		);
+		Core->SystemRegister.FLAGS |= (
+			(1LLU << FLAG_UAO)
+		);
+		Core->SystemRegister.FLAGS |= (
+			(1LLU << FLAG_TCO)
+		);
+		Core->SystemRegister.FLAGS |= (
+			(1LLU << FLAG_NMI)
+		);
+		Core->SystemRegister.FLAGS |= (
+			(1LLU << FLAG_PM)
+		);
 	BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask, Core->Bind);
 }
 
@@ -2957,11 +1449,6 @@ static void PerCore_Reset(CORE_RO *Core)
 	BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
 
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->HWP	, Core->Bind);
-	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1	, Core->Bind);
-	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2	, Core->Bind);
-	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3	, Core->Bind);
-	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV3	, Core->Bind);
-	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->SSBS	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->VM	, Core->Bind);
 
 	BITWISECLR(LOCKLESS, Core->ThermalPoint.Mask);
@@ -2971,11 +1458,6 @@ static void PerCore_Reset(CORE_RO *Core)
 
 static void PerCore_GenericMachine(void *arg)
 {
-	volatile CPUPWRCTLR cpuPwrCtl;
-	volatile PMUSERENR pmuser;
-	volatile PMCNTENSET enset;
-	volatile PMCNTENCLR enclr;
-	volatile REVIDR revid;
 	CORE_RO *Core = (CORE_RO *) arg;
 
 	Query_DeviceTree(Core->Bind);
@@ -2985,38 +1467,12 @@ static void PerCore_GenericMachine(void *arg)
 	  Core->Boost[BOOST(MAX)].Q < PUBLIC(RO(Proc))->Features.Factory.Ratio ?
 		Hybrid_Secondary : Hybrid_Primary;
     }
-    if (Experimental && (PUBLIC(RO(Proc))->HypervisorID == BARE_METAL)) {
-/*	cpuPwrCtl.value = SysRegRead(CPUPWRCTLR_EL1);*/
-	Core->Query.CStateBaseAddr = cpuPwrCtl.WFI_RET_CTRL;
-    }
-/*	__asm__ __volatile__(
-		"mrs	%[pmuser],	pmuserenr_el0"	"\n\t"
-		"mrs	%[enset],	pmcntenset_el0" "\n\t"
-		"mrs	%[enclr],	pmcntenclr_el0" "\n\t"
-		"isb"
-		: [pmuser]	"=r" (pmuser),
-		  [enset]	"=r" (enset),
-		  [enclr]	"=r" (enclr)
-		:
-		: "memory"
-	);*/
-
     if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) {
-	PUBLIC(RO(Proc))->Features.PerfMon.CoreCycles	= pmuser.CR
-							| enset.C
-							| enclr.C;
-	PUBLIC(RO(Proc))->Features.PerfMon.InstrRetired = pmuser.IR
-							| enset.F0
-							| enclr.F0;
+	PUBLIC(RO(Proc))->Features.PerfMon.CoreCycles	= \
+	PUBLIC(RO(Proc))->Features.PerfMon.InstrRetired = 0;
     }
-/*	__asm__ __volatile__(
-		"mrs	%[revid],	revidr_el1"	"\n\t"
-		"isb"
-		: [revid]	"=r" (revid)
-		:
-		: "memory"
-	);*/
-	Core->Query.Revision = revid.Revision;
+
+	Core->Query.Revision = 0;
 
 	SystemRegisters(Core);
 
@@ -3248,132 +1704,22 @@ static void Controller_Exit(void)
 
 static void Generic_Core_Counters_Set(union SAVE_AREA_CORE *Save, CORE_RO *Core)
 {
-/*	__asm__ __volatile__
-	(
-		"# Assign an event number per counter"	"\n\t"
-		"mrs	x12	,	pmselr_el0"	"\n\t"
-		"str	x12	,	%[PMSELR]"	"\n\t"
-		"orr	x12	,	x12, #3"	"\n\t"
-		"msr	pmselr_el0,	x12"		"\n\t"
-
-		"# Choosen [EVENT#] to collect from"	"\n\t"
-		"mrs	x12	,	pmxevtyper_el0" "\n\t"
-		"str	x12	,	%[PMTYPE3]"	"\n\t"
-		"orr	x12	,	x12, %[EVENT3]" "\n\t"
-		"msr	pmxevtyper_el0, x12"		"\n\t"
-
-		"ldr	x12	,	%[PMSELR]"	"\n\t"
-		"orr	x12	,	x12, #2"	"\n\t"
-		"msr	pmselr_el0,	x12"		"\n\t"
-		"mrs	x12	,	pmxevtyper_el0" "\n\t"
-		"str	x12	,	%[PMTYPE2]"	"\n\t"
-		"orr	x12	,	x12, %[EVENT2]" "\n\t"
-		"msr	pmxevtyper_el0, x12"		"\n\t"
-
-		"ldr	x12	,	%[PMSELR]"	"\n\t"
-		"orr	x12	,	x12, #0b11111"	"\n\t"
-		"msr	pmselr_el0,	x12"		"\n\t"
-		"mrs	x12	,	pmxevtyper_el0" "\n\t"
-		"str	x12	,	%[PMTYPE1]"	"\n\t"
-		"orr	x12	,	x12, %[FILTR1]" "\n\t"
-		"msr	pmxevtyper_el0, x12"		"\n\t"
-
-		"# No filtered EL within Cycle counter" "\n\t"
-		"mrs	x12	,	pmccfiltr_el0"	"\n\t"
-		"str	x12	,	%[PMCCFILTR]"	"\n\t"
-		"msr	pmccfiltr_el0,	xzr"		"\n\t"
-
-		"# Enable counters at position [ENSET]" "\n\t"
-		"mrs	x12	,	pmcntenset_el0" "\n\t"
-		"str	x12	,	%[PMCNTEN]"	"\n\t"
-		"orr	x12	,	x12, %[ENSET]"	"\n\t"
-		"msr	pmcntenset_el0, x12"		"\n\t"
-
-		"# Enable User-space access to counters""\n\t"
-		"mrs	x12	,	pmuserenr_el0"	"\n\t"
-		"str	x12	,	%[PMUSER]"	"\n\t"
-		"orr	x12	,	x12, %[ENUSR]"	"\n\t"
-		"msr	pmuserenr_el0,	%12"		"\n\t"
-
-		"# Enable all PMU counters"		"\n\t"
-		"mrs	x12	,	pmcr_el0"	"\n\t"
-		"str	x12	,	%[PMCR]"	"\n\t"
-		"mov	x12	,	%[CTRL]"	"\n\t"
-		"msr	pmcr_el0,	x12"		"\n\t"
-		"isb"
-		: [PMCR]	"+m" (Save->PMCR),
-		  [PMSELR]	"+m" (Save->PMSELR),
-		  [PMTYPE3]	"+m" (Save->PMTYPE[2]),
-		  [PMTYPE2]	"+m" (Save->PMTYPE[1]),
-		  [PMTYPE1]	"+m" (Save->PMTYPE[0]),
-		  [PMCCFILTR]	"+m" (Save->PMCCFILTR),
-		  [PMCNTEN]	"+m" (Save->PMCNTEN),
-		  [PMUSER]	"+m" (Save->PMUSER)
-		: [EVENT3]	"r" (0x0008),
-		  [EVENT2]	"r" (0x0011),
-		  [FILTR1]	"r" (0x0),
-		  [ENSET]	"r" (0b10000000000000000000000000001100),
-		  [ENUSR]	"r" (0b0000101),
-		  [CTRL]	"i" (0b0000000010000111)
-		: "memory", "%x12"
-	);*/
+/*TODO*/
 }
 
 static void Generic_Core_Counters_Clear(union SAVE_AREA_CORE *Save,
 					CORE_RO *Core)
 {
-/*	__asm__ __volatile__(
-		"# Restore PMU configuration registers" "\n\t"
-		"msr	pmcr_el0,	%[PMCR]"	"\n\t"
-
-		"msr	pmuserenr_el0,	%[PMUSER]"	"\n\t"
-
-		"msr	pmcntenset_el0, %[PMCNTEN]"	"\n\t"
-
-		"msr	pmccfiltr_el0,	%[PMCCFILTR]"	"\n\t"
-
-		"ldr	x12	,	%[PMSELR]"	"\n\t"
-		"orr	x12	,	x12, #0b11111"	"\n\t"
-		"msr	pmselr_el0,	x12"		"\n\t"
-		"ldr	x12	,	%[PMTYPE1]"	"\n\t"
-		"msr	pmxevtyper_el0, x12"		"\n\t"
-
-		"ldr	x12	,	%[PMSELR]"	"\n\t"
-		"orr	x12	,	x12, #2"	"\n\t"
-		"msr	pmselr_el0,	x12"		"\n\t"
-		"ldr	x12	,	%[PMTYPE2]"	"\n\t"
-		"msr	pmxevtyper_el0, x12"		"\n\t"
-
-		"ldr	x12	,	%[PMSELR]"	"\n\t"
-		"orr	x12	,	x12, #3"	"\n\t"
-		"msr	pmselr_el0,	x12"		"\n\t"
-		"ldr	x12	,	%[PMTYPE3]"	"\n\t"
-		"msr	pmxevtyper_el0, x12"		"\n\t"
-
-		"ldr	x12	,	%[PMSELR]"	"\n\t"
-		"msr	pmselr_el0,	x12"		"\n\t"
-
-		"isb"
-		:
-		: [PMCR]	"r" (Save->PMCR),
-		  [PMSELR]	"m" (Save->PMSELR),
-		  [PMTYPE3]	"m" (Save->PMTYPE[2]),
-		  [PMTYPE2]	"m" (Save->PMTYPE[1]),
-		  [PMTYPE1]	"m" (Save->PMTYPE[0]),
-		  [PMCCFILTR]	"r" (Save->PMCCFILTR),
-		  [PMCNTEN]	"r" (Save->PMCNTEN),
-		  [PMUSER]	"r" (Save->PMUSER)
-		: "memory", "%x12"
-	);*/
+/*TODO*/
 }
 
 #define Counters_Generic(Core, T)					\
 ({									\
-	RDTSC_COUNTERx3(Core->Counter[T].TSC,				\
-		/*TODO	pmevcntr2_el0*/mcycle,	Core->Counter[T].C0.UCC,\
-		/*TODO	pmccntr_el0*/mcycle,	Core->Counter[T].C0.URC,\
-		/*TODO	pmevcntr3_el0*/mcycle,	Core->Counter[T].INST );\
-									\
+/*	RDTSC_COUNTERx3(Core->Counter[T].TSC,				\
+		**TODO	pmevcntr2_el0**mcycle,	Core->Counter[T].C0.UCC,\
+		**TODO	pmccntr_el0**mcycle,	Core->Counter[T].C0.URC,\
+		**TODO	pmevcntr3_el0**mcycle,	Core->Counter[T].INST );\
+*/									\
 	Core->Counter[T].INST &= INST_COUNTER_OVERFLOW;			\
 	/* Normalize frequency: */					\
 	Core->Counter[T].C1 = ( 					\
@@ -3470,15 +1816,15 @@ static void Generic_Core_Counters_Clear(union SAVE_AREA_CORE *Save,
 
 #define PKG_Counters_Generic(Core, T)					\
 ({									\
-	volatile CNTPCT cntpct; 					\
+/*TODO	volatile unsigned long long cntpct; 				\
 	__asm__ volatile						\
 	(								\
-		"csrr	%[cntpct],	mcycle"/*"cntpct_el0"TODO*/	\
+		"csrr	%[cntpct],	mcycle"				\
 		: [cntpct]	"=r" (cntpct) 				\
 		:							\
 		: "cc", "memory"					\
 	);								\
-	PUBLIC(RO(Proc))->Counter[T].PCLK = cntpct.PhysicalCount;	\
+	PUBLIC(RO(Proc))->Counter[T].PCLK = cntpct;*/			\
 })
 
 #define Pkg_OVH(Pkg, Core)						\
diff --git a/riscv64/corefreqk.h b/riscv64/corefreqk.h
index b24f4b0..1ca20b9 100644
--- a/riscv64/corefreqk.h
+++ b/riscv64/corefreqk.h
@@ -126,7 +126,7 @@ __asm__ volatile							\
 
 /* Manufacturers Identifier Strings.					*/
 #define VENDOR_RESERVED "Reserved"
-#define VENDOR_ARM	"Arm"
+#define VENDOR_RISC	"RISC"
 #define VENDOR_BROADCOM "Broadcom"
 #define VENDOR_CAVIUM	"Cavium"
 #define VENDOR_DEC	"DEC"		/* Digital Equipment Corporation */
@@ -225,12 +225,6 @@ typedef struct
 		union SAVE_AREA_CORE {
 		    struct
 		    {
-			PMCR		PMCR;
-			PMSELR		PMSELR;
-			PMXEVTYPER	PMTYPE[3];
-			PMCCFILTR	PMCCFILTR;
-			PMCNTENSET	PMCNTEN;
-			PMUSERENR	PMUSER;
 		    };
 		} SaveArea;
 #ifdef CONFIG_CPU_FREQ
@@ -369,42 +363,9 @@ static void PerCore_GenericMachine(void *arg) ;
 static void Start_GenericMachine(void *arg) ;
 static void Stop_GenericMachine(void *arg) ;
 static void InitTimer_GenericMachine(unsigned int cpu) ;
-static void Query_DynamIQ(unsigned int cpu) ;
+
 /*	[Void]								*/
 #define _Void_Signature {.ExtFamily=0x00, .Family=0x0, .ExtModel=0x0, .Model=0x0}
-#define _Cortex_A34	{.ExtFamily=0xd0, .Family=0x2, .ExtModel=0x0, .Model=0x8}
-#define _Cortex_A35	{.ExtFamily=0xd0, .Family=0x4, .ExtModel=0x0, .Model=0xa}
-#define _Cortex_A510	{.ExtFamily=0xd4, .Family=0x6, .ExtModel=0x0, .Model=0x0}
-#define _Cortex_A520	{.ExtFamily=0xd8, .Family=0x0, .ExtModel=0x0, .Model=0x0}
-#define _Cortex_A53	{.ExtFamily=0xd0, .Family=0x3, .ExtModel=0x0, .Model=0x3}
-#define _Cortex_A55	{.ExtFamily=0xd0, .Family=0x5, .ExtModel=0x4, .Model=0x5}
-#define _Cortex_A57	{.ExtFamily=0xd0, .Family=0x7, .ExtModel=0x0, .Model=0x1}
-#define _Cortex_A65	{.ExtFamily=0xd0, .Family=0x6, .ExtModel=0x4, .Model=0x6}
-#define _Cortex_A65AE	{.ExtFamily=0xd4, .Family=0x3, .ExtModel=0x4, .Model=0x7}
-#define _Cortex_A710	{.ExtFamily=0xd4, .Family=0x7, .ExtModel=0x0, .Model=0x0}
-#define _Cortex_A715	{.ExtFamily=0xd4, .Family=0xd, .ExtModel=0x0, .Model=0x0}
-#define _Cortex_A72	{.ExtFamily=0xd0, .Family=0x8, .ExtModel=0x0, .Model=0x2}
-#define _Cortex_A720	{.ExtFamily=0xd8, .Family=0x1, .ExtModel=0x0, .Model=0x0}
-#define _Cortex_A73	{.ExtFamily=0xd0, .Family=0x9, .ExtModel=0x0, .Model=0x4}
-#define _Cortex_A75	{.ExtFamily=0xd0, .Family=0xa, .ExtModel=0x4, .Model=0xa}
-#define _Cortex_A76	{.ExtFamily=0xd0, .Family=0xb, .ExtModel=0x0, .Model=0xb}
-#define _Cortex_A76AE	{.ExtFamily=0xd0, .Family=0xe, .ExtModel=0x1, .Model=0x1}
-#define _Cortex_A77	{.ExtFamily=0xd0, .Family=0xd, .ExtModel=0x1, .Model=0x0}
-#define _Cortex_A78	{.ExtFamily=0xd4, .Family=0x1, .ExtModel=0x2, .Model=0x1}
-#define _Cortex_A78AE	{.ExtFamily=0xd4, .Family=0x2, .ExtModel=0x2, .Model=0x2}
-#define _Cortex_A78C	{.ExtFamily=0xd4, .Family=0xb, .ExtModel=0x2, .Model=0x4}
-#define _Cortex_R82	{.ExtFamily=0xd1, .Family=0x5, .ExtModel=0x0, .Model=0x0}
-#define _Cortex_X1	{.ExtFamily=0xd4, .Family=0x4, .ExtModel=0x2, .Model=0x3}
-#define _Cortex_X1C	{.ExtFamily=0xd4, .Family=0xc, .ExtModel=0x2, .Model=0x5}
-#define _Cortex_X2	{.ExtFamily=0xd4, .Family=0x8, .ExtModel=0x0, .Model=0x0}
-#define _Cortex_X3	{.ExtFamily=0xd4, .Family=0xe, .ExtModel=0x0, .Model=0x0}
-#define _Cortex_X4	{.ExtFamily=0xd8, .Family=0x2, .ExtModel=0x0, .Model=0x0}
-#define _DynamIQ_DSU	{.ExtFamily=0x00, .Family=0x0, .ExtModel=0x4, .Model=0x1}
-#define _Neoverse_E1	{.ExtFamily=0xd4, .Family=0xa, .ExtModel=0x4, .Model=0x6}
-#define _Neoverse_N1	{.ExtFamily=0xd0, .Family=0xc, .ExtModel=0x0, .Model=0xc}
-#define _Neoverse_N2	{.ExtFamily=0xd4, .Family=0x9, .ExtModel=0x0, .Model=0x0}
-#define _Neoverse_V1	{.ExtFamily=0xd4, .Family=0x0, .ExtModel=0x2, .Model=0x1}
-#define _Neoverse_V2	{.ExtFamily=0xd4, .Family=0xf, .ExtModel=0x0, .Model=0x0}
 
 typedef kernel_ulong_t (*PCI_CALLBACK)(struct pci_dev *);
 
@@ -413,54 +374,10 @@ static struct pci_device_id PCI_Void_ids[] = {
 };
 
 static char *CodeName[CODENAMES] = {
-	[    ARM64]	= "AArch64",
-	[  ARMv8_R]	= "ARMv8-R",
-	[  ARMv8_A]	= "ARMv8-A",
-	[ARMv8_2_A]	= "ARMv8.2-A",
-	[ARMv8_3_A]	= "ARMv8.3-A",
-	[ARMv8_4_A]	= "ARMv8.4-A",
-	[  ARMv8_5]	= "ARMv8.5",
-	[  ARMv8_6]	= "ARMv8.6",
-	[  ARMv8_7]	= "ARMv8.7",
-	[  ARMv9_A]	= "ARMv9-A",
-	[  ARMv9_4]	= "ARMv9.4",
-	[  ARMv9_5]	= "ARMv9.5"
+	[    RV64]	= "RV64"
 };
 
-#define Arch_Misc_Processor {.Brand = ZLIST(NULL), .CN = ARM64}
-#define Arch_Cortex_A34 {.Brand = ZLIST("Cortex-A34"), .CN = ARMv8_A}
-#define Arch_Cortex_A35 {.Brand = ZLIST("Cortex-A35"), .CN = ARMv8_A}
-#define Arch_Cortex_A510 {.Brand = ZLIST("Cortex-A510"), .CN = ARMv9_A}
-#define Arch_Cortex_A520 {.Brand = ZLIST("Cortex-A520"), .CN = ARMv9_A}
-#define Arch_Cortex_A53 {.Brand = ZLIST("Cortex-A53"), .CN = ARMv8_A}
-#define Arch_Cortex_A55 {.Brand = ZLIST("Cortex-A55"), .CN = ARMv8_2_A}
-#define Arch_Cortex_A57 {.Brand = ZLIST("Cortex-A57"), .CN = ARMv8_A}
-#define Arch_Cortex_A65 {.Brand = ZLIST("Cortex-A65"), .CN = ARMv8_2_A}
-#define Arch_Cortex_A65AE {.Brand = ZLIST("Cortex-A65AE"), .CN = ARMv8_2_A}
-#define Arch_Cortex_A710 {.Brand = ZLIST("Cortex-A710"), .CN = ARMv9_A}
-#define Arch_Cortex_A715 {.Brand = ZLIST("Cortex-A715"), .CN = ARMv9_A}
-#define Arch_Cortex_A72 {.Brand = ZLIST("Cortex-A72"), .CN = ARMv8_A}
-#define Arch_Cortex_A720 {.Brand = ZLIST("Cortex-A720"), .CN = ARMv9_A}
-#define Arch_Cortex_A73 {.Brand = ZLIST("Cortex-A73"), .CN = ARMv8_A}
-#define Arch_Cortex_A75 {.Brand = ZLIST("Cortex-A75"), .CN = ARMv8_2_A}
-#define Arch_Cortex_A76 {.Brand = ZLIST("Cortex-A76"), .CN = ARMv8_2_A}
-#define Arch_Cortex_A76AE {.Brand = ZLIST("Cortex-A76AE"), .CN = ARMv8_2_A}
-#define Arch_Cortex_A77 {.Brand = ZLIST("Cortex-A77"), .CN = ARMv8_2_A}
-#define Arch_Cortex_A78 {.Brand = ZLIST("Cortex-A78"), .CN = ARMv8_2_A}
-#define Arch_Cortex_A78AE {.Brand = ZLIST("Cortex-A78AE"), .CN = ARMv8_2_A}
-#define Arch_Cortex_A78C {.Brand = ZLIST("Cortex-A78C"), .CN = ARMv8_2_A}
-#define Arch_Cortex_R82 {.Brand = ZLIST("Cortex-R82"), .CN = ARMv8_R}
-#define Arch_Cortex_X1 {.Brand = ZLIST("Cortex-X1"), .CN = ARMv8_2_A}
-#define Arch_Cortex_X1C {.Brand = ZLIST("Cortex-X1C"), .CN = ARMv8_2_A}
-#define Arch_Cortex_X2 {.Brand = ZLIST("Cortex-X2"), .CN = ARMv9_A}
-#define Arch_Cortex_X3 {.Brand = ZLIST("Cortex-X3"), .CN = ARMv9_A}
-#define Arch_Cortex_X4 {.Brand = ZLIST("Cortex-X4"), .CN = ARMv9_A}
-#define Arch_DynamIQ_DSU {.Brand = ZLIST("DynamIQ DSU"), .CN = ARMv8_2_A}
-#define Arch_Neoverse_E1 {.Brand = ZLIST("Neoverse E1"), .CN = ARMv8_2_A}
-#define Arch_Neoverse_N1 {.Brand = ZLIST("Neoverse N1"), .CN = ARMv8_2_A}
-#define Arch_Neoverse_N2 {.Brand = ZLIST("Neoverse N2"), .CN = ARMv9_A}
-#define Arch_Neoverse_V1 {.Brand = ZLIST("Neoverse V1"), .CN = ARMv8_4_A}
-#define Arch_Neoverse_V2 {.Brand = ZLIST("Neoverse V2"), .CN = ARMv9_A}
+#define Arch_Misc_Processor {.Brand = ZLIST(NULL), .CN = RV64}
 
 static PROCESSOR_SPECIFIC Misc_Specific_Processor[] = {
 	{0}
@@ -527,928 +444,4 @@ static ARCH Arch[ARCHITECTURES] = {
 	.SystemDriver = VOID_Driver,
 	.Architecture = Arch_Misc_Processor
 	},
-[Cortex_A34] = {
-	.Signature = _Cortex_A34,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A34
-	},
-[Cortex_A35] = {
-	.Signature = _Cortex_A35,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A35
-	},
-[Cortex_A510] = {
-	.Signature = _Cortex_A510,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A510
-	},
-[Cortex_A520] = {
-	.Signature = _Cortex_A520,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A520
-	},
-[Cortex_A53] = {
-	.Signature = _Cortex_A53,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A53
-	},
-[Cortex_A55] = {
-	.Signature = _Cortex_A55,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A55
-	},
-[Cortex_A57] = {
-	.Signature = _Cortex_A57,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A57
-	},
-[Cortex_A65] = {
-	.Signature = _Cortex_A65,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A65
-	},
-[Cortex_A65AE] = {
-	.Signature = _Cortex_A65AE,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A65AE
-	},
-[Cortex_A710] = {
-	.Signature = _Cortex_A710,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A710
-	},
-[Cortex_A715] = {
-	.Signature = _Cortex_A715,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A715
-	},
-[Cortex_A72] = {
-	.Signature = _Cortex_A72,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A72
-	},
-[Cortex_A720] = {
-	.Signature = _Cortex_A720,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A720
-	},
-[Cortex_A73] = {
-	.Signature = _Cortex_A73,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A73
-	},
-[Cortex_A75] = {
-	.Signature = _Cortex_A75,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A75
-	},
-[Cortex_A76] = {
-	.Signature = _Cortex_A76,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A76
-	},
-[Cortex_A76AE] = {
-	.Signature = _Cortex_A76AE,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A76AE
-	},
-[Cortex_A77] = {
-	.Signature = _Cortex_A77,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A77
-	},
-[Cortex_A78] = {
-	.Signature = _Cortex_A78,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A78
-	},
-[Cortex_A78AE] = {
-	.Signature = _Cortex_A78AE,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A78AE
-	},
-[Cortex_A78C] = {
-	.Signature = _Cortex_A78C,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_A78C
-	},
-[Cortex_R82] = {
-	.Signature = _Cortex_R82,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_R82
-	},
-[Cortex_X1] = {
-	.Signature = _Cortex_X1,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_X1
-	},
-[Cortex_X1C] = {
-	.Signature = _Cortex_X1C,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_X1C
-	},
-[Cortex_X2] = {
-	.Signature = _Cortex_X2,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_X2
-	},
-[Cortex_X3] = {
-	.Signature = _Cortex_X3,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_X3
-	},
-[Cortex_X4] = {
-	.Signature = _Cortex_X4,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Cortex_X4
-	},
-[DynamIQ_DSU] = {
-	.Signature = _DynamIQ_DSU,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_DynamIQ_DSU
-	},
-[Neoverse_E1] = {
-	.Signature = _Neoverse_E1,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Neoverse_E1
-	},
-[Neoverse_N1] = {
-	.Signature = _Neoverse_N1,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Neoverse_N1
-	},
-[Neoverse_N2] = {
-	.Signature = _Neoverse_N2,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Neoverse_N2
-	},
-[Neoverse_V1] = {
-	.Signature = _Neoverse_V1,
-	.Query = Query_DynamIQ,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Neoverse_V1
-	},
-[Neoverse_V2] = {
-	.Signature = _Neoverse_V2,
-	.Query = Query_GenericMachine,
-	.Update = PerCore_GenericMachine,
-	.Start = Start_GenericMachine,
-	.Stop = Stop_GenericMachine,
-	.Exit = NULL,
-	.Timer = InitTimer_GenericMachine,
-	.BaseClock = BaseClock_GenericMachine,
-	.ClockMod = NULL,
-	.TurboClock = NULL,
-	.thermalFormula = THERMAL_FORMULA_NONE,
-#ifdef CONFIG_PM_OPP
-	.voltageFormula = VOLTAGE_FORMULA_OPP,
-#else
-	.voltageFormula = VOLTAGE_FORMULA_NONE,
-#endif
-	.powerFormula   = POWER_FORMULA_NONE,
-	.PCI_ids = PCI_Void_ids,
-	.Uncore = {
-		.Start = NULL,
-		.Stop = NULL,
-		.ClockMod = NULL
-		},
-	.Specific = Misc_Specific_Processor,
-	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Neoverse_V2
-	}
 };
diff --git a/riscv64/coretypes.h b/riscv64/coretypes.h
index 6e731e1..4e4e67d 100644
--- a/riscv64/coretypes.h
+++ b/riscv64/coretypes.h
@@ -37,55 +37,11 @@ enum CRC_MANUFACTURER
 
 enum CODENAME
 {
-	ARM64,
-	ARMv8_R,
-	ARMv8_A,
-	ARMv8_2_A,
-	ARMv8_3_A,
-	ARMv8_4_A,
-	ARMv8_5,
-	ARMv8_6,
-	ARMv8_7,
-	ARMv9_A,
-	ARMv9_4,
-	ARMv9_5,
+	RV64,
 	CODENAMES
 };
 
 enum {	GenuineArch = 0,
-	Cortex_A34,
-	Cortex_A35,
-	Cortex_A510,
-	Cortex_A520,
-	Cortex_A53,
-	Cortex_A55,
-	Cortex_A57,
-	Cortex_A65,
-	Cortex_A65AE,
-	Cortex_A710,
-	Cortex_A715,
-	Cortex_A72,
-	Cortex_A720,
-	Cortex_A73,
-	Cortex_A75,
-	Cortex_A76,
-	Cortex_A76AE,
-	Cortex_A77,
-	Cortex_A78,
-	Cortex_A78AE,
-	Cortex_A78C,
-	Cortex_R82,
-	Cortex_X1,
-	Cortex_X1C,
-	Cortex_X2,
-	Cortex_X3,
-	Cortex_X4,
-	DynamIQ_DSU,
-	Neoverse_E1,
-	Neoverse_N1,
-	Neoverse_N2,
-	Neoverse_V1,
-	Neoverse_V2,
 	ARCHITECTURES
 };
 
diff --git a/riscv64/risc_reg.h b/riscv64/risc_reg.h
index 58d44f6..bdf99a1 100644
--- a/riscv64/risc_reg.h
+++ b/riscv64/risc_reg.h
@@ -3,860 +3,6 @@
  * Copyright (C) 2015-2025 CYRIL COURTIAT
  * Licenses: GPL2
  */
-/*
-#define CPUPWRCTLR_EL1		sys_reg(0b11, 0b000, 0b1111, 0b0010, 0b111)
-#define ID_AA64ISAR2_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0110, 0b010)
-#define ID_AA64ISAR3_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0110, 0b011)
-#define ID_AA64ISAR4_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0110, 0b100)
-#define ID_AA64MMFR2_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b010)
-#define ID_AA64MMFR3_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b011)
-#define ID_AA64SMFR0_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b101)
-#define ID_AA64ZFR0_EL1 	sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b100)
-#define ID_AA64PFR2_EL1 	sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b010)
-#define SCTLR2_EL1		sys_reg(0b11, 0b000, 0b0001, 0b0000, 0b011)
-#define MRS_SSBS2		sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b110)
-#define MRS_PAN 		sys_reg(0b11, 0b000, 0b0100, 0b0010, 0b011)
-#define MRS_UAO 		sys_reg(0b11, 0b000, 0b0100, 0b0010, 0b100)
-#define MRS_DIT 		sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b101)
-#define MRS_TCO 		sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b111)
-#define MRS_ALLINT		sys_reg(0b11, 0b000, 0b0100, 0b0011, 0b000)
-#define MRS_PM			sys_reg(0b11, 0b000, 0b0100, 0b0011, 0b001)
-#define MRS_SVCR		sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b010)
-#define MRS_FPMR		sys_reg(0b11, 0b011, 0b0100, 0b0100, 0b010)
-#define AMCGCR_EL0		sys_reg(0b11, 0b011, 0b1101, 0b0010, 0b010)
-#define CLUSTERCFR_EL1		sys_reg(0b11, 0b000, 0b1111, 0b0011, 0b000)
-#define CLUSTERIDR_EL1		sys_reg(0b11, 0b000, 0b1111, 0b0011, 0b001)
-*/
-typedef union
-{
-	unsigned long long	value;	/* CPU0:0x412fd050 ; CPU4:0x414fd0b0 */
-	struct
-	{
-		unsigned long long
-		Revision	:  4-0,
-		PartNum 	: 16-4,
-		Architecture	: 20-16, /* 0b1111=by CPUID scheme	*/
-		Variant 	: 24-20,
-		Implementer	: 32-24,
-		RES0		: 64-32;
-	};
-} MIDR;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		Aff0		:  8-0,  /*	Thread ID		*/
-		Aff1		: 16-8,  /*	Core ID: CPUID[12-8] L1 */
-		Aff2		: 24-16, /*	Cluster ID - Level2	*/
-		MT		: 25-24, /*	Multithreading		*/
-		UNK		: 30-25,
-		U		: 31-30, /*	0=Uniprocessor		*/
-		RES1		: 32-31,
-		Aff3		: 40-32, /*	Cluster ID - Level3	*/
-		RES0		: 64-40;
-	};
-} MPIDR;
-/*
-CPU:MPIDR
-  0:0x81000000
-  1:0x81000100
-  2:0x81000200
-  3:0x81000300
-  4:0x81000400
-  5:0x81000500
-  6:0x81000600
-  7:0x81000700
-*/
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		Revision	: 32-0,
-		RES0		: 64-32;
-	};
-} REVIDR;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		EnableAll	:  1-0,
-		ResetEvent	:  2-1,
-		ResetCycle	:  3-2,
-		ClockDiv	:  4-3,  /* 1:PMCCNTR counts once / 64 cycles */
-		ExportEvent	:  5-4,
-		DisableCycle	:  6-5,  /* 1:PMCCNTR is disabled	*/
-		EnableLongCycle :  7-6,
-		EnableLongEvent :  8-7,
-		RES0		:  9-8,
-		FZO		: 10-9,  /* 1:Freeze-on-overflow	*/
-		RES1		: 11-10,
-		NumEvtCtrs	: 16-11,
-		IDcode		: 24-16,
-		Implementer	: 32-24,
-		Freeze_On_SPE	: 33-32,
-		RES2		: 64-33;
-	};
-} PMCR;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		SEL		:  5-0,
-		RES0		: 64-5;
-	};
-} PMSELR;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		CFILTR_EVTYPER	: 64-0;
-	};
-} PMXEVTYPER;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		RES0		: 20-0,
-		RLH		: 21-20,
-		RLU		: 22-21,
-		RLK		: 23-22,
-		T		: 24-23,
-		SH		: 25-24,
-		RES1		: 26-25,
-		M		: 27-26,
-		NSH		: 28-27,
-		NSU		: 29-28,
-		NSK		: 30-29,
-		U		: 31-30,
-		P		: 32-31,
-		RES2		: 56-32,
-		VS		: 58-56,
-		RES3		: 64-58;
-	};
-} PMCCFILTR;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		EvtCount	: 16-0,
-		RES0		: 20-16,
-		RLH		: 21-20,
-		RLU		: 22-21,
-		RLK		: 23-22,
-		T		: 24-23,
-		SH		: 25-24,
-		MT		: 26-25,
-		M		: 27-26,
-		NSH		: 28-27,
-		NSU		: 29-28,
-		NSK		: 30-29,
-		U		: 31-30,
-		P		: 32-31,
-		TH		: 44-32,
-		RES1		: 54-44,
-		TLC		: 56-54,
-		VS		: 58-56,
-		SYNC		: 59-58,
-		RES2		: 60-59,
-		TE		: 61-60,
-		TC		: 64-61;
-	};
-} PMEVTYPER;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		Pm		: 31-0,
-		C		: 32-31,
-		F0		: 33-32,
-		RES0		: 64-33;
-	};
-} PMCNTENSET;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		Pm		: 31-0,
-		C		: 32-31,
-		F0		: 33-32,
-		RES0		: 64-33;
-	};
-} PMCNTENCLR;
-
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		EN		:  1-0,
-		SW		:  2-1,
-		CR		:  3-2,
-		ER		:  4-3,
-		UEN		:  5-4,
-		IR		:  6-5,
-		TID		:  7-6,
-		RES0		: 64-7;
-	};
-} PMUSERENR;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		ClockFreq_Hz	: 32-0,
-		RES0		: 64-32;
-	};
-} CNTFRQ;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		PhysicalCount	: 64-0;
-	};
-} CNTPCT;
-
-typedef union
-{
-	unsigned long long	value;	/* SMT=0x0000000000000000	*/
-	struct
-	{
-		unsigned long long
-		CORE_PWRDN_EN	:  1-0,
-		RES0		:  4-1,
-		WFI_RET_CTRL	:  7-4,
-		WFE_RET_CTRL	: 10-7,
-		RES1		: 32-10,
-		RES2		: 64-32;
-	};
-} CPUPWRCTLR;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		InD		:  1-0,
-		Level		:  4-1,
-		RES0		: 32-4,
-		RES1		: 64-32;
-	};
-} CSSELR;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		Ctype1		:  3-0,
-		Ctype2		:  6-3,
-		Ctype3		:  9-6,
-		RES0		: 21-9,
-		LoUIS		: 24-21,
-		LoC		: 27-24,
-		LoUU		: 30-27,
-		ICB		: 33-30,
-		RES1		: 64-33;
-	};
-} CLIDR;
-
-typedef union
-{	/*	CPU0:0x00000000003033ff ; CPU4:0x0000000000300000	*/
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		RES0		: 16-0,
-		ZEN		: 18-16,
-		RES1		: 20-18,
-		FPEN		: 22-20,
-		RES2		: 24-22,
-		SMEN		: 26-24,
-		RES3		: 28-26,
-		TTA		: 29-28,
-		E0POE		: 30-29,
-		RES4		: 64-30;
-	};
-} CPACR;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		CG0NC		:  8-0,
-		CG1NC		: 16-8,
-		RES0		: 64-16;
-	};
-} AMCGCR;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		DebugVer	:  4-0,
-		TraceVer	:  8-4,
-		PMUVer		: 12-8,
-		BRPs		: 16-12,
-		PMSS		: 20-16,
-		WRPs		: 24-20,
-		SEBEP		: 28-24,
-		CTX_CMPs	: 32-28,
-		PMSVer		: 36-32,
-		DoubleLock	: 40-36,
-		TraceFilt	: 44-40,
-		TraceBuffer	: 48-40,
-		MTPMU		: 52-48,
-		BRBE		: 56-52,
-		ExtTrcBuff	: 60-56,
-		HPMN0		: 64-60;
-	};
-} AA64DFR0;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		SYSPMUID	:  8-0,
-		BRPs		: 16-8,
-		WRPs		: 24-16,
-		CTX_CMPs	: 32-24,
-		SPMU		: 36-32,
-		PMICNTR 	: 40-36,
-		ABLE		: 44-40,
-		ITE		: 48-44,
-		EBEP		: 52-48,
-		DPFZS		: 56-52,
-		ABL_CMPs	: 64-56;
-	};
-} AA64DFR1;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		STEP		:  4-0,
-		BWE		:  8-4,
-		RES0		: 64-8;
-	};
-} AA64DFR2;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		RES0		:  4-0,
-		AES		:  8-4,
-		SHA1		: 12-8,
-		SHA2		: 16-12,
-		CRC32		: 20-16,
-		Atomic		: 24-20,
-		TME		: 28-24,
-		RDM		: 32-28,
-		SHA3		: 36-32,
-		SM3		: 40-36,
-		SM4		: 44-40,
-		DP		: 48-44,
-		FHM		: 52-48,
-		TS		: 56-52,
-		TLB		: 60-56,
-		RNDR		: 64-60;
-	};
-} AA64ISAR0;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		DPB		:  4-0,
-		APA		:  8-4,
-		API		: 12-8,
-		JSCVT		: 16-12,
-		FCMA		: 20-16,
-		LRCPC		: 24-20,
-		GPA		: 28-24,
-		GPI		: 32-28,
-		FRINTTS 	: 36-32,
-		SB		: 40-36,
-		SPECRES 	: 44-40,
-		BF16		: 48-44,
-		DGH		: 52-48,
-		I8MM		: 56-52,
-		XS		: 60-56,
-		LS64		: 64-60;
-	};
-} AA64ISAR1;
-
-typedef union
-{
-	unsigned long long	value;	/* CPU0:0x00000000 ; CPU4:0x00000000 */
-	struct
-	{
-		unsigned long long
-		WFxT		:  4-0,
-		RPRES		:  8-4,
-		GPA3		: 12-8,
-		APA3		: 16-12,
-		MOPS		: 20-16,
-		BC		: 24-20,
-		PAC_frac	: 28-24,
-		CLRBHB		: 32-28,
-		SYSREG_128	: 36-32,
-		SYSINSTR_128	: 40-36,
-		PRFMSLC 	: 44-40,
-		PCDPHINT	: 48-44,
-		RPRFM		: 52-48,
-		CSSC		: 56-52,
-		LUT		: 60-56,
-		ATS1A		: 64-60;
-	};
-} AA64ISAR2;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		CPA		:  4-0,
-		FAMINMAX	:  8-4,
-		TLBIW		: 12-8,
-		PACM		: 16-12,
-		LSFE		: 20-16,
-		OCCMO		: 24-20,
-		LSUI		: 28-24,
-		FPRCVT		: 32-28,
-		RES0		: 64-32;
-	};
-} AA64ISAR3;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		PARange 	:  4-0,
-		ASID_Bits	:  8-4,
-		BigEnd		: 12-8,
-		SNSMem		: 16-12,
-		BigEnd_EL0	: 20-16,
-		TGran16 	: 24-20,
-		TGran64 	: 28-24,
-		TGran4		: 32-28,
-		TGran16_2	: 36-32,
-		TGran64_2	: 40-36,
-		TGran4_2	: 44-40,
-		ExS		: 48-44,
-		RES0		: 56-48,
-		FGT		: 60-56,
-		ECV		: 64-60;
-	};
-} AA64MMFR0;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		HAFDBS		:  4-0,
-		VMID_Bits	:  8-4,
-		VH		: 12-8,
-		HPDS		: 16-12,
-		LO		: 20-16,
-		PAN		: 24-20,
-		SpecSEI		: 28-24,
-		XNX		: 32-28,
-		TWED		: 36-32,
-		ETS		: 40-36,
-		HCX		: 44-40,
-		AFP		: 48-44,
-		nTLBPA		: 52-48,
-		TIDCP1		: 56-52,
-		CMOW		: 60-56,
-		ECBHB		: 64-60;
-	};
-} AA64MMFR1;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		CnP		:  4-0,
-		UAO		:  8-4,
-		LSM		: 12-8,
-		IESB		: 16-12,
-		VARange 	: 20-16,
-		CCIDX		: 24-20,
-		NV		: 28-24,
-		ST		: 32-28,
-		AT		: 36-32,
-		IDS		: 40-36,
-		FWB		: 44-40,
-		RES0		: 48-44,
-		TTL		: 52-48,
-		BBM		: 56-52,
-		EVT		: 60-56,
-		E0PD		: 64-60;
-	};
-} AA64MMFR2;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		TCRX		:  4-0,
-		SCTLRX		:  8-4,
-		S1PIE		: 12-8,
-		S2PIE		: 16-12,
-		S1POE		: 20-16,
-		S2POE		: 24-20,
-		AIE		: 28-24,
-		MEC		: 32-28,
-		D128		: 36-32,
-		D128_2		: 40-36,
-		SNERR		: 44-40,
-		ANERR		: 48-44,
-		RES0		: 52-48,
-		SDERR		: 56-52,
-		ADERR		: 60-56,
-		Spec_FPACC	: 64-60;
-	};
-} AA64MMFR3;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		PoPS		:  4-0,
-		EIESB		:  8-4,
-		ASID2		: 12-8,
-		HACDBS		: 16-12,
-		FGWTE3		: 20-16,
-		NV_frac 	: 24-20,
-		E2H0		: 28-24,
-		RMEGDI		: 32-28,
-		RES0		: 36-32,
-		E3DSE		: 40-36,
-		RES1		: 44-40,
-		SRMASK		: 48-44,
-		RES2		: 64-48;
-	};
-} AA64MMFR4;
-
-typedef union
-{				/* CPU0:0x11112222 ; CPU4:0x1100000011111112 */
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		EL0		:  4-0,  /*0b0001=AArch64;0b0010=AArch{32,64}*/
-		EL1		:  8-4,
-		EL2		: 12-8,
-		EL3		: 16-12,
-		FP		: 20-16,
-		AdvSIMD 	: 24-20,
-		GIC		: 28-24,
-		RAS		: 32-28,
-		SVE		: 36-32,
-		SEL2		: 40-36,
-		MPAM		: 44-40,
-		AMU		: 48-44,
-		DIT		: 52-48,
-		RME		: 56-52,
-		CSV2		: 60-56,
-		CSV3		: 64-60;
-	};
-} AA64PFR0;
-/*
-CPU:AA64PFR0
- 1:0x0000000011112222
- 0:0x0000000011112222
- 2:0x0000000011112222
- 3:0x0000000011112222
- 4:0x1100000011111112
- 5:0x1100000011111112
- 6:0x1100000011111112
- 7:0x1100000011111112
-*/
-typedef union
-{
-	unsigned long long	value;	/*	Pkg:0x00000010		*/
-	struct
-	{
-		unsigned long long
-		BT		:  4-0,
-		SSBS		:  8-4,
-		MTE		: 12-8,
-		RAS_frac	: 16-12,
-		MPAM_frac	: 20-16,
-		SME		: 28-24,
-		RNDR_trap	: 32-28,
-		CSV2_frac	: 36-32,
-		NMI		: 40-36,
-		MTE_frac	: 44-40,
-		GCS		: 48-44,
-		THE		: 52-48,
-		MTEX		: 56-52,
-		DF2		: 60-56,
-		PFAR		: 64-60;
-	};
-} AA64PFR1;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		MTEPERM 	:  4-0,
-		MTESTOREONLY	:  8-4,
-		MTEFAR		: 12-8,
-		RES0		: 16-12,
-		UINJ		: 20-16,
-		RES1		: 32-20,
-		FPMR		: 36-32,
-		RES2		: 64-36;
-	};
-} AA64PFR2;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		RES0		: 28-0,
-		SF8DP2		: 29-28,
-		SF8DP4		: 30-29,
-		SF8FMA		: 31-30,
-		RES1		: 32-31,
-		F32F32		: 33-32,
-		BI32I32 	: 34-33,
-		B16F32		: 35-34,
-		F16F32		: 36-35,
-		I8I32		: 40-36,
-		F8F32		: 41-40,
-		F8F16		: 42-41,
-		F16F16		: 43-42,
-		B16B16		: 44-43,
-		I16I32		: 48-44,
-		F64F64		: 49-48,
-		RES2		: 52-49,
-		I16I64		: 56-52,
-		SMEver		: 60-56,
-		LUTv2		: 61-60,
-		RES3		: 63-61,
-		FA64		: 64-63;
-	};
-} AA64SMFR0;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		SVE_Ver 	:  4-0,
-		SVE_AES 	:  8-4,
-		RES0		: 16-8,
-		BitPerm 	: 20-16,
-		SVE_BF16	: 24-20,
-		B16B16		: 28-24,
-		RES1		: 32-28,
-		SVE_SHA3	: 36-32,
-		RES2		: 40-36,
-		SVE_SM4 	: 44-40,
-		SVE_I8MM	: 48-44,
-		RES3		: 52-48,
-		SVE_F32MM	: 56-52,
-		SVE_F64MM	: 60-56,
-		RES4		: 64-60;
-	};
-} AA64ZFR0;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		RES0		: 12-0,
-		SSBS		: 13-12,
-		RES1		: 32-13,
-		RES2		: 64-32;
-	};
-} SSBS2;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		SIMDReg 	:  4-0,
-		FPSP		:  8-4,
-		FPDP		: 12-8,
-		FPTrap		: 16-12,
-		FPDivide	: 20-16,
-		FPSqrt		: 24-20,
-		FPShVec 	: 28-24,
-		FPRound 	: 32-28,
-		RES0		: 64-32;
-	};
-} MVFR0;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		FPFtZ		:  4-0,
-		FPDNaN		:  8-4,
-		SIMDLS		: 12-8,
-		SIMDInt 	: 16-12,
-		SIMDSP		: 20-16,
-		SIMDHP		: 24-20,
-		FPHP		: 28-24,
-		SIMDFMAC 	: 32-28,
-		RES0		: 64-32;
-	};
-} MVFR1;
-
-typedef union
-{
-	unsigned long long	value;
-	struct
-	{
-		unsigned long long
-		SIMDMisc	:  4-0,
-		FPMisc		:  8-4,
-		RES0		: 32-8,
-		RES1		: 64-32;
-	};
-} MVFR2;
-
-typedef union
-{	/* R82; A55; A75; A76; A76AE; A77; A78; A78AE; A78C; X1; X1C; N3; V1 */
-	unsigned long long	value;	/*	Pkg:0x0000000007bfda77	*/
-	struct
-	{
-		unsigned long long
-		NUMCORE 	:  4-0,
-		NUMPE		:  9-4,
-		L3		: 10-9,
-		WRLAT		: 12-10,
-		RDLAT		: 13-12,
-		RDSLC		: 14-13,
-		ECC		: 15-14,
-		NUMMAS		: 17-15,
-		MAS		: 18-17,
-		RAZ1		: 19-18,
-		ACPW		: 20-19,
-		ACP		: 21-20,
-		RAZ2		: 22-21,
-		PPW		: 23-22,
-		PP		: 24-23,
-		RAZ3		: 25-24,
-		TRSH		: 29-25,
-		TRSV		: 33-29,
-		RAZ4		: 51-33,
-		L3SLC		: 54-51,
-		RAZ5		: 55-24,
-		SFIDX		: 59-55,
-		SFWAY		: 61-59,
-		NODES		: 64-61;
-	} IMP;
-	struct
-	{
-		unsigned long long
-		NUMCORE 	:  3-0,
-		RAZ1		:  4-3,
-		L3		:  5-4,
-		WRLAT		:  6-5,
-		RDLAT		:  7-6,
-		RDSLC		:  8-7,
-		ECC		:  9-8,
-		MAS		: 11-9,
-		ACP		: 12-11,
-		PP		: 13-12,
-		MAS_Ext 	: 14-13,
-		CPUSLC		: 22-14,
-		RAZ2		: 23-22,
-		WRDLY		: 24-23,
-		NUMPE		: 28-24,
-		RAZ3		: 30-28,
-		SafetyMode	: 32-30,
-		RSVD		: 64-32;
-	} DSU;
-} CLUSTERCFR;
-
-typedef union
-{
-	unsigned long long	value;	/*	Pkg:0x0000000000000041	*/
-	struct
-	{
-		unsigned long long
-		Revision	:  4-0,
-		Variant 	:  8-4,
-		RAZ		: 32-8,
-		RSVD		: 64-32;
-	};
-} CLUSTERIDR;
 
 typedef union
 {