From 036cb1692a6121ad3961acbb375b3930f2722ebb Mon Sep 17 00:00:00 2001 From: lenawanel Date: Wed, 29 May 2024 21:59:44 +0200 Subject: [PATCH 1/2] add tests for expected signed dword fload conversion behavior addressess part of https://github.com/d0iasm/rvemu/issues/33#issue-2324074572 --- tests/rv32d.rs | 34 ++++++++++++++++++++++++++++++++-- tests/rv32f.rs | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 64 insertions(+), 4 deletions(-) diff --git a/tests/rv32d.rs b/tests/rv32d.rs index e7bbc77..7d63df2 100644 --- a/tests/rv32d.rs +++ b/tests/rv32d.rs @@ -380,7 +380,7 @@ fn fcvtdw_rd_rs1_rs2() { emu.cpu.xregs.write(31, -4 as i64 as u64); let data = vec![ - 0xd3, 0x8f, 0x0f, 0xd2, // fcvt.d.w x31, f31 (rm: 000) + 0xd3, 0x8f, 0x0f, 0xd2, // fcvt.d.w f31, x31 (rm: 000) ]; let expected_xregs = helper::create_xregs(vec![(31, -4 as i64 as u64)]); let expected_fregs = helper::create_fregs(vec![(31, -4.0)]); @@ -395,7 +395,7 @@ fn fcvtdwu_rd_rs1_rs2() { emu.cpu.xregs.write(31, 4); let data = vec![ - 0xd3, 0x8f, 0x1f, 0xd2, // fcvt.d.wu x31, f31 (rm: 000) + 0xd3, 0x8f, 0x1f, 0xd2, // fcvt.d.wu f31, x31 (rm: 000) ]; let expected_xregs = helper::create_xregs(vec![(31, 4)]); let expected_fregs = helper::create_fregs(vec![(31, 4.0)]); @@ -403,6 +403,36 @@ fn fcvtdwu_rd_rs1_rs2() { helper::run(&mut emu, data, &expected_xregs, &expected_fregs); } +#[test] +fn fcvtld_rd_fs1() { + let mut emu = Emulator::new(); + + emu.cpu.fregs.write(31, -1.0); + + let data = vec![ + 0xd3, 0xff, 0x2f, 0xc2, // fcvt.l.d x31,f31 (rm: 000) + ]; + let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]); + let expected_fregs = helper::create_fregs(vec![(31, -1.0)]); + + helper::run(&mut emu, data, &expected_xregs, &expected_fregs); +} + +#[test] +fn fcvtdl_frd_rs1() { + let mut emu = Emulator::new(); + + emu.cpu.xregs.write(31, -1i64 as u64); + + let data = vec![ + 0xd3, 0xff, 0x2f, 0xd2, // fcvt.d.l f31,x31 (rm: 000) + ]; + let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]); + let expected_fregs = helper::create_fregs(vec![(31, -1.0)]); + + helper::run(&mut emu, data, &expected_xregs, &expected_fregs); +} + #[test] fn fclassd_rd_rs1_rs2() { let mut emu = Emulator::new(); diff --git a/tests/rv32f.rs b/tests/rv32f.rs index 5205ba9..21e0cce 100644 --- a/tests/rv32f.rs +++ b/tests/rv32f.rs @@ -356,7 +356,7 @@ fn fcvtsw_rd_rs1_rs2() { emu.cpu.xregs.write(31, -4 as i64 as u64); let data = vec![ - 0xd3, 0x8f, 0x0f, 0xd0, // fcvt.s.w x31, f31 (rm: 000) + 0xd3, 0x8f, 0x0f, 0xd0, // fcvt.s.w f31, x31 (rm: 000) ]; let expected_xregs = helper::create_xregs(vec![(31, -4 as i64 as u64)]); let expected_fregs = helper::create_fregs(vec![(31, -4.0)]); @@ -371,7 +371,7 @@ fn fcvtswu_rd_rs1_rs2() { emu.cpu.xregs.write(31, 4); let data = vec![ - 0xd3, 0x8f, 0x1f, 0xd0, // fcvt.s.wu x31, f31 (rm: 000) + 0xd3, 0x8f, 0x1f, 0xd0, // fcvt.s.wu f31, x31 (rm: 000) ]; let expected_xregs = helper::create_xregs(vec![(31, 4)]); let expected_fregs = helper::create_fregs(vec![(31, 4.0)]); @@ -379,6 +379,36 @@ fn fcvtswu_rd_rs1_rs2() { helper::run(&mut emu, data, &expected_xregs, &expected_fregs); } +#[test] +fn fcvtls_rd_fs1() { + let mut emu = Emulator::new(); + + emu.cpu.fregs.write(31, -1.0); + + let data = vec![ + 0xd3, 0xff, 0x2f, 0xc0, // fcvt.l.s x31,f31 (rm: 000) + ]; + let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]); + let expected_fregs = helper::create_fregs(vec![(31, -1.0)]); + + helper::run(&mut emu, data, &expected_xregs, &expected_fregs); +} + +#[test] +fn fcvtsl_frd_rs1() { + let mut emu = Emulator::new(); + + emu.cpu.xregs.write(31, -1i64 as u64); + + let data = vec![ + 0xd3, 0xff, 0x2f, 0xd0, // fcvt.s.l f31,x31 (rm: 000) + ]; + let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]); + let expected_fregs = helper::create_fregs(vec![(31, -1.0)]); + + helper::run(&mut emu, data, &expected_xregs, &expected_fregs); +} + #[test] fn fmvxw_rd_rs1_rs2() { let mut emu = Emulator::new(); From 786534db7819951bece3e73414faeff1de0bf206 Mon Sep 17 00:00:00 2001 From: lenawanel Date: Wed, 29 May 2024 22:23:58 +0200 Subject: [PATCH 2/2] fix the conversion issue fixes https://github.com/d0iasm/rvemu/issues/33#issue-2324074572 --- src/cpu.rs | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/cpu.rs b/src/cpu.rs index 759dc40..a4c0fc6 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -2979,7 +2979,7 @@ impl Cpu { self.debug(inst, "fcvt.l.s"); self.xregs - .write(rd, (self.fregs.read(rs1) as f32).round() as u64); + .write(rd, (self.fregs.read(rs1) as f32).round() as i64 as u64); } 0x3 => { // fcvt.lu.s @@ -3019,7 +3019,8 @@ impl Cpu { inst_count!(self, "fcvt.l.d"); self.debug(inst, "fcvt.l.d"); - self.xregs.write(rd, self.fregs.read(rs1).round() as u64); + self.xregs + .write(rd, self.fregs.read(rs1).round() as i64 as u64); } 0x3 => { // fcvt.lu.d @@ -3056,7 +3057,8 @@ impl Cpu { inst_count!(self, "fcvt.s.l"); self.debug(inst, "fcvt.s.l"); - self.fregs.write(rd, (self.xregs.read(rs1) as f32) as f64); + self.fregs + .write(rd, (self.xregs.read(rs1) as i64 as f32) as f64); } 0x3 => { // fcvt.s.lu @@ -3092,7 +3094,7 @@ impl Cpu { inst_count!(self, "fcvt.d.l"); self.debug(inst, "fcvt.d.l"); - self.fregs.write(rd, self.xregs.read(rs1) as f64); + self.fregs.write(rd, self.xregs.read(rs1) as i64 as f64); } 0x3 => { // fcvt.d.lu