-
Notifications
You must be signed in to change notification settings - Fork 2
/
Copy pathgpif.c
293 lines (268 loc) · 16.6 KB
/
gpif.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
// This program configures the General Programmable Interface (GPIF) for FX2.
// Please do not modify sections of text which are marked as "DO NOT EDIT ...".
//
// DO NOT EDIT ...
// GPIF Initialization
// Interface Timing Async
// Internal Ready Init IntRdy=1
// CTL Out Tristate-able Binary
// SingleWrite WF Select 1
// SingleRead WF Select 0
// FifoWrite WF Select 3
// FifoRead WF Select 2
// Data Bus Idle Drive Tristate
// END DO NOT EDIT
// DO NOT EDIT ...
// GPIF Wave Names
// Wave 0 = Single R
// Wave 1 = Single W
// Wave 2 = FIFO Rea
// Wave 3 = FIFO Wri
// GPIF Ctrl Outputs Level
// CTL 0 = CTL0 CMOS
// CTL 1 = CTL1 CMOS
// CTL 2 = CTL2 CMOS
// CTL 3 = CTL3 CMOS
// CTL 4 = CTL4 CMOS
// CTL 5 = CTL5 CMOS
// GPIF Rdy Inputs
// RDY0 = RDY0
// RDY1 = RDY1
// RDY2 = RDY2
// RDY3 = RDY3
// RDY4 = RDY4
// RDY5 = TCXpire
// FIFOFlag = FIFOFlag
// IntReady = IntReady
// END DO NOT EDIT
// DO NOT EDIT ...
//
// GPIF Waveform 0: Single R
//
// Interval 0 1 2 3 4 5 6 Idle (7)
// _________ _________ _________ _________ _________ _________ _________ _________
//
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
// NextData SameData SameData SameData SameData SameData SameData SameData
// Int Trig No Int No Int No Int No Int No Int No Int No Int
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
// Term A
// LFunc
// Term B
// Branch1
// Branch0
// Re-Exec
// Sngl/CRC Default Default Default Default Default Default Default
// CTL0 0 0 0 0 0 0 0 0
// CTL1 1 1 1 1 1 1 1 1
// CTL2 0 0 0 0 0 0 0 0
// CTL3 0 0 0 0 0 0 0 0
// CTL4 0 0 0 0 0 0 0 0
// CTL5 0 0 0 0 0 0 0 0
//
// END DO NOT EDIT
// DO NOT EDIT ...
//
// GPIF Waveform 1: Single W
//
// Interval 0 1 2 3 4 5 6 Idle (7)
// _________ _________ _________ _________ _________ _________ _________ _________
//
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
// NextData SameData SameData SameData SameData SameData SameData SameData
// Int Trig No Int No Int No Int No Int No Int No Int No Int
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
// Term A
// LFunc
// Term B
// Branch1
// Branch0
// Re-Exec
// Sngl/CRC Default Default Default Default Default Default Default
// CTL0 0 0 0 0 0 0 0 0
// CTL1 1 1 1 1 1 1 1 1
// CTL2 0 0 0 0 0 0 0 0
// CTL3 0 0 0 0 0 0 0 0
// CTL4 0 0 0 0 0 0 0 0
// CTL5 0 0 0 0 0 0 0 0
//
// END DO NOT EDIT
// DO NOT EDIT ...
//
// GPIF Waveform 2: FIFO Rea
//
// Interval 0 1 2 3 4 5 6 Idle (7)
// _________ _________ _________ _________ _________ _________ _________ _________
//
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
// DataMode NO Data NO Data NO Data NO Data Activate NO Data NO Data
// NextData SameData SameData SameData SameData SameData SameData SameData
// Int Trig No Int No Int No Int No Int No Int No Int No Int
// IF/Wait Wait 1 Wait 1 Wait 1 IF Wait 1 Wait 2 IF
// Term A RDY0 RDY1
// LFunc AND AND
// Term B RDY0 RDY1
// Branch1 Then 4 Then 0
// Branch0 Else 2 ElseIdle
// Re-Exec No No
// Sngl/CRC Default Default Default Default Default Default Default
// CTL0 1 0 1 0 1 0 0 0
// CTL1 0 0 1 1 1 1 1 1
// CTL2 0 0 0 0 0 0 0 0
// CTL3 0 0 0 0 0 0 0 0
// CTL4 0 0 0 0 0 0 0 0
// CTL5 0 0 0 0 0 0 0 0
//
// END DO NOT EDIT
// DO NOT EDIT ...
//
// GPIF Waveform 3: FIFO Wri
//
// Interval 0 1 2 3 4 5 6 Idle (7)
// _________ _________ _________ _________ _________ _________ _________ _________
//
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
// DataMode Activate Activate Activate Activate Activate Activate NO Data
// NextData SameData SameData SameData SameData NextData SameData SameData
// Int Trig No Int No Int No Int No Int No Int Trig Int No Int
// IF/Wait Wait 1 Wait 4 Wait 3 IF IF Wait 1 IF
// Term A RDY2 RDY1 RDY2
// LFunc AND AND AND
// Term B RDY2 RDY1 RDY2
// Branch1 Then 4 Then 5 Then 6
// Branch0 Else 1 ElseIdle ElseIdle
// Re-Exec No Yes Yes
// Sngl/CRC Default Default Default Default Default Default Default
// CTL0 0 1 0 0 0 0 0 0
// CTL1 0 1 1 1 1 1 1 1
// CTL2 0 0 0 0 0 0 0 0
// CTL3 0 0 0 0 0 0 0 0
// CTL4 0 0 0 0 0 0 0 0
// CTL5 0 0 0 0 0 0 0 0
//
// END DO NOT EDIT
// GPIF Program Code
// DO NOT EDIT ...
#include <fx2regs.h>
#include <fx2macros.h>
#include <delay.h>
#define SYNCDELAY SYNCDELAY4;
// END DO NOT EDIT
// DO NOT EDIT ...
const char __xdata WaveData[128] =
{
// Wave 0
/* LenBr */ 0x04, 0x04, 0x04, 0x03, 0x2a, 0x04, 0x03, 0x07,
/* Opcode*/ 0x06, 0x02, 0x02, 0x02, 0x03, 0x02, 0x02, 0x02,
/* Output*/ 0x01, 0x00, 0x03, 0x02, 0x02, 0x03, 0x02, 0x02,
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
// Wave 1
/* LenBr */ 0x04, 0x04, 0x04, 0x03, 0x2a, 0x04, 0x03, 0x07,
/* Opcode*/ 0x06, 0x02, 0x02, 0x02, 0x03, 0x02, 0x02, 0x02,
/* Output*/ 0x01, 0x00, 0x03, 0x02, 0x02, 0x03, 0x02, 0x02,
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
// Wave 2
/* LenBr */ 0x01, 0x01, 0x01, 0x22, 0x01, 0x02, 0x07, 0x07,
/* Opcode*/ 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x01, 0x00,
/* Output*/ 0x01, 0x00, 0x03, 0x02, 0x03, 0x02, 0x02, 0x02,
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x3F,
// Wave 3
/* LenBr */ 0x01, 0x04, 0x03, 0x21, 0xAF, 0x01, 0xB7, 0x07,
/* Opcode*/ 0x02, 0x02, 0x02, 0x03, 0x07, 0x12, 0x01, 0x00,
/* Output*/ 0x00, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
/* LFun */ 0x00, 0x00, 0x00, 0x12, 0x09, 0x00, 0x12, 0x3F,
};
// END DO NOT EDIT
// DO NOT EDIT ...
const char __xdata FlowStates[36] =
{
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 2 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 3 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
};
// END DO NOT EDIT
// DO NOT EDIT ...
const char __xdata InitData[7] =
{
/* Regs */ 0xA0,0x00,0x00,0x02,0xEA,0x4E,0x00
};
// END DO NOT EDIT
// TO DO: You may add additional code below.
void GpifInit( void )
{
BYTE i;
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// 8051 doesn't have access to waveform memories 'til
// the part is in GPIF mode.
IFCONFIG = 0xEA;
// IFCLKSRC=1 , FIFOs executes on internal clk source
// xMHz=1 , 48MHz internal clk rate
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// ASYNC=1 , master samples asynchronous
// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
// IFCFG[1:0]=10, FX2 in GPIF master mode
GPIFABORT = 0xFF; // abort any waveforms pending
GPIFREADYCFG = InitData[ 0 ];
GPIFCTLCFG = InitData[ 1 ];
GPIFIDLECS = InitData[ 2 ];
GPIFIDLECTL = InitData[ 3 ];
GPIFWFSELECT = InitData[ 5 ];
GPIFREADYSTAT = InitData[ 6 ];
// use dual autopointer feature...
AUTOPTRSETUP = 0x07; // inc both pointers,
// ...warning: this introduces pdata hole(s)
// ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
// source
AUTOPTRH1 = MSB( &WaveData );
AUTOPTRL1 = LSB( &WaveData );
// destination
AUTOPTRH2 = 0xE4;
AUTOPTRL2 = 0x00;
// transfer
for ( i = 0x00; i < 128; i++ )
{
EXTAUTODAT2 = EXTAUTODAT1;
}
// Configure GPIF Address pins, output initial value,
PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
OEC = 0xFF; // and as outputs
PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
OEE |= 0x80; // and as output
// ...OR... tri-state GPIFADR[8:0] pins
// PORTCCFG = 0x00; // [7:0] as port I/O
// OEC = 0x00; // and as inputs
// PORTECFG &= 0x7F; // [8] as port I/O
// OEE &= 0x7F; // and as input
// GPIF address pins update when GPIFADRH/L written
SYNCDELAY; //
GPIFADRH = 0x00; // bits[7:1] always 0
SYNCDELAY; //
GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
// Configure GPIF FlowStates registers for Wave 0 of WaveData
FLOWSTATE = FlowStates[ 0 ];
FLOWLOGIC = FlowStates[ 1 ];
FLOWEQ0CTL = FlowStates[ 2 ];
FLOWEQ1CTL = FlowStates[ 3 ];
FLOWHOLDOFF = FlowStates[ 4 ];
FLOWSTB = FlowStates[ 5 ];
FLOWSTBEDGE = FlowStates[ 6 ];
FLOWSTBHPERIOD = FlowStates[ 7 ];
}