20131010r

Today I should get the logical design done.

Etter samtaler med Per-Thommas:

• Dataminne er 16 bits ord, ikke 32 som tidligere antatt.
• The flags of the memory should be set like this
• CE# Chip Enable Input = ENABLE
• WE# Write Enable Input = WRITE
• OE# Output Enable Input = GND
• LB# Lower Byte Control = GND
• UB# Upper Byte Control = GND

About configuration the FPGA from U380 page ~50:

If JTAG is the only configuration mode, then PROGRAM_B, INIT_B, and DONE can be tied High to a 330Ω resistor.

Fra UG385: CMPCS_B_2 on the FPGA can be left unconnected or high. SUSPEND can be connected to ground.

Questions for Odd-Rune:

• Where do I attach power and ground to the micro controller?
• Where is the JTAG for the microcontroller?
• What is decoupling, and how is it done best?