20131014f

Tried to compile project, saw a bunch of errors.

• Many of those were caused by the absence of net_lables over the harnesses on top level.
• Some were caused by a port appearing to be a single-signal-port while it had a buss entering it. '
• Had different grid settings between the memorychip schematic and the schematic that memory chip was placed into, which caused some warnings (pins not being alligned smoothly to the grid). I thought that the compile-error was caused by this, but I was wrong and it was, in fact, not.

Seems like most compile-errors in the project are fixed, waiting for Rune to finish his work on microcontroller schematic to try to make a PCB design.