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Connect MPU module
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@dpretet
dpretet committed Oct 7, 2023
1 parent 029acbb commit 9490ce0
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Showing 12 changed files with 613 additions and 160 deletions.
5 changes: 4 additions & 1 deletion rtl/friscv_control.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -89,7 +89,9 @@ module friscv_control
output logic ctrl_rd_wr,
output logic [5 -1:0] ctrl_rd_addr,
output logic [XLEN -1:0] ctrl_rd_val,

// PMP / PMA Check
output logic [AXI_ADDR_W -1:0] pmp_addr,
input wire [4 -1:0] pmp_allow,
// CSR shared bus
input wire [`CSR_SB_W -1:0] csr_sb,
output logic [`CTRL_SB_W -1:0] ctrl_sb
Expand Down Expand Up @@ -559,6 +561,7 @@ module friscv_control

assign pc_val = pc_reg;

assign pmp_addr = pc_reg;

assign flush_reqs = flush_pipe;

Expand Down
162 changes: 96 additions & 66 deletions rtl/friscv_csr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -24,12 +24,42 @@ module friscv_csr
parameter SUPERVISOR_MODE = 0,
// Support user mode
parameter USER_MODE = 0,
// PMP / PMA supported
parameter MPU_SUPPORT = 0,
// Reduced RV32 arch
parameter RV32E = 0,
// MHART_ID CSR value
parameter HART_ID = 0
parameter HART_ID = 0,
// PMP / PMA supported
// = 0, no PMP
// = 1, PMP available but fixed synthesis thus at boot time
// > 1, PMP available and configurable at runtime
parameter MPU_SUPPORT = 0,
// Number of physical memory protection regions
parameter NB_PMP_REGION = 16,
// Maximum PMP regions support by the core
parameter MAX_PMP_REGION = 16,
// PMP value at initialization
parameter PMPCFG0_INIT = 32'h0,
parameter PMPCFG1_INIT = 32'h0,
parameter PMPCFG2_INIT = 32'h0,
parameter PMPCFG3_INIT = 32'h0,
parameter PMPADDR0_INIT = 32'h0,
parameter PMPADDR1_INIT = 32'h0,
parameter PMPADDR2_INIT = 32'h0,
parameter PMPADDR3_INIT = 32'h0,
parameter PMPADDR4_INIT = 32'h0,
parameter PMPADDR5_INIT = 32'h0,
parameter PMPADDR6_INIT = 32'h0,
parameter PMPADDR7_INIT = 32'h0,
parameter PMPADDR8_INIT = 32'h0,
parameter PMPADDR9_INIT = 32'h0,
parameter PMPADDR10_INIT = 32'h0,
parameter PMPADDR11_INIT = 32'h0,
parameter PMPADDR12_INIT = 32'h0,
parameter PMPADDR13_INIT = 32'h0,
parameter PMPADDR14_INIT = 32'h0,
parameter PMPADDR15_INIT = 32'h0,
// Virtual memory support
parameter MMU_SUPPORT = 0
)(
// Clock/reset interface
input wire aclk,
Expand Down Expand Up @@ -806,33 +836,33 @@ module friscv_csr
end
end
end
//

///////////////////////////////////////////////////////////////////////////
// PMPCFG0/3 - 0x3A0-0x3A3
///////////////////////////////////////////////////////////////////////////
always @ (posedge aclk or negedge aresetn) begin
if (!aresetn) begin
pmpcfg0 <= {XLEN{1'b0}};
pmpcfg1 <= {XLEN{1'b0}};
pmpcfg2 <= {XLEN{1'b0}};
pmpcfg3 <= {XLEN{1'b0}};
pmpcfg0 <= PMPCFG0_INIT;
pmpcfg1 <= PMPCFG1_INIT;
pmpcfg2 <= PMPCFG2_INIT;
pmpcfg3 <= PMPCFG3_INIT;
end else if (srst) begin
pmpcfg0 <= {XLEN{1'b0}};
pmpcfg1 <= {XLEN{1'b0}};
pmpcfg2 <= {XLEN{1'b0}};
pmpcfg3 <= {XLEN{1'b0}};
end else if (MPU_SUPPORT) begin
pmpcfg0 <= PMPCFG0_INIT;
pmpcfg1 <= PMPCFG1_INIT;
pmpcfg2 <= PMPCFG2_INIT;
pmpcfg3 <= PMPCFG3_INIT;
end else if (MPU_SUPPORT > 1) begin
if (csr_wren) begin
if (csr==PMPCFG0) begin
if (csr==PMPCFG0 && NB_PMP_REGION>=1) begin
pmpcfg0 <= newval;
end
if (csr==PMPCFG1) begin
if (csr==PMPCFG1 && NB_PMP_REGION>=5) begin
pmpcfg1 <= newval;
end
if (csr==PMPCFG2) begin
if (csr==PMPCFG2 && NB_PMP_REGION>=9) begin
pmpcfg2 <= newval;
end
if (csr==PMPCFG3) begin
if (csr==PMPCFG3 && NB_PMP_REGION>=13) begin
pmpcfg3 <= newval;
end
end
Expand All @@ -844,57 +874,57 @@ module friscv_csr
///////////////////////////////////////////////////////////////////////////
always @ (posedge aclk or negedge aresetn) begin
if (!aresetn) begin
pmpaddr0 <= {XLEN{1'b0}};
pmpaddr1 <= {XLEN{1'b0}};
pmpaddr2 <= {XLEN{1'b0}};
pmpaddr3 <= {XLEN{1'b0}};
pmpaddr4 <= {XLEN{1'b0}};
pmpaddr5 <= {XLEN{1'b0}};
pmpaddr6 <= {XLEN{1'b0}};
pmpaddr7 <= {XLEN{1'b0}};
pmpaddr8 <= {XLEN{1'b0}};
pmpaddr9 <= {XLEN{1'b0}};
pmpaddr10 <= {XLEN{1'b0}};
pmpaddr11 <= {XLEN{1'b0}};
pmpaddr12 <= {XLEN{1'b0}};
pmpaddr13 <= {XLEN{1'b0}};
pmpaddr14 <= {XLEN{1'b0}};
pmpaddr15 <= {XLEN{1'b0}};
pmpaddr0 <= PMPADDR0_INIT;
pmpaddr1 <= PMPADDR1_INIT;
pmpaddr2 <= PMPADDR2_INIT;
pmpaddr3 <= PMPADDR3_INIT;
pmpaddr4 <= PMPADDR4_INIT;
pmpaddr5 <= PMPADDR5_INIT;
pmpaddr6 <= PMPADDR6_INIT;
pmpaddr7 <= PMPADDR7_INIT;
pmpaddr8 <= PMPADDR8_INIT;
pmpaddr9 <= PMPADDR9_INIT;
pmpaddr10 <= PMPADDR10_INIT;
pmpaddr11 <= PMPADDR11_INIT;
pmpaddr12 <= PMPADDR12_INIT;
pmpaddr13 <= PMPADDR13_INIT;
pmpaddr14 <= PMPADDR14_INIT;
pmpaddr15 <= PMPADDR15_INIT;
end else if (srst) begin
pmpaddr0 <= {XLEN{1'b0}};
pmpaddr1 <= {XLEN{1'b0}};
pmpaddr2 <= {XLEN{1'b0}};
pmpaddr3 <= {XLEN{1'b0}};
pmpaddr4 <= {XLEN{1'b0}};
pmpaddr5 <= {XLEN{1'b0}};
pmpaddr6 <= {XLEN{1'b0}};
pmpaddr7 <= {XLEN{1'b0}};
pmpaddr8 <= {XLEN{1'b0}};
pmpaddr9 <= {XLEN{1'b0}};
pmpaddr10 <= {XLEN{1'b0}};
pmpaddr11 <= {XLEN{1'b0}};
pmpaddr12 <= {XLEN{1'b0}};
pmpaddr13 <= {XLEN{1'b0}};
pmpaddr14 <= {XLEN{1'b0}};
pmpaddr15 <= {XLEN{1'b0}};
end else if (MPU_SUPPORT) begin
pmpaddr0 <= PMPADDR0_INIT;
pmpaddr1 <= PMPADDR1_INIT;
pmpaddr2 <= PMPADDR2_INIT;
pmpaddr3 <= PMPADDR3_INIT;
pmpaddr4 <= PMPADDR4_INIT;
pmpaddr5 <= PMPADDR5_INIT;
pmpaddr6 <= PMPADDR6_INIT;
pmpaddr7 <= PMPADDR7_INIT;
pmpaddr8 <= PMPADDR8_INIT;
pmpaddr9 <= PMPADDR9_INIT;
pmpaddr10 <= PMPADDR10_INIT;
pmpaddr11 <= PMPADDR11_INIT;
pmpaddr12 <= PMPADDR12_INIT;
pmpaddr13 <= PMPADDR13_INIT;
pmpaddr14 <= PMPADDR14_INIT;
pmpaddr15 <= PMPADDR15_INIT;
end else if (MPU_SUPPORT > 1) begin
if (csr_wren) begin
if (csr==PMPADDR0 ) pmpaddr0 <= newval;
if (csr==PMPADDR1 ) pmpaddr1 <= newval;
if (csr==PMPADDR2 ) pmpaddr2 <= newval;
if (csr==PMPADDR3 ) pmpaddr3 <= newval;
if (csr==PMPADDR4 ) pmpaddr4 <= newval;
if (csr==PMPADDR5 ) pmpaddr5 <= newval;
if (csr==PMPADDR6 ) pmpaddr6 <= newval;
if (csr==PMPADDR7 ) pmpaddr7 <= newval;
if (csr==PMPADDR8 ) pmpaddr8 <= newval;
if (csr==PMPADDR9 ) pmpaddr9 <= newval;
if (csr==PMPADDR10) pmpaddr10 <= newval;
if (csr==PMPADDR11) pmpaddr11 <= newval;
if (csr==PMPADDR12) pmpaddr12 <= newval;
if (csr==PMPADDR13) pmpaddr13 <= newval;
if (csr==PMPADDR14) pmpaddr14 <= newval;
if (csr==PMPADDR15) pmpaddr15 <= newval;
if (csr==PMPADDR0 && NB_PMP_REGION>1 ) pmpaddr0 <= newval;
if (csr==PMPADDR1 && NB_PMP_REGION>2 ) pmpaddr1 <= newval;
if (csr==PMPADDR2 && NB_PMP_REGION>3 ) pmpaddr2 <= newval;
if (csr==PMPADDR3 && NB_PMP_REGION>4 ) pmpaddr3 <= newval;
if (csr==PMPADDR4 && NB_PMP_REGION>5 ) pmpaddr4 <= newval;
if (csr==PMPADDR5 && NB_PMP_REGION>6 ) pmpaddr5 <= newval;
if (csr==PMPADDR6 && NB_PMP_REGION>7 ) pmpaddr6 <= newval;
if (csr==PMPADDR7 && NB_PMP_REGION>8 ) pmpaddr7 <= newval;
if (csr==PMPADDR8 && NB_PMP_REGION>9 ) pmpaddr8 <= newval;
if (csr==PMPADDR9 && NB_PMP_REGION>10) pmpaddr9 <= newval;
if (csr==PMPADDR10 && NB_PMP_REGION>11) pmpaddr10 <= newval;
if (csr==PMPADDR11 && NB_PMP_REGION>12) pmpaddr11 <= newval;
if (csr==PMPADDR12 && NB_PMP_REGION>13) pmpaddr12 <= newval;
if (csr==PMPADDR13 && NB_PMP_REGION>14) pmpaddr13 <= newval;
if (csr==PMPADDR14 && NB_PMP_REGION>14) pmpaddr14 <= newval;
if (csr==PMPADDR15 && NB_PMP_REGION>15) pmpaddr15 <= newval;
end
end
end
Expand Down
10 changes: 5 additions & 5 deletions rtl/friscv_h.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -122,11 +122,11 @@
`define PMP_NA4 2
`define PMP_NAPOT 3

`define PMP_R 0
`define PMP_W 1
`define PMP_X 2
`define PMP_A 3
`define PMP_L 7
`define PMA_R 0
`define PMA_W 1
`define PMA_X 2
`define PMA_A 3 // 4:3
`define PMA_L 7

//////////////////////////////////////////////////////////////////
// Instruction bus feeding ALUs
Expand Down
14 changes: 9 additions & 5 deletions rtl/friscv_memfy.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,9 @@ module friscv_memfy
output logic [5 -1:0] memfy_rd_addr,
output logic [XLEN -1:0] memfy_rd_val,
output logic [XLEN/8 -1:0] memfy_rd_strb,
// PMP / PMA Checks
output logic [AXI_ADDR_W -1:0] pmp_addr,
input wire [4 -1:0] pmp_allow,
// data memory interface
output logic awvalid,
input wire awready,
Expand Down Expand Up @@ -660,7 +663,7 @@ module friscv_memfy
// Manage the RD write operation
////////////////////////////////////////////////////////////////////////

generate if (SYNC_RD_WR) begin
generate if (SYNC_RD_WR) begin : RD_WR_FFD

always @ (posedge aclk or negedge aresetn) begin
if (!aresetn) begin
Expand All @@ -682,7 +685,7 @@ module friscv_memfy
end
end

end else begin
end else begin : RD_WR_COMB

assign memfy_rd_wr = rvalid & rready;
assign memfy_rd_addr = rd_r;
Expand All @@ -702,6 +705,7 @@ module friscv_memfy

// The address to access during a LOAD or a STORE
assign addr = $signed({{(XLEN-12){imm12[11]}}, imm12}) + $signed(memfy_rs1_val);
assign pmp_addr = addr;

// Unused: information forwarded to control unit for FENCE execution:
// bit 0: memory write
Expand All @@ -716,15 +720,15 @@ module friscv_memfy
////////////////////////////////////////////////////////////////////////////
generate

if (IO_MAP_NB > 0) begin
if (IO_MAP_NB > 0) begin : IO_MAP_DEC

for (genvar i=0;i<IO_MAP_NB;i=i+1) begin
for (genvar i=0;i<IO_MAP_NB;i=i+1) begin : GEN_IO_HIT
assign io_map_hit[i] = (addr>=IO_MAP[i*2*XLEN+:XLEN] && addr<=IO_MAP[i*2*XLEN+XLEN+:XLEN]);
end

assign is_io_req = |io_map_hit;

end else begin
end else begin : NO_IO_MAP

assign is_io_req = 1'b0;

Expand Down
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