New: Check access fault in u-mode

dpretet · Nov 14, 2023 · 9515da1 · 9515da1
1 parent 65230e9
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diff --git a/doc/TODO.md b/doc/TODO.md
@@ -35,38 +35,37 @@ Traps
 - [ ] Vector interrupts
 - [ ] Interrupts mixed over exceptions
 
-Loop d'access de RW avec des illegal access (misaligned et illegal)
-Faire varier la periode de l'EIRQ
-Ecrire un contexte switch pour les tests
+- [X] Faire varier la periode de l'EIRQ
 
 U-mode
 - [X] pass from/to m-mode/u-mode
 - [X] try mret in u-mode, needs to fail
 - [X] try to access m-mode only CSRs
 
-Interrupt
+Traps
 - [X] Do something within a loop with interrupt enabled, data needs to be OK
-- [ ] WFI in u-mode, interrupt enabled, trapped in m-mode
-- [ ] WFI in u-mode, interrupt disabled, NOP
+- [X] WFI in u-mode, interrupt enabled, trapped in m-mode
+- [X] WFI in u-mode, interrupt disabled, NOP
 - [ ] Add test for vector table
 - [ ] Test des exception load/store misaligned
-- [ ] test MSTATUS.TW
+- [ ] Test MSTATUS.TW
 
 MPU:
 - [X] configure registers
-- [ ] all region configuration mode: NA4 / NAPOT / TOR
-- [ ] multiple mixed region type and size
-- [ ] Access exceptions
-    -> Store = store access-fault
-    -> Load = load access-fault
-    -> Execute = instruction access-fault
-    - [ ] read/execute instruction outside allowed regions (U-mode)
-    - [ ] read/write data in U-mode
-    - [ ] read/write data in M-mode with MPRV + MPP w/ U-mode
+- [X] all region configuration mode: NA4 / NAPOT / TOR
+- [X] multiple mixed region type and size
+- [-] Access exceptions
+    - [X] execute instruction outside allowed regions (U-mode)
+    - [X] write data in U-mode
+    - [X] read data in U-mode
+    - [ ] read data in M-mode with MPRV=1 + MPP w/ U-mode
+    - [ ] write data in M-mode with MPRV=1 + MPP w/ U-mode
+    - [ ] execute in M-mode without X + locked region
 - [ ] locked access to change configuration
-- [ ] locked region accessed wrongly by m-mode
+- [ ] region's permissions overlap
 
 Final:
 - Pass compliance with U-mode
+- Run REPL app
 - Review testcases
 - Parse again the documentation
diff --git a/doc/project_mgt_hw.md b/doc/project_mgt_hw.md
@@ -6,7 +6,9 @@
     - [-] Support PMP/PMA
     - [ ] Atomic operations for single core
     - [ ] AXI Exception management with a CLIC
+        - maange all traps into it?
     - [ ] Zc extension
+    - [ ] https://github.com/eembc/coremark
 
 
 # BACKLOG
@@ -39,6 +41,7 @@ Any new features should be carefully study to ensure a proper exception and inte
     - raise an exception
     - methode AER-like pour les enregistrer: src, address, permission
     - trig an interrupt catched with PLIC controller
+    - https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-risc-v.html
 
 
 ## Cache Stages
@@ -55,6 +58,7 @@ Any new features should be carefully study to ensure a proper exception and inte
 - [ ] New cache associativity (2 / 4 / 8 ways configurable)
 - [ ] OoO read: miss could be stacked and served later waiting for cache fill and continue reading the next address
 - [ ] Fully concurrent read / write access (Issue #1)
+    - Split memfy in load unit & store unit
 
 
 ## Miscellanous

diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv
@@ -659,7 +659,7 @@ module friscv_control
                     // new instruction from memory:
                     ///////////////////////////////////////////////////////////
 
-                    // 
+                    //
                     // Any trap handling, asynchronous and synchronous
                     //
                     if (trap_occuring) begin
@@ -896,7 +896,7 @@ module friscv_control
                         status <= 5'b0;
                         flush_pipe <= 1'b1;
                         if (USER_MODE && sb_mie) priv_mode <= `MMODE;
-                        
+
                         if (sb_mie) begin
                             arid <= next_id(arid, MAX_ID, AXI_ID_MASK);
                             araddr <= mtvec;
@@ -1190,7 +1190,7 @@ module friscv_control
                        ) ? 1'b1 : 1'b0;
 
     // PC is not aligned with XLEN boundary
-    assign inst_addr_misaligned = (pc[1:0]!=2'b0) ? jump_branch : 1'b0;
+    assign inst_addr_misaligned = (pc_reg[1:0]!=2'b0) ? inst_ready : 1'b0;
 
     //////////////////////////////////////////////////////////////////////
     // WFI timeout management
@@ -1228,13 +1228,13 @@ module friscv_control
     // Unsupported instruction
     assign inst_dec_error = dec_error & (cfsm==FETCH) & inst_ready;
 
-    // Is fetching instruction on forbidden memory region 
-    assign inst_access_fault = (!mpu_allow[`ALW_X] | !mpu_allow[`ALW_R]) &
+    // Is fetching instruction on forbidden memory region
+    assign inst_access_fault = !mpu_allow[`ALW_X] &
                                   (priv_mode == `UMODE ||
-                                   priv_mode==`MMODE && mpu_allow[`ALW_L]);
+                                   priv_mode == `MMODE & mpu_allow[`ALW_L]);
 
     //////////////////////////////////////////////////////////////////////
-    // Stores the incoming excpetions from processing. Can't handle 
+    // Stores the incoming excpetions from processing. Can't handle
     // multiple exceptions on the same cycle but should not arrive
     //////////////////////////////////////////////////////////////////////
     friscv_scfifo
@@ -1266,7 +1266,7 @@ module friscv_control
                            proc_exceptions[`SAF]  ;
 
     // Pull when we trap for one the processing exceptions
-    assign pull_proc_exp = (trap_occuring && !cant_trap && 
+    assign pull_proc_exp = (trap_occuring && !cant_trap &&
                             (mcause_code == 32'h5 ||
                              mcause_code == 32'h7 ||
                              mcause_code == 32'h4 ||
@@ -1298,11 +1298,11 @@ module friscv_control
                                                             '0         ;
 
         assign illegal_csr = (priv_mode==`MMODE || !sys[`IS_CSR])    ? 1'b0       :
-                             (csr[11:0]=='hC00 && !sb_mcounteren[0]) ? inst_ready : // Cycle  
-                             (csr[11:0]=='hC01 && !sb_mcounteren[1]) ? inst_ready : // Time  
-                             (csr[11:0]=='hC02 && !sb_mcounteren[2]) ? inst_ready : // Instret  
-                             (csr[11:4]=='hFC)                       ? inst_ready : // Custom perf. registers  
-                             (csr[ 9:8]!=2'b00)                      ? inst_ready : // M-Mode only registers 
+                             (csr[11:0]=='hC00 && !sb_mcounteren[0]) ? inst_ready : // Cycle
+                             (csr[11:0]=='hC01 && !sb_mcounteren[1]) ? inst_ready : // Time
+                             (csr[11:0]=='hC02 && !sb_mcounteren[2]) ? inst_ready : // Instret
+                             (csr[11:4]=='hFC)                       ? inst_ready : // Custom perf. registers
+                             (csr[ 9:8]!=2'b00)                      ? inst_ready : // M-Mode only registers
                                                                        1'b0 ;
 
     end else begin : NO_UMODE

diff --git a/test/common/debug_platform_verilator.gtkw b/test/common/debug_platform_verilator.gtkw
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Wed Nov  1 17:32:10 2023
+[*] Tue Nov  7 19:31:27 2023
 [*]
 [dumpfile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/friscv_testbench.vcd"
-[dumpfile_mtime] "Wed Nov  1 17:03:56 2023"
-[dumpfile_size] 9007697
+[dumpfile_mtime] "Sun Nov  5 19:46:50 2023"
+[dumpfile_size] 61559319
 [savefile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/debug_platform_verilator.gtkw"
-[timestart] 6058
-[size] 2560 1440
+[timestart] 1
+[size] 1440 900
 [pos] -1 -1
-*-5.355745 6239 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-14.355745 29879 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] friscv_testbench.
 [treeopen] friscv_testbench.friscv_testbench.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.
@@ -24,10 +24,10 @@
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.
-[sst_width] 365
-[signals_width] 344
+[sst_width] 253
+[signals_width] 262
 [sst_expanded] 1
-[sst_vpaned_height] 365
+[sst_vpaned_height] 211
 @c00200
 -AXI4-lite RAM
 @22
@@ -104,7 +104,9 @@ friscv_testbench.friscv_testbench.genblk2.axi4l_ram.p1_bvalid
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg0[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg1[31:0]
+@23
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg2[31:0]
+@22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg3[31:0]
 @200
 -
@@ -125,34 +127,6 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr12[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr13[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr14[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr15[31:0]
-@200
--
-@28
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus_wr
-@22
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus[31:0]
-@28
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mepc_wr
-@22
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mepc[31:0]
-@200
--
-@22
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mstatus[31:0]
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
-@200
--
-@28
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr_rden
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr_wren
-@22
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr[11:0]
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.newval[31:0]
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.oldval[31:0]
-@200
--
-@22
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg0[31:0]
 @1000200
 -CSRs
 @800200
@@ -288,9 +262,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_valid
 -
 @28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring
-@29
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.async_trap_occuring
-@28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sync_trap_occuring
 @200
 -
@@ -306,7 +278,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_ro_wr
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_addr_misaligned
 @200
 -
-@c00200
+@800200
 -CSRs
 @c00022
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0]
@@ -413,6 +385,8 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mtvec[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.aclk
 @200
 -
+@28
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mie
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mcounteren[31:0]
 @28
@@ -431,13 +405,13 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtie
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtip
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtvec[31:0]
-@1401200
+@1000200
 -CSRs
 @200
 -
 @1000200
 -control
-@800200
+@c00200
 -Memfy
 @28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_valid
@@ -488,7 +462,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.store_access
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.store_misaligned
 @200
 -
-@1000200
+@1401200
 -Memfy
 @c00200
 -Registers
@@ -526,7 +500,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x30_t5[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x31_t6[31:0]
 @1401200
 -Registers
-@800200
+@c00200
 -MPU
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.imem_addr[31:0]
@@ -617,6 +591,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKER
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[1].REGION_ACTIVE.pmp_region.pmp_mask[31:0]
 @1000200
 -Region 1
+@1401200
 -MPU
 [pattern_trace] 1
 [pattern_trace] 0
diff --git a/test/common/functions.sh b/test/common/functions.sh
@@ -156,10 +156,10 @@ gather_result() {
     msg=$(grep -ni "ERROR:" tc.log)
 
     if [ "$2" -eq 1 ] || [ "$ec" != 0 ]; then
-        ts_res="${ts_res} - $1:\t❌\n"
+        ts_res="${ts_res}  ❌ $1\n"
         ts_res="${ts_res}$msg\n"
     else
-        ts_res="${ts_res} - $1:\t✅\n"
+        ts_res="${ts_res}  ✅ $1\n"
     fi
 }
 #------------------------------------------------------------------------------

diff --git a/test/priv_sec_testsuite/tests/env/pmp.S b/test/priv_sec_testsuite/tests/env/pmp.S
@@ -1,6 +1,18 @@
 # distributed under the mit license
 # https://opensource.org/licenses/mit-license.php
 
+.equ PMPADDR,   0xFFFFFFFF
+.equ PMPCFG,    0x77777777
+
+.equ S2MB,      0x200000
+.equ S1MB,      0x100000
+.equ S512K,     0x80000
+.equ S256K,     0x40000
+.equ S64KB,     0x10000
+.equ S16KB,     0x10000
+.equ S4KB,      0x4000
+.equ S1KB,      0x1000
+
 .equ OFF,       0
 .equ TOR_RWX,   0x0F
 .equ TOR_RW,    0x0B
@@ -9,8 +21,10 @@
 .equ NA4_RW,    0x13
 .equ NA4_RX,    0x15
 .equ NAPOT_RWX, 0x1F
-.equ NAPOT_RW , 0x1B
-.equ NAPOT_RX , 0x1D
+.equ NAPOT_RW,  0x1B
+.equ NAPOT_RX,  0x1D
+.equ NAPOT_R,   0x19
+.equ NAPOT_W,   0x1C
 
 .equ TOR_LRWX,   0x8F
 .equ TOR_LRW,    0x8B

diff --git a/test/priv_sec_testsuite/tests/env/pmp_service.S b/test/priv_sec_testsuite/tests/env/pmp_service.S
@@ -214,11 +214,6 @@ INTP_SERVICE:
     csrw mie, t4
     j RET_ECALL
 
-EXP_SERVICE:
-    addi s0, s0, 1
-    # j RET_ECALL
-    mret
-
 ////////////////////////////////////////////
 # Configure a NAPOT / NA4 region
 ////////////////////////////////////////////