From 966305baac495ade7c295d241ab6950698bc9964 Mon Sep 17 00:00:00 2001
From: Damien Pretet <damien.pretet@me.com>
Date: Fri, 27 Oct 2023 20:14:09 +0200
Subject: [PATCH] Change: Control now hanldes interrupt as soon they occur.

---
 doc/TODO.md                                   |  12 +-
 rtl/friscv_control.sv                         |  80 +++++-----
 test/common/debug_platform_verilator.gtkw     | 145 ++++++++++++++++--
 .../priv_sec_testsuite/tests/rv32ui-p-test1.v |   2 +-
 .../priv_sec_testsuite/tests/rv32ui-p-test2.v |  98 ++++++------
 .../priv_sec_testsuite/tests/rv32ui-v-test1.v |   2 +-
 .../priv_sec_testsuite/tests/rv32ui-v-test2.v | 105 +++++++------
 .../priv_sec_testsuite/tests/rv64ui-p-test1.v |   2 +-
 .../priv_sec_testsuite/tests/rv64ui-p-test2.v |  98 ++++++------
 .../priv_sec_testsuite/tests/rv64ui-v-test1.v |   2 +-
 .../priv_sec_testsuite/tests/rv64ui-v-test2.v | 111 +++++++-------
 test/priv_sec_testsuite/tests/rv64ui/test1.S  |   8 +-
 test/priv_sec_testsuite/tests/rv64ui/test2.S  | 126 +++++++++------
 13 files changed, 491 insertions(+), 300 deletions(-)

diff --git a/doc/TODO.md b/doc/TODO.md
index f1f1380..081e128 100644
--- a/doc/TODO.md
+++ b/doc/TODO.md
@@ -30,6 +30,15 @@
 
 # Testcases
 
+Traps
+- [ ] Nested interrupts
+- [ ] Vector interrupts
+- [ ] Interrupts mixed over exceptions
+
+Loop d'access de RW avec des illegal access (misaligned et illegal)
+Faire varier la periode de l'EIRQ
+Ecrire un contexte switch pour les tests
+
 U-mode
 - [X] pass from/to m-mode/u-mode
 - [X] try mret in u-mode, needs to fail
@@ -55,8 +64,9 @@ MPU:
     - [ ] read/write data in U-mode
     - [ ] read/write data in M-mode with MPRV + MPP w/ U-mode
 - [ ] locked access to change configuration
-- [ ] locked region accessed wrongly by m-mode- pass xIE & xIP to the control
+- [ ] locked region accessed wrongly by m-mode
 
+Final:
 - Pass compliance with U-mode
 - Review testcases
 - Parse again the documentation
diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv
index 6776ad0..6ef25fc 100644
--- a/rtl/friscv_control.sv
+++ b/rtl/friscv_control.sv
@@ -659,18 +659,28 @@ module friscv_control
                     // new instruction from memory:
                     ///////////////////////////////////////////////////////////
 
+                    // 
+                    // Any trap handling, asynchronous and synchronous
+                    //
+                    if (trap_occuring) begin
+
+                        // Get a new ID for the new batch
+                        arid <= next_id(arid, MAX_ID, AXI_ID_MASK);
+                        // Jump to trap handler
+                        araddr <= mtvec;
+
                     //
                     //   - ECALL / MRET / JALR / Any branching
                     //
-                    if (inst_ready && !proc_busy &&
-                        (jump_branch || sys[`IS_ECALL] || sys[`IS_MRET] || trap_occuring))
+                    end else if (inst_ready && !proc_busy &&
+                        (jump_branch || sys[`IS_ECALL] || sys[`IS_MRET]))
                     begin
 
                         // Get a new ID for the new batch
                         arid <= next_id(arid, MAX_ID, AXI_ID_MASK);
 
-                        // ECALL / Trap handling
-                        if (sys[`IS_ECALL] || trap_occuring) araddr <= mtvec;
+                        // ECALL
+                        if (sys[`IS_ECALL]) araddr <= mtvec;
                         // MRET
                         else if (sys[`IS_MRET]) araddr <= sb_mepc;
                         // jalr / branch
@@ -705,7 +715,23 @@ module friscv_control
 
                     ///////////////////////////////////////////////////////////
                     // Manages the PC vs the different instructions to execute
-                    if (inst_ready) begin
+
+                    // Move to the trap handling when received an
+                    // interrupt, a wrong instruction, ...
+                    if (trap_occuring) begin
+
+                        if (!cant_trap) begin
+                            `ifdef USE_SVL
+                            print_mcause("Handling a trap -> MCAUSE=0x", mcause_code);
+                            print_instruction;
+                            `endif
+                            status[3] <= 1'b1;
+                            flush_pipe <= 1'b1;
+                            if (USER_MODE) priv_mode <= `MMODE;
+                            pc_reg <= mtvec;
+                        end
+
+                    end else if (inst_ready) begin
 
                         // Need to branch/process but ALU/memfy/CSR didn't finish
                         // to execute last instruction, so store PCs.
@@ -713,25 +739,9 @@ module friscv_control
                             pc_jal_saved <= pc_plus4;
                             pc_auipc_saved <= pc_reg;
                         end
-
-                        // Move to the trap handling when received an
-                        // interrupt, a wrong instruction, ...
-                        if (trap_occuring) begin
-
-                            if (!cant_trap) begin
-                                `ifdef USE_SVL
-                                print_mcause("Handling a trap -> MCAUSE=0x", mcause_code);
-                                print_instruction;
-                                `endif
-                                status[3] <= 1'b1;
-                                flush_pipe <= 1'b1;
-                                if (USER_MODE) priv_mode <= `MMODE;
-                                pc_reg <= mtvec;
-                            end
-
                         // Needs to jump or branch thus stop the pipeline
                         // and reload new instructions
-                        end else if (jalr | branching) begin
+                        if (jalr | branching) begin
 
                             if (!cant_jump) begin
                                 print_instruction;
@@ -947,21 +957,21 @@ module friscv_control
                 mcause_wr <= 1'b0;
                 mtval_wr <= 1'b0;
 
-                if (inst_ready) begin
+                if (trap_occuring && !cant_trap) begin
 
-                    if (trap_occuring && !cant_trap) begin
+                    mepc_wr <= 1'b1;
+                    mepc <= pc_reg;
+                    mcause_wr <= 1'b1;
+                    mcause <= mcause_code;
+                    mtval_wr <= 1'b1;
+                    mtval <= mtval_info;
+                    mstatus_wr <= 1'b1;
+                    mstatus <= mstatus_for_trap;
+                    clr_meip <= (mcause_code == 'h8000000B);
 
-                        mepc_wr <= 1'b1;
-                        mepc <= pc_reg;
-                        mcause_wr <= 1'b1;
-                        mcause <= mcause_code;
-                        mtval_wr <= 1'b1;
-                        mtval <= mtval_info;
-                        mstatus_wr <= 1'b1;
-                        mstatus <= mstatus_for_trap;
-                        clr_meip <= (mcause_code == 'h8000000B);
+                end else if (inst_ready) begin
 
-                    end else if (|sys || |fence) begin
+                    if (|sys || |fence) begin
 
                         clr_meip <= 1'b0;
 
@@ -1388,7 +1398,7 @@ module friscv_control
 
     // Trigger the trap handling execution in main FSM
 
-    assign async_trap_occuring = (sb_msip&sb_msie | sb_mtip&sb_mtie | sb_meip&sb_meie) & sb_mie;
+    assign async_trap_occuring = (sb_msip&sb_msie | sb_mtip&sb_mtie | sb_meip&sb_meie&!clr_meip) & sb_mie;
 
     assign sync_trap_occuring = csr_ro_wr            |
                                 inst_addr_misaligned |
diff --git a/test/common/debug_platform_verilator.gtkw b/test/common/debug_platform_verilator.gtkw
index 2eafb23..1b42864 100644
--- a/test/common/debug_platform_verilator.gtkw
+++ b/test/common/debug_platform_verilator.gtkw
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Sun Oct 22 18:40:10 2023
+[*] Thu Oct 26 19:01:31 2023
 [*]
 [dumpfile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/friscv_testbench.vcd"
-[dumpfile_mtime] "Sun Oct 22 18:10:23 2023"
-[dumpfile_size] 2015157
+[dumpfile_mtime] "Thu Oct 26 18:59:38 2023"
+[dumpfile_size] 7831491
 [savefile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/debug_platform_verilator.gtkw"
-[timestart] 2212
+[timestart] 1868
 [size] 1440 900
 [pos] -1 -1
-*-4.496682 2287 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-3.355745 1895 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] friscv_testbench.
 [treeopen] friscv_testbench.friscv_testbench.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.
@@ -21,9 +21,9 @@
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.
 [sst_width] 255
-[signals_width] 237
+[signals_width] 230
 [sst_expanded] 1
-[sst_vpaned_height] 234
+[sst_vpaned_height] 397
 @c00200
 -AXI4-lite RAM
 @22
@@ -97,14 +97,14 @@ friscv_testbench.friscv_testbench.genblk2.axi4l_ram.p1_bvalid
 -CSRs
 @200
 -
-@23
+@22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg0[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg1[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg2[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg3[31:0]
 @200
 -
-@23
+@22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr0[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr1[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr2[31:0]
@@ -123,14 +123,19 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr14[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr15[31:0]
 @200
 -
-@23
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus[31:0]
-@29
+@28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus_wr
+@22
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus[31:0]
+@28
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mepc_wr
+@22
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mepc[31:0]
 @200
 -
-@23
+@22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mstatus[31:0]
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
 @1401200
 -CSRs
 @c00200
@@ -218,21 +223,29 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.ext_irq
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.aclk
 @200
 -
+@c00200
+-AXI4-lite
 @28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.arvalid
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.arready
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.araddr[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.arid[7:0]
+@28
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.rready
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.rvalid
+@22
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.rid[7:0]
+@1401200
+-AXI4-lite
 @200
 -
--
 @28
 [color] 3
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.priv_mode[1:0]
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cfsm[3:0]
-@200
+@201
 -
 @28
 [color] 3
@@ -249,6 +262,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.instruction[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_busy
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_ready
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_ready
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cant_trap
 @200
 -
 @28
@@ -257,14 +271,56 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_valid
 -
 @28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.async_trap_occuring
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sync_trap_occuring
+@200
+-
+@28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.store_misaligned
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.store_access_fault
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.load_access_fault
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.load_misaligned
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_access_fault
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.illegal_csr
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.illegal_instruction
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_ro_wr
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_addr_misaligned
+@200
+-
+@c00022
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0]
+@28
+(0)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0]
+(1)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0]
+(2)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0]
+(3)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0]
+(4)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0]
+(5)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0]
+@1401200
+-group_end
 @200
 -
 @28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_en
+@c00022
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+@28
+(0)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(1)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(2)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(3)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(4)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(5)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(6)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(7)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(8)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(9)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(10)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+(11)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr[11:0]
+@1401200
+-group_end
+@28
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_ro_wr
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mstatus[31:0]
 @200
@@ -285,10 +341,47 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mie[31:0]
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mcause[31:0]
 @28
+[color] 2
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.mepc_wr
-@22
+@c00022
+[color] 2
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
 @28
+(0)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(1)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(2)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(3)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(4)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(5)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(6)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(7)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(8)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(9)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(10)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(11)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(12)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(13)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(14)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(15)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(16)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(17)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(18)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(19)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(20)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(21)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(22)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(23)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(24)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(25)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(26)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(27)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(28)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(29)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(30)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+(31)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
+@1401200
+-group_end
+@28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.mtval_wr
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mtval[31:0]
@@ -299,6 +392,26 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mtvec[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.aclk
 @200
 -
+@22
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mcounteren[31:0]
+@28
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_meie
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_meip
+@22
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mepc[31:0]
+@28
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mie
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_msie
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_msip
+@22
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mstatus[31:0]
+@28
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtie
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtip
+@22
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtvec[31:0]
+@200
+-
 @1000200
 -control
 @c00200
diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test1.v b/test/priv_sec_testsuite/tests/rv32ui-p-test1.v
index fe40272..a468902 100755
--- a/test/priv_sec_testsuite/tests/rv32ui-p-test1.v
+++ b/test/priv_sec_testsuite/tests/rv32ui-p-test1.v
@@ -27,7 +27,7 @@ B7 0E 00 80 93 8E 7E 00 63 08 DF 1D 93 0E 50 00
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 13 0F 0F 80 F3 2E 40 30 B3 EE EE 01 73 90 4E 30
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diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v
index 2fac139..6da1bf4 100755
--- a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v
+++ b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v
@@ -1,9 +1,9 @@
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@@ -26,50 +26,50 @@ B7 0E 00 80 93 8E 7E 00 63 0C DF 6B 93 0E 50 00
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@@ -125,8 +130,7 @@ E3 94 62 FE 67 80 00 00 63 14 30 02 0F 00 F0 0F
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 @00011000
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diff --git a/test/priv_sec_testsuite/tests/rv32ui-v-test1.v b/test/priv_sec_testsuite/tests/rv32ui-v-test1.v
index 4d2ef59..5e158c0 100755
--- a/test/priv_sec_testsuite/tests/rv32ui-v-test1.v
+++ b/test/priv_sec_testsuite/tests/rv32ui-v-test1.v
@@ -196,7 +196,7 @@ B3 F6 C7 00 93 F5 17 00 B3 86 06 01 E3 96 05 FC
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diff --git a/test/priv_sec_testsuite/tests/rv32ui-v-test2.v b/test/priv_sec_testsuite/tests/rv32ui-v-test2.v
index bd17261..85229e5 100755
--- a/test/priv_sec_testsuite/tests/rv32ui-v-test2.v
+++ b/test/priv_sec_testsuite/tests/rv32ui-v-test2.v
@@ -121,11 +121,11 @@ E3 9C 07 FD 73 90 08 10 93 97 26 00 B3 06 F6 00
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 EF F0 9F D2 83 25 C5 08 13 01 01 FB 23 24 81 04
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@@ -139,14 +139,14 @@ EF F0 9F D2 83 25 C5 08 13 01 01 FB 23 24 81 04
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@@ -246,7 +246,7 @@ B7 02 FF FF 93 82 F2 0F 33 73 53 00 93 96 86 00
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diff --git a/test/priv_sec_testsuite/tests/rv64ui-p-test1.v b/test/priv_sec_testsuite/tests/rv64ui-p-test1.v
index e4ac283..4bed4b5 100755
--- a/test/priv_sec_testsuite/tests/rv64ui-p-test1.v
+++ b/test/priv_sec_testsuite/tests/rv64ui-p-test1.v
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diff --git a/test/priv_sec_testsuite/tests/rv64ui-p-test2.v b/test/priv_sec_testsuite/tests/rv64ui-p-test2.v
index 1e6a081..6f72f1c 100755
--- a/test/priv_sec_testsuite/tests/rv64ui-p-test2.v
+++ b/test/priv_sec_testsuite/tests/rv64ui-p-test2.v
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diff --git a/test/priv_sec_testsuite/tests/rv64ui-v-test1.v b/test/priv_sec_testsuite/tests/rv64ui-v-test1.v
index 1b1f026..26fdbd4 100755
--- a/test/priv_sec_testsuite/tests/rv64ui-v-test1.v
+++ b/test/priv_sec_testsuite/tests/rv64ui-v-test1.v
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diff --git a/test/priv_sec_testsuite/tests/rv64ui-v-test2.v b/test/priv_sec_testsuite/tests/rv64ui-v-test2.v
index 1235629..950cec8 100755
--- a/test/priv_sec_testsuite/tests/rv64ui-v-test2.v
+++ b/test/priv_sec_testsuite/tests/rv64ui-v-test2.v
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+73 2F 00 3A 63 9E EE 47 73 10 00 3A B7 7E 77 77
+93 8E 7E 77 73 90 1E 3A 73 2F 10 3A 63 92 EE 47
 73 10 10 3A B7 7E 77 77 93 8E 7E 77 73 90 2E 3A
-73 2F 20 3A 63 9E EE 3F 73 10 20 3A B7 7E 77 77
-93 8E 7E 77 73 90 3E 3A 73 2F 30 3A 63 92 EE 3F
-73 10 30 3A 6F 00 00 35 37 0F 00 00 13 0F 8F 08
+73 2F 20 3A 63 96 EE 45 73 10 20 3A B7 7E 77 77
+93 8E 7E 77 73 90 3E 3A 73 2F 30 3A 63 9A EE 43
+73 10 30 3A 6F 00 40 34 37 0F 00 00 13 0F 8F 08
 F3 2E 00 30 B3 EE EE 01 73 90 0E 30 37 1F 00 00
 13 0F 0F 80 F3 2E 40 30 B3 EE EE 01 73 90 4E 30
-6F 00 40 32 13 04 14 00 6F 00 C0 31 6F 00 80 31
-6F 00 40 31 93 02 40 00 63 42 55 02 93 02 80 00
+6F 00 80 31 13 04 14 00 73 00 20 30 6F 00 C0 30
+6F 00 80 30 93 02 40 00 63 42 55 02 93 02 80 00
 63 40 55 0C 93 02 C0 00 63 4E 55 14 93 02 00 01
-63 4C 55 1E 13 05 10 00 6F 00 C0 2E 93 D5 25 00
+63 4C 55 1E 13 05 10 00 6F 00 00 2E 93 D5 25 00
 73 23 00 3A 93 02 00 00 63 8E A2 00 93 02 10 00
 63 86 A2 02 93 02 20 00 63 82 A2 04 93 02 30 00
 63 8E A2 04 73 90 05 3B 9B 02 10 00 93 92 02 02
@@ -240,7 +240,7 @@ B7 02 01 00 9B 82 F2 FF 93 92 02 01 93 82 F2 0F
 B7 02 01 00 9B 82 12 F0 93 92 02 01 93 82 F2 FF
 33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 35 3B
 B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01
-6F 00 40 00 33 63 D3 00 73 10 03 3A 6F 00 80 24
+6F 00 40 00 33 63 D3 00 73 10 03 3A 6F 00 C0 23
 93 D5 25 00 73 23 10 3A 93 02 00 00 63 8E A2 00
 93 02 10 00 63 86 A2 02 93 02 20 00 63 82 A2 04
 93 02 30 00 63 8E A2 04 73 90 45 3B 9B 02 10 00
@@ -251,7 +251,7 @@ B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01
 93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01
 73 90 75 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00
 93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 03 3A
-6F 00 40 1A 93 D5 25 00 73 23 10 3A 93 02 00 00
+6F 00 80 19 93 D5 25 00 73 23 10 3A 93 02 00 00
 63 8E A2 00 93 02 10 00 63 86 A2 02 93 02 20 00
 63 82 A2 04 93 02 30 00 63 8C A2 04 73 90 85 3B
 9B 02 10 00 93 92 02 02 93 82 02 F0 33 73 53 00
@@ -261,7 +261,7 @@ B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01
 93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01
 73 90 A5 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00
 93 96 86 01 6F 00 40 00 73 90 B5 3B 33 63 D3 00
-73 10 03 3A 6F 00 00 10 93 D5 25 00 73 23 30 3A
+73 10 03 3A 6F 00 40 0F 93 D5 25 00 73 23 30 3A
 93 02 00 00 63 8E A2 00 93 02 10 00 63 86 A2 02
 93 02 20 00 63 82 A2 04 93 02 30 00 63 8E A2 04
 73 90 C5 3B 9B 02 10 00 93 92 02 02 93 82 02 F0
@@ -271,24 +271,29 @@ B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01
 9B 82 12 F0 93 92 02 01 93 82 F2 FF 33 73 53 00
 93 96 06 01 6F 00 C0 01 73 90 F5 3B B7 02 00 01
 9B 82 F2 FF 33 73 53 00 93 96 86 01 6F 00 40 00
-33 63 D3 00 73 10 33 3A 6F 00 C0 05 93 02 00 00
-63 8A 56 04 93 02 80 00 13 F3 86 00 E3 0C 53 D2
-93 02 00 01 13 F3 06 01 E3 04 53 D2 93 02 80 01
-13 F3 06 01 E3 0C 53 D0 13 05 10 00 6F 00 80 02
-93 0E 00 00 E3 8E D8 A9 93 0E 10 00 E3 84 D8 AF
-93 0E 80 00 E3 8C D8 FB 93 0E 90 00 E3 8E D8 CB
-6F 00 40 00 F3 2E 10 34 93 8E 4E 00 73 90 1E 34
-73 00 20 30 13 0A 1A 00 73 00 20 30 93 08 00 00
-73 00 00 00 93 08 10 00 73 00 00 00 13 05 00 00
-B7 05 10 00 13 06 00 00 93 06 F0 08 93 08 80 00
-73 00 00 00 EF 00 80 01 B7 02 10 00 23 A0 02 00
-93 02 10 00 63 1E 54 02 6F 00 80 04 93 02 00 00
+33 63 D3 00 73 10 33 3A 6F 00 00 05 93 02 00 00
+63 04 57 04 93 02 80 00 E3 0E 57 D2 93 02 00 01
+E3 08 57 D2 93 02 80 01 E3 02 57 D2 13 05 10 00
+6F 00 80 02 93 0E 00 00 E3 84 D8 AB 93 0E 10 00
+E3 8A D8 AF 93 0E 80 00 E3 82 D8 FD 93 0E 90 00
+E3 84 D8 CD 6F 00 40 00 F3 2E 10 34 93 8E 4E 00
+73 90 1E 34 73 00 20 30 13 0A 1A 00 73 00 20 30
+93 08 00 00 73 00 00 00 93 08 10 00 73 00 00 00
+13 05 00 00 B7 05 10 00 13 06 00 00 93 06 F0 08
+13 07 80 00 93 08 80 00 73 00 00 00 EF 00 00 07
+B7 02 10 00 23 A0 02 00 13 00 00 00 13 00 00 00
+13 00 00 00 93 02 10 00 63 14 54 08 93 08 00 00
+73 00 00 00 6F 00 C0 08 13 05 00 00 93 05 00 00
+37 06 10 00 93 06 F0 09 93 08 80 00 73 00 00 00
+EF 00 C0 02 B7 02 10 00 23 A0 02 00 13 00 00 00
+13 00 00 00 13 00 00 00 93 02 10 00 63 12 54 04
+93 08 00 00 73 00 00 00 6F 00 80 04 93 02 00 00
 13 03 A0 00 93 03 00 00 13 0E 00 00 B3 83 53 00
 23 20 7E 00 93 83 13 00 83 23 0E 00 93 82 12 00
 13 9E 22 00 E3 94 62 FE 67 80 00 00 63 1A 30 00
 13 95 11 00 63 00 05 00 13 65 15 00 73 00 00 00
 13 05 10 00 73 00 00 00 73 00 10 00 73 10 00 C0
-@80002FB0
+@80003000
 41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64
 3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C
 3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20
diff --git a/test/priv_sec_testsuite/tests/rv64ui/test1.S b/test/priv_sec_testsuite/tests/rv64ui/test1.S
index 5974611..ba9207d 100644
--- a/test/priv_sec_testsuite/tests/rv64ui/test1.S
+++ b/test/priv_sec_testsuite/tests/rv64ui/test1.S
@@ -18,8 +18,8 @@
 # when encounter a problem during the testcase
 
 # Machine interrupt enable (MSTATUS)
-.equ MIE_ON,    0x00000088
-.equ MIE_OFF,   0xFFFFFFF7
+.equ MPIE_ON,   0x00000080
+.equ MPIE_OFF,  0xFFFFFFF7
 # Machine external interrupt enable (MIE)
 .equ MEIE_ON,   0x00000800
 .equ MEIE_OFF,  0xFFFFF7FF
@@ -41,8 +41,8 @@ ECALL_USER_MODE:
     li t4, 9
     bne a7, t4, RET_ECALL
     # Enable IRQ
-    lui t5, %hi(MIE_ON)
-    addi t5, t5, %lo(MIE_ON)
+    lui t5, %hi(MPIE_ON)
+    addi t5, t5, %lo(MPIE_ON)
     csrr t4, mstatus
     or t4, t4, t5
     csrw mstatus, t4
diff --git a/test/priv_sec_testsuite/tests/rv64ui/test2.S b/test/priv_sec_testsuite/tests/rv64ui/test2.S
index f11071c..46f3d89 100644
--- a/test/priv_sec_testsuite/tests/rv64ui/test2.S
+++ b/test/priv_sec_testsuite/tests/rv64ui/test2.S
@@ -11,7 +11,7 @@
 
 # Configure PMP and check the address matching are OK and out-of-range
 # and forbidden access are correctly handled
-# 
+#
 # x31 is the error status register to trigger the testbench status
 # when encounter a problem during the testcase
 ######################################################################
@@ -92,7 +92,7 @@ ILLEGAL_INSTRUCTION:
 ////////////////////////////////////////////
 // Erase all PMP configurations
 ////////////////////////////////////////////
-ERASE_PMP: 
+ERASE_PMP:
     csrw pmpcfg0, x0
     csrw pmpcfg1, x0
     csrw pmpcfg2, x0
@@ -119,13 +119,13 @@ ERASE_PMP:
 // Write all PMP registers to check it's accessible without limitations
 ///////////////////////////////////////////////////////////////////////
 CHECK_RW_PMP:
-    
+
     // pmpaddr0
     lui t4, %hi(PMPADDR)
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr0, t4
     csrr t5, pmpaddr0
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr0, x0
 
     // pmpaddr1
@@ -133,7 +133,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr1, t4
     csrr t5, pmpaddr1
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr1, x0
 
     // pmpaddr2
@@ -141,7 +141,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr2, t4
     csrr t5, pmpaddr2
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr2, x0
 
     // pmpaddr3
@@ -149,7 +149,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr3, t4
     csrr t5, pmpaddr3
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr3, x0
 
     // pmpaddr4
@@ -157,7 +157,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr4, t4
     csrr t5, pmpaddr4
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr4, x0
 
     // pmpaddr5
@@ -165,7 +165,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr5, t4
     csrr t5, pmpaddr5
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr5, x0
 
     // pmpaddr6
@@ -173,7 +173,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr6, t4
     csrr t5, pmpaddr6
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr6, x0
 
     // pmpaddr7
@@ -181,7 +181,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr7, t4
     csrr t5, pmpaddr7
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr7, x0
 
     // pmpaddr8
@@ -189,7 +189,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr8, t4
     csrr t5, pmpaddr8
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr8, x0
 
     // pmpaddr9
@@ -197,7 +197,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr9, t4
     csrr t5, pmpaddr9
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr9, x0
 
     // pmpaddr10
@@ -205,7 +205,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr10, t4
     csrr t5, pmpaddr10
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr10, x0
 
     // pmpaddr1
@@ -213,7 +213,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr11, t4
     csrr t5, pmpaddr11
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr11, x0
 
     // pmpaddr12
@@ -221,7 +221,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr12, t4
     csrr t5, pmpaddr12
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr12, x0
 
     // pmpaddr13
@@ -229,7 +229,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr13, t4
     csrr t5, pmpaddr13
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr13, x0
 
     // pmpaddr14
@@ -237,7 +237,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr14, t4
     csrr t5, pmpaddr14
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr14, x0
 
     // pmpaddr15
@@ -245,15 +245,15 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPADDR)
     csrw pmpaddr15, t4
     csrr t5, pmpaddr15
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpaddr15, x0
-    
+
     // pmpcfg0
     lui t4, %hi(PMPCFG)
     addi t4, t4, %lo(PMPCFG)
     csrw pmpcfg0, t4
     csrr t5, pmpcfg0
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpcfg0, x0
 
     // pmpcfg1
@@ -261,7 +261,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPCFG)
     csrw pmpcfg1, t4
     csrr t5, pmpcfg1
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpcfg1, x0
 
     // pmpcfg2
@@ -269,7 +269,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPCFG)
     csrw pmpcfg2, t4
     csrr t5, pmpcfg2
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpcfg2, x0
 
     // pmpaddr3
@@ -277,7 +277,7 @@ CHECK_RW_PMP:
     addi t4, t4, %lo(PMPCFG)
     csrw pmpcfg3, t4
     csrr t5, pmpcfg3
-    bne t4, t5, fail 
+    bne t4, t5, fail
     csrw pmpcfg3, x0
     j RET_ECALL
 
@@ -301,23 +301,21 @@ INTP_SERVICE:
 
 EXP_SERVICE:
     addi s0, s0, 1
-    j RET_ECALL
+    # j RET_ECALL
+    mret
 
 ////////////////////////////////////////////
-# Configure a NAPOT region
+# Configure a NAPOT / NA4 region
 ////////////////////////////////////////////
+SET_NA4:
 SET_NAPOT:
     j RET_ECALL
 
-////////////////////////////////////////////
-# Configure a NA4 region
-////////////////////////////////////////////
-SET_NA4:
-    j RET_ECALL
 
 ////////////////////////////////////////////
 # Configure a TOR region
 ////////////////////////////////////////////
+SET_PMP:
 SET_TOR:
     li t0, 4
     blt a0, t0, CFGREG0
@@ -332,8 +330,11 @@ SET_TOR:
     j RET_ECALL
 
 CFGREG0:
+    // prepare address, must be store by removing 2 LSBs
     srli a1, a1, 2
+    // load configuration to update
     csrr t1, pmpcfg0
+    // check pmp region to configure
     li t0, 0
     beq t0, a0, 0f
     li t0, 1
@@ -366,6 +367,7 @@ CFGREG0:
     slli a3, a3, 24
     j 4f
 4:
+    // Store config and start MPU
     or t1, t1, a3
     csrw pmpcfg0, t1
     j RET_ECALL
@@ -499,16 +501,13 @@ CFGREG3:
 //////////////////////////////////////////////////
 PMP_SERVICE:
     li t0, OFF
-    beq a3, t0, RET_ECALL
+    beq a4, t0, RET_ECALL
     li t0, TOR
-    andi t1, a3, TOR
-    beq t1, t0, SET_TOR
+    beq a4, t0, SET_TOR
     li t0, NA4
-    andi t1, a3, NA4
-    beq t1, t0, SET_NA4
+    beq a4, t0, SET_NA4
     li t0, NAPOT
-    andi t1, a3, NA4
-    beq t1, t0, SET_NAPOT
+    beq a4, t0, SET_NAPOT
     // region type unsupported, returns an error
     li a0, 1
     j RET_ECALL
@@ -583,7 +582,8 @@ TEST3_1TOR:
     li a0, 0       // pmp number
     li a1, S1MB    // base address
     li a2, 0       // size
-    li a3, TOR_RWX // type
+    li a3, TOR_RWX // permissions
+    li a4, TOR     // type
     li a7, 8
     ecall
 // Run some duties into the region
@@ -595,16 +595,55 @@ TEST3_OUT_OF_BOUND:
     # lui t0, %hi(S1MB)
     # addi t0, t0, %lo(S1MB)
     sw x0, 0(t0) // raise an exception, which will increment s0
+    # bunch of nop to wait for exception handling
+    nop
+    nop
+    nop
+    // Check the exception has been handled correctly
+    li t0, 1
+    bne s0, t0, fail
+
+TEST3_TEARDOWN:
+    li a7, 0
+    ecall
+    # j pass
+
+// NAPOT region - 1MB RWX
+TEST4_1NAPOT:
+    // Configure the region
+    li a0, 0         // pmp number
+    li a1, 0         // base address
+    li a2, S1MB      // size
+    li a3, NAPOT_RWX // permissions
+    li a3, NAPOT     // type
+    li a7, 8
+    ecall
+// Run some duties into the region
+TEST4_RW_ACCESS:
+    call LD_ST_ARITH
+// Try to access outside the memory region
+TEST4_OUT_OF_BOUND:
+    li t0, S1MB
+    # lui t0, %hi(S1MB)
+    # addi t0, t0, %lo(S1MB)
+    sw x0, 0(t0) // raise an exception, which will increment s0
+    # bunch of nop to wait for exception handling
+    nop
+    nop
+    nop
     // Check the exception has been handled correctly
-    // TODO: insert NOP like to be sure we catch the exp
     li t0, 1
     bne s0, t0, fail
 
-TEST_R_ALLOWED:
-TEST_W_ALLOWED:
+TEST4_TEARDOWN:
+    li a7, 0
+    ecall
     j pass
 
+
+//////////////////////////////////////////////////////
 // Stupid loop to access the memory over a small range
+//////////////////////////////////////////////////////
 LD_ST_ARITH:
     li t0, 0
     li t1, 10
@@ -619,9 +658,10 @@ LD_ST_ARITH:
     slli t3, t0, 2
     bne t0, t1, 1b
     ret
+//////////////////////////////////////////////////////
 
 
-TEST_PASSFAIL 
+TEST_PASSFAIL
 
 RVTEST_CODE_END