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Add NAPOT region test
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@dpretet
dpretet committed Oct 30, 2023
1 parent 79d8c7a commit a12eeeb
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Showing 8 changed files with 416 additions and 360 deletions.
4 changes: 2 additions & 2 deletions rtl/friscv_control.sv
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Expand Up @@ -1220,9 +1220,9 @@ module friscv_control
assign inst_dec_error = dec_error & (cfsm==FETCH) & inst_ready;

// Is fetching instruction on forbidden memory region
assign inst_access_fault = (!mpu_allow[`PMA_X] | !mpu_allow[`PMA_R]) &
assign inst_access_fault = (!mpu_allow[`ALW_X] | !mpu_allow[`ALW_R]) &
(priv_mode == `UMODE ||
priv_mode==`MMODE && mpu_allow[3] /*locked*/);
priv_mode==`MMODE && mpu_allow[`ALW_L]);

//////////////////////////////////////////////////////////////////////
// Stores the incoming excpetions from processing. Can't handle
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5 changes: 5 additions & 0 deletions rtl/friscv_h.sv
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Expand Up @@ -128,6 +128,11 @@
`define PMA_A 3 // 4:3
`define PMA_L 7

`define ALW_R 0
`define ALW_W 1
`define ALW_X 2
`define ALW_L 3

//////////////////////////////////////////////////////////////////
// Instruction bus feeding ALUs
//////////////////////////////////////////////////////////////////
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16 changes: 8 additions & 8 deletions rtl/friscv_memfy.sv
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Expand Up @@ -435,7 +435,7 @@ module friscv_memfy
opcode_r <= opcode;

// STORE
if (opcode==`STORE && mpu_allow[`PMA_W] && !store_misaligned) begin
if (opcode==`STORE && mpu_allow[`ALW_W] && !store_misaligned) begin

if (waiting_rd_cpl || arvalid) begin
state <= WAIT;
Expand All @@ -460,7 +460,7 @@ module friscv_memfy
arvalid <= 1'b0;

// LOAD
end else if (opcode==`LOAD && mpu_allow[`PMA_R] && !load_misaligned) begin
end else if (opcode==`LOAD && mpu_allow[`ALW_R] && !load_misaligned) begin
if (waiting_wr_cpl || awvalid) begin
state <= WAIT;
arvalid <= 1'b0;
Expand Down Expand Up @@ -637,14 +637,14 @@ module friscv_memfy
end else begin

// Write xfers tracker
if (memfy_valid && memfy_ready && opcode==`STORE && !bvalid && !max_wr_or) begin
if (memfy_valid && memfy_ready && opcode==`STORE && !bvalid && !max_wr_or && mpu_allow[`ALW_W]) begin
wr_or_cnt <= wr_or_cnt + 1'b1;
end else if (!(memfy_valid && memfy_ready && opcode==`STORE) && bvalid && bready && wr_or_cnt!={MAX_OR_W{1'b0}}) begin
wr_or_cnt <= wr_or_cnt - 1'b1;
end

// Read xfers tracker
if (memfy_valid && memfy_ready && opcode==`LOAD && !memfy_rd_wr && !max_rd_or) begin
if (memfy_valid && memfy_ready && opcode==`LOAD && !memfy_rd_wr && !max_rd_or && mpu_allow[`ALW_R]) begin
rd_or_cnt <= rd_or_cnt + 1'b1;
end else if (!(memfy_valid && memfy_ready && opcode==`LOAD) && memfy_rd_wr && rd_or_cnt!={MAX_OR_W{1'b0}}) begin
rd_or_cnt <= rd_or_cnt - 1'b1;
Expand Down Expand Up @@ -769,7 +769,7 @@ module friscv_memfy
------------------------------------------------------------------------------------------------
ACACHE | AWCACHE | ARCACHE
[3] [2] [1] [0] | |
[3] [2] [1] [0] | |
------------------------------------------------------------------------------------------------
0 0 0 0 | Device Non-cacheable Non-bufferable | Device Non-cacheable Non-bufferable
0 0 0 1 | Device Non-cacheable Bufferable | Device Non-cacheable Bufferable
Expand All @@ -781,7 +781,7 @@ module friscv_memfy
| Write-Through Read-Allocate |
------------------------------------------------------------------------------------------------
0 1 1 1 | Write-Back No-Allocate | Write-Back Read-Allocate
| Write-Back Read-Allocate |
| Write-Back Read-Allocate |
------------------------------------------------------------------------------------------------
1 0 1 0 | Write-Through Write-Allocate | Write-Through No-Allocate
| | Write-Through Write-Allocate
Expand Down Expand Up @@ -843,10 +843,10 @@ module friscv_memfy
1'b0 ;

// Load access outside am allowed region
assign load_access_fault = (opcode==`LOAD) & !mpu_allow[`PMA_R] & check_access & active_access;
assign load_access_fault = (opcode==`LOAD) & !mpu_allow[`ALW_R] & check_access & active_access;

// Store access outside am allowed region
assign store_access_fault = (opcode==`STORE) & !mpu_allow[`PMA_W] & check_access & active_access;
assign store_access_fault = (opcode==`STORE) & !mpu_allow[`ALW_W] & check_access & active_access;


// Shared bus routing back to control unit
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170 changes: 87 additions & 83 deletions test/priv_sec_testsuite/tests/rv32ui-p-test2.v
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