From ce407a0723148ca5c1f6f0aa76e0dbf656613609 Mon Sep 17 00:00:00 2001 From: Damien Pretet Date: Sun, 29 Oct 2023 20:03:59 +0100 Subject: [PATCH] Change: testbench runs now randomly external IRQ. Add also software IRQ --- doc/project_mgt_sw.md | 1 + rtl/friscv_csr.sv | 41 ++++- rtl/friscv_pulser.sv | 40 ++++ syn/friscv_rv32i.ys | 1 + test/common/files.f | 1 + test/common/friscv_testbench.sv | 77 +++++--- .../priv_sec_testsuite/tests/rv32ui-p-test2.v | 166 ++++++++--------- .../priv_sec_testsuite/tests/rv32ui-v-test2.v | 174 +++++++++--------- .../priv_sec_testsuite/tests/rv64ui-p-test2.v | 170 ++++++++--------- .../priv_sec_testsuite/tests/rv64ui-v-test2.v | 160 ++++++++-------- 10 files changed, 463 insertions(+), 368 deletions(-) create mode 100644 rtl/friscv_pulser.sv diff --git a/doc/project_mgt_sw.md b/doc/project_mgt_sw.md index ad6a702..294a5b1 100644 --- a/doc/project_mgt_sw.md +++ b/doc/project_mgt_sw.md @@ -70,6 +70,7 @@ Minimalistic Unix - [ ] Support Linux / FreeBSD / NetBSD - https://github.com/cnlohr/mini-rv32ima - https://popovicu.com/posts/789-kb-linux-without-mmu-riscv/ + - https://popovicu.com/posts/making-a-micro-linux-distro/ - [ ] Code Pong with AI for auto game - [ ] Run Doom: https://www.youtube.com/watch?v=uZMNK17VCMU&list=WL&index=1&t=2s - [ ] Code the game of life diff --git a/rtl/friscv_csr.sv b/rtl/friscv_csr.sv index 7baf40f..895046e 100644 --- a/rtl/friscv_csr.sv +++ b/rtl/friscv_csr.sv @@ -122,6 +122,10 @@ module friscv_csr logic timer_irq_sync; logic sw_irq_sync; + logic ext_irq_pulse; + logic timer_irq_pulse; + logic sw_irq_pulse; + // External source of CSRs logic ctrl_mepc_wr; logic [XLEN -1:0] ctrl_mepc; @@ -407,7 +411,8 @@ module friscv_csr assign ready = 1'b1; ////////////////////////////////////////////////////////////////////////// - // Synchronize the IRQs in the core's clock domain + // Synchronize the IRQs in the core's clock domain and transoform them + // into a single pulse ////////////////////////////////////////////////////////////////////////// friscv_bit_sync @@ -449,6 +454,32 @@ module friscv_csr .bit_o (sw_irq_sync) ); + friscv_pulser eirq_pulse + ( + .aclk (aclk), + .aresetn (aresetn), + .srst (srst), + .intp (ext_irq_sync), + .pulse (ext_irq_pulse) + ); + + friscv_pulser tirq_pulse + ( + .aclk (aclk), + .aresetn (aresetn), + .srst (srst), + .intp (timer_irq_sync), + .pulse (timer_irq_pulse) + ); + + friscv_pulser sirq_pulse + ( + .aclk (aclk), + .aresetn (aresetn), + .srst (srst), + .intp (sw_irq_sync), + .pulse (sw_irq_pulse) + ); ////////////////////////////////////////////////////////////////////////// // ISA register Write Stage @@ -811,21 +842,21 @@ module friscv_csr end else if (srst) begin mip <= {XLEN{1'b0}}; end else begin - if (ext_irq_sync || timer_irq_sync || sw_irq_sync || ctrl_clr_meip) begin + if (ext_irq_pulse || timer_irq_pulse || sw_irq_pulse || ctrl_clr_meip) begin // external interrupt enable && external interrupt pin asserted - if ( ext_irq_sync) begin + if (ext_irq_pulse) begin mip[11] <= 1'b1; end else if (ctrl_clr_meip) begin mip[11] <= 1'b0; end // software interrupt enable && software interrupt pin asserted - if (mie[3] && sw_irq_sync) begin + if (sw_irq_pulse) begin mip[3] <= 1'b1; end else begin mip[3] <= 1'b0; end // timer interrupt enable && timer interrupt pin asserted - if (mie[7] && timer_irq_sync) begin + if (timer_irq_pulse) begin mip[7] <= 1'b1; end else begin mip[7] <= 1'b0; diff --git a/rtl/friscv_pulser.sv b/rtl/friscv_pulser.sv new file mode 100644 index 0000000..ac76fe1 --- /dev/null +++ b/rtl/friscv_pulser.sv @@ -0,0 +1,40 @@ +// distributed under the mit license +// https://opensource.org/licenses/mit-license.php + +`timescale 1 ns / 1 ps +`default_nettype none + +/* +* Used to transform a signal like an interrupt which spans over several +* clock cycles into a single pulse. +*/ +module friscv_pulser + + ( + input wire aclk, + input wire aresetn, + input wire srst, + input wire intp, + output logic pulse + ); + + logic intp_reg; + + always @ (posedge aclk or negedge aresetn) begin + if (!aresetn) begin + intp_reg <= 1'b0; + pulse <= 1'b0; + end else if (srst) begin + intp_reg <= 1'b0; + pulse <= 1'b0; + end else begin + intp_reg <= intp; + pulse <= intp & !intp_reg; + end + end + + +endmodule + +`resetall + diff --git a/syn/friscv_rv32i.ys b/syn/friscv_rv32i.ys index bf74866..860b87e 100644 --- a/syn/friscv_rv32i.ys +++ b/syn/friscv_rv32i.ys @@ -30,6 +30,7 @@ read -sv2012 ../rtl/friscv_rv32i_core.sv read -sv2012 ../rtl/friscv_axi_or_tracker.sv read -sv2012 ../rtl/friscv_mpu.sv read -sv2012 ../rtl/friscv_pmp_region.sv +read -sv2012 ../rtl/friscv_pulser.sv # synthsize the core synth -top friscv_rv32i_core diff --git a/test/common/files.f b/test/common/files.f index b2f7a17..cbe792c 100644 --- a/test/common/files.f +++ b/test/common/files.f @@ -10,6 +10,7 @@ ../../rtl/friscv_memfy.sv ../../rtl/friscv_registers.sv ../../rtl/friscv_csr.sv +../../rtl/friscv_pulser.sv ../../rtl/friscv_scfifo.sv ../../rtl/friscv_ram.sv ../../rtl/friscv_rambe.sv diff --git a/test/common/friscv_testbench.sv b/test/common/friscv_testbench.sv index 8946d80..4929bf7 100644 --- a/test/common/friscv_testbench.sv +++ b/test/common/friscv_testbench.sv @@ -141,7 +141,7 @@ module friscv_testbench( parameter PMPADDR13_INIT = `PMPADDR13_INIT; parameter PMPADDR14_INIT = `PMPADDR14_INIT; parameter PMPADDR15_INIT = `PMPADDR15_INIT; - `else + `else // PMP / PMA supported // = 0, no PMP // = 1, PMP available but fixed at boot time @@ -215,7 +215,7 @@ module friscv_testbench( // Minimum program counter value a test needs to reach parameter MIN_PC = `MIN_PC; `ifdef WFI_TW - // Timeout applied for WFI + // Timeout applied for WFI parameter WFI_TW = `WFI_TW; `else parameter WFI_TW = 0; @@ -329,30 +329,53 @@ module friscv_testbench( assign imem_bready = 1'b1; initial ext_irq = 1'b0; + initial sw_irq = 1'b0; `ifdef GEN_EIRQ - generate - if (`GEN_EIRQ>0) begin - always @ (posedge aclk or negedge aresetn) begin - integer cnt; - if (!aresetn) begin - ext_irq <= 1'b0; - cnt <= 0; - end else if (srst) begin - ext_irq <= 1'b0; - cnt <= 0; + + generate if (`GEN_EIRQ>0) begin + + integer cnt; + logic [31:0] xirq_lfsr; + logic [7 :0] irq_reset; + logic [3 :0] next_eirq; + logic [3 :0] next_sirq; + + lfsr32 + #( + .KEY ('1) + ) + irq_lsfr + ( + .aclk (aclk), + .aresetn (aresetn), + .srst (srst), + .en (1'b1), + .lfsr (xirq_lfsr) + ); + + always @ (posedge aclk or negedge aresetn) begin + if (!aresetn) begin + cnt <= 0; + end else if (srst) begin + cnt <= 0; + end else begin + if (cnt == irq_reset) begin + irq_reset <= xirq_lfsr[7:0]; + next_eirq <= xirq_lfsr[8+:4]; + next_sirq <= xirq_lfsr[16+:4]; + cnt <= 'h0; end else begin - if (cnt == 100) begin - cnt <= 0; - ext_irq <= 1'b1; - end else begin - cnt <= cnt + 1; - ext_irq <= 1'b0; - end + cnt <= cnt + 1; end end end - endgenerate + + assign ext_irq = (cnt >= (irq_reset-next_eirq)); + assign sw_irq = (cnt >= (irq_reset-next_sirq)); + + end + endgenerate `endif // Run the testbench by using only the CPU core @@ -361,7 +384,6 @@ module friscv_testbench( if (TB_CHOICE=="CORE") begin assign timer_irq = 1'b0; - assign sw_irq = 1'b0; friscv_rv32i_core #( @@ -378,7 +400,7 @@ module friscv_testbench( .SUPERVISOR_MODE (SUPERVISOR_MODE), .USER_MODE (USER_MODE), .PROCESSING_BUS_PIPELINE (PROCESSING_BUS_PIPELINE), - .WFI_TW (WFI_TW), + .WFI_TW (WFI_TW), .AXI_ADDR_W (AXI_ADDR_W), .AXI_ID_W (AXI_ID_W), .AXI_IMEM_W (AXI_IMEM_W), @@ -463,9 +485,9 @@ module friscv_testbench( axi4l_ram #( `ifdef RAM_MODE_PERF - .MODE ("performance"), + .MODE ("performance"), `else - .MODE ("compliance"), + .MODE ("compliance"), `endif .INIT ("test.v"), .AXI_ADDR_W (AXI_ADDR_W), @@ -530,7 +552,6 @@ module friscv_testbench( end else if (TB_CHOICE=="PLATFORM") begin assign timer_irq = 1'b0; - assign sw_irq = 1'b0; assign rtc = aclk; // Can't use interactive mode with Verilator @@ -589,7 +610,7 @@ module friscv_testbench( .SUPERVISOR_MODE (SUPERVISOR_MODE), .USER_MODE (USER_MODE), .PROCESSING_BUS_PIPELINE (PROCESSING_BUS_PIPELINE), - .WFI_TW (WFI_TW), + .WFI_TW (WFI_TW), .AXI_ADDR_W (AXI_ADDR_W), .AXI_ID_W (AXI_ID_W), .AXI_DATA_W (AXI_DATA_W), @@ -667,9 +688,9 @@ module friscv_testbench( axi4l_ram #( `ifdef RAM_MODE_PERF - .MODE ("performance"), + .MODE ("performance"), `else - .MODE ("compliance"), + .MODE ("compliance"), `endif .INIT ("test.v"), .AXI_ADDR_W (AXI_ADDR_W), diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v index 6da1bf4..7cfcfd9 100755 --- a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v +++ b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v @@ -1,9 +1,9 @@ @00010000 -6F 00 80 08 73 2F 20 34 93 0E 80 00 63 0A DF 6B +6F 00 80 08 73 2F 20 34 93 0E 80 00 63 08 DF 6B 93 0E 90 00 63 02 DF 1B 93 0E B0 00 63 02 DF 1B 93 0E 20 00 63 00 DF 1B B7 0E 00 80 93 8E BE 00 -63 02 DF 6D B7 0E 00 80 93 8E 3E 00 63 0C DF 6B -B7 0E 00 80 93 8E 7E 00 63 06 DF 6B 93 0E 50 00 +63 00 DF 6D B7 0E 00 80 93 8E 3E 00 63 0A DF 6B +B7 0E 00 80 93 8E 7E 00 63 04 DF 6B 93 0E 50 00 63 00 DF 3F 93 0E 70 00 63 0C DF 3D 93 0E 10 00 63 08 DF 3D 13 0F 00 00 63 04 0F 00 67 00 0F 00 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 @@ -26,108 +26,108 @@ B7 0E 00 80 93 8E 7E 00 63 06 DF 6B 93 0E 50 00 73 00 10 00 93 02 00 00 63 8A 02 00 73 90 52 10 B7 B2 00 00 93 82 92 10 73 90 22 30 73 50 00 30 97 02 00 00 93 82 42 01 73 90 12 34 73 25 40 F1 -73 00 20 30 6F 00 80 54 93 8F 1F 00 73 00 10 00 -6F 00 40 52 93 8F 1F 00 73 00 10 00 73 10 00 3A +73 00 20 30 6F 00 40 54 93 8F 1F 00 73 00 10 00 +6F 00 00 52 93 8F 1F 00 73 00 10 00 73 10 00 3A 73 10 10 3A 73 10 20 3A 73 10 30 3A 73 10 00 3B 73 10 10 3B 73 10 20 3B 73 10 30 3B 73 10 40 3B 73 10 50 3B 73 10 60 3B 73 10 70 3B 73 10 80 3B 73 10 90 3B 73 10 A0 3B 73 10 B0 3B 73 10 C0 3B -73 10 D0 3B 73 10 E0 3B 73 10 F0 3B 6F 00 80 4C +73 10 D0 3B 73 10 E0 3B 73 10 F0 3B 6F 00 40 4C B7 0E 00 00 93 8E FE FF 73 90 0E 3B 73 2F 00 3B -63 9E EE 59 73 10 00 3B B7 0E 00 00 93 8E FE FF -73 90 1E 3B 73 2F 10 3B 63 92 EE 59 73 10 10 3B +63 9C EE 59 73 10 00 3B B7 0E 00 00 93 8E FE FF +73 90 1E 3B 73 2F 10 3B 63 90 EE 59 73 10 10 3B B7 0E 00 00 93 8E FE FF 73 90 2E 3B 73 2F 20 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63 82 A2 04 +73 90 C5 3B 93 02 00 F0 33 73 53 00 6F 00 C0 04 +73 90 D5 3B B7 02 FF FF 93 82 F2 0F 33 73 53 00 +93 96 86 00 6F 00 40 03 73 90 E5 3B B7 02 01 FF +93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 +73 90 F5 3B B7 02 00 01 93 82 F2 FF 33 73 53 00 +93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 33 3A +6F 00 00 05 93 02 00 00 63 04 57 04 93 02 80 00 +E3 0E 57 D8 93 02 00 01 E3 08 57 D8 93 02 80 01 +E3 04 57 D8 13 05 10 00 6F 00 80 02 93 0E 00 00 +E3 86 D8 B1 93 0E 10 00 E3 8C D8 B5 93 0E 80 00 +E3 82 D8 FD 93 0E 90 00 E3 86 D8 D3 6F 00 40 00 +F3 2E 10 34 93 8E 4E 00 73 90 1E 34 73 00 20 30 +13 0A 1A 00 73 00 20 30 93 08 00 00 73 00 00 00 +93 08 10 00 73 00 00 00 13 05 00 00 B7 05 10 00 +13 06 00 00 93 06 F0 08 13 07 80 00 93 08 80 00 +73 00 00 00 EF 00 00 07 B7 02 10 00 23 A0 02 00 +13 00 00 00 13 00 00 00 13 00 00 00 93 02 10 00 +63 14 54 08 93 08 00 00 73 00 00 00 13 05 00 00 +93 05 00 00 37 06 10 00 93 06 F0 09 93 06 80 01 +93 08 80 00 73 00 00 00 EF 00 C0 02 B7 02 10 00 23 A0 02 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