From fcf3db20cd83bb77cec814f06f6c9623b9331f29 Mon Sep 17 00:00:00 2001 From: Damien Pretet Date: Mon, 20 Nov 2023 20:56:32 +0100 Subject: [PATCH] Fix: control unit was able to support instruction access fault Fix: memfy blocked if no U-MODE supported New: testcase to check access fault --- doc/TODO.md | 16 +- doc/project_mgt_hw.md | 18 +- rtl/friscv_control.sv | 9 +- rtl/friscv_memfy.sv | 266 +++------- rtl/friscv_memfy_h.sv | 166 ++++++ rtl/friscv_processing.sv | 12 + rtl/friscv_rv32i_core.sv | 4 + test/c_testsuite/tests/extern_vars.v | 17 +- .../tests/extern_vars/extern_vars.v | 17 +- test/c_testsuite/tests/heap.v | 501 +++++++++--------- test/c_testsuite/tests/heap/heap.v | 501 +++++++++--------- test/common/debug_platform_verilator.gtkw | 2 +- test/priv_sec_testsuite/tests/env/pmp.S | 1 + .../tests/env/pmp_service.S | 103 +++- .../priv_sec_testsuite/tests/rv32ui-p-test2.v | 103 ++-- .../priv_sec_testsuite/tests/rv32ui-p-test3.v | 103 ++-- .../priv_sec_testsuite/tests/rv32ui-p-test4.v | 191 ++++--- .../priv_sec_testsuite/tests/rv32ui-v-test2.v | 157 +++--- .../priv_sec_testsuite/tests/rv32ui-v-test3.v | 157 +++--- .../priv_sec_testsuite/tests/rv32ui-v-test4.v | 199 ++++--- .../priv_sec_testsuite/tests/rv64ui-p-test2.v | 49 +- .../priv_sec_testsuite/tests/rv64ui-p-test3.v | 49 +- .../priv_sec_testsuite/tests/rv64ui-p-test4.v | 135 +++-- .../priv_sec_testsuite/tests/rv64ui-v-test2.v | 166 +++--- .../priv_sec_testsuite/tests/rv64ui-v-test3.v | 148 +++--- .../priv_sec_testsuite/tests/rv64ui-v-test4.v | 145 ++--- test/priv_sec_testsuite/tests/rv64ui/test4.S | 150 ++++-- 27 files changed, 1922 insertions(+), 1463 deletions(-) create mode 100644 rtl/friscv_memfy_h.sv diff --git a/doc/TODO.md b/doc/TODO.md index a5c588c..5a5e8df 100644 --- a/doc/TODO.md +++ b/doc/TODO.md @@ -30,11 +30,6 @@ # Testcases -Traps -- [ ] Nested interrupts -- [ ] Vector interrupts -- [ ] Interrupts mixed over exceptions - - [X] Faire varier la periode de l'EIRQ U-mode @@ -46,8 +41,8 @@ Traps - [X] Do something within a loop with interrupt enabled, data needs to be OK - [X] WFI in u-mode, interrupt enabled, trapped in m-mode - [X] WFI in u-mode, interrupt disabled, NOP +- [X] Test des exception load/store misaligned - [ ] Add test for vector table -- [ ] Test des exception load/store misaligned - [ ] Test MSTATUS.TW MPU: @@ -58,11 +53,10 @@ MPU: - [X] execute instruction outside allowed regions (U-mode) - [X] write data in U-mode - [X] read data in U-mode - - [ ] read data in M-mode with MPRV=1 + MPP w/ U-mode - - [ ] write data in M-mode with MPRV=1 + MPP w/ U-mode - - [ ] execute in M-mode without X + locked region -- [ ] locked access to change configuration -- [ ] region's permissions overlap + - [X] read data in M-mode with MPRV=1 + MPP=U-mode + - [X] write data in M-mode with MPRV=1 + MPP=U-mode + - [X] execute in M-mode without X + locked region +- [X] locked access to change configuration Final: - Pass compliance with U-mode diff --git a/doc/project_mgt_hw.md b/doc/project_mgt_hw.md index d773ed1..e463c50 100644 --- a/doc/project_mgt_hw.md +++ b/doc/project_mgt_hw.md @@ -2,11 +2,16 @@ - [ ] v1.6.0: Kernel-capable Hart - [X] Supporter des set de config du core en test bench. - - [-] Support U-mode - - [-] Support PMP/PMA - - [ ] Atomic operations for single core - - [ ] AXI Exception management with a CLIC - - maange all traps into it? + - [X] Support U-mode + - [X] Support PMP/PMA + - [ ] Atomic operations + - stage to execute the instruction, controlling ldst Stages + - memfy exposes two interfaces for requests. + - memfy drives back response along register write channel + - support exclusive access in cache, don't substitute tag, so support single access + - support exclusive access in memory, track the ID with a LUT + - [ ] Advanced Interrupt controller + - [ ] AXI Exception management - [ ] Zc extension - [ ] https://github.com/eembc/coremark @@ -70,6 +75,9 @@ Any new features should be carefully study to ensure a proper exception and inte - [ ] Analogue pocket - [C] Cloud - [ ] Add registers to configure the core in platform (use custom CSR) + - Caches + - Interconnect + - processing: scheduling, hazard detection - [ ] Support CLIC controller - [ ] Random peripheral - [ ] UART: Support 9/10 bits & parity diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv index adac882..8b18f50 100644 --- a/rtl/friscv_control.sv +++ b/rtl/friscv_control.sv @@ -227,6 +227,7 @@ module friscv_control logic ecall_umode; logic ecall_mmode; logic [2 -1:0] priv_mode; + logic [2 -1:0] mpp; logic load_access_fault; logic store_access_fault; @@ -359,6 +360,12 @@ module friscv_control mstatus_wr, mstatus, mepc_wr, mepc}; + generate if (USER_MODE) begin: MPP_UMODE + assign mpp = sb_mstatus[11+:2]; + end else begin: MPP_MMODE + assign mpp = `MMODE; + end + endgenerate /////////////////////////////////////////////////////////////////////////// // Input stage @@ -501,7 +508,7 @@ module friscv_control assign proc_instbus[`INST +: `INST_W ] = instruction; assign proc_instbus[`PC +: `PC_W ] = pc_reg; assign proc_instbus[`PRIV +: `PRIV_W ] = priv_mode; - assign proc_instbus[`MPP +: `PRIV_W ] = sb_mstatus[11+:2]; + assign proc_instbus[`MPP +: `PRIV_W ] = mpp; assign proc_instbus[`MPRV ] = sb_mstatus[17]; assign csr_instbus = proc_instbus; diff --git a/rtl/friscv_memfy.sv b/rtl/friscv_memfy.sv index d24aed2..346e205 100644 --- a/rtl/friscv_memfy.sv +++ b/rtl/friscv_memfy.sv @@ -55,6 +55,14 @@ module friscv_memfy parameter MAX_OR = 8, // Add pipeline on Rd write stage parameter SYNC_RD_WR = 0, + // Support hypervisor mode + parameter HYPERVISOR_MODE = 0, + // Support supervisor mode + parameter SUPERVISOR_MODE = 0, + // Support user mode + parameter USER_MODE = 0, + // PMP / PMA supported + parameter MPU_SUPPORT = 0, // IO regions for direct read/write access parameter IO_MAP_NB = 1, // IO address ranges, organized by memory region as END-ADDR_START-ADDR: @@ -118,166 +126,8 @@ module friscv_memfy input wire [AXI_DATA_W -1:0] rdata ); - - /////////////////////////////////////////////////////////////////////////// - // - // AXI Alignment Functions - // - /////////////////////////////////////////////////////////////////////////// - - - /////////////////////////////////////////////////////////////////////////// - // Align the read memory value to write in RD. Right shift the data. - // Args: - // - data: the word to align - // - offset: the shift to apply, ADDR's LSBs - // Returns: - // - data aligned ready to store - /////////////////////////////////////////////////////////////////////////// - function automatic logic [XLEN-1:0] get_axi_data( - - input logic [XLEN -1:0] data, - input logic [2 -1:0] offset - ); - if (offset==2'b00) get_axi_data = data; - if (offset==2'b01) get_axi_data = {data[XLEN- 8-1:0], data[XLEN-1-:8]}; - if (offset==2'b10) get_axi_data = {data[XLEN-16-1:0], data[XLEN-1-:16]}; - if (offset==2'b11) get_axi_data = {data[XLEN-24-1:0], data[XLEN-1-:24]}; - - endfunction - - - /////////////////////////////////////////////////////////////////////////// - // Align the write strobes to write in memory - // Args: - // - strb: the strobes to align - // - offset: the shift to apply, ADDR's LSBs - // Returns: - // - strobes aligned ready to store - /////////////////////////////////////////////////////////////////////////// - function automatic logic [XLEN/8-1:0] aligned_axi_strb( - - input logic [XLEN/8-1:0] strb, - input logic [2 -1:0] offset - ); - if (offset==2'b00) aligned_axi_strb = strb; - if (offset==2'b01) aligned_axi_strb = {strb[XLEN/8-2:0], 1'b0}; - if (offset==2'b10) aligned_axi_strb = {strb[XLEN/8-3:0], 2'b0}; - if (offset==2'b11) aligned_axi_strb = {strb[XLEN/8-4:0], 3'b0}; - - endfunction - - /////////////////////////////////////////////////////////////////////////// - // Create the strobe vector to aply during a STORE instruction - // Args: - // - funct3: opcode's funct3 identifier - // - offset: the shift to apply, ADDR's LSBs - // Returns: - // - the ready to use strobes - /////////////////////////////////////////////////////////////////////////// - function automatic logic [XLEN/8-1:0] get_axi_strb( - - input logic [2:0] funct3, - input logic [1:0] offset - ); - if (funct3==`SB) get_axi_strb = aligned_axi_strb({{(XLEN/8-1){1'b0}},1'b1}, offset); - if (funct3==`SH) get_axi_strb = aligned_axi_strb({{(XLEN/8-2){1'b0}},2'b11}, offset); - if (funct3==`SW) get_axi_strb = aligned_axi_strb({(XLEN/8){1'b1}}, offset); - - endfunction - - - /////////////////////////////////////////////////////////////////////////// - // - // ISA registers Alignment functions - // - /////////////////////////////////////////////////////////////////////////// - - - /////////////////////////////////////////////////////////////////////////// - // Align the read memory value to write in RD. Right shift the data. - // Args: - // - data: the word to align - // - offset: the shift to apply, ADDR's LSBs - // Returns: - // - data aligned ready to store - /////////////////////////////////////////////////////////////////////////// - function automatic logic [XLEN-1:0] get_aligned_rd_data( - - input logic [XLEN -1:0] data, - input logic [2 -1:0] offset - ); - if (offset==2'b00) get_aligned_rd_data = data; - if (offset==2'b01) get_aligned_rd_data = {data[XLEN-24-1:0], data[XLEN-1:8]}; - if (offset==2'b10) get_aligned_rd_data = {data[XLEN-16-1:0], data[XLEN-1:16]}; - if (offset==2'b11) get_aligned_rd_data = {data[XLEN- 8-1:0], data[XLEN-1:24]}; - - endfunction - - /////////////////////////////////////////////////////////////////////////// - // Create the strobe vector to apply during a RD write - // Args: - // - funct3: opcode's funct3 identifier - // - rdata: the word to align - // - offset: the shift to apply, ADDR's LSBs - // Returns: - // - the ready to use strobes - /////////////////////////////////////////////////////////////////////////// - function automatic logic [XLEN-1:0] get_rd_val( - - input logic [3 -1:0] funct3, - input logic [XLEN-1:0] data, - input logic [2 -1:0] offset - ); - logic [XLEN-1:0] data_aligned; - - data_aligned = get_aligned_rd_data(data, offset); - - if (funct3==`LB) get_rd_val = {{24{data_aligned[7]}}, data_aligned[7:0]}; - if (funct3==`LBU) get_rd_val = {{24{1'b0}}, data_aligned[7:0]}; - if (funct3==`LH) get_rd_val = {{16{data_aligned[15]}}, data_aligned[15:0]}; - if (funct3==`LHU) get_rd_val = {{16{1'b0}}, data_aligned[15:0]}; - if (funct3==`LW) get_rd_val = data_aligned; - - endfunction - - /////////////////////////////////////////////////////////////////////////// - // Create the strobe vector to apply during a RD write - // Args: - // - funct3: opcode's funct3 identifier - // - phase: first (0) or second (1) phase of the STORE request - // Returns: - // - the ready to use strobes - /////////////////////////////////////////////////////////////////////////// - function automatic logic [XLEN/8-1:0] get_rd_strb( - - input logic [3 -1:0] funct3, - input logic [2 -1:0] offset - ); - if (funct3==`LB || funct3==`LBU) begin - get_rd_strb = {(XLEN/8){1'b1}}; - end - if (funct3==`LH || funct3==`LHU) begin - if (offset==2'h3) begin - get_rd_strb = {{(XLEN/8-1){1'b0}},1'b1}; - end else begin - get_rd_strb = {(XLEN/8){1'b1}}; - end - end - if (funct3==`LW) begin - if (offset==2'h0) begin - get_rd_strb = {(XLEN/8){1'b1}}; - end else if (offset==2'h1) begin - get_rd_strb = {{(XLEN/8-3){1'b0}},3'b111}; - end else if (offset==2'h2) begin - get_rd_strb = {{(XLEN/8-2){1'b0}},2'b11}; - end else if (offset==2'h3) begin - get_rd_strb = {{(XLEN/8-1){1'b0}},1'b1}; - end - end - - endfunction - + // All functions necessary for access alignment + `include "friscv_memfy_h.sv" /////////////////////////////////////////////////////////////////////////// // @@ -287,6 +137,7 @@ module friscv_memfy localparam MAX_OR_W = $clog2(MAX_OR) + 1; + // instruction bus logic signed [XLEN -1:0] addr; logic [`OPCODE_W -1:0] opcode; logic [`FUNCT3_W -1:0] funct3; @@ -303,34 +154,44 @@ module friscv_memfy logic [`PRIV_W -1:0] mpp; logic mprv; - logic load_misaligned; - logic store_misaligned; - logic check_access; - logic load_access_fault; - logic store_access_fault; - - logic active_access; - - logic memfy_ready_fsm; - logic stall_bus; - + // read response channel logic push_rd_or; logic rd_or_full; logic rd_or_empty; logic [2 -1:0] offset; + // IO request management logic [IO_MAP_NB -1:0] io_map_hit; logic is_io_req; logic [4 -1:0] acache; + // Outstanding request counters logic [MAX_OR_W -1:0] wr_or_cnt; logic max_wr_or; logic [MAX_OR_W -1:0] rd_or_cnt; logic max_rd_or; logic waiting_rd_cpl; logic waiting_wr_cpl; + + // registers under use for scheduler logic [MAX_OR_W -1:0] regs_or[NB_INT_REG-1:0]; + // MPU accesses + logic check_access; + logic active_access; + logic read_allowed; + logic write_allowed; + + // exceptions + logic load_misaligned; + logic store_misaligned; + logic load_access_fault; + logic store_access_fault; + + // Central FSM + logic memfy_ready_fsm; + logic stall_bus; + typedef enum logic[1:0] { IDLE = 0, WAIT = 1, @@ -354,7 +215,7 @@ module friscv_memfy assign pc = memfy_instbus[`PC +: `PC_W ]; assign inst = memfy_instbus[`INST +: `INST_W ]; assign priv = memfy_instbus[`PRIV +: `PRIV_W ]; - assign mpp = memfy_instbus[`PRIV +: `PRIV_W ]; + assign mpp = memfy_instbus[`MPP +: `PRIV_W ]; assign mprv = memfy_instbus[`MPRV ]; @@ -435,7 +296,7 @@ module friscv_memfy opcode_r <= opcode; // STORE - if (opcode==`STORE && mpu_allow[`ALW_W] && !store_misaligned) begin + if (opcode==`STORE && write_allowed) begin if (waiting_rd_cpl || arvalid) begin state <= WAIT; @@ -460,7 +321,7 @@ module friscv_memfy arvalid <= 1'b0; // LOAD - end else if (opcode==`LOAD && mpu_allow[`ALW_R] && !load_misaligned) begin + end else if (opcode==`LOAD && read_allowed) begin if (waiting_wr_cpl || awvalid) begin state <= WAIT; arvalid <= 1'b0; @@ -547,7 +408,9 @@ module friscv_memfy /////////////////////////////////////////////////////////////////////////// + // // Store outstanding read request info for data alignment of the completion + // /////////////////////////////////////////////////////////////////////////// assign push_rd_or = memfy_valid & memfy_ready & (opcode==`LOAD) & !load_misaligned; @@ -581,8 +444,12 @@ module friscv_memfy `endif end + //////////////////////////////////////////////////////////////////////// + // // Track which integer registers is used by an outstanding request + // for instruction scheduling + // //////////////////////////////////////////////////////////////////////// always @ (posedge aclk or negedge aresetn) begin @@ -620,8 +487,11 @@ module friscv_memfy assign memfy_regs_sts[i] = regs_or[i] == '0; end + //////////////////////////////////////////////////////////////////////// + // // Track the current read/write outstanding requests waiting completions + // //////////////////////////////////////////////////////////////////////// always @ (posedge aclk or negedge aresetn) begin @@ -637,14 +507,14 @@ module friscv_memfy end else begin // Write xfers tracker - if (memfy_valid && memfy_ready && opcode==`STORE && !bvalid && !max_wr_or && mpu_allow[`ALW_W] && !store_misaligned) begin + if (memfy_valid && memfy_ready && opcode==`STORE && !bvalid && !max_wr_or && write_allowed) begin wr_or_cnt <= wr_or_cnt + 1'b1; end else if (!(memfy_valid && memfy_ready && opcode==`STORE) && bvalid && bready && wr_or_cnt!={MAX_OR_W{1'b0}}) begin wr_or_cnt <= wr_or_cnt - 1'b1; end // Read xfers tracker - if (memfy_valid && memfy_ready && opcode==`LOAD && !memfy_rd_wr && !max_rd_or && mpu_allow[`ALW_R] && !load_misaligned) begin + if (memfy_valid && memfy_ready && opcode==`LOAD && !memfy_rd_wr && !max_rd_or && read_allowed) begin rd_or_cnt <= rd_or_cnt + 1'b1; end else if (!(memfy_valid && memfy_ready && opcode==`LOAD) && memfy_rd_wr && rd_or_cnt!={MAX_OR_W{1'b0}}) begin rd_or_cnt <= rd_or_cnt - 1'b1; @@ -682,7 +552,9 @@ module friscv_memfy //////////////////////////////////////////////////////////////////////// + // // Manage the RD write operation + // //////////////////////////////////////////////////////////////////////// generate if (SYNC_RD_WR) begin : RD_WR_FFD @@ -722,12 +594,13 @@ module friscv_memfy ///////////////////////////////////////////////////////////////////////// + // // Address to read/write and fence information + // //////////////////////////////////////////////////////////////////////// // The address to access during a LOAD or a STORE assign addr = $signed({{(XLEN-12){imm12[11]}}, imm12}) + $signed(memfy_rs1_val); - assign mpu_addr = addr; // Unused: information forwarded to control unit for FENCE execution: // bit 0: memory write @@ -738,7 +611,9 @@ module friscv_memfy //////////////////////////////////////////////////////////////////////////// - // device/IO vs normal memory detection to ensure IO maps will not be cached + // + // Device/IO vs normal memory detection to ensure IO maps will not be cached + // //////////////////////////////////////////////////////////////////////////// generate @@ -820,16 +695,39 @@ module friscv_memfy assign rready = 1'b1; + //////////////////////////////////////////////////////////////////////////// + // + // MPU management + // + //////////////////////////////////////////////////////////////////////////// + + + generate if (USER_MODE) begin: UMODE_SUPPORT + + // Check access fault if u-mode or m-mode setup with u-mode rights + assign check_access = (priv==`UMODE) || (priv==`MMODE && mpp==`UMODE && mprv) || + (priv==`MMODE && mpu_allow[`ALW_L]); + + end else begin: NO_UMODE_SUPPORT + assign check_access = 1'b1; + end + endgenerate + + assign mpu_addr = addr; + + assign write_allowed = mpu_allow[`ALW_W] & !store_misaligned & check_access; + + assign read_allowed = mpu_allow[`ALW_R] & !load_misaligned & check_access; + + ////////////////////////////////////////////////////////////////////////// + // // Exception flags, driven back to control unit + // ////////////////////////////////////////////////////////////////////////// assign active_access = memfy_valid & memfy_ready; - // Check access fault if u-mode or m-mode setup with u-mode rights - assign check_access = (priv==`UMODE) || (priv==`MMODE && mpp==`UMODE && mprv) || - (priv==`MMODE && mpu_allow[3]); // locked - // LOAD is not XLEN-boundary aligned assign load_misaligned = (opcode==`LOAD && (funct3==`LH || funct3==`LHU) && (addr[1:0]==2'h3 || addr[1:0]==2'h1)) ? active_access : @@ -842,10 +740,10 @@ module friscv_memfy (opcode==`STORE && funct3==`SW && addr[1:0]!=2'b0) ? active_access : 1'b0 ; - // Load access outside am allowed region + // Load access outside an allowed region assign load_access_fault = (opcode==`LOAD) & !mpu_allow[`ALW_R] & check_access & active_access; - // Store access outside am allowed region + // Store access outside an allowed region assign store_access_fault = (opcode==`STORE) & !mpu_allow[`ALW_W] & check_access & active_access; diff --git a/rtl/friscv_memfy_h.sv b/rtl/friscv_memfy_h.sv new file mode 100644 index 0000000..f9d0d11 --- /dev/null +++ b/rtl/friscv_memfy_h.sv @@ -0,0 +1,166 @@ +// distributed under the mit license +// https://opensource.org/licenses/mit-license.php + +`ifndef MEMFY_H +`define MEMFY_H + + /////////////////////////////////////////////////////////////////////////// + // + // AXI Alignment Functions + // + /////////////////////////////////////////////////////////////////////////// + + + /////////////////////////////////////////////////////////////////////////// + // Align the read memory value to write in RD. Right shift the data. + // Args: + // - data: the word to align + // - offset: the shift to apply, ADDR's LSBs + // Returns: + // - data aligned ready to store + /////////////////////////////////////////////////////////////////////////// + function automatic logic [XLEN-1:0] get_axi_data( + + input logic [XLEN -1:0] data, + input logic [2 -1:0] offset + ); + if (offset==2'b00) get_axi_data = data; + if (offset==2'b01) get_axi_data = {data[XLEN- 8-1:0], data[XLEN-1-:8]}; + if (offset==2'b10) get_axi_data = {data[XLEN-16-1:0], data[XLEN-1-:16]}; + if (offset==2'b11) get_axi_data = {data[XLEN-24-1:0], data[XLEN-1-:24]}; + + endfunction + + + /////////////////////////////////////////////////////////////////////////// + // Align the write strobes to write in memory + // Args: + // - strb: the strobes to align + // - offset: the shift to apply, ADDR's LSBs + // Returns: + // - strobes aligned ready to store + /////////////////////////////////////////////////////////////////////////// + function automatic logic [XLEN/8-1:0] aligned_axi_strb( + + input logic [XLEN/8-1:0] strb, + input logic [2 -1:0] offset + ); + if (offset==2'b00) aligned_axi_strb = strb; + if (offset==2'b01) aligned_axi_strb = {strb[XLEN/8-2:0], 1'b0}; + if (offset==2'b10) aligned_axi_strb = {strb[XLEN/8-3:0], 2'b0}; + if (offset==2'b11) aligned_axi_strb = {strb[XLEN/8-4:0], 3'b0}; + + endfunction + + /////////////////////////////////////////////////////////////////////////// + // Create the strobe vector to aply during a STORE instruction + // Args: + // - funct3: opcode's funct3 identifier + // - offset: the shift to apply, ADDR's LSBs + // Returns: + // - the ready to use strobes + /////////////////////////////////////////////////////////////////////////// + function automatic logic [XLEN/8-1:0] get_axi_strb( + + input logic [2:0] funct3, + input logic [1:0] offset + ); + if (funct3==`SB) get_axi_strb = aligned_axi_strb({{(XLEN/8-1){1'b0}},1'b1}, offset); + if (funct3==`SH) get_axi_strb = aligned_axi_strb({{(XLEN/8-2){1'b0}},2'b11}, offset); + if (funct3==`SW) get_axi_strb = aligned_axi_strb({(XLEN/8){1'b1}}, offset); + + endfunction + + + /////////////////////////////////////////////////////////////////////////// + // + // ISA registers Alignment functions + // + /////////////////////////////////////////////////////////////////////////// + + + /////////////////////////////////////////////////////////////////////////// + // Align the read memory value to write in RD. Right shift the data. + // Args: + // - data: the word to align + // - offset: the shift to apply, ADDR's LSBs + // Returns: + // - data aligned ready to store + /////////////////////////////////////////////////////////////////////////// + function automatic logic [XLEN-1:0] get_aligned_rd_data( + + input logic [XLEN -1:0] data, + input logic [2 -1:0] offset + ); + if (offset==2'b00) get_aligned_rd_data = data; + if (offset==2'b01) get_aligned_rd_data = {data[XLEN-24-1:0], data[XLEN-1:8]}; + if (offset==2'b10) get_aligned_rd_data = {data[XLEN-16-1:0], data[XLEN-1:16]}; + if (offset==2'b11) get_aligned_rd_data = {data[XLEN- 8-1:0], data[XLEN-1:24]}; + + endfunction + + /////////////////////////////////////////////////////////////////////////// + // Create the strobe vector to apply during a RD write + // Args: + // - funct3: opcode's funct3 identifier + // - rdata: the word to align + // - offset: the shift to apply, ADDR's LSBs + // Returns: + // - the ready to use strobes + /////////////////////////////////////////////////////////////////////////// + function automatic logic [XLEN-1:0] get_rd_val( + + input logic [3 -1:0] funct3, + input logic [XLEN-1:0] data, + input logic [2 -1:0] offset + ); + logic [XLEN-1:0] data_aligned; + + data_aligned = get_aligned_rd_data(data, offset); + + if (funct3==`LB) get_rd_val = {{24{data_aligned[7]}}, data_aligned[7:0]}; + if (funct3==`LBU) get_rd_val = {{24{1'b0}}, data_aligned[7:0]}; + if (funct3==`LH) get_rd_val = {{16{data_aligned[15]}}, data_aligned[15:0]}; + if (funct3==`LHU) get_rd_val = {{16{1'b0}}, data_aligned[15:0]}; + if (funct3==`LW) get_rd_val = data_aligned; + + endfunction + + /////////////////////////////////////////////////////////////////////////// + // Create the strobe vector to apply during a RD write + // Args: + // - funct3: opcode's funct3 identifier + // - phase: first (0) or second (1) phase of the STORE request + // Returns: + // - the ready to use strobes + /////////////////////////////////////////////////////////////////////////// + function automatic logic [XLEN/8-1:0] get_rd_strb( + + input logic [3 -1:0] funct3, + input logic [2 -1:0] offset + ); + if (funct3==`LB || funct3==`LBU) begin + get_rd_strb = {(XLEN/8){1'b1}}; + end + if (funct3==`LH || funct3==`LHU) begin + if (offset==2'h3) begin + get_rd_strb = {{(XLEN/8-1){1'b0}},1'b1}; + end else begin + get_rd_strb = {(XLEN/8){1'b1}}; + end + end + if (funct3==`LW) begin + if (offset==2'h0) begin + get_rd_strb = {(XLEN/8){1'b1}}; + end else if (offset==2'h1) begin + get_rd_strb = {{(XLEN/8-3){1'b0}},3'b111}; + end else if (offset==2'h2) begin + get_rd_strb = {{(XLEN/8-2){1'b0}},2'b11}; + end else if (offset==2'h3) begin + get_rd_strb = {{(XLEN/8-1){1'b0}},1'b1}; + end + end + + endfunction + +`endif diff --git a/rtl/friscv_processing.sv b/rtl/friscv_processing.sv index 24055ee..d1f10ac 100644 --- a/rtl/friscv_processing.sv +++ b/rtl/friscv_processing.sv @@ -35,6 +35,14 @@ module friscv_processing parameter DATA_OSTDREQ_NUM = 8, // Add pipeline on Rd write stage parameter SYNC_RD_WR = 0, + // Support hypervisor mode + parameter HYPERVISOR_MODE = 0, + // Support supervisor mode + parameter SUPERVISOR_MODE = 0, + // Support user mode + parameter USER_MODE = 0, + // PMP / PMA supported + parameter MPU_SUPPORT = 0, // IO regions for direct read/write access parameter IO_MAP_NB = 1, // IO address ranges, organized by memory region as END-ADDR_START-ADDR: @@ -316,6 +324,10 @@ module friscv_processing .AXI_DATA_W (AXI_DATA_W), .AXI_ID_MASK (AXI_ID_MASK), .SYNC_RD_WR (SYNC_RD_WR), + .HYPERVISOR_MODE (HYPERVISOR_MODE), + .SUPERVISOR_MODE (SUPERVISOR_MODE), + .USER_MODE (USER_MODE), + .MPU_SUPPORT (MPU_SUPPORT), .IO_MAP_NB (IO_MAP_NB), .IO_MAP (IO_MAP) ) diff --git a/rtl/friscv_rv32i_core.sv b/rtl/friscv_rv32i_core.sv index c01764e..8e07352 100644 --- a/rtl/friscv_rv32i_core.sv +++ b/rtl/friscv_rv32i_core.sv @@ -695,6 +695,10 @@ module friscv_rv32i_core .MAX_UNIT (MAX_ALU_UNIT), .DATA_OSTDREQ_NUM (DATA_OSTDREQ_NUM), .INST_BUS_PIPELINE (PROCESSING_BUS_PIPELINE), + .HYPERVISOR_MODE (HYPERVISOR_MODE), + .SUPERVISOR_MODE (SUPERVISOR_MODE), + .MPU_SUPPORT (MPU_SUPPORT), + .USER_MODE (USER_MODE), .IO_MAP_NB (IO_MAP_NB), .IO_MAP (IO_MAP) ) diff --git a/test/c_testsuite/tests/extern_vars.v b/test/c_testsuite/tests/extern_vars.v index 46c2170..576b526 100755 --- a/test/c_testsuite/tests/extern_vars.v +++ b/test/c_testsuite/tests/extern_vars.v @@ -12,13 +12,12 @@ F3 22 10 34 93 82 42 00 73 90 12 34 73 00 20 30 @000100B0 13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 -97 07 07 00 93 87 07 F4 13 07 20 03 23 A0 E7 00 -23 26 04 FE 6F 00 40 01 EF 00 00 05 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 10 03 -E3 D4 E7 FE 97 07 07 00 93 87 C7 F0 03 A7 07 00 -93 07 40 06 63 04 F7 00 93 8F 1F 00 73 00 10 00 -93 07 00 00 13 85 07 00 83 20 C1 01 03 24 81 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 97 07 07 00 93 87 C7 EC 83 A7 07 00 -13 87 17 00 97 07 07 00 93 87 C7 EB 23 A0 E7 00 +B7 07 08 00 13 07 20 03 23 A0 E7 00 23 26 04 FE +6F 00 40 01 EF 00 C0 04 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 10 03 E3 D4 E7 FE +B7 07 08 00 03 A7 07 00 93 07 40 06 63 04 F7 00 +93 8F 1F 00 73 00 10 00 93 07 00 00 13 85 07 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 08 00 +83 A7 07 00 13 87 17 00 B7 07 08 00 23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/test/c_testsuite/tests/extern_vars/extern_vars.v b/test/c_testsuite/tests/extern_vars/extern_vars.v index 46c2170..576b526 100755 --- a/test/c_testsuite/tests/extern_vars/extern_vars.v +++ b/test/c_testsuite/tests/extern_vars/extern_vars.v @@ -12,13 +12,12 @@ F3 22 10 34 93 82 42 00 73 90 12 34 73 00 20 30 @000100B0 13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 -97 07 07 00 93 87 07 F4 13 07 20 03 23 A0 E7 00 -23 26 04 FE 6F 00 40 01 EF 00 00 05 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 10 03 -E3 D4 E7 FE 97 07 07 00 93 87 C7 F0 03 A7 07 00 -93 07 40 06 63 04 F7 00 93 8F 1F 00 73 00 10 00 -93 07 00 00 13 85 07 00 83 20 C1 01 03 24 81 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 97 07 07 00 93 87 C7 EC 83 A7 07 00 -13 87 17 00 97 07 07 00 93 87 C7 EB 23 A0 E7 00 +B7 07 08 00 13 07 20 03 23 A0 E7 00 23 26 04 FE +6F 00 40 01 EF 00 C0 04 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 10 03 E3 D4 E7 FE +B7 07 08 00 03 A7 07 00 93 07 40 06 63 04 F7 00 +93 8F 1F 00 73 00 10 00 93 07 00 00 13 85 07 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 08 00 +83 A7 07 00 13 87 17 00 B7 07 08 00 23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/test/c_testsuite/tests/heap.v b/test/c_testsuite/tests/heap.v index 2609c5f..8004ece 100755 --- a/test/c_testsuite/tests/heap.v +++ b/test/c_testsuite/tests/heap.v @@ -12,259 +12,258 @@ F3 22 10 34 93 82 42 00 73 90 12 34 73 00 20 30 @000100B0 13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 -EF 00 40 06 23 26 04 FE 6F 00 00 03 97 07 07 00 -93 87 87 79 03 A7 07 00 83 27 C4 FE 93 97 27 00 -B3 07 F7 00 03 27 C4 FE 23 A0 E7 00 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 90 00 -E3 D6 E7 FC EF 00 00 06 73 00 10 00 93 07 00 00 -13 85 07 00 83 20 C1 01 03 24 81 01 13 01 01 02 -67 80 00 00 13 01 01 FF 23 26 11 00 23 24 81 00 -13 04 01 01 13 05 80 02 EF 00 40 06 93 07 05 00 -13 87 07 00 97 07 07 00 93 87 07 72 23 A0 E7 00 -13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 11 00 23 24 81 00 -13 04 01 01 97 07 07 00 93 87 07 6F 83 A7 07 00 -13 85 07 00 EF 00 80 02 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 93 05 05 00 -17 05 07 00 03 25 85 69 6F 00 40 01 93 05 05 00 -17 05 07 00 03 25 85 68 6F 00 10 17 13 01 01 FD -23 20 21 03 23 26 11 02 23 24 81 02 23 22 91 02 -23 2E 31 01 23 2C 41 01 23 2A 51 01 23 28 61 01 -23 26 71 01 23 24 81 01 23 22 91 01 93 87 B5 00 -13 07 60 01 13 09 05 00 63 66 F7 06 93 07 00 01 -63 E8 B7 1E EF 00 40 78 93 04 00 01 93 07 80 01 -13 06 20 00 97 09 07 00 93 89 C9 DE B3 87 F9 00 -03 A4 47 00 13 87 87 FF 63 0C E4 20 83 27 44 00 -83 26 C4 00 03 26 84 00 93 F7 C7 FF B3 07 F4 00 -03 A7 47 00 23 26 D6 00 23 A4 C6 00 13 67 17 00 -13 05 09 00 23 A2 E7 00 EF 00 40 73 13 05 84 00 -6F 00 C0 19 93 F4 87 FF 63 C4 07 18 63 E2 B4 18 -EF 00 80 71 93 07 70 1F 63 F0 97 48 93 D7 94 00 -63 88 07 1A 13 07 40 00 63 66 F7 3E 93 D7 64 00 -13 86 97 03 13 85 87 03 93 16 36 00 97 09 07 00 -93 89 49 D6 B3 86 D9 00 03 A4 46 00 93 86 86 FF -63 86 86 02 93 05 F0 00 6F 00 00 01 63 56 07 34 -03 24 C4 00 63 8C 86 00 83 27 44 00 93 F7 C7 FF -33 87 97 40 E3 D4 E5 FE 13 06 05 00 03 A4 09 01 -97 08 07 00 93 88 88 D2 63 0A 14 17 83 25 44 00 -13 07 F0 00 93 F5 C5 FF B3 87 95 40 63 44 F7 42 -23 AA 19 01 23 A8 19 01 63 DE 07 3E 93 07 F0 1F -63 E2 B7 30 93 F7 85 FF 93 87 87 00 03 A5 49 00 -B3 87 F9 00 83 A6 07 00 93 D5 55 00 13 07 10 00 -33 17 B7 00 33 67 A7 00 93 85 87 FF 23 26 B4 00 -23 24 D4 00 23 A2 E9 00 23 A0 87 00 23 A6 86 00 -93 57 26 40 93 05 10 00 B3 95 F5 00 63 6A B7 10 -B3 F7 E5 00 63 94 07 02 93 95 15 00 13 76 C6 FF -B3 F7 E5 00 13 06 46 00 63 9A 07 00 93 95 15 00 -B3 F7 E5 00 13 06 46 00 E3 8A 07 FE 13 08 F0 00 -13 13 36 00 33 83 69 00 13 05 03 00 83 27 C5 00 -13 0E 06 00 63 0A F5 2E 03 A7 47 00 13 84 07 00 -83 A7 C7 00 13 77 C7 FF B3 06 97 40 63 4A D8 2E -E3 C2 06 FE 33 07 E4 00 83 26 47 00 03 26 84 00 -13 05 09 00 93 E6 16 00 23 22 D7 00 23 26 F6 00 -23 A4 C7 00 EF 00 80 5A 13 05 84 00 6F 00 00 01 -93 07 C0 00 23 20 F9 00 13 05 00 00 83 20 C1 02 -03 24 81 02 83 24 41 02 03 29 01 02 83 29 C1 01 -03 2A 81 01 83 2A 41 01 03 2B 01 01 83 2B C1 00 -03 2C 81 00 83 2C 41 00 13 01 01 03 67 80 00 00 -93 06 00 20 13 06 00 04 13 05 F0 03 6F F0 1F E6 -03 A4 C7 00 13 06 26 00 E3 92 87 DE 03 A4 09 01 -97 08 07 00 93 88 88 BB E3 1A 14 E9 03 A7 49 00 -93 57 26 40 93 05 10 00 B3 95 F5 00 E3 7A B7 EE -03 A4 89 00 03 2B 44 00 13 7B CB FF 63 68 9B 00 -B3 07 9B 40 13 07 F0 00 63 4C F7 14 97 0C 07 00 -93 8C 4C 3A 03 A7 0C 00 97 0A 07 00 83 AA 8A 3D -93 07 F0 FF 33 0A 64 01 B3 8A 54 01 63 0E F7 34 -B7 17 00 00 93 87 F7 00 B3 8A FA 00 B7 F7 FF FF -B3 FA FA 00 93 85 0A 00 13 05 09 00 EF 00 40 4C -93 07 F0 FF 93 0B 05 00 63 00 F5 2A 63 6C 45 29 -17 0C 07 00 13 0C CC 35 83 25 0C 00 B3 85 BA 00 -23 20 BC 00 93 87 05 00 63 08 AA 3A 83 A6 0C 00 -13 07 F0 FF 63 80 E6 3C 33 8A 4B 41 B3 07 FA 00 -23 20 FC 00 93 FC 7B 00 63 8A 0C 30 B7 17 00 00 -B3 8B 9B 41 93 85 87 00 93 8B 8B 00 B3 85 95 41 -B3 8A 5B 01 93 87 F7 FF B3 85 55 41 33 FA F5 00 -93 05 0A 00 13 05 09 00 EF 00 80 44 93 07 F0 FF -63 04 F5 3C 33 05 75 41 B3 0A 45 01 83 27 0C 00 -23 A4 79 01 93 EA 1A 00 B3 05 FA 00 23 20 BC 00 -23 A2 5B 01 63 0C 34 35 93 06 F0 00 63 FC 66 35 -03 27 44 00 93 07 4B FF 93 F7 87 FF 13 77 17 00 -33 67 F7 00 23 22 E4 00 13 06 50 00 33 07 F4 00 -23 22 C7 00 23 24 C7 00 63 E2 F6 38 83 AA 4B 00 -13 84 0B 00 97 07 07 00 93 87 87 2B 03 A7 07 00 -63 74 B7 00 23 A0 B7 00 97 07 07 00 93 87 07 2A -03 A7 07 00 63 76 B7 1A 23 A0 B7 00 6F 00 40 1A -13 E7 14 00 23 22 E4 00 B3 04 94 00 23 A4 99 00 -93 E7 17 00 13 05 09 00 23 A2 F4 00 EF 00 00 39 -13 05 84 00 6F F0 9F DF 83 26 C4 00 03 26 84 00 -6F F0 DF C2 93 D7 95 00 13 07 40 00 63 72 F7 14 -13 07 40 01 63 6A F7 22 93 86 C7 05 13 87 B7 05 -93 96 36 00 B3 86 D9 00 83 A7 06 00 93 86 86 FF -63 88 F6 1C 03 A7 47 00 13 77 C7 FF 63 F6 E5 00 -83 A7 87 00 E3 98 F6 FE 83 A6 C7 00 03 A7 49 00 -23 26 D4 00 23 24 F4 00 23 A4 86 00 23 A6 87 00 -6F F0 1F CE 13 07 40 01 63 76 F7 12 13 07 40 05 -63 6A F7 1E 93 D7 C4 00 13 86 F7 06 13 85 E7 06 -93 16 36 00 6F F0 9F C0 13 0E 1E 00 93 77 3E 00 -13 05 85 00 63 8E 07 10 83 27 C5 00 6F F0 9F CF -03 26 84 00 93 E5 14 00 23 22 B4 00 23 26 F6 00 -23 A4 C7 00 B3 04 94 00 23 AA 99 00 23 A8 99 00 -93 E7 16 00 23 A6 14 01 23 A4 14 01 23 A2 F4 00 -33 07 E4 00 13 05 09 00 23 20 D7 00 EF 00 00 2A -13 05 84 00 6F F0 9F D0 13 D6 34 00 93 87 84 00 -6F F0 5F B1 B3 05 B4 00 83 A7 45 00 13 05 09 00 -93 E7 17 00 23 A2 F5 00 EF 00 40 27 13 05 84 00 -6F F0 DF CD 13 E7 14 00 23 22 E4 00 B3 04 94 00 -23 AA 99 00 23 A8 99 00 13 E7 17 00 23 A6 14 01 -23 A4 14 01 23 A2 E4 00 B3 05 B4 00 13 05 09 00 -23 A0 F5 00 EF 00 80 23 13 05 84 00 6F F0 1F CA -93 D7 65 00 93 86 97 03 13 87 87 03 93 96 36 00 -6F F0 5F EC 63 0E 34 11 03 A4 89 00 83 2A 44 00 -93 FA CA FF B3 87 9A 40 63 E6 9A 00 13 07 F0 00 -E3 48 F7 E4 13 05 09 00 EF 00 40 1F 13 05 00 00 -6F F0 DF C5 13 86 C7 05 13 85 B7 05 93 16 36 00 -6F F0 DF AE 83 27 83 00 13 06 F6 FF 63 92 67 1C -93 77 36 00 13 03 83 FF E3 96 07 FE 03 A7 49 00 -93 C7 F5 FF B3 F7 E7 00 23 A2 F9 00 93 95 15 00 -E3 E8 B7 C8 E3 86 05 C8 33 F7 F5 00 63 1A 07 00 -93 95 15 00 33 F7 F5 00 13 0E 4E 00 E3 0A 07 FE -13 06 0E 00 6F F0 DF B8 93 8A 0A 01 6F F0 9F CB -03 A5 49 00 93 55 27 40 13 07 10 00 33 17 B7 00 -33 67 A7 00 23 A2 E9 00 6F F0 9F E3 B3 85 5B 01 -B3 05 B0 40 93 95 45 01 13 DA 45 01 93 05 0A 00 -13 05 09 00 EF 00 C0 14 93 07 F0 FF E3 14 F5 D0 -13 0A 00 00 6F F0 9F D0 13 07 40 05 63 62 F7 08 -93 D7 C5 00 93 86 F7 06 13 87 E7 06 93 96 36 00 -6F F0 5F DC 13 07 40 15 63 62 F7 08 93 D7 F4 00 -13 86 87 07 13 85 77 07 93 16 36 00 6F F0 1F A1 -17 0C 07 00 13 0C CC FA 83 27 0C 00 B3 87 FA 00 -23 20 FC 00 6F F0 9F C5 13 17 4A 01 E3 18 07 C4 -03 A4 89 00 B3 0A 5B 01 93 EA 1A 00 23 22 54 01 -6F F0 5F CF 23 A0 7C 01 6F F0 DF C4 13 84 0B 00 -6F F0 5F CE 93 07 10 00 23 A2 FB 00 6F F0 9F EB -13 07 40 15 63 62 F7 06 93 D7 F5 00 93 86 87 07 -13 87 77 07 93 96 36 00 6F F0 DF D3 13 07 40 55 -63 62 F7 06 93 D7 24 01 13 86 D7 07 13 85 C7 07 -93 16 36 00 6F F0 9F 98 93 8C 8C FF B3 8A 9A 01 -B3 8A 7A 41 13 0A 00 00 6F F0 5F C3 93 05 84 00 -13 05 09 00 EF 00 40 1F 03 A4 89 00 83 25 0C 00 -83 2A 44 00 6F F0 1F C7 13 07 40 55 63 64 F7 02 -93 D7 25 01 93 86 D7 07 13 87 C7 07 93 96 36 00 -6F F0 5F CD 93 06 80 3F 13 06 F0 07 13 05 E0 07 -6F F0 DF 92 93 06 80 3F 13 07 E0 07 6F F0 9F CB -83 A7 49 00 6F F0 9F E5 67 80 00 00 67 80 00 00 -13 01 01 FF 23 24 81 00 13 04 05 00 13 85 05 00 -97 07 07 00 23 AA 07 EC 23 26 11 00 EF 00 40 64 -93 07 F0 FF 63 0A F5 00 83 20 C1 00 03 24 81 00 -13 01 01 01 67 80 00 00 97 07 07 00 83 A7 C7 EA -E3 84 07 FE 83 20 C1 00 23 20 F4 00 03 24 81 00 -13 01 01 01 67 80 00 00 13 01 01 FE 23 2C 81 00 -23 2A 91 00 23 28 21 01 23 26 31 01 23 24 41 01 -93 89 05 00 23 2E 11 00 17 FA 06 00 13 0A 8A 5F -13 09 05 00 EF F0 5F F7 03 27 8A 00 B7 17 00 00 -13 84 F7 FE 83 24 47 00 33 04 34 41 93 F4 C4 FF -33 04 94 00 13 54 C4 00 13 04 F4 FF 13 14 C4 00 -63 4E F4 00 93 05 00 00 13 05 09 00 EF F0 5F F4 -83 27 8A 00 B3 87 97 00 63 08 F5 02 13 05 09 00 -EF F0 DF F2 83 20 C1 01 03 24 81 01 83 24 41 01 -03 29 01 01 83 29 C1 00 03 2A 81 00 13 05 00 00 -13 01 01 02 67 80 00 00 B3 05 80 40 13 05 09 00 -EF F0 1F F0 93 07 F0 FF 63 0A F5 04 17 07 07 00 -13 07 07 DA 83 27 07 00 83 26 8A 00 B3 84 84 40 -93 E4 14 00 B3 87 87 40 13 05 09 00 23 A2 96 00 -23 20 F7 00 EF F0 9F EC 83 20 C1 01 03 24 81 01 +EF 00 00 06 23 26 04 FE 6F 00 C0 02 B7 17 08 00 +03 A7 47 86 83 27 C4 FE 93 97 27 00 B3 07 F7 00 +03 27 C4 FE 23 A0 E7 00 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 90 00 E3 D8 E7 FC +EF 00 C0 05 73 00 10 00 93 07 00 00 13 85 07 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 +13 05 80 02 EF 00 C0 05 93 07 05 00 13 87 07 00 +B7 17 08 00 23 A2 E7 86 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 11 00 23 24 81 00 13 04 01 01 B7 17 08 00 +83 A7 47 86 13 85 07 00 EF 00 80 02 13 00 00 00 +83 20 C1 00 03 24 81 00 13 01 01 01 67 80 00 00 +93 05 05 00 17 05 07 00 03 25 45 6A 6F 00 40 01 +93 05 05 00 17 05 07 00 03 25 45 69 6F 00 10 17 +13 01 01 FD 23 20 21 03 23 26 11 02 23 24 81 02 +23 22 91 02 23 2E 31 01 23 2C 41 01 23 2A 51 01 +23 28 61 01 23 26 71 01 23 24 81 01 23 22 91 01 +93 87 B5 00 13 07 60 01 13 09 05 00 63 66 F7 06 +93 07 00 01 63 E8 B7 1E EF 00 40 78 93 04 00 01 +93 07 80 01 13 06 20 00 97 09 07 00 93 89 89 DF +B3 87 F9 00 03 A4 47 00 13 87 87 FF 63 0C E4 20 +83 27 44 00 83 26 C4 00 03 26 84 00 93 F7 C7 FF +B3 07 F4 00 03 A7 47 00 23 26 D6 00 23 A4 C6 00 +13 67 17 00 13 05 09 00 23 A2 E7 00 EF 00 40 73 +13 05 84 00 6F 00 C0 19 93 F4 87 FF 63 C4 07 18 +63 E2 B4 18 EF 00 80 71 93 07 70 1F 63 F0 97 48 +93 D7 94 00 63 88 07 1A 13 07 40 00 63 66 F7 3E +93 D7 64 00 13 86 97 03 13 85 87 03 93 16 36 00 +97 09 07 00 93 89 09 D7 B3 86 D9 00 03 A4 46 00 +93 86 86 FF 63 86 86 02 93 05 F0 00 6F 00 00 01 +63 56 07 34 03 24 C4 00 63 8C 86 00 83 27 44 00 +93 F7 C7 FF 33 87 97 40 E3 D4 E5 FE 13 06 05 00 +03 A4 09 01 97 08 07 00 93 88 48 D3 63 0A 14 17 +83 25 44 00 13 07 F0 00 93 F5 C5 FF B3 87 95 40 +63 44 F7 42 23 AA 19 01 23 A8 19 01 63 DE 07 3E +93 07 F0 1F 63 E2 B7 30 93 F7 85 FF 93 87 87 00 +03 A5 49 00 B3 87 F9 00 83 A6 07 00 93 D5 55 00 +13 07 10 00 33 17 B7 00 33 67 A7 00 93 85 87 FF +23 26 B4 00 23 24 D4 00 23 A2 E9 00 23 A0 87 00 +23 A6 86 00 93 57 26 40 93 05 10 00 B3 95 F5 00 +63 6A B7 10 B3 F7 E5 00 63 94 07 02 93 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85 D6 07 13 86 C6 07 93 95 35 00 6F F0 5F E7 -93 05 80 3F 13 06 E0 07 6F F0 9F E6 93 E6 17 00 -23 22 D7 00 23 20 F6 00 6F F0 DF DC 13 01 01 FE -23 28 21 01 03 A9 05 00 23 2C 81 00 23 2A 91 00 -23 2E 11 00 23 26 31 01 23 24 41 01 13 84 05 00 -93 04 05 00 63 02 09 04 83 29 09 00 63 88 09 02 -03 AA 09 00 63 0E 0A 00 83 25 0A 00 63 84 05 00 -EF F0 DF FB 93 05 0A 00 13 85 04 00 EF F0 DF C9 -93 85 09 00 13 85 04 00 EF F0 1F C9 93 05 09 00 -13 85 04 00 EF F0 5F C8 93 05 04 00 03 24 81 01 -83 20 C1 01 03 29 01 01 83 29 C1 00 03 2A 81 00 -13 85 04 00 83 24 41 01 13 01 01 02 6F F0 DF C5 -97 07 07 00 83 A7 87 96 63 8A A7 10 83 25 C5 04 -13 01 01 FE 23 2A 91 00 23 2E 11 00 23 2C 81 00 -23 28 21 01 23 26 31 01 93 04 05 00 63 80 05 04 -13 09 00 00 93 09 00 08 B3 87 25 01 03 A4 07 00 -63 0E 04 00 93 05 04 00 03 24 04 00 13 85 04 00 -EF F0 9F C0 E3 18 04 FE 83 A5 C4 04 13 09 49 00 -E3 1C 39 FD 13 85 04 00 EF F0 1F BF 83 A5 04 04 -63 86 05 00 13 85 04 00 EF F0 1F BE 03 A4 84 14 -63 00 04 02 13 89 C4 14 63 0C 24 01 93 05 04 00 -03 24 04 00 13 85 04 00 EF F0 1F BC E3 18 89 FE -83 A5 44 05 63 86 05 00 13 85 04 00 EF F0 DF BA -83 A7 84 03 63 86 07 04 83 A7 C4 03 13 85 04 00 -E7 80 07 00 03 A4 04 2E 63 0C 04 02 83 25 04 00 -63 86 05 00 13 85 04 00 EF F0 5F E9 93 05 04 00 +13 05 00 00 13 01 01 02 67 80 00 00 B3 05 80 40 +13 05 09 00 EF F0 1F F0 93 07 F0 FF 63 0A F5 04 +17 07 07 00 13 07 C7 DA 83 27 07 00 83 26 8A 00 +B3 84 84 40 93 E4 14 00 B3 87 87 40 13 05 09 00 +23 A2 96 00 23 20 F7 00 EF F0 9F EC 83 20 C1 01 +03 24 81 01 83 24 41 01 03 29 01 01 83 29 C1 00 +03 2A 81 00 13 05 10 00 13 01 01 02 67 80 00 00 +93 05 00 00 13 05 09 00 EF F0 DF E9 03 27 8A 00 +93 06 F0 00 B3 07 E5 40 E3 DC F6 F4 97 06 07 00 +83 A6 46 D3 33 05 D5 40 93 E7 17 00 97 06 07 00 +23 A8 A6 D2 23 22 F7 00 6F F0 9F F3 63 8A 05 12 +13 01 01 FF 23 24 81 00 23 22 91 00 13 84 05 00 +93 04 05 00 23 26 11 00 EF F0 5F E4 83 25 C4 FF +13 07 84 FF 17 F8 06 00 13 08 C8 4B 93 F7 E5 FF +33 06 F7 00 83 26 46 00 03 25 88 00 93 F6 C6 FF +63 0A C5 1A 23 22 D6 00 93 F5 15 00 33 05 D6 00 +63 90 05 0A 03 23 84 FF 83 25 45 00 97 F8 06 00 +93 88 C8 48 33 07 67 40 03 25 87 00 B3 87 67 00 +93 F5 15 00 63 00 15 15 03 23 C7 00 23 26 65 00 +23 24 A3 00 63 84 05 1E 93 E6 17 00 23 22 D7 00 +23 20 F6 00 93 06 F0 1F 63 E8 F6 0A 93 F6 87 FF +93 86 86 00 83 25 48 00 B3 06 D8 00 03 A6 06 00 +13 D5 57 00 93 07 10 00 B3 97 A7 00 B3 E7 B7 00 +93 85 86 FF 23 26 B7 00 23 24 C7 00 23 22 F8 00 +23 A0 E6 00 23 26 E6 00 03 24 81 00 83 20 C1 00 +13 85 04 00 83 24 41 00 13 01 01 01 6F F0 5F D7 +83 25 45 00 93 F5 15 00 63 9E 05 02 B3 87 D7 00 +97 F8 06 00 93 88 88 3E 83 26 86 00 13 E5 17 00 +B3 05 F7 00 63 88 16 17 03 26 C6 00 23 A6 C6 00 +23 24 D6 00 23 22 A7 00 23 A0 F5 00 6F F0 9F F6 +67 80 00 00 93 E6 17 00 23 2E D4 FE 23 20 F6 00 +93 06 F0 1F E3 FC F6 F4 93 D6 97 00 13 06 40 00 +63 6C D6 0E 93 D6 67 00 93 85 96 03 13 86 86 03 +93 95 35 00 B3 05 B8 00 83 A6 05 00 93 85 85 FF +63 88 D5 12 03 A6 46 00 13 76 C6 FF 63 F6 C7 00 +83 A6 86 00 E3 98 D5 FE 83 A5 C6 00 23 26 B7 00 +23 24 D7 00 03 24 81 00 83 20 C1 00 23 A4 E5 00 +13 85 04 00 83 24 41 00 23 A6 E6 00 13 01 01 01 +6F F0 1F CB 63 96 05 14 83 25 C6 00 03 26 86 00 +B3 86 F6 00 03 24 81 00 23 26 B6 00 23 A4 C5 00 +93 E7 16 00 83 20 C1 00 23 22 F7 00 13 85 04 00 +33 07 D7 00 83 24 41 00 23 20 D7 00 13 01 01 01 +6F F0 1F C7 93 F5 15 00 B3 86 D7 00 63 90 05 02 +83 25 84 FF 33 07 B7 40 83 27 C7 00 03 26 87 00 +B3 86 B6 00 23 26 F6 00 23 A4 C7 00 93 E7 16 00 +23 22 F7 00 23 24 E8 00 97 07 07 00 83 A7 C7 AE +E3 E4 F6 EA 97 05 07 00 83 A5 C5 B1 13 85 04 00 +EF F0 DF C7 6F F0 5F E9 13 06 40 01 63 74 D6 02 +13 06 40 05 63 64 D6 06 93 D6 C7 00 93 85 F6 06 +13 86 E6 06 93 95 35 00 6F F0 DF EF B3 87 D7 00 +6F F0 9F E9 93 85 C6 05 13 86 B6 05 93 95 35 00 +6F F0 5F EE 23 2A E8 00 23 28 E8 00 23 26 17 01 +23 24 17 01 23 22 A7 00 23 A0 F5 00 6F F0 DF E3 +03 25 48 00 13 56 26 40 93 07 10 00 B3 97 C7 00 +B3 E7 A7 00 23 22 F8 00 6F F0 5F ED 13 06 40 15 +63 6C D6 00 93 D6 F7 00 93 85 86 07 13 86 76 07 +93 95 35 00 6F F0 1F E9 13 06 40 55 63 6C D6 00 +93 D6 27 01 93 85 D6 07 13 86 C6 07 93 95 35 00 +6F F0 5F E7 93 05 80 3F 13 06 E0 07 6F F0 9F E6 +93 E6 17 00 23 22 D7 00 23 20 F6 00 6F F0 DF DC +13 01 01 FE 23 28 21 01 03 A9 05 00 23 2C 81 00 +23 2A 91 00 23 2E 11 00 23 26 31 01 23 24 41 01 +13 84 05 00 93 04 05 00 63 02 09 04 83 29 09 00 +63 88 09 02 03 AA 09 00 63 0E 0A 00 83 25 0A 00 +63 84 05 00 EF F0 DF FB 93 05 0A 00 13 85 04 00 +EF F0 DF C9 93 85 09 00 13 85 04 00 EF F0 1F C9 +93 05 09 00 13 85 04 00 EF F0 5F C8 93 05 04 00 03 24 81 01 83 20 C1 01 03 29 01 01 83 29 C1 00 -13 85 04 00 83 24 41 01 13 01 01 02 6F F0 DF B5 -83 20 C1 01 03 24 81 01 83 24 41 01 03 29 01 01 -83 29 C1 00 13 01 01 02 67 80 00 00 67 80 00 00 -97 06 07 00 93 86 86 88 03 A7 06 00 13 01 01 FF -23 26 11 00 93 07 05 00 63 10 07 02 93 08 60 0D -13 05 00 00 73 00 00 00 13 06 F0 FF 13 07 05 00 -63 0A C5 02 23 A0 A6 00 93 08 60 0D 33 85 E7 00 -73 00 00 00 03 A7 06 00 B3 87 E7 00 63 1C F5 00 -83 20 C1 00 23 A0 A6 00 13 05 07 00 13 01 01 01 -67 80 00 00 EF 00 C0 01 83 20 C1 00 93 07 C0 00 -23 20 F5 00 13 05 F0 FF 13 01 01 01 67 80 00 00 -17 F5 06 00 03 25 85 7C 67 80 00 00 -@0001107C +03 2A 81 00 13 85 04 00 83 24 41 01 13 01 01 02 +6F F0 DF C5 97 07 07 00 83 A7 47 97 63 8A A7 10 +83 25 C5 04 13 01 01 FE 23 2A 91 00 23 2E 11 00 +23 2C 81 00 23 28 21 01 23 26 31 01 93 04 05 00 +63 80 05 04 13 09 00 00 93 09 00 08 B3 87 25 01 +03 A4 07 00 63 0E 04 00 93 05 04 00 03 24 04 00 +13 85 04 00 EF F0 9F C0 E3 18 04 FE 83 A5 C4 04 +13 09 49 00 E3 1C 39 FD 13 85 04 00 EF F0 1F BF +83 A5 04 04 63 86 05 00 13 85 04 00 EF F0 1F BE +03 A4 84 14 63 00 04 02 13 89 C4 14 63 0C 24 01 +93 05 04 00 03 24 04 00 13 85 04 00 EF F0 1F BC +E3 18 89 FE 83 A5 44 05 63 86 05 00 13 85 04 00 +EF F0 DF BA 83 A7 84 03 63 86 07 04 83 A7 C4 03 +13 85 04 00 E7 80 07 00 03 A4 04 2E 63 0C 04 02 +83 25 04 00 63 86 05 00 13 85 04 00 EF F0 5F E9 +93 05 04 00 03 24 81 01 83 20 C1 01 03 29 01 01 +83 29 C1 00 13 85 04 00 83 24 41 01 13 01 01 02 +6F F0 DF B5 83 20 C1 01 03 24 81 01 83 24 41 01 +03 29 01 01 83 29 C1 00 13 01 01 02 67 80 00 00 +67 80 00 00 97 06 07 00 93 86 46 89 03 A7 06 00 +13 01 01 FF 23 26 11 00 93 07 05 00 63 10 07 02 +93 08 60 0D 13 05 00 00 73 00 00 00 13 06 F0 FF +13 07 05 00 63 0A C5 02 23 A0 A6 00 93 08 60 0D +33 85 E7 00 73 00 00 00 03 A7 06 00 B3 87 E7 00 +63 1C F5 00 83 20 C1 00 23 A0 A6 00 13 05 07 00 +13 01 01 01 67 80 00 00 EF 00 C0 01 83 20 C1 00 +93 07 C0 00 23 20 F5 00 13 05 F0 FF 13 01 01 01 +67 80 00 00 17 F5 06 00 03 25 45 7D 67 80 00 00 +@00011070 08 04 08 00 @00080000 00 00 00 00 00 00 00 00 00 00 08 00 00 00 08 00 diff --git a/test/common/debug_platform_verilator.gtkw b/test/common/debug_platform_verilator.gtkw index e61541c..bcb62ed 100644 --- a/test/common/debug_platform_verilator.gtkw +++ b/test/common/debug_platform_verilator.gtkw @@ -2,7 +2,7 @@ [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI [*] Tue Nov 7 19:31:27 2023 [*] -[dumpfile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/friscv_testbench.vcd" +[dumpfile] "/Users/damien/workspace/hdl/friscv/test/c_testsuite/friscv_testbench.vcd" [dumpfile_mtime] "Sun Nov 5 19:46:50 2023" [dumpfile_size] 61559319 [savefile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/debug_platform_verilator.gtkw" diff --git a/test/priv_sec_testsuite/tests/env/pmp.S b/test/priv_sec_testsuite/tests/env/pmp.S index da9060f..40e627a 100644 --- a/test/priv_sec_testsuite/tests/env/pmp.S +++ b/test/priv_sec_testsuite/tests/env/pmp.S @@ -22,6 +22,7 @@ .equ NA4_RX, 0x15 .equ NAPOT_RWX, 0x1F .equ NAPOT_RW, 0x1B +.equ NAPOT_LRW, 0x9B .equ NAPOT_RX, 0x1D .equ NAPOT_R, 0x19 .equ NAPOT_W, 0x1C diff --git a/test/priv_sec_testsuite/tests/env/pmp_service.S b/test/priv_sec_testsuite/tests/env/pmp_service.S index f1fc19f..7ac9a0f 100644 --- a/test/priv_sec_testsuite/tests/env/pmp_service.S +++ b/test/priv_sec_testsuite/tests/env/pmp_service.S @@ -3,10 +3,18 @@ #include "pmp.S" -.equ SVC_ERASE, 0 -.equ SVC_CHECK, 1 -.equ SVC_SETUP, 8 -.equ SVC_INTP, 9 +.equ SVC_ERASE, 0 +.equ SVC_CHECK, 1 +.equ SVC_SETUP, 8 +.equ SVC_INTP, 9 +.equ SVC_MPRV, 10 +.equ SVC_READ, 11 +.equ SVC_WRITE, 12 +.equ SVC_EXE, 13 +.equ SVC_CHECK_REGION, 14 + +.EQU MPRV_ON, 0x00020000 +.EQU MPRV_OFF, 0xFFFDFFFF //////////////////////////////////////////// // Erase all PMP configurations @@ -219,6 +227,69 @@ INTP_SERVICE: csrw mie, t4 j RET_ECALL +//////////////////////////////////////////// +// Check a configured region matches a +// a configuration +// TODO: support another region than 1 +//////////////////////////////////////////// +CHECK_PMP_REGION: + csrr t0, pmpcfg0 + li t1, 0xFF + srli t0, t0, 8 + and t0, t0, t1 + bne t0, a3, 1f + li a0, 0 + j RET_ECALL +1: + li a0, 1 + j RET_ECALL + +//////////////////////////////////////////// +# Setup MPRV bit +//////////////////////////////////////////// +MPRV_SERVICE: + csrr t0, mstatus + bne a0, zero,2f +1: + li t1, MPRV_OFF + and t0, t0, t1 + j 3f +2: + li t1, MPRV_ON + or t0, t0, t1 +3: + csrw mstatus, t0 + j RET_ECALL + +MACHINE_READ_SERVICE: + lw x0, 0(a0) + nop + nop + nop + nop + nop + nop + nop + nop + +MACHINE_WRITE_SERVICE: + sw x0, 0(a0) + nop + nop + nop + nop + nop + nop + nop + nop + +MACHINE_EXE_SERVICE: + jalr zero, 0(a0) + nop + nop + nop + nop + //////////////////////////////////////////// # Configure a NAPOT / NA4 region //////////////////////////////////////////// @@ -452,17 +523,33 @@ PMP_SERVICE: ///////////////////////////////////////////////////// ECALL_USER_MODE: # Init PMP registers - li t4, 0 + li t4, SVC_ERASE beq a7, t4, ERASE_PMP # Setup PMPADDRs/CFGs with 0xFFFFFFFF/0x77777777 - li t4, 1 + li t4, SVC_CHECK beq a7, t4, CHECK_RW_PMP # PMP service - li t4, 8 + li t4, SVC_SETUP beq a7, t4, PMP_SERVICE # Interrupt service - li t4, 9 + li t4, SVC_INTP beq a7, t4, INTP_SERVICE + # MPRV service + li t4, SVC_MPRV + beq a7, t4, MPRV_SERVICE + # Machine read service + li t4, SVC_READ + beq a7, t4, MACHINE_READ_SERVICE + # Machine write service + li t4, SVC_WRITE + beq a7, t4, MACHINE_WRITE_SERVICE + # Machine execute service + li t4, SVC_EXE + beq a7, t4, MACHINE_EXE_SERVICE + # Check a region matches a configuration + li t4, SVC_CHECK_REGION + beq a7, t4, CHECK_PMP_REGION + # Unrecognized service j RET_ECALL //////////////////////////////////////////// diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v index 05a3273..6760d39 100755 --- a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v +++ b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v @@ -1,10 +1,10 @@ @00010000 6F 00 00 0B 73 2F 20 34 93 0E 80 00 63 14 DF 01 -6F 20 C0 52 93 0E 90 00 63 04 DF 1D 93 0E B0 00 +6F 20 40 5D 93 0E 90 00 63 04 DF 1D 93 0E B0 00 63 04 DF 1D 93 0E 20 00 63 02 DF 1D B7 0E 00 80 -93 8E BE 00 63 14 DF 01 6F 20 80 53 B7 0E 00 80 -93 8E 3E 00 63 14 DF 01 6F 20 80 52 B7 0E 00 80 -93 8E 7E 00 63 14 DF 01 6F 20 80 51 93 0E 50 00 +93 8E BE 00 63 14 DF 01 6F 20 80 60 B7 0E 00 80 +93 8E 3E 00 63 14 DF 01 6F 20 80 5F B7 0E 00 80 +93 8E 7E 00 63 14 DF 01 6F 20 80 5E 93 0E 50 00 63 0A DF 19 93 0E 70 00 63 06 DF 19 93 0E 10 00 63 02 DF 19 93 0E 40 00 63 0E DF 17 93 0E 60 00 63 0A DF 17 93 0E 00 00 63 06 DF 17 13 0F 00 00 @@ -29,7 +29,7 @@ B7 02 00 80 93 82 F2 FF 73 90 02 3B 93 02 F0 01 63 8A 02 00 73 90 52 10 B7 B2 00 00 93 82 92 10 73 90 22 30 73 50 00 30 97 02 00 00 93 82 42 01 73 90 12 34 73 25 40 F1 73 00 20 30 6F 00 00 02 -93 8F 1F 00 73 00 10 00 6F 20 80 37 93 8F 1F 00 +93 8F 1F 00 73 00 10 00 6F 20 80 44 93 8F 1F 00 73 00 10 00 13 04 14 00 73 00 20 30 93 08 00 00 73 00 00 00 93 08 10 00 73 00 00 00 93 04 00 00 13 09 00 01 33 85 04 00 B7 05 10 00 13 06 00 00 @@ -79,7 +79,7 @@ E3 9C 24 F9 13 05 00 00 93 05 00 00 37 06 04 00 73 10 40 3B 73 10 50 3B 73 10 60 3B 73 10 70 3B 73 10 80 3B 73 10 90 3B 73 10 A0 3B 73 10 B0 3B 73 10 C0 3B 73 10 D0 3B 73 10 E0 3B 73 10 F0 3B -6F 00 00 51 93 02 00 00 B7 0E 00 00 93 8E FE FF +6F 00 00 5E 93 02 00 00 B7 0E 00 00 93 8E FE FF 73 90 0E 3B 73 2F 00 3B 63 84 EE 01 6F E0 CF B4 73 10 00 3B B7 0E 00 00 93 8E FE FF 73 90 1E 3B 73 2F 10 3B 63 84 EE 01 6F E0 0F B3 73 10 10 3B @@ -114,51 +114,64 @@ B7 0E 00 00 93 8E FE FF 73 90 EE 3B 73 2F E0 3B B7 7E 77 77 93 8E 7E 77 73 90 2E 3A 73 2F 20 3A 63 84 EE 01 6F E0 4F 95 73 10 20 3A B7 7E 77 77 93 8E 7E 77 73 90 3E 3A 73 2F 30 3A 63 84 EE 01 -6F E0 8F 93 73 10 30 3A 6F 00 80 2D 37 0F 00 00 +6F E0 8F 93 73 10 30 3A 6F 00 80 3A 37 0F 00 00 13 0F 0F 08 F3 2E 00 30 B3 EE EE 01 73 90 0E 30 37 1F 00 00 13 0F 0F 80 F3 2E 40 30 B3 EE EE 01 -73 90 4E 30 6F 00 C0 2A 13 06 F6 FF 13 56 36 00 -93 D5 25 00 B3 E5 C5 00 6F 00 80 00 93 D5 25 00 -93 02 40 00 63 40 55 02 93 02 80 00 63 40 55 0A -93 02 C0 00 63 40 55 12 93 02 00 01 63 40 55 1A -6F 00 00 27 73 23 00 3A 93 02 00 00 63 8E A2 00 -93 02 10 00 63 82 A2 02 93 02 20 00 63 8A A2 02 -93 02 30 00 63 82 A2 04 73 90 05 3B 93 02 00 F0 -33 73 53 00 6F 00 C0 04 73 90 15 3B B7 02 FF FF +73 90 4E 30 6F 00 C0 37 F3 22 00 3A 13 03 F0 0F +93 D2 82 00 B3 F2 62 00 63 96 D2 00 13 05 00 00 +6F 00 00 36 13 05 10 00 6F 00 80 35 F3 22 00 30 +63 1A 05 00 37 03 FE FF 13 03 F3 FF B3 F2 62 00 +6F 00 C0 00 37 03 02 00 B3 E2 62 00 73 90 02 30 +6F 00 00 33 03 20 05 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 23 20 05 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 67 00 05 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +13 06 F6 FF 13 56 36 00 93 D5 25 00 B3 E5 C5 00 +6F 00 80 00 93 D5 25 00 93 02 40 00 63 40 55 02 +93 02 80 00 63 40 55 0A 93 02 C0 00 63 40 55 12 +93 02 00 01 63 40 55 1A 6F 00 80 29 73 23 00 3A +93 02 00 00 63 8E A2 00 93 02 10 00 63 82 A2 02 +93 02 20 00 63 8A A2 02 93 02 30 00 63 82 A2 04 +73 90 05 3B 93 02 00 F0 33 73 53 00 6F 00 C0 04 +73 90 15 3B B7 02 FF FF 93 82 F2 0F 33 73 53 00 +93 96 86 00 6F 00 40 03 73 90 25 3B B7 02 01 FF +93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 +73 90 35 3B B7 02 00 01 93 82 F2 FF 33 73 53 00 +93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 03 3A +6F 00 00 21 73 23 10 3A 93 02 40 00 63 8E A2 00 +93 02 50 00 63 82 A2 02 93 02 60 00 63 8A A2 02 +93 02 70 00 63 82 A2 04 73 90 45 3B 93 02 00 F0 +33 73 53 00 6F 00 C0 04 73 90 55 3B B7 02 FF FF 93 82 F2 0F 33 73 53 00 93 96 86 00 6F 00 40 03 -73 90 25 3B B7 02 01 FF 93 82 F2 FF 33 73 53 00 -93 96 06 01 6F 00 C0 01 73 90 35 3B B7 02 00 01 +73 90 65 3B B7 02 01 FF 93 82 F2 FF 33 73 53 00 +93 96 06 01 6F 00 C0 01 73 90 75 3B B7 02 00 01 93 82 F2 FF 33 73 53 00 93 96 86 01 6F 00 40 00 -33 63 D3 00 73 10 03 3A 6F 00 80 1E 73 23 10 3A -93 02 40 00 63 8E A2 00 93 02 50 00 63 82 A2 02 -93 02 60 00 63 8A A2 02 93 02 70 00 63 82 A2 04 -73 90 45 3B 93 02 00 F0 33 73 53 00 6F 00 C0 04 -73 90 55 3B B7 02 FF FF 93 82 F2 0F 33 73 53 00 -93 96 86 00 6F 00 40 03 73 90 65 3B B7 02 01 FF +33 63 D3 00 73 10 13 3A 6F 00 80 18 73 23 20 3A +93 02 80 00 63 8E A2 00 93 02 90 00 63 82 A2 02 +93 02 A0 00 63 8A A2 02 93 02 B0 00 63 82 A2 04 +73 90 85 3B 93 02 00 F0 33 73 53 00 6F 00 C0 04 +73 90 95 3B B7 02 FF FF 93 82 F2 0F 33 73 53 00 +93 96 86 00 6F 00 40 03 73 90 A5 3B B7 02 01 FF 93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 -73 90 75 3B B7 02 00 01 93 82 F2 FF 33 73 53 00 -93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 13 3A -6F 00 00 16 73 23 20 3A 93 02 80 00 63 8E A2 00 -93 02 90 00 63 82 A2 02 93 02 A0 00 63 8A A2 02 -93 02 B0 00 63 82 A2 04 73 90 85 3B 93 02 00 F0 -33 73 53 00 6F 00 C0 04 73 90 95 3B B7 02 FF FF +73 90 B5 3B B7 02 00 01 93 82 F2 FF 33 73 53 00 +93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 23 3A +6F 00 00 10 73 23 30 3A 93 02 C0 00 63 8E A2 00 +93 02 D0 00 63 82 A2 02 93 02 E0 00 63 8A A2 02 +93 02 F0 00 63 82 A2 04 73 90 C5 3B 93 02 00 F0 +33 73 53 00 6F 00 C0 04 73 90 D5 3B B7 02 FF FF 93 82 F2 0F 33 73 53 00 93 96 86 00 6F 00 40 03 -73 90 A5 3B B7 02 01 FF 93 82 F2 FF 33 73 53 00 -93 96 06 01 6F 00 C0 01 73 90 B5 3B B7 02 00 01 +73 90 E5 3B B7 02 01 FF 93 82 F2 FF 33 73 53 00 +93 96 06 01 6F 00 C0 01 73 90 F5 3B B7 02 00 01 93 82 F2 FF 33 73 53 00 93 96 86 01 6F 00 40 00 -33 63 D3 00 73 10 23 3A 6F 00 80 0D 73 23 30 3A -93 02 C0 00 63 8E A2 00 93 02 D0 00 63 82 A2 02 -93 02 E0 00 63 8A A2 02 93 02 F0 00 63 82 A2 04 -73 90 C5 3B 93 02 00 F0 33 73 53 00 6F 00 C0 04 -73 90 D5 3B B7 02 FF FF 93 82 F2 0F 33 73 53 00 -93 96 86 00 6F 00 40 03 73 90 E5 3B B7 02 01 FF -93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 -73 90 F5 3B B7 02 00 01 93 82 F2 FF 33 73 53 00 -93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 33 3A -6F 00 00 05 93 02 00 00 63 04 57 04 93 02 80 00 -E3 06 57 DA 93 02 00 01 E3 08 57 D8 93 02 80 01 -E3 04 57 D8 13 05 10 00 6F 00 80 02 93 0E 00 00 -E3 80 D8 AD 93 0E 10 00 E3 86 D8 B1 93 0E 80 00 -E3 82 D8 FD 93 0E 90 00 E3 8A D8 D3 6F 00 40 00 +33 63 D3 00 73 10 33 3A 6F 00 80 07 93 02 00 00 +63 08 57 06 93 02 80 00 E3 06 57 DA 93 02 00 01 +E3 08 57 D8 93 02 80 01 E3 04 57 D8 13 05 10 00 +6F 00 00 05 93 0E 00 00 E3 8C D8 A1 93 0E 10 00 +E3 82 D8 A7 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30 00 13 95 11 00 63 00 05 00 +13 65 15 00 73 00 00 00 13 05 10 00 73 00 00 00 +73 00 10 00 73 10 00 C0 +@80003128 41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C 3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20 diff --git a/test/priv_sec_testsuite/tests/rv64ui-v-test4.v b/test/priv_sec_testsuite/tests/rv64ui-v-test4.v index af05855..52016a7 100755 --- a/test/priv_sec_testsuite/tests/rv64ui-v-test4.v +++ b/test/priv_sec_testsuite/tests/rv64ui-v-test4.v @@ -9,8 +9,8 @@ 13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 13 0F 00 00 93 0F 00 00 97 02 00 00 93 82 02 F8 73 90 52 30 17 A1 00 00 13 01 C1 E4 F3 22 40 F1 -93 92 C2 00 33 01 51 00 73 10 01 34 EF 20 10 64 -17 35 00 00 13 05 05 E4 6F 20 00 6B 83 32 85 10 +93 92 C2 00 33 01 51 00 73 10 01 34 EF 20 90 71 +17 35 00 00 13 05 85 F1 6F 20 00 6B 83 32 85 10 73 90 12 14 83 30 85 00 03 31 05 01 83 31 85 01 03 32 05 02 83 32 85 02 03 33 05 03 83 33 85 03 03 34 05 04 83 34 85 04 83 35 85 05 03 36 05 06 @@ -114,11 +114,11 @@ E3 9C 07 FD 73 90 08 10 93 97 36 00 B3 06 F6 00 63 94 E5 04 93 96 36 00 B3 06 D6 00 23 B0 F6 00 73 00 05 12 83 30 81 00 13 01 01 01 67 80 00 00 93 E7 07 04 6F F0 1F FE 97 77 00 00 23 BC 07 B2 -6F F0 1F F0 17 15 00 00 13 05 45 B0 EF F0 1F D8 -13 05 30 00 EF F0 1F DC 17 15 00 00 13 05 85 B3 +6F F0 1F F0 17 15 00 00 13 05 C5 CB EF F0 1F D8 +13 05 30 00 EF F0 1F DC 17 15 00 00 13 05 05 CF EF F0 DF D6 13 05 30 00 EF F0 DF DA 17 15 00 00 -13 05 C5 B6 EF F0 9F D5 13 05 30 00 EF F0 9F D9 -17 15 00 00 13 05 05 B7 EF F0 5F D4 13 05 30 00 +13 05 45 D2 EF F0 9F D5 13 05 30 00 EF F0 9F D9 +17 15 00 00 13 05 85 D2 EF F0 5F D4 13 05 30 00 EF F0 5F D8 83 35 85 11 13 01 01 F8 23 38 81 06 23 3C 11 06 23 34 91 06 23 30 21 07 23 3C 31 05 23 38 41 05 23 34 51 05 23 30 61 05 23 3C 71 03 @@ -132,12 +132,12 @@ EF F0 5F D8 83 35 85 11 13 01 01 F8 23 38 81 06 03 3D 01 02 83 3D 81 01 13 01 01 08 6F D0 1F AF 03 37 85 10 93 77 37 00 63 98 07 06 EF 07 80 00 73 10 30 00 03 27 07 00 83 A7 07 00 63 0A F7 04 -13 05 10 10 93 07 10 04 97 16 00 00 93 86 86 AC +13 05 10 10 93 07 10 04 97 16 00 00 93 86 06 C8 17 F7 FF FF 13 07 07 A0 13 15 05 03 83 35 07 00 93 86 16 00 33 E6 A7 00 63 8A 05 00 97 F7 FF FF 23 B2 07 A2 83 37 07 00 E3 9A 07 FE 83 C7 06 00 23 30 C7 00 E3 9C 07 FC 13 05 30 00 EF F0 9F C6 -13 05 10 00 EF F0 1F C6 17 15 00 00 13 05 85 B1 +13 05 10 00 EF F0 1F C6 17 15 00 00 13 05 05 CD EF F0 DF C0 13 05 30 00 EF F0 DF C4 03 29 05 05 37 1C 00 00 97 24 00 00 93 84 C4 99 97 3B 00 00 93 8B 4B 99 37 0B 04 00 B7 0A E0 FF 97 7D 00 00 @@ -151,10 +151,10 @@ EF F0 DF C0 13 05 30 00 EF F0 DF C4 03 29 05 05 93 FC 0C 08 83 35 81 00 63 80 0C 04 37 16 00 00 13 05 0C 00 EF F0 DF 8F B3 87 84 00 73 10 0D 10 03 B7 0D 00 23 B0 07 00 E3 1E 07 F6 23 B0 FD 00 -23 30 FA 00 6F F0 9F F7 17 15 00 00 13 05 05 A6 -EF F0 DF B2 6F F0 5F F0 17 15 00 00 13 05 05 9F +23 30 FA 00 6F F0 9F F7 17 15 00 00 13 05 85 C1 +EF F0 DF B2 6F F0 5F F0 17 15 00 00 13 05 85 BA EF F0 DF B1 13 05 30 00 EF F0 DF B5 17 15 00 00 -13 05 45 9A EF F0 9F B0 13 05 30 00 EF F0 9F B4 +13 05 C5 B5 EF F0 9F B0 13 05 30 00 EF F0 9F B4 13 05 09 00 EF F0 1F B4 F3 27 40 F1 63 9A 07 18 97 57 00 00 93 87 07 89 13 01 01 ED 93 D7 C7 00 23 30 81 12 17 68 00 00 13 08 C8 87 13 04 05 00 @@ -186,50 +186,61 @@ E3 1A E3 FC 13 06 00 12 93 05 00 00 13 05 01 00 2F 20 07 00 13 D7 17 00 B3 C7 E7 00 93 97 E7 03 B3 F7 D7 00 B3 E7 E7 00 33 F7 C7 00 93 F5 17 00 33 07 A7 00 E3 9E 05 FC 03 20 07 00 6F F0 9F FD -17 15 00 00 13 05 85 86 EF F0 5F 90 13 05 30 00 +17 15 00 00 13 05 05 A2 EF F0 5F 90 13 05 30 00 EF F0 5F 94 73 10 00 3A 73 10 10 3A 73 10 20 3A 73 10 30 3A 73 10 00 3B 73 10 10 3B 73 10 20 3B 73 10 30 3B 73 10 40 3B 73 10 50 3B 73 10 60 3B 73 10 70 3B 73 10 80 3B 73 10 90 3B 73 10 A0 3B 73 10 B0 3B 73 10 C0 3B 73 10 D0 3B 73 10 E0 3B -73 10 F0 3B 6F 00 00 52 93 02 00 00 B7 0E 00 00 -93 8E FE FF 73 90 0E 3B 73 2F 00 3B 63 96 EE 5F +73 10 F0 3B 6F 00 80 5F 93 02 00 00 B7 0E 00 00 +93 8E FE FF 73 90 0E 3B 73 2F 00 3B 63 90 EE 7B 73 10 00 3B B7 0E 00 00 93 8E FE FF 73 90 1E 3B -73 2F 10 3B 63 9A EE 5D 73 10 10 3B B7 0E 00 00 -93 8E FE FF 73 90 2E 3B 73 2F 20 3B 63 9E EE 5B +73 2F 10 3B 63 94 EE 79 73 10 10 3B B7 0E 00 00 +93 8E FE FF 73 90 2E 3B 73 2F 20 3B 63 98 EE 77 73 10 20 3B B7 0E 00 00 93 8E FE FF 73 90 3E 3B -73 2F 30 3B 63 92 EE 5B 73 10 30 3B B7 0E 00 00 -93 8E FE FF 73 90 4E 3B 73 2F 40 3B 63 96 EE 59 +73 2F 30 3B 63 9C EE 75 73 10 30 3B B7 0E 00 00 +93 8E FE FF 73 90 4E 3B 73 2F 40 3B 63 90 EE 75 73 10 40 3B B7 0E 00 00 93 8E FE FF 73 90 5E 3B -73 2F 50 3B 63 9A EE 57 73 10 50 3B B7 0E 00 00 -93 8E FE FF 73 90 6E 3B 73 2F 60 3B 63 9E EE 55 +73 2F 50 3B 63 94 EE 73 73 10 50 3B B7 0E 00 00 +93 8E FE FF 73 90 6E 3B 73 2F 60 3B 63 98 EE 71 73 10 60 3B B7 0E 00 00 93 8E FE FF 73 90 7E 3B -73 2F 70 3B 63 92 EE 55 73 10 70 3B B7 0E 00 00 -93 8E FE FF 73 90 8E 3B 73 2F 80 3B 63 96 EE 53 +73 2F 70 3B 63 9C EE 6F 73 10 70 3B B7 0E 00 00 +93 8E FE FF 73 90 8E 3B 73 2F 80 3B 63 90 EE 6F 73 10 80 3B B7 0E 00 00 93 8E FE FF 73 90 9E 3B -73 2F 90 3B 63 9A EE 51 73 10 90 3B B7 0E 00 00 -93 8E FE FF 73 90 AE 3B 73 2F A0 3B 63 9E EE 4F +73 2F 90 3B 63 94 EE 6D 73 10 90 3B B7 0E 00 00 +93 8E FE FF 73 90 AE 3B 73 2F A0 3B 63 98 EE 6B 73 10 A0 3B B7 0E 00 00 93 8E FE FF 73 90 BE 3B -73 2F B0 3B 63 92 EE 4F 73 10 B0 3B B7 0E 00 00 -93 8E FE FF 73 90 CE 3B 73 2F C0 3B 63 96 EE 4D +73 2F B0 3B 63 9C EE 69 73 10 B0 3B B7 0E 00 00 +93 8E FE FF 73 90 CE 3B 73 2F C0 3B 63 90 EE 69 73 10 C0 3B B7 0E 00 00 93 8E FE FF 73 90 DE 3B -73 2F D0 3B 63 9A EE 4B 73 10 D0 3B B7 0E 00 00 -93 8E FE FF 73 90 EE 3B 73 2F E0 3B 63 9E EE 49 +73 2F D0 3B 63 94 EE 67 73 10 D0 3B B7 0E 00 00 +93 8E FE FF 73 90 EE 3B 73 2F E0 3B 63 98 EE 65 73 10 E0 3B B7 0E 00 00 93 8E FE FF 73 90 FE 3B -73 2F F0 3B 63 92 EE 49 73 10 F0 3B B7 7E 77 77 -93 8E 7E 77 73 90 0E 3A 73 2F 00 3A 63 96 EE 47 +73 2F F0 3B 63 9C EE 63 73 10 F0 3B B7 7E 77 77 +93 8E 7E 77 73 90 0E 3A 73 2F 00 3A 63 90 EE 63 73 10 00 3A B7 7E 77 77 93 8E 7E 77 73 90 1E 3A -73 2F 10 3A 63 9A EE 45 73 10 10 3A B7 7E 77 77 -93 8E 7E 77 73 90 2E 3A 73 2F 20 3A 63 9E EE 43 +73 2F 10 3A 63 94 EE 61 73 10 10 3A B7 7E 77 77 +93 8E 7E 77 73 90 2E 3A 73 2F 20 3A 63 98 EE 5F 73 10 20 3A B7 7E 77 77 93 8E 7E 77 73 90 3E 3A -73 2F 30 3A 63 92 EE 43 73 10 30 3A 6F 00 80 33 +73 2F 30 3A 63 9C EE 5D 73 10 30 3A 6F 00 00 41 37 0F 00 00 13 0F 0F 08 F3 2E 00 30 B3 EE EE 01 73 90 0E 30 37 1F 00 00 13 0F 0F 80 F3 2E 40 30 -B3 EE EE 01 73 90 4E 30 6F 00 C0 30 13 06 F6 FF +B3 EE EE 01 73 90 4E 30 6F 00 40 3E F3 22 00 3A +13 03 F0 0F 93 D2 82 00 B3 F2 62 00 63 96 D2 00 +13 05 00 00 6F 00 80 3C 13 05 10 00 6F 00 00 3C +F3 22 00 30 63 1E 05 00 37 83 00 00 1B 03 F3 FF +13 13 13 01 13 03 F3 FF B3 F2 62 00 6F 00 C0 00 +37 03 02 00 B3 E2 62 00 73 90 02 30 6F 00 00 39 +03 20 05 00 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 23 20 05 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 67 00 05 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 06 F6 FF 13 56 36 00 93 D5 25 00 B3 E5 C5 00 6F 00 80 00 93 D5 25 00 93 02 40 00 63 40 55 02 93 02 80 00 63 4C 55 0A 93 02 C0 00 63 48 55 14 93 02 00 01 -63 44 55 1E 6F 00 00 2D 73 23 00 3A 93 02 00 00 +63 44 55 1E 6F 00 80 2F 73 23 00 3A 93 02 00 00 63 8E A2 00 93 02 10 00 63 86 A2 02 93 02 20 00 63 82 A2 04 93 02 30 00 63 8E A2 04 73 90 05 3B 9B 02 10 00 93 92 02 02 93 82 02 F0 33 73 53 00 @@ -239,7 +250,7 @@ B3 EE EE 01 73 90 4E 30 6F 00 C0 30 13 06 F6 FF 93 92 02 01 93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 35 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01 6F 00 40 00 33 63 D3 00 -73 10 03 3A 6F 00 00 23 73 23 10 3A 93 02 40 00 +73 10 03 3A 6F 00 80 25 73 23 10 3A 93 02 40 00 63 8E A2 00 93 02 50 00 63 86 A2 02 93 02 60 00 63 82 A2 04 93 02 70 00 63 8E A2 04 73 90 45 3B 9B 02 10 00 93 92 02 02 93 82 02 F0 33 73 53 00 @@ -249,7 +260,7 @@ B3 EE EE 01 73 90 4E 30 6F 00 C0 30 13 06 F6 FF 93 92 02 01 93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 75 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01 6F 00 40 00 33 63 D3 00 -73 10 13 3A 6F 00 00 19 73 23 20 3A 93 02 80 00 +73 10 13 3A 6F 00 80 1B 73 23 20 3A 93 02 80 00 63 8E A2 00 93 02 90 00 63 86 A2 02 93 02 A0 00 63 82 A2 04 93 02 B0 00 63 8E A2 04 73 90 85 3B 9B 02 10 00 93 92 02 02 93 82 02 F0 33 73 53 00 @@ -259,7 +270,7 @@ B3 EE EE 01 73 90 4E 30 6F 00 C0 30 13 06 F6 FF 93 92 02 01 93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 B5 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01 6F 00 40 00 33 63 D3 00 -73 10 23 3A 6F 00 00 0F 73 23 30 3A 93 02 C0 00 +73 10 23 3A 6F 00 80 11 73 23 30 3A 93 02 C0 00 63 8E A2 00 93 02 D0 00 63 86 A2 02 93 02 E0 00 63 82 A2 04 93 02 F0 00 63 8E A2 04 73 90 C5 3B 9B 02 10 00 93 92 02 02 93 82 02 F0 33 73 53 00 @@ -269,29 +280,45 @@ B3 EE EE 01 73 90 4E 30 6F 00 C0 30 13 06 F6 FF 93 92 02 01 93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 F5 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01 6F 00 40 00 33 63 D3 00 -73 10 33 3A 6F 00 00 05 93 02 00 00 63 04 57 04 +73 10 33 3A 6F 00 80 07 93 02 00 00 63 08 57 06 93 02 80 00 E3 06 57 D4 93 02 00 01 E3 08 57 D2 -93 02 80 01 E3 04 57 D2 13 05 10 00 6F 00 80 02 -93 0E 00 00 E3 88 D8 AB 93 0E 10 00 E3 8E D8 AF -93 0E 80 00 E3 82 D8 FD 93 0E 90 00 E3 8A D8 CD -6F 00 40 00 F3 2E 10 34 93 8E 4E 00 73 90 1E 34 -73 00 20 30 13 0A 1A 00 73 00 20 30 67 80 00 00 -6F 00 40 05 93 8F 1F 00 73 00 10 00 6F F0 9F FD -93 8F 1F 00 73 00 10 00 13 09 19 00 73 24 20 34 -93 02 40 00 63 0A 54 00 93 02 60 00 63 06 54 00 -93 02 00 00 63 04 54 00 73 00 20 30 93 02 30 00 -63 94 22 09 97 02 00 00 93 82 C2 06 73 90 12 34 -6F F0 9F FE 13 05 00 00 93 05 00 00 37 06 04 00 +93 02 80 01 E3 04 57 D2 13 05 10 00 6F 00 00 05 +93 0E 00 00 E3 80 D8 A1 93 0E 10 00 E3 86 D8 A5 +93 0E 80 00 E3 82 D8 FD 93 0E 90 00 E3 82 D8 C3 +93 0E A0 00 E3 86 D8 C7 93 0E B0 00 E3 8A D8 C9 +93 0E C0 00 E3 88 D8 CB 93 0E D0 00 E3 86 D8 CD +93 0E E0 00 E3 84 D8 C3 6F 00 40 00 F3 2E 10 34 +93 8E 4E 00 73 90 1E 34 73 00 20 30 13 0A 1A 00 +73 00 20 30 67 80 00 00 6F 00 00 08 93 8F 1F 00 +73 00 10 00 6F F0 9F FD 93 8F 1F 00 73 00 10 00 +73 24 20 34 93 02 50 00 63 0A 54 00 93 02 70 00 +63 02 54 02 93 02 10 00 63 0A 54 02 13 09 19 00 +13 05 50 00 97 02 00 00 93 82 82 09 73 90 12 34 +6F 00 40 03 13 09 19 00 13 05 70 00 97 02 00 00 +93 82 C2 0B 73 90 12 34 6F 00 C0 01 13 09 19 00 +13 05 10 00 97 02 00 00 93 82 C2 0E 73 90 12 34 +6F 00 40 00 73 00 20 30 13 05 00 00 93 05 00 00 +37 06 04 00 93 06 F0 01 13 07 80 01 93 08 80 00 +73 00 00 00 13 04 00 00 13 05 10 00 93 08 A0 00 +73 00 00 00 13 05 10 00 B7 05 04 00 37 06 04 00 +93 06 C0 01 13 07 80 01 93 08 80 00 73 00 00 00 +37 05 04 00 93 08 B0 00 73 00 00 00 93 02 50 00 +63 16 A4 0C 93 02 10 00 63 12 59 0C 13 00 00 00 +13 05 10 00 B7 05 04 00 37 06 04 00 93 06 90 01 +13 07 80 01 93 08 80 00 73 00 00 00 37 05 04 00 +93 08 C0 00 73 00 00 00 93 02 70 00 63 18 A4 08 +93 02 20 00 63 14 59 08 13 00 00 00 13 05 10 00 +B7 05 04 00 37 06 04 00 93 06 B0 09 13 07 80 01 +93 08 80 00 73 00 00 00 93 02 30 01 37 03 04 00 +23 20 53 00 37 05 04 00 93 08 D0 00 73 00 00 00 +93 02 10 00 63 14 A4 04 93 02 30 00 63 10 59 04 +13 00 00 00 13 05 10 00 B7 05 04 00 13 06 00 02 93 06 F0 01 13 07 80 01 93 08 80 00 73 00 00 00 -13 04 00 00 93 02 10 00 23 A0 02 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -93 02 60 00 63 1A 54 02 93 02 30 00 03 A0 02 00 -93 02 40 00 63 12 54 02 93 02 20 00 67 80 02 00 -93 02 00 00 63 1A 54 00 93 02 30 00 63 16 59 00 -6F 00 80 01 63 1A 30 00 13 95 11 00 63 00 05 00 -13 65 15 00 73 00 00 00 13 05 10 00 73 00 00 00 -73 00 10 00 73 10 00 C0 -@80002FD8 +13 05 F0 01 93 08 E0 00 73 00 00 00 93 02 10 00 +63 16 55 00 6F 00 80 01 63 1A 30 00 13 95 11 00 +63 00 05 00 13 65 15 00 73 00 00 00 13 05 10 00 +73 00 00 00 73 00 10 00 73 10 00 C0 +@80003190 41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C 3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20 diff --git a/test/priv_sec_testsuite/tests/rv64ui/test4.S b/test/priv_sec_testsuite/tests/rv64ui/test4.S index 13d19b3..3335f63 100644 --- a/test/priv_sec_testsuite/tests/rv64ui/test4.S +++ b/test/priv_sec_testsuite/tests/rv64ui/test4.S @@ -9,10 +9,9 @@ #include "pmp.S" ###################################################################### -# Test 3: PMP permissions - -# Configure PMP and check permissions are correctly followed by the -# mpu and control/memfy units with U-mode +# Test 3: machine mode access fault +# +# Checks MPRV mstatus bit and PMP.LOCK to provoque access fault # # x31 is the error status register to trigger the testbench status # when encounter a problem during the testcase @@ -29,6 +28,7 @@ .equ MEIE_ON, 0x00000800 .equ MEIE_OFF, 0xFFFFF7FF +.equ NOP_INST, 0x00000013 RVTEST_RV64U RVTEST_CODE_BEGIN @@ -63,30 +63,40 @@ ILLEGAL_INSTRUCTION: EXP_SERVICE: - // increment error - addi s2, s2, 1 csrr s0, mcause - li t0, CAUSE_MISALIGNED_LOAD - beq s0, t0, EXP_MRET - li t0, CAUSE_MISALIGNED_STORE - beq s0, t0, EXP_MRET - li t0, CAUSE_MISALIGNED_FETCH + li t0, CAUSE_LOAD_ACCESS + beq s0, t0, EXP_LOAD_ACCESS + li t0, CAUSE_STORE_ACCESS + beq s0, t0, EXP_STORE_ACCESS + li t0, CAUSE_FETCH_ACCESS beq s0, t0, EXP_INST_FAULT -EXP_MRET: - mret +EXP_LOAD_ACCESS: + // increment error + addi s2, s2, 1 + li a0, CAUSE_LOAD_ACCESS + la t0, TEST1_CHECK + csrw mepc, t0 + j EXP_MRET + +EXP_STORE_ACCESS: + // increment error + addi s2, s2, 1 + li a0, CAUSE_STORE_ACCESS + la t0, TEST2_CHECK + csrw mepc, t0 + j EXP_MRET EXP_INST_FAULT: - // move back to test4 - li t0, 3 - bne t0, s2, fail -EXP_BACK3: - // replace mepc with TEST4_CHECK because - // it contains the access fault address + // increment error + addi s2, s2, 1 + li a0, CAUSE_FETCH_ACCESS la t0, TEST3_CHECK csrw mepc, t0 j EXP_MRET +EXP_MRET: + mret ################################################## @@ -111,53 +121,111 @@ TEST_SETUP: li s0, 0 -// Check store access misaligned +// Check machine mode experience an read access fault TEST1_SETUP: + // First set the MPRV bit in MSTATUS + li a0, 1 + li a7, SVC_MPRV + ecall + // enable a write only region + li a0, 1 // pmp number + li a1, S256K // base address + li a2, S256K // size + li a3, NAPOT_W // permissions + li a4, NAPOT // type + li a7, SVC_SETUP + ecall +// Request a read access TEST1: - // raise an exception, which will increment s0 - li t0, 1 - sw x0, 0(t0) - nop - nop - nop - nop - nop + li a0, S256K + li a7, SVC_READ + ecall +TEST1_CHECK: // Check the exception has been handled correctly - li t0, CAUSE_MISALIGNED_STORE - bne s0, t0, fail + li t0, CAUSE_LOAD_ACCESS + bne s0, a0, fail + li t0, 1 + bne s2, t0, fail TEST1_TEARDOWN: + nop -// Check load access misaligned +// Check machine mode experience an store access fault TEST2_SETUP: + // enable a read only region + li a0, 1 // pmp number + li a1, S256K // base address + li a2, S256K // size + li a3, NAPOT_R // permissions + li a4, NAPOT // type + li a7, SVC_SETUP + ecall TEST2: - // raise an exception, which will increment s0 - li t0, 3 - lw x0, 0(t0) + li a0, S256K + li a7, SVC_WRITE + ecall +TEST2_CHECK: // Check the exception has been handled correctly - li t0, CAUSE_MISALIGNED_LOAD - bne s0, t0, fail + li t0, CAUSE_STORE_ACCESS + bne s0, a0, fail + li t0, 2 + bne s2, t0, fail TEST2_TEARDOWN: + nop // Check execute access misaligned in u-mode TEST3_SETUP: + // enable a read only region + li a0, 1 // pmp number + li a1, S256K // base address + li a2, S256K // size + li a3, NAPOT_LRW // permissions + li a4, NAPOT // type + li a7, SVC_SETUP + ecall TEST3: - // raise an exception, which will increment s0 - li t0, 2 - jalr x0, 0(t0) + // Store a NOP instruction + li t0, NOP_INST + li t1, S256K + sw t0, 0(t1) + // Go jump in locked/read/write only region + li a0, S256K + li a7, SVC_EXE + ecall + TEST3_CHECK: - li t0, CAUSE_MISALIGNED_FETCH - bne s0, t0, fail + // Check the exception has been handled correctly + li t0, CAUSE_FETCH_ACCESS + bne s0, a0, fail li t0, 3 bne s2, t0, fail TEST3_TEARDOWN: + nop + +TEST4_SETUP: + // enable a read only region + li a0, 1 // pmp number + li a1, S256K // base address + li a2, 32 // size + li a3, NAPOT_RWX // permissions + li a4, NAPOT // type + li a7, SVC_SETUP + ecall +TEST4: + li a0, NAPOT_RWX + li a7, SVC_CHECK_REGION + ecall +TEST4_CHECK: + li t0, 1 + bne a0, t0, fail +TEST4_TEARDOWN: j pass TEST_PASSFAIL