From baed753eb0695e3f962af0019495f7d98bc89b64 Mon Sep 17 00:00:00 2001 From: Florentine Rosiere Date: Wed, 18 Dec 2024 11:43:52 +0100 Subject: [PATCH] #815 Add the possibility to specify in the assembling the side of which the SVC is regulating for hvdcs closes #815 Signed-off-by: Florentine Rosiere --- etc/xsd/assembling_dynaflow.xsd | 8 + .../Algo/include/HVDCDefinitionAlgorithm.h | 41 +- sources/Algo/src/HVDCDefinitionAlgorithm.cpp | 54 +- sources/Inputs/include/AssemblingDataBase.h | 9 +- sources/Inputs/include/HvdcLine.h | 2 +- sources/Inputs/src/AssemblingDataBase.cpp | 10 +- sources/Outputs/src/DydHvdc.cpp | 14 +- sources/Outputs/src/ParDynModel.cpp | 16 +- sources/Outputs/src/ParHvdc.cpp | 38 +- tests/algo/TestHvdcLineAlgo.cpp | 135 +++- tests/algo/res/assembling_test_hvdc_side2.xml | 53 ++ tests/inputs/TestAssemblingXmlDocument.cpp | 21 + tests/inputs/res/assembling.xml | 6 + tests/main/CMakeLists.txt | 1 + .../main/reference/hvdc_svc_side2/Network.par | 26 + .../TestIIDM_hvdc_svc_side2.dyd | 102 ++++ .../TestIIDM_hvdc_svc_side2.par | 200 ++++++ .../reference/hvdc_svc_side2/constraints.xml | 2 + .../hvdc_svc_side2/lostEquipments.xml | 2 + .../reference/hvdc_svc_side2/outputIIDM.xml | 575 ++++++++++++++++++ .../main/reference/hvdc_svc_side2/solver.par | 32 + tests/main/res/TestIIDM_hvdc_svc_side2.iidm | 567 +++++++++++++++++ tests/main/res/assembling_svc_hvdc_side2.xml | 34 ++ tests/main/res/config_hvdc_svc_side2.json | 9 + tests/main/res/setting_svc_hvdc_side2.xml | 32 + tests/outputs/TestDiagram.cpp | 12 +- tests/outputs/TestDyd.cpp | 10 +- tests/outputs/TestPar.cpp | 38 +- 28 files changed, 1969 insertions(+), 80 deletions(-) create mode 100644 tests/algo/res/assembling_test_hvdc_side2.xml create mode 100644 tests/main/reference/hvdc_svc_side2/Network.par create mode 100644 tests/main/reference/hvdc_svc_side2/TestIIDM_hvdc_svc_side2.dyd create mode 100644 tests/main/reference/hvdc_svc_side2/TestIIDM_hvdc_svc_side2.par create mode 100644 tests/main/reference/hvdc_svc_side2/constraints.xml create mode 100644 tests/main/reference/hvdc_svc_side2/lostEquipments.xml create mode 100644 tests/main/reference/hvdc_svc_side2/outputIIDM.xml create mode 100644 tests/main/reference/hvdc_svc_side2/solver.par create mode 100644 tests/main/res/TestIIDM_hvdc_svc_side2.iidm create mode 100644 tests/main/res/assembling_svc_hvdc_side2.xml create mode 100644 tests/main/res/config_hvdc_svc_side2.json create mode 100644 tests/main/res/setting_svc_hvdc_side2.xml diff --git a/etc/xsd/assembling_dynaflow.xsd b/etc/xsd/assembling_dynaflow.xsd index be0d1928..337b7475 100644 --- a/etc/xsd/assembling_dynaflow.xsd +++ b/etc/xsd/assembling_dynaflow.xsd @@ -120,8 +120,16 @@ SPDX-License-Identifier: MPL-2.0 --> + + + + + + + + diff --git a/sources/Algo/include/HVDCDefinitionAlgorithm.h b/sources/Algo/include/HVDCDefinitionAlgorithm.h index 5990c1df..7bfd7331 100644 --- a/sources/Algo/include/HVDCDefinitionAlgorithm.h +++ b/sources/Algo/include/HVDCDefinitionAlgorithm.h @@ -123,7 +123,13 @@ class HVDCDefinition { HvdcPVRpcl2Side1, HvdcPVDiagramPQRpcl2Side1, HvdcPVDanglingRpcl2Side1, - HvdcPVDanglingDiagramPQRpcl2Side1 + HvdcPVDanglingDiagramPQRpcl2Side1, + HvdcPVEmulationSetRpcl2Side2, + HvdcPVDiagramPQEmulationSetRpcl2Side2, + HvdcPVRpcl2Side2, + HvdcPVDiagramPQRpcl2Side2, + HvdcPVDanglingRpcl2Side2, + HvdcPVDanglingDiagramPQRpcl2Side2 }; /** @@ -135,7 +141,8 @@ class HVDCDefinition { model == HVDCModel::HvdcPTanPhiDiagramPQ || model == HVDCModel::HvdcPQPropDiagramPQ || model == HVDCModel::HvdcPQPropDiagramPQEmulationSet || model == HVDCModel::HvdcPVDiagramPQ || model == HVDCModel::HvdcPVDiagramPQEmulationSet || model == HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side1 || model == HVDCModel::HvdcPVDiagramPQRpcl2Side1 || - model == HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1; + model == HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1 || model == HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side2 || + model == HVDCModel::HvdcPVDiagramPQRpcl2Side2 || model == HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2; } /** @@ -145,7 +152,8 @@ class HVDCDefinition { bool hasEmulationModel() const { return model == HVDCModel::HvdcPQPropEmulationSet || model == HVDCModel::HvdcPQPropDiagramPQEmulationSet || model == HVDCModel::HvdcPVEmulationSet || model == HVDCModel::HvdcPVDiagramPQEmulationSet || model == HVDCModel::HvdcPVEmulationSetRpcl2Side1 || - model == HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side1; + model == HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side1 || model == HVDCModel::HvdcPVEmulationSetRpcl2Side2 || + model == HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side2; } /** @@ -164,7 +172,8 @@ class HVDCDefinition { bool hasDanglingModel() const { return model == HVDCModel::HvdcPTanPhiDangling || model == HVDCModel::HvdcPTanPhiDanglingDiagramPQ || model == HVDCModel::HvdcPQPropDangling || model == HVDCModel::HvdcPQPropDanglingDiagramPQ || model == HVDCModel::HvdcPVDangling || model == HVDCModel::HvdcPVDanglingDiagramPQ || - model == HVDCModel::HvdcPVDanglingRpcl2Side1 || model == HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1; + model == HVDCModel::HvdcPVDanglingRpcl2Side1 || model == HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1 || + model == HVDCModel::HvdcPVDanglingRpcl2Side2 || model == HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2; } /** * @brief test is the HVDC definition has a reactive power control loop 2 for connection to the secondary voltage control @@ -174,7 +183,19 @@ class HVDCDefinition { bool hasRpcl2() const { return model == HVDCModel::HvdcPVEmulationSetRpcl2Side1 || model == HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side1 || model == HVDCModel::HvdcPVRpcl2Side1 || model == HVDCModel::HvdcPVDiagramPQRpcl2Side1 || model == HVDCModel::HvdcPVDanglingRpcl2Side1 || - model == HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1; + model == HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1 || model == HVDCModel::HvdcPVEmulationSetRpcl2Side2 || + model == HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side2 || model == HVDCModel::HvdcPVRpcl2Side2 || model == HVDCModel::HvdcPVDiagramPQRpcl2Side2 || + model == HVDCModel::HvdcPVDanglingRpcl2Side2 || model == HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2; + } + /** + * @brief test is the HVDC definition has a reactive power control loop 2 for connection to the secondary voltage control + * + * @return @b true if the HVDC definition has a reactive power control loop 2 for connection to the secondary voltage control, @b false otherwise + */ + bool converterStationOnSide2() const { + return model == HVDCModel::HvdcPVEmulationSetRpcl2Side2 || model == HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side2 || + model == HVDCModel::HvdcPVRpcl2Side2 || model == HVDCModel::HvdcPVDiagramPQRpcl2Side2 || model == HVDCModel::HvdcPVDanglingRpcl2Side2 || + model == HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2; } /** @@ -201,18 +222,20 @@ class HVDCDefinition { * @param pSetPoint active power set-point of the hvdc line in MW * @param rdc dc resistance of the hvdc line in Ohm * @param lossFactors loss factors for converters 1 and 2 + * @param ConverterStationSide1 whether the side1 of the hvdc should be connected to the side1 of the network */ explicit HVDCDefinition(const HvdcLineId &id, const inputs::HvdcLine::ConverterType converterType, const ConverterId &converter1Id, const BusId &converter1BusId, const boost::optional &converter1VoltageRegulationOn, const ConverterId &converter2Id, const BusId &converter2BusId, const boost::optional &converter2VoltageRegulationOn, const Position position, const HVDCModel &model, const std::array &powerFactors, double pMax, const boost::optional &vscDefinition1, const boost::optional &vscDefinition2, const boost::optional &droop, const boost::optional &p0, - bool isConverter1Rectifier, const double vdcNom, const double pSetPoint, const double rdc, const std::array &lossFactors) + bool isConverter1Rectifier, const double vdcNom, const double pSetPoint, const double rdc, const std::array &lossFactors, + bool ConverterStationSide1) : id{id}, converterType{converterType}, converter1Id{converter1Id}, converter1BusId{converter1BusId}, converter1VoltageRegulationOn{converter1VoltageRegulationOn}, converter2Id{converter2Id}, converter2BusId{converter2BusId}, converter2VoltageRegulationOn{converter2VoltageRegulationOn}, position{position}, model{model}, powerFactors(powerFactors), pMax{pMax}, vscDefinition1(vscDefinition1), vscDefinition2(vscDefinition2), droop(droop), p0(p0), isConverter1Rectifier{isConverter1Rectifier}, vdcNom(vdcNom), - pSetPoint(pSetPoint), rdc(rdc), lossFactors(lossFactors) {} + pSetPoint(pSetPoint), rdc(rdc), lossFactors(lossFactors), ConverterStationSide1(ConverterStationSide1) {} const HvdcLineId id; ///< HvdcLine id const ConverterType converterType; ///< type of converter of the hvdc line @@ -235,6 +258,7 @@ class HVDCDefinition { const double pSetPoint; ///< active power set-point of the hvdc line in MW const double rdc; ///< dc resistance of the hvdc line in Ohm const std::array lossFactors; ///< loss factors for converters 1 and 2 + const bool ConverterStationSide1; ///< whether the side1 of the hvdc should be connected to the side1 of the network }; /// @brief HVDC line definitions @@ -328,7 +352,8 @@ class HVDCDefinitionAlgorithm { const inputs::NetworkManager::BusMapRegulating &busesToNumberOfRegulationMap_; ///< mapping of busId and the number of generators that regulates them const bool infiniteReactiveLimits_; ///< whether we use infinite reactive limits std::unordered_map> vscConverters_; ///< List of VSC converters to use - std::unordered_set hvdcLinesInSVC; ///< If a hvdc line id is in this map then it belongs to a secondary voltage control area + std::unordered_map + hvdcLinesInSVC_; ///< If a hvdc line id is in this map then it belongs to a secondary voltage control area }; } // namespace algo diff --git a/sources/Algo/src/HVDCDefinitionAlgorithm.cpp b/sources/Algo/src/HVDCDefinitionAlgorithm.cpp index 6d76b6cb..4b1c7ea9 100644 --- a/sources/Algo/src/HVDCDefinitionAlgorithm.cpp +++ b/sources/Algo/src/HVDCDefinitionAlgorithm.cpp @@ -33,7 +33,7 @@ HVDCDefinitionAlgorithm::HVDCDefinitionAlgorithm(HVDCLineDefinitions &hvdcLinesD if (manager.assembling().isSingleAssociation(macroConn.id)) { const auto &assoc = manager.assembling().getSingleAssociation(macroConn.id); if (assoc.hvdcLine) { - hvdcLinesInSVC.insert(assoc.hvdcLine.get().name); + hvdcLinesInSVC_[assoc.hvdcLine.get().name] = assoc.hvdcLine.get().converterStation1; } } } @@ -80,27 +80,39 @@ auto HVDCDefinitionAlgorithm::computeModelVSC(const inputs::HvdcLine &hvdcline, auto HVDCDefinitionAlgorithm::computeModel(const inputs::HvdcLine &hvdcline, HVDCDefinition::Position position, inputs::HvdcLine::ConverterType type) const -> HVDCModelDefinition { - const bool isInSVC = hvdcLinesInSVC.find(hvdcline.id) != hvdcLinesInSVC.end(); + const auto &itHvdc = hvdcLinesInSVC_.find(hvdcline.id); + const bool isInSVC = itHvdc != hvdcLinesInSVC_.end(); + const bool converterSide1 = isInSVC && itHvdc->second == inputs::AssemblingDataBase::HvdcLineConverterSide::SIDE1; if (position == HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT) { if (type == inputs::HvdcLine::ConverterType::LCC) { return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPTanPhi : HVDCDefinition::HVDCModel::HvdcPTanPhiDiagramPQ}; } else { const bool hvdcAngleDroopActivePowerControlIsEnabled = hvdcline.activePowerControl.has_value(); if (!hvdcAngleDroopActivePowerControlIsEnabled) { - if (isInSVC) - return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPVRpcl2Side1 - : HVDCDefinition::HVDCModel::HvdcPVDiagramPQRpcl2Side1}; - else + if (isInSVC) { + if (converterSide1) + return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPVRpcl2Side1 + : HVDCDefinition::HVDCModel::HvdcPVDiagramPQRpcl2Side1}; + else + return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPVRpcl2Side2 + : HVDCDefinition::HVDCModel::HvdcPVDiagramPQRpcl2Side2}; + } else { return computeModelVSC(hvdcline, position, HVDCDefinition::HVDCModel::HvdcPQProp, HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQ, HVDCDefinition::HVDCModel::HvdcPV, HVDCDefinition::HVDCModel::HvdcPVDiagramPQ); + } } else { - if (isInSVC) - return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPVEmulationSetRpcl2Side1 - : HVDCDefinition::HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side1}; - else + if (isInSVC) { + if (converterSide1) + return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPVEmulationSetRpcl2Side1 + : HVDCDefinition::HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side1}; + else + return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPVEmulationSetRpcl2Side2 + : HVDCDefinition::HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side2}; + } else { return computeModelVSC(hvdcline, position, HVDCDefinition::HVDCModel::HvdcPQPropEmulationSet, HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQEmulationSet, HVDCDefinition::HVDCModel::HvdcPVEmulationSet, HVDCDefinition::HVDCModel::HvdcPVDiagramPQEmulationSet); + } } } } else { @@ -109,12 +121,17 @@ auto HVDCDefinitionAlgorithm::computeModel(const inputs::HvdcLine &hvdcline, HVD return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPTanPhiDangling : HVDCDefinition::HVDCModel::HvdcPTanPhiDanglingDiagramPQ}; } else { - if (isInSVC) - return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side1 - : HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1}; - else + if (isInSVC) { + if (converterSide1) + return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side1 + : HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1}; + else + return HVDCModelDefinition{infiniteReactiveLimits_ ? HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side2 + : HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2}; + } else { return computeModelVSC(hvdcline, position, HVDCDefinition::HVDCModel::HvdcPQPropDangling, HVDCDefinition::HVDCModel::HvdcPQPropDanglingDiagramPQ, HVDCDefinition::HVDCModel::HvdcPVDangling, HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQ); + } } } } @@ -122,6 +139,7 @@ auto HVDCDefinitionAlgorithm::computeModel(const inputs::HvdcLine &hvdcline, HVD std::pair, bool> HVDCDefinitionAlgorithm::getOrCreateHvdcLineDefinition(const inputs::HvdcLine &hvdcLine) { auto &hvdcLines = hvdcLinesDefinitions_.hvdcLines; auto it = hvdcLines.find(hvdcLine.id); + const auto &hvdcIt = hvdcLinesInSVC_.find(hvdcLine.id); bool alreadyInserted = it != hvdcLines.end(); if (alreadyInserted) { return {std::ref(it->second), alreadyInserted}; @@ -145,12 +163,18 @@ std::pair, bool> HVDCDefinitionAlgorithm: voltageRegulation2 = converterVSC2->voltageRegulationOn; } + inputs::AssemblingDataBase::HvdcLineConverterSide side = inputs::AssemblingDataBase::HvdcLineConverterSide::SIDE1; // by default + // side 1 of dynamic model is connected to the side 1 of the static model + if (hvdcIt != hvdcLinesInSVC_.end()) { + side = hvdcIt->second; + } boost::optional droop = (hvdcLine.activePowerControl) ? hvdcLine.activePowerControl->droop : boost::optional(); boost::optional p0 = (hvdcLine.activePowerControl) ? hvdcLine.activePowerControl->p0 : boost::optional(); HVDCDefinition createdHvdcLine(hvdcLine.id, hvdcLine.converterType, hvdcLine.converter1->converterId, hvdcLine.converter1->busId, voltageRegulation1, hvdcLine.converter2->converterId, hvdcLine.converter2->busId, voltageRegulation2, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPTanPhi, powerFactors, hvdcLine.pMax, def1, - def2, droop, p0, hvdcLine.isConverter1Rectifier, hvdcLine.vdcNom, hvdcLine.pSetPoint, hvdcLine.rdc, hvdcLine.lossFactors); + def2, droop, p0, hvdcLine.isConverter1Rectifier, hvdcLine.vdcNom, hvdcLine.pSetPoint, hvdcLine.rdc, hvdcLine.lossFactors, + side == inputs::AssemblingDataBase::HvdcLineConverterSide::SIDE1); auto pair = hvdcLines.emplace(hvdcLine.id, createdHvdcLine); return {std::ref(pair.first->second), alreadyInserted}; } diff --git a/sources/Inputs/include/AssemblingDataBase.h b/sources/Inputs/include/AssemblingDataBase.h index eac3b75c..c0f3c564 100644 --- a/sources/Inputs/include/AssemblingDataBase.h +++ b/sources/Inputs/include/AssemblingDataBase.h @@ -32,6 +32,12 @@ namespace inputs { */ class AssemblingDataBase { public: + /// @brief Different tables in the diagram, qmin or qmax + enum class HvdcLineConverterSide { + SIDE1 = 0, ///< Side 1 + SIDE2 ///< Side 2 + }; + /** * @brief Connection XML element */ @@ -93,7 +99,8 @@ class AssemblingDataBase { * @brief Hvdc line XML element */ struct HvdcLine { - std::string name; ///< name of the Hvdc line + std::string name; ///< name of the Hvdc line + HvdcLineConverterSide converterStation1; ///< side of the network on which the side1 of the hvdc should be connected }; /** diff --git a/sources/Inputs/include/HvdcLine.h b/sources/Inputs/include/HvdcLine.h index bae07b8b..c9421a01 100644 --- a/sources/Inputs/include/HvdcLine.h +++ b/sources/Inputs/include/HvdcLine.h @@ -19,9 +19,9 @@ #include "Behaviours.h" +#include #include #include -#include namespace dfl { namespace inputs { diff --git a/sources/Inputs/src/AssemblingDataBase.cpp b/sources/Inputs/src/AssemblingDataBase.cpp index 4a791509..d3af808c 100644 --- a/sources/Inputs/src/AssemblingDataBase.cpp +++ b/sources/Inputs/src/AssemblingDataBase.cpp @@ -232,7 +232,15 @@ AssemblingDataBase::AssemblingXmlDocument::TfoHandler::TfoHandler(const elementN } AssemblingDataBase::AssemblingXmlDocument::HvdcLineHandler::HvdcLineHandler(const elementName_type &root) { - onStartElement(root, [this](const parser::ElementName &, const attributes_type &attributes) { currentHvdcLine->name = attributes["name"].as_string(); }); + onStartElement(root, [this](const parser::ElementName &, const attributes_type &attributes) { + currentHvdcLine->name = attributes["name"].as_string(); + currentHvdcLine->converterStation1 = AssemblingDataBase::HvdcLineConverterSide::SIDE1; + if (attributes.has("converterStation1")) { + if (attributes["converterStation1"].as_string() == "SIDE2") { + currentHvdcLine->converterStation1 = AssemblingDataBase::HvdcLineConverterSide::SIDE2; + } + } + }); } AssemblingDataBase::AssemblingXmlDocument::SingleShuntHandler::SingleShuntHandler(const elementName_type &root) { diff --git a/sources/Outputs/src/DydHvdc.cpp b/sources/Outputs/src/DydHvdc.cpp index 2d1f420d..5f33b49e 100644 --- a/sources/Outputs/src/DydHvdc.cpp +++ b/sources/Outputs/src/DydHvdc.cpp @@ -43,13 +43,19 @@ const std::unordered_map DydHvdc:: std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVRpcl2Side1, "HvdcPVRpcl2Side1"), std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVDiagramPQRpcl2Side1, "HvdcPVDiagramPQRpcl2Side1"), std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side1, "HvdcPVDanglingRpcl2Side1"), - std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1, "HvdcPVDanglingDiagramPQRpcl2Side1")}; + std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1, "HvdcPVDanglingDiagramPQRpcl2Side1"), + std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVEmulationSetRpcl2Side2, "HvdcPVEmulationSetRpcl2Side1"), + std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side2, "HvdcPVDiagramPQEmulationSetRpcl2Side1"), + std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVRpcl2Side2, "HvdcPVRpcl2Side1"), + std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVDiagramPQRpcl2Side2, "HvdcPVDiagramPQRpcl2Side1"), + std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side2, "HvdcPVDanglingRpcl2Side1"), + std::make_pair(algo::HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2, "HvdcPVDanglingDiagramPQRpcl2Side1")}; void DydHvdc::write(boost::shared_ptr &dynamicModelsToConnect, const std::string &basename) { for (const auto &keyValue : hvdcDefinitions_.hvdcLines) { auto hvdcLine = keyValue.second; auto blackBoxModel = helper::buildBlackBoxStaticId(hvdcLine.id, hvdcLine.id, hvdcModelsNames_.at(hvdcLine.model), basename + ".par", hvdcLine.id); - if (hvdcLine.position == algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT) { + if (hvdcLine.position == algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT || hvdcLine.converterStationOnSide2()) { blackBoxModel->addStaticRef("hvdc_PInj1Pu", "p2"); blackBoxModel->addStaticRef("hvdc_QInj1Pu", "q2"); blackBoxModel->addStaticRef("hvdc_state", "state2"); @@ -71,10 +77,12 @@ void DydHvdc::write(boost::shared_ptr &dyn } void DydHvdc::writeConnect(boost::shared_ptr &dynamicModelsToConnect, const algo::HVDCDefinition &hvdcLine) { - if (hvdcLine.position == algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT) { + if (hvdcLine.position == algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT || hvdcLine.converterStationOnSide2()) { dynamicModelsToConnect->addConnect(constants::networkModelName, hvdcLine.converter1BusId + "_ACPIN", hvdcLine.id, "hvdc_terminal2"); dynamicModelsToConnect->addConnect(constants::networkModelName, hvdcLine.converter2BusId + "_ACPIN", hvdcLine.id, "hvdc_terminal1"); dynamicModelsToConnect->addConnect(constants::networkModelName, hvdcLine.converter2BusId + "_switchOff", hvdcLine.id, "hvdc_switchOffSignal1Side1"); + if (hvdcLine.position == algo::HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT) + dynamicModelsToConnect->addConnect(constants::networkModelName, hvdcLine.converter1BusId + "_switchOff", hvdcLine.id, "hvdc_switchOffSignal1Side2"); } else { // case both : 1 <-> 1 and 2 <-> 2 dynamicModelsToConnect->addConnect(constants::networkModelName, hvdcLine.converter1BusId + "_ACPIN", hvdcLine.id, "hvdc_terminal1"); diff --git a/sources/Outputs/src/ParDynModel.cpp b/sources/Outputs/src/ParDynModel.cpp index 022d8c72..75dc2e79 100644 --- a/sources/Outputs/src/ParDynModel.cpp +++ b/sources/Outputs/src/ParDynModel.cpp @@ -56,8 +56,8 @@ boost::optional ParDynModel::getTransformerComponentId(const algo:: } std::shared_ptr ParDynModel::writeSVCParameterSet(const inputs::SettingDataBase::Set &set, - const inputs::DynamicDataBaseManager &dynamicDataBaseManager, - const algo::DynamicModelDefinition &automaton) { + const inputs::DynamicDataBaseManager &dynamicDataBaseManager, + const algo::DynamicModelDefinition &automaton) { auto new_set = parameters::ParametersSetFactory::newParametersSet(set.id); std::unordered_map regulatorIdToInitialIndex; @@ -143,9 +143,15 @@ std::shared_ptr ParDynModel::writeSVCParameterSet(con genInitialParamToValues["secondaryVoltageControl_Qr_" + std::to_string(it->second) + "_"])); } new_set->addParameter(helper::buildParameter("secondaryVoltageControl_Participate0_" + std::to_string(idx) + "_", true)); - new_set->addReference(helper::buildReference("secondaryVoltageControl_P0Pu_" + std::to_string(idx) + "_", "p1_pu", "DOUBLE", hvdcDefinition.id)); - new_set->addReference(helper::buildReference("secondaryVoltageControl_Q0Pu_" + std::to_string(idx) + "_", "q1_pu", "DOUBLE", hvdcDefinition.id)); - new_set->addReference(helper::buildReference("secondaryVoltageControl_U0Pu_" + std::to_string(idx) + "_", "v1_pu", "DOUBLE", hvdcDefinition.id)); + std::string side = "1"; + if (hvdcDefinition.converterStationOnSide2()) + side = "2"; + new_set->addReference( + helper::buildReference("secondaryVoltageControl_P0Pu_" + std::to_string(idx) + "_", "p" + side + "_pu", "DOUBLE", hvdcDefinition.id)); + new_set->addReference( + helper::buildReference("secondaryVoltageControl_Q0Pu_" + std::to_string(idx) + "_", "q" + side + "_pu", "DOUBLE", hvdcDefinition.id)); + new_set->addReference( + helper::buildReference("secondaryVoltageControl_U0Pu_" + std::to_string(idx) + "_", "v" + side + "_pu", "DOUBLE", hvdcDefinition.id)); assert(hvdcDefinition.vscDefinition1); if (hvdcDefinition.vscDefinition1->q < hvdcDefinition.vscDefinition1->qmax && hvdcDefinition.vscDefinition1->q > hvdcDefinition.vscDefinition1->qmin) { diff --git a/sources/Outputs/src/ParHvdc.cpp b/sources/Outputs/src/ParHvdc.cpp index 5fd7a135..380b6b80 100644 --- a/sources/Outputs/src/ParHvdc.cpp +++ b/sources/Outputs/src/ParHvdc.cpp @@ -26,9 +26,9 @@ void ParHvdc::write(boost::shared_ptr ¶ } std::shared_ptr ParHvdc::writeHdvcLine(const algo::HVDCDefinition &hvdcDefinition, const std::string &basename, - const boost::filesystem::path &dirname, - dfl::inputs::Configuration::StartingPointMode startingPointMode, - const inputs::DynamicDataBaseManager &dynamicDataBaseManager) { + const boost::filesystem::path &dirname, + dfl::inputs::Configuration::StartingPointMode startingPointMode, + const inputs::DynamicDataBaseManager &dynamicDataBaseManager) { auto dirnameDiagram = dirname; dirnameDiagram.append(basename + common::constants::diagramDirectorySuffix); @@ -82,7 +82,7 @@ std::shared_ptr ParHvdc::writeHdvcLine(const algo::HV auto set = parameters::ParametersSetFactory::newParametersSet(hvdcDefinition.id); std::string first = "1"; std::string second = "2"; - if (hvdcDefinition.position == dfl::algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT) { + if (hvdcDefinition.position == dfl::algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT || hvdcDefinition.converterStationOnSide2()) { first = "2"; second = "1"; } @@ -161,19 +161,25 @@ std::shared_ptr ParHvdc::writeHdvcLine(const algo::HV set->addParameter(helper::buildParameter("hvdc_Q2MaxPu", std::numeric_limits::max())); } else { const auto &hvdcConverterIdMain = - (hvdcDefinition.position == algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT) ? hvdcDefinition.converter2Id : hvdcDefinition.converter1Id; - size_t converterNumber = (hvdcDefinition.position == algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT) ? 2 : 1; + (hvdcDefinition.position == algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT || hvdcDefinition.converterStationOnSide2()) + ? hvdcDefinition.converter2Id + : hvdcDefinition.converter1Id; + size_t converterNumber = + (hvdcDefinition.position == algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT || hvdcDefinition.converterStationOnSide2()) ? 2 : 1; constexpr size_t parameterMainNumber = 1; updateHVDCParams(set, hvdcConverterIdMain, converterNumber, parameterMainNumber); if (hvdcDefinition.position == algo::HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT) { // always converter 2 on parameter number 2 to add in that case - updateHVDCParams(set, hvdcDefinition.converter2Id, 2, 2); + if (hvdcDefinition.converterStationOnSide2()) + updateHVDCParams(set, hvdcDefinition.converter1Id, 1, 2); + else + updateHVDCParams(set, hvdcDefinition.converter2Id, 2, 2); } } if (hvdcDefinition.converterType == dfl::inputs::HvdcLine::ConverterType::VSC) { - if (hvdcDefinition.position == dfl::algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT) { + if (hvdcDefinition.position == dfl::algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT || hvdcDefinition.converterStationOnSide2()) { set->addParameter(helper::buildParameter("hvdc_modeU10", hvdcDefinition.converter2VoltageRegulationOn.value())); set->addParameter(helper::buildParameter("hvdc_modeU20", hvdcDefinition.converter1VoltageRegulationOn.value())); set->addReference(helper::buildReference("hvdc_Q1Ref0Pu", "targetQ_pu", "DOUBLE", hvdcDefinition.converter2Id)); @@ -239,7 +245,7 @@ std::shared_ptr ParHvdc::writeHdvcLine(const algo::HV } if (hvdcDefinition.converterType == dfl::inputs::HvdcLine::ConverterType::LCC) { - if (hvdcDefinition.position == dfl::algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT) { + if (hvdcDefinition.position == dfl::algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT || hvdcDefinition.converterStationOnSide2()) { set->addReference(helper::buildReference("hvdc_CosPhi1Ref0", "powerFactor", "DOUBLE", hvdcDefinition.converter2Id)); set->addReference(helper::buildReference("hvdc_CosPhi2Ref0", "powerFactor", "DOUBLE", hvdcDefinition.converter1Id)); } else { @@ -257,13 +263,21 @@ std::shared_ptr ParHvdc::writeHdvcLine(const algo::HV set->addReference(helper::buildReference("hvdc_QPercent1", "qMax_pu", "DOUBLE", hvdcDefinition.converter2Id)); break; case dfl::algo::HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT: - set->addReference(helper::buildReference("hvdc_QPercent1", "qMax_pu", "DOUBLE", hvdcDefinition.converter1Id)); - set->addReference(helper::buildReference("hvdc_QPercent2", "qMax_pu", "DOUBLE", hvdcDefinition.converter2Id)); + if (hvdcDefinition.converterStationOnSide2()) { + set->addReference(helper::buildReference("hvdc_QPercent1", "qMax_pu", "DOUBLE", hvdcDefinition.converter2Id)); + set->addReference(helper::buildReference("hvdc_QPercent2", "qMax_pu", "DOUBLE", hvdcDefinition.converter1Id)); + } else { + set->addReference(helper::buildReference("hvdc_QPercent1", "qMax_pu", "DOUBLE", hvdcDefinition.converter1Id)); + set->addReference(helper::buildReference("hvdc_QPercent2", "qMax_pu", "DOUBLE", hvdcDefinition.converter2Id)); + } break; } } if (!hvdcDefinition.hasDanglingModel() && !hvdcDefinition.hasEmulationModel()) { - set->addReference(helper::buildReference("P1Ref_ValueIn", "p1_pu", "DOUBLE")); + if (hvdcDefinition.converterStationOnSide2()) + set->addReference(helper::buildReference("P1Ref_ValueIn", "p2_pu", "DOUBLE")); + else + set->addReference(helper::buildReference("P1Ref_ValueIn", "p1_pu", "DOUBLE")); } if (hvdcDefinition.hasEmulationModel()) { // Try to use AC emulation tFilter from the setting ddb (if provided in the ddb, use default value otherwise) diff --git a/tests/algo/TestHvdcLineAlgo.cpp b/tests/algo/TestHvdcLineAlgo.cpp index 32de0055..4453ef48 100644 --- a/tests/algo/TestHvdcLineAlgo.cpp +++ b/tests/algo/TestHvdcLineAlgo.cpp @@ -17,8 +17,8 @@ #include "HVDCDefinitionAlgorithm.h" #include "Tests.h" -#include #include +#include // Required for testing unit tests testing::Environment *initXmlEnvironment(); @@ -147,18 +147,18 @@ TEST(HvdcLine, base) { dfl::algo::HVDCDefinition("HVDCLCCLine", dfl::inputs::HvdcLine::ConverterType::LCC, "LCCStation1", "_BUS___11_TN", boost::none, "StationN", "_BUS___99_TN", boost::none, dfl::algo::HVDCDefinition::Position::FIRST_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDangling, {1., 99.}, 0., boost::none, boost::none, boost::none, boost::none, false, - 320, 322, 0.125, {0.01, 0.01}), + 320, 322, 0.125, {0.01, 0.01}, true), dfl::algo::HVDCDefinition( "HVDCVSCLine", dfl::inputs::HvdcLine::ConverterType::VSC, "StationN", "_BUS___99_TN", false, "VSCStation2", "_BUS___11_TN", false, dfl::algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDangling, {0., 0.}, 10., dfl::algo::VSCDefinition(dummyStationVSC->converterId, dummyStationVSC->qMax, dummyStationVSC->qMin, dummyStationVSC->qMin, 10., dummyStationVSC->points), dfl::algo::VSCDefinition(vscStation2->converterId, vscStation2->qMax, vscStation2->qMin, vscStation2->qMin, 10., vscStation2->points), boost::none, - boost::none, false, 320, 322, 0.125, {0.01, 0.01}), + boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true), dfl::algo::HVDCDefinition("HVDCLineBothInMain", dfl::inputs::HvdcLine::ConverterType::LCC, "LCCStationMain1", "_BUS__11_TN", boost::none, "LCCStationMain2", "_BUS__11_TN", boost::none, dfl::algo::HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDangling, {1., 2.}, 20., boost::none, boost::none, boost::none, boost::none, false, - 320, 322, 0.125, {0.01, 0.01}), + 320, 322, 0.125, {0.01, 0.01}, true), }; nodes[0]->converters.emplace_back(lccStation1); @@ -457,3 +457,130 @@ TEST(HvdcLine, modelsSVC) { ASSERT_EQ(hvdcLines.at("HVDCVSCLineSwitch1").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1); ASSERT_EQ(hvdcLines.at("HVDCVSCLineSwitch2").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side1); } + +TEST(HvdcLine, modelsSVCSide2) { + auto testServiceManager = boost::make_shared(); + auto vl = std::make_shared("VL"); + std::vector> nodes{ + dfl::inputs::Node::build("0", vl, 98.0, {}, false, testServiceManager), dfl::inputs::Node::build("1", vl, 111.0, {}, false, testServiceManager), + dfl::inputs::Node::build("2", vl, 24.0, {}, false, testServiceManager), dfl::inputs::Node::build("3", vl, 63.0, {}, false, testServiceManager), + dfl::inputs::Node::build("4", vl, 56.0, {}, false, testServiceManager), dfl::inputs::Node::build("5", vl, 46.0, {}, false, testServiceManager), + dfl::inputs::Node::build("6", vl, 0.0, {}, false, testServiceManager), dfl::inputs::Node::build("7", vl, 0.0, {}, false, testServiceManager), + dfl::inputs::Node::build("8", vl, 0.0, {}, false, testServiceManager), dfl::inputs::Node::build("9", vl, 0.0, {}, false, testServiceManager), + dfl::inputs::Node::build("10", vl, 0.0, {}, false, testServiceManager), dfl::inputs::Node::build("11", vl, 0.0, {}, false, testServiceManager), + dfl::inputs::Node::build("12", vl, 0.0, {}, false, testServiceManager), + }; + std::vector emptyPoints{}; + + auto activeControl = boost::optional(dfl::inputs::HvdcLine::ActivePowerControl(10., 5.)); + + auto dummyStation = std::make_shared("StationN", "_BUS___99_TN", nullptr, 1.); + auto dummyStationVSC = std::make_shared("StationN", "_BUS___99_TN", nullptr, false, 0., 0., 0., emptyPoints); + auto lccStation1 = std::make_shared("LCCStation1", "0", nullptr, 1.); + auto lccStation3 = std::make_shared("LCCStation3", "3", nullptr, 1.); + auto lccStation4 = std::make_shared("LCCStation4", "4", nullptr, 1.); + auto vscStation1 = std::make_shared("VSCStation1", "1", nullptr, false, 1.1, 1., 1., emptyPoints); + auto vscStation2 = std::make_shared("VSCStation2", "2", nullptr, true, 2.1, 2., 2., emptyPoints); + auto vscStation21 = std::make_shared("VSCStation21", "2", nullptr, true, 2.1, 2., 2., emptyPoints); + auto vscStation22 = std::make_shared("VSCStation22", "2", nullptr, true, 2.1, 2., 2., emptyPoints); + auto vscStation23 = std::make_shared("VSCStation23", "2", nullptr, true, 2.1, 2., 2., emptyPoints); + auto vscStation5 = std::make_shared("VSCStation5", "5", nullptr, true, 5.1, 5., 5., emptyPoints); + auto vscStation6 = std::make_shared("VSCStation6", "6", nullptr, true, 6.1, 6., 6., emptyPoints); + auto vscStation7 = std::make_shared("VSCStation7", "7", nullptr, true, 7.1, 7., 7., emptyPoints); + auto vscStation8 = std::make_shared("VSCStation8", "8", nullptr, true, 8.1, 8., 8., emptyPoints); + auto vscStation9 = std::make_shared("VSCStation9", "9", nullptr, true, 9.1, 9., 9., emptyPoints); + auto vscStation10 = std::make_shared("VSCStation10", "10", nullptr, true, 10.1, 10., 10., emptyPoints); + auto vscStation11 = std::make_shared("VSCStation11", "11", nullptr, true, 11.1, 11., 11., emptyPoints); + auto vscStation12 = std::make_shared("VSCStation12", "12", nullptr, true, 12.1, 12., 12., emptyPoints); + auto hvdcLineLCC = dfl::inputs::HvdcLine::build("HVDCLCCLine", dfl::inputs::HvdcLine::ConverterType::LCC, lccStation1, dummyStation, boost::none, 0, false, + 320, 322, 0.125, {0.01, 0.01}); // first is in main cc + auto hvdcLineVSC = dfl::inputs::HvdcLine::build("HVDCVSCLine", dfl::inputs::HvdcLine::ConverterType::VSC, vscStation1, dummyStationVSC, boost::none, 1, false, + 320, 322, 0.125, {0.01, 0.01}); // first in main cc + auto hvdcLineVSC2 = dfl::inputs::HvdcLine::build("HVDCVSCLine2", dfl::inputs::HvdcLine::ConverterType::VSC, dummyStationVSC, vscStation2, boost::none, 2, + false, 320, 322, 0.125, {0.01, 0.01}); // second in main cc + auto hvdcLineVSC3 = dfl::inputs::HvdcLine::build("HVDCVSCLine3", dfl::inputs::HvdcLine::ConverterType::VSC, vscStation21, dummyStationVSC, boost::none, 2, + false, 320, 322, 0.125, {0.01, 0.01}); // first in main cc + auto hvdcLineBothInMainComponent = dfl::inputs::HvdcLine::build("HVDCLineBothInMain1", dfl::inputs::HvdcLine::ConverterType::LCC, lccStation3, lccStation4, + boost::none, 3.4, false, 320, 322, 0.125, {0.01, 0.01}); // both in main cc + auto hvdcLineBothInMainComponent2 = dfl::inputs::HvdcLine::build("HVDCLineBothInMain2", dfl::inputs::HvdcLine::ConverterType::VSC, vscStation5, vscStation6, + activeControl, 5.6, false, 320, 322, 0.125, {0.01, 0.01}); // both in main cc + auto hvdcLineBothInMainComponent3 = dfl::inputs::HvdcLine::build("HVDCLineBothInMain3", dfl::inputs::HvdcLine::ConverterType::VSC, vscStation22, vscStation7, + activeControl, 2.7, false, 320, 322, 0.125, {0.01, 0.01}); // both in main cc + auto hvdcLineBothInMainComponent4 = dfl::inputs::HvdcLine::build("HVDCLineBothInMain4", dfl::inputs::HvdcLine::ConverterType::VSC, vscStation9, vscStation10, + boost::none, 9.10, false, 320, 322, 0.125, {0.01, 0.01}); // both in main cc + auto hvdcLineBothInMainComponent5 = dfl::inputs::HvdcLine::build("HVDCLineBothInMain5", dfl::inputs::HvdcLine::ConverterType::VSC, vscStation23, vscStation8, + boost::none, 2.8, false, 320, 322, 0.125, {0.01, 0.01}); // both in main cc + auto hvdcLineVSCSwitch1 = dfl::inputs::HvdcLine::build("HVDCVSCLineSwitch1", dfl::inputs::HvdcLine::ConverterType::VSC, vscStation11, dummyStationVSC, + boost::none, 11, false, 320, 322, 0.125, {0.01, 0.01}); // first in main cc + auto hvdcLineVSCSwitch2 = dfl::inputs::HvdcLine::build("HVDCVSCLineSwitch2", dfl::inputs::HvdcLine::ConverterType::VSC, vscStation12, dummyStationVSC, + boost::none, 12, false, 320, 322, 0.125, {0.01, 0.01}); // first in main cc + nodes[0]->converters.push_back(lccStation1); + nodes[1]->converters.push_back(vscStation1); + nodes[2]->converters.push_back(vscStation2); + nodes[2]->converters.push_back(vscStation21); + nodes[2]->converters.push_back(vscStation22); + nodes[2]->converters.push_back(vscStation23); + nodes[3]->converters.push_back(lccStation3); + nodes[4]->converters.push_back(lccStation4); + nodes[5]->converters.push_back(vscStation5); + nodes[6]->converters.push_back(vscStation6); + nodes[7]->converters.push_back(vscStation7); + nodes[8]->converters.push_back(vscStation8); + nodes[9]->converters.push_back(vscStation9); + nodes[10]->converters.push_back(vscStation10); + nodes[11]->converters.push_back(vscStation11); + nodes[12]->converters.push_back(vscStation12); + + testServiceManager->add("11", vl->id, "12"); + + dfl::inputs::NetworkManager::BusMapRegulating busMap{std::make_pair("2", dfl::inputs::NetworkManager::NbOfRegulating::MULTIPLES), + std::make_pair("11", dfl::inputs::NetworkManager::NbOfRegulating::MULTIPLES), + std::make_pair("12", dfl::inputs::NetworkManager::NbOfRegulating::MULTIPLES)}; + + dfl::algo::HVDCLineDefinitions hvdcDefs; + bool useReactiveLimits = true; + std::unordered_set> set{ + vscStation1, vscStation2, vscStation21, vscStation22, vscStation23, vscStation5, vscStation6, + vscStation7, vscStation8, vscStation9, vscStation10, vscStation11, vscStation12, + }; + dfl::inputs::DynamicDataBaseManager manager("", "res/assembling_test_hvdc_side2.xml"); + dfl::algo::HVDCDefinitionAlgorithm algo(hvdcDefs, busMap, useReactiveLimits, set, manager); + std::shared_ptr algoRes(new dfl::algo::AlgorithmsResults()); + for (const auto &node : nodes) { + algo(node, algoRes); + } + + auto &hvdcLines = hvdcDefs.hvdcLines; + ASSERT_EQ(hvdcLines.size(), 11); + ASSERT_EQ(hvdcLines.at("HVDCLCCLine").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPTanPhiDangling); + ASSERT_EQ(hvdcLines.at("HVDCVSCLine2").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCVSCLine3").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCLineBothInMain1").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPTanPhi); + ASSERT_EQ(hvdcLines.at("HVDCLineBothInMain2").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVEmulationSetRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCLineBothInMain3").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVEmulationSetRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCLineBothInMain4").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCLineBothInMain5").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCVSCLineSwitch1").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCVSCLineSwitch2").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side2); + + hvdcLines.clear(); + // case diagrams + useReactiveLimits = false; + dfl::algo::HVDCDefinitionAlgorithm algo2(hvdcDefs, busMap, useReactiveLimits, set, manager); + for (const auto &node : nodes) { + algo2(node, algoRes); + } + + ASSERT_EQ(hvdcLines.size(), 11); + ASSERT_EQ(hvdcLines.at("HVDCLCCLine").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPTanPhiDanglingDiagramPQ); + ASSERT_EQ(hvdcLines.at("HVDCVSCLine").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCVSCLine2").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCVSCLine3").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCLineBothInMain1").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPTanPhiDiagramPQ); + ASSERT_EQ(hvdcLines.at("HVDCLineBothInMain2").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCLineBothInMain3").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDiagramPQEmulationSetRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCLineBothInMain4").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDiagramPQRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCLineBothInMain5").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDiagramPQRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCVSCLineSwitch1").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2); + ASSERT_EQ(hvdcLines.at("HVDCVSCLineSwitch2").model, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQRpcl2Side2); +} diff --git a/tests/algo/res/assembling_test_hvdc_side2.xml b/tests/algo/res/assembling_test_hvdc_side2.xml new file mode 100644 index 00000000..d04d3d1e --- /dev/null +++ b/tests/algo/res/assembling_test_hvdc_side2.xml @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/inputs/TestAssemblingXmlDocument.cpp b/tests/inputs/TestAssemblingXmlDocument.cpp index feffe378..02dc9155 100644 --- a/tests/inputs/TestAssemblingXmlDocument.cpp +++ b/tests/inputs/TestAssemblingXmlDocument.cpp @@ -72,6 +72,8 @@ TEST(AssemblingXmlDocument, readFile) { ASSERT_NO_THROW(assembling.getSingleAssociation("MESURE_I_SALON")); ASSERT_NO_THROW(assembling.getSingleAssociation("ORDER_SALON")); ASSERT_NO_THROW(assembling.getSingleAssociation("HVDC_LINE")); + ASSERT_NO_THROW(assembling.getSingleAssociation("HVDC_LINE_SIDE1")); + ASSERT_NO_THROW(assembling.getSingleAssociation("HVDC_LINE_SIDE2")); auto singleAssoc = assembling.getSingleAssociation("MESURE_MODELE_1_VL4"); ASSERT_EQ(singleAssoc.id, "MESURE_MODELE_1_VL4"); ASSERT_FALSE(singleAssoc.line); @@ -112,6 +114,25 @@ TEST(AssemblingXmlDocument, readFile) { ASSERT_FALSE(singleAssoc.line); ASSERT_FALSE(singleAssoc.shunt); ASSERT_EQ(singleAssoc.hvdcLine->name, "MyHvdc"); + ASSERT_EQ(singleAssoc.hvdcLine->converterStation1, dfl::inputs::AssemblingDataBase::HvdcLineConverterSide::SIDE1); + singleAssoc = assembling.getSingleAssociation("HVDC_LINE_SIDE1"); + ASSERT_EQ(singleAssoc.id, "HVDC_LINE_SIDE1"); + ASSERT_FALSE(singleAssoc.bus); + ASSERT_TRUE(singleAssoc.hvdcLine); + ASSERT_FALSE(singleAssoc.tfo); + ASSERT_FALSE(singleAssoc.line); + ASSERT_FALSE(singleAssoc.shunt); + ASSERT_EQ(singleAssoc.hvdcLine->name, "MyHvdc"); + ASSERT_EQ(singleAssoc.hvdcLine->converterStation1, dfl::inputs::AssemblingDataBase::HvdcLineConverterSide::SIDE1); + singleAssoc = assembling.getSingleAssociation("HVDC_LINE_SIDE2"); + ASSERT_EQ(singleAssoc.id, "HVDC_LINE_SIDE2"); + ASSERT_FALSE(singleAssoc.bus); + ASSERT_TRUE(singleAssoc.hvdcLine); + ASSERT_FALSE(singleAssoc.tfo); + ASSERT_FALSE(singleAssoc.line); + ASSERT_FALSE(singleAssoc.shunt); + ASSERT_EQ(singleAssoc.hvdcLine->name, "MyHvdc"); + ASSERT_EQ(singleAssoc.hvdcLine->converterStation1, dfl::inputs::AssemblingDataBase::HvdcLineConverterSide::SIDE2); ASSERT_THROW_DYNAWO(assembling.getMultipleAssociation("dummy"), DYN::Error::GENERAL, dfl::KeyError_t::UnknownMultiAssoc); ASSERT_NO_THROW(assembling.getMultipleAssociation("SHUNTS_MODELE_1_VL4")); diff --git a/tests/inputs/res/assembling.xml b/tests/inputs/res/assembling.xml index 235b5c46..57482472 100644 --- a/tests/inputs/res/assembling.xml +++ b/tests/inputs/res/assembling.xml @@ -59,6 +59,12 @@ + + + + + + diff --git a/tests/main/CMakeLists.txt b/tests/main/CMakeLists.txt index 7345d2ec..8fb53e15 100644 --- a/tests/main/CMakeLists.txt +++ b/tests/main/CMakeLists.txt @@ -54,6 +54,7 @@ DEFINE_LAUNCH_TEST(hvdc_HvdcPQPropDangling_diagrams) DEFINE_LAUNCH_TEST(hvdc_HvdcPV_HvdcPTanPhi_diagrams) DEFINE_LAUNCH_TEST(hvdc_HvdcPVDangling_HvdcPTanPhiDangling_diagrams) DEFINE_LAUNCH_TEST(hvdc_svc) +DEFINE_LAUNCH_TEST(hvdc_svc_side2) DEFINE_LAUNCH_TEST(distant_regulation) diff --git a/tests/main/reference/hvdc_svc_side2/Network.par b/tests/main/reference/hvdc_svc_side2/Network.par new file mode 100644 index 00000000..68f04883 --- /dev/null +++ b/tests/main/reference/hvdc_svc_side2/Network.par @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/main/reference/hvdc_svc_side2/TestIIDM_hvdc_svc_side2.dyd b/tests/main/reference/hvdc_svc_side2/TestIIDM_hvdc_svc_side2.dyd new file mode 100644 index 00000000..66e46565 --- /dev/null +++ b/tests/main/reference/hvdc_svc_side2/TestIIDM_hvdc_svc_side2.dyd @@ -0,0 +1,102 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/main/reference/hvdc_svc_side2/TestIIDM_hvdc_svc_side2.par b/tests/main/reference/hvdc_svc_side2/TestIIDM_hvdc_svc_side2.par new file mode 100644 index 00000000..f83d0e7a --- /dev/null +++ b/tests/main/reference/hvdc_svc_side2/TestIIDM_hvdc_svc_side2.par @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/main/reference/hvdc_svc_side2/constraints.xml b/tests/main/reference/hvdc_svc_side2/constraints.xml new file mode 100644 index 00000000..cbbcff11 --- /dev/null +++ b/tests/main/reference/hvdc_svc_side2/constraints.xml @@ -0,0 +1,2 @@ + + diff --git a/tests/main/reference/hvdc_svc_side2/lostEquipments.xml b/tests/main/reference/hvdc_svc_side2/lostEquipments.xml new file mode 100644 index 00000000..caee57c0 --- /dev/null +++ b/tests/main/reference/hvdc_svc_side2/lostEquipments.xml @@ -0,0 +1,2 @@ + + diff --git a/tests/main/reference/hvdc_svc_side2/outputIIDM.xml b/tests/main/reference/hvdc_svc_side2/outputIIDM.xml new file mode 100644 index 00000000..8a5ca0e3 --- /dev/null +++ b/tests/main/reference/hvdc_svc_side2/outputIIDM.xml @@ -0,0 +1,575 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/main/reference/hvdc_svc_side2/solver.par b/tests/main/reference/hvdc_svc_side2/solver.par new file mode 100644 index 00000000..5b1e3abd --- /dev/null +++ b/tests/main/reference/hvdc_svc_side2/solver.par @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/main/res/TestIIDM_hvdc_svc_side2.iidm b/tests/main/res/TestIIDM_hvdc_svc_side2.iidm new file mode 100644 index 00000000..f72ec614 --- /dev/null +++ b/tests/main/res/TestIIDM_hvdc_svc_side2.iidm @@ -0,0 +1,567 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/main/res/assembling_svc_hvdc_side2.xml b/tests/main/res/assembling_svc_hvdc_side2.xml new file mode 100644 index 00000000..5d2de99f --- /dev/null +++ b/tests/main/res/assembling_svc_hvdc_side2.xml @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/main/res/config_hvdc_svc_side2.json b/tests/main/res/config_hvdc_svc_side2.json new file mode 100644 index 00000000..33e65691 --- /dev/null +++ b/tests/main/res/config_hvdc_svc_side2.json @@ -0,0 +1,9 @@ +{ + "dfl-config": { + "OutputDir": "../resultsTestsTmp/hvdc_svc_side2", + "DsoVoltageLevel": 600, + "InfiniteReactiveLimits": true, + "SettingPath": "../res/setting_svc_hvdc_side2.xml", + "AssemblingPath": "../res/assembling_svc_hvdc_side2.xml" + } + } diff --git a/tests/main/res/setting_svc_hvdc_side2.xml b/tests/main/res/setting_svc_hvdc_side2.xml new file mode 100644 index 00000000..284e4764 --- /dev/null +++ b/tests/main/res/setting_svc_hvdc_side2.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/outputs/TestDiagram.cpp b/tests/outputs/TestDiagram.cpp index 94d683e4..1667a527 100644 --- a/tests/outputs/TestDiagram.cpp +++ b/tests/outputs/TestDiagram.cpp @@ -175,15 +175,15 @@ TEST(Diagram, writeVSC) { std::make_pair("0", HVDCDefinition("HVDCVSCLine", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation1", "_BUS___11_TN", false, "VSCStation99", "_BUS___99_TN", false, HVDCDefinition::Position::FIRST_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQ, - {}, 0., vscStation1, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01})), + {}, 0., vscStation1, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true)), std::make_pair("1", HVDCDefinition("HVDCVSCLine1", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation99", "_BUS___99_TN", false, "VSCStation2", "_BUS___12_TN", false, HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQEmulationSet, {}, 0., boost::none, vscStation2, boost::none, boost::none, - false, 320, 322, 0.125, {0.01, 0.01})), + false, 320, 322, 0.125, {0.01, 0.01}, true)), std::make_pair("2", HVDCDefinition("HVDCVSCLine2", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation3", "_BUS___13_TN", false, "VSCStation4", "_BUS___14_TN", false, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPVDanglingDiagramPQ, - {}, 0., vscStation3, vscStation4, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01})), + {}, 0., vscStation3, vscStation4, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true)), }; dfl::algo::HVDCLineDefinitions defs{map}; std::vector generators; @@ -225,15 +225,15 @@ TEST(Diagram, writeLCC) { std::make_pair("0", HVDCDefinition("HVDCLCCLine", HVDCDefinition::ConverterType::LCC, "LCCStation1", "_BUS___11_TN", false, "LCCStation99", "_BUS___99_TN", false, HVDCDefinition::Position::FIRST_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQ, {0.5, 0.5}, 0., - boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01})), + boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true)), std::make_pair("1", HVDCDefinition("HVDCLCCLine1", HVDCDefinition::ConverterType::LCC, "LCCStation99", "_BUS___99_TN", false, "LCCStation11", "_BUS___11_TN", false, HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQ, {0.5, 0.5}, 10., - boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01})), + boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true)), std::make_pair("2", HVDCDefinition("HVDCLCCLine2", HVDCDefinition::ConverterType::LCC, "LCCStation12", "_BUS___12_TN", false, "LCCStation2", "_BUS___22_TN", false, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQ, {0.5, 0.5}, 10., - boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01})), + boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true)), }; dfl::algo::HVDCLineDefinitions defs{map}; diff --git a/tests/outputs/TestDyd.cpp b/tests/outputs/TestDyd.cpp index cede319b..34411ea6 100644 --- a/tests/outputs/TestDyd.cpp +++ b/tests/outputs/TestDyd.cpp @@ -133,10 +133,10 @@ TEST(Dyd, writeHvdc) { auto hvdcLineLCC = HVDCDefinition("HVDCLCCLine", dfl::inputs::HvdcLine::ConverterType::LCC, "LCCStation1", "_BUS___11_TN", false, "LCCStation2", "_BUS___10_TN", false, HVDCDefinition::Position::FIRST_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPTanPhiDangling, - {}, 0., boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + {}, 0., boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC = HVDCDefinition("HVDCVSCLine", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation1", "_BUS___10_TN", true, "VSCStation2", "_BUS___11_TN", false, HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPVDangling, {}, - 0., boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + 0., boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); // maybe watch out but you can't access the hdvLine from the converterInterface HVDCLineDefinitions::HvdcLineMap hvdcLines = {std::make_pair(hvdcLineVSC.id, hvdcLineVSC), std::make_pair(hvdcLineLCC.id, hvdcLineLCC)}; HVDCLineDefinitions hvdcDefs{hvdcLines}; @@ -228,7 +228,7 @@ TEST(Dyd, writeDynamicModel) { auto hvdcLineVSC = dfl::algo::HVDCDefinition("HVDCVSCLine", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation1", "BUS_1", true, "VSCStation2", "BUS_2", false, dfl::algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side1, - {}, 0., boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + {}, 0., boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); // maybe watch out but you can't access the hdvLine from the converterInterface HVDCLineDefinitions::HvdcLineMap hvdcLines = {std::make_pair(hvdcLineVSC.id, hvdcLineVSC)}; HVDCLineDefinitions hvdcDefs{hvdcLines}; @@ -354,10 +354,10 @@ TEST(Dyd, writeVRRemote) { auto hvdcLineLCC = HVDCDefinition("HVDCLCCLine", dfl::inputs::HvdcLine::ConverterType::LCC, "LCCStation1", "BUS_3", false, "LCCStation2", "BUS_1", false, HVDCDefinition::Position::FIRST_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPTanPhiDangling, {}, 0., boost::none, - boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC = HVDCDefinition("HVDCVSCLine", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation1", "BUS_1", true, "VSCStation2", "BUS_3", true, HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPQPropDangling, {}, 0., boost::none, - boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); HVDCLineDefinitions::HvdcLineMap hvdcLines = {std::make_pair(hvdcLineVSC.id, hvdcLineVSC), std::make_pair(hvdcLineLCC.id, hvdcLineLCC)}; HVDCLineDefinitions hvdcDefs{hvdcLines}; diff --git a/tests/outputs/TestPar.cpp b/tests/outputs/TestPar.cpp index cd7819fd..ec984c24 100644 --- a/tests/outputs/TestPar.cpp +++ b/tests/outputs/TestPar.cpp @@ -136,32 +136,32 @@ TEST(TestPar, writeHdvc) { auto hvdcLineLCC = HVDCDefinition("HVDCLCCLine", dfl::inputs::HvdcLine::ConverterType::LCC, "LCCStation1", "_BUS___21_TN", false, "LCCStation2", "_BUS___22_TN", false, HVDCDefinition::Position::FIRST_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPTanPhiDangling, {}, 0., boost::none, - boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC = HVDCDefinition("HVDCVSCLine", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation1", "_BUS___10_TN", true, "VSCStation2", "_BUS___11_TN", false, HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPTanPhiDangling, {}, 0., vscStation1, - vscStation2, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + vscStation2, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC2 = HVDCDefinition("HVDCVSCLine2", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation1", "_BUS___10_TN", true, "VSCStation2", "_BUS___11_TN", false, HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQ, {0., 0.}, 0., vscStation1, - vscStation2, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + vscStation2, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC3 = HVDCDefinition("HVDCVSCLine3", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation2", "_BUS___11_TN", true, "VSCStation3", "_BUS___12_TN", true, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQ, {0., 0.}, 0., vscStation2, - vscStation3, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + vscStation3, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC4 = HVDCDefinition("HVDCVSCLine4", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation2", "_BUS___11_TN", true, "VSCStation3", "_BUS___12_TN", true, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPQPropEmulationSet, {0., 0.}, 0., vscStation2, - vscStation3, 5, 120., false, 320, 322, 0.125, {0.01, 0.01}); + vscStation3, 5, 120., false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC5 = HVDCDefinition("HVDCVSCLine5", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation2", "_BUS___11_TN", true, "VSCStation3", "_BUS___12_TN", false, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPQPropEmulationSet, {0., 0.}, 0., vscStation2, - vscStation3, 5, 120., true, 320, 322, 0.125, {0.01, 0.01}); + vscStation3, 5, 120., true, 320, 322, 0.125, {0.01, 0.01}, true); double powerFactor = 1. / std::sqrt(5.); // sqrt(1/(2^2+1)) => qMax = 2 with pMax = 1 auto hvdcLineLCC2 = HVDCDefinition("HVDCLCCLine2", dfl::inputs::HvdcLine::ConverterType::LCC, "LCCStation1", "_BUS___11_TN", false, "LCCStation2", "_BUS___22_TN", false, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPTanPhiDiagramPQ, {powerFactor, powerFactor}, - 1., boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + 1., boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); dfl::algo::HVDCLineDefinitions::HvdcLineMap hvdcLines = { std::make_pair(hvdcLineVSC.id, hvdcLineVSC), std::make_pair(hvdcLineLCC.id, hvdcLineLCC), std::make_pair(hvdcLineVSC2.id, hvdcLineVSC2), std::make_pair(hvdcLineVSC3.id, hvdcLineVSC3), std::make_pair(hvdcLineVSC4.id, hvdcLineVSC4), std::make_pair(hvdcLineVSC5.id, hvdcLineVSC5), @@ -262,15 +262,15 @@ TEST(TestPar, DynModel) { dfl::algo::HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVDanglingRpcl2Side1, {}, 0., dfl::algo::VSCDefinition(dummyStationVSC->converterId, dummyStationVSC->qMax, dummyStationVSC->qMin, dummyStationVSC->qMin, 10., dummyStationVSC->points), dfl::algo::VSCDefinition(vscStation2->converterId, vscStation2->qMax, vscStation2->qMin, vscStation2->qMin, 10., vscStation2->points), boost::none, - boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSCACEmulation1 = dfl::algo::HVDCDefinition("HVDCVSCLine1", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation22", "BUS_22", true, "VSCStation33", "BUS_33", true, dfl::algo::HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVEmulationSet, {0., 0.}, - 0., vscStation22, vscStation33, 5, 120., false, 320, 322, 0.125, {0.01, 0.01}); + 0., vscStation22, vscStation33, 5, 120., false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSCACEmulation2 = dfl::algo::HVDCDefinition("HVDCVSCLine2", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation22", "BUS_22", true, "VSCStation44", "BUS_44", true, dfl::algo::HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPVEmulationSet, {0., 0.}, - 0., vscStation22, vscStation44, 5, 120., false, 320, 322, 0.125, {0.01, 0.01}); + 0., vscStation22, vscStation44, 5, 120., false, 320, 322, 0.125, {0.01, 0.01}, true); // maybe watch out but you can't access the hdvLine from the converterInterface HVDCLineDefinitions::HvdcLineMap hvdcLines = {std::make_pair(hvdcLineVSC.id, hvdcLineVSC), std::make_pair(hvdcLineVSCACEmulation1.id, hvdcLineVSCACEmulation1), @@ -400,10 +400,10 @@ TEST(TestPar, writeVRRemote) { auto hvdcLineLCC = HVDCDefinition("HVDCLCCLine", dfl::inputs::HvdcLine::ConverterType::LCC, "LCCStation1", "BUS_3", false, "LCCStation2", "BUS_1", false, HVDCDefinition::Position::FIRST_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPTanPhiDangling, {}, 0., boost::none, - boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC = HVDCDefinition("HVDCVSCLine", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation1", "BUS_1", false, "VSCStation2", "BUS_3", true, HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, HVDCDefinition::HVDCModel::HvdcPQPropDangling, {}, 0., boost::none, - boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); HVDCLineDefinitions::HvdcLineMap hvdcLines = {std::make_pair(hvdcLineVSC.id, hvdcLineVSC), std::make_pair(hvdcLineLCC.id, hvdcLineLCC)}; HVDCLineDefinitions hvdcDefs{hvdcLines}; @@ -471,32 +471,32 @@ TEST(TestPar, startingPointMode) { auto hvdcLineLCC = HVDCDefinition("HVDCLCCLine", dfl::inputs::HvdcLine::ConverterType::LCC, "LCCStation1", "_BUS___21_TN", false, "LCCStation2", "_BUS___22_TN", false, HVDCDefinition::Position::FIRST_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPTanPhiDangling, {}, 0., boost::none, - boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC = HVDCDefinition("HVDCVSCLine", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation1", "_BUS___10_TN", true, "VSCStation2", "_BUS___11_TN", false, HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPTanPhiDangling, {}, 0., vscStation1, - vscStation2, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + vscStation2, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC2 = HVDCDefinition("HVDCVSCLine2", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation1", "_BUS___10_TN", true, "VSCStation2", "_BUS___11_TN", false, HVDCDefinition::Position::SECOND_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQ, {0., 0.}, 0., vscStation1, - vscStation2, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + vscStation2, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC3 = HVDCDefinition("HVDCVSCLine3", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation2", "_BUS___11_TN", true, "VSCStation3", "_BUS___12_TN", true, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPQPropDiagramPQ, {0., 0.}, 0., vscStation2, - vscStation3, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + vscStation3, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC4 = HVDCDefinition("HVDCVSCLine4", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation2", "_BUS___11_TN", true, "VSCStation3", "_BUS___12_TN", true, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPQPropEmulationSet, {0., 0.}, 0., - vscStation2, vscStation3, 5, 120., false, 320, 322, 0.125, {0.01, 0.01}); + vscStation2, vscStation3, 5, 120., false, 320, 322, 0.125, {0.01, 0.01}, true); auto hvdcLineVSC5 = HVDCDefinition("HVDCVSCLine5", dfl::inputs::HvdcLine::ConverterType::VSC, "VSCStation2", "_BUS___11_TN", true, "VSCStation3", "_BUS___12_TN", false, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPQPropEmulationSet, {0., 0.}, 0., - vscStation2, vscStation3, 5, 120., true, 320, 322, 0.125, {0.01, 0.01}); + vscStation2, vscStation3, 5, 120., true, 320, 322, 0.125, {0.01, 0.01}, true); double powerFactor = 1. / std::sqrt(5.); // sqrt(1/(2^2+1)) => qMax = 2 with pMax = 1 auto hvdcLineLCC2 = HVDCDefinition("HVDCLCCLine2", dfl::inputs::HvdcLine::ConverterType::LCC, "LCCStation1", "_BUS___11_TN", false, "LCCStation2", "_BUS___22_TN", false, HVDCDefinition::Position::BOTH_IN_MAIN_COMPONENT, dfl::algo::HVDCDefinition::HVDCModel::HvdcPTanPhiDiagramPQ, {powerFactor, powerFactor}, - 1., boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}); + 1., boost::none, boost::none, boost::none, boost::none, false, 320, 322, 0.125, {0.01, 0.01}, true); dfl::algo::HVDCLineDefinitions::HvdcLineMap hvdcLines = { std::make_pair(hvdcLineVSC.id, hvdcLineVSC), std::make_pair(hvdcLineLCC.id, hvdcLineLCC), std::make_pair(hvdcLineVSC2.id, hvdcLineVSC2), std::make_pair(hvdcLineVSC3.id, hvdcLineVSC3), std::make_pair(hvdcLineVSC4.id, hvdcLineVSC4), std::make_pair(hvdcLineVSC5.id, hvdcLineVSC5),