diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json
index 6a40256f..e40aff37 100644
--- a/.devcontainer/devcontainer.json
+++ b/.devcontainer/devcontainer.json
@@ -7,7 +7,6 @@
 		"ms-vscode.cpptools",
 		"ms-vscode.cmake-tools",
 		"marus25.cortex-debug",
-		"vsciot-vscode.vscode-iot-workbench",
 		"vsciot-vscode.vscode-dtdl",
 		"xaver.clang-format",
 		"ms-azuretools.vscode-docker"
diff --git a/MXChip/AZ3166/CMakeLists.txt b/MXChip/AZ3166/CMakeLists.txt
index abc7f425..b4f1e5eb 100644
--- a/MXChip/AZ3166/CMakeLists.txt
+++ b/MXChip/AZ3166/CMakeLists.txt
@@ -1,7 +1,7 @@
 # Copyright (c) Microsoft Corporation.
 # Licensed under the MIT License.
 
-cmake_minimum_required(VERSION 3.10 FATAL_ERROR)
+cmake_minimum_required(VERSION 3.13 FATAL_ERROR)
 set(CMAKE_C_STANDARD 99)
 
 set(GSG_BASE_DIR ${CMAKE_SOURCE_DIR}/../..)
diff --git a/MXChip/AZ3166/app/wwd_networking.c b/MXChip/AZ3166/app/wwd_networking.c
index 4a3bd7a7..270f0aff 100644
--- a/MXChip/AZ3166/app/wwd_networking.c
+++ b/MXChip/AZ3166/app/wwd_networking.c
@@ -194,7 +194,7 @@ int platform_init(CHAR* ssid, CHAR* password, WiFi_Mode mode)
         &nx_pool[0], "NetX Main TX Packet Pool", SAMPLE_PACKET_SIZE, sample_tx_pool_stack, SAMPLE_TX_POOL_SIZE);
     if (status != NX_SUCCESS)
     {
-        printf("Sample platform initialize fail: PACKET POOL CREATE FAIL.");
+        printf("Platform initialize fail: PACKET POOL CREATE FAIL.");
         return status;
     }
 
@@ -204,7 +204,7 @@ int platform_init(CHAR* ssid, CHAR* password, WiFi_Mode mode)
     if (status != NX_SUCCESS)
     {
         nx_packet_pool_delete(&nx_pool[0]);
-        printf("Sample platform initialize fail: PACKET POOL CREATE FAIL.\r\n");
+        printf("Platform initialize fail: PACKET POOL CREATE FAIL.\r\n");
         return status;
     }
 
@@ -214,7 +214,7 @@ int platform_init(CHAR* ssid, CHAR* password, WiFi_Mode mode)
     {
         nx_packet_pool_delete(&nx_pool[0]);
         nx_packet_pool_delete(&nx_pool[1]);
-        printf("Sample platform initialize fail: WiFi JOIN FAIL.\r\n");
+        printf("Platform initialize fail: WiFi JOIN FAIL.\r\n");
         return status;
     }
 
@@ -233,7 +233,7 @@ int platform_init(CHAR* ssid, CHAR* password, WiFi_Mode mode)
     {
         nx_packet_pool_delete(&nx_pool[0]);
         nx_packet_pool_delete(&nx_pool[1]);
-        printf("Sample platform initialize fail: IP CREATE FAIL.\r\n");
+        printf("Platform initialize fail: IP CREATE FAIL.\r\n");
         return status;
     }
 
@@ -244,7 +244,7 @@ int platform_init(CHAR* ssid, CHAR* password, WiFi_Mode mode)
         nx_ip_delete(&nx_ip);
         nx_packet_pool_delete(&nx_pool[0]);
         nx_packet_pool_delete(&nx_pool[1]);
-        printf("Sample platform initialize fail: ARP ENABLE FAIL.\r\n");
+        printf("Platform initialize fail: ARP ENABLE FAIL.\r\n");
         return status;
     }
 
@@ -255,7 +255,7 @@ int platform_init(CHAR* ssid, CHAR* password, WiFi_Mode mode)
         nx_ip_delete(&nx_ip);
         nx_packet_pool_delete(&nx_pool[0]);
         nx_packet_pool_delete(&nx_pool[1]);
-        printf("Sample platform initialize fail: ICMP ENABLE FAIL.\r\n");
+        printf("Platform initialize fail: ICMP ENABLE FAIL.\r\n");
         return status;
     }
 
@@ -267,7 +267,7 @@ int platform_init(CHAR* ssid, CHAR* password, WiFi_Mode mode)
         nx_packet_pool_delete(&nx_pool[0]);
         nx_packet_pool_delete(&nx_pool[1]);
         /* LogError */
-        printf("Sample platform initialize fail: TCP ENABLE FAIL.\r\n");
+        printf("Platform initialize fail: TCP ENABLE FAIL.\r\n");
         return status;
     }
 
@@ -278,7 +278,7 @@ int platform_init(CHAR* ssid, CHAR* password, WiFi_Mode mode)
         nx_ip_delete(&nx_ip);
         nx_packet_pool_delete(&nx_pool[0]);
         nx_packet_pool_delete(&nx_pool[1]);
-        printf("Sample platform initialize fail: UDP ENABLE FAIL.\r\n");
+        printf("Platform initialize fail: UDP ENABLE FAIL.\r\n");
         return status;
     }
 
@@ -292,7 +292,7 @@ int platform_init(CHAR* ssid, CHAR* password, WiFi_Mode mode)
         nx_ip_delete(&nx_ip);
         nx_packet_pool_delete(&nx_pool[0]);
         nx_packet_pool_delete(&nx_pool[1]);
-        printf("Sample platform initialize fail: %u\r\n", status);
+        printf("Platform initialize fail: %u\r\n", status);
         return status;
     }
 
diff --git a/MXChip/AZ3166/lib/wiced_sdk/binary_build/CMakeLists.txt b/MXChip/AZ3166/lib/wiced_sdk/binary_build/CMakeLists.txt
index 9442e047..61174a56 100644
--- a/MXChip/AZ3166/lib/wiced_sdk/binary_build/CMakeLists.txt
+++ b/MXChip/AZ3166/lib/wiced_sdk/binary_build/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.10)
+cmake_minimum_required(VERSION 3.13)
 
 project(wiced_sdk C)
 
diff --git a/MXChip/AZ3166/readme.md b/MXChip/AZ3166/readme.md
index 54e4368d..0f29d73f 100644
--- a/MXChip/AZ3166/readme.md
+++ b/MXChip/AZ3166/readme.md
@@ -361,11 +361,10 @@ To use Azure CLI to call a method:
 1. View the Termite terminal to confirm the output messages:
 
     ```output
-    Received direct method=setLedState, id=1, message=true
+    Received direct method call: setLedState
+        Payload: true
     LED is turned ON
-    Sending device twin update with bool value
-    Sending message {"ledState":true}
-    Direct method=setLedState invoked
+    Device twin property sent: {"ledState":true}
     ```
 
 ## Debugging
diff --git a/Microchip/ATSAME54-XPRO/CMakeLists.txt b/Microchip/ATSAME54-XPRO/CMakeLists.txt
index 6942d1df..8888510a 100644
--- a/Microchip/ATSAME54-XPRO/CMakeLists.txt
+++ b/Microchip/ATSAME54-XPRO/CMakeLists.txt
@@ -1,7 +1,7 @@
 # Copyright (c) Microsoft Corporation.
 # Licensed under the MIT License.
 
-cmake_minimum_required(VERSION 3.10 FATAL_ERROR)
+cmake_minimum_required(VERSION 3.13 FATAL_ERROR)
 set(CMAKE_C_STANDARD 99)
 
 set(GSG_BASE_DIR ${CMAKE_SOURCE_DIR}/../..)
diff --git a/Microchip/ATSAME54-XPRO/readme.md b/Microchip/ATSAME54-XPRO/readme.md
index 8765a192..e335324a 100644
--- a/Microchip/ATSAME54-XPRO/readme.md
+++ b/Microchip/ATSAME54-XPRO/readme.md
@@ -81,7 +81,7 @@ To install the tools:
 
 To install the remaining tools:
 
-1. Install [Atmel Studio 7](https://www.microchip.com/mplab/avr-support/atmel-studio-7). Atmel Studio is a device development environment that includes the tools to program and flash program the Microchip E54. For this tutorial, you use Atmel Studio only to flash the Microchip E54. The installation takes several minutes, and prompts you several times to approve the installation of components.
+1. Install [Atmel Studio 7](https://www.microchip.com/mplab/avr-support/atmel-studio-7). Atmel Studio is a device development environment that includes the tools to program and flash the Microchip E54. For this tutorial, you use Atmel Studio only to flash the Microchip E54. The installation takes several minutes, and prompts you several times to approve the installation of components.
 
 ### Create an IoT hub
 
@@ -232,10 +232,6 @@ You can use the **Termite** utility to monitor communication and confirm that yo
     ```output
     Starting Azure thread
 
-    Initializing WiFi
-    	Connecting to SSID 'iot'
-    SUCCESS: WiFi connected to iot
-
     Initializing DHCP
     	IP address: 10.0.0.123
     	Mask: 255.255.255.0
@@ -388,12 +384,12 @@ To use Azure CLI to call a method:
 1. View the Termite terminal to confirm the output messages:
 
     ```output
-    Received direct method=setLedState, id=1, message=true
+    Received direct method call: setLedState
+        Payload: true
     LED is turned ON
-    Sending device twin update with bool value
-    Sending message {"ledState":true}
-    Direct method=setLedState invoked
+    Device twin property sent: {"ledState":true}
     ```
+
 ## Debugging
 
 For debugging the application, see [Debugging with Visual Studio Code](../../docs/debugging.md).
diff --git a/NXP/MIMXRT1050-EVKB/CMakeLists.txt b/NXP/MIMXRT1050-EVKB/CMakeLists.txt
index 36eb56a5..011b0c6a 100644
--- a/NXP/MIMXRT1050-EVKB/CMakeLists.txt
+++ b/NXP/MIMXRT1050-EVKB/CMakeLists.txt
@@ -1,7 +1,7 @@
 # Copyright (c) Microsoft Corporation.
 # Licensed under the MIT License.
 
-cmake_minimum_required(VERSION 3.10 FATAL_ERROR)
+cmake_minimum_required(VERSION 3.13 FATAL_ERROR)
 set(CMAKE_C_STANDARD 99)
 
 set(GSG_BASE_DIR ${CMAKE_SOURCE_DIR}/../..)
@@ -26,4 +26,3 @@ project(mimxrt1050_azure_iot C ASM)
 add_subdirectory(${CORE_SRC_DIR} core_src)
 add_subdirectory(lib)
 add_subdirectory(app)
-
diff --git a/NXP/MIMXRT1050-EVKB/app/board_init.h b/NXP/MIMXRT1050-EVKB/app/board_init.h
index a3a896ff..771fb2bb 100644
--- a/NXP/MIMXRT1050-EVKB/app/board_init.h
+++ b/NXP/MIMXRT1050-EVKB/app/board_init.h
@@ -4,8 +4,6 @@
 #ifndef _BOARD_INIT_H
 #define _BOARD_INIT_H
 
-#include "nx_api.h"
-
 void board_init();
 
 #endif // _BOARD_INIT_H
diff --git a/NXP/MIMXRT1050-EVKB/readme.md b/NXP/MIMXRT1050-EVKB/readme.md
index e5ed5a80..3872d4c1 100644
--- a/NXP/MIMXRT1050-EVKB/readme.md
+++ b/NXP/MIMXRT1050-EVKB/readme.md
@@ -191,10 +191,6 @@ You can use the **Termite** utility to monitor communication and confirm that yo
     ```output
     Starting Azure thread
 
-    Initializing WiFi
-    	Connecting to SSID 'iot'
-    SUCCESS: WiFi connected to iot
-
     Initializing DHCP
     	IP address: 10.0.0.123
     	Mask: 255.255.255.0
@@ -347,11 +343,10 @@ To use Azure CLI to call a method:
 1. View the Termite terminal to confirm the output messages:
 
     ```output
-    Received direct method=setLedState, id=1, message=true
+    Received direct method call: setLedState
+        Payload: true
     LED is turned ON
-    Sending device twin update with bool value
-    Sending message {"ledState":true}
-    Direct method=setLedState invoked
+    Device twin property sent: {"ledState":true}
     ```
 
 ## Debugging
diff --git a/NXP/MIMXRT1060-EVK/CMakeLists.txt b/NXP/MIMXRT1060-EVK/CMakeLists.txt
index ca1e142e..ac4e881f 100644
--- a/NXP/MIMXRT1060-EVK/CMakeLists.txt
+++ b/NXP/MIMXRT1060-EVK/CMakeLists.txt
@@ -1,7 +1,7 @@
 # Copyright (c) Microsoft Corporation.
 # Licensed under the MIT License.
 
-cmake_minimum_required(VERSION 3.10 FATAL_ERROR)
+cmake_minimum_required(VERSION 3.13 FATAL_ERROR)
 set(CMAKE_C_STANDARD 99)
 
 set(GSG_BASE_DIR ${CMAKE_SOURCE_DIR}/../..)
diff --git a/NXP/MIMXRT1060-EVK/app/board_init.h b/NXP/MIMXRT1060-EVK/app/board_init.h
index a3a896ff..771fb2bb 100644
--- a/NXP/MIMXRT1060-EVK/app/board_init.h
+++ b/NXP/MIMXRT1060-EVK/app/board_init.h
@@ -4,8 +4,6 @@
 #ifndef _BOARD_INIT_H
 #define _BOARD_INIT_H
 
-#include "nx_api.h"
-
 void board_init();
 
 #endif // _BOARD_INIT_H
diff --git a/NXP/MIMXRT1060-EVK/readme.md b/NXP/MIMXRT1060-EVK/readme.md
index 80373044..e2ee23ad 100644
--- a/NXP/MIMXRT1060-EVK/readme.md
+++ b/NXP/MIMXRT1060-EVK/readme.md
@@ -190,10 +190,6 @@ You can use the **Termite** utility to monitor communication and confirm that yo
     ```output
     Starting Azure thread
 
-    Initializing WiFi
-    	Connecting to SSID 'iot'
-    SUCCESS: WiFi connected to iot
-
     Initializing DHCP
     	IP address: 10.0.0.123
     	Mask: 255.255.255.0
@@ -347,11 +343,10 @@ To use Azure CLI to call a method:
 1. View the Termite terminal to confirm the output messages:
 
     ```output
-    Received direct method=setLedState, id=1, message=true
+    Received direct method call: setLedState
+        Payload: true
     LED is turned ON
-    Sending device twin update with bool value
-    Sending message {"ledState":true}
-    Direct method=setLedState invoked
+    Device twin property sent: {"ledState":true}
     ```
 
 ## Debugging
diff --git a/README.md b/README.md
index 3a57a31e..4babbf71 100644
--- a/README.md
+++ b/README.md
@@ -26,6 +26,7 @@ The following board specific guides will get you started with Azure RTOS and Azu
   * [MIMXRT1060-EVK](NXP/MIMXRT1060-EVK)
 * Renesas: 
   * [AE-Cloud2](Renesas/Synergy)
+  * [RSK+RX65N-2MB](Renesas/RSK_RX65N_2MB)
 * STMicroelectronics: 
   * [B-L475E-IOT01A](STMicroelectronics/STM32L4_L4+)
   * [B-L4S5I-IOT01A](STMicroelectronics/STM32L4_L4+)
diff --git a/Renesas/RSK_RX65N_2MB/.vscode/cmake-kits.json b/Renesas/RSK_RX65N_2MB/.vscode/cmake-kits.json
new file mode 100644
index 00000000..a2531d05
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/.vscode/cmake-kits.json
@@ -0,0 +1,6 @@
+[
+    {
+        "name": "Renesas RX65N GCC",
+        "toolchainFile": "${workspaceFolder}/../../cmake/renesas-rx-gcc-rx65n.cmake"
+    }
+]
\ No newline at end of file
diff --git a/Renesas/RSK_RX65N_2MB/CMakeLists.txt b/Renesas/RSK_RX65N_2MB/CMakeLists.txt
new file mode 100644
index 00000000..21855f9f
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/CMakeLists.txt
@@ -0,0 +1,30 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+cmake_minimum_required(VERSION 3.13 FATAL_ERROR)
+set(CMAKE_C_STANDARD 99)
+
+set(GSG_BASE_DIR ${CMAKE_SOURCE_DIR}/../..)
+set(CORE_SRC_DIR ${GSG_BASE_DIR}/core/src)
+set(CORE_LIB_DIR ${GSG_BASE_DIR}/core/lib)
+
+# use the repo version of ninja on Windows as there is no Ninja installer
+if(WIN32)
+    set(CMAKE_MAKE_PROGRAM ${GSG_BASE_DIR}/cmake/ninja CACHE STRING "Ninja location")
+endif()
+
+# Set the toolchain if not defined
+if(NOT CMAKE_TOOLCHAIN_FILE)
+    set(CMAKE_TOOLCHAIN_FILE "${GSG_BASE_DIR}/cmake/renesas-rx-gcc-rx65n.cmake")
+endif()
+
+include(${GSG_BASE_DIR}/cmake/utilities.cmake)
+
+# Define the Project
+project(rx65n_azure_iot C ASM)
+
+set(DISABLE_NEWLIB_STUB true)
+
+add_subdirectory(${CORE_SRC_DIR} core_src)
+add_subdirectory(lib)
+add_subdirectory(app)
diff --git a/Renesas/RSK_RX65N_2MB/app/.vscode/cmake-kits.json b/Renesas/RSK_RX65N_2MB/app/.vscode/cmake-kits.json
new file mode 100644
index 00000000..a2531d05
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/.vscode/cmake-kits.json
@@ -0,0 +1,6 @@
+[
+    {
+        "name": "Renesas RX65N GCC",
+        "toolchainFile": "${workspaceFolder}/../../cmake/renesas-rx-gcc-rx65n.cmake"
+    }
+]
\ No newline at end of file
diff --git a/Renesas/RSK_RX65N_2MB/app/CMakeLists.txt b/Renesas/RSK_RX65N_2MB/app/CMakeLists.txt
new file mode 100644
index 00000000..972b6e3a
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/CMakeLists.txt
@@ -0,0 +1,50 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+set(LINKER_SCRIPT "${CMAKE_CURRENT_LIST_DIR}/startup/linker_script.ld")
+
+set(SOURCES
+#    startup/startup_MIMXRT1062.S
+    startup/tx_initialize_low_level.S
+
+    legacy/mqtt.c
+    azure_config.h
+    nx_client.c
+    board_init.c
+    console.c
+    main.c    
+)
+
+add_executable(${PROJECT_NAME} ${SOURCES})
+
+target_link_libraries(${PROJECT_NAME} 
+    PUBLIC
+        azrtos::threadx
+        azrtos::netxduo
+
+        app_common
+        jsmn
+        rx_driver_package
+        netx_driver
+)
+
+target_link_options(${PROJECT_NAME}
+    PRIVATE 
+        -T${LINKER_SCRIPT} 
+        -Wl,-Map=${PROJECT_NAME}.map
+        -Wl,-e_PowerON_Reset
+)
+
+set_target_properties(${PROJECT_NAME}
+    PROPERTIES 
+        LINK_DEPENDS ${LINKER_SCRIPT}
+        SUFFIX ".elf"
+)
+
+target_include_directories(${PROJECT_NAME} 
+    PUBLIC 
+        .
+)
+
+create_bin_output(${PROJECT_NAME})
+firmware_size(${PROJECT_NAME})
diff --git a/Renesas/RSK_RX65N_2MB/app/azure_config.h b/Renesas/RSK_RX65N_2MB/app/azure_config.h
new file mode 100644
index 00000000..45fba7c8
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/azure_config.h
@@ -0,0 +1,48 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+
+#ifndef _AZURE_CONFIG_H
+#define _AZURE_CONFIG_H
+
+// ----------------------------------------------------------------------------
+// Azure IoT Hub Connection Transport
+//    Define to use the legacy MQTT connection, else Azure RTOS SDK for Azure IoT
+// ----------------------------------------------------------------------------
+//#define ENABLE_LEGACY_MQTT
+
+// ----------------------------------------------------------------------------
+// Azure IoT Dynamic Provisioning Service
+//    Define this to use the DPS service, otherwise direct IoT Hub
+// ----------------------------------------------------------------------------
+//#define ENABLE_DPS
+
+// ----------------------------------------------------------------------------
+// Azure IoT DPS Self-Signed X509Certificate
+//    Define this to connect to DPS or Iot Hub using a X509 certificate
+// ----------------------------------------------------------------------------
+// #define ENABLE_X509
+
+// ----------------------------------------------------------------------------
+// Azure IoT Hub connection config
+//    IOT_HUB_HOSTNAME:  The Azure IoT Hub hostname
+//    IOT_HUB_DEVICE_ID: The Azure IoT Hub device id
+// ----------------------------------------------------------------------------
+#define IOT_HUB_HOSTNAME  ""
+#define IOT_HUB_DEVICE_ID ""
+
+// ----------------------------------------------------------------------------
+// Azure IoT DPS connection config
+//    IOT_DPS_ID_SCOPE:        The DPS ID Scope
+//    IOT_DPS_REGISTRATION_ID: The DPS device Registration Id
+// ----------------------------------------------------------------------------
+#define IOT_DPS_ID_SCOPE        ""
+#define IOT_DPS_REGISTRATION_ID ""
+
+// ----------------------------------------------------------------------------
+// Azure IoT device SAS key
+//    The SAS key generated by configuring an IoT Hub device or DPS individual
+//    enrollment
+// ----------------------------------------------------------------------------
+#define IOT_DEVICE_SAS_KEY ""
+
+#endif // _AZURE_CONFIG_H
diff --git a/Renesas/RSK_RX65N_2MB/app/azure_device_x509_cert_config.h b/Renesas/RSK_RX65N_2MB/app/azure_device_x509_cert_config.h
new file mode 100644
index 00000000..214b0092
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/azure_device_x509_cert_config.h
@@ -0,0 +1,21 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+
+#ifndef _AZURE_DEVICE_X509_CERT_CONFIG_H
+#define _AZURE_DEVICE_X509_CERT_CONFIG_H
+
+// ----------------------------------------------------------------------------
+// Azure IoT X509 Device Certificate
+// Replace {0x00} with your formatted output from OpenSSL and xxd here
+// ----------------------------------------------------------------------------
+const unsigned char iot_x509_device_cert[] = {0x00};
+unsigned int iot_x509_device_cert_len      = sizeof(iot_x509_device_cert);
+
+// ----------------------------------------------------------------------------
+// Azure IoT X509 Device Private Key
+// Replace {0x00} with your formatted output from OpenSSL and xxd here
+// ----------------------------------------------------------------------------
+unsigned char iot_x509_private_key[]        = {0x00};
+const unsigned int iot_x509_private_key_len = sizeof(iot_x509_private_key);
+
+#endif
\ No newline at end of file
diff --git a/Renesas/RSK_RX65N_2MB/app/azure_pnp_info.h b/Renesas/RSK_RX65N_2MB/app/azure_pnp_info.h
new file mode 100644
index 00000000..134fc372
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/azure_pnp_info.h
@@ -0,0 +1,29 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+
+#ifndef _AZURE_PNP_INFO_H
+#define _AZURE_PNP_INFO_H
+
+#define DEVICE_INFO_COMPONENT_NAME "deviceInformation"
+
+// Device Info property names
+#define DEVICE_INFO_MANUFACTURER_PROPERTY_NAME           "manufacturer"
+#define DEVICE_INFO_MODEL_PROPERTY_NAME                  "model"
+#define DEVICE_INFO_SW_VERSION_PROPERTY_NAME             "swVersion"
+#define DEVICE_INFO_OS_NAME_PROPERTY_NAME                "osName"
+#define DEVICE_INFO_PROCESSOR_ARCHITECTURE_PROPERTY_NAME "processorArchitecture"
+#define DEVICE_INFO_PROCESSOR_MANUFACTURER_PROPERTY_NAME "processorManufacturer"
+#define DEVICE_INFO_TOTAL_STORAGE_PROPERTY_NAME          "totalStorage"
+#define DEVICE_INFO_TOTAL_MEMORY_PROPERTY_NAME           "totalMemory"
+
+// Device Info property values
+#define DEVICE_INFO_MANUFACTURER_PROPERTY_VALUE           "Renesas"
+#define DEVICE_INFO_MODEL_PROPERTY_VALUE                  "RSK+RX65N-2MB"
+#define DEVICE_INFO_SW_VERSION_PROPERTY_VALUE             "1.0.0"
+#define DEVICE_INFO_OS_NAME_PROPERTY_VALUE                "Azure RTOS"
+#define DEVICE_INFO_PROCESSOR_ARCHITECTURE_PROPERTY_VALUE "RX65N"
+#define DEVICE_INFO_PROCESSOR_MANUFACTURER_PROPERTY_VALUE "Renesas"
+#define DEVICE_INFO_TOTAL_STORAGE_PROPERTY_VALUE          2048
+#define DEVICE_INFO_TOTAL_MEMORY_PROPERTY_VALUE           640
+
+#endif
diff --git a/Renesas/RSK_RX65N_2MB/app/board_init.c b/Renesas/RSK_RX65N_2MB/app/board_init.c
new file mode 100644
index 00000000..1520bb96
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/board_init.c
@@ -0,0 +1,41 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+
+#include "board_init.h"
+
+#include "r_cmt_rx_if.h"
+#include "r_ether_rx_if.h"
+#include "r_ether_rx_pinset.h"
+#include "r_smc_entry.h"
+
+#include "platform.h"
+
+#include "Config_SCI8.h"
+
+void _tx_timer_interrupt();
+
+// CMT Timer callback used as the system tick.
+void timer_callback(void* pdata)
+{
+    _tx_timer_interrupt();
+}
+
+void board_init()
+{
+    uint32_t chan;
+    ether_param_t eth_param = {0};
+
+    // Setup SCI8 for printf output
+    R_Config_SCI8_Start();
+
+    // Create periodic timer for the system tick
+    R_CMT_CreatePeriodic(100u, timer_callback, &chan);
+
+    // Setup Ethernet hardware
+    R_ETHER_Initial();
+
+    R_ETHER_PinSet_ETHERC0_MII();
+
+    eth_param.channel = 0u;
+    R_ETHER_Control(CONTROL_POWER_ON, eth_param);
+}
diff --git a/Renesas/RSK_RX65N_2MB/app/board_init.h b/Renesas/RSK_RX65N_2MB/app/board_init.h
new file mode 100644
index 00000000..771fb2bb
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/board_init.h
@@ -0,0 +1,9 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+   
+#ifndef _BOARD_INIT_H
+#define _BOARD_INIT_H
+
+void board_init();
+
+#endif // _BOARD_INIT_H
diff --git a/Renesas/RSK_RX65N_2MB/app/console.c b/Renesas/RSK_RX65N_2MB/app/console.c
new file mode 100644
index 00000000..1efc5e5f
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/console.c
@@ -0,0 +1,51 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+
+#include "r_cg_macrodriver.h"
+
+#include "Config_SCI8.h"
+
+#include "tx_api.h"
+
+TX_MUTEX printf_mutex;
+TX_SEMAPHORE printf_semaphore;
+
+void printf_init(void)
+{
+    UINT res;
+
+    res = tx_mutex_create(&printf_mutex, "printf mutex", TX_INHERIT);
+    if (res != TX_SUCCESS)
+    {
+        for (;;)
+        {
+        }
+    }
+
+    res = tx_semaphore_create(&printf_semaphore, "printf semaphore", 0u);
+    if (res != TX_SUCCESS)
+    {
+        for (;;)
+        {
+        }
+    }
+}
+
+void printf_transmit_end(void)
+{
+    tx_semaphore_put(&printf_semaphore);
+}
+
+void my_sw_charput_function(char c)
+{
+    tx_mutex_get(&printf_mutex, TX_WAIT_FOREVER);
+
+    R_Config_SCI8_Serial_Send(&c, 1u);
+
+    tx_semaphore_get(&printf_semaphore, TX_WAIT_FOREVER);
+
+    tx_mutex_put(&printf_mutex);
+
+    return;
+}
+
diff --git a/Renesas/RSK_RX65N_2MB/app/legacy/mqtt.c b/Renesas/RSK_RX65N_2MB/app/legacy/mqtt.c
new file mode 100644
index 00000000..2cd4fbdc
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/legacy/mqtt.c
@@ -0,0 +1,199 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+
+#include "mqtt.h"
+
+#include <stdio.h>
+
+#include "azure_iot_mqtt.h"
+#include "json_utils.h"
+#include "sntp_client.h"
+
+#include "azure_config.h"
+
+#include "platform.h"
+
+#define IOT_MODEL_ID "dtmi:com:example:azurertos:gsg;1"
+
+#define TELEMETRY_INTERVAL_PROPERTY "telemetryInterval"
+#define LED_STATE_PROPERTY          "ledState"
+
+#define TELEMETRY_INTERVAL_EVENT 1
+
+#define LED_ON  0
+#define LED_OFF 1
+#define LED0    PORT7.PODR.BIT.B3
+#define LED1    PORTG.PODR.BIT.B7
+#define LED2    PORTG.PODR.BIT.B6
+#define LED3    PORTG.PODR.BIT.B5
+
+static AZURE_IOT_MQTT azure_iot_mqtt;
+static TX_EVENT_FLAGS_GROUP azure_iot_flags;
+
+static INT telemetry_interval = 10;
+
+static void set_led_state(bool level)
+{
+    if (level)
+    {
+        printf("LED is turned ON\r\n");
+        LED0 = LED_ON;
+        LED1 = LED_ON;
+        LED2 = LED_ON;
+        LED3 = LED_ON;
+    }
+    else
+    {
+        printf("LED is turned OFF\r\n");
+        LED0 = LED_OFF;
+        LED1 = LED_OFF;
+        LED2 = LED_OFF;
+        LED3 = LED_OFF;
+    }
+}
+
+static void mqtt_direct_method(AZURE_IOT_MQTT* iot_mqtt, CHAR* direct_method_name, CHAR* message)
+{
+    if (strcmp(direct_method_name, "setLedState") == 0)
+    {
+        printf("Direct method=%s invoked\r\n", direct_method_name);
+
+        // 'false' - turn LED off
+        // 'true'  - turn LED on
+        bool arg = (strcmp(message, "true") == 0);
+
+        set_led_state(arg);
+
+        // Return success
+        azure_iot_mqtt_respond_direct_method(iot_mqtt, 200);
+
+        // Update device twin property
+        azure_iot_mqtt_publish_bool_property(iot_mqtt, LED_STATE_PROPERTY, arg);
+    }
+    else
+    {
+        printf("Received direct method=%s is unknown\r\n", direct_method_name);
+        azure_iot_mqtt_respond_direct_method(iot_mqtt, 501);
+    }
+}
+
+static void mqtt_c2d_message(AZURE_IOT_MQTT* iot_mqtt, CHAR* properties, CHAR* message)
+{
+    printf("Received C2D message, properties='%s', message='%s'\r\n", properties, message);
+}
+
+static void mqtt_device_twin_desired_prop(AZURE_IOT_MQTT* iot_mqtt, CHAR* message)
+{
+    jsmn_parser parser;
+    jsmntok_t tokens[64];
+    INT token_count;
+
+    jsmn_init(&parser);
+    token_count = jsmn_parse(&parser, message, strlen(message), tokens, 64);
+
+    if (findJsonInt(message, tokens, token_count, TELEMETRY_INTERVAL_PROPERTY, &telemetry_interval))
+    {
+        // Set a telemetry event so we pick up the change immediately
+        tx_event_flags_set(&azure_iot_flags, TELEMETRY_INTERVAL_EVENT, TX_OR);
+
+        // Confirm reception back to hub
+        azure_iot_mqtt_respond_int_writeable_property(iot_mqtt, TELEMETRY_INTERVAL_PROPERTY, telemetry_interval, 200);
+    }
+}
+
+static void mqtt_device_twin_prop(AZURE_IOT_MQTT* iot_mqtt, CHAR* message)
+{
+    jsmn_parser parser;
+    jsmntok_t tokens[64];
+    INT token_count;
+
+    jsmn_init(&parser);
+    token_count = jsmn_parse(&parser, message, strlen(message), tokens, 64);
+
+    if (findJsonInt(message, tokens, token_count, TELEMETRY_INTERVAL_PROPERTY, &telemetry_interval))
+    {
+        // Set a telemetry event so we pick up the change immediately
+        tx_event_flags_set(&azure_iot_flags, TELEMETRY_INTERVAL_EVENT, TX_OR);
+    }
+
+    // Report writeable properties to the Hub
+    azure_iot_mqtt_publish_int_writeable_property(iot_mqtt, TELEMETRY_INTERVAL_PROPERTY, telemetry_interval);
+}
+
+UINT azure_iot_mqtt_entry(NX_IP* ip_ptr, NX_PACKET_POOL* pool_ptr, NX_DNS* dns_ptr, ULONG (*time_get)(VOID))
+{
+    UINT status;
+    ULONG events;
+    float temperature;
+
+    if ((status = tx_event_flags_create(&azure_iot_flags, "Azure IoT flags")))
+    {
+        printf("FAIL: Unable to create nx_client event flags (0x%02x)\r\n", status);
+        return status;
+    }
+
+#ifdef ENABLE_DPS
+    // Create Azure MQTT for Hub via DPS
+    status = azure_iot_mqtt_create_with_dps(&azure_iot_mqtt,
+        ip_ptr,
+        pool_ptr,
+        dns_ptr,
+        time_get,
+        IOT_DPS_ID_SCOPE,
+        IOT_DPS_REGISTRATION_ID,
+        IOT_DEVICE_SAS_KEY,
+        IOT_MODEL_ID);
+#else
+    // Create Azure MQTT for Hub
+    status = azure_iot_mqtt_create(&azure_iot_mqtt,
+        ip_ptr,
+        pool_ptr,
+        dns_ptr,
+        time_get,
+        IOT_HUB_HOSTNAME,
+        IOT_HUB_DEVICE_ID,
+        IOT_DEVICE_SAS_KEY,
+        IOT_MODEL_ID);
+#endif
+
+    if (status != NXD_MQTT_SUCCESS)
+    {
+        printf("Error: Failed to create Azure IoT MQTT (0x%04x)\r\n", status);
+        return status;
+    }
+
+    // Register callbacks
+    azure_iot_mqtt_register_direct_method_callback(&azure_iot_mqtt, mqtt_direct_method);
+    azure_iot_mqtt_register_c2d_message_callback(&azure_iot_mqtt, mqtt_c2d_message);
+    azure_iot_mqtt_register_device_twin_desired_prop_callback(&azure_iot_mqtt, mqtt_device_twin_desired_prop);
+    azure_iot_mqtt_register_device_twin_prop_callback(&azure_iot_mqtt, mqtt_device_twin_prop);
+
+    // Connect the Azure MQTT client
+    status = azure_iot_mqtt_connect(&azure_iot_mqtt);
+    if (status != NXD_MQTT_SUCCESS)
+    {
+        printf("Error: Failed to create Azure MQTT (0x%02x)\r\n", status);
+        return status;
+    }
+
+    // Update ledState property
+    azure_iot_mqtt_publish_bool_property(&azure_iot_mqtt, LED_STATE_PROPERTY, false);
+
+    // Request the device twin
+    azure_iot_mqtt_device_twin_request(&azure_iot_mqtt);
+
+    printf("\r\nStarting MQTT loop\r\n");
+    while (true)
+    {
+        temperature = 28.5;
+
+        // Sleep
+        tx_event_flags_get(
+            &azure_iot_flags, TELEMETRY_INTERVAL_EVENT, TX_OR_CLEAR, &events, telemetry_interval * NX_IP_PERIODIC_RATE);
+
+        // Send the temperature as a telemetry event
+        azure_iot_mqtt_publish_float_telemetry(&azure_iot_mqtt, "temperature", temperature);
+    }
+
+    return NXD_MQTT_SUCCESS;
+}
\ No newline at end of file
diff --git a/Renesas/RSK_RX65N_2MB/app/legacy/mqtt.h b/Renesas/RSK_RX65N_2MB/app/legacy/mqtt.h
new file mode 100644
index 00000000..d8e4570d
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/legacy/mqtt.h
@@ -0,0 +1,13 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+
+#ifndef _MQTT_H
+#define _MQTT_H
+
+#include "tx_api.h"
+#include "nx_api.h"
+#include "nxd_dns.h"
+
+UINT azure_iot_mqtt_entry(NX_IP* ip_ptr, NX_PACKET_POOL* pool_ptr, NX_DNS* dns_ptr, ULONG (*sntp_time_get)(VOID));
+
+#endif // _MQTT_H
diff --git a/Renesas/RSK_RX65N_2MB/app/main.c b/Renesas/RSK_RX65N_2MB/app/main.c
new file mode 100644
index 00000000..ea76b399
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/main.c
@@ -0,0 +1,96 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+
+#include <stdio.h>
+#include <time.h>
+
+#include "nx_driver_rx_fit.h"
+#include "tx_api.h"
+
+#include "board_init.h"
+#include "networking.h"
+#include "sntp_client.h"
+
+#include "legacy/mqtt.h"
+#include "nx_client.h"
+
+#include "azure_config.h"
+
+#define AZURE_THREAD_STACK_SIZE 4096
+#define AZURE_THREAD_PRIORITY   4
+
+TX_THREAD azure_thread;
+ULONG azure_thread_stack[AZURE_THREAD_STACK_SIZE / sizeof(ULONG)];
+
+void azure_thread_entry(ULONG parameter);
+void tx_application_define(void* first_unused_memory);
+
+void azure_thread_entry(ULONG parameter)
+{
+    UINT status;
+
+    printf("\r\nStarting Azure thread\r\n\r\n");
+
+    // Initialize the network
+    if (!network_init(nx_driver_rx_fit))
+    {
+        printf("Failed to initialize the network\r\n");
+        return;
+    }
+
+    // Start the SNTP client
+    status = sntp_start();
+    if (status != NX_SUCCESS)
+    {
+        printf("Failed to start the SNTP client (0x%02x)\r\n", status);
+        return;
+    }
+
+    // Wait for an SNTP sync
+    status = sntp_sync_wait();
+    if (status != NX_SUCCESS)
+    {
+        printf("Failed to start sync SNTP time (0x%02x)\r\n", status);
+        return;
+    }
+
+#ifdef ENABLE_LEGACY_MQTT
+    if ((status = azure_iot_mqtt_entry(&nx_ip, &nx_pool, &nx_dns_client, sntp_time_get)))
+#else
+    if ((status = azure_iot_nx_client_entry(&nx_ip, &nx_pool, &nx_dns_client, sntp_time)))
+#endif
+    {
+        printf("Failed to run Azure IoT (0x%04x)\r\n", status);
+        return;
+    }
+}
+
+void tx_application_define(void* first_unused_memory)
+{
+    // Create Azure SDK thread.
+    UINT status = tx_thread_create(&azure_thread,
+        "Azure Thread",
+        azure_thread_entry,
+        0,
+        azure_thread_stack,
+        AZURE_THREAD_STACK_SIZE,
+        AZURE_THREAD_PRIORITY,
+        AZURE_THREAD_PRIORITY,
+        TX_NO_TIME_SLICE,
+        TX_AUTO_START);
+
+    if (status != TX_SUCCESS)
+    {
+        printf("Azure IoT application failed, please restart\r\n");
+    }
+}
+
+int main(void)
+{
+    // Initialise the board
+    board_init();
+
+    tx_kernel_enter();
+
+    return 0;
+}
diff --git a/Renesas/RSK_RX65N_2MB/app/nx_client.c b/Renesas/RSK_RX65N_2MB/app/nx_client.c
new file mode 100644
index 00000000..e4257788
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/nx_client.c
@@ -0,0 +1,272 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+
+#include "nx_client.h"
+
+#include <stdio.h>
+
+#include "nx_api.h"
+#include "nx_azure_iot_hub_client.h"
+#include "nx_azure_iot_json_reader.h"
+#include "nx_azure_iot_provisioning_client.h"
+
+#include "azure_iot_nx_client.h"
+#include "nx_azure_iot_pnp_helpers.h"
+
+#include "azure_config.h"
+#include "azure_device_x509_cert_config.h"
+#include "azure_pnp_info.h"
+
+#include "platform.h"
+
+#define IOT_MODEL_ID "dtmi:azurertos:devkit:gsg;1"
+
+#define TELEMETRY_INTERVAL_PROPERTY "telemetryInterval"
+#define LED_STATE_PROPERTY          "ledState"
+#define SET_LED_STATE_COMMAND       "setLedState"
+
+#define TELEMETRY_INTERVAL_EVENT 1
+
+#define LED_ON  0
+#define LED_OFF 1
+#define LED0    PORT7.PODR.BIT.B3
+#define LED1    PORTG.PODR.BIT.B7
+#define LED2    PORTG.PODR.BIT.B6
+#define LED3    PORTG.PODR.BIT.B5
+
+static AZURE_IOT_NX_CONTEXT azure_iot_nx_client;
+static TX_EVENT_FLAGS_GROUP azure_iot_flags;
+
+static int32_t telemetry_interval = 10;
+
+static UINT append_device_info_properties(NX_AZURE_IOT_JSON_WRITER* json_writer, VOID* context)
+{
+    if (nx_azure_iot_json_writer_append_property_with_string_value(json_writer,
+            (UCHAR*)DEVICE_INFO_MANUFACTURER_PROPERTY_NAME,
+            sizeof(DEVICE_INFO_MANUFACTURER_PROPERTY_NAME) - 1,
+            (UCHAR*)DEVICE_INFO_MANUFACTURER_PROPERTY_VALUE,
+            sizeof(DEVICE_INFO_MANUFACTURER_PROPERTY_VALUE) - 1) ||
+        nx_azure_iot_json_writer_append_property_with_string_value(json_writer,
+            (UCHAR*)DEVICE_INFO_MODEL_PROPERTY_NAME,
+            sizeof(DEVICE_INFO_MODEL_PROPERTY_NAME) - 1,
+            (UCHAR*)DEVICE_INFO_MODEL_PROPERTY_VALUE,
+            sizeof(DEVICE_INFO_MODEL_PROPERTY_VALUE) - 1) ||
+        nx_azure_iot_json_writer_append_property_with_string_value(json_writer,
+            (UCHAR*)DEVICE_INFO_SW_VERSION_PROPERTY_NAME,
+            sizeof(DEVICE_INFO_SW_VERSION_PROPERTY_NAME) - 1,
+            (UCHAR*)DEVICE_INFO_SW_VERSION_PROPERTY_VALUE,
+            sizeof(DEVICE_INFO_SW_VERSION_PROPERTY_VALUE) - 1) ||
+        nx_azure_iot_json_writer_append_property_with_string_value(json_writer,
+            (UCHAR*)DEVICE_INFO_OS_NAME_PROPERTY_NAME,
+            sizeof(DEVICE_INFO_OS_NAME_PROPERTY_NAME) - 1,
+            (UCHAR*)DEVICE_INFO_OS_NAME_PROPERTY_VALUE,
+            sizeof(DEVICE_INFO_OS_NAME_PROPERTY_VALUE) - 1) ||
+        nx_azure_iot_json_writer_append_property_with_string_value(json_writer,
+            (UCHAR*)DEVICE_INFO_PROCESSOR_ARCHITECTURE_PROPERTY_NAME,
+            sizeof(DEVICE_INFO_PROCESSOR_ARCHITECTURE_PROPERTY_NAME) - 1,
+            (UCHAR*)DEVICE_INFO_PROCESSOR_ARCHITECTURE_PROPERTY_VALUE,
+            sizeof(DEVICE_INFO_PROCESSOR_ARCHITECTURE_PROPERTY_VALUE) - 1) ||
+        nx_azure_iot_json_writer_append_property_with_string_value(json_writer,
+            (UCHAR*)DEVICE_INFO_PROCESSOR_MANUFACTURER_PROPERTY_NAME,
+            sizeof(DEVICE_INFO_PROCESSOR_MANUFACTURER_PROPERTY_NAME) - 1,
+            (UCHAR*)DEVICE_INFO_PROCESSOR_MANUFACTURER_PROPERTY_VALUE,
+            sizeof(DEVICE_INFO_PROCESSOR_MANUFACTURER_PROPERTY_VALUE) - 1) ||
+        nx_azure_iot_json_writer_append_property_with_double_value(json_writer,
+            (UCHAR*)DEVICE_INFO_TOTAL_STORAGE_PROPERTY_NAME,
+            sizeof(DEVICE_INFO_TOTAL_STORAGE_PROPERTY_NAME) - 1,
+            DEVICE_INFO_TOTAL_STORAGE_PROPERTY_VALUE,
+            2) ||
+        nx_azure_iot_json_writer_append_property_with_double_value(json_writer,
+            (UCHAR*)DEVICE_INFO_TOTAL_MEMORY_PROPERTY_NAME,
+            sizeof(DEVICE_INFO_TOTAL_MEMORY_PROPERTY_NAME) - 1,
+            DEVICE_INFO_TOTAL_MEMORY_PROPERTY_VALUE,
+            2))
+    {
+        return NX_NOT_SUCCESSFUL;
+    }
+
+    return NX_AZURE_IOT_SUCCESS;
+}
+
+static void set_led_state(bool level)
+{
+    if (level)
+    {
+        printf("LED is turned ON\r\n");
+        LED0 = LED_ON;
+        LED1 = LED_ON;
+        LED2 = LED_ON;
+        LED3 = LED_ON;
+    }
+    else
+    {
+        printf("LED is turned OFF\r\n");
+        LED0 = LED_OFF;
+        LED1 = LED_OFF;
+        LED2 = LED_OFF;
+        LED3 = LED_OFF;
+    }
+}
+
+static void direct_method_cb(AZURE_IOT_NX_CONTEXT* nx_context,
+    const UCHAR* method,
+    USHORT method_length,
+    UCHAR* payload,
+    USHORT payload_length,
+    VOID* context,
+    USHORT context_length)
+{
+    UINT status;
+    UINT http_status    = 501;
+    CHAR* http_response = "{}";
+
+    if (strncmp((CHAR*)method, SET_LED_STATE_COMMAND, method_length) == 0)
+    {
+        bool arg = (strncmp((CHAR*)payload, "true", payload_length) == 0);
+        set_led_state(arg);
+
+        azure_iot_nx_client_publish_bool_property(&azure_iot_nx_client, LED_STATE_PROPERTY, arg);
+
+        http_status = 200;
+    }
+
+    if ((status = nx_azure_iot_hub_client_direct_method_message_response(&nx_context->iothub_client,
+             http_status,
+             context,
+             context_length,
+             (UCHAR*)http_response,
+             strlen(http_response),
+             NX_WAIT_FOREVER)))
+    {
+        printf("Direct method response failed! (0x%08x)\r\n", status);
+        return;
+    }
+}
+
+static void device_twin_desired_property_cb(UCHAR* component_name,
+    UINT component_name_len,
+    UCHAR* property_name,
+    UINT property_name_len,
+    NX_AZURE_IOT_JSON_READER property_value_reader,
+    UINT version,
+    VOID* userContextCallback)
+{
+    UINT status;
+    AZURE_IOT_NX_CONTEXT* nx_context = (AZURE_IOT_NX_CONTEXT*)userContextCallback;
+
+    if (strncmp((CHAR*)property_name, TELEMETRY_INTERVAL_PROPERTY, property_name_len) == 0)
+    {
+        status = nx_azure_iot_json_reader_token_int32_get(&property_value_reader, &telemetry_interval);
+        if (status == NX_AZURE_IOT_SUCCESS)
+        {
+            // Confirm reception back to hub
+            azure_nx_client_respond_int_writeable_property(
+                nx_context, TELEMETRY_INTERVAL_PROPERTY, telemetry_interval, 200, version);
+
+            // Set a telemetry event so we pick up the change immediately
+            tx_event_flags_set(&azure_iot_flags, TELEMETRY_INTERVAL_EVENT, TX_OR);
+        }
+    }
+}
+
+static void device_twin_property_cb(UCHAR* component_name,
+    UINT component_name_len,
+    UCHAR* property_name,
+    UINT property_name_len,
+    NX_AZURE_IOT_JSON_READER property_value_reader,
+    UINT version,
+    VOID* userContextCallback)
+{
+    if (strncmp((CHAR*)property_name, TELEMETRY_INTERVAL_PROPERTY, property_name_len) == 0)
+    {
+        nx_azure_iot_json_reader_token_int32_get(&property_value_reader, &telemetry_interval);
+    }
+}
+
+static void device_twin_received_cb(AZURE_IOT_NX_CONTEXT* nx_context)
+{
+    azure_iot_nx_client_publish_int_writeable_property(nx_context, TELEMETRY_INTERVAL_PROPERTY, telemetry_interval);
+    azure_iot_nx_client_publish_bool_property(&azure_iot_nx_client, LED_STATE_PROPERTY, false);
+    azure_iot_nx_client_publish_properties(
+        &azure_iot_nx_client, DEVICE_INFO_COMPONENT_NAME, append_device_info_properties);
+}
+
+UINT azure_iot_nx_client_entry(
+    NX_IP* ip_ptr, NX_PACKET_POOL* pool_ptr, NX_DNS* dns_ptr, UINT (*unix_time_callback)(ULONG* unix_time))
+{
+    UINT status;
+    ULONG events = 0;
+
+    if ((status = tx_event_flags_create(&azure_iot_flags, "Azure IoT flags")))
+    {
+        printf("FAIL: Unable to create nx_client event flags (0x%08x)\r\n", status);
+        return status;
+    }
+
+    status =
+        azure_iot_nx_client_create(&azure_iot_nx_client, ip_ptr, pool_ptr, dns_ptr, unix_time_callback, IOT_MODEL_ID);
+    if (status != NX_SUCCESS)
+    {
+        printf("ERROR: azure_iot_nx_client_create failed (0x%08x)\r\n", status);
+        return status;
+    }
+
+#ifdef ENABLE_X509
+    status = azure_iot_nx_client_cert_set(&azure_iot_nx_client,
+        (UCHAR*)iot_x509_device_cert,
+        iot_x509_device_cert_len,
+        (UCHAR*)iot_x509_private_key,
+        iot_x509_private_key_len);
+#else
+    status = azure_iot_nx_client_sas_set(&azure_iot_nx_client, IOT_DEVICE_SAS_KEY);
+#endif
+    if (status != NX_SUCCESS)
+    {
+        printf("ERROR: azure_iot_nx_client_[sas|cert]_set failed (0x%08x)\r\n", status);
+        return status;
+    }
+
+#ifdef ENABLE_DPS
+    azure_iot_nx_client_dps_create(&azure_iot_nx_client, IOT_DPS_ID_SCOPE, IOT_DPS_REGISTRATION_ID);
+#else
+    azure_iot_nx_client_hub_create(&azure_iot_nx_client, IOT_HUB_HOSTNAME, IOT_HUB_DEVICE_ID);
+#endif
+    if (status != NX_SUCCESS)
+    {
+        printf("ERROR: azure_iot_nx_client_[hub|dps]_create failed (0x%08x)\r\n", status);
+        return status;
+    }
+
+    // Register the callbacks
+    azure_iot_nx_client_register_direct_method(&azure_iot_nx_client, direct_method_cb);
+    azure_iot_nx_client_register_device_twin_desired_prop(&azure_iot_nx_client, device_twin_desired_property_cb);
+    azure_iot_nx_client_register_device_twin_prop(&azure_iot_nx_client, device_twin_property_cb);
+    azure_iot_nx_client_register_device_twin_received(&azure_iot_nx_client, device_twin_received_cb);
+
+    if ((status = azure_iot_nx_client_connect(&azure_iot_nx_client)))
+    {
+        printf("ERROR: failed to connect nx client (0x%08x)\r\n", status);
+        return status;
+    }
+
+    // Request the device twin for writeable property update
+    if ((status = nx_azure_iot_hub_client_device_twin_properties_request(
+             &azure_iot_nx_client.iothub_client, NX_WAIT_FOREVER)))
+    {
+        printf("ERROR: failed to request device twin (0x%08x)\r\n", status);
+        return status;
+    }
+
+    float temperature = 28.5;
+
+    printf("\r\nStarting Main loop\r\n");
+    while (true)
+    {
+        tx_event_flags_get(
+            &azure_iot_flags, TELEMETRY_INTERVAL_EVENT, TX_OR_CLEAR, &events, telemetry_interval * NX_IP_PERIODIC_RATE);
+
+        azure_iot_nx_client_publish_float_telemetry(&azure_iot_nx_client, "temperature", temperature);
+    }
+
+    return NX_SUCCESS;
+}
diff --git a/Renesas/RSK_RX65N_2MB/app/nx_client.h b/Renesas/RSK_RX65N_2MB/app/nx_client.h
new file mode 100644
index 00000000..179cf526
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/nx_client.h
@@ -0,0 +1,14 @@
+/* Copyright (c) Microsoft Corporation.
+   Licensed under the MIT License. */
+
+#ifndef _NX_CLIENT_H
+#define _NX_CLIENT_H
+
+#include "nx_api.h"
+#include "nxd_dns.h"
+#include "tx_api.h"
+
+UINT azure_iot_nx_client_entry(
+    NX_IP* ip_ptr, NX_PACKET_POOL* pool_ptr, NX_DNS* dns_ptr, UINT (*unix_time_callback)(ULONG* unix_time));
+
+#endif // _NX_CLIENT_H
\ No newline at end of file
diff --git a/Renesas/RSK_RX65N_2MB/app/startup/linker_script.ld b/Renesas/RSK_RX65N_2MB/app/startup/linker_script.ld
new file mode 100644
index 00000000..a26030c5
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/startup/linker_script.ld
@@ -0,0 +1,195 @@
+MEMORY
+{
+	RAM : ORIGIN = 0x4, LENGTH = 0x3fffc
+	RAM2 : ORIGIN = 0x00800000, LENGTH = 393216
+	ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152
+	OFS : ORIGIN = 0xFE7F5D00, LENGTH = 128
+}
+
+INCLUDE ../app/startup/linker_script_rvectors_extern.inc
+
+SECTIONS
+{
+	.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
+	{
+		"_exvectors_start" = .;
+		KEEP(*(.exvectors))
+	"_exvectors_end" = .;
+	} >ROM
+	.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
+	{
+		KEEP(*(.fvectors))
+	} > ROM
+	.text 0xFFE00000: AT(0xFFE00000)
+	{
+		*(.text)
+		*(.text.*)
+		*(P)
+		etext = .;
+	} > ROM
+	.rvectors ALIGN(4):
+	{
+		_rvectors_start = .;
+		INCLUDE ../app/startup/linker_script_rvectors.inc
+		_rvectors_end = .;
+	} > ROM
+	.init :
+	{
+		KEEP(*(.init))
+		__preinit_array_start = .;
+		KEEP(*(.preinit_array))
+		__preinit_array_end = .;
+		__init_array_start = (. + 3) & ~ 3;
+		KEEP(*(.init_array))
+		KEEP(*(SORT(.init_array.*)))
+		__init_array_end = .;
+		__fini_array_start = .;
+		KEEP(*(.fini_array))
+		KEEP(*(SORT(.fini_array.*)))
+		__fini_array_end = .;
+	} > ROM
+	.fini :
+	{
+		KEEP(*(.fini))
+	} > ROM
+	.got :
+	{
+		*(.got)
+		*(.got.plt)
+	} > ROM
+	.rodata :
+	{
+		*(.rodata)
+		*(.rodata.*)
+		*(C_1)
+		*(C_2)
+		*(C)
+		_erodata = .;
+	} > ROM
+	.eh_frame_hdr :
+	{
+		*(.eh_frame_hdr)
+	} > ROM
+	.eh_frame :
+	{
+		*(.eh_frame)
+	} > ROM
+	.jcr :
+	{
+		*(.jcr)
+	} > ROM
+	.tors :
+	{
+		__CTOR_LIST__ = .;
+		. = ALIGN(2);
+		___ctors = .;
+		*(.ctors)
+		___ctors_end = .;
+		__CTOR_END__ = .;
+		__DTOR_LIST__ = .;
+		___dtors = .;
+		*(.dtors)
+		___dtors_end = .;
+		__DTOR_END__ = .;
+		. = ALIGN(2);
+		_mdata = .;
+	} > ROM
+	B_ETHERNET_BUFFERS_1 0x00010000 (NOLOAD) : AT(0x00010000)
+    {
+        _B_ETHERNET_BUFFERS_1_start = .;
+        *(B_ETHERNET_BUFFERS_1)
+        _B_ETHERNET_BUFFERS_1_end = .;
+    } >RAM
+        B_RX_DESC_1 (NOLOAD) :
+    {
+        _B_RX_DESC_1_start = .;
+        *(B_RX_DESC_1)
+        _B_RX_DESC_1_end = .;
+    } >RAM
+        B_TX_DESC_1 (NOLOAD) :
+    {
+        _B_TX_DESC_1_start = .;
+        *(B_TX_DESC_1)
+        _B_TX_DESC_1_end = .;
+    } >RAM
+	.data : AT(_mdata)
+	{
+		_data = .;
+		*(.data)
+		*(.data.*)
+		*(D)
+		*(D_1)
+		*(D_2)
+		_edata = .;
+	} > RAM
+	.gcc_exc :
+	{
+		*(.gcc_exc)
+	} > RAM
+	
+	.bss :
+	{
+		_bss = .;
+		*(.bss)
+		*(.bss.**)
+		*(COMMON)
+		*(B)
+		*(B_1)
+		*(B_2)
+		_ebss = .;
+		_end = .;
+	} > RAM2
+	.ofs1 0xFE7F5D00: AT(0xFE7F5D00)
+	{
+		KEEP(*(.ofs1))
+	} > OFS
+	.ofs2 0xFE7F5D10: AT(0xFE7F5D10)
+	{
+		KEEP(*(.ofs2))
+	} > OFS
+	.ofs3 0xFE7F5D20: AT(0xFE7F5D20)
+	{
+		KEEP(*(.ofs3))
+	} > OFS
+	.ofs4 0xFE7F5D40: AT(0xFE7F5D40)
+	{
+		KEEP(*(.ofs4))
+	} > OFS
+	.ofs5 0xFE7F5D48: AT(0xFE7F5D48)
+	{
+		KEEP(*(.ofs5))
+	} > OFS
+	.ofs6 0xFE7F5D50: AT(0xFE7F5D50)
+	{
+		KEEP(*(.ofs6))
+	} > OFS
+	.ofs7 0xFE7F5D64: AT(0xFE7F5D64)
+	{
+		KEEP(*(.ofs7))
+	} > OFS
+	.ofs8 0xFE7F5D70: AT(0xFE7F5D70)
+	{
+		KEEP(*(.ofs8))
+	} > OFS
+	.r_bsp_NULL :
+	{
+		. += 0x100;
+		"_r_bsp_NULL_end" = .;
+	} >RAM
+.r_bsp_istack BLOCK(0x4) (NOLOAD) :
+	{
+		KEEP(*(.r_bsp_istack))
+	} >RAM
+.istack :
+	{
+		"_istack" = .;
+	} >RAM
+.r_bsp_ustack BLOCK(0x4) (NOLOAD) :
+	{
+		KEEP(*(.r_bsp_ustack))
+	} >RAM
+.ustack :
+	{
+		"_ustack" = .;
+	} >RAM
+}
diff --git a/Renesas/RSK_RX65N_2MB/app/startup/linker_script_rvectors.inc b/Renesas/RSK_RX65N_2MB/app/startup/linker_script_rvectors.inc
new file mode 100644
index 00000000..d30ad475
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/startup/linker_script_rvectors.inc
@@ -0,0 +1,283 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : linker_script_rvectors.inc
+* Description  : This module is used to set the interrupt table.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+***********************************************************************************************************************/
+
+LONG(DEFINED($tableentry$0$.rvectors) ? $tableentry$0$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$1$.rvectors) ? $tableentry$1$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$2$.rvectors) ? $tableentry$2$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$3$.rvectors) ? $tableentry$3$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$4$.rvectors) ? $tableentry$4$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$5$.rvectors) ? $tableentry$5$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$6$.rvectors) ? $tableentry$6$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$7$.rvectors) ? $tableentry$7$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$8$.rvectors) ? $tableentry$8$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$9$.rvectors) ? $tableentry$9$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$10$.rvectors) ? $tableentry$10$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$11$.rvectors) ? $tableentry$11$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$12$.rvectors) ? $tableentry$12$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$13$.rvectors) ? $tableentry$13$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$14$.rvectors) ? $tableentry$14$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$15$.rvectors) ? $tableentry$15$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$16$.rvectors) ? $tableentry$16$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$17$.rvectors) ? $tableentry$17$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$18$.rvectors) ? $tableentry$18$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$19$.rvectors) ? $tableentry$19$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$20$.rvectors) ? $tableentry$20$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$21$.rvectors) ? $tableentry$21$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$22$.rvectors) ? $tableentry$22$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$23$.rvectors) ? $tableentry$23$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$24$.rvectors) ? $tableentry$24$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$25$.rvectors) ? $tableentry$25$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$26$.rvectors) ? $tableentry$26$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$27$.rvectors) ? $tableentry$27$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$28$.rvectors) ? $tableentry$28$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$29$.rvectors) ? $tableentry$29$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$30$.rvectors) ? $tableentry$30$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$31$.rvectors) ? $tableentry$31$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$32$.rvectors) ? $tableentry$32$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$33$.rvectors) ? $tableentry$33$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$34$.rvectors) ? $tableentry$34$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$35$.rvectors) ? $tableentry$35$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$36$.rvectors) ? $tableentry$36$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$37$.rvectors) ? $tableentry$37$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$38$.rvectors) ? $tableentry$38$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$39$.rvectors) ? $tableentry$39$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$40$.rvectors) ? $tableentry$40$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$41$.rvectors) ? $tableentry$41$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$42$.rvectors) ? $tableentry$42$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$43$.rvectors) ? $tableentry$43$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$44$.rvectors) ? $tableentry$44$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$45$.rvectors) ? $tableentry$45$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$46$.rvectors) ? $tableentry$46$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$47$.rvectors) ? $tableentry$47$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$48$.rvectors) ? $tableentry$48$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$49$.rvectors) ? $tableentry$49$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$50$.rvectors) ? $tableentry$50$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$51$.rvectors) ? $tableentry$51$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$52$.rvectors) ? $tableentry$52$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$53$.rvectors) ? $tableentry$53$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$54$.rvectors) ? $tableentry$54$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$55$.rvectors) ? $tableentry$55$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$56$.rvectors) ? $tableentry$56$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$57$.rvectors) ? $tableentry$57$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$58$.rvectors) ? $tableentry$58$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$59$.rvectors) ? $tableentry$59$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$60$.rvectors) ? $tableentry$60$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$61$.rvectors) ? $tableentry$61$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$62$.rvectors) ? $tableentry$62$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$63$.rvectors) ? $tableentry$63$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$64$.rvectors) ? $tableentry$64$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$65$.rvectors) ? $tableentry$65$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$66$.rvectors) ? $tableentry$66$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$67$.rvectors) ? $tableentry$67$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$68$.rvectors) ? $tableentry$68$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$69$.rvectors) ? $tableentry$69$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$70$.rvectors) ? $tableentry$70$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$71$.rvectors) ? $tableentry$71$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$72$.rvectors) ? $tableentry$72$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$73$.rvectors) ? $tableentry$73$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$74$.rvectors) ? $tableentry$74$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$75$.rvectors) ? $tableentry$75$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$76$.rvectors) ? $tableentry$76$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$77$.rvectors) ? $tableentry$77$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$78$.rvectors) ? $tableentry$78$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$79$.rvectors) ? $tableentry$79$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$80$.rvectors) ? $tableentry$80$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$81$.rvectors) ? $tableentry$81$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$82$.rvectors) ? $tableentry$82$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$83$.rvectors) ? $tableentry$83$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$84$.rvectors) ? $tableentry$84$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$85$.rvectors) ? $tableentry$85$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$86$.rvectors) ? $tableentry$86$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$87$.rvectors) ? $tableentry$87$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$88$.rvectors) ? $tableentry$88$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$89$.rvectors) ? $tableentry$89$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$90$.rvectors) ? $tableentry$90$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$91$.rvectors) ? $tableentry$91$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$92$.rvectors) ? $tableentry$92$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$93$.rvectors) ? $tableentry$93$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$94$.rvectors) ? $tableentry$94$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$95$.rvectors) ? $tableentry$95$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$96$.rvectors) ? $tableentry$96$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$97$.rvectors) ? $tableentry$97$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$98$.rvectors) ? $tableentry$98$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$99$.rvectors) ? $tableentry$99$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$100$.rvectors) ? $tableentry$100$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$101$.rvectors) ? $tableentry$101$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$102$.rvectors) ? $tableentry$102$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$103$.rvectors) ? $tableentry$103$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$104$.rvectors) ? $tableentry$104$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$105$.rvectors) ? $tableentry$105$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$106$.rvectors) ? $tableentry$106$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$107$.rvectors) ? $tableentry$107$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$108$.rvectors) ? $tableentry$108$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$109$.rvectors) ? $tableentry$109$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$110$.rvectors) ? $tableentry$110$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$111$.rvectors) ? $tableentry$111$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$112$.rvectors) ? $tableentry$112$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$113$.rvectors) ? $tableentry$113$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$114$.rvectors) ? $tableentry$114$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$115$.rvectors) ? $tableentry$115$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$116$.rvectors) ? $tableentry$116$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$117$.rvectors) ? $tableentry$117$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$118$.rvectors) ? $tableentry$118$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$119$.rvectors) ? $tableentry$119$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$120$.rvectors) ? $tableentry$120$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$121$.rvectors) ? $tableentry$121$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$122$.rvectors) ? $tableentry$122$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$123$.rvectors) ? $tableentry$123$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$124$.rvectors) ? $tableentry$124$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$125$.rvectors) ? $tableentry$125$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$126$.rvectors) ? $tableentry$126$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$127$.rvectors) ? $tableentry$127$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$128$.rvectors) ? $tableentry$128$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$129$.rvectors) ? $tableentry$129$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$130$.rvectors) ? $tableentry$130$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$131$.rvectors) ? $tableentry$131$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$132$.rvectors) ? $tableentry$132$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$133$.rvectors) ? $tableentry$133$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$134$.rvectors) ? $tableentry$134$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$135$.rvectors) ? $tableentry$135$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$136$.rvectors) ? $tableentry$136$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$137$.rvectors) ? $tableentry$137$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$138$.rvectors) ? $tableentry$138$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$139$.rvectors) ? $tableentry$139$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$140$.rvectors) ? $tableentry$140$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$141$.rvectors) ? $tableentry$141$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$142$.rvectors) ? $tableentry$142$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$143$.rvectors) ? $tableentry$143$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$144$.rvectors) ? $tableentry$144$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$145$.rvectors) ? $tableentry$145$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$146$.rvectors) ? $tableentry$146$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$147$.rvectors) ? $tableentry$147$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$148$.rvectors) ? $tableentry$148$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$149$.rvectors) ? $tableentry$149$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$150$.rvectors) ? $tableentry$150$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$151$.rvectors) ? $tableentry$151$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$152$.rvectors) ? $tableentry$152$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$153$.rvectors) ? $tableentry$153$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$154$.rvectors) ? $tableentry$154$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$155$.rvectors) ? $tableentry$155$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$156$.rvectors) ? $tableentry$156$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$157$.rvectors) ? $tableentry$157$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$158$.rvectors) ? $tableentry$158$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$159$.rvectors) ? $tableentry$159$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$160$.rvectors) ? $tableentry$160$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$161$.rvectors) ? $tableentry$161$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$162$.rvectors) ? $tableentry$162$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$163$.rvectors) ? $tableentry$163$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$164$.rvectors) ? $tableentry$164$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$165$.rvectors) ? $tableentry$165$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$166$.rvectors) ? $tableentry$166$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$167$.rvectors) ? $tableentry$167$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$168$.rvectors) ? $tableentry$168$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$169$.rvectors) ? $tableentry$169$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$170$.rvectors) ? $tableentry$170$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$171$.rvectors) ? $tableentry$171$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$172$.rvectors) ? $tableentry$172$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$173$.rvectors) ? $tableentry$173$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$174$.rvectors) ? $tableentry$174$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$175$.rvectors) ? $tableentry$175$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$176$.rvectors) ? $tableentry$176$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$177$.rvectors) ? $tableentry$177$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$178$.rvectors) ? $tableentry$178$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$179$.rvectors) ? $tableentry$179$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$180$.rvectors) ? $tableentry$180$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$181$.rvectors) ? $tableentry$181$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$182$.rvectors) ? $tableentry$182$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$183$.rvectors) ? $tableentry$183$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$184$.rvectors) ? $tableentry$184$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$185$.rvectors) ? $tableentry$185$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$186$.rvectors) ? $tableentry$186$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$187$.rvectors) ? $tableentry$187$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$188$.rvectors) ? $tableentry$188$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$189$.rvectors) ? $tableentry$189$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$190$.rvectors) ? $tableentry$190$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$191$.rvectors) ? $tableentry$191$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$192$.rvectors) ? $tableentry$192$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$193$.rvectors) ? $tableentry$193$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$194$.rvectors) ? $tableentry$194$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$195$.rvectors) ? $tableentry$195$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$196$.rvectors) ? $tableentry$196$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$197$.rvectors) ? $tableentry$197$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$198$.rvectors) ? $tableentry$198$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$199$.rvectors) ? $tableentry$199$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$200$.rvectors) ? $tableentry$200$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$201$.rvectors) ? $tableentry$201$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$202$.rvectors) ? $tableentry$202$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$203$.rvectors) ? $tableentry$203$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$204$.rvectors) ? $tableentry$204$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$205$.rvectors) ? $tableentry$205$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$206$.rvectors) ? $tableentry$206$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$207$.rvectors) ? $tableentry$207$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$208$.rvectors) ? $tableentry$208$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$209$.rvectors) ? $tableentry$209$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$210$.rvectors) ? $tableentry$210$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$211$.rvectors) ? $tableentry$211$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$212$.rvectors) ? $tableentry$212$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$213$.rvectors) ? $tableentry$213$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$214$.rvectors) ? $tableentry$214$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$215$.rvectors) ? $tableentry$215$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$216$.rvectors) ? $tableentry$216$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$217$.rvectors) ? $tableentry$217$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$218$.rvectors) ? $tableentry$218$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$219$.rvectors) ? $tableentry$219$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$220$.rvectors) ? $tableentry$220$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$221$.rvectors) ? $tableentry$221$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$222$.rvectors) ? $tableentry$222$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$223$.rvectors) ? $tableentry$223$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$224$.rvectors) ? $tableentry$224$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$225$.rvectors) ? $tableentry$225$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$226$.rvectors) ? $tableentry$226$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$227$.rvectors) ? $tableentry$227$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$228$.rvectors) ? $tableentry$228$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$229$.rvectors) ? $tableentry$229$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$230$.rvectors) ? $tableentry$230$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$231$.rvectors) ? $tableentry$231$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$232$.rvectors) ? $tableentry$232$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$233$.rvectors) ? $tableentry$233$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$234$.rvectors) ? $tableentry$234$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$235$.rvectors) ? $tableentry$235$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$236$.rvectors) ? $tableentry$236$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$237$.rvectors) ? $tableentry$237$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$238$.rvectors) ? $tableentry$238$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$239$.rvectors) ? $tableentry$239$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$240$.rvectors) ? $tableentry$240$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$241$.rvectors) ? $tableentry$241$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$242$.rvectors) ? $tableentry$242$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$243$.rvectors) ? $tableentry$243$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$244$.rvectors) ? $tableentry$244$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$245$.rvectors) ? $tableentry$245$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$246$.rvectors) ? $tableentry$246$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$247$.rvectors) ? $tableentry$247$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$248$.rvectors) ? $tableentry$248$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$249$.rvectors) ? $tableentry$249$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$250$.rvectors) ? $tableentry$250$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$251$.rvectors) ? $tableentry$251$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$252$.rvectors) ? $tableentry$252$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$253$.rvectors) ? $tableentry$253$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$254$.rvectors) ? $tableentry$254$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$255$.rvectors) ? $tableentry$255$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
diff --git a/Renesas/RSK_RX65N_2MB/app/startup/linker_script_rvectors_extern.inc b/Renesas/RSK_RX65N_2MB/app/startup/linker_script_rvectors_extern.inc
new file mode 100644
index 00000000..4615190d
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/startup/linker_script_rvectors_extern.inc
@@ -0,0 +1,258 @@
+EXTERN(
+    $tableentry$0$.rvectors
+    $tableentry$1$.rvectors
+    $tableentry$2$.rvectors
+    $tableentry$3$.rvectors
+    $tableentry$4$.rvectors
+    $tableentry$5$.rvectors
+    $tableentry$6$.rvectors
+    $tableentry$7$.rvectors
+    $tableentry$8$.rvectors
+    $tableentry$9$.rvectors
+    $tableentry$10$.rvectors
+    $tableentry$11$.rvectors
+    $tableentry$12$.rvectors
+    $tableentry$13$.rvectors
+    $tableentry$14$.rvectors
+    $tableentry$15$.rvectors
+    $tableentry$16$.rvectors
+    $tableentry$17$.rvectors
+    $tableentry$18$.rvectors
+    $tableentry$19$.rvectors
+    $tableentry$20$.rvectors
+    $tableentry$21$.rvectors
+    $tableentry$22$.rvectors
+    $tableentry$23$.rvectors
+    $tableentry$24$.rvectors
+    $tableentry$25$.rvectors
+    $tableentry$26$.rvectors
+    $tableentry$27$.rvectors
+    $tableentry$28$.rvectors
+    $tableentry$29$.rvectors
+    $tableentry$30$.rvectors
+    $tableentry$31$.rvectors
+    $tableentry$32$.rvectors
+    $tableentry$33$.rvectors
+    $tableentry$34$.rvectors
+    $tableentry$35$.rvectors
+    $tableentry$36$.rvectors
+    $tableentry$37$.rvectors
+    $tableentry$38$.rvectors
+    $tableentry$39$.rvectors
+    $tableentry$40$.rvectors
+    $tableentry$41$.rvectors
+    $tableentry$42$.rvectors
+    $tableentry$43$.rvectors
+    $tableentry$44$.rvectors
+    $tableentry$45$.rvectors
+    $tableentry$46$.rvectors
+    $tableentry$47$.rvectors
+    $tableentry$48$.rvectors
+    $tableentry$49$.rvectors
+    $tableentry$50$.rvectors
+    $tableentry$51$.rvectors
+    $tableentry$52$.rvectors
+    $tableentry$53$.rvectors
+    $tableentry$54$.rvectors
+    $tableentry$55$.rvectors
+    $tableentry$56$.rvectors
+    $tableentry$57$.rvectors
+    $tableentry$58$.rvectors
+    $tableentry$59$.rvectors
+    $tableentry$60$.rvectors
+    $tableentry$61$.rvectors
+    $tableentry$62$.rvectors
+    $tableentry$63$.rvectors
+    $tableentry$64$.rvectors
+    $tableentry$65$.rvectors
+    $tableentry$66$.rvectors
+    $tableentry$67$.rvectors
+    $tableentry$68$.rvectors
+    $tableentry$69$.rvectors
+    $tableentry$70$.rvectors
+    $tableentry$71$.rvectors
+    $tableentry$72$.rvectors
+    $tableentry$73$.rvectors
+    $tableentry$74$.rvectors
+    $tableentry$75$.rvectors
+    $tableentry$76$.rvectors
+    $tableentry$77$.rvectors
+    $tableentry$78$.rvectors
+    $tableentry$79$.rvectors
+    $tableentry$80$.rvectors
+    $tableentry$81$.rvectors
+    $tableentry$82$.rvectors
+    $tableentry$83$.rvectors
+    $tableentry$84$.rvectors
+    $tableentry$85$.rvectors
+    $tableentry$86$.rvectors
+    $tableentry$87$.rvectors
+    $tableentry$88$.rvectors
+    $tableentry$89$.rvectors
+    $tableentry$90$.rvectors
+    $tableentry$91$.rvectors
+    $tableentry$92$.rvectors
+    $tableentry$93$.rvectors
+    $tableentry$94$.rvectors
+    $tableentry$95$.rvectors
+    $tableentry$96$.rvectors
+    $tableentry$97$.rvectors
+    $tableentry$98$.rvectors
+    $tableentry$99$.rvectors
+    $tableentry$100$.rvectors
+    $tableentry$101$.rvectors
+    $tableentry$102$.rvectors
+    $tableentry$103$.rvectors
+    $tableentry$104$.rvectors
+    $tableentry$105$.rvectors
+    $tableentry$106$.rvectors
+    $tableentry$107$.rvectors
+    $tableentry$108$.rvectors
+    $tableentry$109$.rvectors
+    $tableentry$110$.rvectors
+    $tableentry$111$.rvectors
+    $tableentry$112$.rvectors
+    $tableentry$113$.rvectors
+    $tableentry$114$.rvectors
+    $tableentry$115$.rvectors
+    $tableentry$116$.rvectors
+    $tableentry$117$.rvectors
+    $tableentry$118$.rvectors
+    $tableentry$119$.rvectors
+    $tableentry$120$.rvectors
+    $tableentry$121$.rvectors
+    $tableentry$122$.rvectors
+    $tableentry$123$.rvectors
+    $tableentry$124$.rvectors
+    $tableentry$125$.rvectors
+    $tableentry$126$.rvectors
+    $tableentry$127$.rvectors
+    $tableentry$128$.rvectors
+    $tableentry$129$.rvectors
+    $tableentry$130$.rvectors
+    $tableentry$131$.rvectors
+    $tableentry$132$.rvectors
+    $tableentry$133$.rvectors
+    $tableentry$134$.rvectors
+    $tableentry$135$.rvectors
+    $tableentry$136$.rvectors
+    $tableentry$137$.rvectors
+    $tableentry$138$.rvectors
+    $tableentry$139$.rvectors
+    $tableentry$140$.rvectors
+    $tableentry$141$.rvectors
+    $tableentry$142$.rvectors
+    $tableentry$143$.rvectors
+    $tableentry$144$.rvectors
+    $tableentry$145$.rvectors
+    $tableentry$146$.rvectors
+    $tableentry$147$.rvectors
+    $tableentry$148$.rvectors
+    $tableentry$149$.rvectors
+    $tableentry$150$.rvectors
+    $tableentry$151$.rvectors
+    $tableentry$152$.rvectors
+    $tableentry$153$.rvectors
+    $tableentry$154$.rvectors
+    $tableentry$155$.rvectors
+    $tableentry$156$.rvectors
+    $tableentry$157$.rvectors
+    $tableentry$158$.rvectors
+    $tableentry$159$.rvectors
+    $tableentry$160$.rvectors
+    $tableentry$161$.rvectors
+    $tableentry$162$.rvectors
+    $tableentry$163$.rvectors
+    $tableentry$164$.rvectors
+    $tableentry$165$.rvectors
+    $tableentry$166$.rvectors
+    $tableentry$167$.rvectors
+    $tableentry$168$.rvectors
+    $tableentry$169$.rvectors
+    $tableentry$170$.rvectors
+    $tableentry$171$.rvectors
+    $tableentry$172$.rvectors
+    $tableentry$173$.rvectors
+    $tableentry$174$.rvectors
+    $tableentry$175$.rvectors
+    $tableentry$176$.rvectors
+    $tableentry$177$.rvectors
+    $tableentry$178$.rvectors
+    $tableentry$179$.rvectors
+    $tableentry$180$.rvectors
+    $tableentry$181$.rvectors
+    $tableentry$182$.rvectors
+    $tableentry$183$.rvectors
+    $tableentry$184$.rvectors
+    $tableentry$185$.rvectors
+    $tableentry$186$.rvectors
+    $tableentry$187$.rvectors
+    $tableentry$188$.rvectors
+    $tableentry$189$.rvectors
+    $tableentry$190$.rvectors
+    $tableentry$191$.rvectors
+    $tableentry$192$.rvectors
+    $tableentry$193$.rvectors
+    $tableentry$194$.rvectors
+    $tableentry$195$.rvectors
+    $tableentry$196$.rvectors
+    $tableentry$197$.rvectors
+    $tableentry$198$.rvectors
+    $tableentry$199$.rvectors
+    $tableentry$200$.rvectors
+    $tableentry$201$.rvectors
+    $tableentry$202$.rvectors
+    $tableentry$203$.rvectors
+    $tableentry$204$.rvectors
+    $tableentry$205$.rvectors
+    $tableentry$206$.rvectors
+    $tableentry$207$.rvectors
+    $tableentry$208$.rvectors
+    $tableentry$209$.rvectors
+    $tableentry$210$.rvectors
+    $tableentry$211$.rvectors
+    $tableentry$212$.rvectors
+    $tableentry$213$.rvectors
+    $tableentry$214$.rvectors
+    $tableentry$215$.rvectors
+    $tableentry$216$.rvectors
+    $tableentry$217$.rvectors
+    $tableentry$218$.rvectors
+    $tableentry$219$.rvectors
+    $tableentry$220$.rvectors
+    $tableentry$221$.rvectors
+    $tableentry$222$.rvectors
+    $tableentry$223$.rvectors
+    $tableentry$224$.rvectors
+    $tableentry$225$.rvectors
+    $tableentry$226$.rvectors
+    $tableentry$227$.rvectors
+    $tableentry$228$.rvectors
+    $tableentry$229$.rvectors
+    $tableentry$230$.rvectors
+    $tableentry$231$.rvectors
+    $tableentry$232$.rvectors
+    $tableentry$233$.rvectors
+    $tableentry$234$.rvectors
+    $tableentry$235$.rvectors
+    $tableentry$236$.rvectors
+    $tableentry$237$.rvectors
+    $tableentry$238$.rvectors
+    $tableentry$239$.rvectors
+    $tableentry$240$.rvectors
+    $tableentry$241$.rvectors
+    $tableentry$242$.rvectors
+    $tableentry$243$.rvectors
+    $tableentry$244$.rvectors
+    $tableentry$245$.rvectors
+    $tableentry$246$.rvectors
+    $tableentry$247$.rvectors
+    $tableentry$248$.rvectors
+    $tableentry$249$.rvectors
+    $tableentry$250$.rvectors
+    $tableentry$251$.rvectors
+    $tableentry$252$.rvectors
+    $tableentry$253$.rvectors
+    $tableentry$254$.rvectors
+    $tableentry$255$.rvectors
+)
\ No newline at end of file
diff --git a/Renesas/RSK_RX65N_2MB/app/startup/tx_initialize_low_level.S b/Renesas/RSK_RX65N_2MB/app/startup/tx_initialize_low_level.S
new file mode 100644
index 00000000..402796e2
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/app/startup/tx_initialize_low_level.S
@@ -0,0 +1,93 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+
+    .text
+
+;
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_initialize_low_level                             RX/GNURX       */
+;/*                                                           6.1          */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for any low-level processor            */
+;/*    initialization, including setting up interrupt vectors, setting     */
+;/*    up a periodic timer interrupt source, saving the system stack       */
+;/*    pointer for use in ISR processing later, and finding the first      */
+;/*    available RAM memory address for tx_application_define.             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  11-23-2020     William E. Lamie         Initial Version 6.1           */
+;/*                                                                        */
+;/**************************************************************************/
+    .global __tx_initialize_low_level
+__tx_initialize_low_level:
+
+;
+;    /* Save the first available memory address.  */
+;    _tx_initialize_unused_memory =  (VOID_PTR) &free_mem_start;
+;
+    MOV.L    #_end, R1                ; Pickup unused memory address
+    MOV.L    #__tx_initialize_unused_memory, R2
+    MOV.L    R1,[R2]                            ; Save first free memory address
+
+;   /* Set priority of SWINT to 1. */
+    MOV.L    #0x87303, r1
+    MOV.L    #1, r2
+    MOV.B    r2, [r1]
+
+;   /* Enable SWINT. */
+    MOV.L    #0x87203,r1
+    MOV.B    [r1], r2
+    OR       #(1 << 3), r2
+    MOV.B    r2, [r1]
+
+    RTS
+
+
+    .end
diff --git a/Renesas/RSK_RX65N_2MB/lib/CMakeLists.txt b/Renesas/RSK_RX65N_2MB/lib/CMakeLists.txt
new file mode 100644
index 00000000..e5005f31
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/CMakeLists.txt
@@ -0,0 +1,25 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+# Define the CPU architecture for Threadx
+set(THREADX_ARCH "rxv2")
+set(THREADX_TOOLCHAIN "gnu")
+
+# Define ThreadX user configuration
+set(TX_USER_FILE "${CMAKE_CURRENT_LIST_DIR}/threadx/tx_user.h" CACHE STRING "Enable TX user configuration")
+
+# Define NetXDuo user configuration
+set(NX_USER_FILE "${CMAKE_CURRENT_LIST_DIR}/netxduo/nx_user.h" CACHE STRING "Enable NX user configuration")
+set(NXD_ENABLE_AZURE_IOT ON CACHE BOOL "Enable Azure IoT")
+set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo")
+
+# Enable security module
+set(NX_AZURE_DISABLE_IOT_SECURITY_MODULE OFF CACHE BOOL "Security Module")
+
+# Core libraries
+add_subdirectory(${CORE_LIB_DIR}/threadx threadx)
+add_subdirectory(${CORE_LIB_DIR}/netxduo netxduo)
+add_subdirectory(${CORE_LIB_DIR}/jsmn jsmn)
+
+add_subdirectory(netx_driver)
+add_subdirectory(rx_driver_package)
diff --git a/Renesas/RSK_RX65N_2MB/lib/netx_driver/CMakeLists.txt b/Renesas/RSK_RX65N_2MB/lib/netx_driver/CMakeLists.txt
new file mode 100644
index 00000000..aa4eff73
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/netx_driver/CMakeLists.txt
@@ -0,0 +1,24 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+set(SOURCES
+    src/nx_driver_rx_fit.c
+)
+
+set(TARGET netx_driver)
+
+add_library(${TARGET} OBJECT
+    ${SOURCES}
+)
+
+target_include_directories(${TARGET}
+    PUBLIC
+        src
+)
+
+target_link_libraries(${TARGET} 
+    PUBLIC
+        azrtos::threadx
+        azrtos::netxduo
+        rx_driver_package
+)
diff --git a/Renesas/RSK_RX65N_2MB/lib/netx_driver/LICENSE.txt b/Renesas/RSK_RX65N_2MB/lib/netx_driver/LICENSE.txt
new file mode 100644
index 00000000..76974a36
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/netx_driver/LICENSE.txt
@@ -0,0 +1,246 @@
+MICROSOFT SOFTWARE LICENSE TERMS 
+
+MICROSOFT AZURE RTOS 
+
+Shape 
+
+These license terms are an agreement between you and Microsoft Corporation (or
+one of its affiliates). They apply to the software named above and any Microsoft
+services or software updates (except to the extent such services or updates are
+accompanied by new or additional terms, in which case those different terms
+apply prospectively and do not alter your or Microsoft’s rights relating to
+pre-updated software or services). IF YOU COMPLY WITH THESE LICENSE TERMS, YOU
+HAVE THE RIGHTS BELOW.  BY USING THE SOFTWARE, YOU ACCEPT THESE TERMS. 
+
+INSTALLATION AND USE RIGHTS.  
+
+General. You may install and use the software and the included Microsoft
+applications solely for internal development, testing and evaluation purposes.
+Any distribution or production use requires a separate license as set forth in
+Section 2.  
+
+Contributions. Microsoft welcomes contributions to this software. In the event
+that you make a contribution to this software you will be required to agree to a
+Contributor License Agreement (CLA) declaring that you have the right to, and
+actually do, grant Microsoft the rights to use your contribution. For details,
+visit https://cla.microsoft.com.  
+
+Included Microsoft Applications. The software includes other Microsoft
+applications which are governed by the licenses embedded in or made available
+with those applications.  
+
+Third Party Components. The software may include third party components with
+separate legal notices or governed by other agreements, as may be described
+within the software or in the ThirdPartyNotices file(s) accompanying the
+software. 
+
+Competitive Benchmarking. If you are a direct competitor, and you access or use
+the software for purposes of competitive benchmarking, analysis, or intelligence
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+Microsoft’s terms. If you do not waive any such purported restrictions in the
+terms governing your software, you are not allowed to access or use this
+software, and will not do so. 
+
+DISTRIBUTION AND PRODUCTION USE. If you have obtained and/or are developing on
+microprocessor(s) and/or microcontroller(s) (“hardware”) listed in the file
+named “LICENSED-HARDWARE.txt” included in the repository and/or distributed with
+the software you have the following rights in and to the software solely when
+used in combination with the hardware. In the event hardware is not listed in
+the LICENSED-HARDWARE.txt file, you do not have the rights in this Section 2. 
+
+Distribution and Production Use Rights.  
+
+You may use the software in production (e.g. program the modified or unmodified
+software to devices you own or control) and distribute (i.e. make available to
+third parties) the modified or unmodified binary image produced from this code.
+
+
+You may permit your device distributors or developers to copy and distribute the
+binary image as programmed or to be programmed to your devices. 
+
+You may redistribute the unmodified or modified source to your device
+distributors or developers. Modifications must be clearly marked. Any
+redistribution in source code form must contain this license and any other
+licenses that accompany the software. 
+
+Requirements. For any code you distribute, you must: 
+
+when distributed in binary form, except as embedded in a device, include with
+such distribution the terms of this agreement;  
+
+when distributed in source code form to distributors or developers of your
+devices, include with such distribution the terms of this agreement; and 
+
+indemnify, defend and hold harmless Microsoft from  any claims, including
+attorneys’ fees, related to the distribution or use of your devices, except to
+the extent that any claim is based solely on the unmodified software. 
+
+Restrictions. You may not: 
+
+use or modify the software to create a competing real time operating system
+software;  
+
+remove any copyright notices or licenses contained in the software; 
+
+use Microsoft’s trademarks or trade dress in your application in any way that
+suggests your device or application comes from or is endorsed by Microsoft;  
+
+transfer individual components, specific libraries, classes, functions or code
+fragments of the software separately for purposes unrelated to the software; or 
+
+use or distribute the software in any way that would subject the software or
+Microsoft’s intellectual property or technology to any other license terms. 
+
+SCOPE OF LICENSE. The software is licensed, not sold. Microsoft reserves all
+other rights. Unless applicable law gives you more rights despite this
+limitation, you will not (and have no right to): 
+
+remove, minimize, block, or modify any notices of Microsoft or its suppliers in
+the software; 
+
+use the software in any way that is against the law or to create or propagate
+malware; or 
+
+share, publish, distribute, or lease the software (except as permitted in
+Section 2 above), or provide the software as a stand-alone offering for others
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+
+DATA. This software may interact with other Microsoft products that collect data
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+https://go.microsoft.com/fwlink/?LinkId=248681. 
+
+EXPORT RESTRICTIONS. You must comply with all domestic and international export
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+
+SUPPORT SERVICES. Microsoft is not obligated under this agreement to provide any
+support services for the software. Any support provided is “as is”, “with all
+faults”, and without warranty of any kind. 
+
+UPDATES. Microsoft may periodically update the software. You may obtain updates
+only from Microsoft or Microsoft-authorized sources. Updates may not include or
+support all existing software features, services, or peripheral devices. 
+
+TERMINATION. Without prejudice to any other rights, Microsoft may terminate this
+agreement if you fail to comply with any of its terms or conditions. In such
+event, you must destroy all copies of the software and all of its component
+parts. 
+
+ENTIRE AGREEMENT. This agreement, and any other terms Microsoft may provide for
+supplements, updates, or third-party applications, is the entire agreement for
+the software. To the extent you have entered into a separate agreement with
+Microsoft relating specifically to the software, the terms in such agreement
+shall control. 
+
+APPLICABLE LAW AND PLACE TO RESOLVE DISPUTES. If you acquired the software in
+the United States or Canada, the laws of the state or province where you live
+(or, if a business, where your principal place of business is located) govern
+the interpretation of this agreement, claims for its breach, and all other
+claims (including consumer protection, unfair competition, and tort claims),
+regardless of conflict of laws principles. If you acquired the software in any
+other country, its laws apply. If U.S. federal jurisdiction exists, you and
+Microsoft consent to exclusive jurisdiction and venue in the federal court in
+King County, Washington for all disputes heard in court. If not, you and
+Microsoft consent to exclusive jurisdiction and venue in the Superior Court of
+King County, Washington for all disputes heard in court. 
+
+CONSUMER RIGHTS; REGIONAL VARIATIONS. This agreement describes certain legal
+rights. You may have other rights, including consumer rights, under the laws of
+your state or country. Separate and apart from your relationship with Microsoft,
+you may also have rights with respect to the party from which you acquired the
+software. This agreement does not change those other rights if the laws of your
+state or country do not permit it to do so. For example, if you acquired the
+software in one of the below regions, or mandatory country law applies, then the
+following provisions apply to you: 
+
+Australia. You have statutory guarantees under the Australian Consumer Law and
+nothing in this agreement is intended to affect those rights. 
+
+Germany and Austria. 
+
+i.Warranty. The properly licensed software will perform substantially as
+described in any Microsoft materials that accompany the software. However,
+Microsoft gives no contractual guarantee in relation to the licensed software. 
+
+ii.Limitation of Liability. In case of intentional conduct, gross negligence,
+claims based on the Product Liability Act, as well as, in case of death or
+personal or physical injury, Microsoft is liable according to the statutory law.
+
+
+Subject to the foregoing clause ii., Microsoft will only be liable for slight
+negligence if Microsoft is in breach of such material contractual obligations,
+the fulfillment of which facilitate the due performance of this agreement, the
+breach of which would endanger the purpose of this agreement and the compliance
+with which a party may constantly trust in (so-called "cardinal obligations").
+In other cases of slight negligence, Microsoft will not be liable for slight
+negligence. 
+
+DISCLAIMER OF WARRANTY. THE SOFTWARE IS LICENSED “AS IS.” YOU BEAR THE RISK OF
+USING IT. MICROSOFT GIVES NO EXPRESS WARRANTIES, GUARANTEES, OR CONDITIONS. TO
+THE EXTENT PERMITTED UNDER APPLICABLE LAWS, MICROSOFT EXCLUDES ALL IMPLIED
+WARRANTIES, INCLUDING MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+NON-INFRINGEMENT. 
+
+LIMITATION ON AND EXCLUSION OF DAMAGES. IF YOU HAVE ANY BASIS FOR RECOVERING
+DAMAGES DESPITE THE PRECEDING DISCLAIMER OF WARRANTY, YOU CAN RECOVER FROM
+MICROSOFT AND ITS SUPPLIERS ONLY DIRECT DAMAGES UP TO U.S. $5.00. YOU CANNOT
+RECOVER ANY OTHER DAMAGES, INCLUDING CONSEQUENTIAL, LOST PROFITS, SPECIAL,
+INDIRECT, OR INCIDENTAL DAMAGES. 
+
+This limitation applies to (a) anything related to the software, services,
+content (including code) on third party Internet sites, or third party
+applications; and (b) claims for breach of contract, warranty, guarantee, or
+condition; strict liability, negligence, or other tort; or any other claim; in
+each case to the extent permitted by applicable law. 
+
+It also applies even if Microsoft knew or should have known about the
+possibility of the damages. The above limitation or exclusion may not apply to
+you because your state, province, or country may not allow the exclusion or
+limitation of incidental, consequential, or other damages. 
+
+ 
+
+Please note: As this software is distributed in Canada, some of the clauses in
+this agreement are provided below in French. 
+
+Remarque: Ce logiciel étant distribué au Canada, certaines des clauses dans ce
+contrat sont fournies ci-dessous en français. 
+
+EXONÉRATION DE GARANTIE. Le logiciel visé par une licence est offert « tel quel
+». Toute utilisation de ce logiciel est à votre seule risque et péril. Microsoft
+n’accorde aucune autre garantie expresse. Vous pouvez bénéficier de droits
+additionnels en vertu du droit local sur la protection des consommateurs, que ce
+contrat ne peut modifier. La ou elles sont permises par le droit locale, les
+garanties implicites de qualité marchande, d’adéquation à un usage particulier
+et d’absence de contrefaçon sont exclues. 
+
+LIMITATION DES DOMMAGES-INTÉRÊTS ET EXCLUSION DE RESPONSABILITÉ POUR LES
+DOMMAGES. Vous pouvez obtenir de Microsoft et de ses fournisseurs une
+indemnisation en cas de dommages directs uniquement à hauteur de 5,00 $ US. Vous
+ne pouvez prétendre à aucune indemnisation pour les autres dommages, y compris
+les dommages spéciaux, indirects ou accessoires et pertes de bénéfices. 
+
+Cette limitation concerne: 
+
+•tout ce qui est relié au logiciel, aux services ou au contenu (y compris le
+code) figurant sur des sites Internet tiers ou dans des programmes tiers; et 
+
+•les réclamations au titre de violation de contrat ou de garantie, ou au titre
+de responsabilité stricte, de négligence ou d’une autre faute dans la limite
+autorisée par la loi en vigueur. 
+
+Elle s’applique également, même si Microsoft connaissait ou devrait connaître
+l’éventualité d’un tel dommage. Si votre pays n’autorise pas l’exclusion ou la
+limitation de responsabilité pour les dommages indirects, accessoires ou de
+quelque nature que ce soit, il se peut que la limitation ou l’exclusion
+ci-dessus ne s’appliquera pas à votre égard. 
+
+EFFET JURIDIQUE. Le présent contrat décrit certains droits juridiques. Vous
+pourriez avoir d’autres droits prévus par les lois de votre pays. Le présent
+contrat ne modifie pas les droits que vous confèrent les lois de votre pays si
+celles-ci ne le permettent pas. 
\ No newline at end of file
diff --git a/Renesas/RSK_RX65N_2MB/lib/netx_driver/LICENSED-HARDWARE.txt b/Renesas/RSK_RX65N_2MB/lib/netx_driver/LICENSED-HARDWARE.txt
new file mode 100644
index 00000000..77dd1abf
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/netx_driver/LICENSED-HARDWARE.txt
@@ -0,0 +1,16 @@
+LICENSED HARDWARE LIST
+
+Last Updated: 2020-05-08
+
+Microsoft has entered into OEM Agreements with manufacturers of the following
+microprocessors and microcontrollers (the “hardware”) to enable those
+manufacturers to include and distribute Azure RTOS in certain hardware. If you
+have obtained and/or are developing on microprocessor(s) and/or
+microcontroller(s) (“hardware”) listed below you inherit the “Distribution and
+Production Use” rights in Section 2 of the Microsoft Software License Terms for
+Microsoft Azure RTOS. If hardware is not listed below, you do not have those
+rights.
+
+--------------------------------------------------------------------------------
+
+More coming soon. Please check back frequently for updates.
\ No newline at end of file
diff --git a/Renesas/RSK_RX65N_2MB/lib/netx_driver/src/nx_driver_rx_fit.c b/Renesas/RSK_RX65N_2MB/lib/netx_driver/src/nx_driver_rx_fit.c
new file mode 100644
index 00000000..07f04e8b
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/netx_driver/src/nx_driver_rx_fit.c
@@ -0,0 +1,567 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** NetX Component                                                        */
+/**                                                                       */
+/**   Ethernet device driver for the Renesas RX FIT driver.    */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+/* Indicate that driver source is being compiled.  */
+
+#define NX_DRIVER_SOURCE
+
+#include <stdint.h>
+
+#include <tx_api.h>
+#include <nx_api.h>
+
+#include <r_ether_rx_if.h>
+
+#include "nx_driver_rx_fit.h"
+
+#define NX_DRIVER_ETHERNET_IP (0x0800U)
+#define NX_DRIVER_ETHERNET_IPV6 (0x86ddU)
+#define NX_DRIVER_ETHERNET_ARP (0x0806U)
+#define NX_DRIVER_ETHERNET_RARP (0x8035U)
+
+#define NX_DRIVER_ETHERNET_MTU (1514U)
+#define NX_DRIVER_ETHERNET_FRAME_SIZE (14U)
+#define NX_DRIVER_PHYSICAL_ADDRESS_SIZE (6U)
+
+#define NX_DRIVER_STATE_NOT_INITIALIZED (1U)
+#define NX_DRIVER_STATE_INITIALIZE_FAILED (2U)
+#define NX_DRIVER_STATE_INITIALIZED (3U)
+#define NX_DRIVER_STATE_LINK_ENABLED (4U)
+
+
+#define NX_DRIVER_DEFERRED_PACKET_RECEIVED (1U)
+#define NX_DRIVER_DEFERRED_PACKET_TRANSMITTED (2U)
+#define NX_DRIVER_DEFERRED_LINK_STATE_CHANGE (4U)
+
+
+/* Internal driver data. */
+typedef struct netx_driver_rx_fit_data {
+    NX_INTERFACE *netx_interface_ptr;
+    NX_IP *netx_ip_ptr;
+    NX_PACKET_POOL *netx_packet_pool_ptr;
+    ULONG driver_state;
+    ULONG deferred_events_flags;
+    UINT rx_ether_chan;
+} netx_driver_rx_fit_data_t;
+
+static VOID _netx_driver_interface_attach(NX_IP_DRIVER *driver_req_ptr);
+static VOID _netx_driver_initialize(NX_IP_DRIVER *driver_req_ptr);
+static VOID _netx_driver_enable(NX_IP_DRIVER *driver_req_ptr);
+static VOID _netx_driver_disable(NX_IP_DRIVER *driver_req_ptr);
+static VOID _netx_driver_deferred_processing(NX_IP_DRIVER *driver_req_ptr);
+static VOID _netx_driver_packet_send(NX_IP_DRIVER *driver_req_ptr);
+static VOID _netx_driver_get_status(NX_IP_DRIVER *driver_req_ptr);
+
+static VOID _rx_ether_cb(VOID *p_arg);
+static VOID _rx_ether_int_cb(VOID *p_arg);
+
+// TODO - Support two instances.
+static netx_driver_rx_fit_data_t netx_driver_rx_fit_data[1];
+
+/* Driver instance MAC address. MAC address should be set prior to
+   initializing the driver by calling 'nx_ip_interface_physical_address_set()'
+   otherwise the default address will be used.*/
+static UCHAR _netx_driver_rx_fit_mac_address[] = {0x0,0x02,0x00,0x00,0x02,0x00};
+
+
+VOID nx_driver_rx_fit(NX_IP_DRIVER *driver_req_ptr)
+{
+
+    /* Default to successful return.  */
+    driver_req_ptr->nx_ip_driver_status = NX_SUCCESS;
+
+    /* Process according to the driver request type in the IP control
+           block.  */
+    switch(driver_req_ptr->nx_ip_driver_command)
+    {
+    case NX_LINK_INTERFACE_ATTACH:
+        _netx_driver_interface_attach(driver_req_ptr);
+        break;
+
+    case NX_LINK_INITIALIZE:
+        _netx_driver_initialize(driver_req_ptr);
+        break;
+
+    case NX_LINK_ENABLE:
+        _netx_driver_enable(driver_req_ptr);
+        break;
+
+    case NX_LINK_DISABLE:
+        _netx_driver_disable(driver_req_ptr);
+        break;
+
+    case NX_LINK_DEFERRED_PROCESSING:
+        _netx_driver_deferred_processing(driver_req_ptr);
+        break;
+
+    case NX_LINK_ARP_SEND:
+    case NX_LINK_ARP_RESPONSE_SEND:
+    case NX_LINK_PACKET_BROADCAST:
+    case NX_LINK_RARP_SEND:
+    case NX_LINK_PACKET_SEND:
+        _netx_driver_packet_send(driver_req_ptr);
+        break;
+
+    case NX_LINK_GET_STATUS:
+        _netx_driver_get_status(driver_req_ptr);
+        break;
+
+    case NX_LINK_MULTICAST_JOIN:
+    case NX_LINK_MULTICAST_LEAVE:
+        /* Nothing to do here as multicast hash filtering is not supported. */
+        break;
+
+    default:
+        driver_req_ptr->nx_ip_driver_status = NX_UNHANDLED_COMMAND;
+        break;
+    }
+
+}
+
+
+static VOID _netx_driver_interface_attach(NX_IP_DRIVER *driver_req_ptr)
+{
+    // TODO - handle multiple instances.
+
+    /* Save the NETX interface instance associated with this driver instance. */
+    netx_driver_rx_fit_data[0].netx_interface_ptr = driver_req_ptr->nx_ip_driver_interface;
+    netx_driver_rx_fit_data[0].rx_ether_chan = 0u;
+
+    driver_req_ptr->nx_ip_driver_interface->nx_interface_additional_link_info = (void *)0u;
+
+    /* Return success. */
+    driver_req_ptr->nx_ip_driver_status = NX_SUCCESS;
+}
+
+
+static VOID _netx_driver_initialize(NX_IP_DRIVER *driver_req_ptr)
+{
+    NX_IP *ip_ptr;
+    NX_INTERFACE *interface_ptr;
+    UINT chan;
+
+    /* Fetch the NETX IP instance and NETX interface. */
+    ip_ptr = driver_req_ptr->nx_ip_driver_ptr;
+
+    interface_ptr = driver_req_ptr->nx_ip_driver_interface;
+
+    chan = (UINT)interface_ptr->nx_interface_additional_link_info;
+
+    /* Save the packet pool pointer. */
+    netx_driver_rx_fit_data[chan].netx_packet_pool_ptr = ip_ptr->nx_ip_default_packet_pool;
+
+    /* Save the IP instance pointer. */
+    netx_driver_rx_fit_data[chan].netx_ip_ptr = ip_ptr;
+
+    /* Clear deferred event flags. */
+    netx_driver_rx_fit_data[chan].deferred_events_flags = 0u;
+
+    /* Save the MAC address. */
+    interface_ptr->nx_interface_physical_address_msw =
+            (ULONG)((_netx_driver_rx_fit_mac_address[0] << 8) | (_netx_driver_rx_fit_mac_address[1]));
+    interface_ptr->nx_interface_physical_address_lsw =
+            (ULONG)((_netx_driver_rx_fit_mac_address[2] << 24) | (_netx_driver_rx_fit_mac_address[3] << 16) |
+                    (_netx_driver_rx_fit_mac_address[4] << 8) | (_netx_driver_rx_fit_mac_address[5]));
+
+    /* Save the MTU size. */
+    interface_ptr->nx_interface_ip_mtu_size = NX_DRIVER_ETHERNET_MTU;
+
+    /* Indicate to the IP software that IP to physical mapping
+       is required.  */
+    interface_ptr -> nx_interface_address_mapping_needed =  NX_TRUE;
+
+    /* Set initial state to not initialized. */
+    netx_driver_rx_fit_data[chan].driver_state = NX_DRIVER_STATE_INITIALIZED;
+}
+
+
+static VOID _netx_driver_enable(NX_IP_DRIVER *driver_req_ptr)
+{
+    ether_return_t rx_ether_ret;
+    UINT chan;
+    ether_param_t eth_param = {0};
+
+    chan = (UINT)driver_req_ptr->nx_ip_driver_interface->nx_interface_additional_link_info;
+
+    /* Verify that initialization was done. */
+    if(netx_driver_rx_fit_data[chan].driver_state < NX_DRIVER_STATE_INITIALIZED)
+    {
+        driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+        return;
+    }
+
+    /* Verify that it's not already enabled. */
+    if(netx_driver_rx_fit_data[chan].driver_state >= NX_DRIVER_STATE_LINK_ENABLED)
+    {
+        driver_req_ptr->nx_ip_driver_status = NX_ALREADY_ENABLED;
+        return;
+    }
+
+    eth_param.channel = chan;
+    eth_param.ether_callback.pcb_func = _rx_ether_cb;
+    eth_param.ether_int_hnd.pcb_int_hnd = _rx_ether_int_cb;
+
+    rx_ether_ret = R_ETHER_Control(CONTROL_SET_CALLBACK, eth_param);
+    if(rx_ether_ret != ETHER_SUCCESS) {
+        driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+        return;
+    }
+
+    eth_param.channel = chan;
+    eth_param.ether_callback.pcb_func = _rx_ether_cb;
+    eth_param.ether_int_hnd.pcb_int_hnd = _rx_ether_int_cb;
+
+    rx_ether_ret = R_ETHER_Control(CONTROL_SET_INT_HANDLER, eth_param);
+    if(rx_ether_ret != ETHER_SUCCESS) {
+        driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+        return;
+    }
+
+    rx_ether_ret = R_ETHER_Open_ZC2(chan, _netx_driver_rx_fit_mac_address, ETHER_FLAG_OFF);
+    if(rx_ether_ret != ETHER_SUCCESS) {
+        driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+        return;
+    }
+
+    /* Set state to driver enabled. */
+    netx_driver_rx_fit_data[chan].driver_state = NX_DRIVER_STATE_LINK_ENABLED;
+
+    netx_driver_rx_fit_data[chan].netx_interface_ptr->nx_interface_link_up = NX_TRUE;
+
+    driver_req_ptr->nx_ip_driver_status = NX_SUCCESS;
+}
+
+
+static VOID _netx_driver_disable(NX_IP_DRIVER *driver_req_ptr)
+{
+    ether_return_t rx_ether_ret;
+    UINT chan;
+
+    chan = (UINT)driver_req_ptr->nx_ip_driver_interface->nx_interface_additional_link_info;
+
+    /* Verify that initialization was done. */
+    if(netx_driver_rx_fit_data[chan].driver_state < NX_DRIVER_STATE_INITIALIZED)
+    {
+        driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+        return;
+    }
+
+    /* Close the Ethernet channel. */
+    rx_ether_ret = R_ETHER_Close_ZC2(chan);
+    if(rx_ether_ret != ETHER_SUCCESS) {
+        driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+        return;
+    }
+
+    netx_driver_rx_fit_data[chan].driver_state = 0u;
+
+    driver_req_ptr->nx_ip_driver_status = NX_SUCCESS;
+}
+
+
+static VOID _netx_driver_deferred_processing(NX_IP_DRIVER *driver_req_ptr)
+{
+    UINT chan;
+    ULONG flags;
+    UINT res;
+    NX_PACKET *packet_ptr;
+    void *p_buf;
+    int32_t read_res;
+    USHORT packet_type;
+    NX_IP *ip_ptr;
+    uint32_t iter_cnt;
+    TX_INTERRUPT_SAVE_AREA;
+
+
+    TX_DISABLE;
+
+    chan = (UINT)driver_req_ptr->nx_ip_driver_interface->nx_interface_additional_link_info;
+    flags = netx_driver_rx_fit_data[chan].deferred_events_flags;
+    netx_driver_rx_fit_data[chan].deferred_events_flags = 0u;
+
+    /* Fetch the NETX IP instance and NETX interface. */
+    ip_ptr = driver_req_ptr->nx_ip_driver_ptr;
+
+    TX_RESTORE;
+
+    if((flags & NX_DRIVER_DEFERRED_LINK_STATE_CHANGE) != 0u) {
+        /* Link state change detected, process... */
+        R_ETHER_LinkProcess(chan);
+    }
+
+    if((flags & NX_DRIVER_DEFERRED_PACKET_RECEIVED) != 0u) {
+        /* Packet received. */
+
+
+        /* Iterate over received packets with a safety maximum count just in case. */
+        for(iter_cnt = 0u; iter_cnt < (ETHER_CFG_EMAC_RX_DESCRIPTORS * 2u); iter_cnt++) {
+
+            /* Get the received frame from the Ethernet driver. */
+            read_res = R_ETHER_Read_ZC2(chan, &p_buf);
+            if(read_res <= 0) {
+                /* Unexpected error, return. */
+                driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+
+                return;
+            }
+
+            /* Get a new packet buffer. */
+            res = nx_packet_allocate(netx_driver_rx_fit_data[chan].netx_packet_pool_ptr, &packet_ptr, NX_RECEIVE_PACKET, NX_NO_WAIT);
+            if(res != NX_SUCCESS) {
+                if(res == NX_NO_PACKET) {
+                    /* No packet buffer available. Discard received data and exit. */
+                    (void)R_ETHER_Read_ZC2_BufRelease(chan); /* Error ignored, already returning from one. */
+                    driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+
+                    return;
+                }
+            }
+
+            /* Copy packet data. */
+            packet_ptr->nx_packet_append_ptr += 2u;
+            packet_ptr->nx_packet_prepend_ptr += 2u;
+            res = nx_packet_data_append(packet_ptr, p_buf, read_res, netx_driver_rx_fit_data[chan].netx_packet_pool_ptr, TX_NO_WAIT);
+            if(res != NX_SUCCESS) {
+                /* No packet buffer available. Discard received data and exit. */
+                (void)R_ETHER_Read_ZC2_BufRelease(chan); /* Error ignored, already returning from one. */
+                driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+
+                return;
+            }
+
+            /* Release the buffer. */
+            read_res = R_ETHER_Read_ZC2_BufRelease(chan);
+            if(read_res != ETHER_SUCCESS) {
+                driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+
+                return;
+            }
+
+            /* Prepare the packet for NETX. */
+            packet_ptr->nx_packet_ip_interface = netx_driver_rx_fit_data[chan].netx_interface_ptr;
+
+            /* Pickup the packet header to determine where the packet needs to be sent. */
+            packet_type = (USHORT)(((UINT) (*(packet_ptr->nx_packet_prepend_ptr + 12))) << 8) |
+                ((UINT) (*(packet_ptr->nx_packet_prepend_ptr + 13)));
+
+            /* Route the incoming packet according to its Ethernet type. */
+            if(packet_type == NX_DRIVER_ETHERNET_IP || packet_type == NX_DRIVER_ETHERNET_IPV6)
+            {
+                /* Remove the Ethernet header. */
+                packet_ptr->nx_packet_prepend_ptr = packet_ptr->nx_packet_prepend_ptr + NX_DRIVER_ETHERNET_FRAME_SIZE;
+
+                packet_ptr->nx_packet_length = packet_ptr->nx_packet_length - NX_DRIVER_ETHERNET_FRAME_SIZE;
+
+                /* Route to the ip receive function. */
+                _nx_ip_packet_deferred_receive(ip_ptr, packet_ptr);
+            }
+            else if(packet_type == NX_DRIVER_ETHERNET_ARP)
+            {
+
+                /* Clean off the Ethernet header. */
+                packet_ptr->nx_packet_prepend_ptr = packet_ptr->nx_packet_prepend_ptr + NX_DRIVER_ETHERNET_FRAME_SIZE;
+
+                /* Adjust the packet length. */
+                packet_ptr->nx_packet_length = packet_ptr->nx_packet_length - NX_DRIVER_ETHERNET_FRAME_SIZE;
+
+                /* Route to the ARP receive function. */
+                _nx_arp_packet_deferred_receive(ip_ptr, packet_ptr);
+            }
+            else if(packet_type == NX_DRIVER_ETHERNET_RARP)
+            {
+
+                /* Clean off the Ethernet header. */
+                packet_ptr->nx_packet_prepend_ptr = packet_ptr->nx_packet_prepend_ptr + NX_DRIVER_ETHERNET_FRAME_SIZE;
+
+                /* Adjust the packet length. */
+                packet_ptr->nx_packet_length = packet_ptr->nx_packet_length - NX_DRIVER_ETHERNET_FRAME_SIZE;
+
+                /* Route to the RARP receive function. */
+                _nx_rarp_packet_deferred_receive(ip_ptr, packet_ptr);
+            }
+            else
+            {
+                /* Invalid Ethernet header, just release the packet. */
+                nx_packet_release(packet_ptr);
+            }
+
+        }
+
+    }
+
+}
+
+
+static VOID _netx_driver_packet_send(NX_IP_DRIVER *driver_req_ptr)
+{
+    NX_PACKET *packet_ptr;
+    ULONG *frame_ptr;
+    UINT chan;
+    void *p_buf;
+    uint16_t buf_size;
+    UINT len;
+    ether_return_t ether_ret;
+
+    chan = (UINT)driver_req_ptr->nx_ip_driver_interface->nx_interface_additional_link_info;
+
+    /* Verify that the link is up. */
+    if(netx_driver_rx_fit_data[chan].driver_state < NX_DRIVER_STATE_LINK_ENABLED)
+    {
+        driver_req_ptr->nx_ip_driver_status = NX_DRIVER_ERROR;
+
+        nx_packet_transmit_release(driver_req_ptr->nx_ip_driver_packet);
+
+        return;
+    }
+
+    /* Place the Ethernet frame at the front of the packet. */
+    packet_ptr = driver_req_ptr->nx_ip_driver_packet;
+
+    /* Adjust the prepend pointer and packet length. */
+    packet_ptr->nx_packet_prepend_ptr = packet_ptr->nx_packet_prepend_ptr - NX_DRIVER_ETHERNET_FRAME_SIZE;
+
+    packet_ptr->nx_packet_length = packet_ptr->nx_packet_length + NX_DRIVER_ETHERNET_FRAME_SIZE;
+
+    /* Setup the Ethernet frame pointer to build the Ethernet frame. */
+    frame_ptr = (ULONG *) (packet_ptr->nx_packet_prepend_ptr - 2);
+
+    /* Write the hardware addresses in the Ethernet header. */
+    *frame_ptr = driver_req_ptr->nx_ip_driver_physical_address_msw;
+    *(frame_ptr + 1) = driver_req_ptr->nx_ip_driver_physical_address_lsw;
+
+    *(frame_ptr + 2) = (driver_req_ptr->nx_ip_driver_interface->nx_interface_physical_address_msw << 16) |
+        (driver_req_ptr->nx_ip_driver_interface->nx_interface_physical_address_lsw >> 16);
+    *(frame_ptr + 3) = (driver_req_ptr->nx_ip_driver_interface->nx_interface_physical_address_lsw << 16);
+
+    /* Write the frame type field in the Ethernet harder. */
+    if((driver_req_ptr->nx_ip_driver_command == NX_LINK_ARP_SEND) || (driver_req_ptr->nx_ip_driver_command == NX_LINK_ARP_RESPONSE_SEND))
+    {
+        *(frame_ptr + 3) |= NX_DRIVER_ETHERNET_ARP;
+    }
+    else if(driver_req_ptr->nx_ip_driver_command == NX_LINK_RARP_SEND)
+    {
+        *(frame_ptr + 3) |= NX_DRIVER_ETHERNET_RARP;
+    }
+#ifdef FEATURE_NX_IPV6
+    else if(packet_ptr->nx_packet_ip_version == NX_IP_VERSION_V6)
+    {
+        *(frame_ptr + 3) |= NX_DRIVER_ETHERNET_IPV6;
+    }
+#endif
+    else
+    {
+        *(frame_ptr + 3) |= NX_DRIVER_ETHERNET_IP;
+    }
+
+    /* Endian swapping if NX_LITTLE_ENDIAN is defined. */
+    NX_CHANGE_ULONG_ENDIAN(*(frame_ptr));
+    NX_CHANGE_ULONG_ENDIAN(*(frame_ptr + 1));
+    NX_CHANGE_ULONG_ENDIAN(*(frame_ptr + 2));
+    NX_CHANGE_ULONG_ENDIAN(*(frame_ptr + 3));
+
+    /* Determine if the packet exceeds the driver's MTU. */
+    if(packet_ptr->nx_packet_length > NX_DRIVER_ETHERNET_MTU)
+    {
+        /* Remove the Ethernet header. */
+        packet_ptr->nx_packet_prepend_ptr += NX_DRIVER_ETHERNET_FRAME_SIZE;
+        packet_ptr->nx_packet_length -= NX_DRIVER_ETHERNET_FRAME_SIZE;
+
+        /* Indicate an unsuccessful packet send. */
+        driver_req_ptr->nx_ip_driver_status =  NX_DRIVER_ERROR;
+
+        nx_packet_transmit_release(packet_ptr);
+
+        return;
+    }
+
+    /* Fetch a hardware buffer. */
+    ether_ret = R_ETHER_Write_ZC2_GetBuf(chan, &p_buf, &buf_size);
+    if(ether_ret != ETHER_SUCCESS) {
+        /* Indicate an unsuccessful packet send. */
+        driver_req_ptr->nx_ip_driver_status =  NX_DRIVER_ERROR;
+
+        nx_packet_transmit_release(packet_ptr);
+    }
+
+    len = packet_ptr->nx_packet_length;
+
+    /* Copy data. */
+    memcpy(p_buf, packet_ptr->nx_packet_prepend_ptr, len);
+
+    if(len < 60u) {
+        len = 60u;
+    }
+
+    ether_ret = R_ETHER_Write_ZC2_SetBuf(chan, len);
+    if(ether_ret != ETHER_SUCCESS) {
+        /* Indicate an unsuccessful packet send. */
+        driver_req_ptr->nx_ip_driver_status =  NX_DRIVER_ERROR;
+
+        nx_packet_transmit_release(packet_ptr);
+    }
+
+    /* Release packet. */
+    nx_packet_transmit_release(packet_ptr);
+}
+
+
+static VOID _netx_driver_get_status(NX_IP_DRIVER *driver_req_ptr)
+{
+
+    *(driver_req_ptr->nx_ip_driver_return_ptr) = driver_req_ptr->nx_ip_driver_interface->nx_interface_link_up;
+
+    return;
+}
+
+
+static VOID _rx_ether_cb(VOID *p_arg)
+{
+}
+
+
+static VOID _rx_ether_int_cb(VOID *p_arg)
+{
+    ether_cb_arg_t *p_cb_arg;
+    UINT signal;
+    UINT chan;
+
+    p_cb_arg = (ether_cb_arg_t *)p_arg;
+
+    chan = p_cb_arg->channel;
+
+    signal = 0u;
+
+    if((p_cb_arg->status_ecsr & (1u << 2)) != 0u) {
+        /* Link change detected, signal Ethernet processing thread. */
+        netx_driver_rx_fit_data[chan].deferred_events_flags |= NX_DRIVER_DEFERRED_LINK_STATE_CHANGE;
+        signal = 1u;
+    }
+
+    if((p_cb_arg->status_eesr & (1u << 18)) != 0u) {
+        netx_driver_rx_fit_data[chan].deferred_events_flags |= NX_DRIVER_DEFERRED_PACKET_RECEIVED;
+        signal = 1u;
+    }
+
+    if(signal != 0u) {
+        _nx_ip_driver_deferred_processing(netx_driver_rx_fit_data[chan].netx_ip_ptr);
+    }
+}
diff --git a/Renesas/RSK_RX65N_2MB/lib/netx_driver/src/nx_driver_rx_fit.h b/Renesas/RSK_RX65N_2MB/lib/netx_driver/src/nx_driver_rx_fit.h
new file mode 100644
index 00000000..d5e28b4a
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/netx_driver/src/nx_driver_rx_fit.h
@@ -0,0 +1,56 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** NetX Component                                                        */
+/**                                                                       */
+/**   Ethernet device driver for the Renesas RX FIT driver.    */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#ifndef NX_DRIVER_RX_FIT_H
+#define NX_DRIVER_RX_FIT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Include ThreadX header file, if not already.  */
+
+#ifndef TX_API_H
+#include "tx_api.h"
+#endif
+
+
+/* Include NetX header file, if not already.  */
+
+#ifndef NX_API_H
+#include "nx_api.h"
+#endif
+
+
+/* Define custom error code for unrecoverable driver errors. */
+#define NX_DRIVER_ERROR (99U)
+#define NX_DRIVER_BUSY (100U)
+
+/* Define global driver entry function. */
+VOID nx_driver_rx_fit(NX_IP_DRIVER *driver_req_ptr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // #ifndef NX_DRIVER_RX_FIT_H
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/netxduo/nx_user.h b/Renesas/RSK_RX65N_2MB/lib/netxduo/nx_user.h
new file mode 100644
index 00000000..588910ce
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/netxduo/nx_user.h
@@ -0,0 +1,764 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** NetX Component                                                        */
+/**                                                                       */
+/**   User Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    nx_user.h                                           PORTABLE C      */
+/*                                                           6.1          */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Yuxin Zhou, Microsoft Corporation                                   */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains user defines for configuring NetX in specific    */
+/*    ways. This file will have an effect only if the application and     */
+/*    NetX library are built with NX_INCLUDE_USER_DEFINE_FILE defined.    */
+/*    Note that all the defines in this file may also be made on the      */
+/*    command line when building NetX library and application objects.    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  05-19-2020     Yuxin Zhou               Initial Version 6.0           */
+/*  09-30-2020     Yuxin Zhou               Modified comment(s),          */
+/*                                            resulting in version 6.1    */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef NX_USER_H
+#define NX_USER_H
+
+#define NX_SECURE_ENABLE
+#define NX_ENABLE_EXTENDED_NOTIFY_SUPPORT
+#define NX_ENABLE_IP_PACKET_FILTER
+
+#define NX_SNTP_CLIENT_MIN_SERVER_STRATUM 3
+
+#define NXD_MQTT_CLOUD_ENABLE
+
+/* Define various build options for the NetX Duo port.  The application should either make changes
+   here by commenting or un-commenting the conditional compilation defined OR supply the defines
+   though the compiler's equivalent of the -D option.  */
+
+
+
+/* Override various options with default values already assigned in nx_api.h or nx_port.h. Please
+   also refer to nx_port.h for descriptions on each of these options.  */
+
+
+/* Configuration options for Interface */
+
+/* NX_MAX_PHYSICAL_INTERFACES defines the number physical network interfaces
+   present to NetX Duo IP layer.  Physical interface does not include
+   loopback interface. By default there is at least one physical interface
+   in the system. */
+/*
+#define NX_MAX_PHYSICAL_INTERFACES    1
+*/
+
+/* Defined, this option disables NetX Duo support on the 127.0.0.1 loopback interface.
+   127.0.0.1 loopback interface is enabled by default.  Uncomment out the follow code to disable
+   the loopback interface. */
+/*
+#define NX_DISABLE_LOOPBACK_INTERFACE
+*/
+
+/* If defined, the link driver is able to specify extra capability, such as checksum offloading features. */
+/*
+#define NX_ENABLE_INTERFACE_CAPABILITY
+*/
+
+
+/* Configuration options for IP */
+
+/* This defines specifies the number of ThreadX timer ticks in one second. The default value is based
+   on ThreadX timer interrupt.  */
+/*
+#ifdef TX_TIMER_TICKS_PER_SECOND
+#define NX_IP_PERIODIC_RATE         TX_TIMER_TICKS_PER_SECOND
+#else
+#define NX_IP_PERIODIC_RATE         100
+#endif
+*/
+
+/* Defined, NX_ENABLE_IP_RAW_PACKET_FILTER allows an application to install a filter
+   for incoming raw packets. This feature is disabled by default. */
+/*
+#define NX_ENABLE_IP_RAW_PACKET_FILTER
+*/
+
+/* This define specifies the maximum number of RAW packets can be queued for receive.  The default
+   value is 20.  */
+/*
+#define NX_IP_RAW_MAX_QUEUE_DEPTH 20
+*/
+
+/* Defined, this option enables IP static routing feature.  By default IP static routing
+   feature is not compiled in. */
+/*
+#define NX_ENABLE_IP_STATIC_ROUTING
+*/
+
+/* This define specifies the size of IP routing table. The default value is 8. */
+/*
+#define NX_IP_ROUTING_TABLE_SIZE 8
+*/
+
+/* This define specifies the maximum number of multicast groups that can be joined.
+   The default value is 7.  */
+/*
+#define NX_MAX_MULTICAST_GROUPS     7
+*/
+
+
+/* Configuration options for IPv6 */
+
+/* Disable IPv6 processing in NetX Duo.  */
+/*
+#define NX_DISABLE_IPV6
+*/
+
+/* Define the number of entries in IPv6 address pool. */
+/*
+#ifdef NX_MAX_PHYSICAL_INTERFACES
+#define NX_MAX_IPV6_ADDRESSES (NX_MAX_PHYSICAL_INTERFACES * 3)
+#endif
+*/
+
+/* Do not process IPv6 ICMP Redirect Messages. */
+/*
+#define NX_DISABLE_ICMPV6_REDIRECT_PROCESS
+*/
+
+/* Do not process IPv6 Router Advertisement Messages. */
+/*
+#define NX_DISABLE_ICMPV6_ROUTER_ADVERTISEMENT_PROCESS
+*/
+
+/* Do not send IPv6 Router Solicitation Messages. */
+/*
+#define NX_DISABLE_ICMPV6_ROUTER_SOLICITATION
+*/
+
+/* Define the max number of router solicitations a host sends until a router response
+   is received.  If no response is received, the host concludes no router is present. */
+/*
+#define NX_ICMPV6_MAX_RTR_SOLICITATIONS         3
+*/
+
+/* Define the interval between which the host sends router solicitations in seconds. */
+/*
+#define NX_ICMPV6_RTR_SOLICITATION_INTERVAL     4
+*/
+
+/* Define the maximum delay for the initial router solicitation in seconds. */
+/*
+#define NX_ICMPV6_RTR_SOLICITATION_DELAY        1
+*/
+
+/* Do not send ICMPv4 Error Messages. */
+/*
+#define NX_DISABLE_ICMPV4_ERROR_MESSAGE
+*/
+
+/* Do not send ICMPv6 Error Messages. */
+/*
+#define NX_DISABLE_ICMPV6_ERROR_MESSAGE
+*/
+
+/* Disable the Duplicate Address Detection (DAD) protocol when configuring the host IP address. */
+/*
+#define NX_DISABLE_IPV6_DAD
+*/
+
+/* If defined, application is able to control whether or not to perform IPv6 stateless
+   address autoconfiguration with nxd_ipv6_stateless_address_autoconfig_enable() or
+   nxd_ipv6_stateless_address_autoconfig_disable() service.  If defined, the system starts
+   with IPv6 stateless address autoconfiguration enabled.  This feature is disabled by default. */
+/*
+#define NX_IPV6_STATELESS_AUTOCONFIG_CONTROL
+*/
+
+/* If enabled, application is able to install a callback function to get notified
+   when an interface IPv6 address is changed. By default this feature is disabled. */
+/*
+#define NX_ENABLE_IPV6_ADDRESS_CHANGE_NOTIFY
+*/
+
+/* Defined, this option prevents NetX Duo from removing stale (old) cache table entries
+   whose timeout has not expired so are otherwise still valid) to make room for new entries
+   when the table is full.  Static and router entries are not purged.  */
+/*
+#define NX_DISABLE_IPV6_PURGE_UNUSED_CACHE_ENTRIES
+*/
+
+/* This define enables simple IPv6 multicast group join/leave function.  By default
+   the IPv6 multicast join/leave function is not enabled. */
+/*
+#define NX_ENABLE_IPV6_MULTICAST
+*/
+
+/* Defined, Minimum Path MTU Discovery feature is enabled.  */
+/*
+#define NX_ENABLE_IPV6_PATH_MTU_DISCOVERY
+*/
+
+/* Define wait interval in seconds to reset the path MTU for a destination
+   table entry after decreasing it in response to a packet too big error message.
+   RFC 1981 Section 5.4 states the minimum time to wait is
+   5 minutes and recommends 10 minutes.
+*/
+/*
+#define NX_PATH_MTU_INCREASE_WAIT_INTERVAL               600
+*/
+
+
+/* Configuration options for Neighbor Discovery.  */
+/* Define values used for Neighbor Discovery protocol.
+   The default values are suggested by RFC2461, chapter 10. */
+
+/* Define the maximum number of multicast Neighbor Solicitation packets
+   NetX Duo sends for a packet destination needing physical mapping
+   to the IP address. */
+/*
+#define NX_MAX_MULTICAST_SOLICIT        3
+*/
+
+/* Define the maximum number of unicast Neighbor Solicitation packets
+   NetX Duo sends for a cache entry whose reachable time has expired
+   and gone "stale". */
+/*
+#define NX_MAX_UNICAST_SOLICIT          3
+*/
+
+/* Define the length of time, in seconds, that a Neighbor Cache table entry
+   remains in the reachable state before it becomes state. */
+/*
+#define NX_REACHABLE_TIME               30
+*/
+
+/* Define the length of time, in milliseconds, between retransmitting
+   Neighbor Solicitation (NS) packets. */
+/*
+#define NX_RETRANS_TIMER                1000
+*/
+
+/* Define the length of time, in seconds, for a Neighbor Cache entry
+   to remain in the Delay state.  This is the Delay first probe timer. */
+/*
+#define NX_DELAY_FIRST_PROBE_TIME       5
+*/
+
+/* This defines specifies the maximum number of packets that can be queued while waiting for a
+   Neighbor Discovery to resolve an IPv6 address. The default value is 4.  */
+/*
+#define NX_ND_MAX_QUEUE_DEPTH           4
+*/
+
+/* Define the maximum ICMPv6 Duplicate Address Detect Transmit .  */
+/*
+#define NX_IPV6_DAD_TRANSMITS           3
+*/
+
+/* Define the number of neighbor cache entries. */
+/*
+#define NX_IPV6_NEIGHBOR_CACHE_SIZE     16
+*/
+
+/* Define the size of the IPv6 destination table. */
+/*
+#define NX_IPV6_DESTINATION_TABLE_SIZE  8
+*/
+
+/* Define the size of the IPv6 prefix table. */
+/*
+#define NX_IPV6_PREFIX_LIST_TABLE_SIZE  8
+*/
+
+
+/* Configuration options for IPSEC */
+
+/* This define enables IPSEC in NetX Duo.  */
+/*
+#define NX_IPSEC_ENABLE
+*/
+
+
+/* Configuration options for NAT */
+
+/* This define enables NAT process in NetX Duo.  */
+/*
+#define NX_NAT_ENABLE
+*/
+
+
+/* Configuration options for IGMP */
+
+/* Defined, IGMP v2 support is disabled.  By default NetX Duo
+   is built with IGMPv2 enabled .  By uncommenting this option,
+   NetX Duo reverts back to IGMPv1 only. */
+/*
+#define NX_DISABLE_IGMPV2
+*/
+
+
+/* Configuration options for ARP */
+
+/* When defines, ARP reply is sent when address conflict occurs. */
+/*
+#define NX_ARP_DEFEND_BY_REPLY
+*/
+
+/* To use the ARP collision hander to check for invalid ARP messages
+   matching existing entries in the table (man in the middle attack),
+   enable this feature.  */
+/*
+#define  NX_ENABLE_ARP_MAC_CHANGE_NOTIFICATION
+*/
+
+/* This define specifies the number of seconds ARP entries remain valid. The default value of 0 disables
+   aging of ARP entries.  */
+/*
+#define NX_ARP_EXPIRATION_RATE      0
+*/
+
+/* This define specifies the number of seconds between ARP retries. The default value is 10, which represents
+   10 seconds.  */
+/*
+#define NX_ARP_UPDATE_RATE          10
+*/
+
+/* This define specifies the maximum number of ARP retries made without an ARP response. The default
+   value is 18.  */
+/*
+#define NX_ARP_MAXIMUM_RETRIES      18
+*/
+
+/* This defines specifies the maximum number of packets that can be queued while waiting for an ARP
+   response. The default value is 4.  */
+/*
+#define NX_ARP_MAX_QUEUE_DEPTH      4
+*/
+
+/* Defined, this option disables entering ARP request information in the ARP cache.  */
+/*
+#define NX_DISABLE_ARP_AUTO_ENTRY
+*/
+
+/* Define the ARP defend interval. The default value is 10 seconds.  */
+/*
+#define NX_ARP_DEFEND_INTERVAL  10
+*/
+
+
+/* Configuration options for TCP */
+
+/* This define specifies how the number of system ticks (NX_IP_PERIODIC_RATE) is divided to calculate the
+   timer rate for the TCP delayed ACK processing. The default value is 5, which represents 200ms.  */
+/*
+#define NX_TCP_ACK_TIMER_RATE       5
+*/
+
+/* This define specifies how the number of system ticks (NX_IP_PERIODIC_RATE) is divided to calculate the
+   fast TCP timer rate. The fast TCP timer is used to drive various TCP timers, including the delayed ACK
+   timer. The default value is 10, which represents 100ms.  */
+/*
+#define NX_TCP_FAST_TIMER_RATE      10
+*/
+
+/* This define specifies how the number of system ticks (NX_IP_PERIODIC_RATE) is divided to calculate the
+   timer rate for the TCP transmit retry processing. The default value is 1, which represents 1 second.  */
+/*
+#define NX_TCP_TRANSMIT_TIMER_RATE  1
+*/
+
+/* This define specifies how many seconds of inactivity before the keepalive timer activates. The default
+   value is 7200, which represents 2 hours.   */
+/*
+#define NX_TCP_KEEPALIVE_INITIAL    7200
+*/
+
+/* This define specifies how many seconds between retries of the keepalive timer assuming the other side
+   of the connection is not responding. The default value is 75, which represents 75 seconds between
+   retries.  */
+/*
+#define NX_TCP_KEEPALIVE_RETRY      75
+*/
+
+/* This define specifies the maximum packets that are out of order. The default value is 8.  */
+/*
+#define NX_TCP_MAX_OUT_OF_ORDER_PACKETS 8
+*/
+
+/* This define specifies the maximum number of TCP server listen requests. The default value is 10.  */
+/*
+#define NX_MAX_LISTEN_REQUESTS      10
+*/
+
+/* Defined, this option enables the optional TCP keepalive timer.  */
+/*
+#define NX_ENABLE_TCP_KEEPALIVE
+*/
+
+/* Defined, this option enables the optional TCP immediate ACK response processing.  */
+/*
+#define NX_TCP_IMMEDIATE_ACK
+*/
+
+/* This define specifies the number of TCP packets to receive before sending an ACK. */
+/* The default value is 2: ack every 2 packets.                                      */
+/*
+#define NX_TCP_ACK_EVERY_N_PACKETS  2
+*/
+
+/* Automatically define NX_TCP_ACK_EVERY_N_PACKETS to 1 if NX_TCP_IMMEDIATE_ACK is defined.
+   This is needed for backward compatibility. */
+#if (defined(NX_TCP_IMMEDIATE_ACK) && !defined(NX_TCP_ACK_EVERY_N_PACKETS))
+#define NX_TCP_ACK_EVERY_N_PACKETS 1
+#endif
+
+/* This define specifies how many transmit retires are allowed before the connection is deemed broken.
+   The default value is 10.  */
+/*
+#define NX_TCP_MAXIMUM_RETRIES      10
+*/
+
+/* This define specifies the maximum depth of the TCP transmit queue before TCP send requests are
+   suspended or rejected. The default value is 20, which means that a maximum of 20 packets can be in
+   the transmit queue at any given time.  */
+/*
+#define NX_TCP_MAXIMUM_TX_QUEUE     20
+*/
+
+/* This define specifies how the retransmit timeout period changes between successive retries. If this
+   value is 0, the initial retransmit timeout is the same as subsequent retransmit timeouts. If this
+   value is 1, each successive retransmit is twice as long. The default value is 0.  */
+/*
+#define NX_TCP_RETRY_SHIFT          0
+*/
+
+/* This define specifies how many keepalive retries are allowed before the connection is deemed broken.
+   The default value is 10.  */
+/*
+#define NX_TCP_KEEPALIVE_RETRIES    10
+*/
+
+/* Defined, this option enables the TCP window scaling feature. (RFC 1323). Default disabled. */
+/*
+#define NX_ENABLE_TCP_WINDOW_SCALING
+*/
+
+/* Defined, this option disables the reset processing during disconnect when the timeout value is
+   specified as NX_NO_WAIT.  */
+/*
+#define NX_DISABLE_RESET_DISCONNECT
+*/
+
+/* If defined, the incoming SYN packet (connection request) is checked for a minimum acceptable
+   MSS for the host to accept the connection. The default minimum should be based on the host
+   application packet pool payload, socket transmit queue depth and relevant application specific parameters. */
+/*
+#define NX_ENABLE_TCP_MSS_CHECK
+#define NX_TCP_MSS_MINIMUM              128
+*/
+
+/* If defined, NetX Duo has a notify callback for the transmit TCP socket queue decreased from
+   the maximum queue depth.  */
+/*
+#define NX_ENABLE_TCP_QUEUE_DEPTH_UPDATE_NOTIFY
+*/
+
+/* Defined, feature of low watermark is enabled. */
+/*
+#define NX_ENABLE_LOW_WATERMARK
+*/
+
+/* Define the maximum receive queue for TCP socket. */
+/*
+#ifdef NX_ENABLE_LOW_WATERMARK
+#define NX_TCP_MAXIMUM_RX_QUEUE    20
+#endif
+*/
+
+/* Configuration options for fragmentation */
+
+/* Defined, this option disables both IPv4 and IPv6 fragmentation and reassembly logic.  */
+/*
+#define NX_DISABLE_FRAGMENTATION
+*/
+
+/* Defined, this option process IP fragmentation immediately.  */
+/*
+#define NX_FRAGMENT_IMMEDIATE_ASSEMBLY
+*/
+
+/* This define specifies the maximum time of IP reassembly.  The default value is 60.
+   By default this option is not defined.  */
+/*
+#define NX_IP_MAX_REASSEMBLY_TIME   60
+*/
+
+/* This define specifies the maximum time of IPv4 reassembly.  The default value is 15.
+   Note that if NX_IP_MAX_REASSEMBLY_TIME is defined, this option is automatically defined as 60.
+   By default this option is not defined.  */
+/*
+#define NX_IPV4_MAX_REASSEMBLY_TIME 15
+*/
+
+/* This define specifies the maximum time of IPv6 reassembly.  The default value is 60.
+   Note that if NX_IP_MAX_REASSEMBLY_TIME is defined, this option is automatically defined as 60.
+   By default this option is not defined.  */
+/*
+#define NX_IPV6_MAX_REASSEMBLY_TIME 60
+*/
+
+/* Configuration options for checksum */
+
+/* Defiend, this option disables checksum logic on received ICMPv4 packets.
+   Note that if NX_DISABLE_ICMP_RX_CHECKSUM is defined, this option is
+   automatically defined. By default this option is not defined.*/
+/*
+#define NX_DISABLE_ICMPV4_RX_CHECKSUM
+*/
+
+/* Defiend, this option disables checksum logic on received ICMPv6 packets.
+   Note that if NX_DISABLE_ICMP_RX_CHECKSUM is defined, this option is
+   automatically defined. By default this option is not defined.*/
+/*
+#define NX_DISABLE_ICMPV6_RX_CHECKSUM
+*/
+
+/* Defined, this option disables checksum logic on received ICMPv4 or ICMPv6 packets.
+   Note that if NX_DISABLE_ICMP_RX_CHECKSUM is defined, NX_DISABLE_ICMPV4_RX_CHECKSUM
+   and NX_DISABLE_ICMPV6_RX_CHECKSUM are automatically defined. */
+/*
+#define NX_DISABLE_ICMP_RX_CHECKSUM
+*/
+
+/* Defiend, this option disables checksum logic on transmitted ICMPv4 packets.
+   Note that if NX_DISABLE_ICMP_TX_CHECKSUM is defined, this option is
+   automatically defined. By default this option is not defined.*/
+/*
+#define NX_DISABLE_ICMPV4_TX_CHECKSUM
+*/
+
+/* Defiend, this option disables checksum logic on transmitted ICMPv6 packets.
+   Note that if NX_DISABLE_ICMP_TX_CHECKSUM is defined, this option is
+   automatically defined. By default this option is not defined.*/
+/*
+#define NX_DISABLE_ICMPV6_TX_CHECKSUM
+*/
+
+/* Defined, this option disables checksum logic on transmitted ICMPv4 or ICMPv6 packets.
+   Note that if NX_DISABLE_ICMP_TX_CHECKSUM is defined, NX_DISABLE_ICMPV4_TX_CHECKSUM
+   and NX_DISABLE_ICMPV6_TX_CHECKSUM are automatically defined. */
+/*
+#define NX_DISABLE_ICMP_TX_CHECKSUM
+*/
+
+/* Defined, this option disables checksum logic on received IP packets. This is useful if the link-layer
+   has reliable checksum or CRC logic.  */
+/*
+#define NX_DISABLE_IP_RX_CHECKSUM
+*/
+
+/* Defined, this option disables checksum logic on transmitted IP packets.  */
+/*
+#define NX_DISABLE_IP_TX_CHECKSUM
+*/
+
+/* Defined, this option disables checksum logic on received TCP packets.  */
+/*
+#define NX_DISABLE_TCP_RX_CHECKSUM
+*/
+
+/* Defined, this option disables checksum logic on transmitted TCP packets.  */
+/*
+#define NX_DISABLE_TCP_TX_CHECKSUM
+*/
+
+/* Defined, this option disables checksum logic on received UDP packets.  */
+
+/*
+#define NX_DISABLE_UDP_RX_CHECKSUM
+*/
+
+/* Defined, this option disables checksum logic on transmitted UDP packets.  Note that
+   IPV6 requires the UDP checksum computed for outgoing packets.  If this option is
+   defined, the IPv6 NetX Duo host must ensure the UDP checksum is computed elsewhere
+   before the packet is transmitted. */
+/*
+#define NX_DISABLE_UDP_TX_CHECKSUM
+*/
+
+
+/* Configuration options for statistics.  */
+
+/* Defined, ARP information gathering is disabled.  */
+/*
+#define NX_DISABLE_ARP_INFO
+*/
+
+/* Defined, IP information gathering is disabled.  */
+/*
+#define NX_DISABLE_IP_INFO
+*/
+
+/* Defined, ICMP information gathering is disabled.  */
+/*
+#define NX_DISABLE_ICMP_INFO
+*/
+
+/* Defined, IGMP information gathering is disabled.  */
+/*
+#define NX_DISABLE_IGMP_INFO
+*/
+
+/* Defined, packet information gathering is disabled.  */
+/*
+#define NX_DISABLE_PACKET_INFO
+*/
+
+/* Defined, RARP information gathering is disabled.  */
+/*
+#define NX_DISABLE_RARP_INFO
+*/
+
+/* Defined, TCP information gathering is disabled.  */
+/*
+#define NX_DISABLE_TCP_INFO
+*/
+
+/* Defined, UDP information gathering is disabled.  */
+/*
+#define NX_DISABLE_UDP_INFO
+*/
+
+
+/* Configuration options for Packet Pool */
+
+/* This define specifies the size of the physical packet header. The default value is 16 (based on
+   a typical 16-byte Ethernet header).  */
+/*
+#define NX_PHYSICAL_HEADER          16
+*/
+
+/* This define specifies the size of the physical packet trailer and is typically used to reserve storage
+   for things like Ethernet CRCs, etc.  */
+/*
+#define NX_PHYSICAL_TRAILER         4
+*/
+
+/* Defined, this option disables the addition size checking on received packets.  */
+/*
+#define NX_DISABLE_RX_SIZE_CHECKING
+*/
+
+/* Defined, packet debug infromation is enabled.  */
+/*
+#define NX_ENABLE_PACKET_DEBUG_INFO
+*/
+
+/* Defined, NX_PACKET structure is padded for alignment purpose. The default is no padding. */
+/*
+#define NX_PACKET_HEADER_PAD
+#define NX_PACKET_HEADER_PAD_SIZE   1
+*/
+
+/* Defined, packet header and payload are aligned automatically by the value. The default value is sizeof(ULONG). */
+/*
+#define NX_PACKET_ALIGNMENT sizeof(ULONG)
+*/
+
+/* If defined, the packet chain feature is removed. */
+/*
+#define NX_DISABLE_PACKET_CHAIN
+*/
+
+/* Defined, the IP instance manages two packet pools. */
+/*
+#define NX_ENABLE_DUAL_PACKET_POOL
+*/
+
+/* Configuration options for Others */
+
+/* Defined, this option bypasses the basic NetX error checking. This define is typically used
+   after the application is fully debugged.  */
+/*
+#define NX_DISABLE_ERROR_CHECKING
+*/
+
+/* Defined, this option enables deferred driver packet handling. This allows the driver to place a raw
+   packet on the IP instance and have the driver's real processing routine called from the NetX internal
+   IP helper thread.  */
+/*
+#define NX_DRIVER_DEFERRED_PROCESSING
+*/
+
+/* Defined, the source address of incoming packet is checked. The default is disabled. */
+/*
+#define NX_ENABLE_SOURCE_ADDRESS_CHECK
+*/
+
+/* Defined, the extended notify support is enabled.  This feature adds additional callback/notify services
+   to NetX Duo API for notifying the application of socket events, such as TCP connection and disconnect
+   completion.  These extended notify functions are mainly used by the BSD wrapper. The default is this
+   feature is disabled.  */
+/*
+#define NX_ENABLE_EXTENDED_NOTIFY_SUPPORT
+*/
+
+/* Defined, ASSERT is disabled. The default is enabled. */
+/*
+#define NX_DISABLE_ASSERT
+*/
+
+/* Define the process when assert fails. */
+/*
+#define NX_ASSERT_FAIL while (1) tx_thread_sleep(NX_WAIT_FOREVER);
+*/
+
+/* Defined, the IPv4 feature is disabled. */
+/*
+#define NX_DISABLE_IPV4
+*/
+
+/* Defined, the destination address of ICMP packet is checked. The default is disabled.
+   An ICMP Echo Request destined to an IP broadcast or IP multicast address will be silently discarded.
+*/
+/*
+#define NX_ENABLE_ICMP_ADDRESS_CHECK
+*/
+
+/* Define the max string length. The default value is 1024.  */
+/*
+#define NX_MAX_STRING_LENGTH                                1024
+*/
+
+#endif
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/CMakeLists.txt b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/CMakeLists.txt
new file mode 100644
index 00000000..3866012d
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/CMakeLists.txt
@@ -0,0 +1,64 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+set(SOURCES
+    src/smc_gen/Config_PORT/Config_PORT.c
+    src/smc_gen/Config_PORT/Config_PORT_user.c
+    src/smc_gen/Config_SCI8/Config_SCI8.c
+    src/smc_gen/Config_SCI8/Config_SCI8_user.c
+
+    src/smc_gen/general/r_cg_hardware_setup.c
+    src/smc_gen/general/r_smc_cgc.c
+    src/smc_gen/general/r_smc_cgc_user.c
+    src/smc_gen/general/r_smc_interrupt.c
+
+    src/smc_gen/r_bsp/board/generic_rx65n/hwsetup.c
+
+    src/smc_gen/r_bsp/mcu/all/dbsct.c
+    src/smc_gen/r_bsp/mcu/all/lowlvl.c
+    src/smc_gen/r_bsp/mcu/all/lowsrc.c
+    src/smc_gen/r_bsp/mcu/all/mcu_locks.c
+    src/smc_gen/r_bsp/mcu/all/r_bsp_common.c
+    src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c
+    src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c
+    src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c
+    src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c
+    src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c
+    src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c
+    src/smc_gen/r_bsp/mcu/all/reset_program.S
+    src/smc_gen/r_bsp/mcu/all/resetprg.c
+    src/smc_gen/r_bsp/mcu/all/sbrk.c
+
+    src/smc_gen/r_bsp/mcu/rx65n/mcu_clocks.c
+    src/smc_gen/r_bsp/mcu/rx65n/mcu_init.c
+    src/smc_gen/r_bsp/mcu/rx65n/mcu_interrupts.c
+    src/smc_gen/r_bsp/mcu/rx65n/mcu_mapped_interrupts.c
+    src/smc_gen/r_bsp/mcu/rx65n/vecttbl.c
+
+    src/smc_gen/r_cmt_rx/src/r_cmt_rx.c
+
+    src/smc_gen/r_ether_rx/src/phy/phy.c
+    src/smc_gen/r_ether_rx/src/r_ether_rx.c
+    src/smc_gen/r_ether_rx/src/targets/rx65n/r_ether_setting_rx65n.c
+
+    src/smc_gen/r_pincfg/r_ether_rx_pinset.c
+    src/smc_gen/r_pincfg/Pin.c
+)
+
+set(TARGET rx_driver_package)
+
+add_library(${TARGET} OBJECT
+    ${SOURCES}
+)
+
+target_include_directories(${TARGET}
+    PUBLIC
+        src/smc_gen/general
+        src/smc_gen/Config_SCI8
+        src/smc_gen/Config_PORT
+        src/smc_gen/r_bsp
+        src/smc_gen/r_cmt_rx
+        src/smc_gen/r_config
+        src/smc_gen/r_ether_rx
+        src/smc_gen/r_pincfg
+)
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/RSK_RX65N_2MB.scfg b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/RSK_RX65N_2MB.scfg
new file mode 100644
index 00000000..639126d7
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/RSK_RX65N_2MB.scfg
@@ -0,0 +1,1639 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<smc>
+    <general version="2.0.0.0">
+        <configuration active="true" id="com.renesas.smc.toolchain.gccrx.configuration.release">
+            <property id="com.renesas.smc.service.project.buildArtefactType" values="com.renesas.smc.service.project.buildArtefactType.exe"/>
+            <toolchain id="com.renesas.smc.toolchain.gccrx.toolchain.gccrx">
+                <option id="com.renesas.smc.toolchain.option.buildArtefactType" key="com.renesas.smc.toolchain.option.buildArtefactType.exe"/>
+                <option id="com.renesas.smc.toolchain.option.rtos" key="com.renesas.smc.toolchain.option.rtos.none"/>
+            </toolchain>
+        </configuration>
+        <platform id="R5F565NEDxFC"/>
+        <option id="board" value="RSKRX65N-2MB (1.03)"/>
+    </general>
+    <tool id="Clock">
+        <option enabled="true" id="vccinput" selection="textinputitem">
+            <item enabled="true" id="textinputitem" input="3.3" value="3.300"/>
+        </option>
+        <option enabled="true" id="mainclockenable" selection="check">
+            <item enabled="true" id="check"/>
+            <item enabled="true" id="uncheck"/>
+        </option>
+        <option enabled="true" id="mainsourcebox" selection="srcR">
+            <item enabled="true" id="srcR"/>
+            <item enabled="true" id="srcEOI"/>
+        </option>
+        <option enabled="true" id="mainfrequency" selection="textinputitem">
+            <item enabled="true" id="textinputitem" input="24" value="24.000000"/>
+        </option>
+        <option enabled="true" id="mainwaittime" selection="textinputitem">
+            <item enabled="true" id="textinputitem" input="9980" value="9980.000000"/>
+        </option>
+        <option enabled="true" id="subclockenable" selection="uncheck">
+            <item enabled="true" id="check"/>
+            <item enabled="true" id="uncheck"/>
+        </option>
+        <option enabled="false" id="subfrequency" selection="textinputitem">
+            <item enabled="true" id="textinputitem" input="" value="32.768"/>
+        </option>
+        <option enabled="false" id="subdrivecap" selection="standardCL">
+            <item enabled="true" id="standardCL"/>
+            <item enabled="true" id="lowCL"/>
+        </option>
+        <option enabled="false" id="subwaittime" selection="textinputitem">
+            <item enabled="true" id="textinputitem" input="2000" value="2000.000000"/>
+        </option>
+        <option enabled="true" id="hococlockenable" selection="uncheck">
+            <item enabled="true" id="check"/>
+            <item enabled="true" id="uncheck"/>
+        </option>
+        <option enabled="false" id="hocofrequency" selection="frq16">
+            <item enabled="true" id="frq16"/>
+            <item enabled="true" id="frq18"/>
+            <item enabled="true" id="frq20"/>
+        </option>
+        <option enabled="false" id="hocooscenable" selection="uncheck">
+            <item enabled="true" id="check"/>
+            <item enabled="true" id="uncheck"/>
+        </option>
+        <option enabled="true" id="lococlockenable" selection="uncheck">
+            <item enabled="true" id="check"/>
+            <item enabled="true" id="uncheck"/>
+        </option>
+        <option enabled="false" id="locofrequency" selection="textinputitem">
+            <item enabled="true" id="textinputitem" input="" value="240"/>
+        </option>
+        <option enabled="true" id="iwdtclockenable" selection="uncheck">
+            <item enabled="true" id="check"/>
+            <item enabled="true" id="uncheck"/>
+        </option>
+        <option enabled="false" id="iwdtfrequency" selection="textinputitem">
+            <item enabled="true" id="textinputitem" input="" value="120"/>
+        </option>
+        <option enabled="true" id="pllswitcher" selection="pllmain">
+            <item enabled="true" id="pllmain" input="" value="24.0"/>
+            <item enabled="false" id="pllhoco" input="" value="16"/>
+        </option>
+        <option enabled="true" id="plldivider" selection="div1-1">
+            <item enabled="true" id="div1-1"/>
+            <item enabled="true" id="div1-2"/>
+            <item enabled="true" id="div1-3"/>
+        </option>
+        <option enabled="true" id="pllmul" selection="mul10-1">
+            <item enabled="true" id="mul10-1"/>
+            <item enabled="false" id="mul10_5-1"/>
+            <item enabled="false" id="mul11-1"/>
+            <item enabled="false" id="mul11_5-1"/>
+            <item enabled="false" id="mul12-1"/>
+            <item enabled="false" id="mul12_5-1"/>
+            <item enabled="false" id="mul13-1"/>
+            <item enabled="false" id="mul13_5-1"/>
+            <item enabled="false" id="mul14-1"/>
+            <item enabled="false" id="mul14_5-1"/>
+            <item enabled="false" id="mul15-1"/>
+            <item enabled="false" id="mul15_5-1"/>
+            <item enabled="false" id="mul16-1"/>
+            <item enabled="false" id="mul16_5-1"/>
+            <item enabled="false" id="mul17-1"/>
+            <item enabled="false" id="mul17_5-1"/>
+            <item enabled="false" id="mul18-1"/>
+            <item enabled="false" id="mul18_5-1"/>
+            <item enabled="false" id="mul19-1"/>
+            <item enabled="false" id="mul19_5-1"/>
+            <item enabled="false" id="mul20-1"/>
+            <item enabled="false" id="mul20_5-1"/>
+            <item enabled="false" id="mul21-1"/>
+            <item enabled="false" id="mul21_5-1"/>
+            <item enabled="false" id="mul22-1"/>
+            <item enabled="false" id="mul22_5-1"/>
+            <item enabled="false" id="mul23-1"/>
+            <item enabled="false" id="mul23_5-1"/>
+            <item enabled="false" id="mul24-1"/>
+            <item enabled="false" id="mul24_5-1"/>
+            <item enabled="false" id="mul25-1"/>
+            <item enabled="false" id="mul25_5-1"/>
+            <item enabled="false" id="mul26-1"/>
+            <item enabled="false" id="mul26_5-1"/>
+            <item enabled="false" id="mul27-1"/>
+            <item enabled="false" id="mul27_5-1"/>
+            <item enabled="false" id="mul28-1"/>
+            <item enabled="false" id="mul28_5-1"/>
+            <item enabled="false" id="mul29-1"/>
+            <item enabled="false" id="mul29_5-1"/>
+            <item enabled="false" id="mul30-1"/>
+        </option>
+        <option enabled="true" id="sckswitcher" selection="pll">
+            <item enabled="true" id="pll" input="" value="2.4E8"/>
+            <item enabled="true" id="main" input="" value="2.4E7"/>
+            <item enabled="false" id="sub" input="" value="32768.0"/>
+            <item enabled="false" id="hoco" input="" value="16000000"/>
+            <item enabled="false" id="loco" input="" value="240000"/>
+        </option>
+        <option enabled="true" id="fclkdivider" selection="comboBox1-4">
+            <item enabled="false" id="comboBox1-1"/>
+            <item enabled="false" id="comboBox1-2"/>
+            <item enabled="true" id="comboBox1-4"/>
+            <item enabled="true" id="comboBox1-8"/>
+            <item enabled="true" id="comboBox1-16"/>
+            <item enabled="true" id="comboBox1-32"/>
+            <item enabled="true" id="comboBox1-64"/>
+        </option>
+        <option enabled="true" id="iclkdivider" selection="comboBox1-2">
+            <item enabled="false" id="comboBox1-1"/>
+            <item enabled="true" id="comboBox1-2"/>
+            <item enabled="true" id="comboBox1-4"/>
+            <item enabled="true" id="comboBox1-8"/>
+            <item enabled="true" id="comboBox1-16"/>
+            <item enabled="true" id="comboBox1-32"/>
+            <item enabled="true" id="comboBox1-64"/>
+        </option>
+        <option enabled="true" id="pclkadivider" selection="comboBox1-2">
+            <item enabled="false" id="comboBox1-1"/>
+            <item enabled="true" id="comboBox1-2"/>
+            <item enabled="true" id="comboBox1-4"/>
+            <item enabled="true" id="comboBox1-8"/>
+            <item enabled="true" id="comboBox1-16"/>
+            <item enabled="true" id="comboBox1-32"/>
+            <item enabled="true" id="comboBox1-64"/>
+        </option>
+        <option enabled="true" id="pclkbdivider" selection="comboBox1-4">
+            <item enabled="false" id="comboBox1-1"/>
+            <item enabled="false" id="comboBox1-2"/>
+            <item enabled="true" id="comboBox1-4"/>
+            <item enabled="true" id="comboBox1-8"/>
+            <item enabled="true" id="comboBox1-16"/>
+            <item enabled="true" id="comboBox1-32"/>
+            <item enabled="true" id="comboBox1-64"/>
+        </option>
+        <option enabled="true" id="pclkcdivider" selection="comboBox1-4">
+            <item enabled="false" id="comboBox1-1"/>
+            <item enabled="false" id="comboBox1-2"/>
+            <item enabled="true" id="comboBox1-4"/>
+            <item enabled="true" id="comboBox1-8"/>
+            <item enabled="true" id="comboBox1-16"/>
+            <item enabled="true" id="comboBox1-32"/>
+            <item enabled="false" id="comboBox1-64"/>
+        </option>
+        <option enabled="true" id="pclkddivider" selection="comboBox1-4">
+            <item enabled="false" id="comboBox1-1"/>
+            <item enabled="false" id="comboBox1-2"/>
+            <item enabled="true" id="comboBox1-4"/>
+            <item enabled="true" id="comboBox1-8"/>
+            <item enabled="true" id="comboBox1-16"/>
+            <item enabled="true" id="comboBox1-32"/>
+            <item enabled="false" id="comboBox1-64"/>
+        </option>
+        <option enabled="true" id="bckdivider" selection="comboBox1-2">
+            <item enabled="false" id="comboBox1-1"/>
+            <item enabled="true" id="comboBox1-2"/>
+            <item enabled="true" id="comboBox1-4"/>
+            <item enabled="true" id="comboBox1-8"/>
+            <item enabled="true" id="comboBox1-16"/>
+            <item enabled="true" id="comboBox1-32"/>
+            <item enabled="true" id="comboBox1-64"/>
+        </option>
+        <option enabled="true" id="bckselectorenable" selection="uncheck">
+            <item enabled="true" id="check"/>
+            <item enabled="true" id="uncheck"/>
+        </option>
+        <option enabled="false" id="bckselector" selection="comboBox1-2">
+            <item enabled="false" id="comboBox1-1"/>
+            <item enabled="true" id="comboBox1-2"/>
+        </option>
+        <option enabled="true" id="uckenable" selection="uncheck">
+            <item enabled="true" id="check"/>
+            <item enabled="true" id="uncheck"/>
+        </option>
+        <option enabled="false" id="uckdivider" selection="comboBox1-5">
+            <item enabled="false" id="comboBox1-2"/>
+            <item enabled="false" id="comboBox1-3"/>
+            <item enabled="false" id="comboBox1-4"/>
+            <item enabled="true" id="comboBox1-5"/>
+        </option>
+        <option enabled="true" id="fclk" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="60.0"/>
+        </option>
+        <option enabled="true" id="iclk" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="120.0"/>
+        </option>
+        <option enabled="true" id="pclka" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="120.0"/>
+        </option>
+        <option enabled="true" id="pclkb" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="60.0"/>
+        </option>
+        <option enabled="true" id="pclkc" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="60.0"/>
+        </option>
+        <option enabled="true" id="pclkd" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="60.0"/>
+        </option>
+        <option enabled="true" id="bck" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="120.0"/>
+        </option>
+        <option enabled="false" id="bckpin" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="60.0"/>
+        </option>
+        <option enabled="false" id="sdclkenable" selection="uncheck">
+            <item enabled="true" id="check"/>
+            <item enabled="true" id="uncheck"/>
+        </option>
+        <option enabled="false" id="sdclk" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="120.0"/>
+        </option>
+        <option enabled="false" id="uclk" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="48.0"/>
+        </option>
+        <option enabled="false" id="caclclk" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="240"/>
+        </option>
+        <option enabled="false" id="cachclk" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="16"/>
+        </option>
+        <option enabled="false" id="cacsclk" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="32.768"/>
+        </option>
+        <option enabled="false" id="rtcsclkenable" selection="uncheck">
+            <item enabled="true" id="check"/>
+            <item enabled="true" id="uncheck"/>
+        </option>
+        <option enabled="false" id="rtcsclk" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="32.768"/>
+        </option>
+        <option enabled="false" id="cacilclk" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="120"/>
+        </option>
+        <option enabled="true" id="cacmclk" selection="textoutputitem">
+            <item enabled="true" id="textoutputitem" input="" value="24.0"/>
+        </option>
+    </tool>
+    <tool id="Interrupt">
+        <Item currentVect="16" id="BSC_BUSERR" priority="15" usedState="Not Use"/>
+        <Item currentVect="18" id="RAM_RAMERR" priority="15" usedState="Not Use"/>
+        <Item currentVect="21" id="FCU_FIFERR" priority="15" usedState="Not Use"/>
+        <Item currentVect="23" id="FCU_FRDYI" priority="15" usedState="Not Use"/>
+        <Item currentVect="26" id="ICU_SWINT2" priority="1" usedState="Not Use"/>
+        <Item currentVect="27" id="ICU_SWINT" priority="1" usedState="Not Use"/>
+        <Item currentVect="28" id="CMT0_CMI0" priority="15" usedState="Not Use"/>
+        <Item currentVect="29" id="CMT1_CMI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="30" id="CMTW0_CMWI0" priority="15" usedState="Not Use"/>
+        <Item currentVect="31" id="CMTW1_CMWI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="34" id="USB0_D0FIFO0" priority="15" usedState="Not Use"/>
+        <Item currentVect="35" id="USB0_D1FIFO0" priority="15" usedState="Not Use"/>
+        <Item currentVect="38" id="RSPI0_SPRI0" priority="15" usedState="Not Use"/>
+        <Item currentVect="39" id="RSPI0_SPTI0" priority="15" usedState="Not Use"/>
+        <Item currentVect="40" id="RSPI1_SPRI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="41" id="RSPI1_SPTI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="42" id="QSPI_SPRI" priority="15" usedState="Not Use"/>
+        <Item currentVect="43" id="QSPI_SPTI" priority="15" usedState="Not Use"/>
+        <Item currentVect="44" id="SDHI_SBFAI" priority="15" usedState="Not Use"/>
+        <Item currentVect="45" id="MMCIF_MBFAI" priority="15" usedState="Not Use"/>
+        <Item currentVect="50" id="RIIC1_RXI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="51" id="RIIC1_TXI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="52" id="RIIC0_RXI0" priority="15" usedState="Not Use"/>
+        <Item currentVect="53" id="RIIC0_TXI0" priority="15" usedState="Not Use"/>
+        <Item currentVect="54" id="RIIC2_RXI2" priority="15" usedState="Not Use"/>
+        <Item currentVect="55" id="RIIC2_TXI2" priority="15" usedState="Not Use"/>
+        <Item currentVect="58" id="SCI0_RXI0" priority="15" usedState="Not Use"/>
+        <Item currentVect="59" id="SCI0_TXI0" priority="15" usedState="Not Use"/>
+        <Item currentVect="60" id="SCI1_RXI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="61" id="SCI1_TXI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="62" id="SCI2_RXI2" priority="15" usedState="Not Use"/>
+        <Item currentVect="63" id="SCI2_TXI2" priority="15" usedState="Not Use"/>
+        <Item currentVect="64" id="ICU_IRQ0" priority="15" usedState="Not Use"/>
+        <Item currentVect="65" id="ICU_IRQ1" priority="15" usedState="Not Use"/>
+        <Item currentVect="66" id="ICU_IRQ2" priority="15" usedState="Not Use"/>
+        <Item currentVect="67" id="ICU_IRQ3" priority="15" usedState="Not Use"/>
+        <Item currentVect="68" id="ICU_IRQ4" priority="15" usedState="Not Use"/>
+        <Item currentVect="69" id="ICU_IRQ5" priority="15" usedState="Not Use"/>
+        <Item currentVect="70" id="ICU_IRQ6" priority="15" usedState="Not Use"/>
+        <Item currentVect="71" id="ICU_IRQ7" priority="15" usedState="Not Use"/>
+        <Item currentVect="72" id="ICU_IRQ8" priority="15" usedState="Not Use"/>
+        <Item currentVect="73" id="ICU_IRQ9" priority="15" usedState="Not Use"/>
+        <Item currentVect="74" id="ICU_IRQ10" priority="15" usedState="Not Use"/>
+        <Item currentVect="75" id="ICU_IRQ11" priority="15" usedState="Not Use"/>
+        <Item currentVect="76" id="ICU_IRQ12" priority="15" usedState="Not Use"/>
+        <Item currentVect="77" id="ICU_IRQ13" priority="15" usedState="Not Use"/>
+        <Item currentVect="78" id="ICU_IRQ14" priority="15" usedState="Not Use"/>
+        <Item currentVect="79" id="ICU_IRQ15" priority="15" usedState="Not Use"/>
+        <Item currentVect="80" id="SCI3_RXI3" priority="15" usedState="Not Use"/>
+        <Item currentVect="81" id="SCI3_TXI3" priority="15" usedState="Not Use"/>
+        <Item currentVect="82" id="SCI4_RXI4" priority="15" usedState="Not Use"/>
+        <Item currentVect="83" id="SCI4_TXI4" priority="15" usedState="Not Use"/>
+        <Item currentVect="84" id="SCI5_RXI5" priority="15" usedState="Not Use"/>
+        <Item currentVect="85" id="SCI5_TXI5" priority="15" usedState="Not Use"/>
+        <Item currentVect="86" id="SCI6_RXI6" priority="15" usedState="Not Use"/>
+        <Item currentVect="87" id="SCI6_TXI6" priority="15" usedState="Not Use"/>
+        <Item currentVect="88" id="LVD1_LVD1" priority="15" usedState="Not Use"/>
+        <Item currentVect="89" id="LVD2_LVD2" priority="15" usedState="Not Use"/>
+        <Item currentVect="90" id="USB0_USBR0" priority="15" usedState="Not Use"/>
+        <Item currentVect="92" id="RTC_ALM" priority="15" usedState="Not Use"/>
+        <Item currentVect="93" id="RTC_PRD" priority="15" usedState="Not Use"/>
+        <Item currentVect="95" id="IWDT_IWUNI" priority="15" usedState="Not Use"/>
+        <Item currentVect="96" id="WDT_WUNI" priority="15" usedState="Not Use"/>
+        <Item currentVect="97" id="PDC_PCDFI" priority="15" usedState="Not Use"/>
+        <Item currentVect="98" id="SCI7_RXI7" priority="15" usedState="Not Use"/>
+        <Item currentVect="99" id="SCI7_TXI7" priority="15" usedState="Not Use"/>
+        <Item currentVect="100" id="SCI8_RXI8" priority="15" usedState="Used"/>
+        <Item currentVect="101" id="SCI8_TXI8" priority="15" usedState="Used"/>
+        <Item currentVect="102" id="SCI9_RXI9" priority="15" usedState="Not Use"/>
+        <Item currentVect="103" id="SCI9_TXI9" priority="15" usedState="Not Use"/>
+        <Item currentVect="104" id="SCI10_RXI10" priority="15" usedState="Not Use"/>
+        <Item currentVect="105" id="SCI10_TXI10" priority="15" usedState="Not Use"/>
+        <Item currentVect="106" groupchild="&lt;br&gt;1-ERS0&lt;br&gt;2-ERS1" id="BE0" priority="15" usedState="Not Use"/>
+        <Item currentVect="107" groupchild="&lt;br&gt;1-SDIOI" id="BL2" priority="15" usedState="Not Use"/>
+        <Item currentVect="108" id="RSPI2_SPRI2" priority="15" usedState="Not Use"/>
+        <Item currentVect="109" id="RSPI2_SPTI2" priority="15" usedState="Not Use"/>
+        <Item currentVect="110" groupchild="&lt;br&gt;1-TEI0&lt;br&gt;2-ERI0&lt;br&gt;3-TEI1&lt;br&gt;4-ERI1&lt;br&gt;5-TEI2&lt;br&gt;6-ERI2&lt;br&gt;7-TEI3&lt;br&gt;8-ERI3&lt;br&gt;9-TEI4&lt;br&gt;10-ERI4&lt;br&gt;11-TEI5&lt;br&gt;12-ERI5&lt;br&gt;13-TEI6&lt;br&gt;14-ERI6&lt;br&gt;15-TEI7&lt;br&gt;16-ERI7&lt;br&gt;17-TEI12&lt;br&gt;18-ERI12&lt;br&gt;19-SCIX0&lt;br&gt;20-SCIX1&lt;br&gt;21-SCIX2&lt;br&gt;22-SCIX3&lt;br&gt;23-QSPSSLI&lt;br&gt;24-FERRI&lt;br&gt;25-MENDI&lt;br&gt;26-OVFI&lt;br&gt;27-DOPCI&lt;br&gt;28-PCFEI&lt;br&gt;29-PCERI" id="BL0" priority="15" usedState="Not Use"/>
+        <Item currentVect="111" groupchild="&lt;br&gt;1-CDETI&lt;br&gt;2-CACI&lt;br&gt;3-SDACI&lt;br&gt;4-CDETIO&lt;br&gt;5-ERRIO&lt;br&gt;6-ACCIO&lt;br&gt;7-OEI1&lt;br&gt;8-OEI2&lt;br&gt;9-OEI3&lt;br&gt;10-OEI4&lt;br&gt;11-TEI0&lt;br&gt;12-EEI0&lt;br&gt;13-TEI2&lt;br&gt;14-EEI2&lt;br&gt;15-S12CMPAI&lt;br&gt;16-S12CMPBI&lt;br&gt;17-S12CMPAI1&lt;br&gt;18-S12CMPBI1&lt;br&gt;19-TEI8&lt;br&gt;20-ERI8&lt;br&gt;21-TEI9&lt;br&gt;22-ERI9&lt;br&gt;23-TEI1&lt;br&gt;24-EEI1" id="BL1" priority="15" usedState="Used"/>
+        <Item currentVect="112" groupchild="&lt;br&gt;1-TEI10&lt;br&gt;2-ERI10&lt;br&gt;3-TEI11&lt;br&gt;4-ERI11&lt;br&gt;5-SPII0&lt;br&gt;6-SPEI0&lt;br&gt;7-SPII1&lt;br&gt;8-SPEI1&lt;br&gt;9-SPII2&lt;br&gt;10-SPEI2" id="AL0" priority="15" usedState="Not Use"/>
+        <Item currentVect="113" groupchild="&lt;br&gt;1-EINT0&lt;br&gt;2-VPOS&lt;br&gt;3-GR1UF&lt;br&gt;4-GR2UF&lt;br&gt;5-DRW_IRQ" id="AL1" priority="2" usedState="Used"/>
+        <Item currentVect="114" id="SCI11_RXI11" priority="15" usedState="Not Use"/>
+        <Item currentVect="115" id="SCI11_TXI11" priority="15" usedState="Not Use"/>
+        <Item currentVect="116" id="SCI12_RXI12" priority="15" usedState="Not Use"/>
+        <Item currentVect="117" id="SCI12_TXI12" priority="15" usedState="Not Use"/>
+        <Item currentVect="120" id="DMAC_DMAC0I" priority="15" usedState="Not Use"/>
+        <Item currentVect="121" id="DMAC_DMAC1I" priority="15" usedState="Not Use"/>
+        <Item currentVect="122" id="DMAC_DMAC2I" priority="15" usedState="Not Use"/>
+        <Item currentVect="123" id="DMAC_DMAC3I" priority="15" usedState="Not Use"/>
+        <Item currentVect="124" id="DMAC_DMAC74I" priority="15" usedState="Not Use"/>
+        <Item currentVect="125" id="OST_OSTDI" priority="15" usedState="Not Use"/>
+        <Item currentVect="126" id="EXDMAC_EXDMAC0I" priority="15" usedState="Not Use"/>
+        <Item currentVect="127" id="EXDMAC_EXDMAC1I" priority="15" usedState="Not Use"/>
+        <Item currentVect="128" defaultVect="128" id="CMT2_CMI2" priority="15" usedState="Not Use"/>
+        <Item currentVect="129" defaultVect="129" id="CMT3_CMI3" priority="15" usedState="Not Use"/>
+        <Item currentVect="130" defaultVect="130" id="TPU0_TGI0A" priority="15" usedState="Not Use"/>
+        <Item currentVect="131" defaultVect="131" id="TPU0_TGI0B" priority="15" usedState="Not Use"/>
+        <Item currentVect="132" defaultVect="132" id="TPU0_TGI0C" priority="15" usedState="Not Use"/>
+        <Item currentVect="133" defaultVect="133" id="TPU0_TGI0D" priority="15" usedState="Not Use"/>
+        <Item currentVect="134" defaultVect="134" id="TPU0_TCI0V" priority="15" usedState="Not Use"/>
+        <Item currentVect="135" defaultVect="135" id="TPU1_TGI1B" priority="15" usedState="Not Use"/>
+        <Item currentVect="136" defaultVect="136" id="TPU1_TCI1V" priority="15" usedState="Not Use"/>
+        <Item currentVect="137" defaultVect="137" id="TPU1_TCI1U" priority="15" usedState="Not Use"/>
+        <Item currentVect="138" defaultVect="138" id="TPU2_TGI2A" priority="15" usedState="Not Use"/>
+        <Item currentVect="139" defaultVect="139" id="TPU2_TGI2B" priority="15" usedState="Not Use"/>
+        <Item currentVect="140" defaultVect="140" id="TPU2_TCI2V" priority="15" usedState="Not Use"/>
+        <Item currentVect="141" defaultVect="141" id="TPU2_TCI2U" priority="15" usedState="Not Use"/>
+        <Item currentVect="142" defaultVect="142" id="TPU3_TGI3A" priority="15" usedState="Not Use"/>
+        <Item currentVect="143" defaultVect="143" id="TPU3_TGI3B" priority="15" usedState="Not Use"/>
+        <Item currentVect="144" defaultVect="144" id="TPU1_TGI1A" priority="15" usedState="Not Use"/>
+        <Item currentVect="145" defaultVect="145" id="TPU3_TGI3C" priority="15" usedState="Not Use"/>
+        <Item currentVect="146" defaultVect="146" id="TMR0_CMIA0" priority="15" usedState="Not Use"/>
+        <Item currentVect="147" defaultVect="147" id="TMR0_CMIB0" priority="15" usedState="Not Use"/>
+        <Item currentVect="148" defaultVect="148" id="TMR0_OVI0" priority="15" usedState="Not Use"/>
+        <Item currentVect="149" defaultVect="149" id="TMR1_CMIA1" priority="15" usedState="Not Use"/>
+        <Item currentVect="150" defaultVect="150" id="TMR1_CMIB1" priority="15" usedState="Not Use"/>
+        <Item currentVect="151" defaultVect="151" id="TMR1_OVI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="152" defaultVect="152" id="TMR2_CMIA2" priority="15" usedState="Not Use"/>
+        <Item currentVect="153" defaultVect="153" id="TMR2_CMIB2" priority="15" usedState="Not Use"/>
+        <Item currentVect="154" defaultVect="154" id="TMR2_OVI2" priority="15" usedState="Not Use"/>
+        <Item currentVect="155" defaultVect="155" id="TMR3_CMIA3" priority="15" usedState="Not Use"/>
+        <Item currentVect="156" defaultVect="156" id="TMR3_CMIB3" priority="15" usedState="Not Use"/>
+        <Item currentVect="157" defaultVect="157" id="TMR3_OVI3" priority="15" usedState="Not Use"/>
+        <Item currentVect="158" defaultVect="158" id="TPU3_TGI3D" priority="15" usedState="Not Use"/>
+        <Item currentVect="159" defaultVect="159" id="TPU3_TCI3V" priority="15" usedState="Not Use"/>
+        <Item currentVect="160" defaultVect="160" id="TPU4_TGI4A" priority="15" usedState="Not Use"/>
+        <Item currentVect="161" defaultVect="161" id="TPU4_TGI4B" priority="15" usedState="Not Use"/>
+        <Item currentVect="162" defaultVect="162" id="TPU4_TCI4V" priority="15" usedState="Not Use"/>
+        <Item currentVect="163" defaultVect="163" id="TPU4_TCI4U" priority="15" usedState="Not Use"/>
+        <Item currentVect="164" defaultVect="164" id="TPU5_TGI5A" priority="15" usedState="Not Use"/>
+        <Item currentVect="165" defaultVect="165" id="TPU5_TGI5B" priority="15" usedState="Not Use"/>
+        <Item currentVect="166" defaultVect="166" id="TPU5_TCI5V" priority="15" usedState="Not Use"/>
+        <Item currentVect="167" defaultVect="167" id="TPU5_TCI5U" priority="15" usedState="Not Use"/>
+        <Item currentVect="168" defaultVect="168" id="CMTW0_IC0I0" priority="15" usedState="Not Use"/>
+        <Item currentVect="169" defaultVect="169" id="CMTW0_IC1I0" priority="15" usedState="Not Use"/>
+        <Item currentVect="170" defaultVect="170" id="CMTW0_OC0I0" priority="15" usedState="Not Use"/>
+        <Item currentVect="171" defaultVect="171" id="CMTW0_OC1I0" priority="15" usedState="Not Use"/>
+        <Item currentVect="172" defaultVect="172" id="CMTW1_IC0I1" priority="15" usedState="Not Use"/>
+        <Item currentVect="173" defaultVect="173" id="CMTW1_IC1I1" priority="15" usedState="Not Use"/>
+        <Item currentVect="174" defaultVect="174" id="CMTW1_OC0I1" priority="15" usedState="Not Use"/>
+        <Item currentVect="175" defaultVect="175" id="CMTW1_OC1I1" priority="15" usedState="Not Use"/>
+        <Item currentVect="176" defaultVect="176" id="RTC_CUP" priority="15" usedState="Not Use"/>
+        <Item currentVect="177" defaultVect="177" id="CAN0_RXF0" priority="15" usedState="Not Use"/>
+        <Item currentVect="178" defaultVect="178" id="CAN0_TXF0" priority="15" usedState="Not Use"/>
+        <Item currentVect="179" defaultVect="179" id="CAN0_RXM0" priority="15" usedState="Not Use"/>
+        <Item currentVect="180" defaultVect="180" id="CAN0_TXM0" priority="15" usedState="Not Use"/>
+        <Item currentVect="181" defaultVect="181" id="CAN1_RXF1" priority="15" usedState="Not Use"/>
+        <Item currentVect="182" defaultVect="182" id="CAN1_TXF1" priority="15" usedState="Not Use"/>
+        <Item currentVect="183" defaultVect="183" id="CAN1_RXM1" priority="15" usedState="Not Use"/>
+        <Item currentVect="184" defaultVect="184" id="CAN1_TXM1" priority="15" usedState="Not Use"/>
+        <Item currentVect="185" defaultVect="185" id="USB0_USBI0" priority="15" usedState="Not Use"/>
+        <Item currentVect="186" defaultVect="186" id="S12AD_S12ADI" priority="15" usedState="Not Use"/>
+        <Item currentVect="187" defaultVect="187" id="S12AD_S12GBADI" priority="15" usedState="Not Use"/>
+        <Item currentVect="188" defaultVect="188" id="S12AD_S12GCADI" priority="15" usedState="Not Use"/>
+        <Item currentVect="189" defaultVect="189" id="S12AD1_S12ADI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="190" defaultVect="190" id="S12AD1_S12GBADI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="191" defaultVect="191" id="S12AD1_S12GCADI1" priority="15" usedState="Not Use"/>
+        <Item currentVect="192" defaultVect="192" id="RNG_RNGEND" priority="15" usedState="Not Use"/>
+        <Item currentVect="193" defaultVect="193" id="ELC_ELSR18I" priority="15" usedState="Not Use"/>
+        <Item currentVect="194" defaultVect="194" id="ELC_ELSR19I" priority="15" usedState="Not Use"/>
+        <Item currentVect="195" defaultVect="195" id="TSIP_PROC_BUSY" priority="15" usedState="Not Use"/>
+        <Item currentVect="196" defaultVect="196" id="TSIP_ROMOK" priority="15" usedState="Not Use"/>
+        <Item currentVect="197" defaultVect="197" id="TSIP_LONG_PLG" priority="15" usedState="Not Use"/>
+        <Item currentVect="198" defaultVect="198" id="TSIP_TEST_BUSY" priority="15" usedState="Not Use"/>
+        <Item currentVect="199" defaultVect="199" id="TSIP_WRRDY0" priority="15" usedState="Not Use"/>
+        <Item currentVect="200" defaultVect="200" id="TSIP_WRRDY1" priority="15" usedState="Not Use"/>
+        <Item currentVect="201" defaultVect="201" id="TSIP_WRRDY4" priority="15" usedState="Not Use"/>
+        <Item currentVect="202" defaultVect="202" id="TSIP_RDRDY0" priority="15" usedState="Not Use"/>
+        <Item currentVect="203" defaultVect="203" id="TSIP_RDRDY1" priority="15" usedState="Not Use"/>
+        <Item currentVect="204" defaultVect="204" id="TSIP_INTEGRATE_WRRDY" priority="15" usedState="Not Use"/>
+        <Item currentVect="205" defaultVect="205" id="TSIP_INTEGRATE_RDRDY" priority="15" usedState="Not Use"/>
+        <Item currentVect="206" id="PERIB_INTB206" priority="15" usedState="Not Use"/>
+        <Item currentVect="207" id="PERIB_INTB207" priority="15" usedState="Not Use"/>
+        <Item currentVect="208" defaultVect="208" id="MTU1_TGIA1" priority="15" usedState="Not Use"/>
+        <Item currentVect="209" defaultVect="209" id="MTU0_TGIA0" priority="15" usedState="Not Use"/>
+        <Item currentVect="210" defaultVect="210" id="MTU0_TGIB0" priority="15" usedState="Not Use"/>
+        <Item currentVect="211" defaultVect="211" id="MTU0_TGIC0" priority="15" usedState="Not Use"/>
+        <Item currentVect="212" defaultVect="212" id="MTU0_TGID0" priority="15" usedState="Not Use"/>
+        <Item currentVect="213" defaultVect="213" id="MTU0_TCIV0" priority="15" usedState="Not Use"/>
+        <Item currentVect="214" defaultVect="214" id="MTU0_TGIE0" priority="15" usedState="Not Use"/>
+        <Item currentVect="215" defaultVect="215" id="MTU0_TGIF0" priority="15" usedState="Not Use"/>
+        <Item currentVect="216" defaultVect="216" id="MTU1_TGIB1" priority="15" usedState="Not Use"/>
+        <Item currentVect="217" defaultVect="217" id="MTU1_TCIV1" priority="15" usedState="Not Use"/>
+        <Item currentVect="218" defaultVect="218" id="MTU1_TCIU1" priority="15" usedState="Not Use"/>
+        <Item currentVect="219" defaultVect="219" id="MTU2_TGIA2" priority="15" usedState="Not Use"/>
+        <Item currentVect="220" defaultVect="220" id="MTU2_TGIB2" priority="15" usedState="Not Use"/>
+        <Item currentVect="221" defaultVect="221" id="MTU2_TCIV2" priority="15" usedState="Not Use"/>
+        <Item currentVect="222" defaultVect="222" id="MTU2_TCIU2" priority="15" usedState="Not Use"/>
+        <Item currentVect="223" defaultVect="223" id="MTU3_TGIA3" priority="15" usedState="Not Use"/>
+        <Item currentVect="224" defaultVect="224" id="MTU3_TGIB3" priority="15" usedState="Not Use"/>
+        <Item currentVect="225" defaultVect="225" id="MTU3_TGIC3" priority="15" usedState="Not Use"/>
+        <Item currentVect="226" defaultVect="226" id="MTU3_TGID3" priority="15" usedState="Not Use"/>
+        <Item currentVect="227" defaultVect="227" id="MTU3_TCIV3" priority="15" usedState="Not Use"/>
+        <Item currentVect="228" defaultVect="228" id="MTU4_TGIA4" priority="15" usedState="Not Use"/>
+        <Item currentVect="229" defaultVect="229" id="MTU4_TGIB4" priority="15" usedState="Not Use"/>
+        <Item currentVect="230" defaultVect="230" id="MTU4_TGIC4" priority="15" usedState="Not Use"/>
+        <Item currentVect="231" defaultVect="231" id="MTU4_TGID4" priority="15" usedState="Not Use"/>
+        <Item currentVect="232" defaultVect="232" id="MTU4_TCIV4" priority="15" usedState="Not Use"/>
+        <Item currentVect="233" defaultVect="233" id="MTU5_TGIU5" priority="15" usedState="Not Use"/>
+        <Item currentVect="234" defaultVect="234" id="MTU5_TGIV5" priority="15" usedState="Not Use"/>
+        <Item currentVect="235" defaultVect="235" id="MTU5_TGIW5" priority="15" usedState="Not Use"/>
+        <Item currentVect="236" defaultVect="236" id="MTU6_TGIA6" priority="15" usedState="Not Use"/>
+        <Item currentVect="237" defaultVect="237" id="MTU6_TGIB6" priority="15" usedState="Not Use"/>
+        <Item currentVect="238" defaultVect="238" id="MTU6_TGIC6" priority="15" usedState="Not Use"/>
+        <Item currentVect="239" defaultVect="239" id="MTU6_TGID6" priority="15" usedState="Not Use"/>
+        <Item currentVect="240" defaultVect="240" id="MTU6_TCIV6" priority="15" usedState="Not Use"/>
+        <Item currentVect="241" defaultVect="241" id="MTU7_TGIA7" priority="15" usedState="Not Use"/>
+        <Item currentVect="242" defaultVect="242" id="MTU7_TGIB7" priority="15" usedState="Not Use"/>
+        <Item currentVect="243" defaultVect="243" id="MTU7_TGIC7" priority="15" usedState="Not Use"/>
+        <Item currentVect="244" defaultVect="244" id="MTU7_TGID7" priority="15" usedState="Not Use"/>
+        <Item currentVect="245" defaultVect="245" id="MTU7_TCIV7" priority="15" usedState="Not Use"/>
+        <Item currentVect="246" defaultVect="246" id="MTU8_TGIA8" priority="15" usedState="Not Use"/>
+        <Item currentVect="247" defaultVect="247" id="MTU8_TGIB8" priority="15" usedState="Not Use"/>
+        <Item currentVect="248" defaultVect="248" id="MTU8_TGIC8" priority="15" usedState="Not Use"/>
+        <Item currentVect="249" defaultVect="249" id="MTU8_TGID8" priority="15" usedState="Not Use"/>
+        <Item currentVect="250" defaultVect="250" id="MTU8_TCIV8" priority="15" usedState="Not Use"/>
+        <Item currentVect="251" defaultVect="251" id="AES_AESRDY" priority="15" usedState="Not Use"/>
+        <Item currentVect="252" defaultVect="252" id="AES_AESEND" priority="15" usedState="Not Use"/>
+        <Item currentVect="253" id="PERIA_INTA253" priority="15" usedState="Not Use"/>
+        <Item currentVect="254" id="PERIA_INTA254" priority="15" usedState="Not Use"/>
+        <Item currentVect="255" id="PERIA_INTA255" priority="15" usedState="Not Use"/>
+    </tool>
+    <tool id="Pins" version="1.0.1.0">
+        <pinItem allocation="22" comments="" direction="None" id="XTAL" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="59" comments="" direction="None" id="RXD8" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="113" comments="" direction="O" id="PG6" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="116" comments="" direction="O" id="PG5" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="111" comments="" direction="O" id="PG7" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="81" comments="" direction="None" id="ET0_TX_EN" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="101" comments="" direction="None" id="ET0_MDC" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="76" comments="" direction="None" id="ET0_COL" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="74" comments="" direction="None" id="ET0_CRS" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="58" comments="" direction="None" id="TXD8" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="24" comments="" direction="None" id="EXTAL" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="86" comments="" direction="None" id="ET0_RX_DV" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="27" comments="" direction="None" id="ET0_LINKSTA" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="84" comments="" direction="None" id="ET0_RX_ER" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="77" comments="" direction="None" id="ET0_ETXD3" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="78" comments="" direction="None" id="ET0_ETXD2" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="79" comments="" direction="None" id="ET0_ETXD1" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="80" comments="" direction="None" id="ET0_ETXD0" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="85" comments="" direction="None" id="ET0_RX_CLK" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="91" comments="" direction="None" id="ET0_ERXD3" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="89" comments="" direction="None" id="ET0_ERXD2" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="88" comments="" direction="None" id="ET0_ERXD1" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="87" comments="" direction="None" id="ET0_ERXD0" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="82" comments="" direction="None" id="ET0_TX_CLK" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="93" comments="" direction="O" id="P73" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinItem allocation="102" comments="" direction="None" id="ET0_MDIO" isUsedBySoftware="true" locked="false" status="0"/>
+        <pinnumItem comment="ET-ET0ERXD1_RMII0RXD1" id="88"/>
+        <pinnumItem comment="ET-ET0ERXD2" id="89"/>
+        <pinnumItem comment="OnTFT-G2" id="110"/>
+        <pinnumItem comment="LED1" id="111"/>
+        <pinnumItem comment="OnTFT-G3" id="112"/>
+        <pinnumItem comment="LED2" id="113"/>
+        <pinnumItem comment="OnTFT-G4" id="114"/>
+        <pinnumItem comment="LED3" id="116"/>
+        <pinnumItem comment="ET-ET0ERXD3" id="91"/>
+        <pinnumItem comment="OnTFT-G5" id="118"/>
+        <pinnumItem comment="PMOD1-IO2" id="119"/>
+        <pinnumItem comment="LED0" id="93"/>
+        <pinnumItem comment="OnTFT-BACKLIGHT" id="94"/>
+        <pinnumItem comment="SDRAM-A14" id="95"/>
+        <pinnumItem comment="OnTFT-CLK" id="96"/>
+        <pinnumItem comment="OnTFT-VSYNC" id="97"/>
+        <pinnumItem comment="EMLE" id="10"/>
+        <pinnumItem comment="SDRAM-A11" id="98"/>
+        <pinnumItem comment="OnTFT-HSYNC" id="99"/>
+        <pinnumItem comment="PMOD1-CS" id="13"/>
+        <pinnumItem comment="TRST#" id="17"/>
+        <pinnumItem comment="XCIN" id="19"/>
+        <pinnumItem comment="SDRAM-DQMH" id="120"/>
+        <pinnumItem comment="PMOD1-IO3" id="121"/>
+        <pinnumItem comment="AVSS0" id="1"/>
+        <pinnumItem comment="LED2" id="122"/>
+        <pinnumItem comment="SW2" id="2"/>
+        <pinnumItem comment="RL78G1CRTS" id="123"/>
+        <pinnumItem comment="AVCC1" id="3"/>
+        <pinnumItem comment="SDRAM-CKE" id="124"/>
+        <pinnumItem comment="SW1" id="4"/>
+        <pinnumItem comment="OnTFT-G6" id="125"/>
+        <pinnumItem comment="AVSS1" id="5"/>
+        <pinnumItem comment="OnTFT-G7" id="126"/>
+        <pinnumItem comment="PMOD1-SCK" id="6"/>
+        <pinnumItem comment="PMOD1-MISO" id="7"/>
+        <pinnumItem comment="SDRAM-SDCLK" id="128"/>
+        <pinnumItem comment="PMOD1-MOSI" id="8"/>
+        <pinnumItem comment="PMOD1-IO1" id="9"/>
+        <pinnumItem comment="XCOUT" id="20"/>
+        <pinnumItem comment="RES#" id="21"/>
+        <pinnumItem comment="XTAL" id="22"/>
+        <pinnumItem comment="EXTAL" id="24"/>
+        <pinnumItem comment="NMI" id="26"/>
+        <pinnumItem comment="ET-ET0LINKSTA" id="27"/>
+        <pinnumItem comment="CAN1RX" id="28"/>
+        <pinnumItem comment="CAN1TX" id="29"/>
+        <pinnumItem comment="OnTFT-B3" id="130"/>
+        <pinnumItem comment="OnTFT-B4" id="131"/>
+        <pinnumItem comment="OnTFT-B5" id="132"/>
+        <pinnumItem comment="OnTFT-B6" id="133"/>
+        <pinnumItem comment="OnTFT-B7" id="134"/>
+        <pinnumItem comment="SDRAM-D8" id="135"/>
+        <pinnumItem comment="WE#/" id="136"/>
+        <pinnumItem comment="SDRAM-CASn" id="137"/>
+        <pinnumItem comment="DRAM-RASn" id="138"/>
+        <pinnumItem comment="SDRAM-SDCSn" id="139"/>
+        <pinnumItem comment="E1-TMS" id="30"/>
+        <pinnumItem comment="E1-TDI_RXD" id="31"/>
+        <pinnumItem comment="RSPI-CS" id="32"/>
+        <pinnumItem comment="RSPI-MISO" id="33"/>
+        <pinnumItem comment="E1-TCK" id="34"/>
+        <pinnumItem comment="E1-TDO_TXD" id="35"/>
+        <pinnumItem comment="RSPI-CLK" id="36"/>
+        <pinnumItem comment="RSPI-MOSI" id="37"/>
+        <pinnumItem comment="SDHI_CD" id="38"/>
+        <pinnumItem comment="JA3-Csa" id="141"/>
+        <pinnumItem comment="QIO1-B" id="143"/>
+        <pinnumItem comment="QIO0-B" id="145"/>
+        <pinnumItem comment="QSPCLK-B" id="147"/>
+        <pinnumItem comment="QSSL-B" id="148"/>
+        <pinnumItem comment="OnTFT-DISP" id="149"/>
+        <pinnumItem comment="SDHI_WP" id="40"/>
+        <pinnumItem comment="SDHI-D1" id="42"/>
+        <pinnumItem comment="SDHI_D0" id="43"/>
+        <pinnumItem comment="SDHI_CLK" id="44"/>
+        <pinnumItem comment="SDHI-CMD" id="45"/>
+        <pinnumItem comment="SDHI_D3" id="46"/>
+        <pinnumItem comment="SDHI_D2" id="47"/>
+        <pinnumItem comment="USB0_VBUS" id="48"/>
+        <pinnumItem comment="SDHIPE" id="49"/>
+        <pinnumItem comment="QIO3-B" id="150"/>
+        <pinnumItem comment="QIO2-B" id="154"/>
+        <pinnumItem comment="SDRAM-D1" id="156"/>
+        <pinnumItem comment="SDRAM-D0" id="158"/>
+        <pinnumItem comment="PMOD1-IO0" id="50"/>
+        <pinnumItem comment="USB0_OVRCURA" id="51"/>
+        <pinnumItem comment="E2P-SDA" id="52"/>
+        <pinnumItem comment="E2P-SCL" id="53"/>
+        <pinnumItem comment="SERIAL-TXD" id="58"/>
+        <pinnumItem comment="SERIAL-RXD" id="59"/>
+        <pinnumItem comment="TFT-SCL" id="160"/>
+        <pinnumItem comment="TFT-SDA" id="163"/>
+        <pinnumItem comment="SERIAL-CTS" id="68"/>
+        <pinnumItem comment="OnTFT-INT" id="170"/>
+        <pinnumItem comment="VREFL0" id="172"/>
+        <pinnumItem comment="P40" id="173"/>
+        <pinnumItem comment="VREFH0" id="174"/>
+        <pinnumItem comment="AVCC0" id="175"/>
+        <pinnumItem comment="P07" id="176"/>
+        <pinnumItem comment="ET-ET0CRS_RMII0CRSDV" id="74"/>
+        <pinnumItem comment="ET-ET0COL" id="76"/>
+        <pinnumItem comment="ET-ET0ETXD3" id="77"/>
+        <pinnumItem comment="ET-ET0ETXD2" id="78"/>
+        <pinnumItem comment="ET-ET0ETXD1_RMII0TXD1" id="79"/>
+        <pinnumItem comment="OnTFT-DEN" id="100"/>
+        <pinnumItem comment="ET-ET0MDC" id="101"/>
+        <pinnumItem comment="ET-ET0MDIO" id="102"/>
+        <pinnumItem comment="OnTFT-R3" id="104"/>
+        <pinnumItem comment="OnTFT-R4" id="106"/>
+        <pinnumItem comment="ET-ET0ETXD0_RMII0TXD0" id="80"/>
+        <pinnumItem comment="OnTFT-R5" id="107"/>
+        <pinnumItem comment="ET-ET0TXEN_RMII0TXDEN" id="81"/>
+        <pinnumItem comment="OnTFT-R6" id="108"/>
+        <pinnumItem comment="ET-ET0TXCLK" id="82"/>
+        <pinnumItem comment="OnTFT-R7" id="109"/>
+        <pinnumItem comment="ET-ET0RXER_RMII0RXER" id="84"/>
+        <pinnumItem comment="ET-ET0RXCLK_REF50CK0" id="85"/>
+        <pinnumItem comment="ET-ET0RXDV" id="86"/>
+        <pinnumItem comment="ET-ET0ERXD0_RMII0RXD0" id="87"/>
+    </tool>
+    <tool id="SWComponent" version="1.0.0.0">
+        <configuration inuse="true" name="r_bsp">
+            <component description="Dependencies : None&#10;The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder contains files that are common to a MCU group. These files provide functionality such as easy register access, CPU functions, and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each supported board.  Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which board they are using by uncommenting the include path that applies to their board. For example, if you are using the RSK+RX64M then you would uncomment the #include &quot;./board/generic_rx64m/r_bsp.h&quot; include path. Users are encouraged to add their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it to r_bsp_config.h, and use the options inside the file to configure the BSP for their project." detailDescription="Board Support Packages." display="r_bsp" id="r_bsp5.61" version="5.61">
+                <gridItem id="BSP_CFG_STARTUP_DISABLE" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_USER_STACK_ENABLE" selectedIndex="1"/>
+                <gridItem id="BSP_CFG_USTACK_BYTES" selectedIndex="0x1000"/>
+                <gridItem id="BSP_CFG_ISTACK_BYTES" selectedIndex="0x400"/>
+                <gridItem id="BSP_CFG_HEAP_BYTES" selectedIndex="0x400"/>
+                <gridItem id="BSP_CFG_IO_LIB_ENABLE" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_USER_CHARGET_ENABLED" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_USER_CHARGET_FUNCTION" selectedIndex="my_sw_charget_function"/>
+                <gridItem id="BSP_CFG_USER_CHARPUT_ENABLED" selectedIndex="1"/>
+                <gridItem id="BSP_CFG_USER_CHARPUT_FUNCTION" selectedIndex="my_sw_charput_function"/>
+                <gridItem id="BSP_CFG_RUN_IN_USER_MODE" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_ID_CODE_LONG_1" selectedIndex="0xFFFFFFFF"/>
+                <gridItem id="BSP_CFG_ID_CODE_LONG_2" selectedIndex="0xFFFFFFFF"/>
+                <gridItem id="BSP_CFG_ID_CODE_LONG_3" selectedIndex="0xFFFFFFFF"/>
+                <gridItem id="BSP_CFG_ID_CODE_LONG_4" selectedIndex="0xFFFFFFFF"/>
+                <gridItem id="BSP_CFG_ROM_CACHE_ENABLE" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_TRUSTED_MODE_FUNCTION" selectedIndex="0xFFFFFFFF"/>
+                <gridItem id="BSP_CFG_FAW_REG_VALUE" selectedIndex="0xFFFFFFFF"/>
+                <gridItem id="BSP_CFG_ROMCODE_REG_VALUE" selectedIndex="0xFFFFFFFF"/>
+                <gridItem id="BSP_CFG_CODE_FLASH_BANK_MODE" selectedIndex="1"/>
+                <gridItem id="BSP_CFG_CODE_FLASH_START_BANK" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_USER_LOCKING_ENABLED" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_USER_LOCKING_TYPE" selectedIndex="bsp_lock_t"/>
+                <gridItem id="BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION" selectedIndex="my_hw_locking_function"/>
+                <gridItem id="BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION" selectedIndex="my_hw_unlocking_function"/>
+                <gridItem id="BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION" selectedIndex="my_sw_locking_function"/>
+                <gridItem id="BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION" selectedIndex="my_sw_unlocking_function"/>
+                <gridItem id="BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_USER_WARM_START_PRE_C_FUNCTION" selectedIndex="my_sw_warmstart_prec_function"/>
+                <gridItem id="BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_USER_WARM_START_POST_C_FUNCTION" selectedIndex="my_sw_warmstart_postc_function"/>
+                <gridItem id="BSP_CFG_PARAM_CHECKING_ENABLE" selectedIndex="1"/>
+                <gridItem id="BSP_CFG_EBMAPCR_1ST_PRIORITY" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_EBMAPCR_2ND_PRIORITY" selectedIndex="3"/>
+                <gridItem id="BSP_CFG_EBMAPCR_3RD_PRIORITY" selectedIndex="1"/>
+                <gridItem id="BSP_CFG_EBMAPCR_4TH_PRIORITY" selectedIndex="2"/>
+                <gridItem id="BSP_CFG_EBMAPCR_5TH_PRIORITY" selectedIndex="4"/>
+                <gridItem id="BSP_CFG_FIT_IPL_MAX" selectedIndex="15"/>
+                <gridItem id="BSP_CFG_SWINT_UNIT1_ENABLE" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_SWINT_UNIT2_ENABLE" selectedIndex="0"/>
+                <gridItem id="BSP_CFG_SWINT_TASK_BUFFER_NUMBER" selectedIndex="8"/>
+                <gridItem id="BSP_CFG_SWINT_IPR_INITIAL_VALUE" selectedIndex="1"/>
+            </component>
+            <source description="Components supporting Firmware Integration Technology" display="Firmware Integration Technology" id="com.renesas.smc.tools.swcomponent.fit.source"/>
+            <source description="Components supporting Firmware Integration Technology" display="Firmware Integration Technology" id="com.renesas.smc.tools.swcomponent.fit.source"/>
+        </configuration>
+        <configuration inuse="true" name="r_cmt_rx">
+            <component description="Dependency : r_bsp version(s) 5.52&#10;This module creates a timer tick using a CMT channel based on a frequency input by the user." detailDescription="Simple CMT driver for creating timer tick." display="r_cmt_rx" id="r_cmt_rx4.70" version="4.70">
+                <gridItem id="CMT_RX_CFG_IPR" selectedIndex="5"/>
+            </component>
+            <source description="Components supporting Firmware Integration Technology" display="Firmware Integration Technology" id="com.renesas.smc.tools.swcomponent.fit.source"/>
+            <source description="Components supporting Firmware Integration Technology" display="Firmware Integration Technology" id="com.renesas.smc.tools.swcomponent.fit.source"/>
+        </configuration>
+        <configuration id="90b40387-372b-486f-8ce7-3618e7b05c91" inuse="true" name="Config_SCI8">
+            <allocatable id="SCI8">
+                <isocket id="CountingClockB" selection="Clock.tool_clock_pclkb" value="6.0E7"/>
+                <option enabled="true" id="BitEdge" selection="LowLevel">
+                    <item id="LowLevel" input="" vlaue="0"/>
+                    <item id="FallEdge" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="DataLength" selection="8Bits">
+                    <item id="9Bits" input="" vlaue="0"/>
+                    <item id="8Bits" input="" vlaue="0"/>
+                    <item id="7Bits" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="Parity" selection="None">
+                    <item id="None" input="" vlaue="0"/>
+                    <item id="Even" input="" vlaue="0"/>
+                    <item id="Odd" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="StopBit" selection="1Bit">
+                    <item id="1Bit" input="" vlaue="0"/>
+                    <item id="2Bits" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="TransDir" selection="LSB">
+                    <item id="LSB" input="" vlaue="0"/>
+                    <item id="MSB" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="TransClock" selection="Internal">
+                    <item id="Internal" input="" vlaue="0"/>
+                    <item id="External" input="" vlaue="0"/>
+                </option>
+                <option enabled="false" id="BaseClk" selection="16Cyl">
+                    <item id="16Cyl" input="" vlaue="0"/>
+                    <item id="8Cyl" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="Bitrate" selection="FreeValue">
+                    <item id="FreeValue" input="115200" vlaue="9600"/>
+                    <item id="9600" input="9600" vlaue="0"/>
+                    <item id="19200" input="19200" vlaue="0"/>
+                    <item id="31250" input="31250" vlaue="0"/>
+                    <item id="38400" input="38400" vlaue="0"/>
+                    <item id="75000" input="75000" vlaue="0"/>
+                    <item id="150000" input="150000" vlaue="0"/>
+                    <item id="325000" input="325000" vlaue="0"/>
+                    <item id="375000" input="375000" vlaue="0"/>
+                </option>
+                <option enabled="true" id="DutyCorrection" selection="Disable">
+                    <item id="Enable" input="" vlaue="0"/>
+                    <item id="Disable" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="SCKPinFun" selection="SckUnuse">
+                    <item id="SckUnuse" input="" vlaue="0"/>
+                    <item id="ClkOut" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="NoiseFilt" selection="Disable">
+                    <item id="Enable" input="" vlaue="0"/>
+                    <item id="Disable" input="" vlaue="0"/>
+                </option>
+                <option enabled="false" id="FiltClk" selection="Div1">
+                    <item id="Div1" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="FlowControl" selection="None">
+                    <item id="None" input="" vlaue="0"/>
+                    <item id="CTS" input="" vlaue="0"/>
+                    <item id="RTS" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="TransDataHandle" selection="ISR">
+                    <item id="ISR" input="" vlaue="0"/>
+                    <item id="DMAC" input="" vlaue="0"/>
+                    <item id="DTC" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="RecvDataHandle" selection="ISR">
+                    <item id="ISR" input="" vlaue="0"/>
+                    <item id="DMAC" input="" vlaue="0"/>
+                    <item id="DTC" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="TXIPriority" selection="Level15">
+                    <item id="Level0" input="" vlaue="0"/>
+                    <item id="Level1" input="" vlaue="0"/>
+                    <item id="Level2" input="" vlaue="0"/>
+                    <item id="Level3" input="" vlaue="0"/>
+                    <item id="Level4" input="" vlaue="0"/>
+                    <item id="Level5" input="" vlaue="0"/>
+                    <item id="Level6" input="" vlaue="0"/>
+                    <item id="Level7" input="" vlaue="0"/>
+                    <item id="Level8" input="" vlaue="0"/>
+                    <item id="Level9" input="" vlaue="0"/>
+                    <item id="Level10" input="" vlaue="0"/>
+                    <item id="Level11" input="" vlaue="0"/>
+                    <item id="Level12" input="" vlaue="0"/>
+                    <item id="Level13" input="" vlaue="0"/>
+                    <item id="Level14" input="" vlaue="0"/>
+                    <item id="Level15" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="RXIPriority" selection="Level15">
+                    <item id="Level0" input="" vlaue="0"/>
+                    <item id="Level1" input="" vlaue="0"/>
+                    <item id="Level2" input="" vlaue="0"/>
+                    <item id="Level3" input="" vlaue="0"/>
+                    <item id="Level4" input="" vlaue="0"/>
+                    <item id="Level5" input="" vlaue="0"/>
+                    <item id="Level6" input="" vlaue="0"/>
+                    <item id="Level7" input="" vlaue="0"/>
+                    <item id="Level8" input="" vlaue="0"/>
+                    <item id="Level9" input="" vlaue="0"/>
+                    <item id="Level10" input="" vlaue="0"/>
+                    <item id="Level11" input="" vlaue="0"/>
+                    <item id="Level12" input="" vlaue="0"/>
+                    <item id="Level13" input="" vlaue="0"/>
+                    <item id="Level14" input="" vlaue="0"/>
+                    <item id="Level15" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="ERIEnable" selection="Enable">
+                    <item id="Enable" input="" vlaue="0"/>
+                    <item id="Disable" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="ERIPriority" selection="Level15">
+                    <item id="Level0" input="" vlaue="0"/>
+                    <item id="Level1" input="" vlaue="0"/>
+                    <item id="Level2" input="" vlaue="0"/>
+                    <item id="Level3" input="" vlaue="0"/>
+                    <item id="Level4" input="" vlaue="0"/>
+                    <item id="Level5" input="" vlaue="0"/>
+                    <item id="Level6" input="" vlaue="0"/>
+                    <item id="Level7" input="" vlaue="0"/>
+                    <item id="Level8" input="" vlaue="0"/>
+                    <item id="Level9" input="" vlaue="0"/>
+                    <item id="Level10" input="" vlaue="0"/>
+                    <item id="Level11" input="" vlaue="0"/>
+                    <item id="Level12" input="" vlaue="0"/>
+                    <item id="Level13" input="" vlaue="0"/>
+                    <item id="Level14" input="" vlaue="0"/>
+                    <item id="Level15" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="TransEnd" selection="Enable">
+                    <item id="Enable" input="" vlaue="0"/>
+                    <item id="Disable" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="RecvEnd" selection="Enable">
+                    <item id="Enable" input="" vlaue="0"/>
+                    <item id="Disable" input="" vlaue="0"/>
+                </option>
+                <option enabled="true" id="RecvError" selection="Enable">
+                    <item id="Enable" input="" vlaue="0"/>
+                    <item id="Disable" input="" vlaue="0"/>
+                </option>
+            </allocatable>
+            <component description="This software component provides configurations for SCI(SCIF) single(multi-processor) asynchronous mode." detailDescription="" display="SCI/SCIF Asynchronous Mode" id="com.renesas.smc.tools.swcomponent.codegenerator.sciasyncmode" version="1.9.1"/>
+            <allocator channelLevel0="8" channelLevel1="" channelLevel2="" channelLevel3="" channelLevel4="" channelLevel5="" description="SCI channel 8" display="SCI8" id="com.renesas.smc.tools.swcomponent.codegenerator.sciasync.rx651.sci8" type="">
+                <context>
+                    <option enabled="true" id="Mode" selection="BothMode">
+                        <item enabled="true" id="TransMode"/>
+                        <item enabled="true" id="RecvMode"/>
+                        <item enabled="true" id="BothMode"/>
+                        <item enabled="true" id="MultiTransMode"/>
+                        <item enabled="true" id="MultiRecvMode"/>
+                        <item enabled="true" id="MultiBothMode"/>
+                    </option>
+                </context>
+            </allocator>
+            <source description="Code generator components provide peripheral drivers with customized generated source geared towards small code size" display="Code Generator" id="com.renesas.smc.tools.swcomponent.codegenerator.source"/>
+        </configuration>
+        <configuration inuse="true" name="r_ether_rx">
+            <component description="Dependency : r_bsp version(s) 5.52&#10;The Ethernet fit module provides a method to send and receive Ethernet / IEEE802.3 frame using Ethernet controller (ETHERC), Ethernet DMA controller (EDMAC)." detailDescription="Ethernet Driver." display="r_ether_rx" id="r_ether_rx1.21" version="1.21">
+                <gridItem id="CLKOUT25M" selectedIndex="0"/>
+                <gridItem id="ET0_TX_CLK" selectedIndex="1"/>
+                <gridItem id="ET0_RX_CLK" selectedIndex="1"/>
+                <gridItem id="ET0_TX_EN" selectedIndex="1"/>
+                <gridItem id="ET0_ETXD3" selectedIndex="1"/>
+                <gridItem id="ET0_ETXD2" selectedIndex="1"/>
+                <gridItem id="ET0_ETXD1" selectedIndex="1"/>
+                <gridItem id="ET0_ETXD0" selectedIndex="1"/>
+                <gridItem id="ET0_TX_ER" selectedIndex="0"/>
+                <gridItem id="ET0_RX_DV" selectedIndex="1"/>
+                <gridItem id="ET0_ERXD3" selectedIndex="1"/>
+                <gridItem id="ET0_ERXD2" selectedIndex="1"/>
+                <gridItem id="ET0_ERXD1" selectedIndex="1"/>
+                <gridItem id="ET0_ERXD0" selectedIndex="1"/>
+                <gridItem id="ET0_RX_ER" selectedIndex="1"/>
+                <gridItem id="ET0_CRS" selectedIndex="1"/>
+                <gridItem id="ET0_COL" selectedIndex="1"/>
+                <gridItem id="ET0_MDC" selectedIndex="1"/>
+                <gridItem id="ET0_MDIO" selectedIndex="1"/>
+                <gridItem id="PMGI0_MDC" selectedIndex="0"/>
+                <gridItem id="PMGI0_MDIO" selectedIndex="0"/>
+                <gridItem id="ET0_LINKSTA" selectedIndex="1"/>
+                <gridItem id="ET0_EXOUT" selectedIndex="0"/>
+                <gridItem id="ET0_WOL" selectedIndex="0"/>
+                <gridItem id="ETHERC0_MII" selectedIndex="1"/>
+                <gridItem id="CLKOUT25M" selectedIndex="0"/>
+                <gridItem id="REF50CK0" selectedIndex="0"/>
+                <gridItem id="RMII0_TXD_EN" selectedIndex="0"/>
+                <gridItem id="RMII0_TXD1" selectedIndex="0"/>
+                <gridItem id="RMII0_TXD0" selectedIndex="0"/>
+                <gridItem id="RMII0_RXD1" selectedIndex="0"/>
+                <gridItem id="RMII0_RXD0" selectedIndex="0"/>
+                <gridItem id="RMII0_RX_ER" selectedIndex="0"/>
+                <gridItem id="RMII0_CRS_DV" selectedIndex="0"/>
+                <gridItem id="ET0_MDC" selectedIndex="1"/>
+                <gridItem id="ET0_MDIO" selectedIndex="1"/>
+                <gridItem id="PMGI0_MDC" selectedIndex="0"/>
+                <gridItem id="PMGI0_MDIO" selectedIndex="0"/>
+                <gridItem id="ET0_LINKSTA" selectedIndex="1"/>
+                <gridItem id="ET0_EXOUT" selectedIndex="0"/>
+                <gridItem id="ET0_WOL" selectedIndex="0"/>
+                <gridItem id="ETHERC0_RMII" selectedIndex="1"/>
+                <gridItem id="CLKOUT25M" selectedIndex="0"/>
+                <gridItem id="ET1_TX_CLK" selectedIndex="0"/>
+                <gridItem id="ET1_RX_CLK" selectedIndex="0"/>
+                <gridItem id="ET1_TX_EN" selectedIndex="0"/>
+                <gridItem id="ET1_ETXD3" selectedIndex="0"/>
+                <gridItem id="ET1_ETXD2" selectedIndex="0"/>
+                <gridItem id="ET1_ETXD1" selectedIndex="0"/>
+                <gridItem id="ET1_ETXD0" selectedIndex="0"/>
+                <gridItem id="ET1_TX_ER" selectedIndex="0"/>
+                <gridItem id="ET1_RX_DV" selectedIndex="0"/>
+                <gridItem id="ET1_ERXD3" selectedIndex="0"/>
+                <gridItem id="ET1_ERXD2" selectedIndex="0"/>
+                <gridItem id="ET1_ERXD1" selectedIndex="0"/>
+                <gridItem id="ET1_ERXD0" selectedIndex="0"/>
+                <gridItem id="ET1_RX_ER" selectedIndex="0"/>
+                <gridItem id="ET1_CRS" selectedIndex="0"/>
+                <gridItem id="ET1_COL" selectedIndex="0"/>
+                <gridItem id="ET1_MDC" selectedIndex="0"/>
+                <gridItem id="ET1_MDIO" selectedIndex="0"/>
+                <gridItem id="PMGI1_MDC" selectedIndex="0"/>
+                <gridItem id="PMGI1_MDIO" selectedIndex="0"/>
+                <gridItem id="ET1_LINKSTA" selectedIndex="0"/>
+                <gridItem id="ET1_EXOUT" selectedIndex="0"/>
+                <gridItem id="ET1_WOL" selectedIndex="0"/>
+                <gridItem id="ETHERC1_MII" selectedIndex="0"/>
+                <gridItem id="CLKOUT25M" selectedIndex="0"/>
+                <gridItem id="REF50CK1" selectedIndex="0"/>
+                <gridItem id="RMII1_TXD_EN" selectedIndex="0"/>
+                <gridItem id="RMII1_TXD1" selectedIndex="0"/>
+                <gridItem id="RMII1_TXD0" selectedIndex="0"/>
+                <gridItem id="RMII1_RXD1" selectedIndex="0"/>
+                <gridItem id="RMII1_RXD0" selectedIndex="0"/>
+                <gridItem id="RMII1_RX_ER" selectedIndex="0"/>
+                <gridItem id="RMII1_CRS_DV" selectedIndex="0"/>
+                <gridItem id="ET1_MDC" selectedIndex="0"/>
+                <gridItem id="ET1_MDIO" selectedIndex="0"/>
+                <gridItem id="PMGI1_MDC" selectedIndex="0"/>
+                <gridItem id="PMGI1_MDIO" selectedIndex="0"/>
+                <gridItem id="ET1_LINKSTA" selectedIndex="0"/>
+                <gridItem id="ET1_EXOUT" selectedIndex="0"/>
+                <gridItem id="ET1_WOL" selectedIndex="0"/>
+                <gridItem id="ETHERC1_RMII" selectedIndex="0"/>
+                <gridItem id="ETHER_CFG_MODE_SEL" selectedIndex="0"/>
+                <gridItem id="ETHER_CFG_CH0_PHY_ADDRESS" selectedIndex="30"/>
+                <gridItem id="ETHER_CFG_CH1_PHY_ADDRESS" selectedIndex="1"/>
+                <gridItem id="ETHER_CFG_EMAC_RX_DESCRIPTORS" selectedIndex="8"/>
+                <gridItem id="ETHER_CFG_EMAC_TX_DESCRIPTORS" selectedIndex="8"/>
+                <gridItem id="ETHER_CFG_BUFSIZE" selectedIndex="1536"/>
+                <gridItem id="ETHER_CFG_AL1_INT_PRIORTY" selectedIndex="1"/>
+                <gridItem id="ETHER_CFG_CH0_PHY_ACCESS" selectedIndex="0"/>
+                <gridItem id="ETHER_CFG_CH1_PHY_ACCESS" selectedIndex="1"/>
+                <gridItem id="ETHER_CFG_PHY_MII_WAIT" selectedIndex="8"/>
+                <gridItem id="ETHER_CFG_PHY_DELAY_RESET" selectedIndex="0x00020000L"/>
+                <gridItem id="ETHER_CFG_LINK_PRESENT" selectedIndex="0"/>
+                <gridItem id="ETHER_CFG_USE_LINKSTA" selectedIndex="1"/>
+                <gridItem id="ETHER_CFG_USE_PHY_KSZ8041NL" selectedIndex="0"/>
+                <gridItem id="ETHER_CFG_NON_BLOCKING" selectedIndex="0"/>
+                <gridItem id="ETHER_CFG_PMGI_CLOCK" selectedIndex="2500000"/>
+                <gridItem id="ETHER_CFG_PMGI_ENABLE_PREAMBLE" selectedIndex="0"/>
+                <gridItem id="ETHER_CFG_PMGI_HOLD_TIME" selectedIndex="0"/>
+                <gridItem id="ETHER_CFG_PMGI_CAPTURE_TIME" selectedIndex="0"/>
+                <gridItem id="ETHER_CFG_PMGI_INT_PRIORTY" selectedIndex="1"/>
+            </component>
+            <source description="Components supporting Firmware Integration Technology" display="Firmware Integration Technology" id="com.renesas.smc.tools.swcomponent.fit.source"/>
+            <source description="Components supporting Firmware Integration Technology" display="Firmware Integration Technology" id="com.renesas.smc.tools.swcomponent.fit.source"/>
+        </configuration>
+        <configuration id="770d9ff7-0292-4f8d-b3a2-42ed4b81ce10" inuse="true" name="Config_PORT">
+            <allocatable id="Port">
+                <allocatable id="PORT0_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORT1_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORT2_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORT3_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORT4_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORT5_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORT6_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORT7_Chan">
+                    <allocatable id="PORTx0_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveOut">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx1_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveDisable">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx2_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveNormal">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx3_Item">
+                        <option enabled="true" id="UseStatus" selection="Out">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Use">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveOut">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx4_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveNormal">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx5_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveNormal">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx6_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveNormal">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx7_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveNormal">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <option enabled="true" id="ApplyAll" selection="ApplyallUnuse">
+                        <item id="ApplyallUse" input="" vlaue="0"/>
+                        <item id="ApplyallUnuse" input="" vlaue="0"/>
+                    </option>
+                    <option enabled="true" id="UseStatusAll" selection="UnuseAlldisbale">
+                        <item id="UnuseAll" input="" vlaue="0"/>
+                        <item id="InAll" input="" vlaue="0"/>
+                        <item id="OutAll" input="" vlaue="0"/>
+                        <item id="UnuseAlldisbale" input="" vlaue="0"/>
+                        <item id="InAlldisbale" input="" vlaue="0"/>
+                        <item id="OutAlldisbale" input="" vlaue="0"/>
+                    </option>
+                    <option enabled="false" id="PullupAll" selection="PullupUnuseAll">
+                        <item id="PullupUseAll" input="" vlaue="0"/>
+                        <item id="PullupUnuseAll" input="" vlaue="0"/>
+                        <item id="PullupAlldisable" input="" vlaue="0"/>
+                    </option>
+                    <option enabled="false" id="OpendrainAll" selection="CMOSAll">
+                        <item id="CMOSAll" input="" vlaue="0"/>
+                        <item id="NChanelAll" input="" vlaue="0"/>
+                        <item id="PChanelAll" input="" vlaue="0"/>
+                        <item id="HiZAll" input="" vlaue="0"/>
+                        <item id="OpendrainAlldisable" input="" vlaue="0"/>
+                    </option>
+                    <option enabled="false" id="Output1All" selection="Output1UnuseAll">
+                        <item id="Output1UnuseAll" input="" vlaue="0"/>
+                        <item id="Output1UseAll" input="" vlaue="0"/>
+                        <item id="Output1Alldisable" input="" vlaue="0"/>
+                    </option>
+                    <option enabled="true" id="HighdriveSelectAll" selection="HighdriveNormalAll">
+                        <item id="HighdriveNormalAll" input="" vlaue="0"/>
+                        <item id="HighdriveOutAll" input="" vlaue="0"/>
+                        <item id="HighdriveHispeedAll" input="" vlaue="0"/>
+                        <item id="HighdriveDisableAll" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORT7_Check">
+                    <option enabled="true" id="PortnEnable" selection="Enable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORT8_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORT9_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORTA_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORTB_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORTC_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORTD_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORTE_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORTF_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORTG_Chan">
+                    <allocatable id="PORTx0_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveNormal">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx1_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveNormal">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx2_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveOut">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx3_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveOut">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx4_Item">
+                        <option enabled="true" id="UseStatus" selection="Unuse">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Unuse">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveOut">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx5_Item">
+                        <option enabled="true" id="UseStatus" selection="Out">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Use">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveOut">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx6_Item">
+                        <option enabled="true" id="UseStatus" selection="Out">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Use">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveOut">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <allocatable id="PORTx7_Item">
+                        <option enabled="true" id="UseStatus" selection="Out">
+                            <item id="Unuse" input="" vlaue="0"/>
+                            <item id="In" input="" vlaue="0"/>
+                            <item id="Out" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="false" id="Output1" selection="Output1Use">
+                            <item id="Output1Unuse" input="" vlaue="0"/>
+                            <item id="Output1Use" input="" vlaue="0"/>
+                            <item id="Output1disable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Pullup" selection="PullupUnuse">
+                            <item id="PullupUse" input="" vlaue="0"/>
+                            <item id="PullupUnuse" input="" vlaue="0"/>
+                            <item id="Pullupdisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="Opendrain" selection="CMOS">
+                            <item id="CMOS" input="" vlaue="0"/>
+                            <item id="NChanel" input="" vlaue="0"/>
+                            <item id="PChanel" input="" vlaue="0"/>
+                            <item id="HiZ" input="" vlaue="0"/>
+                            <item id="Opendraindisable" input="" vlaue="0"/>
+                        </option>
+                        <option enabled="true" id="HighdriveSelect" selection="HighdriveOut">
+                            <item id="HighdriveNormal" input="" vlaue="0"/>
+                            <item id="HighdriveOut" input="" vlaue="0"/>
+                            <item id="HighdriveHispeed" input="" vlaue="0"/>
+                            <item id="HighdriveDisable" input="" vlaue="0"/>
+                        </option>
+                    </allocatable>
+                    <option enabled="true" id="ApplyAll" selection="ApplyallUnuse">
+                        <item id="ApplyallUse" input="" vlaue="0"/>
+                        <item id="ApplyallUnuse" input="" vlaue="0"/>
+                    </option>
+                    <option enabled="true" id="UseStatusAll" selection="UnuseAlldisbale">
+                        <item id="UnuseAll" input="" vlaue="0"/>
+                        <item id="InAll" input="" vlaue="0"/>
+                        <item id="OutAll" input="" vlaue="0"/>
+                        <item id="UnuseAlldisbale" input="" vlaue="0"/>
+                        <item id="InAlldisbale" input="" vlaue="0"/>
+                        <item id="OutAlldisbale" input="" vlaue="0"/>
+                    </option>
+                    <option enabled="false" id="PullupAll" selection="PullupAlldisable">
+                        <item id="PullupUseAll" input="" vlaue="0"/>
+                        <item id="PullupUnuseAll" input="" vlaue="0"/>
+                        <item id="PullupAlldisable" input="" vlaue="0"/>
+                    </option>
+                    <option enabled="false" id="OpendrainAll" selection="OpendrainAlldisable">
+                        <item id="CMOSAll" input="" vlaue="0"/>
+                        <item id="NChanelAll" input="" vlaue="0"/>
+                        <item id="PChanelAll" input="" vlaue="0"/>
+                        <item id="HiZAll" input="" vlaue="0"/>
+                        <item id="OpendrainAlldisable" input="" vlaue="0"/>
+                    </option>
+                    <option enabled="false" id="Output1All" selection="Output1Alldisable">
+                        <item id="Output1UnuseAll" input="" vlaue="0"/>
+                        <item id="Output1UseAll" input="" vlaue="0"/>
+                        <item id="Output1Alldisable" input="" vlaue="0"/>
+                    </option>
+                    <option enabled="true" id="HighdriveSelectAll" selection="HighdriveNormalAll">
+                        <item id="HighdriveNormalAll" input="" vlaue="0"/>
+                        <item id="HighdriveOutAll" input="" vlaue="0"/>
+                        <item id="HighdriveHispeedAll" input="" vlaue="0"/>
+                        <item id="HighdriveDisableAll" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORTG_Check">
+                    <option enabled="true" id="PortnEnable" selection="Enable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <allocatable id="PORTJ_Check">
+                    <option enabled="true" id="PortnEnable" selection="Disable">
+                        <item id="Enable" input="" vlaue="0"/>
+                        <item id="Disable" input="" vlaue="0"/>
+                    </option>
+                </allocatable>
+                <osocket id="PORTINFO" value=";P73_O;PG5_O;PG6_O;PG7_O;"/>
+            </allocatable>
+            <component description="This software component provides configurations for General Purpose Input/Output. Common features such as reading, writing, and setting the direction of ports and pins can be configured. Enabling features such as open-drain outputs and internal pull-ups are also supported. " detailDescription="" display="Ports" id="com.renesas.smc.tools.swcomponent.codegenerator.port" version="2.1.1"/>
+            <allocator channelLevel0="" channelLevel1="" channelLevel2="" channelLevel3="" channelLevel4="" channelLevel5="" description="Input output configuration of PORT" display="PORT" id="com.renesas.smc.tools.swcomponent.codegenerator.port.rx651.PORT" type="">
+                <context/>
+            </allocator>
+            <source description="Code generator components provide peripheral drivers with customized generated source geared towards small code size" display="Code Generator" id="com.renesas.smc.tools.swcomponent.codegenerator.source"/>
+        </configuration>
+    </tool>
+</smc>
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_PORT/Config_PORT.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_PORT/Config_PORT.c
new file mode 100644
index 00000000..43f1d458
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_PORT/Config_PORT.c
@@ -0,0 +1,82 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : Config_PORT.c
+* Version      : 2.1.1
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements device driver for Config_PORT.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "Config_PORT.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Config_PORT_Create
+* Description  : This function initializes the PORT
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Config_PORT_Create(void)
+{
+    /* Set PORT7 registers */
+    PORT7.PODR.BYTE = _08_Pm3_OUTPUT_1;
+    PORT7.ODR0.BYTE = _00_Pm0_CMOS_OUTPUT | _00_Pm1_CMOS_OUTPUT | _00_Pm2_CMOS_OUTPUT | _00_Pm3_CMOS_OUTPUT;
+    PORT7.ODR1.BYTE = _00_Pm4_CMOS_OUTPUT | _00_Pm5_CMOS_OUTPUT | _00_Pm6_CMOS_OUTPUT | _00_Pm7_CMOS_OUTPUT;
+    PORT7.DSCR.BYTE = _00_Pm2_HIDRV_OFF | _00_Pm4_HIDRV_OFF | _00_Pm5_HIDRV_OFF | _00_Pm6_HIDRV_OFF | _00_Pm7_HIDRV_OFF;
+    PORT7.DSCR2.BYTE = _00_Pm0_HISPEED_OFF | _00_Pm2_HISPEED_OFF | _00_Pm3_HISPEED_OFF | _00_Pm4_HISPEED_OFF | 
+                       _00_Pm5_HISPEED_OFF | _00_Pm6_HISPEED_OFF | _00_Pm7_HISPEED_OFF;
+    PORT7.PMR.BYTE = _00_Pm3_PIN_GPIO;
+    PORT7.PDR.BYTE = _08_Pm3_MODE_OUTPUT;
+
+    /* Set PORTG registers */
+    PORTG.PODR.BYTE = _20_Pm5_OUTPUT_1 | _40_Pm6_OUTPUT_1 | _80_Pm7_OUTPUT_1;
+    PORTG.ODR0.BYTE = _00_Pm0_CMOS_OUTPUT | _00_Pm1_CMOS_OUTPUT | _00_Pm2_CMOS_OUTPUT | _00_Pm3_CMOS_OUTPUT;
+    PORTG.ODR1.BYTE = _00_Pm4_CMOS_OUTPUT | _00_Pm5_CMOS_OUTPUT | _00_Pm6_CMOS_OUTPUT | _00_Pm7_CMOS_OUTPUT;
+    PORTG.DSCR.BYTE = _00_Pm0_HIDRV_OFF | _00_Pm1_HIDRV_OFF;
+    PORTG.DSCR2.BYTE = _00_Pm0_HISPEED_OFF | _00_Pm1_HISPEED_OFF | _00_Pm2_HISPEED_OFF | _00_Pm3_HISPEED_OFF | 
+                       _00_Pm4_HISPEED_OFF | _00_Pm5_HISPEED_OFF | _00_Pm6_HISPEED_OFF | _00_Pm7_HISPEED_OFF;
+    PORTG.PMR.BYTE = _00_Pm5_PIN_GPIO | _00_Pm6_PIN_GPIO | _00_Pm7_PIN_GPIO;
+    PORTG.PDR.BYTE = _20_Pm5_MODE_OUTPUT | _40_Pm6_MODE_OUTPUT | _80_Pm7_MODE_OUTPUT;
+
+    R_Config_PORT_Create_UserInit();
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_PORT/Config_PORT.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_PORT/Config_PORT.h
new file mode 100644
index 00000000..5a06fbee
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_PORT/Config_PORT.h
@@ -0,0 +1,55 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : Config_PORT.h
+* Version      : 2.1.1
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements device driver for Config_PORT.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef CFG_Config_PORT_H
+#define CFG_Config_PORT_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_port.h"
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Config_PORT_Create(void);
+void R_Config_PORT_Create_UserInit(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_PORT/Config_PORT_user.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_PORT/Config_PORT_user.c
new file mode 100644
index 00000000..e2f6e9b3
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_PORT/Config_PORT_user.c
@@ -0,0 +1,63 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : Config_PORT_user.c
+* Version      : 2.1.1
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements device driver for Config_PORT.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "Config_PORT.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Config_PORT_Create_UserInit
+* Description  : This function adds user code after initializing PORT
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Config_PORT_Create_UserInit(void)
+{
+    /* Start user code for user init. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_SCI8/Config_SCI8.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_SCI8/Config_SCI8.c
new file mode 100644
index 00000000..48fb65e1
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_SCI8/Config_SCI8.c
@@ -0,0 +1,216 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : Config_SCI8.c
+* Version      : 1.9.1
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements device driver for Config_SCI8.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "Config_SCI8.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+volatile uint8_t * gp_sci8_tx_address;                /* SCI8 transmit buffer address */
+volatile uint16_t  g_sci8_tx_count;                   /* SCI8 transmit data number */
+volatile uint8_t * gp_sci8_rx_address;                /* SCI8 receive buffer address */
+volatile uint16_t  g_sci8_rx_count;                   /* SCI8 receive data number */
+volatile uint16_t  g_sci8_rx_length;                  /* SCI8 receive data length */
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Config_SCI8_Create
+* Description  : This function initializes the SCI8 channel
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Config_SCI8_Create(void)
+{
+    /* Cancel SCI stop state */
+    MSTP(SCI8) = 0U;
+
+    /* Set interrupt priority */
+    IPR(SCI8, RXI8) = _0F_SCI_PRIORITY_LEVEL15;
+    IPR(SCI8, TXI8) = _0F_SCI_PRIORITY_LEVEL15;
+
+    /* Clear the control register */
+    SCI8.SCR.BYTE = 0x00U;
+
+    /* Set clock enable */
+    SCI8.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED;
+
+    /* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit, and set SPMR */
+    SCI8.SIMR1.BIT.IICM = 0U;
+    SCI8.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED;
+
+    /* Set control registers */
+    SCI8.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_STOP_1 | _00_SCI_PARITY_DISABLE | 
+                    _00_SCI_DATA_LENGTH_8 | _00_SCI_ASYNCHRONOUS_OR_I2C_MODE;
+    SCI8.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | 
+                     _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT;
+    SCI8.SEMR.BYTE = _00_SCI_BIT_MODULATION_DISABLE | _10_SCI_8_BASE_CLOCK | _00_SCI_NOISE_FILTER_DISABLE | 
+                     _40_SCI_BAUDRATE_DOUBLE | _00_SCI_LOW_LEVEL_START_BIT;
+
+    /* Set bit rate */
+    SCI8.BRR = 0x40U;
+
+    /* Set RXD8 pin */
+    MPC.PJ1PFS.BYTE = 0x0AU;
+    PORTJ.PMR.BYTE |= 0x02U;
+
+    /* Set TXD8 pin */
+    MPC.PJ2PFS.BYTE = 0x0AU;
+    PORTJ.PODR.BYTE |= 0x04U;
+    PORTJ.PDR.BYTE |= 0x04U;
+
+    R_Config_SCI8_Create_UserInit();
+}
+
+/***********************************************************************************************************************
+* Function Name: R_Config_SCI8_Start
+* Description  : This function starts the SCI8 channel
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Config_SCI8_Start(void)
+{
+    /* Clear interrupt flag */
+    IR(SCI8, TXI8) = 0U;
+    IR(SCI8, RXI8) = 0U;
+
+    /* Enable SCI interrupt */
+    IEN(SCI8, TXI8) = 1U;
+    ICU.GENBL1.BIT.EN24 = 1U;
+    IEN(SCI8, RXI8) = 1U;
+    ICU.GENBL1.BIT.EN25 = 1U;
+}
+
+/***********************************************************************************************************************
+* Function Name: R_Config_SCI8_Stop
+* Description  : This function stop the SCI8 channel
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Config_SCI8_Stop(void)
+{
+    /* Set TXD8 pin */
+    PORTJ.PMR.BYTE &= 0xFBU;
+
+    /* Disable serial transmit */
+    SCI8.SCR.BIT.TE = 0U;
+
+    /* Disable serial receive */
+    SCI8.SCR.BIT.RE = 0U;
+
+    /* Disable SCI interrupt */
+    SCI8.SCR.BIT.TIE = 0U;
+    SCI8.SCR.BIT.RIE = 0U;
+    IEN(SCI8, TXI8) = 0U;
+    ICU.GENBL1.BIT.EN24 = 0U;
+    IR(SCI8, TXI8) = 0U;
+    IEN(SCI8, RXI8) = 0U;
+    ICU.GENBL1.BIT.EN25 = 0U;
+    IR(SCI8, RXI8) = 0U;
+}
+
+/***********************************************************************************************************************
+* Function Name: R_Config_SCI8_Serial_Receive
+* Description  : This function receive SCI8data
+* Arguments    : rx_buf -
+*                    receive buffer pointer (Not used when receive data handled by DMAC/DTC)
+*                rx_num -
+*                    buffer size (Not used when receive data handled by DMAC/DTC)
+* Return Value : status -
+*                    MD_OK or MD_ARGERROR
+***********************************************************************************************************************/
+
+MD_STATUS R_Config_SCI8_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num)
+{
+    MD_STATUS status = MD_OK;
+
+    if (1U > rx_num)
+    {
+        status = MD_ARGERROR;
+    }
+    else
+    {
+        g_sci8_rx_count = 0U;
+        g_sci8_rx_length = rx_num;
+        gp_sci8_rx_address = rx_buf;
+        SCI8.SCR.BIT.RIE = 1U;
+        SCI8.SCR.BIT.RE = 1U;
+    }
+
+    return (status);
+}
+
+/***********************************************************************************************************************
+* Function Name: R_Config_SCI8_Serial_Send
+* Description  : This function transmits SCI8data
+* Arguments    : tx_buf -
+*                    transfer buffer pointer (Not used when transmit data handled by DMAC/DTC)
+*                tx_num -
+*                    buffer size (Not used when transmit data handled by DMAC/DTC)
+* Return Value : status -
+*                    MD_OK or MD_ARGERROR
+***********************************************************************************************************************/
+
+MD_STATUS R_Config_SCI8_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num)
+{
+    MD_STATUS status = MD_OK;
+
+    if (1U > tx_num)
+    {
+        status = MD_ARGERROR;
+    }
+    else
+    {
+        gp_sci8_tx_address = tx_buf;
+        g_sci8_tx_count = tx_num;
+
+        /* Set TXD8 pin */
+        PORTJ.PMR.BYTE |= 0x04U;
+        SCI8.SCR.BYTE |= 0xA0U;
+    }
+
+    return (status);
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_SCI8/Config_SCI8.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_SCI8/Config_SCI8.h
new file mode 100644
index 00000000..a5db1520
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_SCI8/Config_SCI8.h
@@ -0,0 +1,64 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : Config_SCI8.h
+* Version      : 1.9.1
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements device driver for Config_SCI8.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef CFG_Config_SCI8_H
+#define CFG_Config_SCI8_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_sci.h"
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Config_SCI8_Create(void);
+void R_Config_SCI8_Start(void);
+void R_Config_SCI8_Stop(void);
+void R_Config_SCI8_Create_UserInit(void);
+MD_STATUS R_Config_SCI8_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num);
+MD_STATUS R_Config_SCI8_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num);
+void r_Config_SCI8_transmitend_interrupt(void);
+static void r_Config_SCI8_callback_transmitend(void);
+static void r_Config_SCI8_callback_receiveend(void);
+void r_Config_SCI8_receiveerror_interrupt(void);
+static void r_Config_SCI8_callback_receiveerror(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_SCI8/Config_SCI8_user.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_SCI8/Config_SCI8_user.c
new file mode 100644
index 00000000..0d74ff8f
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/Config_SCI8/Config_SCI8_user.c
@@ -0,0 +1,197 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : Config_SCI8_user.c
+* Version      : 1.9.1
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements device driver for Config_SCI8.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "Config_SCI8.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+extern volatile uint8_t * gp_sci8_tx_address;                /* SCI8 transmit buffer address */
+extern volatile uint16_t  g_sci8_tx_count;                   /* SCI8 transmit data number */
+extern volatile uint8_t * gp_sci8_rx_address;                /* SCI8 receive buffer address */
+extern volatile uint16_t  g_sci8_rx_count;                   /* SCI8 receive data number */
+extern volatile uint16_t  g_sci8_rx_length;                  /* SCI8 receive data length */
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Config_SCI8_Create_UserInit
+* Description  : This function adds user code after initializing the SCI8 channel
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Config_SCI8_Create_UserInit(void)
+{
+    /* Start user code for user init. Do not edit comment generated here */
+    void printf_init(void);
+    printf_init();
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_Config_SCI8_transmit_interrupt
+* Description  : This function is TXI8 interrupt service routine
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void r_Config_SCI8_transmit_interrupt(void)
+{
+    if (0U < g_sci8_tx_count)
+    {
+        SCI8.TDR = *gp_sci8_tx_address;
+        gp_sci8_tx_address++;
+        g_sci8_tx_count--;
+    }
+    else
+    {
+        SCI8.SCR.BIT.TIE = 0U;
+        SCI8.SCR.BIT.TEIE = 1U;
+    }
+}
+
+/***********************************************************************************************************************
+* Function Name: r_Config_SCI8_transmitend_interrupt
+* Description  : This function is TEI8 interrupt service routine
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void r_Config_SCI8_transmitend_interrupt(void)
+{
+    /* Set TXD8 pin */
+    PORTJ.PMR.BYTE &= 0xFBU;
+
+    SCI8.SCR.BIT.TIE = 0U;
+    SCI8.SCR.BIT.TE = 0U;
+    SCI8.SCR.BIT.TEIE = 0U;
+    
+    r_Config_SCI8_callback_transmitend();
+}
+
+/***********************************************************************************************************************
+* Function Name: r_Config_SCI8_receive_interrupt
+* Description  : This function is RXI8 interrupt service routine
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void r_Config_SCI8_receive_interrupt(void)
+{
+    if (g_sci8_rx_length > g_sci8_rx_count)
+    {
+        *gp_sci8_rx_address = SCI8.RDR;
+        gp_sci8_rx_address++;
+        g_sci8_rx_count++;
+    }
+    
+    if (g_sci8_rx_length <= g_sci8_rx_count)
+    {
+        /* All data received */
+        SCI8.SCR.BIT.RIE = 0U;
+        SCI8.SCR.BIT.RE = 0U;
+        r_Config_SCI8_callback_receiveend();
+    }
+}
+
+/***********************************************************************************************************************
+* Function Name: r_Config_SCI8_receiveerror_interrupt
+* Description  : This function is ERI8 interrupt service routine
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void r_Config_SCI8_receiveerror_interrupt(void)
+{
+    uint8_t err_type;
+    
+    r_Config_SCI8_callback_receiveerror();
+    
+    /* Clear overrun, framing and parity error flags */
+    err_type = SCI8.SSR.BYTE;
+    err_type &= 0xC7U;
+    err_type |= 0xC0U;
+    SCI8.SSR.BYTE = err_type;
+}
+
+/***********************************************************************************************************************
+* Function Name: r_Config_SCI8_callback_transmitend
+* Description  : This function is a callback function when SCI8 finishes transmission
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+static void r_Config_SCI8_callback_transmitend(void)
+{
+    /* Start user code for r_Config_SCI8_callback_transmitend. Do not edit comment generated here */
+    void printf_transmit_end(void);
+    printf_transmit_end();
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_Config_SCI8_callback_receiveend
+* Description  : This function is a callback function when SCI8 finishes reception
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+static void r_Config_SCI8_callback_receiveend(void)
+{
+    /* Start user code for r_Config_SCI8_callback_receiveend. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_Config_SCI8_callback_receiveerror
+* Description  : This function is a callback function when SCI8 reception encounters error
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+static void r_Config_SCI8_callback_receiveerror(void)
+{
+    /* Start user code for r_Config_SCI8_callback_receiveerror. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_hardware_setup.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_hardware_setup.c
new file mode 100644
index 00000000..99520fe0
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_hardware_setup.c
@@ -0,0 +1,113 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_hardware_setup.c
+* Version      : 1.2.101
+* Device(s)    : R5F565NEDxFC
+* Description  : Initialization file for code generation configurations.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "Config_SCI8.h"
+#include "Config_PORT.h"
+#include "r_smc_cgc.h"
+#include "r_smc_interrupt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: r_undefined_exception
+* Description  : This function is undefined interrupt service routine
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void r_undefined_exception(void)
+{
+    /* Start user code for r_undefined_exception. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_Systeminit
+* Description  : This function initializes every configuration
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Systeminit(void)
+{
+    /* Enable writing to registers related to operating modes, LPC, CGC and software reset */
+    SYSTEM.PRCR.WORD = 0xA50BU;
+
+    /* Enable writing to MPC pin function control registers */
+    MPC.PWPR.BIT.B0WI = 0U;
+    MPC.PWPR.BIT.PFSWE = 1U;
+
+    /* Write 0 to the target bits in the POECR2 registers */
+    POE3.POECR2.WORD = 0x0000U;
+
+    /* Initialize clocks settings */
+    R_CGC_Create();
+
+    /* Set peripheral settings */
+    R_Config_PORT_Create();
+    R_Config_SCI8_Create();
+
+    /* Set interrupt settings */
+    R_Interrupt_Create();
+
+    /* Register undefined interrupt */
+    R_BSP_InterruptWrite(BSP_INT_SRC_UNDEFINED_INTERRUPT,(bsp_int_cb_t)r_undefined_exception);
+
+    /* Register group BL1 interrupt TEI8 (SCI8) */
+    R_BSP_InterruptWrite(BSP_INT_SRC_BL1_SCI8_TEI8,(bsp_int_cb_t)r_Config_SCI8_transmitend_interrupt);
+
+    /* Register group BL1 interrupt ERI8 (SCI8) */
+    R_BSP_InterruptWrite(BSP_INT_SRC_BL1_SCI8_ERI8,(bsp_int_cb_t)r_Config_SCI8_receiveerror_interrupt);
+
+    /* Disable writing to MPC pin function control registers */
+    MPC.PWPR.BIT.PFSWE = 0U;
+    MPC.PWPR.BIT.B0WI = 1U;
+
+    /* Enable protection */
+    SYSTEM.PRCR.WORD = 0xA500U;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_interrupt_handlers.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_interrupt_handlers.h
new file mode 100644
index 00000000..a5bbe961
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_interrupt_handlers.h
@@ -0,0 +1,58 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_interrupt_handlers.h
+* Version      : 1.2.101
+* Device(s)    : R5F565NEDxFC
+* Description  : This file declares interrupt handlers.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef INTERRUPT_HANDLERS_H
+#define INTERRUPT_HANDLERS_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* SCI8 RXI8 */
+void r_Config_SCI8_receive_interrupt(void) __attribute__ ((interrupt(".rvectors",VECT(SCI8,RXI8))));
+
+/* SCI8 TXI8 */
+void r_Config_SCI8_transmit_interrupt(void) __attribute__ ((interrupt(".rvectors",VECT(SCI8,TXI8))));
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_macrodriver.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_macrodriver.h
new file mode 100644
index 00000000..3ce833b7
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_macrodriver.h
@@ -0,0 +1,85 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_macrodriver.h
+* Version      : 1.2.101
+* Device(s)    : R5F565NEDxFC
+* Description  : Macro header file for code generation.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef MACRODRIVER_H
+#define MACRODRIVER_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "platform.h"
+#include "r_smc_interrupt.h"
+#include "r_cg_interrupt_handlers.h"
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+
+/* Status list definition */
+#define MD_STATUSBASE        (0x00U)
+#define MD_OK                (MD_STATUSBASE + 0x00U) /* register setting OK */
+#define MD_SPT               (MD_STATUSBASE + 0x01U) /* IIC stop */
+#define MD_NACK              (MD_STATUSBASE + 0x02U) /* IIC no ACK */
+#define MD_BUSY1             (MD_STATUSBASE + 0x03U) /* busy 1 */
+#define MD_BUSY2             (MD_STATUSBASE + 0x04U) /* busy 2 */
+
+/* Error list definition */
+#define MD_ERRORBASE         (0x80U)
+#define MD_ERROR             (MD_ERRORBASE + 0x00U)  /* error */
+#define MD_ARGERROR          (MD_ERRORBASE + 0x01U)  /* error argument input error */
+#define MD_ERROR1            (MD_ERRORBASE + 0x02U)  /* error 1 */
+#define MD_ERROR2            (MD_ERRORBASE + 0x03U)  /* error 2 */
+#define MD_ERROR3            (MD_ERRORBASE + 0x04U)  /* error 3 */
+#define MD_ERROR4            (MD_ERRORBASE + 0x05U)  /* error 4 */
+#define MD_ERROR5            (MD_ERRORBASE + 0x06U)  /* error 5 */
+
+#define nop()                R_BSP_NOP()
+#define wait()               R_BSP_WAIT()
+
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+    typedef unsigned short      MD_STATUS;
+    #define __TYPEDEF__
+#endif
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Systeminit(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_port.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_port.h
new file mode 100644
index 00000000..ffced38c
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_port.h
@@ -0,0 +1,195 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_port.h
+* Version      : 1.2.101
+* Device(s)    : R5F565NEDxFC
+* Description  : General header file for PORT peripheral.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef PORT_H
+#define PORT_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+Port Mode Register (PMR)
+*/
+/* Pmn Pin Mode Control (B7 -B0) */
+#define _00_Pm0_PIN_GPIO        (0x00U) /* Pm0 as general I/O pin */
+#define _00_Pm1_PIN_GPIO        (0x00U) /* Pm1 as general I/O pin */
+#define _00_Pm2_PIN_GPIO        (0x00U) /* Pm2 as general I/O pin */
+#define _00_Pm3_PIN_GPIO        (0x00U) /* Pm3 as general I/O pin */
+#define _00_Pm4_PIN_GPIO        (0x00U) /* Pm4 as general I/O pin */
+#define _00_Pm5_PIN_GPIO        (0x00U) /* Pm5 as general I/O pin */
+#define _00_Pm6_PIN_GPIO        (0x00U) /* Pm6 as general I/O pin */
+#define _00_Pm7_PIN_GPIO        (0x00U) /* Pm7 as general I/O pin */
+
+/*
+    Port Direction Register (PDR)
+*/
+/* Pmn Direction Control (B7 - B0) */
+#define _00_Pm0_MODE_INPUT      (0x00U) /* Pm0 as input */
+#define _01_Pm0_MODE_OUTPUT     (0x01U) /* Pm0 as output */
+#define _00_Pm1_MODE_INPUT      (0x00U) /* Pm1 as input */
+#define _02_Pm1_MODE_OUTPUT     (0x02U) /* Pm1 as output */
+#define _00_Pm2_MODE_INPUT      (0x00U) /* Pm2 as input */
+#define _04_Pm2_MODE_OUTPUT     (0x04U) /* Pm2 as output */
+#define _00_Pm3_MODE_INPUT      (0x00U) /* Pm3 as input */
+#define _08_Pm3_MODE_OUTPUT     (0x08U) /* Pm3 as output */
+#define _00_Pm4_MODE_INPUT      (0x00U) /* Pm4 as input */
+#define _10_Pm4_MODE_OUTPUT     (0x10U) /* Pm4 as output */
+#define _00_Pm5_MODE_INPUT      (0x00U) /* Pm5 as input */
+#define _20_Pm5_MODE_OUTPUT     (0x20U) /* Pm5 as output */
+#define _00_Pm6_MODE_INPUT      (0x00U) /* Pm6 as input */
+#define _40_Pm6_MODE_OUTPUT     (0x40U) /* Pm6 as output */
+#define _00_Pm7_MODE_INPUT      (0x00U) /* Pm7 as input */
+#define _80_Pm7_MODE_OUTPUT     (0x80U) /* Pm7 as output */
+#define _50_PDR0_DEFAULT        (0x50U) /* PDR0 default value */
+#define _C0_PDRF_DEFAULT        (0xC0U) /* PDRF default value */
+#define _D0_PDRJ_DEFAULT        (0xD0U) /* PDRJ default value */
+
+/*
+    Port Output Data Register (PODR)
+*/
+/* Pmn Output Data Store (B7 - B0) */
+#define _00_Pm0_OUTPUT_0        (0x00U) /* output low at B0 */
+#define _01_Pm0_OUTPUT_1        (0x01U) /* output high at B0 */
+#define _00_Pm1_OUTPUT_0        (0x00U) /* output low at B1 */
+#define _02_Pm1_OUTPUT_1        (0x02U) /* output high at B1 */
+#define _00_Pm2_OUTPUT_0        (0x00U) /* output low at B2 */
+#define _04_Pm2_OUTPUT_1        (0x04U) /* output high at B2 */
+#define _00_Pm3_OUTPUT_0        (0x00U) /* output low at B3 */
+#define _08_Pm3_OUTPUT_1        (0x08U) /* output high at B3 */
+#define _00_Pm4_OUTPUT_0        (0x00U) /* output low at B4 */
+#define _10_Pm4_OUTPUT_1        (0x10U) /* output high at B4 */
+#define _00_Pm5_OUTPUT_0        (0x00U) /* output low at B5 */
+#define _20_Pm5_OUTPUT_1        (0x20U) /* output high at B5 */
+#define _00_Pm6_OUTPUT_0        (0x00U) /* output low at B6 */
+#define _40_Pm6_OUTPUT_1        (0x40U) /* output high at B6 */
+#define _00_Pm7_OUTPUT_0        (0x00U) /* output low at B7 */
+#define _80_Pm7_OUTPUT_1        (0x80U) /* output high at B7 */
+
+/*
+    Open Drain Control Register 0 (ODR0)
+*/
+/* Pmn Output Type Select (Pm0 to Pm3) */
+#define _00_Pm0_CMOS_OUTPUT     (0x00U) /* CMOS output */
+#define _01_Pm0_NCH_OPEN_DRAIN  (0x01U) /* N-channel open-drain output */
+#define _00_Pm1_CMOS_OUTPUT     (0x00U) /* CMOS output */
+#define _04_Pm1_NCH_OPEN_DRAIN  (0x04U) /* N-channel open-drain output */
+#define _08_Pm1_PCH_OPEN_DRAIN  (0x08U) /* P-channel open-drain output, for PE1 only*/
+#define _00_Pm2_CMOS_OUTPUT     (0x00U) /* CMOS output */
+#define _10_Pm2_NCH_OPEN_DRAIN  (0x10U) /* N-channel open-drain output */
+#define _00_Pm3_CMOS_OUTPUT     (0x00U) /* CMOS output */
+#define _40_Pm3_NCH_OPEN_DRAIN  (0x40U) /* N-channel open-drain output */
+
+/*
+    Open Drain Control Register 1 (ODR1)
+*/
+/* Pmn Output Type Select (Pm4 to Pm7) */
+#define _00_Pm4_CMOS_OUTPUT     (0x00U) /* CMOS output */
+#define _01_Pm4_NCH_OPEN_DRAIN  (0x01U) /* N-channel open-drain output */
+#define _00_Pm5_CMOS_OUTPUT     (0x00U) /* CMOS output */
+#define _04_Pm5_NCH_OPEN_DRAIN  (0x04U) /* N-channel open-drain output */
+#define _00_Pm6_CMOS_OUTPUT     (0x00U) /* CMOS output */
+#define _10_Pm6_NCH_OPEN_DRAIN  (0x10U) /* N-channel open-drain output */
+#define _00_Pm7_CMOS_OUTPUT     (0x00U) /* CMOS output */
+#define _40_Pm7_NCH_OPEN_DRAIN  (0x40U) /* N-channel open-drain output */
+
+/*
+    Pull-Up Control Register (PCR)
+*/
+/* Pmn Input Pull-Up Resistor Control (B7 - B0) */
+#define _00_Pm0_PULLUP_OFF      (0x00U) /* Pn0 pull-up resistor not connected */
+#define _01_Pm0_PULLUP_ON       (0x01U) /* Pn0 pull-up resistor connected */
+#define _00_Pm1_PULLUP_OFF      (0x00U) /* Pn1 pull-up resistor not connected */
+#define _02_Pm1_PULLUP_ON       (0x02U) /* Pn1 pull-up resistor connected */
+#define _00_Pm2_PULLUP_OFF      (0x00U) /* Pn2 Pull-up resistor not connected */
+#define _04_Pm2_PULLUP_ON       (0x04U) /* Pn2 pull-up resistor connected */
+#define _00_Pm3_PULLUP_OFF      (0x00U) /* Pn3 pull-up resistor not connected */
+#define _08_Pm3_PULLUP_ON       (0x08U) /* Pn3 pull-up resistor connected */
+#define _00_Pm4_PULLUP_OFF      (0x00U) /* Pn4 pull-up resistor not connected */
+#define _10_Pm4_PULLUP_ON       (0x10U) /* Pn4 pull-up resistor connected */
+#define _00_Pm5_PULLUP_OFF      (0x00U) /* Pn5 pull-up resistor not connected */
+#define _20_Pm5_PULLUP_ON       (0x20U) /* Pn5 pull-up resistor connected */
+#define _00_Pm6_PULLUP_OFF      (0x00U) /* Pn6 pull-up resistor not connected */
+#define _40_Pm6_PULLUP_ON       (0x40U) /* Pn6 pull-up resistor connected */
+#define _00_Pm7_PULLUP_OFF      (0x00U) /* Pn7 pull-up resistor not connected */
+#define _80_Pm7_PULLUP_ON       (0x80U) /* Pn7 pull-up resistor connected */
+
+/*
+Drive Capacity Control Register (DSCR)
+*/
+/* Pmn Drive Capacity Control (B7 - B0) */
+#define _00_Pm0_HIDRV_OFF       (0x00U) /* Pm0 Normal drive output */
+#define _01_Pm0_HIDRV_ON        (0x01U) /* Pm0 High-drive output */
+#define _00_Pm1_HIDRV_OFF       (0x00U) /* Pm1 Normal drive output */
+#define _02_Pm1_HIDRV_ON        (0x02U) /* Pm1 High-drive output */
+#define _00_Pm2_HIDRV_OFF       (0x00U) /* Pm2 Normal drive output */
+#define _04_Pm2_HIDRV_ON        (0x04U) /* Pm2 High-drive output */
+#define _00_Pm3_HIDRV_OFF       (0x00U) /* Pm3 Normal drive output */
+#define _08_Pm3_HIDRV_ON        (0x08U) /* Pm3 High-drive output */
+#define _00_Pm4_HIDRV_OFF       (0x00U) /* Pm4 Normal drive output */
+#define _10_Pm4_HIDRV_ON        (0x10U) /* Pm4 High-drive output */
+#define _00_Pm5_HIDRV_OFF       (0x00U) /* Pm5 Normal drive output */
+#define _20_Pm5_HIDRV_ON        (0x20U) /* Pm5 High-drive output */
+#define _00_Pm6_HIDRV_OFF       (0x00U) /* Pm6 Normal drive output */
+#define _40_Pm6_HIDRV_ON        (0x40U) /* Pm6 High-drive output */
+#define _00_Pm7_HIDRV_OFF       (0x00U) /* Pm7 Normal drive output */
+#define _80_Pm7_HIDRV_ON        (0x80U) /* Pm7 High-drive output */
+
+/*
+     Drive Capacity Control Register 2 (DSCR2)
+*/
+/* Pmn Drive Capacity Control 2 (B7 - B0) */
+#define _00_Pm0_HISPEED_OFF     (0x00U) /* Pm0 Normal drive/high-drive output */
+#define _01_Pm0_HISPEED_ON      (0x01U) /* Pm0 High-speed interface high-drive output */
+#define _00_Pm1_HISPEED_OFF     (0x00U) /* Pm1 Normal drive/high-drive output */
+#define _02_Pm1_HISPEED_ON      (0x02U) /* Pm1 High-speed interface high-drive output */
+#define _00_Pm2_HISPEED_OFF     (0x00U) /* Pm2 Normal drive/high-drive output */
+#define _04_Pm2_HISPEED_ON      (0x04U) /* Pm2 High-speed interface high-drive output */
+#define _00_Pm3_HISPEED_OFF     (0x00U) /* Pm3 Normal drive/high-drive output */
+#define _08_Pm3_HISPEED_ON      (0x08U) /* Pm3 High-speed interface high-drive output */
+#define _00_Pm4_HISPEED_OFF     (0x00U) /* Pm4 Normal drive/high-drive output */
+#define _10_Pm4_HISPEED_ON      (0x10U) /* Pm4 High-speed interface high-drive output */
+#define _00_Pm5_HISPEED_OFF     (0x00U) /* Pm5 Normal drive/high-drive output */
+#define _20_Pm5_HISPEED_ON      (0x20U) /* Pm5 High-speed interface high-drive output */
+#define _00_Pm6_HISPEED_OFF     (0x00U) /* Pm6 Normal drive/high-drive output */
+#define _40_Pm6_HISPEED_ON      (0x40U) /* Pm6 High-speed interface high-drive output */
+#define _00_Pm7_HISPEED_OFF     (0x00U) /* Pm7 Normal drive/high-drive output */
+#define _80_Pm7_HISPEED_ON      (0x80U) /* Pm7 High-speed interface high-drive output */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_sci.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_sci.h
new file mode 100644
index 00000000..69fd177e
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_sci.h
@@ -0,0 +1,388 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_sci.h
+* Version      : 1.2.101
+* Device(s)    : R5F565NEDxFC
+* Description  : General header file for SCI peripheral.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef SCI_H
+#define SCI_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+    Transmit FIFO Data Register (FTDR)
+*/
+/* Transmit Multi-Processor */
+#define _FC00_SCI_DATA_TRANSMIT                   (0xFC00U) /* Data transmission cycles */
+#define _FE00_SCI_ID_TRANSMIT                     (0xFE00U) /* ID transmission cycles */
+
+/*
+    Serial Mode Register (SMR)
+*/
+/* Clock Select (CKS) */
+#define _00_SCI_CLOCK_PCLK                        (0x00U)   /* PCLK */
+#define _01_SCI_CLOCK_PCLK_4                      (0x01U)   /* PCLK/4 */
+#define _02_SCI_CLOCK_PCLK_16                     (0x02U)   /* PCLK/16 */
+#define _03_SCI_CLOCK_PCLK_64                     (0x03U)   /* PCLK/64 */
+/* Multi-Processor Mode (MP) */
+#define _00_SCI_MULTI_PROCESSOR_DISABLE           (0x00U)   /* Disable multiprocessor mode */
+#define _04_SCI_MULTI_PROCESSOR_ENABLE            (0x04U)   /* Enable multiprocessor mode */
+/* Stop Bit Length (STOP) */
+#define _00_SCI_STOP_1                            (0x00U)   /* 1 stop bit length */
+#define _08_SCI_STOP_2                            (0x08U)   /* 2 stop bits length */
+/* Parity Mode (PM) */
+#define _00_SCI_PARITY_EVEN                       (0x00U)   /* Parity even */
+#define _10_SCI_PARITY_ODD                        (0x10U)   /* Parity odd */
+/* Parity Enable (PE) */
+#define _00_SCI_PARITY_DISABLE                    (0x00U)   /* Parity disable */
+#define _20_SCI_PARITY_ENABLE                     (0x20U)   /* Parity enable */
+/* Character Length (CHR) */
+#define _00_SCI_DATA_LENGTH_8                     (0x00U)   /* Data length 8 bits */
+#define _40_SCI_DATA_LENGTH_7                     (0x40U)   /* Data length 7 bits */
+/* Communications Mode (CM) */
+#define _00_SCI_ASYNCHRONOUS_OR_I2C_MODE          (0x00U)   /* Asynchronous mode or simple I2C mode */
+#define _80_SCI_CLOCK_SYNCHRONOUS_OR_SPI_MODE     (0x80U)   /* Clock synchronous mode or simple SPI mode */
+/* Base Clock Pulse (BCP) */
+#define _00_SCI_32_93_CLOCK_CYCLES                (0x00U)   /* 32 or 93 clock cycles */
+#define _04_SCI_64_128_CLOCK_CYCLES               (0x04U)   /* 64 or 128 clock cycles */
+#define _08_SCI_186_372_CLOCK_CYCLES              (0x08U)   /* 186 or 372 clock cycles */
+#define _0C_SCI_256_512_CLOCK_CYCLES              (0x0CU)   /* 256 or 512 clock cycles */
+/* Block Transfer Mode (BLK) */
+#define _00_SCI_BLK_TRANSFER_DISABLE              (0x00U)   /* Block transfer disable */
+#define _40_SCI_BLK_TRANSFER_ENABLE               (0x40U)   /* Block transfer enable */
+/* GSM Mode (GM) */
+#define _00_SCI_GSM_DISABLE                       (0x00U)   /* Normal mode operation */
+#define _80_SCI_GSM_ENABLE                        (0x80U)   /* GSM mode operation */
+
+/*
+    Serial Control Register (SCR)
+*/
+/* Clock Enable (CKE) */
+#define _00_SCI_INTERNAL_SCK_UNUSED               (0x00U)   /* Internal clock selected, SCK pin unused */
+#define _00_SCI_INTERNAL_SCK_FIXED_LOW            (0x00U)   /* Internal clock selected, SCK pin output low */
+#define _01_SCI_INTERNAL_SCK_OUTPUT               (0x01U)   /* Internal clock selected, SCK pin as clock output */
+#define _02_SCI_INTERNAL_SCK_FIXED_HIGH           (0x02U)   /* Internal clock selected, SCK pin output high */
+#define _02_SCI_EXTERNAL                          (0x02U)   /* External clock selected */
+#define _02_SCI_EXTERNAL_TMR                      (0x02U)   /* External or TMR clock selected */
+/* Transmit End Interrupt Enable (TEIE) */
+#define _00_SCI_TEI_INTERRUPT_DISABLE             (0x00U)   /* TEI interrupt request disable */
+#define _04_SCI_TEI_INTERRUPT_ENABLE              (0x04U)   /* TEI interrupt request enable */
+/* Multi-Processor Interrupt Enable (MPIE) */
+#define _00_SCI_MP_INTERRUPT_NORMAL               (0x00U)   /* Normal reception */
+#define _08_SCI_MP_INTERRUPT_SPECIAL              (0x08U)   /* Multi-processor ID reception */
+/* Receive Enable (RE) */
+#define _00_SCI_RECEIVE_DISABLE                   (0x00U)   /* Disable receive mode */
+#define _10_SCI_RECEIVE_ENABLE                    (0x10U)   /* Enable receive mode */
+/* Transmit Enable (TE) */
+#define _00_SCI_TRANSMIT_DISABLE                  (0x00U)   /* Disable transmit mode */
+#define _20_SCI_TRANSMIT_ENABLE                   (0x20U)   /* Enable transmit mode */
+/* Receive Interrupt Enable (RIE) */
+#define _00_SCI_RXI_ERI_DISABLE                   (0x00U)   /* Disable RXI and ERI interrupt requests */
+#define _40_SCI_RXI_ERI_ENABLE                    (0x40U)   /* Enable RXI and ERI interrupt requests */
+/* Transmit Interrupt Enable (TIE) */
+#define _00_SCI_TXI_DISABLE                       (0x00U)   /* Disable TXI interrupt requests */
+#define _80_SCI_TXI_ENABLE                        (0x80U)   /* Enable TXI interrupt requests */
+
+/*
+    Smart Card Mode Register (SCMR)
+*/
+/* Smart Card Interface Mode Select (SMIF) */
+#define _00_SCI_SERIAL_MODE                       (0x00U)   /* Serial communications interface mode */
+#define _01_SCI_SMART_CARD_MODE                   (0x01U)   /* Smart card interface mode */
+/* Transmitted / Received Data Invert (SINV) */
+#define _00_SCI_DATA_INVERT_NONE                  (0x00U)   /* Data is not inverted */
+#define _04_SCI_DATA_INVERTED                     (0x04U)   /* Data is inverted */
+/* Transmitted / Received Data Transfer Direction (SDIR) */
+#define _00_SCI_DATA_LSB_FIRST                    (0x00U)   /* Transfer data LSB first */
+#define _08_SCI_DATA_MSB_FIRST                    (0x08U)   /* Transfer data MSB first */
+/* Character Length 1 (CHR1) */
+#define _00_SCI_DATA_LENGTH_9                     (0x00U)   /* Transmit/receive in 9-bit data length */
+#define _10_SCI_DATA_LENGTH_8_OR_7                (0x10U)   /* Transmit/receive in 8-bit or 7-bit data length */
+/* Base Clock Pulse 2 (BCP2) */
+#define _00_SCI_93_128_186_512_CLK                (0x00U)   /* 93, 128, 186, or 512 clock cycles */
+#define _80_SCI_32_64_256_372_CLK                 (0x80U)   /* 32, 64, 256, or 372 clock cycles */
+/* SCMR Default Value */
+#define _62_SCI_SCMR_DEFAULT                      (0x62U)   /* Write default value of SCMR */
+
+/*
+    Serial Extended Mode Register (SEMR)
+*/
+/* Asynchronous Mode Clock Source Select (ACS0) */
+#define _00_SCI_ASYNC_SOURCE_EXTERNAL             (0x00U)   /* External clock input */
+#define _01_SCI_ASYNC_SOURCE_TMR                  (0x01U)   /* Logical AND of two clock cycles output from TMR */
+/* Bit Modulation Enable (BRME) */
+#define _00_SCI_BIT_MODULATION_DISABLE            (0x00U)   /* Bit rate modulation function is disabled */
+#define _04_SCI_BIT_MODULATION_ENABLE             (0x04U)   /* Bit rate modulation function is enabled */
+/* Asynchronous Mode Base Clock Select (ABCS) */
+#define _00_SCI_16_BASE_CLOCK                     (0x00U)   /* Selects 16 base clock cycles for 1 bit period */
+#define _10_SCI_8_BASE_CLOCK                      (0x10U)   /* Selects 8 base clock cycles for 1 bit period */
+/* Digital Noise Filter Function Enable (NFEN) */
+#define _00_SCI_NOISE_FILTER_DISABLE              (0x00U)   /* Noise filter is disabled */
+#define _20_SCI_NOISE_FILTER_ENABLE               (0x20U)   /* Noise filter is enabled */
+/* Baud Rate Generator Double-Speed Mode Select (BGDM) */
+#define _00_SCI_BAUDRATE_SINGLE                   (0x00U)   /* Baud rate generator outputs normal frequency */
+#define _40_SCI_BAUDRATE_DOUBLE                   (0x40U)   /* Baud rate generator doubles output frequency */
+/* Asynchronous Start Bit Edge Detections Select (RXDESEL) */
+#define _00_SCI_LOW_LEVEL_START_BIT               (0x00U)   /* Low level on RXDn pin selected as start bit */
+#define _80_SCI_FALLING_EDGE_START_BIT            (0x80U)   /* Falling edge on RXDn pin selected as start bit */
+
+/*
+    Noise Filter Setting Register (SNFR)
+*/
+/* Noise Filter Clock Select (NFCS) */
+#define _00_SCI_ASYNC_DIV_1                       (0x00U)   /* Clock signal divided by 1 */
+#define _01_SCI_IIC_DIV_1                         (0x01U)   /* Clock signal divided by 1 */
+#define _02_SCI_IIC_DIV_2                         (0x02U)   /* Clock signal divided by 2 */
+#define _03_SCI_IIC_DIV_4                         (0x03U)   /* Clock signal divided by 4 */
+#define _04_SCI_IIC_DIV_8                         (0x04U)   /* Clock signal divided by 8 */
+
+/*
+    I2C Mode Register 1 (SIMR1)
+*/
+/* Simple IIC Mode Select (IICM) */
+#define _00_SCI_SERIAL_SMART_CARD_MODE            (0x00U)   /* Serial or smart card mode */
+#define _01_SCI_IIC_MODE                          (0x01U)   /* Simple IIC mode */
+/* SSDA Output Delay Select (IICDL)*/
+#define _00_SCI_NONE                              (0x00U)   /* No output delay */
+#define _08_SCI_0_TO_1_CYCLE                      (0x08U)   /* 0 to 1 cycle */
+#define _10_SCI_1_TO_2_CYCLE                      (0x10U)   /* 1 to 2 cycles */
+#define _18_SCI_2_TO_3_CYCLE                      (0x18U)   /* 2 to 3 cycles */
+#define _20_SCI_3_TO_4_CYCLE                      (0x20U)   /* 3 to 4 cycles */
+#define _28_SCI_4_TO_5_CYCLE                      (0x28U)   /* 4 to 5 cycles */
+#define _30_SCI_5_TO_6_CYCLE                      (0x30U)   /* 5 to 6 cycles */
+#define _38_SCI_6_TO_7_CYCLE                      (0x38U)   /* 6 to 7 cycles */
+#define _40_SCI_7_TO_8_CYCLE                      (0x40U)   /* 7 to 8 cycles */
+#define _48_SCI_8_TO_9_CYCLE                      (0x48U)   /* 8 to 9 cycles */
+#define _50_SCI_9_TO_10_CYCLE                     (0x50U)   /* 9 to 10 cycles */
+#define _58_SCI_10_TO_11_CYCLE                    (0x58U)   /* 10 to 11 cycles */
+#define _60_SCI_11_TO_12_CYCLE                    (0x60U)   /* 11 to 12 cycles */
+#define _68_SCI_12_TO_13_CYCLE                    (0x68U)   /* 12 to 13 cycles */
+#define _70_SCI_13_TO_14_CYCLE                    (0x70U)   /* 13 to 14 cycles */
+#define _78_SCI_14_TO_15_CYCLE                    (0x78U)   /* 14 to 15 cycles */
+#define _80_SCI_15_TO_16_CYCLE                    (0x80U)   /* 15 to 16 cycles */
+#define _88_SCI_16_TO_17_CYCLE                    (0x88U)   /* 16 to 17 cycles */
+#define _90_SCI_17_TO_18_CYCLE                    (0x90U)   /* 17 to 18 cycles */
+#define _98_SCI_18_TO_19_CYCLE                    (0x98U)   /* 18 to 19 cycles */
+#define _A0_SCI_19_TO_20_CYCLE                    (0xA0U)   /* 19 to 20 cycles */
+#define _A8_SCI_20_TO_21_CYCLE                    (0xA8U)   /* 20 to 21 cycles */
+#define _B0_SCI_21_TO_22_CYCLE                    (0xB0U)   /* 21 to 22 cycles */
+#define _B8_SCI_22_TO_23_CYCLE                    (0xB8U)   /* 22 to 23 cycles */
+#define _C0_SCI_23_TO_24_CYCLE                    (0xC0U)   /* 23 to 24 cycles */
+#define _C8_SCI_24_TO_25_CYCLE                    (0xC8U)   /* 24 to 25 cycles */
+#define _D0_SCI_25_TO_26_CYCLE                    (0xD0U)   /* 25 to 26 cycles */
+#define _D8_SCI_26_TO_27_CYCLE                    (0xD8U)   /* 26 to 27 cycles */
+#define _E0_SCI_27_TO_28_CYCLE                    (0xE0U)   /* 27 to 28 cycles */
+#define _E8_SCI_28_TO_29_CYCLE                    (0xE8U)   /* 28 to 29 cycles */
+#define _F0_SCI_29_TO_30_CYCLE                    (0xF0U)   /* 29 to 30 cycles */
+#define _F8_SCI_30_TO_31_CYCLE                    (0xF8U)   /* 30 to 31 cycles */
+
+/*
+    I2C Mode Register 2 (SIMR2)
+*/
+/* IIC Interrupt Mode Select (IICINTM) */
+#define _00_SCI_ACK_NACK_INTERRUPTS               (0x00U)   /* Use ACK/NACK interrupts */
+#define _01_SCI_RX_TX_INTERRUPTS                  (0x01U)   /* Use reception/transmission interrupts */
+/* Clock Synchronization (IICCSC) */
+#define _00_SCI_NO_SYNCHRONIZATION                (0x00U)   /* No synchronization with the clock signal */
+#define _02_SCI_SYNCHRONIZATION                   (0x02U)   /* Synchronization with the clock signal */
+/* ACK Transmission Data (IICACKT) */
+#define _00_SCI_ACK_TRANSMISSION                  (0x00U)   /* ACK transmission */
+#define _20_SCI_NACK_TRANSMISSION                 (0x20U)   /* NACK transmission and reception of ACK/NACK */
+
+/*
+    I2C Mode Register 3 (SIMR3)
+*/
+/* Start Condition Generation (IICSTAREQ) */
+#define _00_SCI_START_CONDITION_OFF               (0x00U)   /* Start condition is not generated */
+#define _01_SCI_START_CONDITION_ON                (0x01U)   /* Start condition is generated */
+/* Restart Condition Generation (IICRSTAREQ) */
+#define _00_SCI_RESTART_CONDITION_OFF             (0x00U)   /* Restart condition is not generated */
+#define _02_SCI_RESTART_CONDITION_ON              (0x02U)   /* Restart condition is generated */
+/* Stop Condition Generation (IICSTPREQ) */
+#define _00_SCI_STOP_CONDITION_OFF                (0x00U)   /* Stop condition is not generated */
+#define _04_SCI_STOP_CONDITION_ON                 (0x04U)   /* Stop condition is generated */
+/* Issuing of Start, Restart, or Stop Condition Completed Flag (IICSTIF) */
+#define _00_SCI_CONDITION_GENERATED               (0x00U)   /* No requests to generate conditions/conditions generated */
+#define _08_SCI_GENERATION_COMPLETED              (0x08U)   /* All request generation has been completed */
+/* SSDA Output Select (IICSDAS) */
+#define _00_SCI_SSDA_DATA_OUTPUT                  (0x00U)   /* SSDA output is serial data output */
+#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U)   /* SSDA output generates start, restart or stop condition */
+#define _20_SCI_SSDA_LOW_LEVEL                    (0x20U)   /* SSDA output low level */
+#define _30_SCI_SSDA_HIGH_IMPEDANCE               (0x30U)   /* SSDA output high impedance */
+/* SSCL Output Select (IICSCLS) */
+#define _00_SCI_SSCL_CLOCK_OUTPUT                 (0x00U)   /* SSCL output is serial clock output */
+#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U)   /* SSCL output generates start, restart or stop condition */
+#define _80_SCI_SSCL_LOW_LEVEL                    (0x80U)   /* SSCL output low level */
+#define _C0_SCI_SSCL_HIGH_IMPEDANCE               (0xC0U)   /* SSCL output high impedance */
+
+/*
+    SPI Mode Register (SPMR)
+*/
+/* SS Pin Function Enable (SSE) */
+#define _00_SCI_SS_PIN_DISABLE                    (0x00U)   /* SS pin function disabled */
+#define _01_SCI_SS_PIN_ENABLE                     (0x01U)   /* SS pin function enabled */
+/* CTS Enable (CTSE) */
+#define _00_SCI_RTS                               (0x00U)   /* RTS function is enabled */
+#define _02_SCI_CTS                               (0x02U)   /* CTS function is enabled */
+/* Master Slave Select (MSS) */
+#define _00_SCI_SPI_MASTER                        (0x00U)   /* Master mode */
+#define _04_SCI_SPI_SLAVE                         (0x04U)   /* Slave mode */
+/* Mode Fault Flag (MFF) */
+#define _00_SCI_NO_MODE_FAULT                     (0x00U)   /* No mode fault */
+#define _10_SCI_MODE_FAULT                        (0x10U)   /* Mode fault */
+/* Clock Polarity Select (CKPOL) */
+#define _00_SCI_CLOCK_NOT_INVERTED                (0x00U)   /* Clock polarity is not inverted */
+#define _40_SCI_CLOCK_INVERTED                    (0x40U)   /* Clock polarity is inverted */
+/* Clock Phase Select (CKPH) */
+#define _00_SCI_CLOCK_NOT_DELAYED                 (0x00U)   /* Clock is not delayed */
+#define _80_SCI_CLOCK_DELAYED                     (0x80U)   /* Clock is delayed */
+
+/*
+    FIFO Control Register (FCR)
+*/
+/* FIFO Mode Select (FM) */
+#define _0000_SCI_NON_FIFO_MODE                   (0x0000U) /* Non-FIFO mode */
+#define _0001_SCI_FIFO_MODE                       (0x0001U) /* FIFO mode */
+/* Receive FIFO Reset (RFRST) */
+#define _0000_SCI_RX_FIFO_RESET_DISABLE           (0x0000U) /* Select receive data full interrupt (RXI) */
+#define _0002_SCI_RX_FIFO_RESET_ENABLE            (0x0002U) /* FIFO mode */
+/* Transmit FIFO Reset (TFRST) */
+#define _0000_SCI_TX_FIFO_RESET_DISABLE           (0x0000U) /* Select receive data full interrupt (RXI) */
+#define _0004_SCI_TX_FIFO_RESET_ENABLE            (0x0004U) /* FIFO mode */
+/* Receive Data Ready Interrupt Select (DRES) */
+#define _0000_SCI_RXI_SELECT                      (0x0000U) /* Select receive data full interrupt (RXI) */
+#define _0008_SCI_ERI_SELECT                      (0x0008U) /* Select error interrupt (ERI) */
+/* Transmit FIFO Threshold Setting (TTRG) */
+#define _0000_SCI_TX_TRIGGER_NUM_0                (0x0000U) /* Transmit FIFO threshold value is 0 */
+#define _0010_SCI_TX_TRIGGER_NUM_1                (0x0010U) /* Transmit FIFO threshold value is 1 */
+#define _0020_SCI_TX_TRIGGER_NUM_2                (0x0020U) /* Transmit FIFO threshold value is 2 */
+#define _0030_SCI_TX_TRIGGER_NUM_3                (0x0030U) /* Transmit FIFO threshold value is 3 */
+#define _0040_SCI_TX_TRIGGER_NUM_4                (0x0040U) /* Transmit FIFO threshold value is 4 */
+#define _0050_SCI_TX_TRIGGER_NUM_5                (0x0050U) /* Transmit FIFO threshold value is 5 */
+#define _0060_SCI_TX_TRIGGER_NUM_6                (0x0060U) /* Transmit FIFO threshold value is 6 */
+#define _0070_SCI_TX_TRIGGER_NUM_7                (0x0070U) /* Transmit FIFO threshold value is 7 */
+#define _0080_SCI_TX_TRIGGER_NUM_8                (0x0080U) /* Transmit FIFO threshold value is 8 */
+#define _0090_SCI_TX_TRIGGER_NUM_9                (0x0090U) /* Transmit FIFO threshold value is 9 */
+#define _00A0_SCI_TX_TRIGGER_NUM_10               (0x00A0U) /* Transmit FIFO threshold value is 10 */
+#define _00B0_SCI_TX_TRIGGER_NUM_11               (0x00B0U) /* Transmit FIFO threshold value is 11 */
+#define _00C0_SCI_TX_TRIGGER_NUM_12               (0x00C0U) /* Transmit FIFO threshold value is 12 */
+#define _00D0_SCI_TX_TRIGGER_NUM_13               (0x00D0U) /* Transmit FIFO threshold value is 13 */
+#define _00E0_SCI_TX_TRIGGER_NUM_14               (0x00E0U) /* Transmit FIFO threshold value is 14 */
+#define _00F0_SCI_TX_TRIGGER_NUM_15               (0x00F0U) /* Transmit FIFO threshold value is 15 */
+/* Receive FIFO Threshold Setting (RTRG) */
+#define _0100_SCI_RX_TRIGGER_NUM_1                (0x0100U) /* Receive FIFO threshold value is 1 */
+#define _0200_SCI_RX_TRIGGER_NUM_2                (0x0200U) /* Receive FIFO threshold value is 2 */
+#define _0300_SCI_RX_TRIGGER_NUM_3                (0x0300U) /* Receive FIFO threshold value is 3 */
+#define _0400_SCI_RX_TRIGGER_NUM_4                (0x0400U) /* Receive FIFO threshold value is 4 */
+#define _0500_SCI_RX_TRIGGER_NUM_5                (0x0500U) /* Receive FIFO threshold value is 5 */
+#define _0600_SCI_RX_TRIGGER_NUM_6                (0x0600U) /* Receive FIFO threshold value is 6 */
+#define _0700_SCI_RX_TRIGGER_NUM_7                (0x0700U) /* Receive FIFO threshold value is 7 */
+#define _0800_SCI_RX_TRIGGER_NUM_8                (0x0800U) /* Receive FIFO threshold value is 8 */
+#define _0900_SCI_RX_TRIGGER_NUM_9                (0x0900U) /* Receive FIFO threshold value is 9 */
+#define _0A00_SCI_RX_TRIGGER_NUM_10               (0x0A00U) /* Receive FIFO threshold value is 10 */
+#define _0B00_SCI_RX_TRIGGER_NUM_11               (0x0B00U) /* Receive FIFO threshold value is 11 */
+#define _0C00_SCI_RX_TRIGGER_NUM_12               (0x0C00U) /* Receive FIFO threshold value is 12 */
+#define _0D00_SCI_RX_TRIGGER_NUM_13               (0x0D00U) /* Receive FIFO threshold value is 13 */
+#define _0E00_SCI_RX_TRIGGER_NUM_14               (0x0E00U) /* Receive FIFO threshold value is 14 */
+#define _0F00_SCI_RX_TRIGGER_NUM_15               (0x0F00U) /* Receive FIFO threshold value is 15 */
+/* RTS# Output Threshold Setting (RSTRG) */
+#define _1000_SCI_RTS_TRIGGER_NUM_1               (0x1000U) /* Receive FIFO threshold value is 1 */
+#define _2000_SCI_RTS_TRIGGER_NUM_2               (0x2000U) /* Receive FIFO threshold value is 2 */
+#define _3000_SCI_RTS_TRIGGER_NUM_3               (0x3000U) /* Receive FIFO threshold value is 3 */
+#define _4000_SCI_RTS_TRIGGER_NUM_4               (0x4000U) /* Receive FIFO threshold value is 4 */
+#define _5000_SCI_RTS_TRIGGER_NUM_5               (0x5000U) /* Receive FIFO threshold value is 5 */
+#define _6000_SCI_RTS_TRIGGER_NUM_6               (0x6000U) /* Receive FIFO threshold value is 6 */
+#define _7000_SCI_RTS_TRIGGER_NUM_7               (0x7000U) /* Receive FIFO threshold value is 7 */
+#define _8000_SCI_RTS_TRIGGER_NUM_8               (0x8000U) /* Receive FIFO threshold value is 8 */
+#define _9000_SCI_RTS_TRIGGER_NUM_9               (0x9000U) /* Receive FIFO threshold value is 9 */
+#define _A000_SCI_RTS_TRIGGER_NUM_10              (0xA000U) /* Receive FIFO threshold value is 10 */
+#define _B000_SCI_RTS_TRIGGER_NUM_11              (0xB000U) /* Receive FIFO threshold value is 11 */
+#define _C000_SCI_RTS_TRIGGER_NUM_12              (0xC000U) /* Receive FIFO threshold value is 12 */
+#define _D000_SCI_RTS_TRIGGER_NUM_13              (0xD000U) /* Receive FIFO threshold value is 13 */
+#define _E000_SCI_RTS_TRIGGER_NUM_14              (0xE000U) /* Receive FIFO threshold value is 14 */
+#define _F000_SCI_RTS_TRIGGER_NUM_15              (0xF000U) /* Receive FIFO threshold value is 15 */
+
+/*
+    Data Comparison Control Register (DCCR)
+*/
+/* ID Frame Select (IDSEL) */
+#define _00_SCI_ALL_DATA_COMPARED                 (0x00U)   /* All data is to be compared */
+#define _40_SCI_ID_FRAME_COMPARED                 (0x40U)   /* Only data in ID frames is compared */
+/* Data Match Detection Enable (DCME) */
+#define _00_SCI_DATA_MATCH_DISABLE                (0x00U)   /* Data match detection is disabled */
+#define _80_SCI_DATA_MATCH_ENABLE                 (0x80U)   /* Data match detection is enabled */
+
+/*
+    Interrupt Source Priority Register n (IPRn)
+*/
+/* Interrupt Priority Level Select (IPR[3:0]) */
+#define _00_SCI_PRIORITY_LEVEL0                   (0x00U)   /* Level 0 (interrupt disabled) */
+#define _01_SCI_PRIORITY_LEVEL1                   (0x01U)   /* Level 1 */
+#define _02_SCI_PRIORITY_LEVEL2                   (0x02U)   /* Level 2 */
+#define _03_SCI_PRIORITY_LEVEL3                   (0x03U)   /* Level 3 */
+#define _04_SCI_PRIORITY_LEVEL4                   (0x04U)   /* Level 4 */
+#define _05_SCI_PRIORITY_LEVEL5                   (0x05U)   /* Level 5 */
+#define _06_SCI_PRIORITY_LEVEL6                   (0x06U)   /* Level 6 */
+#define _07_SCI_PRIORITY_LEVEL7                   (0x07U)   /* Level 7 */
+#define _08_SCI_PRIORITY_LEVEL8                   (0x08U)   /* Level 8 */
+#define _09_SCI_PRIORITY_LEVEL9                   (0x09U)   /* Level 9 */
+#define _0A_SCI_PRIORITY_LEVEL10                  (0x0AU)   /* Level 10 */
+#define _0B_SCI_PRIORITY_LEVEL11                  (0x0BU)   /* Level 11 */
+#define _0C_SCI_PRIORITY_LEVEL12                  (0x0CU)   /* Level 12 */
+#define _0D_SCI_PRIORITY_LEVEL13                  (0x0DU)   /* Level 13 */
+#define _0E_SCI_PRIORITY_LEVEL14                  (0x0EU)   /* Level 14 */
+#define _0F_SCI_PRIORITY_LEVEL15                  (0x0FU)   /* Level 15 (highest) */
+
+/*
+    Transfer Status Control Value
+*/
+/* Simple IIC Transmit Receive Flag */
+#define _80_SCI_IIC_TRANSMISSION                  (0x80U)   /* Simple IIC Transmission State */
+#define _00_SCI_IIC_RECEPTION                     (0x00U)   /* Simple IIC Reception State */
+/* Simple IIC Start Stop Flag */
+#define _80_SCI_IIC_START_CYCLE                   (0x80U)   /* Simple IIC Start Cycle */
+#define _00_SCI_IIC_STOP_CYCLE                    (0x00U)   /* Simple IIC Stop Cycle */
+/* Multiprocessor Asynchronous Communication Flag */
+#define _80_SCI_ID_TRANSMISSION_CYCLE             (0x80U)   /* Multiprocessor Asynchronous ID Transmission Cycle */
+#define _00_SCI_DATA_TRANSMISSION_CYCLE           (0x00U)   /* Multiprocessor Asynchronous Data Transmission Cycle */
+
+/* FIFO Buffer Maximum Size */
+#define _10_SCI_FIFO_MAX_SIZE                     (0x10U)   /* Size of 16-stage FIFO buffer */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_userdefine.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_userdefine.h
new file mode 100644
index 00000000..d225102f
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_cg_userdefine.h
@@ -0,0 +1,61 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_userdefine.h
+* Version      : 1.2.101
+* Device(s)    : R5F565NEDxFC
+* Description  : User header file for code generation.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef CG_USER_DEF_H
+#define CG_USER_DEF_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/* Start user code for register. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Start user code for macro define. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+/* Start user code for type define. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_cgc.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_cgc.c
new file mode 100644
index 00000000..859841e8
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_cgc.c
@@ -0,0 +1,63 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_smc_cgc.c
+* Version      : 1.6.102
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements CGC setting.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_smc_cgc.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Create
+* Description  : This function initializes the clock generator
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_CGC_Create(void)
+{
+    R_CGC_Create_UserInit();
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_cgc.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_cgc.h
new file mode 100644
index 00000000..1ec70c46
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_cgc.h
@@ -0,0 +1,217 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_smc_cgc.h
+* Version      : 1.6.102
+* Device(s)    : R5F565NEDxFC
+* Description  : CGC setting header file.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef SMC_CGC_H
+#define SMC_CGC_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+    System Clock Control Register (SCKCR)
+*/
+/* Peripheral Module Clock D (PCLKD) */
+#define _00000000_CGC_PCLKD_DIV_1           (0x00000000UL) /* x1 */
+#define _00000001_CGC_PCLKD_DIV_2           (0x00000001UL) /* x1/2 */
+#define _00000002_CGC_PCLKD_DIV_4           (0x00000002UL) /* x1/4 */
+#define _00000003_CGC_PCLKD_DIV_8           (0x00000003UL) /* x1/8 */
+#define _00000004_CGC_PCLKD_DIV_16          (0x00000004UL) /* x1/16 */
+#define _00000005_CGC_PCLKD_DIV_32          (0x00000005UL) /* x1/32 */
+#define _00000006_CGC_PCLKD_DIV_64          (0x00000006UL) /* x1/64 */
+/* Peripheral Module Clock C (PCLKC) */
+#define _00000000_CGC_PCLKC_DIV_1           (0x00000000UL) /* x1 */
+#define _00000010_CGC_PCLKC_DIV_2           (0x00000010UL) /* x1/2 */
+#define _00000020_CGC_PCLKC_DIV_4           (0x00000020UL) /* x1/4 */
+#define _00000030_CGC_PCLKC_DIV_8           (0x00000030UL) /* x1/8 */
+#define _00000040_CGC_PCLKC_DIV_16          (0x00000040UL) /* x1/16 */
+#define _00000050_CGC_PCLKC_DIV_32          (0x00000050UL) /* x1/32 */
+#define _00000060_CGC_PCLKC_DIV_64          (0x00000060UL) /* x1/64 */
+/* Peripheral Module Clock B (PCLKB) */
+#define _00000000_CGC_PCLKB_DIV_1           (0x00000000UL) /* x1 */
+#define _00000100_CGC_PCLKB_DIV_2           (0x00000100UL) /* x1/2 */
+#define _00000200_CGC_PCLKB_DIV_4           (0x00000200UL) /* x1/4 */
+#define _00000300_CGC_PCLKB_DIV_8           (0x00000300UL) /* x1/8 */
+#define _00000400_CGC_PCLKB_DIV_16          (0x00000400UL) /* x1/16 */
+#define _00000500_CGC_PCLKB_DIV_32          (0x00000500UL) /* x1/32 */
+#define _00000600_CGC_PCLKB_DIV_64          (0x00000600UL) /* x1/64 */
+/* Peripheral Module Clock A (PCLKA) */
+#define _00000000_CGC_PCLKA_DIV_1           (0x00000000UL) /* x1 */
+#define _00001000_CGC_PCLKA_DIV_2           (0x00001000UL) /* x1/2 */
+#define _00002000_CGC_PCLKA_DIV_4           (0x00002000UL) /* x1/4 */
+#define _00003000_CGC_PCLKA_DIV_8           (0x00003000UL) /* x1/8 */
+#define _00004000_CGC_PCLKA_DIV_16          (0x00004000UL) /* x1/16 */
+#define _00005000_CGC_PCLKA_DIV_32          (0x00005000UL) /* x1/32 */
+#define _00006000_CGC_PCLKA_DIV_64          (0x00006000UL) /* x1/64 */
+/* External Bus Clock (BCLK) */
+#define _00000000_CGC_BCLK_DIV_1            (0x00000000UL) /* x1 */
+#define _00010000_CGC_BCLK_DIV_2            (0x00010000UL) /* x1/2 */
+#define _00020000_CGC_BCLK_DIV_4            (0x00020000UL) /* x1/4 */
+#define _00030000_CGC_BCLK_DIV_8            (0x00030000UL) /* x1/8 */
+#define _00040000_CGC_BCLK_DIV_16           (0x00040000UL) /* x1/16 */
+#define _00050000_CGC_BCLK_DIV_32           (0x00050000UL) /* x1/32 */
+#define _00060000_CGC_BCLK_DIV_64           (0x00060000UL) /* x1/64 */
+/* System Clock (ICLK) */
+#define _00000000_CGC_ICLK_DIV_1            (0x00000000UL) /* x1 */
+#define _01000000_CGC_ICLK_DIV_2            (0x01000000UL) /* x1/2 */
+#define _02000000_CGC_ICLK_DIV_4            (0x02000000UL) /* x1/4 */
+#define _03000000_CGC_ICLK_DIV_8            (0x03000000UL) /* x1/8 */
+#define _04000000_CGC_ICLK_DIV_16           (0x04000000UL) /* x1/16 */
+#define _05000000_CGC_ICLK_DIV_32           (0x05000000UL) /* x1/32 */
+#define _06000000_CGC_ICLK_DIV_64           (0x06000000UL) /* x1/64 */
+/* System Clock (FCLK) */
+#define _00000000_CGC_FCLK_DIV_1            (0x00000000UL) /* x1 */
+#define _10000000_CGC_FCLK_DIV_2            (0x10000000UL) /* x1/2 */
+#define _20000000_CGC_FCLK_DIV_4            (0x20000000UL) /* x1/4 */
+#define _30000000_CGC_FCLK_DIV_8            (0x30000000UL) /* x1/8 */
+#define _40000000_CGC_FCLK_DIV_16           (0x40000000UL) /* x1/16 */
+#define _50000000_CGC_FCLK_DIV_32           (0x50000000UL) /* x1/32 */
+#define _60000000_CGC_FCLK_DIV_64           (0x60000000UL) /* x1/64 */
+
+/*
+    System Clock Control Register 2 (SCKCR2)
+*/
+#define _0010_CGC_UCLK_DIV_1                (0x0010U) /* x1/2 */
+#define _0020_CGC_UCLK_DIV_3                (0x0020U) /* x1/3 */
+#define _0030_CGC_UCLK_DIV_4                (0x0030U) /* x1/4 */
+#define _0040_CGC_UCLK_DIV_5                (0x0040U) /* x1/5 */
+#define _0001_SCKCR2_BIT0                   (0x0001U) /* RESERVE BIT0 */
+
+/*
+    System Clock Control Register 3 (SCKCR3)
+*/
+#define _0000_CGC_CLOCKSOURCE_LOCO          (0x0000U) /* LOCO */
+#define _0100_CGC_CLOCKSOURCE_HOCO          (0x0100U) /* HOCO */
+#define _0200_CGC_CLOCKSOURCE_MAINCLK       (0x0200U) /* Main clock oscillator */
+#define _0300_CGC_CLOCKSOURCE_SUBCLK        (0x0300U) /* Sub-clock oscillator */
+#define _0400_CGC_CLOCKSOURCE_PLL           (0x0400U) /* PLL circuit */
+
+/*
+    PLL Control Register (PLLCR)
+*/
+/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */
+#define _0000_CGC_PLL_FREQ_DIV_1            (0x0000U) /* x1 */
+#define _0001_CGC_PLL_FREQ_DIV_2            (0x0001U) /* x1/2 */
+#define _0002_CGC_PLL_FREQ_DIV_3            (0x0002U) /* x1/3 */
+/* PLL Clock Source Select (PLLSRCSEL) */
+#define _0000_CGC_PLL_SOURCE_MAIN           (0x0000U) /* Main clock oscillator */
+#define _0010_CGC_PLL_SOURCE_HOCO           (0x0010U) /* HOCO */
+/* Frequency Multiplication Factor Select (STC[5:0]) */
+#define _1300_CGC_PLL_FREQ_MUL_10_0         (0x1300U) /* x10.0 */
+#define _1400_CGC_PLL_FREQ_MUL_10_5         (0x1400U) /* x10.5 */
+#define _1500_CGC_PLL_FREQ_MUL_11_0         (0x1500U) /* x11.0 */
+#define _1600_CGC_PLL_FREQ_MUL_11_5         (0x1600U) /* x11.5 */
+#define _1700_CGC_PLL_FREQ_MUL_12_0         (0x1700U) /* x12.0 */
+#define _1800_CGC_PLL_FREQ_MUL_12_5         (0x1800U) /* x12.5 */
+#define _1900_CGC_PLL_FREQ_MUL_13_0         (0x1900U) /* x13.0 */
+#define _1A00_CGC_PLL_FREQ_MUL_13_5         (0x1A00U) /* x13.5 */
+#define _1B00_CGC_PLL_FREQ_MUL_14_0         (0x1B00U) /* x14.0 */
+#define _1C00_CGC_PLL_FREQ_MUL_14_5         (0x1C00U) /* x14.5 */
+#define _1D00_CGC_PLL_FREQ_MUL_15_0         (0x1D00U) /* x15.0 */
+#define _1E00_CGC_PLL_FREQ_MUL_15_5         (0x1E00U) /* x15.5 */
+#define _1F00_CGC_PLL_FREQ_MUL_16_0         (0x1F00U) /* x16.0 */
+#define _2000_CGC_PLL_FREQ_MUL_16_5         (0x2000U) /* x16.5 */
+#define _2100_CGC_PLL_FREQ_MUL_17_0         (0x2100U) /* x17.0 */
+#define _2200_CGC_PLL_FREQ_MUL_17_5         (0x2200U) /* x17.5 */
+#define _2300_CGC_PLL_FREQ_MUL_18_0         (0x2300U) /* x18.0 */
+#define _2400_CGC_PLL_FREQ_MUL_18_5         (0x2400U) /* x18.5 */
+#define _2500_CGC_PLL_FREQ_MUL_19_0         (0x2500U) /* x19.0 */
+#define _2600_CGC_PLL_FREQ_MUL_19_5         (0x2600U) /* x19.5 */
+#define _2700_CGC_PLL_FREQ_MUL_20_0         (0x2700U) /* x20.0 */
+#define _2800_CGC_PLL_FREQ_MUL_20_5         (0x2800U) /* x20.5 */
+#define _2900_CGC_PLL_FREQ_MUL_21_0         (0x2900U) /* x21.0 */
+#define _2A00_CGC_PLL_FREQ_MUL_21_5         (0x2A00U) /* x21.5 */
+#define _2B00_CGC_PLL_FREQ_MUL_22_0         (0x2B00U) /* x22.0 */
+#define _2C00_CGC_PLL_FREQ_MUL_22_5         (0x2C00U) /* x22.5 */
+#define _2D00_CGC_PLL_FREQ_MUL_23_0         (0x2D00U) /* x23.0 */
+#define _2E00_CGC_PLL_FREQ_MUL_23_5         (0x2E00U) /* x23.5 */
+#define _2F00_CGC_PLL_FREQ_MUL_24_0         (0x2F00U) /* x24.0 */
+#define _3000_CGC_PLL_FREQ_MUL_24_5         (0x3000U) /* x24.5 */
+#define _3100_CGC_PLL_FREQ_MUL_25_0         (0x3100U) /* x25.0 */
+#define _3200_CGC_PLL_FREQ_MUL_25_5         (0x3200U) /* x25.5 */
+#define _3300_CGC_PLL_FREQ_MUL_26_0         (0x3300U) /* x26.0 */
+#define _3400_CGC_PLL_FREQ_MUL_26_5         (0x3400U) /* x26.5 */
+#define _3500_CGC_PLL_FREQ_MUL_27_0         (0x3500U) /* x27.0 */
+#define _3600_CGC_PLL_FREQ_MUL_27_5         (0x3600U) /* x27.5 */
+#define _3700_CGC_PLL_FREQ_MUL_28_0         (0x3700U) /* x28.0 */
+#define _3800_CGC_PLL_FREQ_MUL_28_5         (0x3800U) /* x28.5 */
+#define _3900_CGC_PLL_FREQ_MUL_29_0         (0x3900U) /* x29.0 */
+#define _3A00_CGC_PLL_FREQ_MUL_29_5         (0x3A00U) /* x29.5 */
+#define _3B00_CGC_PLL_FREQ_MUL_30_0         (0x3B00U) /* x30.0 */
+
+/*
+    Oscillation Stop Detection Control Register (OSTDCR)
+*/
+/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */
+#define _00_CGC_OSC_STOP_INT_DISABLE        (0x00U) /* The oscillation stop detection interrupt is disabled */
+#define _01_CGC_OSC_STOP_INT_ENABLE         (0x01U) /* The oscillation stop detection interrupt is enabled */
+/* Oscillation Stop Detection Function Enable (OSTDE) */
+#define _00_CGC_OSC_STOP_DISABLE            (0x00U) /* Oscillation stop detection function is disabled */
+#define _80_CGC_OSC_STOP_ENABLE             (0x80U) /* Oscillation stop detection function is enabled */
+
+/*
+    High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2)
+*/
+/* HOCO Frequency Setting (HCFRQ[1:0]) */
+#define _00_CGC_HOCO_CLK_16                 (0x00U) /* 16 MHz */
+#define _01_CGC_HOCO_CLK_18                 (0x01U) /* 18 MHz */
+#define _02_CGC_HOCO_CLK_20                 (0x02U) /* 20 MHz */
+
+/*
+    Main Clock Oscillator Forced Oscillation Control Register (MOFCR)
+*/
+/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */
+#define _00_CGC_MAINOSC_UNDER24M            (0x00U) /* 20.1 to 24 MHz */
+#define _10_CGC_MAINOSC_UNDER20M            (0x10U) /* 16.1 to 20 MHz */
+#define _20_CGC_MAINOSC_UNDER16M            (0x20U) /* 8.1 to 16 MHz */
+#define _30_CGC_MAINOSC_EQUATE8M            (0x30U) /* 8 MHz */
+/* Main Clock Oscillator Switch (MOSEL) */
+#define _00_CGC_MAINOSC_RESONATOR           (0x00U) /* Resonator */
+#define _40_CGC_MAINOSC_EXTERNAL            (0x40U) /* External oscillator input */
+
+/*
+    RTC Control Register 4 (RCR4)
+*/
+/* Count source select */
+#define _00_RTC_SOURCE_SELECT_SUB           (0x00U) /* Select sub-clock oscillator */
+#define _01_RTC_SOURCE_SELECT_MAIN_FORCED   (0x01U) /* Select main clock oscillator */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_CGC_Create(void);
+void R_CGC_Create_UserInit();
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_cgc_user.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_cgc_user.c
new file mode 100644
index 00000000..4ff9f72e
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_cgc_user.c
@@ -0,0 +1,63 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_smc_cgc_user.c
+* Version      : 1.6.102
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements CGC setting.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Create_UserInit
+* Description  : This function adds user code after initializing CGC
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_CGC_Create_UserInit(void)
+{
+    /* Start user code for user init. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_entry.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_entry.h
new file mode 100644
index 00000000..81df189c
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_entry.h
@@ -0,0 +1,56 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_smc_entry.h
+* Version      : 1.2.101
+* Device(s)    : R5F565NEDxFC
+* Description  : SMC platform header file.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef SMC_ENTRY_H
+#define SMC_ENTRY_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "Config_SCI8.h"
+#include "Config_PORT.h"
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_interrupt.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_interrupt.c
new file mode 100644
index 00000000..67515126
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_interrupt.c
@@ -0,0 +1,79 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_smc_interrupt.c
+* Version      : 1.2.0
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements interrupt setting.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_smc_interrupt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Interrupt_Create
+* Description  : This function Used to set the fast interrupt or group interrupt 
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Interrupt_Create(void)
+{
+    /* Disable group BL1 interrupt*/
+    IEN(ICU,GROUPBL1) = 0U;
+    
+    /* Disable group AL1 interrupt*/
+    IEN(ICU,GROUPAL1) = 0U;
+    
+
+    /* Set group BL1 interrupt priority level */
+    IPR(ICU,GROUPBL1) = _0F_ICU_PRIORITY_LEVEL15;
+
+    /* Set group AL1 interrupt priority level */
+    IPR(ICU,GROUPAL1) = _02_ICU_PRIORITY_LEVEL2;
+
+    /* Enable group BL1 interrupt */
+    IEN(ICU,GROUPBL1) = 1U;
+
+    /* Enable group AL1 interrupt */
+    IEN(ICU,GROUPAL1) = 1U;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_interrupt.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_interrupt.h
new file mode 100644
index 00000000..4a273f69
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/general/r_smc_interrupt.h
@@ -0,0 +1,290 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_smc_interrupt.h
+* Version      : 1.2.0
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements interrupt setting.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef SMC_INTERRUPT_H
+#define SMC_INTERRUPT_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/* Priority level of interrupt source. 
+ * These macro definitions are used to set the IPR register directly
+ */
+#define _00_ICU_PRIORITY_LEVEL0                    (0x00U) /* Level 0 (disabled)  */
+#define _01_ICU_PRIORITY_LEVEL1                    (0x01U) /* Level 1  */
+#define _02_ICU_PRIORITY_LEVEL2                    (0x02U) /* Level 2  */
+#define _03_ICU_PRIORITY_LEVEL3                    (0x03U) /* Level 3  */
+#define _04_ICU_PRIORITY_LEVEL4                    (0x04U) /* Level 4  */
+#define _05_ICU_PRIORITY_LEVEL5                    (0x05U) /* Level 5  */
+#define _06_ICU_PRIORITY_LEVEL6                    (0x06U) /* Level 6  */
+#define _07_ICU_PRIORITY_LEVEL7                    (0x07U) /* Level 7  */
+#define _08_ICU_PRIORITY_LEVEL8                    (0x08U) /* Level 8  */
+#define _09_ICU_PRIORITY_LEVEL9                    (0x09U) /* Level 9  */
+#define _0A_ICU_PRIORITY_LEVEL10                   (0x0AU) /* Level 10  */
+#define _0B_ICU_PRIORITY_LEVEL11                   (0x0BU) /* Level 11  */
+#define _0C_ICU_PRIORITY_LEVEL12                   (0x0CU) /* Level 12  */
+#define _0D_ICU_PRIORITY_LEVEL13                   (0x0DU) /* Level 13  */
+#define _0E_ICU_PRIORITY_LEVEL14                   (0x0EU) /* Level 14  */
+#define _0F_ICU_PRIORITY_LEVEL15                   (0x0FU) /* Level 15  */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* The macro definitions below list the full set of priority levels as selected in the Interrupts tab
+ * Please do not modify this file manually
+ */
+#define ICU_BSC_BUSERR_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RAM_RAMERR_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_FCU_FIFERR_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_FCU_FRDYI_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_SWINT2_PRIORITY                    (_01_ICU_PRIORITY_LEVEL1)
+#define ICU_ICU_SWINT_PRIORITY                     (_01_ICU_PRIORITY_LEVEL1)
+#define ICU_CMT0_CMI0_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMT1_CMI1_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMTW0_CMWI0_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMTW1_CMWI1_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_USB0_D0FIFO0_PRIORITY                  (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_USB0_D1FIFO0_PRIORITY                  (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RSPI0_SPRI0_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RSPI0_SPTI0_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RSPI1_SPRI1_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RSPI1_SPTI1_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_QSPI_SPRI_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_QSPI_SPTI_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SDHI_SBFAI_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MMCIF_MBFAI_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RIIC1_RXI1_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RIIC1_TXI1_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RIIC0_RXI0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RIIC0_TXI0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RIIC2_RXI2_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RIIC2_TXI2_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI0_RXI0_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI0_TXI0_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI1_RXI1_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI1_TXI1_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI2_RXI2_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI2_TXI2_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ0_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ1_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ2_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ3_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ4_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ5_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ6_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ7_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ8_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ9_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ10_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ11_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ12_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ13_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ14_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_IRQ15_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI3_RXI3_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI3_TXI3_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI4_RXI4_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI4_TXI4_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI5_RXI5_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI5_TXI5_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI6_RXI6_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI6_TXI6_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_LVD1_LVD1_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_LVD2_LVD2_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_USB0_USBR0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RTC_ALM_PRIORITY                       (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RTC_PRD_PRIORITY                       (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_IWDT_IWUNI_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_WDT_WUNI_PRIORITY                      (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_PDC_PCDFI_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI7_RXI7_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI7_TXI7_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI8_RXI8_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI8_TXI8_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI9_RXI9_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI9_TXI9_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI10_RXI10_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI10_TXI10_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_GROUPBE0_PRIORITY                  (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_GROUPBL2_PRIORITY                  (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RSPI2_SPRI2_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RSPI2_SPTI2_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_GROUPBL0_PRIORITY                  (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_GROUPBL1_PRIORITY                  (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_GROUPAL0_PRIORITY                  (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ICU_GROUPAL1_PRIORITY                  (_02_ICU_PRIORITY_LEVEL2)
+#define ICU_SCI11_RXI11_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI11_TXI11_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI12_RXI12_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_SCI12_TXI12_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_DMAC_DMAC0I_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_DMAC_DMAC1I_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_DMAC_DMAC2I_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_DMAC_DMAC3I_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_DMAC_DMAC74I_PRIORITY                  (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_OST_OSTDI_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_EXDMAC_EXDMAC0I_PRIORITY               (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_EXDMAC_EXDMAC1I_PRIORITY               (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMT2_CMI2_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMT3_CMI3_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU0_TGI0A_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU0_TGI0B_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU0_TGI0C_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU0_TGI0D_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU0_TCI0V_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU1_TGI1B_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU1_TCI1V_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU1_TCI1U_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU2_TGI2A_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU2_TGI2B_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU2_TCI2V_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU2_TCI2U_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU3_TGI3A_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU3_TGI3B_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU1_TGI1A_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU3_TGI3C_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR0_CMIA0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR0_CMIB0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR0_OVI0_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR1_CMIA1_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR1_CMIB1_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR1_OVI1_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR2_CMIA2_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR2_CMIB2_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR2_OVI2_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR3_CMIA3_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR3_CMIB3_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TMR3_OVI3_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU3_TGI3D_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU3_TCI3V_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU4_TGI4A_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU4_TGI4B_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU4_TCI4V_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU4_TCI4U_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU5_TGI5A_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU5_TGI5B_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU5_TCI5V_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TPU5_TCI5U_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMTW0_IC0I0_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMTW0_IC1I0_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMTW0_OC0I0_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMTW0_OC1I0_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMTW1_IC0I1_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMTW1_IC1I1_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMTW1_OC0I1_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CMTW1_OC1I1_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RTC_CUP_PRIORITY                       (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CAN0_RXF0_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CAN0_TXF0_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CAN0_RXM0_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CAN0_TXM0_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CAN1_RXF1_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CAN1_TXF1_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CAN1_RXM1_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_CAN1_TXM1_PRIORITY                     (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_USB0_USBI0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_S12AD_S12ADI_PRIORITY                  (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_S12AD_S12GBADI_PRIORITY                (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_S12AD_S12GCADI_PRIORITY                (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_S12AD1_S12ADI1_PRIORITY                (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_S12AD1_S12GBADI1_PRIORITY              (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_S12AD1_S12GCADI1_PRIORITY              (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_RNG_RNGEND_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ELC_ELSR18I_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_ELC_ELSR19I_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_PROC_BUSY_PRIORITY                (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_ROMOK_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_LONG_PLG_PRIORITY                 (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_TEST_BUSY_PRIORITY                (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_WRRDY0_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_WRRDY1_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_WRRDY4_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_RDRDY0_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_RDRDY1_PRIORITY                   (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_INTEGRATE_WRRDY_PRIORITY          (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_TSIP_INTEGRATE_RDRDY_PRIORITY          (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_PERIB_INTB206_PRIORITY                 (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_PERIB_INTB207_PRIORITY                 (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU1_TGIA1_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU0_TGIA0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU0_TGIB0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU0_TGIC0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU0_TGID0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU0_TCIV0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU0_TGIE0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU0_TGIF0_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU1_TGIB1_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU1_TCIV1_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU1_TCIU1_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU2_TGIA2_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU2_TGIB2_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU2_TCIV2_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU2_TCIU2_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU3_TGIA3_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU3_TGIB3_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU3_TGIC3_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU3_TGID3_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU3_TCIV3_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU4_TGIA4_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU4_TGIB4_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU4_TGIC4_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU4_TGID4_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU4_TCIV4_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU5_TGIU5_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU5_TGIV5_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU5_TGIW5_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU6_TGIA6_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU6_TGIB6_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU6_TGIC6_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU6_TGID6_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU6_TCIV6_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU7_TGIA7_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU7_TGIB7_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU7_TGIC7_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU7_TGID7_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU7_TCIV7_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU8_TGIA8_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU8_TGIB8_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU8_TGIC8_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU8_TGID8_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_MTU8_TCIV8_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_AES_AESRDY_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_AES_AESEND_PRIORITY                    (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_PERIA_INTA253_PRIORITY                 (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_PERIA_INTA254_PRIORITY                 (_0F_ICU_PRIORITY_LEVEL15)
+#define ICU_PERIA_INTA255_PRIORITY                 (_0F_ICU_PRIORITY_LEVEL15)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Interrupt_Create(void);
+#endif
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/hwsetup.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/hwsetup.c
new file mode 100644
index 00000000..f588c408
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/hwsetup.c
@@ -0,0 +1,256 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : hwsetup.c
+* Device(s)    : RX
+* H/W Platform : GENERIC_RX65N
+* Description  : Defines the initialization routines used each time the MCU is restarted.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 15.05.2017 1.00      First Release
+*         : 01.12.2017 1.01      Added EBMAPCR register setting.
+*         : 01.07.2018 1.02      Added the initialization function for Smart Configurator.
+*         : 27.07.2018 1.03      Modified the comment of bsp_adc_initial_configure.
+*         : 28.02.2019 2.00      Added support for GNUC and ICCRX.
+*                                Fixed coding style.
+*                                Added the following function.
+*                                - rom_cache_function_set
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* I/O Register and board definitions */
+#include "platform.h"
+#if BSP_CFG_CONFIGURATOR_SELECT == 1
+#include "r_cg_macrodriver.h"
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+R_BSP_PRAGMA_UNPACK
+typedef struct bsp_bsc {
+    union {
+        uint32_t u_long;
+        R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_13(
+            uint32_t prerr:1,
+            uint32_t :1,
+            uint32_t rpstop:1,
+            uint32_t :10,
+            uint32_t pr5sel:3,
+            uint32_t :1,
+            uint32_t pr4sel:3,
+            uint32_t :1,
+            uint32_t pr3sel:3,
+            uint32_t :1,
+            uint32_t pr2sel:3,
+            uint32_t :1,
+            uint32_t pr1sel:3
+        ) bit;
+    } ebmapcr;
+} st_bsp_bsc_t;
+R_BSP_PRAGMA_PACKOPTION
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+/* ROM cache configuration function declaration */
+#if BSP_CFG_ROM_CACHE_ENABLE == 1
+static void rom_cache_function_set(void);
+#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
+/* MCU I/O port configuration function declaration */
+static void output_ports_configure(void);
+
+/* Interrupt configuration function declaration */
+static void interrupts_configure(void);
+
+/* MCU peripheral module configuration function declaration */
+static void peripheral_modules_enable(void);
+
+/* ADC initial configuration function declaration */
+static void bsp_adc_initial_configure(void);
+
+#if defined(BSP_MCU_RX65N_2MB)
+/* BUS initial configuration function declaration */
+static void bsp_bsc_initial_configure(void);
+#endif/* BSP_MCU_RX65N_2MB */
+
+/***********************************************************************************************************************
+* Function name: hardware_setup
+* Description  : Contains setup functions called at device restart
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+void hardware_setup(void)
+{
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+#if BSP_CFG_ROM_CACHE_ENABLE == 1
+    /* Initialize ROM cache function */
+    rom_cache_function_set();
+#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
+    output_ports_configure();
+    interrupts_configure();
+    peripheral_modules_enable();
+    bsp_non_existent_port_init();
+    bsp_adc_initial_configure();
+#if defined(BSP_MCU_RX65N_2MB)
+    bsp_bsc_initial_configure();
+#endif/* BSP_MCU_RX65N_2MB */
+} /* End of function hardware_setup() */
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+#if BSP_CFG_ROM_CACHE_ENABLE == 1
+/***********************************************************************************************************************
+* Function name: rom_cache_function_set
+* Description  : Configures the rom cache function.
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+static void rom_cache_function_set (void)
+{
+    /* Invalidates the contents of the ROM cache. */
+    FLASH.ROMCIV.WORD = 0x0001;
+    /* WAIT_LOOP */
+    while (FLASH.ROMCIV.WORD != 0x0000)
+    {
+        /* wait for bit to set */
+    }
+
+    /* Enables the ROM cache. */
+    FLASH.ROMCE.WORD = 0x0001;
+    /* WAIT_LOOP */
+    while (FLASH.ROMCE.WORD != 0x0001)
+    {
+        /* wait for bit to set */
+    }
+} /* End of function rom_cache_function_set() */
+#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
+/***********************************************************************************************************************
+* Function name: output_ports_configure
+* Description  : Configures the port and pin direction settings, and sets the pin outputs to a safe level.
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+static void output_ports_configure(void)
+{
+    /* Add code here to setup additional output ports */
+    R_BSP_NOP();
+} /* End of function output_ports_configure() */
+
+/***********************************************************************************************************************
+* Function name: interrupts_configure
+* Description  : Configures interrupts used
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+static void interrupts_configure(void)
+{
+    /* Add code here to setup additional interrupts */
+    R_BSP_NOP();
+} /* End of function interrupts_configure() */
+
+/***********************************************************************************************************************
+* Function name: peripheral_modules_enable
+* Description  : Enables and configures peripheral devices on the MCU
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+static void peripheral_modules_enable(void)
+{
+    /* Add code here to enable peripherals used by the application */
+#if BSP_CFG_CONFIGURATOR_SELECT == 1
+    /* Smart Configurator initialization function */
+    R_Systeminit();
+#endif
+} /* End of function peripheral_modules_enable() */
+
+/***********************************************************************************************************************
+* Function name: bsp_adc_initial_configure
+* Description  : Configures the ADC initial settings
+* Arguments    : none
+* Return value : none
+* Note         : This function should be called when the PSW.I bit is 0 (interrupt disabled).
+*                This function should be called when the ADCSR.ADST bit is 0.
+***********************************************************************************************************************/
+static void bsp_adc_initial_configure(void)
+{
+    uint32_t tmp_mstp;
+
+    /* Protect off. */
+    SYSTEM.PRCR.WORD = 0xA502;
+
+    /* Store the value of the MSTPCR. */
+    tmp_mstp = MSTP(S12AD1);
+
+    /* Release from the module-stop state */
+    MSTP(S12AD1) = 0;
+
+    /* Writing to the A/D conversion time setting register is enabled. */
+    S12AD1.ADSAMPR.BYTE = 0x03;
+
+    /* Sets conversion time for middle-speed for S12AD unit 1. */
+    S12AD1.ADSAM.WORD = 0x0020;
+
+    /* Writing to the A/D conversion time setting register is disabled. */
+    S12AD1.ADSAMPR.BYTE = 0x02;
+
+    /* Restore the value of the MSTPCR. */
+    MSTP(S12AD1) = tmp_mstp;
+
+    /* Protect on. */
+    SYSTEM.PRCR.WORD = 0xA500;
+} /* End of function bsp_adc_initial_configure() */
+
+#if defined(BSP_MCU_RX65N_2MB)
+/***********************************************************************************************************************
+* Function name: bsp_bsc_initial_configure
+* Description  : Configures the BUS initial settings
+* Arguments    : none
+* Return value : none
+* Note         : The EBMAPCR register is only available for products with at least 1.5 Mbytes of code flash memory.
+***********************************************************************************************************************/
+static void bsp_bsc_initial_configure(void)
+{
+    st_bsp_bsc_t bsp_bsc;
+
+    /* Setting priority when bus right request contention occurs. */
+    bsp_bsc.ebmapcr.u_long     = BSC.EBMAPCR.LONG;
+    bsp_bsc.ebmapcr.bit.pr1sel = BSP_CFG_EBMAPCR_1ST_PRIORITY;
+    bsp_bsc.ebmapcr.bit.pr2sel = BSP_CFG_EBMAPCR_2ND_PRIORITY;
+    bsp_bsc.ebmapcr.bit.pr3sel = BSP_CFG_EBMAPCR_3RD_PRIORITY;
+    bsp_bsc.ebmapcr.bit.pr4sel = BSP_CFG_EBMAPCR_4TH_PRIORITY;
+    bsp_bsc.ebmapcr.bit.pr5sel = BSP_CFG_EBMAPCR_5TH_PRIORITY;
+
+    /* Set to EBMAPCR register */
+    BSC.EBMAPCR.LONG = bsp_bsc.ebmapcr.u_long;
+} /* End of function bsp_bsc_initial_configure() */
+#endif/* BSP_MCU_RX65N_2MB */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/hwsetup.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/hwsetup.h
new file mode 100644
index 00000000..3efea2d8
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/hwsetup.h
@@ -0,0 +1,43 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : hwsetup.h
+* Description  : Hardware setup header file.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 01.10.2016 1.00     First Release
+*         : 28.02.2019 1.01     Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef HWSETUP_H
+#define HWSETUP_H
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+void hardware_setup(void); //r_bsp internal function. DO NOT CALL.
+
+/* End of multiple inclusion prevention macro */
+#endif
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/r_bsp.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/r_bsp.h
new file mode 100644
index 00000000..ec4e13af
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/r_bsp.h
@@ -0,0 +1,106 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp.h
+* H/W Platform : GENERIC_RX65N
+* Description  : Has the header files that should be included for this platform.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 15.05.2017 1.00     First Release
+*         : 01.07.2018 1.01     Additional RTOS header file.
+*         : 28.02.2019 2.00     Added the following include path.
+*                                - r_rx_compiler.h
+*                                - r_rtos.h
+*                                - r_bsp_interrupts.h
+*                                - mcu_clocks.h
+*                                - r_rx_intrinsic_functions.h
+*                               Modified the following include path.
+*                                - lowsrc.h
+*                                - r_bsp_mcu_startup.h
+*                                - vecttbl.h
+*                               Added support for GNUC and ICCRX.
+*                               Fixed coding style.
+*         : 08.10.2019 2.01     Added the following include path.
+*                                - r_bsp_software_interrupt.h
+*                               Changed include of iodefine.h for CS+ and RX651.
+*                               Changed include of r_bsp_config.h for added support of Renesas RTOS(RI600V4 or RI600PX).
+***********************************************************************************************************************/
+
+/* Make sure that no other platforms have already been defined. Do not touch this! */
+#ifdef  PLATFORM_DEFINED
+#error  "Error - Multiple platforms defined in platform.h!"
+#else
+#define PLATFORM_DEFINED
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***********************************************************************************************************************
+INCLUDE APPROPRIATE MCU AND BOARD FILES
+***********************************************************************************************************************/
+#include    "mcu/all/r_bsp_common.h"
+#include    "r_bsp_config.h"
+#include    "mcu/all/r_rx_compiler.h"
+
+#include    "r_bsp_interrupt_config.h"
+
+#include    "mcu/all/lowlvl.h"
+#include    "mcu/all/lowsrc.h"
+#include    "mcu/all/r_bsp_mcu_startup.h"
+
+#ifndef __RX651IODEFINE_HEADER__
+#define __RX651IODEFINE_HEADER__
+#if defined(__CCRX__)
+#include    "mcu/rx65n/register_access/ccrx/iodefine.h"
+#elif defined(__GNUC__)
+#include    "mcu/rx65n/register_access/gnuc/iodefine.h"
+#elif defined(__ICCRX__)
+#include    "mcu/rx65n/register_access/iccrx/iodefine.h"
+#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */
+#endif /* __RX651IODEFINE_HEADER__ */
+#include    "mcu/rx65n/r_bsp_cpu.h"
+#include    "mcu/rx65n/r_bsp_locking.h"
+#include    "mcu/rx65n/mcu_clocks.h"
+#include    "mcu/rx65n/mcu_info.h"
+#include    "mcu/rx65n/mcu_init.h"
+#include    "mcu/rx65n/mcu_interrupts.h"
+#include    "mcu/rx65n/mcu_locks.h"
+#include    "mcu/rx65n/mcu_mapped_interrupts_private.h"
+#include    "mcu/rx65n/mcu_mapped_interrupts.h"
+#include    "mcu/rx65n/vecttbl.h"
+
+#include    "board/generic_rx65n/hwsetup.h"
+
+#include    "mcu/all/r_bsp_interrupts.h"
+#include    "mcu/all/r_bsp_software_interrupt.h"
+#include    "mcu/all/r_rx_intrinsic_functions.h"
+#include    "mcu/all/r_rtos.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifndef BSP_BOARD_GENERIC_RX65N
+#define BSP_BOARD_GENERIC_RX65N
+
+#endif /* BSP_BOARD_GENERIC_RX65N */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/r_bsp_config_reference.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/r_bsp_config_reference.h
new file mode 100644
index 00000000..731fd457
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/r_bsp_config_reference.h
@@ -0,0 +1,654 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_config_reference.h
+* Device(s)    : RX65N
+* Description  : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+*                somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+*                is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 15.05.2017 1.00      First Release
+*         : 01.12.2017 1.01      Added the following macro definition.
+*                                - BSP_CFG_EBMAPCR_1ST_PRIORITY
+*                                - BSP_CFG_EBMAPCR_2ND_PRIORITY
+*                                - BSP_CFG_EBMAPCR_3RD_PRIORITY
+*                                - BSP_CFG_EBMAPCR_4TH_PRIORITY
+*                                - BSP_CFG_EBMAPCR_5TH_PRIORITY
+*         : 01.07.2018 1.02      Added the following macro definition.
+*                                - BSP_CFG_CONFIGURATOR_SELECT
+*                                Add RTOS support. FreeRTOS. Define a timer for RTOS.
+*         : 27.07.2018 1.03      Modified the comment of PLL clock source.
+*                                Added the following macro definition for ID code protection.
+*                                 - BSP_CFG_ID_CODE_LONG_1
+*                                 - BSP_CFG_ID_CODE_LONG_2
+*                                 - BSP_CFG_ID_CODE_LONG_3
+*                                 - BSP_CFG_ID_CODE_LONG_4
+*                                Added the following macro definition.
+*                                 - BSP_CFG_FIT_IPL_MAX
+*         : 31.10.2018 1.04      Added support for RX651 with 64 pin package.
+*         : 28.02.2019 2.00      Added support for GNUC and ICCRX.
+*                                Fixed coding style.
+*         : 26.07.2019 2.01      Modified comment.
+*         : 08.10.2019 2.02      Added the following macro definition.
+*                                - BSP_CFG_SWINT_UNIT1_ENABLE
+*                                - BSP_CFG_SWINT_UNIT2_ENABLE
+*                                - BSP_CFG_SWINT_TASK_BUFFER_NUMBER
+*                                - BSP_CFG_SWINT_IPR_INITIAL_VALUE
+*                                Modified comment for added support of Renesas RTOS (RI600V4 or RI600PX).
+*                                Added the following macro definition.
+*                                - BSP_CFG_RENESAS_RTOS_USED
+*         : 31.07.2020 2.03      Modified comment.
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* NOTE:
+   The default settings are the same as when using RSKRX65N-2MB.
+   Change to the settings for the user board.
+*/
+
+/* Start up select
+   0 = Enable BSP startup program.
+   1 = Disable BSP startup program. (e.g. Using user startup program.)
+   NOTE: This setting is available only when using CCRX. */
+#define BSP_CFG_STARTUP_DISABLE (0)
+
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such 
+   as package and memory size.
+   To help parse this information, the part number will be defined using multiple macros.
+   R 5 F 56 5N E D D FP
+   | | | |  |  | | | |  Macro Name                             Description
+   | | | |  |  | | | |__BSP_CFG_MCU_PART_PACKAGE             = Package type, number of pins, and pin pitch
+   | | | |  |  | | |____not used                             = Products with wide temperature range
+   | | | |  |  | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included
+   | | | |  |  |________BSP_CFG_MCU_PART_MEMORY_SIZE         = ROM, RAM, and Data Flash Capacity
+   | | | |  |___________BSP_CFG_MCU_PART_GROUP               = Group name
+   | | | |______________BSP_CFG_MCU_PART_SERIES              = Series name
+   | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE         = Type of memory (Flash, ROMless)
+   | |__________________not used                             = Renesas MCU
+   |____________________not used                             = Renesas semiconductor product.
+*/
+
+/* Package type. Set the macro definition based on values below:
+   Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+   FC           = 0x0             = LFQFP/176/0.50
+   BG           = 0x1             = LFBGA/176/0.80
+   LC           = 0x2             = TFLGA/177/0.50
+   FB           = 0x3             = LFQFP/144/0.50
+   LK           = 0x4             = TFLGA/145/0.50
+   FP           = 0x5             = LFQFP/100/0.50
+   FM           = 0x8             = LFQFP/64/0.50
+   LJ           = 0xA             = TFLGA/100/0.65
+   BP           = 0xC             = TFBGA/64/0.50
+*/
+#define BSP_CFG_MCU_PART_PACKAGE        (0x0)
+
+/* Whether Encryption and SDHI/SDSI are included or not.
+   Character(s) = Value for macro = Description
+   A            = false           = Encryption module not included, SDHI/SDSI module not included
+   B            = false           = Encryption module not included, SDHI/SDSI module included
+   D            = false           = Encryption module not included, SDHI/SDSI module included, dual-bank structure
+   E            = true            = Encryption module included, SDHI/SDSI module not included
+   F            = true            = Encryption module included, SDHI/SDSI module included
+   H            = true            = Encryption module included, SDHI/SDSI module included, dual-bank structure
+*/
+#define BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED   (false)
+
+/* ROM, RAM, and Data Flash Capacity.
+   Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+   4            = 0x4             = 512KB/256KB/Not equipped
+   7            = 0x7             = 768KB/256KB/Not equipped
+   9            = 0x9             = 1MB/256KB/Not equipped
+   C            = 0xC             = 1.5MB/640KB/32KB
+   E            = 0xE             = 2MB/640KB/32KB
+   NOTE: When the RAM capacity is 640KB, the RAM areas are not contiguous.
+*/
+#define BSP_CFG_MCU_PART_MEMORY_SIZE    (0xE)
+
+/* Group name.
+   Character(s) = Value for macro = Description
+   5N/51        = 0x0             = RX65N Group/RX651 Group
+*/
+#define BSP_CFG_MCU_PART_GROUP          (0x0)
+
+/* Series name.
+   Character(s) = Value for macro = Description
+   56           = 0x0             = RX600 Series
+*/
+#define BSP_CFG_MCU_PART_SERIES         (0x0)
+
+/* Memory type.
+   Character(s) = Value for macro = Description
+   F            = 0x0             = Flash memory version
+*/
+#define BSP_CFG_MCU_PART_MEMORY_TYPE    (0x0)
+
+/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack.
+ * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU
+ * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how
+ * much stack space to allocate since the user does not have to worry about always having enough room on the
+ * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not
+ * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used).
+ * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then
+ * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings.
+ *
+ * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored.
+ * 1 = Use 2 stacks. User stack and interrupt stack will both be used.
+ * NOTE: This setting is available only when using CCRX and GNUC.
+ *       This is invalid when using Renesas RTOS with CCRX.
+ */
+#define BSP_CFG_USER_STACK_ENABLE       (1)
+
+/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */
+#if BSP_CFG_USER_STACK_ENABLE == 1
+/* User Stack size in bytes.
+ * NOTE: This setting is available only when using CCRX and GNUC.
+ *       This is invalid when using Renesas RTOS with CCRX. */
+#define BSP_CFG_USTACK_BYTES            (0x1000)
+#endif
+
+/* Interrupt Stack size in bytes.
+   NOTE: This setting is available only when using CCRX and GNUC. */
+#define BSP_CFG_ISTACK_BYTES            (0x400)
+
+/* Heap size in bytes.
+   To disable the heap you must follow these steps:
+   1) Set this macro (BSP_CFG_HEAP_BYTES) to 0.
+   2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0.
+   3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain 
+      settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio.
+      This will present a list of modules that can be included. Uncheck the box for stdio.h.
+   NOTE: This setting is available only when using CCRX and GNUC. */
+#define BSP_CFG_HEAP_BYTES              (0x400)
+
+/* Initializes C input & output library functions.
+   0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+   1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio.
+   NOTE: This setting is available only when using CCRX. */
+#define BSP_CFG_IO_LIB_ENABLE           (1)
+
+/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions
+   by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */
+#define BSP_CFG_USER_CHARGET_ENABLED    (0)
+#define BSP_CFG_USER_CHARGET_FUNCTION     my_sw_charget_function
+
+#define BSP_CFG_USER_CHARPUT_ENABLED    (0)
+#define BSP_CFG_USER_CHARPUT_FUNCTION     my_sw_charput_function
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+   on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+   0 = Stay in Supervisor mode.
+   1 = Switch to User mode.
+   NOTE: This is invalid when using Renesas RTOS with CCRX.
+*/
+#define BSP_CFG_RUN_IN_USER_MODE        (0)
+
+/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set 
+   this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for 
+   it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging.
+   If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using 
+   FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */
+/* Lowest 4-byte section, address 0xFE7F5D50. From MSB to LSB: ID code 4, ID code 3, ID code 2, ID code 1/Control Code.
+ */
+#define BSP_CFG_ID_CODE_LONG_1          (0xFFFFFFFF)
+/* 2nd ID Code section, address 0xFE7F5D54. From MSB to LSB: ID code 8, ID code 7, ID code 6, ID code 5. */
+#define BSP_CFG_ID_CODE_LONG_2          (0xFFFFFFFF)
+/* 3rd ID Code section, address 0xFE7F5D58. From MSB to LSB: ID code 12, ID code 11, ID code 10, ID code 9. */
+#define BSP_CFG_ID_CODE_LONG_3          (0xFFFFFFFF)
+/* 4th ID Code section, address 0xFE7F5D5C. From MSB to LSB: ID code 16, ID code 15, ID code 14, ID code 13. */
+#define BSP_CFG_ID_CODE_LONG_4          (0xFFFFFFFF)
+
+/* Clock source select (CKSEL).
+   0 = Low Speed On-Chip Oscillator  (LOCO)
+   1 = High Speed On-Chip Oscillator (HOCO)
+   2 = Main Clock Oscillator
+   3 = Sub-Clock Oscillator
+   4 = PLL Circuit
+*/
+#define BSP_CFG_CLOCK_SOURCE            (4)
+
+/* Main clock Oscillator Switching (MOSEL).
+   0 = Resonator
+   1 = External clock input
+*/
+#define BSP_CFG_MAIN_CLOCK_SOURCE       (0)
+
+/* The sub-clock oscillation control for using the RTC.
+   When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated.
+   0 = The RTC is not to be used.
+   1 = The RTC is to be used.
+*/
+#define BSP_CFG_RTC_ENABLE              (0)
+
+/* Sub-Clock Oscillator Drive Capacity Control (RTCDV).
+   0 = Drive capacity for standard CL. (default)
+   1 = Drive capacity for low CL.
+*/
+#define BSP_CFG_SOSC_DRV_CAP            (0)
+
+/* Clock configuration options.
+   The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+   multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the
+   ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, USB Clock is 48MHz,
+   and BCLK is 120MHz then the settings would be:
+
+   BSP_CFG_XTAL_HZ  = 24000000
+   BSP_CFG_PLL_DIV  = 1        (no division)
+   BSP_CFG_PLL_MUL  = 10.0     (24MHz x 10.0 = 240MHz)
+   BSP_CFG_ICK_DIV  = 2      : System Clock (ICLK)        = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV)  = 120MHz
+   BSP_CFG_PCKA_DIV = 2      : Peripheral Clock A (PCLKA) = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz
+   BSP_CFG_PCKB_DIV = 4      : Peripheral Clock B (PCLKB) = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz
+   BSP_CFG_PCKC_DIV = 4      : Peripheral Clock C (PCLKC) = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz
+   BSP_CFG_PCKD_DIV = 4      : Peripheral Clock D (PCLKD) = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz
+   BSP_CFG_FCK_DIV  = 4      : Flash IF Clock (FCLK)      = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV)  = 60MHz
+   BSP_CFG_BCK_DIV  = 2      : External Bus Clock (BCK)   = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV)  = 120MHz
+   BSP_CFG_UCK_DIV  = 5      : USB Clock (UCLK)           = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV)  = 48MHz
+*/
+
+/* Input clock frequency in Hz (XTAL or EXTAL). */
+#define BSP_CFG_XTAL_HZ                 (24000000)
+
+/* The HOCO can operate at several different frequencies. Choose which one using the macro below.
+   Available frequency settings:
+   0 = 16MHz (default)
+   1 = 18MHz
+   2 = 20MHz
+*/
+#define BSP_CFG_HOCO_FREQUENCY          (0)
+
+/* PLL clock source (PLLSRCSEL). Choose which clock source to input to the PLL circuit.
+   Available clock sources:
+   0 = Main clock (default)
+   1 = HOCO
+*/
+#define BSP_CFG_PLL_SRC                 (0)
+
+/* PLL Input Frequency Division Ratio Select (PLIDIV).
+   Available divisors = /1 (no division), /2, /3
+*/
+#define BSP_CFG_PLL_DIV                 (1)
+
+/* PLL Frequency Multiplication Factor Select (STC).
+   Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0)
+*/
+#define BSP_CFG_PLL_MUL                 (10.0)
+
+/* System Clock Divider (ICK).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_ICK_DIV                 (2)
+
+/* Peripheral Module Clock A Divider (PCKA).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKA_DIV                (2)
+
+/* Peripheral Module Clock B Divider (PCKB).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKB_DIV                (4)
+
+/* Peripheral Module Clock C Divider (PCKC).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKC_DIV                (4)
+
+/* Peripheral Module Clock D Divider (PCKD).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKD_DIV                (4)
+
+/* External Bus Clock Divider (BCLK).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_BCK_DIV                 (2)
+
+/* Flash IF Clock Divider (FCK).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_FCK_DIV                 (4)
+
+/* USB Clock Divider Select.
+   Available divisors = /2, /3, /4, /5
+*/
+#define BSP_CFG_UCK_DIV                 (5)
+
+/* Configure BCLK output pin (only effective when external bus enabled)
+   Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency
+*/
+#define BSP_CFG_BCLK_OUTPUT             (0)
+
+/* Configure SDCLK output pin (only effective when external bus enabled)
+   Values 0=no output, 1 = BCK frequency
+*/
+#define BSP_CFG_SDCLK_OUTPUT            (0)
+
+/* Main Clock Oscillator Wait Time (MOSCWTCR).
+   The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable 
+   oscillation by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below.
+
+   BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32
+   (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO)
+
+   If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives 
+   BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h).
+
+   NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator.
+         Set the BSP_CFG_MOSC_WAIT_TIME to 00h.
+*/
+#define BSP_CFG_MOSC_WAIT_TIME          (0x53)
+
+/* Sub-Clock Oscillator Wait Time (SOSCWTCR).
+   The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation
+   by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below.
+
+   BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384
+   (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO)
+
+   If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives
+    BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the  BSP_CFG_SOSC_WAIT_TIME bits to 33(21h).
+*/
+#define BSP_CFG_SOSC_WAIT_TIME          (0x21)
+
+/* ROM Cache Enable Register (ROMCE).
+   0 = ROM cache operation disabled.
+   1 = ROM cache operation enabled.
+*/
+#define BSP_CFG_ROM_CACHE_ENABLE        (0)
+
+/* Configure WDT and IWDT settings.
+   OFS0 - Option Function Select Register 0
+       b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1.
+       b28     WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+       b27:b26 WDTRPSS   - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+       b25:b24 WDTRPES   - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+       b23:b20 WDTCKS    - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256,
+                                                                 7=PCLKB/2048, 8=PCLKB/8192)
+       b19:b18 WDTTOPS   - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384)
+       b17     WDTSTRT   - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+       b16:b15 Reserved (set to 1)
+       b14     IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+       b13     Reserved (set to 1)
+       b12     IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+       b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+       b9:b8   IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+       b7:b4   IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+       b3:b2   IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384)
+       b1      IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+       b0      Reserved (set to 1)
+   Default value is 0xFFFFFFFF.
+*/
+#define BSP_CFG_OFS0_REG_VALUE  (0xFFFFFFFF)
+
+/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset.
+   OFS1 - Option Function Select Register 1
+       b31:b9 Reserved (set to 1)
+       b8     HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+       b7:b3  Reserved When reading, these bits return the value written by the user. The write value should be 1.
+       b2     LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled)
+       b1:b0  VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v)
+       NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz.
+             BSP_CFG_HOCO_FREQUENCY should be default value.
+   Default value is 0xFFFFFFFF.
+*/
+#define BSP_CFG_OFS1_REG_VALUE  (0xFFFFFFFF)
+
+/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 46 and 47 (in dual mode) in 
+   the code flash memory by third party software. This feature is disabled by default.
+   TMEF - TM Enable Flag Register
+       b31     Reserved (set to 1)
+       b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFEE 0000h to 
+                                                   FFEE FFFFh is enabled in dual mode.
+                                            - 111: The TM function in the address range from FFEE 0000h to 
+                                                   FFEE FFFFh is disabled in dual mode.
+       b27     Reserved (set to 1)
+       b26:b24 TMEF   - TM Enable - 000: TM function is enabled.
+                                  - 111: TM function is disabled.
+       b23:b0  Reserved (set to 1)
+       NOTE: If the dual bank function has not been incorporated in a device,
+             TMEFDB bits [b30:b26] are reserved area.
+   Default value is 0xFFFFFFFF.
+*/
+#define BSP_CFG_TRUSTED_MODE_FUNCTION  (0xFFFFFFFF)
+
+/* Configure FAW register is used to set the write protection flag and boot area select flag 
+   for setting the flash access window startaddress and flash access window end address.
+   FAW - Flash Access Window Setting Register
+       b31      BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area
+                                              - 1: FFFF E000h to FFFF FFFFh are used as the boot area
+       b30:b28  Reserved - When reading, these bits return the value written by the user.The write value should be 1.
+       b27:b16  FAWE - Flash Access Window End Address - Flash access window end address
+       b15      FSPR - Access Window Protection Flag - 0: With protection (P/E disabled)
+                                                     - 1: Without protection (P/E enabled)
+       b14:b12  Reserved - When reading, these bits return the value written by the user.The write value should be 1.
+       b11:b0   FAWS - Flash Access Window Start Address - Flash access window start address 
+       NOTE: Once 0 is written to this bit, the bit can never be restored to 1.
+             Therefore, the access window and the BTFLG bit never be set again or the TM function 
+             never be disabled once it has been enabled.
+             Exercise extra caution when handling the FSPR bit.
+   Default value is 0xFFFFFFFF.
+*/
+#define BSP_CFG_FAW_REG_VALUE  (0xFFFFFFFF)
+
+/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory
+   when the flash programmer is used during off-board programming.
+   ROMCODE - ROM Code Protection Register
+       b31:b0  ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1).
+                          0000 0001h: ROM code protection enabled (ROM code protection 2).
+                          Other than above: ROM code protection disabled.
+       Note: The ROMCODE register should be set in 32-bit units.
+   Default value is 0xFFFFFFFF.
+*/
+#define BSP_CFG_ROMCODE_REG_VALUE  (0xFFFFFFFF)
+
+/* Select the bank mode of dual-bank function of the code flash memory.
+   0 = Dual mode.
+   1 = Linear mode. (default)
+   NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro.
+         Default setting of the bank mode is linear mode.
+         If the dual bank function has not been incorporated in a device, this macro should be 1.
+*/
+#define BSP_CFG_CODE_FLASH_BANK_MODE    (1)
+
+/* Select the startup bank of the program when dual bank function is in dual mode.
+   0 = The address range of bank 1 from FFE00000h to FFEFFFFFh and bank 0 from FFF00000h to FFFFFFFFh. (default)
+   1 = The address range of bank 1 from FFF00000h to FFFFFFFFh and bank 0 from FFE00000h to FFEFFFFFh.
+   NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro.
+         Default setting of the start bank is bank0.
+         If the dual bank function has not been incorporated in a device, this macro should be 0.
+*/
+#define BSP_CFG_CODE_FLASH_START_BANK   (0)
+
+/* This macro lets other modules no if a RTOS is being used.
+   0 = RTOS is not used.
+   1 = FreeRTOS is used.
+   2 = embOS is used.(This is not available.)
+   3 = MicroC_OS is used.(This is not available.)
+   4 = Renesas ITRON OS (RI600V4 or RI600PX) is used.
+*/
+#define BSP_CFG_RTOS_USED               (0)
+
+/* This macro is used to select which Renesas ITRON OS.
+   0 = RI600V4 is used.
+   1 = RI600PX is used.
+*/
+#define BSP_CFG_RENESAS_RTOS_USED       (0)
+
+/* This macro is used to select which CMT channel used for system timer of RTOS.
+ * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */
+#if BSP_CFG_RTOS_USED != 0
+/* Setting value.
+ * 0      = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS).
+ * 1      = CMT channel 1 used for system timer of RTOS.
+ * 2      = CMT channel 2 used for system timer of RTOS.
+ * 3      = CMT channel 3 used for system timer of RTOS.
+ * Others = Invalid.
+ * NOTE: This is invalid when using Renesas RTOS with CCRX.
+ */
+#define BSP_CFG_RTOS_SYSTEM_TIMER       (0)
+#endif
+
+/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its
+   locking mechanisms then they can change this macro.
+   NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'.
+   0 = Use default locking (non-RTOS)
+   1 = Use user defined locking mechanism.
+*/
+#define BSP_CFG_USER_LOCKING_ENABLED    (0)
+
+/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef
+   that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be 
+   a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks.
+   NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored.
+   NOTE: Do not surround the type with parentheses '(' ')'.
+*/
+#define BSP_CFG_USER_LOCKING_TYPE       bsp_lock_t
+
+/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions
+   that will handle the locking and unlocking. These functions should be defined below.
+   If BSP_CFG_USER_LOCKING_ENABLED is != 0:
+   R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index)
+   R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index)
+       NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter.
+   R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call 
+   BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock)
+   R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call 
+   BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock)
+       NOTE:With these functions the actual address of the lock to use is passed as the parameter.
+   NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, 
+         return false.
+   NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored.
+   NOTE: Do not surround the type with parentheses '(' ')'.
+*/
+#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION      my_hw_locking_function
+#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION    my_hw_unlocking_function
+#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION      my_sw_locking_function
+#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION    my_sw_unlocking_function
+
+/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the
+   following callback definitions AND provide a call back function name for the respective callback
+   function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result
+   in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C
+   runtime environment by resetprg.
+   Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined
+   my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg.
+*/
+#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED    (0)
+#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION     my_sw_warmstart_prec_function
+
+#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED    (0)
+#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION    my_sw_warmstart_postc_function
+
+/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users
+   will want to disable this for production code. The reason for this would be to save execution time and code space.
+   This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its
+   own local macro for this same purpose. By default the local macros will take the global value from here though
+   they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter
+   checking should only used when inputs are known to be good and the increase in speed or decrease in code space is 
+   needed.
+   0 = Global setting for parameter checking is disabled.
+   1 = Global setting for parameter checking is enabled (Default).
+*/
+#define BSP_CFG_PARAM_CHECKING_ENABLE               (1)
+
+/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC
+   graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and
+   display list data read).
+   The default priority order in bsp is below
+   GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC.
+   Priority can be changed with this macro.
+
+   Extended Bus Master Priority setting
+   0 = GLCDC graphics 1 data read
+   1 = DRW2D texture data read
+   2 = DRW2D frame buffer data read write and display list data read
+   3 = GLCDC graphics 2 data read
+   4 = EDMAC
+
+   Note : This macro is only available for products with at least 1.5 Mbytes of code flash memory.
+          Settings other than above are prohibited.
+          Duplicate priority settings can not be made.
+*/
+#define BSP_CFG_EBMAPCR_1ST_PRIORITY                (0) /* Extended Bus Master 1st Priority Selection */
+#define BSP_CFG_EBMAPCR_2ND_PRIORITY                (3) /* Extended Bus Master 2nd Priority Selection */
+#define BSP_CFG_EBMAPCR_3RD_PRIORITY                (1) /* Extended Bus Master 3rd Priority Selection */
+#define BSP_CFG_EBMAPCR_4TH_PRIORITY                (2) /* Extended Bus Master 4th Priority Selection */
+#define BSP_CFG_EBMAPCR_5TH_PRIORITY                (4) /* Extended Bus Master 5th Priority Selection */
+
+/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This
+   macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */
+#define BSP_CFG_MCU_VCC_MV                          (3300)
+
+/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool.
+   When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0.
+   0 = Disabled (default)
+   1 = Smart Configurator initialization code used
+*/
+#define BSP_CFG_CONFIGURATOR_SELECT                 (0)
+
+/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other 
+   FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the 
+   specified interrupt priority level.
+   This macro sets the IPL. Range is 0x0 - 0xF.
+   Please set this macro more than IPR for other FIT module interrupts.
+   The default value is 0xF (maximum value).
+   Don't change if there is no special processing with higher priority than all fit modules.
+*/
+#define BSP_CFG_FIT_IPL_MAX                         (0xF)
+
+/* Software Interrupt (SWINT).
+   0 = Software interrupt is not used.
+   1 = Software interrupt is used.
+   NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. 
+*/
+#define BSP_CFG_SWINT_UNIT1_ENABLE    (1)
+#define BSP_CFG_SWINT_UNIT2_ENABLE    (1)
+
+/* Software Interrupt Task Buffer Number.
+   For software interrupt, this value is number of buffering user tasks.
+   So user can increase this value if user system would have many software interrupt tasks
+   and user system has enough buffer. This value requires 9 byte per task.
+   NOTE: This setting is common to all units. It can not be set individually. 
+         The maximum value is 254.
+*/
+#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER     (8)
+
+/* Initial value of the software interrupt priority.
+   For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF.
+   NOTE: This setting is common to all units. It can not be set individually. 
+         Please be careful that this setting is the initial value of the interrupt priority register(IPR).
+         It is possible to dynamically change the IPR.
+*/
+#define BSP_CFG_SWINT_IPR_INITIAL_VALUE     (0x1)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/r_bsp_interrupt_config_reference.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/r_bsp_interrupt_config_reference.h
new file mode 100644
index 00000000..39237823
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/generic_rx65n/r_bsp_interrupt_config_reference.h
@@ -0,0 +1,214 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer 
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_interrupt_config.h
+* Description  : This module maps Interrupt A & B interrupts. More information on how this is done is given below.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 01.10.2016 1.00      First Release
+*         : 15.05.2017 2.00      Changed the name of the following macro definition, because there was a mistake
+*                                in the name of macro definition.
+*                                - From XXX_TPU0_TGI0V to XXX_TPU0_TCI0V.
+*                                - From XXX_TPU1_TGI1V to XXX_TPU1_TCI1V.
+*                                - From XXX_TPU1_TGI1U to XXX_TPU1_TCI1U.
+*                                - From XXX_TPU2_TGI2V to XXX_TPU2_TCI2V.
+*                                - From XXX_TPU2_TGI2U to XXX_TPU2_TCI2U.
+*                                - From XXX_TPU3_TGI3V to XXX_TPU3_TCI3V.
+*                                - From XXX_TPU4_TGI4V to XXX_TPU4_TCI4V.
+*                                - From XXX_TPU4_TGI4U to XXX_TPU4_TCI4U.
+*                                - From XXX_TPU5_TGI5V to XXX_TPU5_TCI5V.
+*                                - From XXX_TPU5_TGI5U to XXX_TPU5_TCI5U.
+*                                - From XXX_MTU0_TGIV0 to XXX_MTU0_TCIV0.
+*                                - From XXX_MTU1_TGIV1 to XXX_MTU1_TCIV1.
+*                                - From XXX_MTU1_TGIU1 to XXX_MTU1_TCIU1.
+*                                - From XXX_MTU2_TGIV2 to XXX_MTU2_TCIV2.
+*                                - From XXX_MTU2_TGIU2 to XXX_MTU2_TCIU2.
+*                                - From XXX_MTU3_TGIV3 to XXX_MTU3_TCIV3.
+*                                - From XXX_MTU4_TGIV4 to XXX_MTU4_TCIV4.
+*                                - From XXX_MTU6_TGIV6 to XXX_MTU6_TCIV6.
+*                                - From XXX_MTU7_TGIV7 to XXX_MTU7_TCIV7.
+*                                - From XXX_MTU8_TGIV8 to XXX_MTU8_TCIV8.
+*                                Added select processing of the following software configurable interrupt source.
+*                                - TSIP_PROC_BUSY
+*                                - TSIP_ROMOK
+*                                - TSIP_LONG_PLG
+*                                - TSIP_TEST_BUSY
+*                                - TSIP_WRRDY0
+*                                - TSIP_WRRDY1
+*                                - TSIP_WRRDY4
+*                                - TSIP_RDRDY0
+*                                - TSIP_RDRDY1
+*                                - TSIP_INTEGRATE_WRRDY
+*                                - TSIP_INTEGRATE_RDRDY
+***********************************************************************************************************************/
+#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE
+#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you
+ * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you
+ * would do the following:
+ *
+ * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP                                 176
+ */
+
+/* Interrupt B Sources.
+ * -Valid vector numbers are 128-207.
+ * -There are more vector slots for B sources than actual B sources. By default all B sources are mapped.
+ * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default.
+ * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be
+ *  in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0'
+ *  interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots.
+ */
+#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2                               128
+#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3                               129
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0                              146
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0                              147
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0                               148
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1                              149
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1                              150
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1                               151
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2                              152
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2                              153
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2                               154
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3                              155
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3                              156
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3                               157
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A                              130
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B                              131
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C                              132
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D                              133
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V                              134
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A                              144
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B                              135
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V                              136
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U                              137
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A                              138
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B                              139
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V                              140
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U                              141
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A                              142
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B                              143
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C                              145
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D                              158
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V                              159
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A                              160
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B                              161
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V                              162
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U                              163
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A                              164
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B                              165
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V                              166
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U                              167
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0                             168
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0                             169
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0                             170
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0                             171
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1                             172
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1                             173
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1                             174
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1                             175
+#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP                                 176
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0                               177
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0                               178
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0                               179
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0                               180
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1                               181
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1                               182
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1                               183
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1                               184
+#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0                              185
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0                         186
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0                       187
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0                       188
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1                         189
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1                       190
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1                       191
+#define BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND                              192
+#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I                             193
+#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I                             194
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY                          195
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK                              196
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG                           197
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY                          198
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0                             199
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1                             200
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4                             201
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0                             202
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1                             203
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY                    204
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY                    205
+
+/* Interrupt A Sources.
+ * -Valid vector numbers are 208-255.
+ * -There are more A sources than A vector slots. By default none of the GPT interrupts are mapped.
+ * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default.
+ */
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0                              209
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0                              210
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0                              211
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0                              212
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0                              213
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0                              214
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0                              215
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1                              208
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1                              216
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1                              217
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1                              218
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2                              219
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2                              220
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2                              221
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2                              222
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3                              223
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3                              224
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3                              225
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3                              226
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3                              227
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4                              228
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4                              229
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4                              230
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4                              231
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4                              232
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5                              233
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5                              234
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5                              235
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6                              236
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6                              237
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6                              238
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6                              239
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6                              240
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7                              241
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7                              242
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7                              243
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7                              244
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7                              245
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8                              246
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8                              247
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8                              248
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8                              249
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8                              250
+#define BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY                              251
+#define BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND                              252
+
+#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/user/r_bsp.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/user/r_bsp.h
new file mode 100644
index 00000000..94ecab16
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/board/user/r_bsp.h
@@ -0,0 +1,54 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer 
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.    
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp.h 
+* Description  : Has the header files that should be included for this platform.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 13.01.2012 1.00     First Release
+*         : 27.06.2012 1.10     Updated with new information to reflect udpated r_bsp structure.
+***********************************************************************************************************************/
+
+#ifndef BSP_BOARD_USER
+#define BSP_BOARD_USER
+
+/* Make sure that no other platforms have already been defined. Do not touch this! */
+#ifdef  PLATFORM_DEFINED
+#error  "Error - Multiple platforms defined in platform.h!"
+#else
+#define PLATFORM_DEFINED
+#endif
+
+/***********************************************************************************************************************
+INCLUDE APPROPRIATE MCU AND BOARD FILES
+***********************************************************************************************************************/
+/* This is a user defined board. Start off by:
+   1)Copy and rename one of the 'board' folders that most closely matches your system (same MCU Series and Group).
+   2)Substitute in your MCU Group for the *MCU Group* option in the #include below for mcu_info.h.
+   3)Copy the other #includes from the r_bsp.h in the 'board' folder that you copied earlier.
+   4)Configure the BSP for your board by modifying the r_bsp_config_reference.h.
+   5)Copy r_bsp_config_reference.h to your project directory and rename it r_bsp_config.h.
+   You can also add your own include files here as well. */
+#include    "r_bsp_config.h"
+#include    "mcu/*MCU Group*/mcu_info.h"           
+
+#endif /* BSP_BOARD_USER */
+
+
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diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/dbsct.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/dbsct.c
new file mode 100644
index 00000000..9f71dec6
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/dbsct.c
@@ -0,0 +1,133 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : dbsct.c
+* Description  : Defines the structure of the ROM and RAM areas.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 3.00     Merged processing of all devices.
+*                               Added support for GNUC and ICCRX.
+*                               Fixed coding style.
+*                               Added definition for section of D_8, B_8, and C_8.
+*         : 08.10.2019 3.01     Added section for Renesas RTOS (RI600V4 or RI600PX).
+*         : 14.02.2020 3.02     Corrected pragma declaration of unpack.
+***********************************************************************************************************************/
+
+#if defined(__CCRX__)
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/* Preprocessor directive */
+#pragma unpack
+
+/* MCU ROM and RAM structure definition */
+typedef struct
+{
+    uint8_t *rom_s;       /* Start address of the initialized data section in ROM */
+    uint8_t *rom_e;       /* End address of the initialized data section in ROM */
+    uint8_t *ram_s;       /* Start address of the initialized data section in RAM */
+} st_dtbl_t;
+
+typedef struct
+{
+    uint8_t *b_s;         /* Start address of non-initialized data section */
+    uint8_t *b_e;         /* End address of non-initialized data section */
+} st_btbl_t;
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/* Section start */
+#pragma section C C$DSEC
+
+extern st_dtbl_t const _DTBL[] = {
+#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT
+    { __sectop("D_8"), __secend("D_8"), __sectop("R_8") },
+#endif
+    { __sectop("D"), __secend("D"), __sectop("R") },
+    { __sectop("D_2"), __secend("D_2"), __sectop("R_2") },
+    { __sectop("D_1"), __secend("D_1"), __sectop("R_1") }
+#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600PX)
+   ,{ __sectop("DRI_ROM"), __secend("DRI_ROM"), __sectop("RRI_RAM") }
+#endif /* Renesas RI600PX */
+};
+
+/* Section start */
+#pragma section C C$BSEC
+
+extern st_btbl_t const _BTBL[] = {
+#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT
+    { __sectop("B_8"), __secend("B_8") },
+#endif
+    { __sectop("B"), __secend("B") },
+    { __sectop("B_2"), __secend("B_2") },
+    { __sectop("B_1"), __secend("B_1") }
+#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600V4)
+   ,{ __sectop("BRI_RAM"), __secend("BRI_RAM") }
+#endif /* Renesas RI600V4 */
+};
+
+/* Section start */
+#pragma section
+
+#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600PX)
+#pragma section C CS
+#endif /* Renesas RI600PX */
+
+/* CTBL prevents excessive output of L1100 messages when linking.
+   Even if CTBL is deleted, the operation of the program does not change. */
+uint8_t * const _CTBL[] = {
+    __sectop("C_1"), __sectop("C_2"), __sectop("C"),
+#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT
+    __sectop("C_8"),
+#endif
+    __sectop("W_1"), __sectop("W_2"), __sectop("W")
+};
+
+/* Preprocessor directive */
+#pragma packoption
+
+/* This is to ensure compatibility with new L section in version 1.1 and up of the RXC compiler.  Do not remove! */
+#pragma section C L
+const uint32_t deadSpace = 0xDEADDEAD;
+#pragma section
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
+#endif /* defined(__CCRX__) */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/linker_script_rvectors.inc b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/linker_script_rvectors.inc
new file mode 100644
index 00000000..d30ad475
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/linker_script_rvectors.inc
@@ -0,0 +1,283 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : linker_script_rvectors.inc
+* Description  : This module is used to set the interrupt table.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+***********************************************************************************************************************/
+
+LONG(DEFINED($tableentry$0$.rvectors) ? $tableentry$0$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$1$.rvectors) ? $tableentry$1$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$2$.rvectors) ? $tableentry$2$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$3$.rvectors) ? $tableentry$3$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$4$.rvectors) ? $tableentry$4$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$5$.rvectors) ? $tableentry$5$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$6$.rvectors) ? $tableentry$6$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$7$.rvectors) ? $tableentry$7$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$8$.rvectors) ? $tableentry$8$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$9$.rvectors) ? $tableentry$9$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$10$.rvectors) ? $tableentry$10$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$11$.rvectors) ? $tableentry$11$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$12$.rvectors) ? $tableentry$12$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$13$.rvectors) ? $tableentry$13$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$14$.rvectors) ? $tableentry$14$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$15$.rvectors) ? $tableentry$15$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$16$.rvectors) ? $tableentry$16$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$17$.rvectors) ? $tableentry$17$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$18$.rvectors) ? $tableentry$18$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$19$.rvectors) ? $tableentry$19$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$20$.rvectors) ? $tableentry$20$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$21$.rvectors) ? $tableentry$21$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$22$.rvectors) ? $tableentry$22$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$23$.rvectors) ? $tableentry$23$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$24$.rvectors) ? $tableentry$24$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$25$.rvectors) ? $tableentry$25$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$26$.rvectors) ? $tableentry$26$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$27$.rvectors) ? $tableentry$27$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$28$.rvectors) ? $tableentry$28$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$29$.rvectors) ? $tableentry$29$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$30$.rvectors) ? $tableentry$30$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$31$.rvectors) ? $tableentry$31$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$32$.rvectors) ? $tableentry$32$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$33$.rvectors) ? $tableentry$33$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$34$.rvectors) ? $tableentry$34$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$35$.rvectors) ? $tableentry$35$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$36$.rvectors) ? $tableentry$36$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$37$.rvectors) ? $tableentry$37$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$38$.rvectors) ? $tableentry$38$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$39$.rvectors) ? $tableentry$39$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$40$.rvectors) ? $tableentry$40$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$41$.rvectors) ? $tableentry$41$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$42$.rvectors) ? $tableentry$42$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$43$.rvectors) ? $tableentry$43$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$44$.rvectors) ? $tableentry$44$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$45$.rvectors) ? $tableentry$45$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$46$.rvectors) ? $tableentry$46$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$47$.rvectors) ? $tableentry$47$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$48$.rvectors) ? $tableentry$48$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$49$.rvectors) ? $tableentry$49$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$50$.rvectors) ? $tableentry$50$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$51$.rvectors) ? $tableentry$51$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$52$.rvectors) ? $tableentry$52$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$53$.rvectors) ? $tableentry$53$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$54$.rvectors) ? $tableentry$54$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$55$.rvectors) ? $tableentry$55$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$56$.rvectors) ? $tableentry$56$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$57$.rvectors) ? $tableentry$57$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$58$.rvectors) ? $tableentry$58$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$59$.rvectors) ? $tableentry$59$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$60$.rvectors) ? $tableentry$60$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$61$.rvectors) ? $tableentry$61$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$62$.rvectors) ? $tableentry$62$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$63$.rvectors) ? $tableentry$63$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$64$.rvectors) ? $tableentry$64$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$65$.rvectors) ? $tableentry$65$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$66$.rvectors) ? $tableentry$66$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$67$.rvectors) ? $tableentry$67$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$68$.rvectors) ? $tableentry$68$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$69$.rvectors) ? $tableentry$69$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$70$.rvectors) ? $tableentry$70$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$71$.rvectors) ? $tableentry$71$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$72$.rvectors) ? $tableentry$72$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$73$.rvectors) ? $tableentry$73$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$74$.rvectors) ? $tableentry$74$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$75$.rvectors) ? $tableentry$75$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$76$.rvectors) ? $tableentry$76$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$77$.rvectors) ? $tableentry$77$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$78$.rvectors) ? $tableentry$78$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$79$.rvectors) ? $tableentry$79$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$80$.rvectors) ? $tableentry$80$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$81$.rvectors) ? $tableentry$81$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$82$.rvectors) ? $tableentry$82$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$83$.rvectors) ? $tableentry$83$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$84$.rvectors) ? $tableentry$84$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$85$.rvectors) ? $tableentry$85$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$86$.rvectors) ? $tableentry$86$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$87$.rvectors) ? $tableentry$87$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$88$.rvectors) ? $tableentry$88$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$89$.rvectors) ? $tableentry$89$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$90$.rvectors) ? $tableentry$90$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$91$.rvectors) ? $tableentry$91$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$92$.rvectors) ? $tableentry$92$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$93$.rvectors) ? $tableentry$93$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$94$.rvectors) ? $tableentry$94$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$95$.rvectors) ? $tableentry$95$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$96$.rvectors) ? $tableentry$96$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$97$.rvectors) ? $tableentry$97$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$98$.rvectors) ? $tableentry$98$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$99$.rvectors) ? $tableentry$99$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$100$.rvectors) ? $tableentry$100$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$101$.rvectors) ? $tableentry$101$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$102$.rvectors) ? $tableentry$102$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$103$.rvectors) ? $tableentry$103$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$104$.rvectors) ? $tableentry$104$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$105$.rvectors) ? $tableentry$105$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$106$.rvectors) ? $tableentry$106$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$107$.rvectors) ? $tableentry$107$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$108$.rvectors) ? $tableentry$108$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$109$.rvectors) ? $tableentry$109$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$110$.rvectors) ? $tableentry$110$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$111$.rvectors) ? $tableentry$111$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$112$.rvectors) ? $tableentry$112$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$113$.rvectors) ? $tableentry$113$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$114$.rvectors) ? $tableentry$114$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$115$.rvectors) ? $tableentry$115$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$116$.rvectors) ? $tableentry$116$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$117$.rvectors) ? $tableentry$117$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$118$.rvectors) ? $tableentry$118$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$119$.rvectors) ? $tableentry$119$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$120$.rvectors) ? $tableentry$120$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$121$.rvectors) ? $tableentry$121$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$122$.rvectors) ? $tableentry$122$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$123$.rvectors) ? $tableentry$123$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$124$.rvectors) ? $tableentry$124$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$125$.rvectors) ? $tableentry$125$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$126$.rvectors) ? $tableentry$126$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$127$.rvectors) ? $tableentry$127$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$128$.rvectors) ? $tableentry$128$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$129$.rvectors) ? $tableentry$129$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$130$.rvectors) ? $tableentry$130$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$131$.rvectors) ? $tableentry$131$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$132$.rvectors) ? $tableentry$132$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$133$.rvectors) ? $tableentry$133$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$134$.rvectors) ? $tableentry$134$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$135$.rvectors) ? $tableentry$135$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$136$.rvectors) ? $tableentry$136$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$137$.rvectors) ? $tableentry$137$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$138$.rvectors) ? $tableentry$138$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$139$.rvectors) ? $tableentry$139$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$140$.rvectors) ? $tableentry$140$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$141$.rvectors) ? $tableentry$141$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$142$.rvectors) ? $tableentry$142$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$143$.rvectors) ? $tableentry$143$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$144$.rvectors) ? $tableentry$144$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$145$.rvectors) ? $tableentry$145$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$146$.rvectors) ? $tableentry$146$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$147$.rvectors) ? $tableentry$147$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$148$.rvectors) ? $tableentry$148$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$149$.rvectors) ? $tableentry$149$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$150$.rvectors) ? $tableentry$150$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$151$.rvectors) ? $tableentry$151$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$152$.rvectors) ? $tableentry$152$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$153$.rvectors) ? $tableentry$153$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$154$.rvectors) ? $tableentry$154$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$155$.rvectors) ? $tableentry$155$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$156$.rvectors) ? $tableentry$156$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$157$.rvectors) ? $tableentry$157$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$158$.rvectors) ? $tableentry$158$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$159$.rvectors) ? $tableentry$159$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$160$.rvectors) ? $tableentry$160$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$161$.rvectors) ? $tableentry$161$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$162$.rvectors) ? $tableentry$162$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$163$.rvectors) ? $tableentry$163$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$164$.rvectors) ? $tableentry$164$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$165$.rvectors) ? $tableentry$165$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$166$.rvectors) ? $tableentry$166$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$167$.rvectors) ? $tableentry$167$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$168$.rvectors) ? $tableentry$168$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$169$.rvectors) ? $tableentry$169$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$170$.rvectors) ? $tableentry$170$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$171$.rvectors) ? $tableentry$171$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$172$.rvectors) ? $tableentry$172$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$173$.rvectors) ? $tableentry$173$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$174$.rvectors) ? $tableentry$174$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$175$.rvectors) ? $tableentry$175$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$176$.rvectors) ? $tableentry$176$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$177$.rvectors) ? $tableentry$177$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$178$.rvectors) ? $tableentry$178$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$179$.rvectors) ? $tableentry$179$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$180$.rvectors) ? $tableentry$180$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$181$.rvectors) ? $tableentry$181$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$182$.rvectors) ? $tableentry$182$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$183$.rvectors) ? $tableentry$183$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$184$.rvectors) ? $tableentry$184$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$185$.rvectors) ? $tableentry$185$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$186$.rvectors) ? $tableentry$186$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$187$.rvectors) ? $tableentry$187$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$188$.rvectors) ? $tableentry$188$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$189$.rvectors) ? $tableentry$189$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$190$.rvectors) ? $tableentry$190$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$191$.rvectors) ? $tableentry$191$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$192$.rvectors) ? $tableentry$192$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$193$.rvectors) ? $tableentry$193$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$194$.rvectors) ? $tableentry$194$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$195$.rvectors) ? $tableentry$195$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$196$.rvectors) ? $tableentry$196$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$197$.rvectors) ? $tableentry$197$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$198$.rvectors) ? $tableentry$198$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$199$.rvectors) ? $tableentry$199$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$200$.rvectors) ? $tableentry$200$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$201$.rvectors) ? $tableentry$201$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$202$.rvectors) ? $tableentry$202$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$203$.rvectors) ? $tableentry$203$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$204$.rvectors) ? $tableentry$204$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$205$.rvectors) ? $tableentry$205$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$206$.rvectors) ? $tableentry$206$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$207$.rvectors) ? $tableentry$207$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$208$.rvectors) ? $tableentry$208$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$209$.rvectors) ? $tableentry$209$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$210$.rvectors) ? $tableentry$210$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$211$.rvectors) ? $tableentry$211$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$212$.rvectors) ? $tableentry$212$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$213$.rvectors) ? $tableentry$213$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$214$.rvectors) ? $tableentry$214$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$215$.rvectors) ? $tableentry$215$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$216$.rvectors) ? $tableentry$216$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$217$.rvectors) ? $tableentry$217$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$218$.rvectors) ? $tableentry$218$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$219$.rvectors) ? $tableentry$219$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$220$.rvectors) ? $tableentry$220$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$221$.rvectors) ? $tableentry$221$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$222$.rvectors) ? $tableentry$222$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$223$.rvectors) ? $tableentry$223$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$224$.rvectors) ? $tableentry$224$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$225$.rvectors) ? $tableentry$225$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$226$.rvectors) ? $tableentry$226$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$227$.rvectors) ? $tableentry$227$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$228$.rvectors) ? $tableentry$228$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$229$.rvectors) ? $tableentry$229$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$230$.rvectors) ? $tableentry$230$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$231$.rvectors) ? $tableentry$231$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$232$.rvectors) ? $tableentry$232$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$233$.rvectors) ? $tableentry$233$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$234$.rvectors) ? $tableentry$234$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$235$.rvectors) ? $tableentry$235$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$236$.rvectors) ? $tableentry$236$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$237$.rvectors) ? $tableentry$237$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$238$.rvectors) ? $tableentry$238$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$239$.rvectors) ? $tableentry$239$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$240$.rvectors) ? $tableentry$240$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$241$.rvectors) ? $tableentry$241$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$242$.rvectors) ? $tableentry$242$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$243$.rvectors) ? $tableentry$243$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$244$.rvectors) ? $tableentry$244$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$245$.rvectors) ? $tableentry$245$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$246$.rvectors) ? $tableentry$246$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$247$.rvectors) ? $tableentry$247$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$248$.rvectors) ? $tableentry$248$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$249$.rvectors) ? $tableentry$249$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$250$.rvectors) ? $tableentry$250$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$251$.rvectors) ? $tableentry$251$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$252$.rvectors) ? $tableentry$252$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$253$.rvectors) ? $tableentry$253$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$254$.rvectors) ? $tableentry$254$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+LONG(DEFINED($tableentry$255$.rvectors) ? $tableentry$255$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowlvl.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowlvl.c
new file mode 100644
index 00000000..b17b9c02
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowlvl.c
@@ -0,0 +1,126 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : lowlvl.c
+* Description  : Functions to support stream I/O to the E1 virtual Console
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 3.00     Merged processing of all devices.
+*                               Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define BSP_PRV_E1_DBG_PORT (*(volatile st_dbg_t     R_BSP_EVENACCESS_SFR *)0x84080)
+#define BSP_PRV_TXFL0EN     (0x00000100)          /* debug tx flow control bit */
+#define BSP_PRV_RXFL0EN     (0x00001000)          /* debug RX flow control bit */
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef struct
+{
+    uint32_t   tx_data;     /* Debug Virtual Console TX data */
+    char       wk1[12];     /* spacer */
+    uint32_t   rx_data;     /* Debug Virtual Console RX data */
+    char       wk2[44];     /* spacer */
+    uint32_t   dbgstat;     /* Debug Virtual Console Status */
+} st_dbg_t;
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+#if BSP_CFG_USER_CHARPUT_ENABLED != 0
+/* If user has indicated they want to provide their own charput function then this is the prototype. */
+void BSP_CFG_USER_CHARPUT_FUNCTION(char output_char);
+#endif
+
+#if BSP_CFG_USER_CHARGET_ENABLED != 0
+/* If user has indicated they want to provide their own charget function then this is the prototype. */
+char BSP_CFG_USER_CHARGET_FUNCTION(void);
+#endif
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: charput
+* Description  : Outputs a character on a serial port
+* Arguments    : character to output
+* Return Value : none
+***********************************************************************************************************************/
+void charput (char output_char)
+{
+    /* If user has provided their own charput() function, then call it. */
+#if BSP_CFG_USER_CHARPUT_ENABLED == 1
+    BSP_CFG_USER_CHARPUT_FUNCTION(output_char);
+#else
+    /* Wait for transmit buffer to be empty */
+    /* WAIT_LOOP */
+    while(0 != (BSP_PRV_E1_DBG_PORT.dbgstat & BSP_PRV_TXFL0EN))
+    {
+        /* do nothing */
+        R_BSP_NOP();
+    }
+
+    /* Write the character out */
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_E1_DBG_PORT.tx_data = (int32_t)output_char;
+#endif
+} /* End of function charput() */
+
+/***********************************************************************************************************************
+* Function Name: charget
+* Description  : Gets a character on a serial port
+* Arguments    : none
+* Return Value : received character
+***********************************************************************************************************************/
+char charget (void)
+{
+    /* If user has provided their own charget() function, then call it. */
+#if BSP_CFG_USER_CHARGET_ENABLED == 1
+    return BSP_CFG_USER_CHARGET_FUNCTION();
+#else
+    /* Wait for rx buffer buffer to be ready */
+    /* WAIT_LOOP */
+    while(0 == (BSP_PRV_E1_DBG_PORT.dbgstat & BSP_PRV_RXFL0EN))
+    {
+        /* do nothing */
+        R_BSP_NOP();
+    }
+
+    /* Read data, send back up */
+    /* Casting is valid because it matches the type to the retern value. */
+    return (char)BSP_PRV_E1_DBG_PORT.rx_data;
+#endif
+} /* End of function charget() */
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowlvl.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowlvl.h
new file mode 100644
index 00000000..9ca8db79
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowlvl.h
@@ -0,0 +1,58 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : lowlvl.h
+* Description  : Functions to support stream I/O
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+***********************************************************************************************************************/
+
+/* Multiple inclusion prevention macro */
+#ifndef LOWLVL_H
+#define LOWLVL_H
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+/* Output one character to standard output (the E1 Virtual Console or a serial port via user own charput function) */
+void charput (char output_char);
+
+/* Input one character from standard input (the E1 Virtual Console or a serial port via user own charget function) */
+char charget (void);
+
+#endif  /* End of multiple inclusion prevention macro */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowsrc.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowsrc.c
new file mode 100644
index 00000000..36078db9
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowsrc.c
@@ -0,0 +1,571 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : lowsrc.c
+* Description  : Functions to support stream I/O
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 3.00     Merged processing of all devices.
+*                               Added support for GNUC and ICCRX.
+*                               Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#if defined(__CCRX__)
+#include <string.h>
+#include <stdio.h>
+#endif /* defined(__CCRX__) */
+#include "r_bsp_common.h"
+#include "r_bsp_config.h"
+#include "lowlvl.h"
+#include "lowsrc.h"
+
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+
+/* Do not include this file if stdio is disabled in r_bsp_config. */
+#if BSP_CFG_IO_LIB_ENABLE == 1
+
+#if defined(__CCRX__)
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/*Number of I/O Stream*/
+#define BSP_PRV_IOSTREAM (20)
+
+/* file number */
+#define BSP_PRV_STDIN    (0)    /* Standard input (console) */
+#define BSP_PRV_STDOUT   (1)    /* Standard output (console) */
+#define BSP_PRV_STDERR   (2)    /* Standard error output (console) */
+
+#define BSP_PRV_FLMIN    (0)    /* Minimum file number */
+#define BSP_PRV_MOPENR   (0x1)
+#define BSP_PRV_MOPENW   (0x2)
+#define BSP_PRV_MOPENA   (0x4)
+#define BSP_PRV_MTRUNC   (0x8)
+#define BSP_PRV_MCREAT   (0x10)
+#define BSP_PRV_MBIN     (0x20)
+#define BSP_PRV_MEXCL    (0x40)
+#define BSP_PRV_MALBUF   (0x40)
+#define BSP_PRV_MALFIL   (0x80)
+#define BSP_PRV_MEOF     (0x100)
+#define BSP_PRV_MERR     (0x200)
+#define BSP_PRV_MLBF     (0x400)
+#define BSP_PRV_MNBF     (0x800)
+#define BSP_PRV_MREAD    (0x1000)
+#define BSP_PRV_MWRITE   (0x2000)
+#define BSP_PRV_MBYTE    (0x4000)
+#define BSP_PRV_MWIDE    (0x8000)
+/* File Flags */
+#define BSP_PRV_O_RDONLY (0x0001)  /* Read only */
+#define BSP_PRV_O_WRONLY (0x0002)  /* Write only */
+#define BSP_PRV_O_RDWR   (0x0004)  /* Both read and Write */
+#define BSP_PRV_O_CREAT  (0x0008)  /* A file is created if it is not existed */
+#define BSP_PRV_O_TRUNC  (0x0010)  /* The file size is changed to 0 if it is existed. */
+#define BSP_PRV_O_APPEND (0x0020)  /* The position is set for next reading/writing
+                                      0: Top of the file 1: End of file */
+
+/* Special character code */
+#define BSP_PRV_CR (0x0d) /* Carriage return */
+#define BSP_PRV_LF (0x0a) /* Line feed */
+
+#define BSP_PRV_FPATH_STDIN     "C:\\stdin"
+#define BSP_PRV_FPATH_STDOUT    "C:\\stdout"
+#define BSP_PRV_FPATH_STDERR    "C:\\stderr"
+
+#ifdef _REENTRANT
+// For Reentrant Library (generated lbgrx with -reent option)
+#define BSP_PRV_MALLOC_SEM   (1)  /* Semaphore No. for malloc */
+#define BSP_PRV_STRTOK_SEM   (2)  /* Semaphore No. for strtok */
+#define BSP_PRV_FILE_TBL_SEM (3)  /* Semaphore No. for fopen  */
+#define BSP_PRV_MBRLEN_SEM   (4)  /* Semaphore No. for mbrlen */
+#define BSP_PRV_FPSWREG_SEM  (5)  /* Semaphore No. for FPSW register */
+#define BSP_PRV_FILES_SEM    (6)  /* Semaphore No. for _Files */
+#define BSP_PRV_SEMSIZE      (26) /* BSP_PRV_FILES_SEM + _nfiles (assumed _nfiles=20) */
+
+#define BSP_PRV_TRUE  (1)
+#define BSP_PRV_FALSE (0)
+#define BSP_PRV_OK    (1)
+#define BSP_PRV_NG    (0)
+#endif /* _REENTRANT */
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+extern const long _nfiles;     /* The number of files for input/output files */
+char flmod[BSP_PRV_IOSTREAM];          /* The location for the mode of opened file. */
+
+unsigned char sml_buf[BSP_PRV_IOSTREAM];
+
+FILE *_Files[BSP_PRV_IOSTREAM]; /* structure for FILE */
+char *env_list[] = {            /* Array for environment variables(**environ) */
+    "ENV1=temp01",
+    "ENV2=temp02",
+    "ENV9=end",
+    '\0'                        /* Terminal for environment variables */
+};
+
+char **environ = env_list;
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+#ifdef _REENTRANT
+static long sem_errno;
+static int force_fail_signal_sem = BSP_PRV_FALSE;
+static int semaphore[BSP_PRV_SEMSIZE];
+#endif /* _REENTRANT */
+
+/***********************************************************************************************************************
+* Function Name: init_iolib
+* Description  : Initialize C library Functions, if necessary. Define USES_SIMIO on Assembler Option.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+void init_iolib(void)
+{
+    /* A file for standard input/output is opened or created. Each FILE
+     * structure members are initialized by the library. Each _Buf member
+     * in it is re-set the end of buffer pointer.
+     */
+
+    /* Initializations of File Stream Table */
+    _Files[0] = stdin;
+    _Files[1] = stdout;
+    _Files[2] = stderr;
+
+    /* Standard Input File */
+    if( freopen( BSP_PRV_FPATH_STDIN, "r", stdin ) == NULL )
+    {
+        stdin->_Mode = 0xffff;  /* Not allow the access if it fails to open */
+    }
+    stdin->_Mode  = BSP_PRV_MOPENR;         /* Read only attribute */
+    stdin->_Mode |= BSP_PRV_MNBF;           /* Non-buffering for data */
+    stdin->_Bend = stdin->_Buf + 1;  /* Re-set pointer to the end of buffer */
+
+    /* Standard Output File */
+    if( freopen( BSP_PRV_FPATH_STDOUT, "w", stdout ) == NULL ) 
+    {
+        stdout->_Mode = 0xffff; /* Not allow the access if it fails to open */
+    }
+    stdout->_Mode |= BSP_PRV_MNBF;            /* Non-buffering for data */
+    stdout->_Bend = stdout->_Buf + 1;  /* Re-set pointer to the end of buffer */
+    
+    /* Standard Error File */
+    if( freopen( BSP_PRV_FPATH_STDERR, "w", stderr ) == NULL )
+    {
+        stderr->_Mode = 0xffff;  /* Not allow the access if it fails to open */
+    }
+    stderr->_Mode |= BSP_PRV_MNBF;             /* Non-buffering for data */
+    stderr->_Bend = stderr->_Buf + 1;/* Re-set pointer to the end of buffer */
+} /* End of function init_iolib() */
+
+/***********************************************************************************************************************
+* Function Name: close_all
+* Description  : Colses the file
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+void close_all(void)
+{
+    long i;
+
+    /* WAIT_LOOP */
+    for( i=0; i < _nfiles; i++ )
+    {
+        /* Checks if the file is opened or not */
+        if( _Files[i]->_Mode & (BSP_PRV_MOPENR | BSP_PRV_MOPENW | BSP_PRV_MOPENA ) )
+        {
+            fclose( _Files[i] );    /* Closes the file */
+        }
+    }
+} /* End of function close_all() */
+
+/***********************************************************************************************************************
+* Function Name: open
+* Description  : file open
+* Arguments    : name - File name
+*                mode - Open mode
+*                flg - Open flag
+* Return Value : File number (Pass)
+*                -1          (Failure)
+***********************************************************************************************************************/
+long open(const char *name, long  mode, long  flg)
+{
+    /* This code is only used to remove compiler info messages about these parameters not being used. */
+    INTERNAL_NOT_USED(flg);
+
+    if( 0 == strcmp( name, BSP_PRV_FPATH_STDIN ) )       /* Standard Input file? */
+    {
+        if( 0 == ( mode & BSP_PRV_O_RDONLY ) )
+        {
+            return -1;
+        }
+        flmod[BSP_PRV_STDIN] = mode;
+        return BSP_PRV_STDIN;
+    }
+    else if( 0 == strcmp( name, BSP_PRV_FPATH_STDOUT ) ) /* Standard Output file? */
+    {
+        if( 0 == ( mode & BSP_PRV_O_WRONLY ) )
+        {
+            return -1;
+        }
+        flmod[BSP_PRV_STDOUT] = mode;
+        return BSP_PRV_STDOUT;
+    }
+    else if( 0 == strcmp(name, BSP_PRV_FPATH_STDERR ) )   /* Standard Error file? */
+    {
+        if( 0 == ( mode & BSP_PRV_O_WRONLY ) )
+        {
+            return -1;
+        }
+        flmod[BSP_PRV_STDERR] = mode;
+        return BSP_PRV_STDERR;
+    }
+    else
+    {
+        return -1;                              /*Others */
+    }
+} /* End of function open() */
+
+/***********************************************************************************************************************
+* Function Name: close
+* Description  : dummy
+* Arguments    : fileno - File number
+* Return Value : 1
+***********************************************************************************************************************/
+long close(long fileno)
+{
+    /* This code is only used to remove compiler info messages about these parameters not being used. */
+    INTERNAL_NOT_USED(fileno);
+
+    return 1;
+} /* End of function close() */
+
+/***********************************************************************************************************************
+* Function Name: write
+* Description  : Data write
+* Arguments    : fileno - File number
+*                buf - The address of destination buffer
+*                count - The number of chacter to write
+* Return Value : Number of write characters (Pass)
+*                -1                         (Failure)
+***********************************************************************************************************************/
+long write(long  fileno, const unsigned char *buf, long  count)
+{
+    long    i;                          /* A variable for counter */
+    unsigned char    c;                 /* An output character */
+
+    /* Checking the mode of file , output each character
+     * Checking the attribute for Write-Only, Read-Only or Read-Write
+     */
+    if((flmod[fileno]&BSP_PRV_O_WRONLY) || (flmod[fileno]&BSP_PRV_O_RDWR))
+    {
+        if( BSP_PRV_STDIN == fileno )
+        {
+            return -1;            /* Standard Input */
+        }
+        else if( (BSP_PRV_STDOUT == fileno) || (BSP_PRV_STDERR == fileno) ) /* Standard Error/output */
+        {
+            /* WAIT_LOOP */
+            for( i = count; i > 0; --i )
+            {
+                c = *buf++;
+                charput(c);
+            }
+            return count;        /*Return the number of written characters */
+        }
+        else
+        {
+            return -1;                  /* Incorrect file number */
+        }
+    }
+    else
+    {
+        return -1;                      /* An error */
+    }
+} /* End of function write() */
+
+/***********************************************************************************************************************
+* Function Name: read
+* Description  : Data read
+* Arguments    : fileno - File number
+*                buf - The address of destination buffer
+*                count - The number of chacter to read
+* Return Value : Number of read characters (Pass)
+*                -1                        (Failure)
+***********************************************************************************************************************/
+long read(long fileno, unsigned char *buf, long count)
+{
+       long i;
+
+       /* Checking the file mode with the file number, each character is input and stored the buffer */
+
+       if((flmod[fileno]&BSP_PRV_MOPENR) || (flmod[fileno]&BSP_PRV_O_RDWR))
+       {
+             /* WAIT_LOOP */
+             for(i = count; i > 0; i--)
+             {
+                   *buf = charget();
+                   if(BSP_PRV_CR == (*buf))
+                   {
+                         *buf = BSP_PRV_LF; /* Replace the new line character */
+                   }
+                   buf++;
+             }
+             return count;
+       }
+       else 
+       {
+             return -1;
+       }
+} /* End of function read() */
+
+/***********************************************************************************************************************
+* Function Name: lseek
+* Description  : dummy
+* Arguments    : fileno - File number
+*                offset - Offset indicating reading / writing position
+*                base - Offset starting point
+* Return Value : -1L
+***********************************************************************************************************************/
+long lseek(long fileno, long offset, long base)
+{
+    /* This code is only used to remove compiler info messages about these parameters not being used. */
+    INTERNAL_NOT_USED(fileno);
+
+    /* This code is only used to remove compiler info messages about these parameters not being used. */
+    INTERNAL_NOT_USED(offset);
+
+    /* This code is only used to remove compiler info messages about these parameters not being used. */
+    INTERNAL_NOT_USED(base);
+
+    return -1L;
+} /* End of function lseek() */
+
+#ifdef _REENTRANT
+/***********************************************************************************************************************
+* Function Name: errno_addr
+* Description  : Acquisition of errno address
+* Arguments    : none
+* Return Value : errno address
+***********************************************************************************************************************/
+long *errno_addr(void)
+{
+    /* Return the errno address of the current task */
+    return (&sem_errno);
+}
+
+/***********************************************************************************************************************
+* Function Name: wait_sem
+* Description  : Defines the specified numbers of semaphores
+* Arguments    : semnum - Semaphore ID
+* Return Value : BSP_PRV_OK(=1) (Normal)
+*                BSP_PRV_NG(=0) (Error)
+***********************************************************************************************************************/
+long wait_sem(long semnum) /* Semaphore ID */
+{
+    if((0 < semnum) && (semnum < BSP_PRV_SEMSIZE)) {
+        if(semaphore[semnum] == BSP_PRV_FALSE) {
+            semaphore[semnum] = BSP_PRV_TRUE;
+            return(BSP_PRV_OK);
+        }
+    }
+    return(BSP_PRV_NG);
+}
+
+/***********************************************************************************************************************
+* Function Name: signal_sem
+* Description  : Releases the specified numbers of semaphores
+* Arguments    : semnum - Semaphore ID
+* Return Value : BSP_PRV_OK(=1) (Normal)
+*                BSP_PRV_NG(=0) (Error)
+***********************************************************************************************************************/
+long signal_sem(long semnum) /* Semaphore ID */
+{
+    if(!force_fail_signal_sem) {
+        if((0 <= semnum) && (semnum < BSP_PRV_SEMSIZE)) {
+            if( semaphore[semnum] == BSP_PRV_TRUE ) {
+                semaphore[semnum] = BSP_PRV_FALSE;
+                return(BSP_PRV_OK);
+            }
+        }
+    }
+    return(BSP_PRV_NG);
+}
+#endif /* _REENTRANT */
+
+#endif /* defined(__CCRX__) */
+
+#endif /* BSP_CFG_IO_LIB_ENABLE */
+
+#if defined(__GNUC__)
+/***********************************************************************************************************************
+* Function Name: write
+* Description  : Data write (for GNURX+NEWLIB)
+* Arguments    : fileno - File number
+*                buf - The address of destination buffer
+*                count - The number of chacter to write
+* Return Value : Number of write characters (Pass)
+***********************************************************************************************************************/
+int write(int fileno, char *buf, int count)
+{
+    int i;
+    char c;
+
+    /* This code is only used to remove compiler info messages about these parameters not being used. */
+    INTERNAL_NOT_USED(fileno);
+
+    /* WAIT_LOOP */
+    for(i = count; i > 0; --i)
+    {
+       c = *buf++;
+       charput(c);
+    }
+
+    return count;
+}
+
+/***********************************************************************************************************************
+* Function Name: read
+* Description  : Data read (for GNURX+NEWLIB)
+* Arguments    : fileno - File number
+*                buf - The address of destination buffer
+*                count - The number of chacter to read
+* Return Value : 1 (Pass)
+***********************************************************************************************************************/
+int read(int fileno, char *buf, int count)
+{
+    /* This code is only used to remove compiler info messages about these parameters not being used. */
+    INTERNAL_NOT_USED(fileno);
+    INTERNAL_NOT_USED(count);
+
+    *buf = charget();
+    return 1;
+}
+
+/***********************************************************************************************************************
+* Function Name: _write
+* Description  : Data write (for GNURX+OPTLIB)
+* Arguments    : fileno - File number
+*                buf - The address of destination buffer
+*                count - The number of chacter to write
+* Return Value : Number of write characters (Pass)
+***********************************************************************************************************************/
+int _write(int fileno, char *buf, int count)
+{
+    int i;
+    char c;
+
+    /* This code is only used to remove compiler info messages about these parameters not being used. */
+    INTERNAL_NOT_USED(fileno);
+
+    /* WAIT_LOOP */
+    for(i = count; i > 0; --i)
+    {
+       c = *buf++;
+       charput(c);
+    }
+
+    return count;
+}
+
+/***********************************************************************************************************************
+* Function Name: read
+* Description  : Data read (for GNURX+OPTLIB)
+* Arguments    : fileno - File number
+*                buf - The address of destination buffer
+*                count - The number of chacter to read
+* Return Value : 1 (Pass)
+***********************************************************************************************************************/
+int _read(int fileno, char *buf, int count)
+{
+    /* This code is only used to remove compiler info messages about these parameters not being used. */
+    INTERNAL_NOT_USED(fileno);
+    INTERNAL_NOT_USED(count);
+
+    *buf = charget();
+    return 1;
+}
+
+/***********************************************************************************************************************
+* Function Name: close
+* Description  : dummy
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+void close (void)
+{
+    /* This is dummy function.
+       This function is used to suppress the warning messages of GNU compiler.
+       Plese edit the function as required. */
+}
+
+/***********************************************************************************************************************
+* Function Name: fstat
+* Description  : dummy
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+void fstat (void)
+{
+    /* This is dummy function.
+       This function is used to suppress the warning messages of GNU compiler.
+       Plese edit the function as required. */
+}
+
+/***********************************************************************************************************************
+* Function Name: isatty
+* Description  : dummy
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+void isatty (void)
+{
+    /* This is dummy function.
+       This function is used to suppress the warning messages of GNU compiler.
+       Plese edit the function as required. */
+}
+
+/***********************************************************************************************************************
+* Function Name: lseek
+* Description  : dummy
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+void lseek (void)
+{
+    /* This is dummy function.
+       This function is used to suppress the warning messages of GNU compiler.
+       Plese edit the function as required. */
+}
+
+#endif /* defined(__GNUC__) */
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowsrc.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowsrc.h
new file mode 100644
index 00000000..d30f5e28
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/lowsrc.h
@@ -0,0 +1,81 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : lowsrc.h
+* Description  : Functions to support stream I/O
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 2.00     Merged processing of all devices.
+*                               Added support for GNUC and ICCRX.
+*                               Fixed coding style.
+*         : 31.07.2020 2.01     Fixed an issue that caused build errors when the _REENTRANT option was specified in 
+*                               the CCRX compiler.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef LOWSRC_H
+#define LOWSRC_H
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+#if defined(__CCRX__)
+void init_iolib(void);
+void close_all(void);
+long open(const char *name, long  mode, long  flg);
+long close(long fileno);
+long write(long  fileno, const unsigned char *buf, long  count);
+long read(long fileno, unsigned char *buf, long count);
+long lseek(long fileno, long offset, long base);
+#ifdef _REENTRANT
+long *errno_addr(void);
+long wait_sem(long semnum);
+long signal_sem(long semnum);
+#endif
+#endif /* defined(__CCRX__) */
+
+#if defined(__GNUC__)
+int write(int fileno, char *buf, int count);
+int read(int fileno, char *buf, int count);
+int _write(int fileno, char *buf, int count);
+int _read(int fileno, char *buf, int count);
+void close(void);
+void fstat(void);
+void isatty(void);
+void lseek(void);
+#endif /* defined(__GNUC__) */
+
+#endif  /* End of multiple inclusion prevention macro */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/mcu_locks.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/mcu_locks.c
new file mode 100644
index 00000000..4fb5c24b
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/mcu_locks.c
@@ -0,0 +1,48 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_locks.c
+* Description  : This source file has 1 lock per MCU resource.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 2.00     Merged processing of all devices.
+*                               Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Used for getting MCU information to accurately reflect available MCU resources. */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+/* Below are locks for controlling access to MCU resources. */
+BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[BSP_NUM_LOCKS];
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c
new file mode 100644
index 00000000..ab902b06
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c
@@ -0,0 +1,225 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_common.c
+* Description  : Implements functions that apply to all r_bsp boards and MCUs.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 06.05.2013 1.00     First Release
+*         : 26.03.2014 1.10     Added R_BSP_SoftwareDelay() function
+*         : 03.09.2014 1.20     Corrected R_BSP_SoftwareDelay() timing when using an RX64M
+*         : 30.09.2015 1.30     Added RX23T
+*         : 01.02.2016 1.40     Added RX24T
+*                               Changed the value of the following macro definition.
+*                               - OVERHEAD_CYCLES
+*                               - OVERHEAD_CYCLES_64
+*         : 29.02.2016 1.50     Added RX230
+*         : 01.10.2016 1.60     Added RX65N
+*         : 22.08.2016 1.70     Added RX24U
+*         : 15.05.2017 1.80     Changed method of selecting the number of CPU cycles required to execute 
+*                               the delayWait() loop.
+*         : 27.07.2018 1.90     Changed the value of the following macro definition, because added RX66T.
+*                               - CPU_CYCLES_PER_LOOP
+*         : 28.02.2019 2.00     Deleted the following definition. 
+*                               (The following definition moved to the common file (mcu_info.h).)
+*                               - CPU_CYCLES_PER_LOOP
+*                               Added support for GNUC and ICCRX.
+*                               Fixed coding style.
+*                               Renamed following macro definitions.
+*                               - BSP_PRV_OVERHEAD_CYCLES
+*                               - BSP_PRV_OVERHEAD_CYCLES_64
+*                               - BSP_PRV_CKSEL_LOCO
+*                               Renamed following function.
+*                               - delay_wait
+*         : 26.07.2019 2.01     Modified comment of API function to Doxygen style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Get information about current board and MCU. */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define BSP_PRV_OVERHEAD_CYCLES        (2)    /* R_BSP_SoftwareDelay() overhead per call */
+#define BSP_PRV_OVERHEAD_CYCLES_64     (2)    /* R_BSP_SoftwareDelay() overhead per call using 64-bit ints */
+
+#define BSP_PRV_CKSEL_LOCO             (0x0)  /* SCKCR3 register setting for LOCO */
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_GetVersion
+ ******************************************************************************************************************//**
+ * @brief Returns the current version of the r_bsp.
+ * @return Version of the r_bsp.
+ * @details This function will return the version of the currently installed r_bsp. The version number is encoded 
+ * where the top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For 
+ * example, Version 4.25 would be returned as 0x00040019.
+ */
+uint32_t R_BSP_GetVersion (void)
+{
+    /* These version macros are defined in platform.h. */
+    return ((((uint32_t)R_BSP_VERSION_MAJOR) << 16) | (uint32_t)R_BSP_VERSION_MINOR);
+} /* End of function R_BSP_GetVersion() */
+
+
+/***********************************************************************************************************************
+* Function Name: delay_wait
+* Description  : This asm loop executes a known number (5) of CPU cycles. If a value of '4' is passed
+*                in as an argument, then this function would consume 20 CPU cycles before returning.
+* Arguments    : loop_cnt - A single 32-bit value is provided as the number of loops to execute.
+* Return Value : None
+***********************************************************************************************************************/
+R_BSP_PRAGMA_STATIC_INLINE_ASM(delay_wait)
+void delay_wait (unsigned long loop_cnt)
+{
+    R_BSP_ASM_INTERNAL_USED(loop_cnt)
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    BRA.B   R_BSP_ASM_LAB_NEXT(0)     )
+    R_BSP_ASM(    NOP                               )
+    R_BSP_ASM_LAB(0:                                )
+    R_BSP_ASM(    NOP                               )
+    R_BSP_ASM(    SUB     #01H, R1                  )
+    R_BSP_ASM(    BNE.B   R_BSP_ASM_LAB_PREV(0)     )
+    R_BSP_ASM_END
+} /* End of function delay_wait() */
+
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_GetIClkFreqHz
+ ******************************************************************************************************************//**
+ * @brief Returns the system clock frequency.
+ * @return System clock frequency specified by the r_bsp.
+ * @details This function returns the system clock frequency. For example, when the system clock is set to 120 MHz in 
+ * r_bsp_config_h and the r_bsp has completed to specify the clock setting, then even if the user changed the system 
+ * clock frequency to 60 MHz, the return value is '60000000'.
+ */
+uint32_t R_BSP_GetIClkFreqHz(void)
+{
+    return get_iclk_freq_hz();  // Get the MCU specific ICLK frequency
+} /* End of function R_BSP_GetIClkFreqHz() */
+
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_SoftwareDelay
+ ******************************************************************************************************************//**
+ * @brief Delay the specified duration in units and return.
+ * @param[in] delay The number of 'units' to delay.
+ * @param[in] units The 'base' for the units specified.
+ * @retval true True if delay executed.
+ * @retval false False if delay/units combination resulted in overflow/underflow.
+ * @details This is function that may be called for all MCU targets to implement a specific wait time.
+ * The actual delay time is plus the overhead at a specified duration. The overhead changes under the influence of 
+ * the compiler, operating frequency and ROM cache. When the operating frequency is low, or the specified duration in 
+ * units of microsecond level, please note that the error becomes large.
+ */
+bool R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units)
+{
+    volatile uint32_t iclk_rate;
+    volatile uint32_t delay_cycles;
+    volatile uint32_t loop_cnt;
+    volatile uint64_t delay_cycles_64;
+    volatile uint64_t loop_cnt_64;
+
+#ifdef BSP_CFG_PARAM_CHECKING_ENABLE
+    if ((BSP_DELAY_MICROSECS != units) && (BSP_DELAY_MILLISECS != units) && (BSP_DELAY_SECS != units))
+    {
+        return(false);
+    }
+#endif
+
+    iclk_rate = R_BSP_GetIClkFreqHz();  /* Get the current ICLK frequency */
+
+    /*
+     * In order to handle all possible combinations of delay/ICLK it is necessary to use 64-bit
+     * integers (not all MCUs have floating point support). However, there is no native hw support
+     * for 64 bit integers so it requires many more clock cycles. This is not an issue if the
+     * requested delay is long enough and the ICLK is fast, but for delays in the low microseconds
+     * and/or a slow ICLK we use 32 bit integers to reduce the overhead cycles of this function
+     * by approximately a third and stand the best chance of achieving the requested delay.
+     */
+    if ( (BSP_DELAY_MICROSECS == units) &&
+         (delay <= (0xFFFFFFFFUL / iclk_rate)) )  /* Ensure (iclk_rate * delay) will not exceed 32 bits */
+    {
+        delay_cycles = ((iclk_rate * delay) / units);
+
+        if (delay_cycles > BSP_PRV_OVERHEAD_CYCLES)
+        {
+            delay_cycles -= BSP_PRV_OVERHEAD_CYCLES;
+        }
+        else
+        {
+            delay_cycles = 0;
+        }
+
+        loop_cnt = delay_cycles / CPU_CYCLES_PER_LOOP;
+
+        if (0 == loop_cnt)
+        {
+            /* The requested delay is too large/small for the current ICLK. Return false which
+             * also results in the minimum possible delay. */
+            return(false);
+        }
+    }
+    else
+    {
+        /* Casting is valid because it matches the type to the right side or argument. */
+        delay_cycles_64 = (((uint64_t)iclk_rate * (uint64_t)delay) / units);
+
+        if (delay_cycles_64 > BSP_PRV_OVERHEAD_CYCLES_64)
+        {
+            delay_cycles_64 -= BSP_PRV_OVERHEAD_CYCLES_64;
+        }
+        else
+        {
+            delay_cycles = 0;
+        }
+
+        loop_cnt_64 = delay_cycles_64 / CPU_CYCLES_PER_LOOP;
+
+        if ((loop_cnt_64 > 0xFFFFFFFFUL) || (0 == loop_cnt_64))
+        {
+            /* The requested delay is too large/small for the current ICLK. Return false which
+             * also results in the minimum possible delay. */
+            return(false);
+        }
+
+        /* Casting is valid because it matches the type to the right side or argument. */
+        loop_cnt = (uint32_t)loop_cnt_64;
+    }
+
+    delay_wait(loop_cnt);
+
+    return(true);
+} /* End of function R_BSP_SoftwareDelay() */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h
new file mode 100644
index 00000000..f96b45d8
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h
@@ -0,0 +1,146 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_common.h
+* Description  : Implements functions that apply to all r_bsp boards and MCUs.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 06.05.2013 1.00     First Release
+*         : 25.06.2013 1.10     Now contains standard includes (stdint.h, stdbool.h, etc) as well as include for
+*                               r_typedefs.h when needed.
+*         : 02.07.2013 1.11     Added #include for machine.h.
+*         : 10.02.2014 1.12     Changed minor version to '40'.
+*         : 24.03.2014 1.12     Changed minor version to '60'.
+*         : 14.04.2014 1.12     Added typedef for fit_callback_t.
+*         : 30.09.2015 1.13     Changed Major/Minor version to 3.00
+*         : 30.09.2015 1.14     Changed Minor version to 3.01
+*         : 01.12.2015 1.15     Changed Minor version to 3.10
+*         : 01.02.2016 1.16     Changed Minor version to 3.20
+*         : 29.02.2016 1.17     Changed Minor version to 3.30
+*         : 13.04.2016 1.18     Changed Minor version to 3.31
+*         : 01.10.2016 1.19     Changed Minor version to 3.40
+*         : 04.11.2016 1.20     Changed Minor version to 3.50
+*         : 15.05.2017 1.21     Changed Minor version to 3.60
+*         : 01.11.2017 1.22     Changed Minor version to 3.70
+*         : 01.12.2017 1.23     Changed Minor version to 3.71
+*         : 01.07.2018 1.24     Changed Minor version to 3.80
+*         : 27.07.2018 1.25     Changed Minor version to 3.90.
+*         : 31.08.2018 1.26     Changed Minor version to 3.91.
+*         : 31.10.2018 1.27     Changed Major/Minor version to 4.00.
+*         : 11.01.2019 1.28     Changed Minor version to 4.01.
+*         : 28.02.2019 1.29     Changed Major version to 5.00.
+*                               Added the following macro definition.
+*                                - INTERNAL_NOT_USED(p)
+*                               Added support for GNUC and ICCRX.
+*                               Fixed coding style.
+*         : 29.03.2019 1.30     Changed Minor version to 5.10.
+*         : 08.04.2019 1.31     Changed Minor version to 5.20.
+*         : 23.07.2019 1.32     Changed Minor version to 5.21.
+*         : 26.07.2019 1.33     Changed Minor version to 5.30.
+*         : 31.07.2019 1.34     Changed Minor version to 5.40.
+*         : 08.10.2019 1.35     Changed Minor version to 5.50.
+*         : 10.12.2019 1.36     Changed Minor version to 5.51.
+*         : 14.02.2020 1.37     Changed Minor version to 5.52.
+*         : 31.07.2020 1.38     Changed Minor version to 5.60.
+*         : 04.08.2020 1.39     Changed Minor version to 5.61.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* C99 (or later) is necessary because r_rx_compiler.h uses Pragma operator and variadic macros.
+ * This means that r_typedefs.h is not used in any case. */
+#if !defined(__cplusplus) && !defined(CPPAPP)
+/* All implementation is C99 (or later) */
+#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)
+#include    <stdint.h>
+#include    <stdbool.h>
+#include    <stdio.h>
+#include    <stddef.h>
+#else
+#error "This version of FIT needs C99 (or later)."
+#endif
+#else /* defined(__cplusplus) || defined(CPPAPP) */
+/* Interface might be referred from C++ */
+#include    <stdint.h>
+#include    <stdbool.h>
+#include    <stdio.h>
+#include    <stddef.h>
+#endif /* !defined(__cplusplus) && !defined(CPPAPP) */
+
+#if defined(__CCRX__) || defined(__ICCRX__)
+/* Intrinsic functions provided by compiler. */
+#include <machine.h>
+#elif defined(__GNUC__)
+/* No header file for intrinsic functions. */
+#else
+/* PORT: Use header file for other compiler and port r_rx_compiler.h. */
+#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef R_BSP_COMMON_H
+#define R_BSP_COMMON_H
+
+/* Version Number of r_bsp. */
+#define R_BSP_VERSION_MAJOR           (5)
+#define R_BSP_VERSION_MINOR           (61)
+
+/* This macro is used to suppress compiler messages about not only a parameter but also a auto variable not being used
+ * in a function. The nice thing about using this implementation is that it does not take any extra RAM or ROM.
+ * This macro is available for the followings:
+ * CC-RX's 'M0520826:Parameter "XXXX" was never referenced'
+ * CC-RX's 'W0520550:Variable "XXXX" was set but never used'
+ * GNURX's 'unused parameter 'XXXX' [-Wunused-parameter]'
+ * GNURX's 'variable 'XXXX' set but not used [-Wunused-but-set-variable]'
+ * When the variable is declared as volatile, the '&' can be applied like 'R_INTERNAL_NOT_USED(&volatile_variable);'.
+ */
+#define INTERNAL_NOT_USED(p)        ((void)(p))
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+/* Available delay units. */
+typedef enum
+{
+    BSP_DELAY_MICROSECS = 1000000,  // Requested delay amount is in microseconds
+    BSP_DELAY_MILLISECS = 1000,     // Requested delay amount is in milliseconds
+    BSP_DELAY_SECS = 1              // Requested delay amount is in seconds
+} bsp_delay_units_t;
+
+/* Easy to use typedef for FIT module callback functions. */
+typedef void (*fit_callback_t)(void *p_args);
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+uint32_t R_BSP_GetVersion(void);
+bool R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units);
+uint32_t R_BSP_GetIClkFreqHz(void);
+
+/* End of multiple inclusion prevention macro */
+#endif  /* R_BSP_COMMON_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c
new file mode 100644
index 00000000..b575b573
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c
@@ -0,0 +1,672 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_cpu.c
+* Description  : This module implements CPU specific functions. An example is enabling/disabling interrupts.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 3.00     Merged processing of all devices.
+*                               Added support for GNUC and ICCRX.
+*                               Fixed coding style.
+*         : 26.07.2019 3.10     Added the API function(R_BSP_SoftwareReset).
+*                               Modified comment of API function to Doxygen style.
+*                               Added the vbatt_voltage_stability_wait function.
+*                               Modified the following functions.
+*                               - R_BSP_RegisterProtectEnable
+*                               - R_BSP_RegisterProtectDisable
+*         : 31.07.2019 3.11     Deleted the compile condition for R_BSP_SoftwareReset.
+*         : 08.10.2019 3.12     Changed the following functions.
+*                               - R_BSP_InterruptsDisable
+*                               - R_BSP_InterruptsEnable
+*                               - R_BSP_CpuInterruptLevelWrite
+*         : 10.12.2019 3.13     Modified the following functions.
+*                               - R_BSP_RegisterProtectEnable
+*                               - R_BSP_RegisterProtectDisable
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Platform support. */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION
+/* Key code for writing PRCR register. */
+#define BSP_PRV_PRCR_KEY        (0xA500)
+#endif
+
+#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING
+/* The macro definition for combinations where settings of USBVON bit conflict. */
+#define BSP_PRV_USBVON_CONFLICT (BSP_VOL_USB_POWEROFF | BSP_VOL_USB_POWERON)
+/* The macro definition for combinations where settings of PGAVLS bit conflict. */
+#define BSP_PRV_PGAVLS_CONFLICT (BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT | BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT)
+/* The macro definition for combinations where settings of RICVLS bit conflict. */
+#define BSP_PRV_RICVLS_CONFLICT (BSP_VOL_RIIC_4_5V_OROVER | BSP_VOL_RIIC_UNDER_4_5V)
+/* Bit number of VOLSR register. */
+#define BSP_PRV_VOLSR_RICVLS_BIT_NUM  (7)
+#define BSP_PRV_VOLSR_PGAVLS_BIT_NUM  (6)
+#define BSP_PRV_VOLSR_USBVON_BIT_NUM  (2)
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION
+/* Used for holding reference counters for protection bits. */
+static volatile uint16_t s_protect_counters[BSP_REG_PROTECT_TOTAL_ITEMS];
+
+/* Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */
+static const    uint16_t s_prcr_masks[BSP_REG_PROTECT_TOTAL_ITEMS-1] = 
+{
+#ifdef BSP_MCU_RCPC_PRC0
+    0x0001,         /* PRC0. */
+#endif
+#ifdef BSP_MCU_RCPC_PRC1
+    0x0002,         /* PRC1. */
+#endif
+#ifdef BSP_MCU_RCPC_PRC2
+    0x0004,         /* PRC2. */
+#endif
+#ifdef BSP_MCU_RCPC_PRC3
+    0x0008,         /* PRC3. */
+#endif
+};
+#endif
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_InterruptsDisable
+ ******************************************************************************************************************//**
+ * @brief Globally disables interrupts.
+ * @details This function globally disables interrupts. This is performed by clearing the 'I' bit in the CPU's 
+ * Processor Status Word (PSW) register.
+ * @note The 'I' bit of the PSW can only be modified when in Supervisor Mode. If the CPU is in User Mode and this 
+ * function is called, this function does nothing.
+ */
+void R_BSP_InterruptsDisable (void)
+{
+    uint32_t    pmode;
+
+    /* Read current processor mode. */
+    pmode = (R_BSP_GET_PSW() & 0x00100000);
+
+    /* Check current processor mode. */
+    if (0 == pmode)
+    {
+        /* Use the compiler intrinsic function to clear the I flag. */
+        R_BSP_CLRPSW_I();
+    }
+
+} /* End of function R_BSP_InterruptsDisable() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_InterruptsEnable
+ ******************************************************************************************************************//**
+ * @brief Globally enable interrupts.
+ * @details This function globally enables interrupts. This is performed by setting the 'I' bit in the CPU's Processor 
+ * Status Word (PSW) register.
+ * @note The 'I' bit of the PSW can only be modified when in Supervisor Mode. If the CPU is in User Mode and this 
+ * function is called, this function does nothing.
+ */
+void R_BSP_InterruptsEnable (void)
+{
+    uint32_t    pmode;
+
+    /* Read current processor mode. */
+    pmode = (R_BSP_GET_PSW() & 0x00100000);
+
+    /* Check current processor mode. */
+    if (0 == pmode)
+    {
+        /* Use the compiler intrinsic function to set the I flag. */
+        R_BSP_SETPSW_I();
+    }
+
+} /* End of function R_BSP_InterruptsEnable() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_CpuInterruptLevelRead
+ ******************************************************************************************************************//**
+ * @brief Reads the CPU's Interrupt Priority Level.
+ * @return The CPU's Interrupt Priority Level.
+ * @details This function reads the CPU's Interrupt Priority Level. This level is stored in the IPL bits of the 
+ * Processor Status Word (PSW) register.
+ */
+uint32_t R_BSP_CpuInterruptLevelRead (void)
+{
+    /* Use the compiler intrinsic function to read the CPU IPL. */
+    uint32_t psw_value;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    psw_value = (uint32_t)R_BSP_GET_PSW();
+    psw_value = psw_value & 0x0f000000;
+    psw_value = psw_value >> 24;
+
+    return psw_value;
+} /* End of function R_BSP_CpuInterruptLevelRead() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_CpuInterruptLevelWrite
+ ******************************************************************************************************************//**
+ * @brief Writes the CPU's Interrupt Priority Level.
+ * @param[in] level The level to write to the CPU's IPL.
+ * @retval true Successful, CPU's IPL has been written.
+ * @retval false Failure, provided 'level' has invalid IPL value or called when the CPU is in User Mode.
+ * @details This function writes the CPU's Interrupt Priority Level. This level is stored in the IPL bits of the 
+ * Processor Status Word (PSW) register. This function does check to make sure that the IPL being written is valid. 
+ * The maximum and minimum valid settings for the CPU IPL are defined in mcu_info.h using the BSP_MCU_IPL_MAX and 
+ * BSP_MCU_IPL_MIN macros.
+ * @note The CPU's IPL can only be modified by the user when in Supervisor Mode. If the CPU is in User Mode and this
+ * function is called, this function does not control IPL and return false.
+ */
+bool R_BSP_CpuInterruptLevelWrite (uint32_t level)
+{
+    bool ret;
+    uint32_t pmode;
+
+    /* The R_BSP_SET_IPL() function use the MVTIPL instruction.
+       The MVTIPL instruction needs to set an immediate value to src. */
+
+    ret = false;
+
+    /* Read current processor mode. */
+    pmode = (R_BSP_GET_PSW() & 0x00100000);
+
+    /* Check current processor mode. */
+    if (0 == pmode)
+    {
+        ret = true;
+
+        /* Use the compiler intrinsic function to set the CPU IPL. */
+        switch (level)
+        {
+            case (0):
+
+                /* IPL = 0 */
+                R_BSP_SET_IPL(0);
+                break;
+
+            case (1):
+
+                /* IPL = 1 */
+                R_BSP_SET_IPL(1);
+                break;
+
+            case (2):
+
+                /* IPL = 2 */
+                R_BSP_SET_IPL(2);
+                break;
+
+            case (3):
+
+                /* IPL = 3 */
+                R_BSP_SET_IPL(3);
+                break;
+
+            case (4):
+
+                /* IPL = 4 */
+                R_BSP_SET_IPL(4);
+                break;
+
+            case (5):
+
+                /* IPL = 5 */
+                R_BSP_SET_IPL(5);
+                break;
+
+            case (6):
+
+                /* IPL = 6 */
+                R_BSP_SET_IPL(6);
+                break;
+
+            case (7):
+
+                /* IPL = 7 */
+                R_BSP_SET_IPL(7);
+                break;
+
+    #if 7 < BSP_MCU_IPL_MAX
+            case (8):
+
+                /* IPL = 8 */
+                R_BSP_SET_IPL(8);
+                break;
+
+            case (9):
+
+                /* IPL = 9 */
+                R_BSP_SET_IPL(9);
+                break;
+
+            case (10):
+
+                /* IPL = 10 */
+                R_BSP_SET_IPL(10);
+                break;
+
+            case (11):
+
+                /* IPL = 11 */
+                R_BSP_SET_IPL(11);
+                break;
+
+            case (12):
+
+                /* IPL = 12 */
+                R_BSP_SET_IPL(12);
+                break;
+
+            case (13):
+
+                /* IPL = 13 */
+                R_BSP_SET_IPL(13);
+                break;
+
+            case (14):
+
+                /* IPL = 14 */
+                R_BSP_SET_IPL(14);
+                break;
+
+            case (15):
+
+                /* IPL = 15 */
+                R_BSP_SET_IPL(15);
+                break;
+    #endif /* BSP_MCU_IPL_MAX */
+
+            default:
+                ret = false;
+                break;
+        }
+    }
+
+    return ret;
+} /* End of function R_BSP_CpuInterruptLevelWrite() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_RegisterProtectEnable
+ ******************************************************************************************************************//**
+ * @brief Enables write protection for selected registers.
+ * @param[in] regs_to_protect Which registers to enable write protection for.
+ * @details This function enables write protection for the input registers. Only certain MCU registers have the 
+ * ability to be write protected. To see which registers are available to be protected by this function look at the 
+ * bsp_reg_protect_t enum in r_bsp_cpu.h for your MCU.
+ * This function, and R_BSP_RegisterProtectDisable(), use counters for each entry in the bsp_reg_protect_t enum so 
+ * that users can call these functions multiple times without problem. This function uses the interrupt disable / 
+ * enable function by controlling the Processor Interrupt Priority Level (IPL) of the R_BSP_InterruptControl function, 
+ * because counter control is the critical section. If the function is executed while the processor mode is supervisor 
+ * mode, interrupts that are at or below the specified interrupt priority level will be disabled by controlling the 
+ * IPL. If the function is executed while the processor mode is user mode, the IPL controlling does not execute. An 
+ * example of why this is needed is shown below in the Special Notes section below.
+ * @note 
+ * (1) About why counters are needed. \n
+ * See Section 5.7 in the application note for details.\n
+ * (2) Notes on user mode \n
+ * The R_BSP_InterruptControl function used to secure atomicity in the critical section of the counter control with 
+ * this function is valid only in supervisor mode. When this function is executed in user mode, the 
+ * R_BSP_InterruptControl function is executed but atomicity is not to secure.
+ */
+void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect)
+{
+#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION
+    bsp_int_ctrl_t int_ctrl;
+
+    /* Set IPL to the maximum value to disable all interrupts,
+     * so the scheduler can not be scheduled in critical region.
+     * Note: Please set this macro more than IPR for other FIT module interrupts. */
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl);
+
+    /* Is it safe to disable write access? */
+    if (0 != s_protect_counters[regs_to_protect])
+    {
+        /* Decrement the protect counter */
+        s_protect_counters[regs_to_protect]--;
+    }
+
+    /* Is it safe to disable write access? */
+    if (0 == s_protect_counters[regs_to_protect])
+    {
+        if (BSP_REG_PROTECT_MPC != regs_to_protect)
+        {
+            /* Enable protection using PRCR register. */
+            /* When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
+               disable writes.
+               b15:b8 PRKEY - Write 0xA5 to upper byte to enable writing to lower byte
+               b7:b4  Reserved (set to 0)
+               b3     PRC3  - Please check the user's manual.
+               b2     PRC2  - Please check the user's manual.
+               b1     PRC1  - Please check the user's manual.
+               b0     PRC0  - Please check the user's manual.
+            */
+            SYSTEM.PRCR.WORD = (uint16_t)((SYSTEM.PRCR.WORD | BSP_PRV_PRCR_KEY) & (~s_prcr_masks[regs_to_protect]));
+        }
+        else
+        {
+            /* Enable protection for MPC using PWPR register. */
+            /* Enable writing of PFSWE bit. It could be assumed that the B0WI bit is still cleared from a call to
+               protection disable function, but it is written here to make sure that the PFSWE bit always gets
+               cleared. */
+            MPC.PWPR.BIT.B0WI = 0;
+
+            /* Disable writing to PFS registers. */
+            MPC.PWPR.BIT.PFSWE = 0;
+
+            /* Disable writing of PFSWE bit. */
+            MPC.PWPR.BIT.B0WI = 1;
+        }
+    }
+
+    /* Restore the IPL. */
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl);
+
+#else /* BSP_MCU_REGISTER_WRITE_PROTECTION */
+    /* No registers to protect. */
+    /* This code is only used to remove compiler info messages about this parameter not being used. */
+    INTERNAL_NOT_USED(regs_to_protect);
+#endif /* BSP_MCU_REGISTER_WRITE_PROTECTION */
+} /* End of function R_BSP_RegisterProtectEnable() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_RegisterProtectDisable
+ ******************************************************************************************************************//**
+ * @brief Disables write protection for selected registers.
+ * @param[in] regs_to_unprotect Which registers to disable write protection for.
+ * @details This function disables write protection for the input registers. Only certain MCU registers have the 
+ * ability to be write protected. To see which registers are available to be protected by this function look at the 
+ * bsp_reg_protect_t enum in r_bsp_cpu.h for your MCU.
+ * This function, and R_BSP_RegisterProtectEnable(), use counters for each entry in the bsp_reg_protect_t enum so that 
+ * users can call these functions multiple times without problem. This function uses the interrupt disable / 
+ * enable function by controlling the Processor Interrupt Priority Level (IPL) of the R_BSP_InterruptControl function, 
+ * because counter control is the critical section. If the function is executed while the processor mode is supervisor 
+ * mode, interrupts that are at or below the specified interrupt priority level will be disabled by controlling the 
+ * IPL. If the function is executed while the processor mode is user mode, the IPL controlling does not execute.
+ * @note The R_BSP_InterruptControl function used to secure atomicity in the critical section of the counter control 
+ * with this function is valid only in supervisor mode. When this function is executed in user mode, the 
+ * R_BSP_InterruptControl function is executed but atomicity is not to secure.
+ */
+void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect)
+{
+#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION
+    bsp_int_ctrl_t int_ctrl;
+
+    /* Set IPL to the maximum value to disable all interrupts,
+     * so the scheduler can not be scheduled in critical region.
+     * Note: Please set this macro more than IPR for other FIT module interrupts. */
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl);
+
+    /* If this is first entry then disable protection. */
+    if (0 == s_protect_counters[regs_to_unprotect])
+    {
+        if (BSP_REG_PROTECT_MPC != regs_to_unprotect)
+        {
+            /* Enable protection using PRCR register. */
+            /* When writing to the PRCR register the upper 8-bits must be the correct key.
+               Set lower bits to 1 to enable writes.
+               b15:b8 PRKEY - Write 0xA5 to upper byte to enable writing to lower byte
+               b7:b4  Reserved (set to 0)
+               b3     PRC3  - Please check the user's manual.
+               b2     PRC2  - Please check the user's manual.
+               b1     PRC1  - Please check the user's manual.
+               b0     PRC0  - Please check the user's manual.
+            */
+            SYSTEM.PRCR.WORD = (uint16_t)((SYSTEM.PRCR.WORD | BSP_PRV_PRCR_KEY) | s_prcr_masks[regs_to_unprotect]);
+        }
+        else
+        {
+            /* Disable protection for MPC using PWPR register. */
+            /* Enable writing of PFSWE bit. */
+            MPC.PWPR.BIT.B0WI = 0;
+
+            /* Enable writing to PFS registers. */
+            MPC.PWPR.BIT.PFSWE = 1;
+        }
+    }
+
+    /* Increment the protect counter */
+    s_protect_counters[regs_to_unprotect]++;
+
+    /* Restore the IPL. */
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl);
+
+#else /* BSP_MCU_REGISTER_WRITE_PROTECTION */
+    /* No registers to protect. */
+    /* This code is only used to remove compiler info messages about this parameter not being used. */
+    INTERNAL_NOT_USED(regs_to_unprotect);
+#endif /* BSP_MCU_REGISTER_WRITE_PROTECTION */
+} /* End of function R_BSP_RegisterProtectDisable() */
+
+#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING
+/**********************************************************************************************************************
+ * Function Name: R_BSP_VoltageLevelSetting
+ ******************************************************************************************************************//**
+ * @brief This API function is used excessively with the RX66T and RX72T. It makes settings to the voltage level 
+ * setting register (VOLSR) that are necessary in order to use the USB, AD, and RIIC peripheral modules. Call this 
+ * function only when it is necessary to change the register settings.
+ * @param[in] ctrl_ptn Register Setting Patterns
+ * The following setting patterns cannot be selected at the same time.
+ * When specifying more than one pattern at the same time, use the "|" (OR) operator.
+ * - BSP_VOL_USB_POWEROFF and BSP_VOL_USB_POWERON
+ * - BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT and BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT
+ * - BSP_VOL_RIIC_4_5V_OROVER and BSP_VOL_RIIC_UNDER_4_5V
+ *
+ *   BSP_VOL_USB_POWEROFF: Updates the USBVON bit to 0.
+ *
+ *   BSP_VOL_USB_POWERON: Updates the USBVON bit to 1.
+ *
+ *   BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT: Updates the PGAVLS bit to 0.
+ *
+ *   BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT: Updates the PGAVLS bit to 1.
+ *
+ *   BSP_VOL_RIIC_4_5V_OROVER: Updates the RICVLS bit to 0.
+ *
+ *   BSP_VOL_RIIC_UNDER_4_5V: Updates the RICVLS bit to 1.
+ * @retval true Processing completed, register successfully updated.
+ * @retval false The function was called under the following conditions, so the register setting was not updated.
+ * - Setting patterns that cannot be selected at the same time were selected.
+ * - A setting pattern related to the USB was selected when the USB was not in the module stop state.
+ * - A setting pattern related to the AD was selected when the AD was not in the module stop state.
+ * - A setting pattern related to the RIIC was selected when the RIIC was not in the module stop state.
+ * @details This function initializes the voltage level setting register (VOLSR), which is necessary in order to use 
+ * the USB, AD and RIIC peripheral modules. When specifying a setting pattern related to the USB, call this function 
+ * before the USB is released from the module stop state. When specifying a setting pattern related to the AD, call 
+ * this function before the AD (unit 0 and unit 1) is released from the module stop state. When specifying a setting 
+ * pattern related to the RIIC, call this function before the RIIC is released from the module stop state. If the 
+ * function is called with a setting pattern related to the USB specified after the USB is released from the module 
+ * stop state, the function returns "false" as the return value and does not update the register settings. If the 
+ * function is called with a setting pattern related to the AD specified after the AD (unit 0 and unit 1) is released 
+ * from the module stop state, the function returns "false" as the return value and does not update the register 
+ * settings. Finally, if the function is called with a setting pattern related to the RIIC specified after the RIIC is 
+ * released from the module stop state, the function returns "false" as the return value and does not update the 
+ * register settings.
+ */
+bool R_BSP_VoltageLevelSetting (uint8_t ctrl_ptn)
+{
+    uint8_t  *p_volsr_addr;
+
+#if BSP_CFG_PARAM_CHECKING_ENABLE == 1
+    /* ---- CHECK ARGUMENTS ---- */
+    if (BSP_PRV_USBVON_CONFLICT == (ctrl_ptn & BSP_PRV_USBVON_CONFLICT))
+    {
+        return false;
+    }
+
+    if (BSP_PRV_PGAVLS_CONFLICT == (ctrl_ptn & BSP_PRV_PGAVLS_CONFLICT))
+    {
+        return false;
+    }
+
+    if (BSP_PRV_RICVLS_CONFLICT == (ctrl_ptn & BSP_PRV_RICVLS_CONFLICT))
+    {
+        return false;
+    }
+#endif
+
+    /* Check USB module stop state. */
+    if(0 != (ctrl_ptn & BSP_PRV_USBVON_CONFLICT))
+    {
+        /* Casting is valid because it matches the type to the right side or argument. */
+        if(0 == MSTP(USB0))
+        {
+            return false;
+        }
+    }
+
+    /* Check AD module stop state. */
+    if(0 != (ctrl_ptn & BSP_PRV_PGAVLS_CONFLICT))
+    {
+        /* Casting is valid because it matches the type to the right side or argument. */
+        if((0 == MSTP(S12AD)) || (0 == MSTP(S12AD1)))
+        {
+            return false;
+        }
+    }
+
+    /* Check RIIC module stop state. */
+    if(0 != (ctrl_ptn & BSP_PRV_RICVLS_CONFLICT))
+    {
+        /* Casting is valid because it matches the type to the right side or argument. */
+        if(0 == MSTP(RIIC0))
+        {
+            return false;
+        }
+    }
+
+    /* Protect off. */
+    SYSTEM.PRCR.WORD = 0xA502;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    p_volsr_addr = (uint8_t *)&SYSTEM.VOLSR.BYTE;
+
+    /* Updated the RICVLS bit. */
+    if(0 != (ctrl_ptn & BSP_VOL_RIIC_UNDER_4_5V))
+    {
+        R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_RICVLS_BIT_NUM);
+    }
+
+    if(0 != (ctrl_ptn & BSP_VOL_RIIC_4_5V_OROVER))
+    {
+        R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_RICVLS_BIT_NUM);
+    }
+
+    /* Updated the PGAVLS bit. */
+    if(0 != (ctrl_ptn & BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT))
+    {
+        R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_PGAVLS_BIT_NUM);
+    }
+
+    if(0 != (ctrl_ptn & BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT))
+    {
+        R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_PGAVLS_BIT_NUM);
+    }
+
+    /* Updated the USBVON bit. */
+    if(0 != (ctrl_ptn & BSP_VOL_USB_POWERON))
+    {
+        R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_USBVON_BIT_NUM);
+    }
+
+    if(0 != (ctrl_ptn & BSP_VOL_USB_POWEROFF))
+    {
+        R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_USBVON_BIT_NUM);
+    }
+
+    /* Protect on. */
+    SYSTEM.PRCR.WORD = 0xA500;
+
+    return true;
+}  /* End of function R_BSP_VoltageLevelSetting() */ 
+#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_SoftwareReset
+ ******************************************************************************************************************//**
+ * @details Reset the MCU by Software Reset.
+ */
+void R_BSP_SoftwareReset(void)
+{
+#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION
+    /* Protect off. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR);
+#endif
+
+    /* Resets the MCU. */
+    SYSTEM.SWRR = 0xA501;
+
+    /* WAIT_LOOP */
+    while(1)
+    {
+         R_BSP_NOP();
+    }
+} /* End of function R_BSP_SoftwareReset() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_register_protect_open
+* Description  : Initializes variables needed for register protection functionality.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+void bsp_register_protect_open (void)
+{
+#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION
+    uint32_t i;
+
+    /* Initialize reference counters to 0. */
+    /* WAIT_LOOP */
+    for (i = 0; i < BSP_REG_PROTECT_TOTAL_ITEMS; i++)
+    {
+        s_protect_counters[i] = 0;
+    }
+#else
+    /* No registers to protect. */
+#endif
+} /* End of function bsp_register_protect_open() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_ram_initialize
+* Description  : Initialize ram variable.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+void bsp_ram_initialize (void)
+{
+    uint32_t i;
+
+    /* Initialize g_bsp_Locks to 0. */
+    /* WAIT_LOOP */
+    for (i = 0; i < BSP_NUM_LOCKS; i++)
+    {
+        g_bsp_Locks[i].lock = 0;
+    }
+} /* End of function bsp_ram_initialize() */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c
new file mode 100644
index 00000000..a72ade03
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c
@@ -0,0 +1,1085 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_interrupts.c
+* Description  : This module allows for callbacks to be registered for certain interrupts. 
+*                And handle exception interrupts.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+*         : 08.04.2019 1.01     Added process for Group IE0 interrupts.
+*                               Added process for EXNMI interrupts.
+*         : 26.07.2019 1.10     Modified comment of API function to Doxygen style.
+*                               Modified the following function for added function.
+*                               - R_BSP_InterruptControl
+*                               Added the following functions.
+*                               - bsp_fit_interrupts_control
+*                               - bsp_fit_interrupt_enable
+*                               - bsp_fit_interrupt_disable
+*                               Fixed coding style.
+*         : 08.10.2019 1.11     Added process for software interrupt.
+*         : 10.12.2019 1.12     Modified comment.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#ifdef BSP_MCU_FLOATING_POINT
+/* Defines CV, CO, CZ, CU, CX, and CE bits. */
+#define BSP_PRV_FPU_CAUSE_FLAGS     (0x000000FC)
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* This array holds callback functions. */
+static void (* g_bsp_vectors[BSP_INT_SRC_TOTAL_ITEMS])(void * pdata);
+
+static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata);
+
+#ifdef BSP_MCU_GROUP_INTERRUPT
+static bsp_int_err_t bsp_gr_int_enable_disable (bsp_int_src_t vector, bool enable, uint32_t ipl);
+#endif /* BSP_MCU_GROUP_INTERRUPT */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_InterruptRequestEnable
+ ******************************************************************************************************************//**
+ * @brief Enable the specified interrupt request.
+ * @param[in] vector Interrupt vector number.
+ * @details Enable the specified interrupt request. Calculate the corresponding IER [m].IEN [j] from the vector number 
+ * of the argument, and set "1" to that bit. The macro defined in iodefine.h can be used to the setting of the 
+ * argument "vector". A description example is shown in Example.
+ * @note When setting an immediate value for an argument "vector", the argument must be 0 to 255. Don't set the 
+ * vector number of the reserved interrupt source to the argument.
+ */
+void R_BSP_InterruptRequestEnable (uint32_t vector)
+{
+    uint32_t ier_reg_num;
+    uint32_t ien_bit_num;
+    uint8_t  *p_ier_addr;
+
+    /* Calculate the register number. (IER[m].IENj)(m = vector_number / 8) */
+    ier_reg_num = vector >> 3;
+
+    /* Calculate the bit number. (IERm.IEN[j])(j = vector_number % 8) */
+    ien_bit_num = vector & 0x00000007;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    p_ier_addr = (uint8_t *)&ICU.IER[ier_reg_num].BYTE;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    R_BSP_BIT_SET(p_ier_addr, ien_bit_num);
+} /* End of function R_BSP_InterruptRequestEnable() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_InterruptRequestDisable
+ ******************************************************************************************************************//**
+ * @brief Disable the specified interrupt request.
+ * @param[in] vector Interrupt vector number.
+ * @details Disable the specified interrupt request. Calculate the corresponding IER [m].IEN [j] from the vector 
+ * number of the argument, and clear "0" to that bit. The macro defined in iodefine.h can be used to the setting of 
+ * the argument "vector". A description example is shown in Example.
+ * @note When setting an immediate value for an argument "vector", the argument must be 0 to 255. Don't set the 
+ * vector number of the reserved interrupt source to the argument.
+ */
+void R_BSP_InterruptRequestDisable (uint32_t vector)
+{
+    uint32_t ier_reg_num;
+    uint32_t ien_bit_num;
+    uint8_t  *p_ier_addr;
+
+    /* Calculate the register number. (IER[m].IENj)(m = vector_number / 8) */
+    ier_reg_num = vector >> 3;
+
+    /* Calculate the bit number. (IERm.IEN[j])(j = vector_number % 8) */
+    ien_bit_num = vector & 0x00000007;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    p_ier_addr = (uint8_t *)&ICU.IER[ier_reg_num].BYTE;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    R_BSP_BIT_CLEAR(p_ier_addr, ien_bit_num);
+} /* End of function R_BSP_InterruptRequestDisable() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_interrupt_open
+* Description  : Initialize callback function array.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void bsp_interrupt_open (void)
+{
+    uint32_t i;
+
+    /* WAIT_LOOP */
+    for (i = 0; i < BSP_INT_SRC_TOTAL_ITEMS; i++)
+    {
+        /* Casting is valid because it matches the type to the right side or argument. */
+        g_bsp_vectors[i] = FIT_NO_FUNC;
+    }
+
+#ifdef BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT
+    /* Initialize mapped interrupts. */
+    bsp_mapped_interrupt_open();
+#endif
+
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+    R_BSP_SoftwareInterruptOpen(BSP_SWINT_UNIT1);
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+    R_BSP_SoftwareInterruptOpen(BSP_SWINT_UNIT2);
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+} /* End of function bsp_interrupt_open() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_InterruptWrite
+ ******************************************************************************************************************//**
+ * @brief Registers a callback function for an interrupt.
+ * @param[in] vector Which interrupt to register a callback for.
+ * @param[in] callback Pointer to function to call when interrupt occurs.
+ * @retval BSP_INT_SUCCESS Successful, callback has been registered.
+ * @retval BSP_INT_ERR_INVALID_ARG Invalid function address input, any previous function has been unregistered.
+ * @details This function registers a callback function for an interrupt. If FIT_NO_FUNC, NULL, or any other invalid 
+ * function address is passed for the callback argument then any previously registered callbacks are unregistered.
+ * If one of the interrupts that is handled by this code is triggered then the interrupt handler will query this code 
+ * to see if a valid callback function is registered. If one is found then the callback function will be called.
+ * If one is not found then the interrupt handler will clear the appropriate flag(s) and exit. If the user has a 
+ * callback function registered and wishes to no longer handle the interrupt then the user should call this function 
+ * again with FIT_NO_FUNC as the vector parameter.
+ * @note Use of FIT_NO_FUNC is preferred over NULL since access to the address defined by FIT_NO_FUNC will cause a 
+ * bus error which is easy for the user to catch. NULL typically resolves to 0 which is a valid address on RX MCUs.
+ */
+bsp_int_err_t R_BSP_InterruptWrite (bsp_int_src_t vector,  bsp_int_cb_t callback)
+{
+    bsp_int_err_t err;
+
+    err = BSP_INT_SUCCESS;
+
+    /* Check for valid address. */
+    if (((uint32_t)callback == (uint32_t)NULL) || ((uint32_t)callback == (uint32_t)FIT_NO_FUNC))
+    {
+        /* Casting is valid because it matches the type to the right side or argument. */
+        g_bsp_vectors[vector] = FIT_NO_FUNC;
+    }
+    else
+    {
+        g_bsp_vectors[vector] = callback;
+    }
+
+    return err;
+} /* End of function R_BSP_InterruptWrite() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_InterruptRead
+ ******************************************************************************************************************//**
+ * @brief Gets the callback for an interrupt if one is registered.
+ * @param[in] vector Which interrupt to read the callback for.
+ * @param[out] callback Pointer to where to store callback address.
+ * @retval BSP_INT_SUCCESS Successful, callback address has been returned.
+ * @retval BSP_INT_ERR_NO_REGISTERED_CALLBACK No valid callback has been registered for this interrupt source.
+ * @details This function returns the callback function address for an interrupt if one has been registered. If a 
+ * callback function has not been registered then an error is returned and nothing is stored to the callback address.
+ */
+bsp_int_err_t R_BSP_InterruptRead (bsp_int_src_t vector, bsp_int_cb_t * callback)
+{
+    bsp_int_err_t err;
+
+    err = BSP_INT_SUCCESS;
+
+    /* Check for valid address. */
+    if (((uint32_t)g_bsp_vectors[vector] == (uint32_t)NULL) || ((uint32_t)g_bsp_vectors[vector] == (uint32_t)FIT_NO_FUNC))
+    {
+        err = BSP_INT_ERR_NO_REGISTERED_CALLBACK;
+    }
+    else
+    {
+        *callback = g_bsp_vectors[vector];
+    }
+
+    return err;
+} /* End of function R_BSP_InterruptRead() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_InterruptControl
+ ******************************************************************************************************************//**
+ * @brief Controls various interrupt operations.
+ * @param[in] vector Which interrupt to control for.\n
+ * If the interrupt control commands is the BSP_INT_CMD_FIT_INTERRUPT_ENABLE or the BSP_INT_CMD_FIT_INTERRUPT_DISABLE 
+ * commands, set BSP_INT_SRC_EMPTY to "vector" because no arguments are used.
+ * @param[in] cmd Interrupt control command.
+ * @param[in,out] pdata Pointer to the argument for each interrupt control command. Typecasted to void*. See typedef 
+ * defines of bsp_int_ctrl_t. \n
+ * Most of the interrupt control commands do not need the argument and take FIT_NO_PTR for 
+ * this parameter. If the interrupt control command is the BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command, set the 
+ * interrupt priority level for group interrupts as the argument. If the interrupt control command is the 
+ * BSP_INT_CMD_FIT_INTERRUPT_DISABLE command, set the address of a variable for saving the current processor interrupt 
+ * priority level in the argument. If the interrupt control command is the BSP_INT_CMD_FIT_INTERRUPT_ENABLE command, 
+ * set the address of a variable used in the BSP_INT_CMD_FIT_INTERRUPT_DISABLE command.
+ * @retval BSP_INT_SUCCESS Successful.
+ * @retval BSP_INT_ERR_NO_REGISTERED_CALLBACK No valid callback has been registered for this interrupt source.
+ * @retval BSP_INT_ERR_INVALID_ARG The command passed is invalid.
+ * @retval BSP_INT_ERR_UNSUPPORTED This processing is not supported.
+ * @retval BSP_INT_ERR_GROUP_STILL_ENABLED Group interrupt request remains enabled.
+ * @retval BSP_INT_ERR_INVALID_IPL Illegal IPL value input.
+ * @details This function controls the interrupt callback function call and enabling/disabling interrupts such as bus 
+ * error interrupt, floating-point exception, NMI pin interrupt, and group interrupts, and enabling/disabling 
+ * interrupts by controlling the Processor Interrupt Priority Level. When BSP_INT_CMD_GROUP_INTERRUPT_ENABLE is set as 
+ * the interrupt control command, the interrupt request (IER) for group interrupts is enabled and also the interrupt 
+ * priority level is set. The interrupt priority level set must be higher than the current level. When 
+ * BSP_INT_CMD_GROUP_INTERRUPT_DISABLE is set as the interrupt control command, the interrupt request (IER) for group 
+ * interrupts is disabled. Note that the interrupt request (IER) for group interrupts cannot be disabled as long as 
+ * all interrupt requests (GEN) caused by grouped interrupt sources are disabled. When 
+ * BSP_INT_CMD_FIT_INTERRUPT_DISABLE is set as the interrupt control command, the current processor interrupt priority 
+ * level (IPL) is saved to the address specified by pdata as an argument, and disables interrupts by controlling the 
+ * IPL. The value of IPL to be set is the value of BSP_CFG_FIT_IPL_MAX. When BSP_INT_CMD_FIT_INTERRUPT_ENABLE is set 
+ * as the interrupt control command, the interrupt is enabled by setting the value stored in the address specified by 
+ * pdata to IPL. These two commands are valid only in supervisor mode. When BSP_INT_CMD_FIT_INTERRUPT_DISABLE and 
+ * BSP_INT_CMD_FIT_INTERRUPT_ENABLE commands are executed in user mode, Controlling IPL is not executed and an error 
+ * code BSP_INT_ERR_UNSUPPORTED is returned.
+ * @note BSP_INT_CMD_FIT_INTERRUPT_DISABLE and BSP_INT_CMD_FIT_INTERRUPT_ENABLE commands can be used to secure 
+ * atomicity of critical sections. However, these commands are valid only in supervisor mode. When these commands are 
+ * executed in user mode, atomicity is not to secure.\n
+ * See Section 5.15 in the application note for more information.
+ */
+bsp_int_err_t R_BSP_InterruptControl (bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata)
+{
+    bsp_int_err_t       err;
+    bsp_int_cb_args_t   cb_args;
+
+    err = BSP_INT_SUCCESS;
+
+#ifdef BSP_MCU_GROUP_INTERRUPT
+    /* nothing */
+#else
+    /* This code is only used to remove compiler info messages about these parameters not being used. */
+    INTERNAL_NOT_USED(pdata);
+#endif
+
+    switch (cmd)
+    {
+        case (BSP_INT_CMD_CALL_CALLBACK):
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            if (((uint32_t)g_bsp_vectors[vector] != (uint32_t)NULL) && ((uint32_t)g_bsp_vectors[vector] != (uint32_t)FIT_NO_FUNC))
+            {
+                /* Fill in callback info. */
+                cb_args.vector = vector;
+
+                g_bsp_vectors[vector](&cb_args);
+            }
+            else
+            {
+                err = BSP_INT_ERR_NO_REGISTERED_CALLBACK;
+            }
+            break;
+
+        case (BSP_INT_CMD_INTERRUPT_ENABLE):
+            err = bsp_interrupt_enable_disable(vector, true);
+            break;
+
+        case (BSP_INT_CMD_INTERRUPT_DISABLE):
+            err = bsp_interrupt_enable_disable(vector, false);
+            break;
+
+#ifdef BSP_MCU_GROUP_INTERRUPT
+        case (BSP_INT_CMD_GROUP_INTERRUPT_ENABLE):
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            if(((uint32_t)NULL != (uint32_t)pdata) && ((uint32_t)FIT_NO_FUNC != (uint32_t)pdata))
+            {
+                /* Casting is valid because it matches the type to the right side or argument. */
+                err = bsp_gr_int_enable_disable(vector, true, ((bsp_int_ctrl_t *)pdata)->ipl);
+            }
+            else
+            {
+                 err = BSP_INT_ERR_INVALID_ARG;
+            }
+            break;
+
+        case (BSP_INT_CMD_GROUP_INTERRUPT_DISABLE):
+            err = bsp_gr_int_enable_disable(vector, false, 0);
+            break;
+#endif
+
+        case (BSP_INT_CMD_FIT_INTERRUPT_ENABLE):
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            err = bsp_fit_interrupts_control(true, (bsp_int_ctrl_t *)pdata);
+            break;
+
+        case (BSP_INT_CMD_FIT_INTERRUPT_DISABLE):
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            err = bsp_fit_interrupts_control(false, (bsp_int_ctrl_t *)pdata);
+            break;
+
+        default:
+            err = BSP_INT_ERR_INVALID_ARG;
+            break;
+    }
+
+    return err;
+} /* End of function R_BSP_InterruptControl() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_fit_interrupts_control
+* Description  : 
+* Arguments    : enable -
+*                    Whether to enable or disable the interrupt.
+*                pdata -
+*                    Pointer to variable for saves ipl or restore ipl.
+* Return Value : BSP_INT_SUCCESS -
+*                    Interrupt enabled or disabled.
+*                BSP_INT_ERR_INVALID_ARG -
+*                    Invalid argument input.
+*                BSP_INT_ERR_INVALID_IPL -
+*                    Invalid IPL input.
+*                BSP_INT_ERR_UNSUPPORTED -
+*                    This processing is not supported. (Executed in user mode.)
+***********************************************************************************************************************/
+static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata)
+{
+    bsp_int_err_t       err;
+    uint32_t            pmode;
+    bool                ret;
+    uint32_t            ipl_value;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    if(((uint32_t)NULL != (uint32_t)pdata) && ((uint32_t)FIT_NO_FUNC != (uint32_t)pdata))
+    {
+        /* Read current processor mode. */
+        pmode = (R_BSP_GET_PSW() & 0x00100000);
+
+        /* Check current processor mode. */
+        if (0 == pmode)
+        {
+            err = BSP_INT_SUCCESS;
+
+            if (true == enable)
+            {
+                ipl_value = pdata->ipl;
+            }
+            else
+            {
+                 /* Get the current Processor Interrupt Priority Level (IPL) and save IPL value. */
+                pdata->ipl = R_BSP_CpuInterruptLevelRead();
+
+                /* Set IPL to the maximum value to disable all interrupts,
+                 * so the scheduler can not be scheduled in critical region.
+                 * Note: Please set this macro more than IPR for other FIT module interrupts. */
+                ipl_value = BSP_CFG_FIT_IPL_MAX;
+            }
+
+            if (pdata->ipl < BSP_CFG_FIT_IPL_MAX)
+            {
+                ret = R_BSP_CpuInterruptLevelWrite(ipl_value);
+                if (false == ret)
+                {
+                    err = BSP_INT_ERR_INVALID_IPL;
+                }
+            }
+            else
+            {
+                err = BSP_INT_ERR_INVALID_IPL;
+            }
+        }
+        else
+        {
+            err = BSP_INT_ERR_UNSUPPORTED;
+        }
+    }
+    else
+    {
+        err = BSP_INT_ERR_INVALID_ARG;
+    }
+
+    return err;
+} /* End of function bsp_fit_interrupts_control() */
+
+#ifdef BSP_MCU_GROUP_INTERRUPT
+/***********************************************************************************************************************
+* Function Name: bsp_gr_int_enable_disable
+* Description  : Either enables or disables a group interrupt. If a group interrupt is called multiple times to be
+*                enabled then it will use the highest given IPL. A group interrupt will only be disabled when all
+*                interrupt sources for that group are already disabled.
+* Arguments    : vector -
+*                    An interrupt source inside the group that is to be enabled/disabled.
+*                enable -
+*                    Whether to enable or disable the interrupt.
+*                ipl -
+*                    If enabling a group interrupt, what IPL to use.
+* Return Value : BSP_INT_SUCCESS -
+*                    Interrupt enabled or disabled.
+*                BSP_INT_ERR_INVALID_ARG -
+*                    Invalid IPL or vector
+*                BSP_INT_ERR_GROUP_STILL_ENABLED -
+*                    Not all group interrupts were disabled so group interrupt was not disabled.
+***********************************************************************************************************************/
+static bsp_int_err_t bsp_gr_int_enable_disable (bsp_int_src_t vector, bool enable, uint32_t ipl)
+{
+    bsp_int_err_t err = BSP_INT_SUCCESS;
+
+#if BSP_CFG_PARAM_CHECKING_ENABLE == 1
+    /* If interrupt is going to be enabled, verify that IPL is valid. */
+    if ((true == enable) && ((BSP_MCU_IPL_MIN == ipl) || (ipl > BSP_MCU_IPL_MAX)))
+    {
+        return BSP_INT_ERR_INVALID_ARG;
+    }
+#endif
+
+    if ((vector > BSP_INT_SRC_GR_INT_IE0_TOP) && (vector < BSP_INT_SRC_GR_INT_BE0_TOP))
+    {
+        /* Group IE0. */
+#ifdef BSP_MCU_GROUP_INTERRUPT_IE0
+        if (true == enable)
+        {
+            R_BSP_InterruptRequestDisable(VECT(ICU, GROUPIE0));
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IR(ICU, GROUPIE0)  = 0;
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IPR(ICU, GROUPIE0) = (uint8_t)((ipl > IPR(ICU, GROUPIE0)) ? ipl : IPR(ICU, GROUPIE0));
+            R_BSP_InterruptRequestEnable(VECT(ICU, GROUPIE0));
+        }
+        else
+        {
+            /* Check to make sure all interrupt sources are already disabled for this group. */
+            if (0 == ICU.GENIE0.LONG)
+            {
+                R_BSP_InterruptRequestDisable(VECT(ICU, GROUPIE0));
+
+                /* Casting is valid because it matches the type to the right side or argument. */
+                IPR(ICU, GROUPIE0) = 0;
+            }
+            else
+            {
+                err = BSP_INT_ERR_GROUP_STILL_ENABLED;
+            }
+        }
+#else /* BSP_MCU_GROUP_INTERRUPT_IE0 */
+        err = BSP_INT_ERR_INVALID_ARG;
+#endif /* BSP_MCU_GROUP_INTERRUPT_IE0 */
+    }
+    else if ((vector > BSP_INT_SRC_GR_INT_BE0_TOP) && (vector < BSP_INT_SRC_GR_INT_BL0_TOP))
+    {
+        /* Group BE0. */
+#ifdef BSP_MCU_GROUP_INTERRUPT_BE0
+        if (true == enable)
+        {
+            R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBE0));
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IR(ICU, GROUPBE0)  = 0;
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IPR(ICU, GROUPBE0) = (uint8_t)((ipl > IPR(ICU, GROUPBE0)) ? ipl : IPR(ICU, GROUPBE0));
+            R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBE0));
+        }
+        else
+        {
+            /* Check to make sure all interrupt sources are already disabled for this group. */
+            if (0 == ICU.GENBE0.LONG)
+            {
+                R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBE0));
+
+                /* Casting is valid because it matches the type to the right side or argument. */
+                IPR(ICU, GROUPBE0) = 0;
+            }
+            else
+            {
+                err = BSP_INT_ERR_GROUP_STILL_ENABLED;
+            }
+        }
+#else /* BSP_MCU_GROUP_INTERRUPT_BE0 */
+        err = BSP_INT_ERR_INVALID_ARG;
+#endif /* BSP_MCU_GROUP_INTERRUPT_BE0 */
+    }
+    else if ((vector > BSP_INT_SRC_GR_INT_BL0_TOP) && (vector < BSP_INT_SRC_GR_INT_BL1_TOP))
+    {
+        /* Group BL0. */
+#ifdef BSP_MCU_GROUP_INTERRUPT_BL0
+        if (true == enable)
+        {
+            R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL0));
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IR(ICU, GROUPBL0)  = 0;
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IPR(ICU, GROUPBL0) = (uint8_t)((ipl > IPR(ICU, GROUPBL0)) ? ipl : IPR(ICU, GROUPBL0));
+            R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL0));
+        }
+        else
+        {
+            /* Check to make sure all interrupt sources are already disabled for this group. */
+            if (0 == ICU.GENBL0.LONG)
+            {
+                R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL0));
+
+                /* Casting is valid because it matches the type to the right side or argument. */
+                IPR(ICU, GROUPBL0) = 0;
+            }
+            else
+            {
+                err = BSP_INT_ERR_GROUP_STILL_ENABLED;
+            }
+        }
+#else /* BSP_MCU_GROUP_INTERRUPT_BL0 */
+        err = BSP_INT_ERR_INVALID_ARG;
+#endif /* BSP_MCU_GROUP_INTERRUPT_BL0 */
+    }
+    else if ((vector > BSP_INT_SRC_GR_INT_BL1_TOP) && (vector < BSP_INT_SRC_GR_INT_BL2_TOP))
+    {
+        /* Group BL1. */
+#ifdef BSP_MCU_GROUP_INTERRUPT_BL1
+        if (true == enable)
+        {
+            R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL1));
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IR(ICU, GROUPBL1)  = 0;
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IPR(ICU, GROUPBL1) = (uint8_t)((ipl > IPR(ICU, GROUPBL1)) ? ipl : IPR(ICU, GROUPBL1));
+            R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL1));
+        }
+        else
+        {
+            /* Check to make sure all interrupt sources are already disabled for this group. */
+            if (0 == ICU.GENBL1.LONG)
+            {
+                R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL1));
+
+                /* Casting is valid because it matches the type to the right side or argument. */
+                IPR(ICU, GROUPBL1) = 0;
+            }
+            else
+            {
+                err = BSP_INT_ERR_GROUP_STILL_ENABLED;
+            }
+        }
+#else /* BSP_MCU_GROUP_INTERRUPT_BL1 */
+        err = BSP_INT_ERR_INVALID_ARG;
+#endif /* BSP_MCU_GROUP_INTERRUPT_BL1 */
+    }
+    else if ((vector > BSP_INT_SRC_GR_INT_BL2_TOP) && (vector < BSP_INT_SRC_GR_INT_AL0_TOP))
+    {
+        /* Group BL2. */
+#ifdef BSP_MCU_GROUP_INTERRUPT_BL2
+        if (true == enable)
+        {
+            R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL2));
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IR(ICU, GROUPBL2)  = 0;
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IPR(ICU, GROUPBL2) = (uint8_t)((ipl > IPR(ICU, GROUPBL2)) ? ipl : IPR(ICU, GROUPBL2));
+            R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL2));
+        }
+        else
+        {
+            /* Check to make sure all interrupt sources are already disabled for this group. */
+            if (0 == ICU.GENBL2.LONG)
+            {
+                R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL2));
+
+                /* Casting is valid because it matches the type to the right side or argument. */
+                IPR(ICU, GROUPBL2) = 0;
+            }
+            else
+            {
+                err = BSP_INT_ERR_GROUP_STILL_ENABLED;
+            }
+        }
+#else /* BSP_MCU_GROUP_INTERRUPT_BL2 */
+        err = BSP_INT_ERR_INVALID_ARG;
+#endif /* BSP_MCU_GROUP_INTERRUPT_BL2 */
+    }
+    else if ((vector > BSP_INT_SRC_GR_INT_AL0_TOP) && (vector < BSP_INT_SRC_GR_INT_AL1_TOP))
+    {
+        /* Group AL0. */
+#ifdef BSP_MCU_GROUP_INTERRUPT_AL0
+        if (true == enable)
+        {
+            R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL0));
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IR(ICU, GROUPAL0)  = 0;
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IPR(ICU, GROUPAL0) = (uint8_t)((ipl > IPR(ICU, GROUPAL0)) ? ipl : IPR(ICU, GROUPAL0));
+            R_BSP_InterruptRequestEnable(VECT(ICU, GROUPAL0));
+        }
+        else
+        {
+            /* Check to make sure all interrupt sources are already disabled for this group. */
+            if (0 == ICU.GENAL0.LONG)
+            {
+                R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL0));
+
+                /* Casting is valid because it matches the type to the right side or argument. */
+                IPR(ICU, GROUPAL0) = 0;
+            }
+            else
+            {
+                err = BSP_INT_ERR_GROUP_STILL_ENABLED;
+            }
+        }
+#else /* BSP_MCU_GROUP_INTERRUPT_AL0 */
+        err = BSP_INT_ERR_INVALID_ARG;
+#endif /* BSP_MCU_GROUP_INTERRUPT_AL0 */
+    }
+    else if ((vector > BSP_INT_SRC_GR_INT_AL1_TOP) && (vector < BSP_INT_SRC_GR_INT_END))
+    {
+        /* Group AL1. */
+#ifdef BSP_MCU_GROUP_INTERRUPT_AL1
+        if (true == enable)
+        {
+            R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL1));
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IR(ICU, GROUPAL1)  = 0;
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            IPR(ICU, GROUPAL1) = (uint8_t)((ipl > IPR(ICU, GROUPAL1)) ? ipl : IPR(ICU, GROUPAL1));
+            R_BSP_InterruptRequestEnable(VECT(ICU, GROUPAL1));
+        }
+        else
+        {
+            /* Check to make sure all interrupt sources are already disabled for this group. */
+            if (0 == ICU.GENAL1.LONG)
+            {
+                R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL1));
+
+                /* Casting is valid because it matches the type to the right side or argument. */
+                IPR(ICU, GROUPAL1) = 0;
+            }
+            else
+            {
+                err = BSP_INT_ERR_GROUP_STILL_ENABLED;
+            }
+        }
+#else /* BSP_MCU_GROUP_INTERRUPT_AL1 */
+        err = BSP_INT_ERR_INVALID_ARG;
+#endif /* BSP_MCU_GROUP_INTERRUPT_AL1 */
+    }
+    else
+    {
+        /* Vector given was not part of a group. */
+        err = BSP_INT_ERR_INVALID_ARG;
+    }
+
+    return err;
+} /* End of function bsp_gr_int_enable_disable() */
+#endif /* BSP_MCU_GROUP_INTERRUPT */
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+
+#ifdef BSP_MCU_EXCEP_SUPERVISOR_INST_ISR
+/***********************************************************************************************************************
+* Function name: excep_supervisor_inst_isr
+* Description  : Supervisor Instruction Violation ISR
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_ATTRIB_INTERRUPT void excep_supervisor_inst_isr(void)
+{
+    /* If user has registered a callback for this exception then call it. */
+    R_BSP_InterruptControl(BSP_INT_SRC_EXC_SUPERVISOR_INSTR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+} /* End of function excep_supervisor_inst_isr() */
+#endif
+
+#ifdef BSP_MCU_EXCEP_ACCESS_ISR
+/***********************************************************************************************************************
+* Function name: excep_access_isr
+* Description  : Access exception ISR
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_ATTRIB_INTERRUPT void excep_access_isr(void)
+{
+    /* If user has registered a callback for this exception then call it. */
+    R_BSP_InterruptControl(BSP_INT_SRC_EXC_ACCESS, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+} /* End of function excep_access_isr() */
+#endif
+
+#ifdef BSP_MCU_EXCEP_UNDEFINED_INST_ISR
+/***********************************************************************************************************************
+* Function name: excep_undefined_inst_isr
+* Description  : Undefined instruction exception ISR
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_ATTRIB_INTERRUPT void excep_undefined_inst_isr(void)
+{
+    /* If user has registered a callback for this exception then call it. */
+    R_BSP_InterruptControl(BSP_INT_SRC_EXC_UNDEFINED_INSTR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+} /* End of function excep_undefined_inst_isr() */
+#endif
+
+#ifdef BSP_MCU_EXCEP_FLOATING_POINT_ISR
+/***********************************************************************************************************************
+* Function name: excep_floating_point_isr
+* Description  : Floating point exception ISR
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_ATTRIB_INTERRUPT void excep_floating_point_isr(void)
+{
+#ifdef __FPU
+    /* Used for reading FPSW register. */
+    uint32_t tmp_fpsw;
+#endif
+
+    /* If user has registered a callback for this exception then call it. */
+    R_BSP_InterruptControl(BSP_INT_SRC_EXC_FPU, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+#ifdef __FPU
+    /* Get current FPSW. */
+    tmp_fpsw = (uint32_t)R_BSP_GET_FPSW();
+
+    /* Clear only the FPU exception flags. */
+    R_BSP_SET_FPSW(tmp_fpsw & ((uint32_t)~BSP_PRV_FPU_CAUSE_FLAGS));
+#endif
+} /* End of function excep_floating_point_isr() */
+#endif
+
+#ifdef BSP_MCU_NON_MASKABLE_ISR
+/***********************************************************************************************************************
+* Function name: non_maskable_isr
+* Description  : Non-maskable interrupt ISR
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_ATTRIB_INTERRUPT void non_maskable_isr(void)
+{
+    /* Determine what is the cause of this interrupt. */
+
+#ifdef BSP_MCU_NMI_EXC_NMI_PIN
+    /* EXC_NMI_PIN */
+    if ((1 == ICU.NMISR.BIT.NMIST) && (1 == ICU.NMIER.BIT.NMIEN))
+    {
+        /* NMI pin interrupt is requested. */
+        R_BSP_InterruptControl(BSP_INT_SRC_EXC_NMI_PIN, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+        /* Clear NMI pin interrupt flag. */
+        ICU.NMICLR.BIT.NMICLR = 1;
+    }
+#endif
+
+#ifdef BSP_MCU_NMI_OSC_STOP_DETECT
+    /* OSC_STOP_DETECT */
+    if ((1 == ICU.NMISR.BIT.OSTST) && (1 == ICU.NMIER.BIT.OSTEN))
+    {
+        /* Oscillation stop detection interrupt is requested. */
+        R_BSP_InterruptControl(BSP_INT_SRC_OSC_STOP_DETECT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+        /* Clear oscillation stop detect flag. */
+        ICU.NMICLR.BIT.OSTCLR = 1;
+    }
+#endif
+
+#ifdef BSP_MCU_NMI_WDT_ERROR
+    /* WDT_ERROR */
+    if ((1 == ICU.NMISR.BIT.WDTST) && (1 == ICU.NMIER.BIT.WDTEN))
+    {
+        /* WDT underflow/refresh error interrupt is requested. */
+        R_BSP_InterruptControl(BSP_INT_SRC_WDT_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+        /* Clear WDT flag. */
+        ICU.NMICLR.BIT.WDTCLR = 1;
+    }
+#endif
+
+#ifdef BSP_MCU_NMI_LVD
+    /* LVD */
+    if ((1 == ICU.NMISR.BIT.LVDST) && (1 == ICU.NMIER.BIT.LVDEN))
+    {
+        /* Voltage monitoring 1 interrupt is requested. */
+        R_BSP_InterruptControl(BSP_INT_SRC_LVD1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+#endif
+
+#ifdef BSP_MCU_NMI_IWDT_ERROR
+    /* IWDT_ERROR */
+    if ((1 == ICU.NMISR.BIT.IWDTST) && (1 == ICU.NMIER.BIT.IWDTEN))
+    {
+        /* IWDT underflow/refresh error interrupt is requested. */
+        R_BSP_InterruptControl(BSP_INT_SRC_IWDT_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+        /* Clear IWDT flag. */
+        ICU.NMICLR.BIT.IWDTCLR = 1;
+    }
+#endif
+
+#ifdef BSP_MCU_NMI_LVD1
+    /* LVD1 */
+    if ((1 == ICU.NMISR.BIT.LVD1ST) && (1 == ICU.NMIER.BIT.LVD1EN))
+    {
+        /* Voltage monitoring 1 interrupt is requested. */
+        R_BSP_InterruptControl(BSP_INT_SRC_LVD1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+        /* Clear LVD1 flag. */
+        ICU.NMICLR.BIT.LVD1CLR = 1;
+    }
+#endif
+
+#ifdef BSP_MCU_NMI_LVD2
+    /* LVD2 */
+    if ((1 == ICU.NMISR.BIT.LVD2ST) && (1 == ICU.NMIER.BIT.LVD2EN))
+    {
+        /* Voltage monitoring 1 interrupt is requested. */
+        R_BSP_InterruptControl(BSP_INT_SRC_LVD2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+        /* Clear LVD2 flag. */
+        ICU.NMICLR.BIT.LVD2CLR = 1;
+    }
+#endif
+
+#ifdef BSP_MCU_NMI_VBATT
+    /* VBATT */
+    if ((1 == ICU.NMISR.BIT.VBATST) && (1 == ICU.NMIER.BIT.VBATEN))
+    {
+        /* VBATT monitoring interrupt is requested. */
+        R_BSP_InterruptControl(BSP_INT_SRC_VBATT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+        /* Clear LVD2 flag. */
+        ICU.NMICLR.BIT.VBATCLR = 1;
+    }
+#endif
+
+#ifdef BSP_MCU_NMI_ECCRAM
+    /* ECCRAM */
+    if ((1 == ICU.NMISR.BIT.ECCRAMST) && (1 == ICU.NMIER.BIT.ECCRAMEN))
+    {
+        if(1 == ECCRAM.ECCRAM1STS.BIT.ECC1ERR)
+        {
+            /* ECCRAM Error interrupt is requested. */
+            R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+            /* Clear ECCRAM flags. */
+            ECCRAM.ECCRAM1STS.BIT.ECC1ERR = 0;
+        }
+
+        if(1 == ECCRAM.ECCRAM2STS.BIT.ECC2ERR)
+        {
+            /* ECCRAM Error interrupt is requested. */
+            R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+            /* Clear ECCRAM flags. */
+            ECCRAM.ECCRAM2STS.BIT.ECC2ERR = 0;
+        }
+    }
+#endif
+
+#ifdef BSP_MCU_NMI_RAM
+    /* RAM */
+    if ((1 == ICU.NMISR.BIT.RAMST) && (1 == ICU.NMIER.BIT.RAMEN))
+    {
+        /* Casting is valid because it matches the type to the right side or argument. */
+        if(1 == RAM.RAMSTS.BIT.RAMERR)
+        {
+            /* RAM Error interrupt is requested. */
+            R_BSP_InterruptControl(BSP_INT_SRC_RAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+            /* Clear RAM flags. */
+            RAM.RAMSTS.BIT.RAMERR = 0;
+        }
+    #ifdef BSP_MCU_NMI_RAM_EXRAM
+
+        /* Casting is valid because it matches the type to the right side or argument. */
+        if(1 == RAM.EXRAMSTS.BIT.EXRAMERR)
+        {
+            /* Expansion RAM Error interrupt is requested. */
+            R_BSP_InterruptControl(BSP_INT_SRC_EXRAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+            /* Clear Expansion RAM flags. */
+            RAM.EXRAMSTS.BIT.EXRAMERR = 0;
+        }
+    #endif /* BSP_MCU_NMI_RAM_EXRAM */
+
+    #ifdef BSP_MCU_NMI_RAM_ECCRAM
+
+        /* Casting is valid because it matches the type to the right side or argument. */
+        if(1 == RAM.ECCRAM1STS.BIT.ECC1ERR)
+        {
+            /* ECCRAM Error interrupt is requested. */
+            R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+            /* Clear ECCRAM flags. */
+            RAM.ECCRAM1STS.BIT.ECC1ERR = 0;
+        }
+
+        /* Casting is valid because it matches the type to the right side or argument. */
+        if(1 == RAM.ECCRAM2STS.BIT.ECC2ERR)
+        {
+            /* ECCRAM Error interrupt is requested. */
+            R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+            /* Clear ECCRAM flags. */
+            RAM.ECCRAM2STS.BIT.ECC2ERR = 0;
+        }
+    #endif /* BSP_MCU_NMI_RAM_ECCRAM */
+    }
+#endif /* BSP_MCU_NMI_RAM */
+
+#ifdef BSP_MCU_NMI_EXNMI
+    /* EXNMI */
+    if ((1 == ICU.NMISR.BIT.EXNMIST) && (1 == ICU.NMIER.BIT.EXNMIEN))
+    {
+    #ifdef BSP_MCU_NMI_EXNMI_RAM
+
+        /* Casting is valid because it matches the type to the right side or argument. */
+        if ((1 == ICU.EXNMISR.BIT.RAMST) && (1 == ICU.EXNMIER.BIT.RAMEN))
+        {
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            if(1 == RAM.RAMSTS.BIT.RAMERR)
+            {
+                /* RAM Error interrupt is requested. */
+                R_BSP_InterruptControl(BSP_INT_SRC_RAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+                /* Clear RAM flags. */
+                RAM.RAMSTS.BIT.RAMERR = 0;
+            }
+        #ifdef BSP_MCU_NMI_EXNMI_RAM_EXRAM
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            if(1 == RAM.EXRAMSTS.BIT.EXRAMERR)
+            {
+                /* Expansion RAM Error interrupt is requested. */
+                R_BSP_InterruptControl(BSP_INT_SRC_EXRAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+                /* Clear Expansion RAM flags. */
+                RAM.EXRAMSTS.BIT.EXRAMERR = 0;
+            }
+        #endif /* BSP_MCU_NMI_EXNMI_RAM_EXRAM */
+
+        #ifdef BSP_MCU_NMI_EXNMI_RAM_ECCRAM
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            if(1 == ECCRAM.ECCRAM1STS.BIT.ECC1ERR)
+            {
+                /* ECCRAM Error interrupt is requested. */
+                R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+                /* Clear ECCRAM flags. */
+                ECCRAM.ECCRAM1STS.BIT.ECC1ERR = 0;
+            }
+
+            /* Casting is valid because it matches the type to the right side or argument. */
+            if(1 == ECCRAM.ECCRAM2STS.BIT.ECC2ERR)
+            {
+                /* ECCRAM Error interrupt is requested. */
+                R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+                /* Clear ECCRAM flags. */
+                ECCRAM.ECCRAM2STS.BIT.ECC2ERR = 0;
+            }
+        #endif /* BSP_MCU_NMI_EXNMI_RAM_ECCRAM */
+        }
+    #endif /* BSP_MCU_NMI_EXNMI_RAM */
+
+    #ifdef BSP_MCU_NMI_EXNMI_DPFPUEX
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    if ((1 == ICU.EXNMISR.BIT.DPFPUST) && (1 == ICU.EXNMIER.BIT.DPFPUEN))
+        {
+            /* Double-Precision Floating-Point Exception interrupt is requested. */
+            R_BSP_InterruptControl(BSP_INT_SRC_DPFPUEX, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+
+            /* Clear DPFPUST flag. */
+            ICU.EXNMICLR.BIT.DPFPUCLR = 1;
+        }
+    #endif /* BSP_MCU_NMI_EXNMI_DPFPUEX */
+    }
+#endif /* BSP_MCU_NMI_EXNMI */
+
+    /* WAIT_LOOP */
+    while(1)
+    {
+        /* Infinite loop. Return from Non-maskable interrupt handlling routine is prohibited.
+           Never use the non-maskable interrupt with an attempt to return to the program that was being executed at 
+           the time of interrupt generation after the exception handling routine is ended.
+         */
+         R_BSP_NOP();
+    }
+} /* End of function non_maskable_isr() */
+#endif /* BSP_MCU_NON_MASKABLE_ISR */
+
+#ifdef BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR
+/***********************************************************************************************************************
+* Function name: undefined_interrupt_source_isr
+* Description  : All undefined interrupt vectors point to this function.
+*                Set a breakpoint in this function to determine which source is creating unwanted interrupts.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_ATTRIB_INTERRUPT void undefined_interrupt_source_isr(void)
+{
+    /* If user has registered a callback for this exception then call it. */
+    R_BSP_InterruptControl(BSP_INT_SRC_UNDEFINED_INTERRUPT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+} /* End of function undefined_interrupt_source_isr() */
+#endif
+
+#ifdef BSP_MCU_BUS_ERROR_ISR
+/***********************************************************************************************************************
+* Function name: bus_error_isr
+* Description  : By default, this demo code enables the Bus Error Interrupt. This interrupt will fire if the user tries 
+*                to access code or data from one of the reserved areas in the memory map, including the areas covered 
+*                by disabled chip selects. A nop() statement is included here as a convenient place to set a breakpoint 
+*                during debugging and development, and further handling should be added by the user for their 
+*                application.
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+R_BSP_ATTRIB_INTERRUPT void bus_error_isr (void)
+{
+    /* Clear the bus error */
+    BSC.BERCLR.BIT.STSCLR = 1;
+
+    /* 
+        To find the address that was accessed when the bus error occurred, read the register BSC.BERSR2.WORD.
+        The upper 13 bits of this register contain the upper 13-bits of the offending address (in 512K byte units)
+    */
+
+    /* If user has registered a callback for this exception then call it. */
+    R_BSP_InterruptControl(BSP_INT_SRC_BUS_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+} /* End of function bus_error_isr() */
+#endif
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h
new file mode 100644
index 00000000..d6de101b
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h
@@ -0,0 +1,83 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_interrupts.h
+* Description  : This module allows for callbacks to be registered for certain interrupts. 
+*                And handle exception interrupts.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef INTERRUPTS_H
+#define INTERRUPTS_H
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+void R_BSP_InterruptRequestEnable(uint32_t vector);
+void R_BSP_InterruptRequestDisable(uint32_t vector);
+bsp_int_err_t R_BSP_InterruptWrite(bsp_int_src_t vector,  bsp_int_cb_t callback);
+bsp_int_err_t R_BSP_InterruptRead(bsp_int_src_t vector, bsp_int_cb_t * callback);
+bsp_int_err_t R_BSP_InterruptControl(bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata);
+
+void bsp_interrupt_open(void); //r_bsp internal function. DO NOT CALL.
+
+#ifdef BSP_MCU_EXCEP_SUPERVISOR_INST_ISR
+R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_supervisor_inst_isr)
+#endif
+#ifdef BSP_MCU_EXCEP_ACCESS_ISR
+R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_access_isr)
+#endif
+#ifdef BSP_MCU_EXCEP_UNDEFINED_INST_ISR
+R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_undefined_inst_isr)
+#endif
+#ifdef BSP_MCU_EXCEP_FLOATING_POINT_ISR
+R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_floating_point_isr)
+#endif
+#ifdef BSP_MCU_NON_MASKABLE_ISR
+R_BSP_PRAGMA_INTERRUPT_FUNCTION(non_maskable_isr)
+#endif
+#ifdef BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR
+R_BSP_PRAGMA_INTERRUPT_DEFAULT(undefined_interrupt_source_isr)
+#endif
+#ifdef BSP_MCU_BUS_ERROR_ISR
+R_BSP_PRAGMA_INTERRUPT(bus_error_isr, VECT(BSC,BUSERR))
+#endif
+
+#endif  /* End of multiple inclusion prevention macro */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c
new file mode 100644
index 00000000..6170397d
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c
@@ -0,0 +1,187 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_locking.c
+* Description  : This implements a locking mechanism that can be used by all code. The locking is done atomically so
+*                common resources can be accessed safely.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 2.00     Merged processing of all devices.
+*                               Added support for GNUC and ICCRX.
+*                               Fixed coding style.
+*         : 26.07.2019 2.01     Modified comment of API function to Doxygen style.
+*         : 10.12.2019 2.02     Modified comment.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Platform configuration. */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+ 
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_SoftwareLock
+ ******************************************************************************************************************//**
+ * @brief Attempts to reserve a lock.
+ * @param[out] plock Pointer to lock structure with lock to try and acquire.
+ * @retval true Successful, lock was available and acquired.
+ * @retval false Failure, lock was already acquired and is not available.
+ * @details This function implements an atomic locking mechanism. Locks can be used in numerous ways. Two common uses 
+ * of locks are to protect critical sections of code and to protect against duplicate resource allocation.
+ * For protecting critical sections of code the user would require that the code first obtain the critical section's 
+ * lock before executing. An example of protecting against duplicate resource allocation would be if the user had two 
+ * FIT modules that used the same peripheral. For example, the user may have one FIT module that uses the SCI 
+ * peripheral in UART mode and another FIT module that uses the SCI peripheral in I2C mode. To make sure that both 
+ * modules cannot use the same SCI channel, locks can be used.
+ * Care should be taken when using locks as they do not provide advanced features one might expect from an RTOS
+ * semaphore or mutex. If used improperly locks can lead to deadlock in the user's system.
+ * Users can override the default locking mechanisms.
+ */
+bool R_BSP_SoftwareLock (BSP_CFG_USER_LOCKING_TYPE * const plock)
+{
+#if BSP_CFG_USER_LOCKING_ENABLED == 0
+    bool ret = false;
+
+    /* Variable used in trying to acquire lock. Using the xchg instruction makes this atomic */
+    int32_t is_locked = true;
+    
+    /* This example uses the RX MCU's atomic xchg() instruction. plock->lock is the lock we are trying to reserve. 
+       The way this works is that 'is_locked' gets the value of the plock->lock and plock->lock gets the value of 
+       'is_locked' which we just set to 'true'. Basically this is an atomic 'swap' command. If the lock had not yet been
+       reserved then its value would be 'false' and after the xchg() instruction finished 'is_locked' would have 
+       'false'. If it had already been reserved then 'is_locked' would have 'true' after the xchg() instruction. Since 
+       plock->lock was already 'true' and we just set it back to 'true' everything is ok. To see if we reserved the lock
+       we just need to check the value of 'is_locked' after this instruction finishes. */
+
+    /* Try to acquire semaphore to obtain lock */
+    R_BSP_EXCHANGE(&is_locked, &plock->lock);
+    
+    /* Check to see if semaphore was successfully taken */
+    if (false == is_locked)
+    {        
+        /* Lock obtained, return success. */
+        ret = true;
+    }
+    else
+    {
+        /* Lock was not obtained, another task already has it. */
+        R_BSP_NOP();
+    }
+
+    return ret;
+#else
+    /* User is going to handle the locking themselves. */
+    return BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(plock);
+#endif
+} /* End of function R_BSP_SoftwareLock() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_SoftwareUnlock
+ ******************************************************************************************************************//**
+ * @brief Releases a lock.
+ * @param[out] plock Pointer to lock structure with lock to release.
+ * @retval true Successful, lock was released. Or the lock has been already released.
+ * @retval false Failure, lock could not be released.
+ * @details This function releases a lock that was previously acquired using the R_BSP_SoftwareLock() function.
+ */
+bool R_BSP_SoftwareUnlock (BSP_CFG_USER_LOCKING_TYPE * const plock)
+{
+#if BSP_CFG_USER_LOCKING_ENABLED == 0
+    /* Set lock back to unlocked. */
+    plock->lock = false;
+
+    return true;
+#else
+    /* User is going to handle the locking themselves. */
+    return BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(plock);
+#endif
+} /* End of function R_BSP_SoftwareUnlock() */
+
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_HardwareLock
+ ******************************************************************************************************************//**
+ * @brief Attempts to reserve a hardware peripheral lock.
+ * @param[in] hw_index Index of lock to acquire from the hardware lock array.
+ * @retval true Successful, lock was available and acquired.
+ * @retval false Failure, lock was already acquired and is not available.
+ * @details This function attempts to acquire the lock for a hardware resource of the MCU. Instead of sending in a 
+ * pointer to a lock as with the R_BSP_SoftwareLock() function, the user sends in an index to an array that holds 1 
+ * lock per MCU hardware resource. This array is shared amongst all FIT modules and user code therefore allowing 
+ * multiple FIT modules (and user code) to use the same locks. The user can see the available hardware resources by 
+ * looking at the mcu_lock_t enum in mcu_locks.h. These enum values are also the index into the hardware lock array.
+ * The same atomic locking mechanisms from the R_BSP_SoftwareLock() function are used with this function as well.
+ * @note Each entry in the mcu_lock_t enum in mcu_locks.h will be allocated a lock. On RX MCUs, each lock is required 
+ * to be 4-bytes. If RAM space is an issue then the user can remove the entries from the mcu_lock_t enum they are not 
+ * using. For example, if the user is not using the CRC peripheral then they could delete the BSP_LOCK_CRC entry. The 
+ * user will save 4-bytes per deleted entry.
+ */
+bool R_BSP_HardwareLock (mcu_lock_t const hw_index)
+{
+#if BSP_CFG_USER_LOCKING_ENABLED == 0
+    /* Pass actual lock to software lock function. */
+    return R_BSP_SoftwareLock(&g_bsp_Locks[hw_index]);
+#else
+    /* User is going to handle the locking themselves. */
+    return BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(hw_index);
+#endif
+} /* End of function R_BSP_HardwareLock() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_HardwareUnlock
+ ******************************************************************************************************************//**
+ * @brief Releases a hardware peripheral lock.
+ * @param[in] hw_index Index of lock to release from the hardware lock array.
+ * @retval true Successful, lock was released.
+ * @retval false Failure, lock could not be released.
+ * @details This function attempts to release the lock for a hardware resource of the MCU that was previously acquired 
+ * using the R_BSP_HardwareLock() function.
+ * @note Each entry in the mcu_lock_t enum in mcu_locks.h will be allocated a lock. On RX MCUs, each lock is required 
+ * to be 4-bytes. If RAM space is an issue then the user can remove the entries from the mcu_lock_t enum that they are 
+ * not using. For example, if the user is not using the CRC peripheral then they could delete the BSP_LOCK_CRC entry. 
+ * The user will save 4-bytes per deleted entry.
+ */
+bool R_BSP_HardwareUnlock (mcu_lock_t const hw_index)
+{
+#if BSP_CFG_USER_LOCKING_ENABLED == 0
+    /* Pass actual lock to software unlock function. */
+    return R_BSP_SoftwareUnlock(&g_bsp_Locks[hw_index]);
+#else
+    /* User is going to handle the locking themselves. */
+    return BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(hw_index);
+#endif
+} /* End of function R_BSP_HardwareUnlock() */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c
new file mode 100644
index 00000000..69a22da8
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c
@@ -0,0 +1,93 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_mcu_startup.c
+* Description  : This module implements user startup specific functions.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 2.00     Merged processing of all devices.
+*                               Fixed coding style.
+*         : 26.07.2019 2.01     Modified comment of API function to Doxygen style.
+*                               Added Initialization the trigonometric function unit in R_BSP_StartupOpen function.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Platform support. */
+#include "platform.h"
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE != 0
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Error checking
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_StartupOpen
+ ******************************************************************************************************************//**
+ * @brief Specifies settings to use the BSP and peripheral FIT modules. Call this function only when the BSP startup 
+ * is disabled.
+ * @details This function performs initialization for the interrupt callback, register protection, and the hardware 
+ * and pins. These processing are needed for using the BSP and peripheral FIT modules. Thus, this function must be 
+ * called in the beginning of the main function. Call this function only when the BSP startup is disabled.
+ * @note The R_BSP_StartupOpen function performs a part of processing in the startup function.
+ * See Section 5.18 in the application note for more information.
+ */
+void R_BSP_StartupOpen (void)
+{
+    /* Initializes the trigonometric function unit. */
+#ifdef BSP_MCU_TRIGONOMETRIC
+#ifdef __TFU
+    R_BSP_INIT_TFU();
+#endif
+#endif
+    /* Initialize RAM. */
+    bsp_ram_initialize();
+
+    /* Initialize MCU interrupt callbacks. */
+    bsp_interrupt_open();
+
+    /* Initialize register protection functionality. */
+    bsp_register_protect_open();
+
+    /* Configure the MCU and board hardware */
+    hardware_setup();
+} /* End of function R_BSP_StartupOpen() */
+
+#endif /* BSP_CFG_STARTUP_DISABLE != 0 */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h
new file mode 100644
index 00000000..50a8304d
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_mcu_startup.h
+* Description  : This module implements user startup specific functions.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 2.00     Merged processing of all devices.
+*                               Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef MCU_STARTUP_H
+#define MCU_STARTUP_H
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+void R_BSP_StartupOpen(void);
+
+#endif  /* End of multiple inclusion prevention macro */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c
new file mode 100644
index 00000000..203210da
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c
@@ -0,0 +1,1053 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_software_interrupt.c
+* Description  : This module implements software interrupt specific functions.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 08.10.2019 1.00     First Release
+*         : 10.12.2019 1.01     Modified comment.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define BSP_PRV_SWINT_TASK_BUFFER_MAX               (BSP_CFG_SWINT_TASK_BUFFER_NUMBER + 1)
+#define BSP_PRV_SWINT_ACCESS_ACCEPTATION            (1)
+#define BSP_PRV_SWINT_ACCESS_REJECTION              (0)
+#define BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT       (1)
+#define BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT      (0)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) || \
+    (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+
+st_bsp_swint_access_control_t g_bsp_swint_access_ctrl[BSP_SWINT_UNIT_MAX];
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* Interrupt functions */
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+R_BSP_PRAGMA_STATIC_INTERRUPT(bsp_swint_isr, VECT(ICU, SWINT))
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+R_BSP_PRAGMA_STATIC_INTERRUPT(bsp_swint2_isr, VECT(ICU, SWINT2))
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+
+/* Functions */
+static void bsp_swint_get_interrupt_information(e_bsp_swint_unit_t unit,  void * const p_args);
+static void bsp_swint_enable_interrupt(e_bsp_swint_unit_t unit);
+static void bsp_swint_disable_interrupt(e_bsp_swint_unit_t unit);
+static e_bsp_swint_err_t bsp_swint_set_interrupt_priority(e_bsp_swint_unit_t unit,  void * const p_args);
+static void bsp_swint_set_interrupt_request(e_bsp_swint_unit_t unit);
+static void bsp_swint_clear_interrupt_request(e_bsp_swint_unit_t unit);
+static void bsp_swint_enable_nested_interrupt(e_bsp_swint_unit_t unit);
+static void bsp_swint_disable_nested_interrupt(e_bsp_swint_unit_t unit);
+static e_bsp_swint_err_t bsp_swint_clear_task(e_bsp_swint_unit_t unit, void * const p_args);
+static e_bsp_swint_err_t bsp_swint_clear_all_task(e_bsp_swint_unit_t unit);
+static void bsp_swint_get_all_task_status(e_bsp_swint_unit_t unit, void * const p_args);
+static bool bsp_swint_get_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args);
+static bool bsp_swint_release_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args);
+static void bsp_swint_execute_task(e_bsp_swint_unit_t unit);
+static void bsp_swint_dummy_task(void * p_dummy_context);
+
+/* Variables */
+static st_bsp_swint_task_t s_bsp_swint_task[BSP_SWINT_UNIT_MAX][BSP_PRV_SWINT_TASK_BUFFER_MAX];
+static uint8_t s_bsp_swint_buf_used[BSP_SWINT_UNIT_MAX];
+static uint8_t s_bsp_swint_buf_top[BSP_SWINT_UNIT_MAX];
+static uint8_t s_bsp_swint_buf_bottom[BSP_SWINT_UNIT_MAX];
+static uint8_t s_bsp_swint_nested_int_status[BSP_SWINT_UNIT_MAX];
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_SoftwareInterruptOpen
+ ******************************************************************************************************************//**
+ * @brief This function initializes software interrupts.
+ * @param[in] unit Software interrupt unit
+ * @retval BSP_SWINT_SUCCESS Success.
+ * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified.
+ * @retval BSP_SWINT_ERR_ALREADY_OPEN Failed to lock hardware.
+ * @details This function locks the hardware, resets the access control status, clears the interrupt request (IR),
+ * initializes the interrupt priority level (IPR), enables nested-interrupt status, initializes the task buffer, and 
+ * enables interrupts (IEN).
+ * @note This function is available only when use of software interrupts is enabled in a configuration macro.
+ * This function is called automatically at BSP startup when the value of BSP_CFG_SWINT_UNITn_ENABLE in r_bsp_config.h 
+ * is 1.
+ */
+e_bsp_swint_err_t R_BSP_SoftwareInterruptOpen(e_bsp_swint_unit_t unit)
+{
+    bool lock_ret;
+    e_bsp_swint_err_t swint_ret;
+    uint8_t buf_num;
+    uint8_t swint_ipr;
+
+    swint_ret = BSP_SWINT_SUCCESS;
+
+    switch (unit)
+    {
+        /* Hardware Lock */
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+        case BSP_SWINT_UNIT1:
+            lock_ret = R_BSP_HardwareLock(BSP_LOCK_SWINT);
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+        case BSP_SWINT_UNIT2:
+            lock_ret = R_BSP_HardwareLock(BSP_LOCK_SWINT2);
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+
+        default:
+            swint_ret = BSP_SWINT_ERR_INVALID_UNIT;
+            break;
+    }
+
+    if (BSP_SWINT_SUCCESS == swint_ret)
+    {
+        if (true == lock_ret)
+        {
+            /* Reset Access Control Status */
+            g_bsp_swint_access_ctrl[unit].status = BSP_PRV_SWINT_ACCESS_ACCEPTATION;
+
+            /* Disable Interrupt(IEN) */
+            R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_DISABLE_INTERRUPT, FIT_NO_PTR);
+
+            /* Clear Interrupt Request(IR) */
+            R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, FIT_NO_PTR);
+
+            /* Set Interrupt Priority(IPR) */
+            swint_ipr = BSP_CFG_SWINT_IPR_INITIAL_VALUE;
+            R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY, &swint_ipr);
+
+            /* Set Multiple Interrupt Status */
+            s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT;
+
+            /* Clear Task Buffer */
+            for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++)
+            {
+                s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST;
+                s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task;
+                s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR;
+            }
+
+            /* Reset Task Buffer Position */
+            s_bsp_swint_buf_top[unit] = 0;
+            s_bsp_swint_buf_bottom[unit] = 0;
+            s_bsp_swint_buf_used[unit] = 0;
+
+            /* Enable Interrupt(IEN) */
+            R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_ENABLE_INTERRUPT, FIT_NO_PTR);
+        }
+        else
+        {
+            swint_ret = BSP_SWINT_ERR_ALREADY_OPEN;
+        }
+    }
+
+    return swint_ret;
+} /* End of function R_BSP_SoftwareInterruptOpen() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_SoftwareInterruptClose
+ ******************************************************************************************************************//**
+ * @brief This function terminates software interrupts.
+ * @param[in] unit Software interrupt unit
+ * @retval BSP_SWINT_SUCCESS Success.
+ * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified.
+ * @retval BSP_SWINT_ERR_ALREADY_OPEN Failed to lock hardware.
+ * @details This function unlocks the hardware, disables interrupts (IEN), clears the interrupt request (IR), 
+ * initializes the task buffer, and disables nested-interrupt status.
+ * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this 
+ * function after the R_BSP_SoftwareInterruptOpen function has run.\n
+ * If the R_BSP_SoftwareInterruptSetTask function or software interrupt function (bsp_swint_execute_task) is acquiring 
+ * acces control rights and an interrupt is generated and this function is called within the interrupt, the task 
+ * buffer may not be controlled correctly. If this function is used in an interrupt, clear the all task by the 
+ * R_BSP_SoftwareInterruptControl function with the BSP_SWINT_CMD_CLEAR_ALL_TASK command before call this function.
+ */
+e_bsp_swint_err_t R_BSP_SoftwareInterruptClose(e_bsp_swint_unit_t unit)
+{
+    bool lock_ret;
+    e_bsp_swint_err_t swint_ret;
+    uint8_t buf_num;
+
+    /* Check Unit */
+    if (BSP_SWINT_UNIT_MAX > unit)
+    {
+        /* Disable Interrupt(IEN) */
+        R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_DISABLE_INTERRUPT, FIT_NO_PTR);
+
+        /* Clear Interrupt Request(IR) */
+        R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, FIT_NO_PTR);
+
+        /* Clear Task Buffer */
+        for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++)
+        {
+            s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST;
+            s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task;
+            s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR;
+        }
+
+        /* Reset Task Buffer Position */
+        s_bsp_swint_buf_top[unit] = 0;
+        s_bsp_swint_buf_bottom[unit] = 0;
+        s_bsp_swint_buf_used[unit] = 0;
+
+        /* Clear Multiple Interrupt Status */
+        s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT;
+
+        switch (unit)
+        {
+            /* Hardware Lock */
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+            case BSP_SWINT_UNIT1:
+                lock_ret = R_BSP_HardwareUnlock(BSP_LOCK_SWINT);
+                break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+            case BSP_SWINT_UNIT2:
+                lock_ret = R_BSP_HardwareUnlock(BSP_LOCK_SWINT2);
+                break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+
+            default:
+
+                /* Do nothing. */
+                break;
+        }
+
+        if (true == lock_ret)
+        {
+            swint_ret = BSP_SWINT_SUCCESS;
+        }
+        else
+        {
+            swint_ret = BSP_SWINT_ERR_NOT_CLOSED;
+        }
+    }
+    else
+    {
+        swint_ret = BSP_SWINT_ERR_INVALID_UNIT;
+    }
+
+    return swint_ret;
+} /* End of function R_BSP_SoftwareInterruptClose() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_SoftwareInterruptSetTask
+ ******************************************************************************************************************//**
+ * @brief This function sets a task in the software interrupt task buffer.
+ * @param[in] unit Software interrupt unit
+ * @param[in] set_task Software interrupt task
+ * @retval BSP_SWINT_SUCCESS Success.
+ * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified.
+ * @retval BSP_SWINT_ERR_INVALID_TASK Invalid task pointer specified.
+ * @retval BSP_SWINT_ERR_FULL_BUFFER Task buffer full.
+ * @retval BSP_SWINT_ERR_ACCESS_REJECTION Failed to obtain access control right.
+ * @details This function sets the task specified by an argument in the software interrupt task buffer. After setting 
+ * the task, the software interrupt occurs. If the task buffer is full, the task is not set.
+ * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this 
+ * function after the R_BSP_SoftwareInterruptOpen function has run.\n
+ * If the access control right cannot be obtained, provide a wait period and then call this function again. It is not 
+ * possible to obtain the access control right during interrupt processing if the interrupt is generated in a state 
+ * where other processing has the access control right. For this reason a deadlock will occur if polling is used in 
+ * the interrupt processing to obtain the access control right.
+ */
+e_bsp_swint_err_t R_BSP_SoftwareInterruptSetTask(e_bsp_swint_unit_t unit, st_bsp_swint_task_t set_task)
+{
+    e_bsp_swint_err_t ret;
+    st_bsp_swint_access_control_t access_control;
+
+    /* Check Unit */
+    if (BSP_SWINT_UNIT_MAX > unit)
+    {
+        /* Get Access Control */
+        access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION;
+        if (true == bsp_swint_get_access_control(unit, &access_control))
+        {
+            /* Casting is valid because it matches the type to the right side or argument. */
+            if (((uint32_t)FIT_NO_FUNC == (uint32_t)set_task.p_taskAddr) || ((uint32_t)NULL == (uint32_t)set_task.p_taskAddr))
+            {
+                ret = BSP_SWINT_ERR_INVALID_TASK;
+            }
+            else if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_used[unit])
+            {
+                ret = BSP_SWINT_ERR_FULL_BUFFER;
+            }
+            else
+            {
+                if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_top[unit])
+                {
+                    s_bsp_swint_buf_top[unit] = 0;
+                }
+                else
+                {
+                    s_bsp_swint_buf_top[unit]++;
+                }
+
+                s_bsp_swint_buf_used[unit]++;
+
+                /* Set Task Buffer */
+                s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].status = BSP_SWINT_TASK_STATUS_REQUESTED;
+                s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].p_taskAddr = set_task.p_taskAddr;
+                s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].p_context = set_task.p_context;
+
+                ret = BSP_SWINT_SUCCESS;
+            }
+
+            /* Release Access Control */
+            bsp_swint_release_access_control(unit, &access_control);
+
+            /* Set Interrupt Request(IR) */
+            R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR);
+        }
+        else
+        {
+            ret = BSP_SWINT_ERR_ACCESS_REJECTION;
+        }
+    }
+    else
+    {
+        ret = BSP_SWINT_ERR_INVALID_UNIT;
+    }
+
+    return ret;
+} /* End of function R_BSP_SoftwareInterruptSetTask() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_get_interrupt_information
+* Description  : Get the software interrupt information.
+* Arguments    : unit - Unit number of software interrupt.
+*                p_args - Pointer of setting parameter.
+* Return Value : None.
+***********************************************************************************************************************/
+static void bsp_swint_get_interrupt_information(e_bsp_swint_unit_t unit,  void * const p_args)
+{
+    st_bsp_swint_int_info_t *p_swint_int_info;
+
+    /* Casting is valid because it matches the type of the void type argument to the left. */
+    p_swint_int_info = (st_bsp_swint_int_info_t *)p_args;
+
+    switch (unit)
+    {
+        /* Get Interrupt Information */
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+        case BSP_SWINT_UNIT1:
+            p_swint_int_info->ipr = IPR(ICU, SWINT);
+            p_swint_int_info->ien = IEN(ICU, SWINT);
+            p_swint_int_info->ir = IR(ICU, SWINT);
+            p_swint_int_info->nested_int = s_bsp_swint_nested_int_status[unit];
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+        case BSP_SWINT_UNIT2:
+            p_swint_int_info->ipr = IPR(ICU, SWINT2);
+            p_swint_int_info->ien = IEN(ICU, SWINT2);
+            p_swint_int_info->ir = IR(ICU, SWINT2);
+            p_swint_int_info->nested_int = s_bsp_swint_nested_int_status[unit];
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+
+        default:
+
+            /* Do nothing. */
+            break;
+    }
+} /* End of function bsp_swint_get_interrupt_information() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_enable_interrupt
+* Description  : Enable interrupt. (Set the IEN bit.)
+* Arguments    : unit - Unit number of software interrupt.
+* Return Value : None.
+***********************************************************************************************************************/
+static void bsp_swint_enable_interrupt(e_bsp_swint_unit_t unit)
+{
+    switch (unit)
+    {
+        /* Enable Interrupt */
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+        case BSP_SWINT_UNIT1:
+            R_BSP_InterruptRequestEnable(VECT(ICU, SWINT));
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+        case BSP_SWINT_UNIT2:
+            R_BSP_InterruptRequestEnable(VECT(ICU, SWINT2));
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+
+        default:
+
+            /* Do nothing. */
+            break;
+    }
+} /* End of function bsp_swint_enable_interrupt() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_disable_interrupt
+* Description  : Disable interrupt. (Clear the IEN bit.)
+* Arguments    : unit - Unit number of software interrupt.
+* Return Value : None.
+***********************************************************************************************************************/
+static void bsp_swint_disable_interrupt(e_bsp_swint_unit_t unit)
+{
+    switch (unit)
+    {
+        /* Disable Interrupt */
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+        case BSP_SWINT_UNIT1:
+            R_BSP_InterruptRequestDisable(VECT(ICU, SWINT));
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+        case BSP_SWINT_UNIT2:
+            R_BSP_InterruptRequestDisable(VECT(ICU, SWINT2));
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+
+        default:
+
+            /* Do nothing. */
+            break;
+    }
+} /* End of function bsp_swint_disable_interrupt() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_set_interrupt_priority
+* Description  : Set interrupt priority. (Set the IPR register.)
+* Arguments    : unit - Unit number of software interrupt.
+*                p_args - Pointer of setting parameter.
+* Return Value : BSP_SWINT_SUCCESS - Operation successful.
+*                BSP_SWINT_ERR_INVALID_IPR - Overflow interrupt priority.
+***********************************************************************************************************************/
+static e_bsp_swint_err_t bsp_swint_set_interrupt_priority(e_bsp_swint_unit_t unit,  void * const p_args)
+{
+    e_bsp_swint_err_t ret;
+    uint8_t *p_swint_ipr;
+    uint8_t ien;
+    bsp_int_ctrl_t int_ctrl;
+
+    /* Casting is valid because it matches the type of the void type argument to the left. */
+    p_swint_ipr = (uint8_t *)p_args;
+
+    /* Check Interrupt Priority */
+    if (BSP_MCU_IPL_MAX < (*p_swint_ipr))
+    {
+        ret = BSP_SWINT_ERR_INVALID_IPR;
+    }
+    else
+    {
+        /* Set IPL to the maximum value to disable all interrupts*/
+        R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl);
+
+        switch (unit)
+        {
+            /* Set Interrupt Priority */
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+            case BSP_SWINT_UNIT1:
+                ien = IEN(ICU, SWINT);
+                R_BSP_InterruptRequestDisable(VECT(ICU, SWINT));
+
+                /* Casting is valid because it matches the type to the left side. */
+                IPR(ICU, SWINT) = (uint8_t)*p_swint_ipr;
+
+                if (1 == ien)
+                {
+                    R_BSP_InterruptRequestEnable(VECT(ICU, SWINT));
+                }
+                break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+            case BSP_SWINT_UNIT2:
+                ien = IEN(ICU, SWINT2);
+                R_BSP_InterruptRequestDisable(VECT(ICU, SWINT2));
+
+                /* Casting is valid because it matches the type to the left side. */
+                IPR(ICU, SWINT2) = (uint8_t)*p_swint_ipr;
+
+                if (1 == ien)
+                {
+                    R_BSP_InterruptRequestEnable(VECT(ICU, SWINT2));
+                }
+                break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+
+            default:
+
+                /* Do nothing. */
+                break;
+        }
+
+        /* Restore the IPL */
+        R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl);
+
+        ret = BSP_SWINT_SUCCESS;
+    }
+
+    return ret;
+} /* End of function bsp_swint_set_interrupt_priority() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_set_interrupt_request
+* Description  : Set interrupt request. (Set the SWINTR register.)
+* Arguments    : unit - Unit number of software interrupt.
+* Return Value : None.
+***********************************************************************************************************************/
+static void bsp_swint_set_interrupt_request(e_bsp_swint_unit_t unit)
+{
+    switch (unit)
+    {
+        /* Set Interrupt Request */
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+        case BSP_SWINT_UNIT1:
+            ICU.SWINTR.BIT.SWINT = 1;
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+        case BSP_SWINT_UNIT2:
+            ICU.SWINT2R.BIT.SWINT2 = 1;
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+
+        default:
+
+            /* Do nothing. */
+            break;
+    }
+} /* End of function bsp_swint_set_interrupt_request() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_clear_interrupt_request
+* Description  : Clear interrupt request. (Clear the IR bit.)
+* Arguments    : unit - Unit number of software interrupt.
+* Return Value : None.
+***********************************************************************************************************************/
+static void bsp_swint_clear_interrupt_request(e_bsp_swint_unit_t unit)
+{
+    switch (unit)
+    {
+        /* Clear Interrupt Request */
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+        case BSP_SWINT_UNIT1:
+            IR(ICU, SWINT) = 0;
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+        case BSP_SWINT_UNIT2:
+            IR(ICU, SWINT2) = 0;
+            break;
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+
+        default:
+
+            /* Do nothing. */
+            break;
+    }
+} /* End of function bsp_swint_clear_interrupt_request() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_enable_nested_interrupt
+* Description  : Set nested interrupt status.
+* Arguments    : unit - Unit number of software interrupt.
+* Return Value : None.
+***********************************************************************************************************************/
+static void bsp_swint_enable_nested_interrupt(e_bsp_swint_unit_t unit)
+{
+    /* Set Multiple Interrupt Status */
+    s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT;
+} /* End of function bsp_swint_enable_nested_interrupt() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_disable_nested_interrupt
+* Description  : Clear nested interrupt status.
+* Arguments    : unit - Unit number of software interrupt.
+* Return Value : None.
+***********************************************************************************************************************/
+static void bsp_swint_disable_nested_interrupt(e_bsp_swint_unit_t unit)
+{
+    /* Clear Multiple Interrupt Status */
+    s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT;
+} /* End of function bsp_swint_disable_nested_interrupt() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_clear_task
+* Description  : Clear the task of software interrupt in the buffer.
+* Arguments    : unit - Unit number of software interrupt.
+*                p_args - Pointer of setting parameter.
+* Return Value : BSP_SWINT_SUCCESS - Operation successful.
+*                BSP_SWINT_ERR_ACCESS_REJECTION - Failed to get access.
+*                BSP_SWINT_ERR_TASK_EXECUTING - Accessed during task execution.
+*                BSP_SWINT_ERR_INVALID_BUFFER_NUMBER - Set invalid buffer number.
+***********************************************************************************************************************/
+static e_bsp_swint_err_t bsp_swint_clear_task(e_bsp_swint_unit_t unit, void * const p_args)
+{
+    e_bsp_swint_err_t ret;
+    st_bsp_swint_task_buffer_t *p_swint_task_buffer;
+    st_bsp_swint_access_control_t access_control;
+
+    /* Get Access Control */
+    access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION;
+    if (true == bsp_swint_get_access_control(unit, &access_control))
+    {
+        /* Casting is valid because it matches the type of the void type argument to the left. */
+        p_swint_task_buffer = (st_bsp_swint_task_buffer_t *)p_args;
+
+        if (BSP_PRV_SWINT_TASK_BUFFER_MAX > p_swint_task_buffer->number)
+        {
+            /* Clear Task Buffer */
+            if (BSP_SWINT_TASK_STATUS_EXECUTING != s_bsp_swint_task[unit][p_swint_task_buffer->number].status)
+            {
+                s_bsp_swint_task[unit][p_swint_task_buffer->number].status = BSP_SWINT_TASK_STATUS_NO_REQUEST;
+                s_bsp_swint_task[unit][p_swint_task_buffer->number].p_taskAddr = bsp_swint_dummy_task;
+                s_bsp_swint_task[unit][p_swint_task_buffer->number].p_context = FIT_NO_PTR;
+                ret = BSP_SWINT_SUCCESS;
+            }
+            else
+            {
+                ret = BSP_SWINT_ERR_TASK_EXECUTING;
+            }
+        }
+        else
+        {
+            ret = BSP_SWINT_ERR_INVALID_BUFFER_NUMBER;
+        }
+
+        /* Release Access Control */
+        bsp_swint_release_access_control(unit, &access_control);
+
+        /* Set Interrupt Request(IR)
+         * If a software interrupt is generated while this function has the access control right, the software 
+         * interrupt cannot obtain the access control right and interrupt processing ends with the task remaining 
+         * unexecuted. For this reason, after returning from a software interrupt the interrupt request is cleared 
+         * regardless of whether a task has been set in the task buffer. To avoid it, setting of the interrupt 
+         * request occurs in this timing.
+         */
+        R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR);
+    }
+    else
+    {
+        ret = BSP_SWINT_ERR_ACCESS_REJECTION;
+    }
+
+    return ret;
+} /* End of function bsp_swint_clear_task() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_clear_all_task
+* Description  : Clear the  all task of software interrupt in the buffer.
+* Arguments    : unit - Unit number of software interrupt.
+* Return Value : BSP_SWINT_SUCCESS - Operation successful.
+*                BSP_SWINT_ERR_ACCESS_REJECTION - Failed to get access.
+*                BSP_SWINT_ERR_TASK_EXECUTING - Accessed during task execution.
+***********************************************************************************************************************/
+static e_bsp_swint_err_t bsp_swint_clear_all_task(e_bsp_swint_unit_t unit)
+{
+    e_bsp_swint_err_t ret;
+    uint8_t buf_num;
+    st_bsp_swint_access_control_t access_control;
+
+    /* Get Access Control */
+    access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION;
+    if (true == bsp_swint_get_access_control(unit, &access_control))
+    {
+        ret = BSP_SWINT_SUCCESS;
+
+        /* Check Task Status */
+        for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++)
+        {
+            if (BSP_SWINT_TASK_STATUS_EXECUTING == s_bsp_swint_task[unit][buf_num].status)
+            {
+                ret = BSP_SWINT_ERR_TASK_EXECUTING;
+                break;
+            }
+        }
+
+        if (BSP_SWINT_SUCCESS == ret)
+        {
+            /* Clear ALL Task Buffer */
+            for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++)
+            {
+                s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST;
+                s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task;
+                s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR;
+            }
+
+            /* Reset Task Buffer Position */
+            s_bsp_swint_buf_top[unit] = 0;
+            s_bsp_swint_buf_bottom[unit] = 0;
+            s_bsp_swint_buf_used[unit] = 0;
+
+            /* Release Access Control */
+            bsp_swint_release_access_control(unit, &access_control);
+        }
+        else
+        {
+            /* Release Access Control */
+            bsp_swint_release_access_control(unit, &access_control);
+
+            /* Set Interrupt Request(IR)
+             * If a software interrupt is generated while this function has the access control right, the software 
+             * interrupt cannot obtain the access control right and interrupt processing ends with the task remaining 
+             * unexecuted. For this reason, after returning from a software interrupt the interrupt request is cleared 
+             * regardless of whether a task has been set in the task buffer. To avoid it, setting of the interrupt 
+             * request occurs in this timing.
+             */
+            R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR);
+        }
+    }
+    else
+    {
+        ret = BSP_SWINT_ERR_ACCESS_REJECTION;
+    }
+
+    return ret;
+} /* End of function bsp_swint_clear_all_task() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_get_all_task_status
+* Description  : Get the task status of software interrupt.
+* Arguments    : unit - Unit number of software interrupt.
+*                p_args - Pointer of setting parameter.
+* Return Value : None.
+***********************************************************************************************************************/
+static void bsp_swint_get_all_task_status(e_bsp_swint_unit_t unit, void * const p_args)
+{
+    uint8_t buf_num;
+    st_bsp_swint_task_t *p_swint_task;
+
+    /* Casting is valid because it matches the type of the void type argument to the left. */
+    p_swint_task = (st_bsp_swint_task_t *)p_args;
+
+    /* Clear Task Status */
+    for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++)
+    {
+        p_swint_task->status = s_bsp_swint_task[unit][buf_num].status;
+        p_swint_task->p_taskAddr = s_bsp_swint_task[unit][buf_num].p_taskAddr;
+        p_swint_task->p_context = s_bsp_swint_task[unit][buf_num].p_context;
+        p_swint_task++;
+    }
+} /* End of function bsp_swint_get_all_task_status() */
+
+/**********************************************************************************************************************
+ * Function Name: R_BSP_SoftwareInterruptControl
+ ******************************************************************************************************************//**
+ * @brief This function controls software interrupts.
+ * @param[in] unit Software interrupt unit
+ * @param[in] cmd Software interrupt control command
+ * @param[in, out] p_args Pointer to arguments for software interrupt control commands. Set the argument type to match 
+ * each software interrupt control command. For commands that do not require arguments, use the setting FIT_NO_PTR.
+ * @retval BSP_SWINT_SUCCESS Success.
+ * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified.
+ * @retval BSP_SWINT_ERR_INVALID_IPR Invalid interrupt priority level specified.
+ * @retval BSP_SWINT_ERR_INVALID_CMD Invalid command specified.
+ * @retval BSP_SWINT_ERR_INVALID_BUFFER_NUMBER Invalid task buffer number specified.
+ * @retval BSP_SWINT_ERR_TASK_EXECUTING Attempt to manipulate a task that is running.
+ * @retval BSP_SWINT_ERR_ACCESS_REJECTION Failed to obtain access control right.
+ * @details This function performs software interrupt control in response to commands. Refer the application note for 
+ * the operation of each command.
+ * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this 
+ * function after the R_BSP_SoftwareInterruptOpen function has run.\n
+ * Do not change the interrupt priority level (IPR) while a software interrupt is being processed.\n
+ * When the BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY command is run, interrupts are disabled temporarily in order to set 
+ * the interrupt priority level (IPR).\n
+ * If the access control right cannot be obtained, provide a wait period and then call this function again. It is not 
+ * possible to obtain the access control right during interrupt processing if the interrupt is generated in a state 
+ * where other processing has the access control right. For this reason a deadlock will occur if polling is used in 
+ * the interrupt processing to obtain the access control right.\n
+ * If a software interrupt is generated while this function has the access control right, the software interrupt 
+ * cannot obtain the access control right and interrupt processing ends with the task remaining unexecuted. For this 
+ * reason, after returning from a software interrupt the interrupt request is cleared regardless of whether a task has 
+ * been set in the task buffer. To avoid this, setting of the interrupt request occurs at the end of the processing of 
+ * the BSP_SWINT_CMD_CLEAR_TASK and BSP_SWINT_CMD_CLEAR_ALL_TASK commands. Nevertheless, since all task buffers are 
+ * cleared when processing of the BSP_SWINT_CMD_CLEAR_ALL_TASK command completes successfully, the interrupt request 
+ * is not set.
+ */
+e_bsp_swint_err_t R_BSP_SoftwareInterruptControl(e_bsp_swint_unit_t unit, e_bsp_swint_cmd_t const cmd, void * const p_args)
+{
+    e_bsp_swint_err_t ret;
+    uint8_t *p_swint_buf_num;
+
+    /* Check Unit */
+    if (BSP_SWINT_UNIT_MAX > unit)
+    {
+        ret = BSP_SWINT_SUCCESS;
+
+        /* Execute Command */
+        switch (cmd)
+        {
+            case BSP_SWINT_CMD_GET_INTERRUPT_INFORMATION:
+                bsp_swint_get_interrupt_information(unit, p_args);
+                break;
+
+            case BSP_SWINT_CMD_ENABLE_INTERRUPT:
+                bsp_swint_enable_interrupt(unit);
+                break;
+
+            case BSP_SWINT_CMD_DISABLE_INTERRUPT:
+                bsp_swint_disable_interrupt(unit);
+                break;
+
+            case BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY:
+                ret = bsp_swint_set_interrupt_priority(unit, p_args);
+                break;
+
+            case BSP_SWINT_CMD_SET_INTERRUPT_REQUEST:
+                bsp_swint_set_interrupt_request(unit);
+                break;
+
+            case BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST:
+                bsp_swint_clear_interrupt_request(unit);
+                break;
+
+            case BSP_SWINT_CMD_ENABLE_NESTED_INTERRUPT:
+                bsp_swint_enable_nested_interrupt(unit);
+                break;
+
+            case BSP_SWINT_CMD_DISABLE_NESTED_INTERRUPT:
+                bsp_swint_disable_nested_interrupt(unit);
+                break;
+
+            case BSP_SWINT_CMD_CLEAR_TASK:
+                ret = bsp_swint_clear_task(unit, p_args);
+                break;
+
+            case BSP_SWINT_CMD_CLEAR_ALL_TASK:
+                ret = bsp_swint_clear_all_task(unit);
+                break;
+
+            case BSP_SWINT_CMD_GET_ALL_TASK_STATUS:
+                bsp_swint_get_all_task_status(unit, p_args);
+                break;
+
+            case BSP_SWINT_CMD_GET_USED_BUFFER:
+
+                /* Casting is valid because it matches the type of the void type argument to the left. */
+                p_swint_buf_num = (uint8_t *)p_args;
+
+                /* Casting is valid because it matches the type to the left side. */
+                *p_swint_buf_num = (uint8_t)s_bsp_swint_buf_used[unit];
+                break;
+
+            case BSP_SWINT_CMD_GET_UNUSED_BUFFER:
+
+                /* Casting is valid because it matches the type of the void type argument to the left. */
+                p_swint_buf_num = (uint8_t *)p_args;
+
+                /* Casting is valid because it matches the type to the left side. */
+                *p_swint_buf_num = (uint8_t)(BSP_CFG_SWINT_TASK_BUFFER_NUMBER - s_bsp_swint_buf_used[unit]);
+                break;
+
+            default:
+                ret = BSP_SWINT_ERR_INVALID_CMD;
+                break;
+        }
+    }
+    else
+    {
+        ret = BSP_SWINT_ERR_INVALID_UNIT;
+    }
+
+    return ret;
+} /* End of function R_BSP_SoftwareInterruptControl() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_get_access_control
+* Description  : Get access of software interrupt.
+* Arguments    : unit - Unit number of software interrupt.
+*                p_args - Pointer of setting parameter.
+* Return Value : true - Get access.
+*                false - Failed to get access.
+***********************************************************************************************************************/
+static bool bsp_swint_get_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args)
+{
+    bool ret;
+
+    /* Get Access */
+    R_BSP_EXCHANGE(&g_bsp_swint_access_ctrl[unit].status, &p_args->status);
+
+    if (BSP_PRV_SWINT_ACCESS_ACCEPTATION == p_args->status)
+    {
+        ret = true;
+    }
+    else
+    {
+        ret = false;
+    }
+
+    return ret;
+} /* End of function bsp_swint_get_access_control() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_swint_release_access_control
+* Description  : Release access of software interrupt.
+* Arguments    : unit - Unit number of software interrupt.
+*                p_args - Pointer of setting parameter.
+* Return Value : true - Release access.
+*                false - Failed to release access.
+***********************************************************************************************************************/
+static bool bsp_swint_release_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args)
+{
+    bool ret;
+
+    /* Release access */
+    R_BSP_EXCHANGE(&g_bsp_swint_access_ctrl[unit].status, &p_args->status);
+
+    if (BSP_PRV_SWINT_ACCESS_ACCEPTATION == g_bsp_swint_access_ctrl[unit].status)
+    {
+        ret = true;
+    }
+    else
+    {
+        ret = false;
+    }
+
+    return ret;
+} /* End of function bsp_swint_release_access_control() */
+
+/***********************************************************************************************************************
+* Function name: bsp_swint_dummy_task
+* Description  : Dummy task.
+* Arguments    : p_dummy_context - Dummy arguments.
+* Return value : None.
+***********************************************************************************************************************/
+static void bsp_swint_dummy_task(void * p_dummy_context)
+{
+    R_BSP_NOP();
+} /* End of function bsp_swint_dummy_task() */
+
+/***********************************************************************************************************************
+* Function name: bsp_swint_execute_task
+* Description  : Execute task of software interrupt.
+* Arguments    : unit - Unit number of software interrupt.
+* Return value : None.
+***********************************************************************************************************************/
+static void bsp_swint_execute_task(e_bsp_swint_unit_t unit)
+{
+    st_bsp_swint_access_control_t access_control;
+
+    /* Get Access Control */
+    access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION;
+    if (true == bsp_swint_get_access_control(unit, &access_control))
+    {
+        /* Release Access Control */
+        bsp_swint_release_access_control(unit, &access_control);
+
+        /* Enable Multiple Interrupt */
+        if (BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT == s_bsp_swint_nested_int_status[unit])
+        {
+            R_BSP_InterruptsEnable();
+        }
+
+        /* Get Access Control */
+        access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION;
+        bsp_swint_get_access_control(unit, &access_control);
+
+        /* WAIT_LOOP */
+        while (0 != s_bsp_swint_buf_used[unit])
+        {
+            if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_bottom[unit])
+            {
+                s_bsp_swint_buf_bottom[unit] = 0;
+            }
+            else
+            {
+                s_bsp_swint_buf_bottom[unit]++;
+            }
+
+            if (BSP_SWINT_TASK_STATUS_REQUESTED == s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status)
+            {
+                /* Change Task Status to "EXECUTING" */
+                s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status = BSP_SWINT_TASK_STATUS_EXECUTING;
+
+                /* Release Access Control */
+                bsp_swint_release_access_control(unit, &access_control);
+
+                /* Execute Task */
+                s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].p_taskAddr(s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].p_context);
+
+                /* Get Access Control */
+                access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION;
+                bsp_swint_get_access_control(unit, &access_control);
+
+                if (BSP_SWINT_TASK_STATUS_EXECUTING == s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status)
+                {
+                    /* Change Task Status to "COMPLETED" */
+                    s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status = BSP_SWINT_TASK_STATUS_COMPLETED;
+                }
+            }
+
+            if (0 != s_bsp_swint_buf_used[unit])
+            {
+                s_bsp_swint_buf_used[unit]--;
+            }
+        }
+
+        /* Release Access Control */
+        bsp_swint_release_access_control(unit, &access_control);
+    }
+} /* End of function bsp_swint_execute_task() */
+
+#endif /* (BSP_CFG_SWINT_UNIT1_ENABLE == 1) || (BSP_CFG_SWINT_UNIT2_ENABLE == 1) */
+
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+/***********************************************************************************************************************
+* Function name: bsp_swint_isr
+* Description  : Software interrupt function. (Unit1)
+* Arguments    : None.
+* Return value : None.
+***********************************************************************************************************************/
+R_BSP_ATTRIB_STATIC_INTERRUPT void bsp_swint_isr(void)
+{
+    bsp_swint_execute_task(BSP_SWINT_UNIT1);
+} /* End of function bsp_swint_isr() */
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+/***********************************************************************************************************************
+* Function name: bsp_swint2_isr
+* Description  : Software interrupt function. (Unit2)
+* Arguments    : None.
+* Return value : None.
+***********************************************************************************************************************/
+R_BSP_ATTRIB_STATIC_INTERRUPT void bsp_swint2_isr(void)
+{
+    bsp_swint_execute_task(BSP_SWINT_UNIT2);
+} /* End of function bsp_swint2_isr() */
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h
new file mode 100644
index 00000000..0ce9ba05
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h
@@ -0,0 +1,138 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_software_interrupt.h
+* Description  : This module implements software interrupt specific functions.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 08.10.2019 1.00     First Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/* Multiple inclusion prevention macro */
+#ifndef SOFTWARE_INTERRUPT_H
+#define SOFTWARE_INTERRUPT_H
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) || \
+    (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+
+typedef enum e_bsp_swint_unit
+{
+#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1))
+    BSP_SWINT_UNIT1,
+#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */
+#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1))
+    BSP_SWINT_UNIT2,
+#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */
+    BSP_SWINT_UNIT_MAX
+} e_bsp_swint_unit_t;
+
+typedef enum e_bsp_swint_err
+{
+    BSP_SWINT_SUCCESS = 0,
+    BSP_SWINT_ERR_ALREADY_OPEN,
+    BSP_SWINT_ERR_NOT_CLOSED,
+    BSP_SWINT_ERR_INVALID_UNIT,
+    BSP_SWINT_ERR_INVALID_IPR,
+    BSP_SWINT_ERR_INVALID_CMD,
+    BSP_SWINT_ERR_INVALID_TASK,
+    BSP_SWINT_ERR_INVALID_BUFFER_NUMBER,
+    BSP_SWINT_ERR_TASK_EXECUTING,
+    BSP_SWINT_ERR_FULL_BUFFER,
+    BSP_SWINT_ERR_ACCESS_REJECTION
+} e_bsp_swint_err_t;
+
+typedef enum e_bsp_swint_cmd
+{
+    BSP_SWINT_CMD_GET_INTERRUPT_INFORMATION = 0,
+    BSP_SWINT_CMD_ENABLE_INTERRUPT,
+    BSP_SWINT_CMD_DISABLE_INTERRUPT,
+    BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY,
+    BSP_SWINT_CMD_SET_INTERRUPT_REQUEST,
+    BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST,
+    BSP_SWINT_CMD_ENABLE_NESTED_INTERRUPT,
+    BSP_SWINT_CMD_DISABLE_NESTED_INTERRUPT,
+    BSP_SWINT_CMD_CLEAR_TASK,
+    BSP_SWINT_CMD_CLEAR_ALL_TASK,
+    BSP_SWINT_CMD_GET_ALL_TASK_STATUS,
+    BSP_SWINT_CMD_GET_USED_BUFFER,
+    BSP_SWINT_CMD_GET_UNUSED_BUFFER
+} e_bsp_swint_cmd_t;
+
+typedef struct st_bsp_swint_int_info
+{
+    uint8_t ipr;
+    uint8_t ien;
+    uint8_t ir;
+    uint8_t nested_int;
+} st_bsp_swint_int_info_t;
+
+typedef enum e_bsp_swint_task_status
+{
+    BSP_SWINT_TASK_STATUS_NO_REQUEST = 0,
+    BSP_SWINT_TASK_STATUS_REQUESTED,
+    BSP_SWINT_TASK_STATUS_EXECUTING,
+    BSP_SWINT_TASK_STATUS_COMPLETED
+} e_bsp_swint_task_status_t;
+
+typedef struct st_bsp_swint_task
+{
+    e_bsp_swint_task_status_t status;
+    void (*p_taskAddr)(void *p_task_args);
+    void *p_context;
+} st_bsp_swint_task_t;
+
+typedef struct st_bsp_swint_task_buffer
+{
+    uint8_t number;
+} st_bsp_swint_task_buffer_t;
+
+typedef struct st_bsp_swint_access_control
+{
+    int32_t status;
+} st_bsp_swint_access_control_t;
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+e_bsp_swint_err_t R_BSP_SoftwareInterruptOpen(e_bsp_swint_unit_t unit);
+e_bsp_swint_err_t R_BSP_SoftwareInterruptClose(e_bsp_swint_unit_t unit);
+e_bsp_swint_err_t R_BSP_SoftwareInterruptSetTask(e_bsp_swint_unit_t unit, st_bsp_swint_task_t set_task);
+e_bsp_swint_err_t R_BSP_SoftwareInterruptControl(e_bsp_swint_unit_t unit, e_bsp_swint_cmd_t const cmd, void * const p_args);
+
+#endif /* (BSP_CFG_SWINT_UNIT1_ENABLE == 1) || (BSP_CFG_SWINT_UNIT2_ENABLE == 1) */
+
+#endif  /* End of multiple inclusion prevention macro */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rtos.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rtos.h
new file mode 100644
index 00000000..6d4d8268
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rtos.h
@@ -0,0 +1,66 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_rtos.h
+* Description  : This module implements functions of rtos.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+*         : 08.10.2019 1.10     Added include file and macro definitions for Renesas RTOS (RI600V4 or RI600PX).
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_bsp_config.h"
+
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#include "queue.h"
+#include "croutine.h"
+#include "timers.h"
+#include "event_groups.h"
+#include "freertos_start.h"
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+#include "kernel.h"
+#include "kernel_id.h"
+
+#define RENESAS_RI600V4  0
+#define RENESAS_RI600PX  1
+
+#undef  BSP_CFG_RTOS_SYSTEM_TIMER
+#define BSP_CFG_RTOS_SYSTEM_TIMER      _RI_CLOCK_TIMER
+#else
+#endif
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef R_RTOS_H
+#define R_RTOS_H
+
+#endif  /* R_RTOS_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h
new file mode 100644
index 00000000..d0335907
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h
@@ -0,0 +1,1638 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_rx_compiler.h
+* Description  : This is a file for integrating the definitions of different functions for each compilers.
+*                Replace different functions for each compiler.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+*         : 08.10.2019 1.01     Modified definition of __RX_DPFPU_INSNS__ to __RX_DFPU_INSNS__ for GNUC.
+*                               Modified definition of TFU for GNUC.
+*                               Modified comment of TFU for ICCRX.
+*                               Added include of r_bsp_config.h.
+*                               Changed the following definitions for added support of Renesas RTOS(RI600V4 or RI600PX).
+*                               - R_BSP_SECNAME_INTVECTTBL
+*                               - R_BSP_SECNAME_EXCEPTVECTTBL
+*                               - R_BSP_SECNAME_FIXEDVECTTBL
+*                               - R_BSP_PRAGMA_INTERRUPT
+*                               - R_BSP_PRAGMA_STATIC_INTERRUPT
+*                               - R_BSP_PRAGMA_INTERRUPT_FUNCTION
+*                               - R_BSP_ATTRIB_STATIC_INTERRUPT
+*                               - R_BSP_PRAGMA_INTERRUPT_DEFAULT
+*                               - R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT
+*                               Changed the following definitions to definition without __no_init for ICCRX so that 
+*                               there is no warning when the initial value is specified.
+*                               - _R_BSP_ATTRIB_SECTION_CHANGE_C1
+*                               - _R_BSP_ATTRIB_SECTION_CHANGE_C2
+*                               - _R_BSP_ATTRIB_SECTION_CHANGE_C4
+*                               - _R_BSP_ATTRIB_SECTION_CHANGE_C8
+*                               - _R_BSP_ATTRIB_SECTION_CHANGE_D1
+*                               - _R_BSP_ATTRIB_SECTION_CHANGE_D2
+*                               - _R_BSP_ATTRIB_SECTION_CHANGE_D4
+*                               - _R_BSP_ATTRIB_SECTION_CHANGE_D8
+*         : 17.12.2019 1.02     Modified the comment of description.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_bsp_common.h"
+#include "r_bsp_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef R_RX_COMPILER_H
+#define R_RX_COMPILER_H
+
+/* ========== Check Compiler ========== */
+#if defined(__CCRX__)
+    /* supported */
+#elif defined(__GNUC__)
+    /* supported */
+#elif defined(__ICCRX__)
+    /* supported */
+#else
+    #error "Unrecognized compiler"
+#endif
+
+
+/* ========== Macros ========== */
+#if defined(__CCRX__)
+
+/* #define __RX 1 */ /* This is automatically defined by CCRX. */
+/* #define __LIT 1 */ /* This is automatically defined by CCRX. */
+/* #define __BIG 1 */ /* This is automatically defined by CCRX. */
+/* #define __FPU 1 */ /* This is automatically defined by CCRX. */
+/* #define __RXV1 1 */ /* This is automatically defined by CCRX. */
+/* #define __RXV2 1 */ /* This is automatically defined by CCRX. */
+/* #define __RXV3 1 */ /* This is automatically defined by CCRX. */
+/* #define __TFU 1 */ /* This is automatically defined by CCRX. */
+/* #define __DPFPU 1 */ /* This is automatically defined by CCRX. */
+
+#elif defined(__GNUC__)
+
+#if !defined(__RX)
+#define __RX 1
+#endif
+
+#if defined(__RX_LITTLE_ENDIAN__)
+#if !defined(__LIT)
+#define __LIT 1
+#endif
+#elif defined(__RX_BIG_ENDIAN__)
+#if !defined(__BIG)
+#define __BIG 1
+#endif
+#endif
+
+#if defined(__RX_FPU_INSNS__)
+#if !defined(__FPU)
+#define __FPU 1
+#endif
+#endif
+
+#if defined(__RXv1__)
+#if !defined(__RXV1)
+#define __RXV1 1
+#endif
+#endif
+
+#if defined(__RXv2__)
+#if !defined(__RXV2)
+#define __RXV2 1
+#endif
+#endif
+
+#if defined(__RXv3__)
+#if !defined(__RXV3)
+#define __RXV3 1
+#endif
+#endif
+
+/* #define __TFU 1 */ /* This is automatically defined by GNUC. */
+
+#if defined(__RX_DFPU_INSNS__)
+#if !defined(__DPFPU)
+#define __DPFPU 1
+#endif
+#endif
+
+#elif defined(__ICCRX__)
+
+#if !defined(__RX)
+#define __RX 1
+#endif
+
+/* #define __LIT 1 */ /* This is automatically defined by ICCRX. */
+/* #define __BIG 1 */ /* This is automatically defined by ICCRX. */
+/* #define __FPU 1 */ /* This is automatically defined by ICCRX. */
+/* #define __RXV1 1 */ /* This is automatically defined by ICCRX. */
+/* #define __RXV2 1 */ /* This is automatically defined by ICCRX. */
+/* #define __RXV3 1 */ /* This is automatically defined by ICCRX. */
+/* #define __TFU 1 */ /* This is automatically defined by ICCRX. */
+/* #define __DPFPU 1 */ /* Not yet supported. */
+
+#endif
+
+
+/* ========== Keywords ========== */
+#if !(defined(__CCRX__) && defined(__cplusplus))
+#define R_BSP_PRAGMA(...)    _Pragma(#__VA_ARGS__)
+#else
+/* CC-RX' C++ mode does not support Pragma operator and variadic macros */
+#define R_BSP_PRAGMA(x)
+#endif
+
+#if defined(__CCRX__)
+
+#define R_BSP_VOLATILE_EVENACCESS        volatile __evenaccess
+#define R_BSP_EVENACCESS                 __evenaccess
+#define R_BSP_EVENACCESS_SFR             __evenaccess
+#define R_BSP_VOLATILE_SFR               volatile
+#define R_BSP_SFR                        /* none */
+
+#elif defined(__GNUC__)
+
+#define R_BSP_VOLATILE_EVENACCESS        volatile
+#define R_BSP_EVENACCESS                 /* none */
+#define R_BSP_EVENACCESS_SFR             /* none */
+#define R_BSP_VOLATILE_SFR               volatile
+#define R_BSP_SFR                        /* none */
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_VOLATILE_EVENACCESS        volatile
+#define R_BSP_EVENACCESS                 volatile
+#define R_BSP_EVENACCESS_SFR             __sfr
+#define R_BSP_VOLATILE_SFR               volatile __sfr
+#define R_BSP_SFR                        __sfr
+
+#endif
+
+
+/* ========== Sections ========== */
+
+/* ---------- Operators ---------- */
+#if defined(__CCRX__)
+
+#define R_BSP_SECTOP(name)        __sectop(#name)
+#define R_BSP_SECEND(name)        __secend(#name)
+#define R_BSP_SECSIZE(name)       __secsize(#name)
+
+#define R_BSP_SECTION_OPERATORS_INIT(name)    /* none */
+
+#elif defined(__GNUC__)
+
+#define R_BSP_SECTOP(name)        ((void *)name##_start)
+#define R_BSP_SECEND(name)        ((void *)name##_end)
+#define R_BSP_SECSIZE(name)       ((size_t)((uint8_t *)R_BSP_SECEND(name) - (uint8_t *)R_BSP_SECTOP(name)))
+
+#define R_BSP_SECTION_OPERATORS_INIT(name)    extern uint8_t name##_start[], name##_end[];
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_SECTOP(name)        __section_begin(#name)
+#define R_BSP_SECEND(name)        __section_end(#name)
+#define R_BSP_SECSIZE(name)       __section_size(#name)
+
+#define R_BSP_SECTION_OPERATORS_INIT(name)    R_BSP_PRAGMA(section = #name);
+
+#endif
+
+/* ---------- Names ---------- */
+#if defined(__CCRX__)
+
+#if BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+#define R_BSP_SECNAME_INTVECTTBL       "INTERRUPT_VECTOR"
+#else /* BSP_CFG_RTOS_USED != 4 */
+#define R_BSP_SECNAME_INTVECTTBL       "C$VECT"
+#endif /* BSP_CFG_RTOS_USED */
+
+#if defined(__RXV2) || defined(__RXV3)
+#if BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+#define R_BSP_SECNAME_EXCEPTVECTTBL    "FIX_INTERRUPT_VECTOR"
+#else /* BSP_CFG_RTOS_USED != 4 */
+#define R_BSP_SECNAME_EXCEPTVECTTBL    "EXCEPTVECT"
+#endif /* BSP_CFG_RTOS_USED */
+#define R_BSP_SECNAME_RESETVECT        "RESETVECT"
+#else /* __RXV1 */
+#if BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+#define R_BSP_SECNAME_FIXEDVECTTBL     "FIX_INTERRUPT_VECTOR"
+#else /* BSP_CFG_RTOS_USED != 4 */
+#define R_BSP_SECNAME_FIXEDVECTTBL     "FIXEDVECT"
+#endif /* BSP_CFG_RTOS_USED */
+#endif /* defined(__RXV2) || defined(__RXV3) */
+#define R_BSP_SECNAME_UBSETTINGS       "UBSETTINGS"
+
+#elif defined(__GNUC__)
+
+#define R_BSP_SECNAME_INTVECTTBL       ".rvectors"
+#if defined(__RXV2) || defined(__RXV3)
+#define R_BSP_SECNAME_EXCEPTVECTTBL    ".exvectors"
+#define R_BSP_SECNAME_RESETVECT        ".fvectors"
+#else
+#define R_BSP_SECNAME_FIXEDVECTTBL     ".fvectors"
+#endif
+#define R_BSP_SECNAME_UBSETTINGS       ".ubsettings"
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_SECNAME_INTVECTTBL       ".inttable"
+#if defined(__RXV2) || defined(__RXV3)
+#define R_BSP_SECNAME_EXCEPTVECTTBL    ".exceptvect"
+#define R_BSP_SECNAME_RESETVECT        ".resetvect"
+#else
+#define R_BSP_SECNAME_FIXEDVECTTBL     ".exceptvect"
+#endif
+#define R_BSP_SECNAME_UBSETTINGS       ".ubsettings"
+
+#endif
+
+/* ---------- Addresses ---------- */
+#if defined(__CCRX__)
+
+#define R_BSP_SECTOP_INTVECTTBL       __sectop(R_BSP_SECNAME_INTVECTTBL)
+#if defined(__RXV2) || defined(__RXV3)
+#define R_BSP_SECTOP_EXCEPTVECTTBL    __sectop(R_BSP_SECNAME_EXCEPTVECTTBL)
+#endif
+
+#elif defined(__GNUC__)
+
+#define R_BSP_SECTOP_INTVECTTBL       ((void *)rvectors_start)
+extern void * const                   rvectors_start[];
+#if defined(__RXV2) || defined(__RXV3)
+#define R_BSP_SECTOP_EXCEPTVECTTBL    ((void *)exvectors_start)
+extern void * const                   exvectors_start[];
+#endif
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_SECTOP_INTVECTTBL       /* none */
+#if defined(__RXV2) || defined(__RXV3)
+#define R_BSP_SECTOP_EXCEPTVECTTBL    /* none */
+#endif
+
+#endif
+
+
+/* ========== #pragma Directive ========== */
+
+/* ---------- Stack Size ---------- */
+#if defined(__CCRX__)
+
+#define R_BSP_PRAGMA_STACKSIZE_SI(_size)     _R_BSP_PRAGMA_STACKSIZE_SI(_size) /* _size means '(size)' */
+#define _R_BSP_PRAGMA_STACKSIZE_SI(_size)    __R_BSP_PRAGMA_STACKSIZE_SI##_size
+#define __R_BSP_PRAGMA_STACKSIZE_SI(size)    R_BSP_PRAGMA(stacksize si=size)
+#define R_BSP_PRAGMA_STACKSIZE_SU(_size)     _R_BSP_PRAGMA_STACKSIZE_SU(_size) /* _size means '(size)' */
+#define _R_BSP_PRAGMA_STACKSIZE_SU(_size)    __R_BSP_PRAGMA_STACKSIZE_SU##_size
+#define __R_BSP_PRAGMA_STACKSIZE_SU(size)    R_BSP_PRAGMA(stacksize su=size)
+
+#elif defined(__GNUC__)
+
+#define R_BSP_PRAGMA_STACKSIZE_SI(size)      static uint8_t istack_area[size] __attribute__((section(".r_bsp_istack"), used));
+#define R_BSP_PRAGMA_STACKSIZE_SU(size)      static uint8_t ustack_area[size] __attribute__((section(".r_bsp_ustack"), used));
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_PRAGMA_STACKSIZE_SI(size)      /* none */
+#define R_BSP_PRAGMA_STACKSIZE_SU(size)      /* none */
+
+#endif
+
+/* ---------- Section Switch (part1) ---------- */
+#if defined(__CCRX__)
+
+#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS                R_BSP_PRAGMA(section C UBSETTINGS)
+#if defined(__RXV2) || defined(__RXV3)
+#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT                R_BSP_PRAGMA(section C EXCEPTVECT)
+#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT                 R_BSP_PRAGMA(section C RESETVECT)
+#else
+#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT                 R_BSP_PRAGMA(section C FIXEDVECT)
+#endif
+
+#elif defined(__GNUC__)
+
+#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS                __attribute__((section(R_BSP_SECNAME_UBSETTINGS)))
+#if defined(__RXV2) || defined(__RXV3)
+#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT                __attribute__((section(R_BSP_SECNAME_EXCEPTVECTTBL)))
+#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT                 __attribute__((section(R_BSP_SECNAME_RESETVECT)))
+#else
+#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT                 __attribute__((section(R_BSP_SECNAME_FIXEDVECTTBL)))
+#endif
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS                R_BSP_PRAGMA(location=R_BSP_SECNAME_UBSETTINGS)
+#if defined(__RXV2) || defined(__RXV3)
+#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT                /* none */
+#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT                 /* none */
+#else
+#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT                 /* none */
+#endif
+#endif
+
+/* ---------- Section Switch (part2) ---------- */
+#if defined(__CCRX__)
+
+#define __R_BSP_ATTRIB_SECTION_CHANGE_V(type, section_name)    R_BSP_PRAGMA(section type section_name)
+#define __R_BSP_ATTRIB_SECTION_CHANGE_F(type, section_name)    R_BSP_PRAGMA(section type section_name)
+
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_1' automatically */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_2' automatically */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX does not add postfix '_4' */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_8' automatically */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_1' automatically */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_2' automatically */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX does not add postfix '_4' */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_8' automatically */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_1' automatically */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_2' automatically */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX does not add postfix '_4' */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_8' automatically */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag)            __R_BSP_ATTRIB_SECTION_CHANGE_F(P, P##section_tag)
+
+#if !defined(__cplusplus)
+#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...)    _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag)
+#else
+/* CC-RX' C++ mode does not support variadic macros */
+#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, align)  _R_BSP_ATTRIB_SECTION_CHANGE_##type##align(section_tag)
+#endif
+
+#define R_BSP_ATTRIB_SECTION_CHANGE_END                        R_BSP_PRAGMA(section)
+
+#elif defined(__GNUC__)
+
+#define __R_BSP_ATTRIB_SECTION_CHANGE_V(section_name)          __attribute__((section(#section_name)))
+#define __R_BSP_ATTRIB_SECTION_CHANGE_F(section_name)          __attribute__((section(#section_name)))
+
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_1)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_2)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag) /* No postfix '_4' because the CC-RX does not add it */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_8)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_1)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_2)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag) /* No postfix '_4' because the CC-RX does not add it */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_8)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_1)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_2)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag) /* No postfix '_4' because the CC-RX does not add it */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_8)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag)            __R_BSP_ATTRIB_SECTION_CHANGE_F(P##section_tag)
+
+#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...)    _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag)
+#define R_BSP_ATTRIB_SECTION_CHANGE_END                        /* none */
+
+#elif defined(__ICCRX__)
+
+#define __R_BSP_ATTRIB_SECTION_CHANGE_V(section_name)          R_BSP_PRAGMA(location=#section_name)\
+                                                               __no_init
+#define __R_BSP_ATTRIB_SECTION_CHANGE_F(section_name)          R_BSP_PRAGMA(location=#section_name)
+
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_1)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_2)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag) /* No postfix '_4' because the CC-RX does not add it */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_8)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_1)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_2)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag) /* No postfix '_4' because the CC-RX does not add it */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_8)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_1)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_2)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag) /* No postfix '_4' because the CC-RX does not add it */
+#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag)           __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_8)
+#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag)            __R_BSP_ATTRIB_SECTION_CHANGE_F(P##section_tag)
+
+#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...)    _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag)
+#define R_BSP_ATTRIB_SECTION_CHANGE_END                        /* none */
+
+#endif
+
+/* ---------- Interrupt Function Creation ---------- */
+#if defined(__CCRX__)
+
+/* Standard */
+#if BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+#define R_BSP_PRAGMA_INTERRUPT(function_name, vector)                 extern void function_name(void);
+
+#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector)          void function_name(void);
+
+#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name)                extern void function_name(void);
+
+#else /* BSP_CFG_RTOS_USED != 4*/
+#define R_BSP_PRAGMA_INTERRUPT(function_name, vector)                 R_BSP_PRAGMA(interrupt function_name(vect=vector))\
+                                                                      extern void function_name(void);
+#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector)          R_BSP_PRAGMA(interrupt function_name(vect=vector))\
+                                                                      static void function_name(void);
+
+#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name)                R_BSP_PRAGMA(interrupt function_name)\
+                                                                      extern void function_name(void);
+#endif /* BSP_CFG_RTOS_USED */
+
+#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name)         R_BSP_PRAGMA(interrupt function_name)\
+                                                                      static void function_name(void);
+
+#define R_BSP_ATTRIB_INTERRUPT                                        extern /* only this one because of no corresponding keyword */
+
+#if BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+#define R_BSP_ATTRIB_STATIC_INTERRUPT                                 
+#else /* BSP_CFG_RTOS_USED !=4 */
+#define R_BSP_ATTRIB_STATIC_INTERRUPT                                 static /* only this one because of no corresponding keyword */
+#endif /* BSP_CFG_RTOS_USED */
+
+/* Fast */
+#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vector)            R_BSP_PRAGMA(interrupt function_name(vect=vector, fint))\
+                                                                      extern void function_name(void);
+#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vector)     R_BSP_PRAGMA(interrupt function_name(vect=vector, fint))\
+                                                                      static void function_name(void);
+
+#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name)           R_BSP_PRAGMA(interrupt function_name(fint))\
+                                                                      extern void function_name(void);
+#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name)    R_BSP_PRAGMA(interrupt function_name(fint))\
+                                                                      static void function_name(void);
+
+#define R_BSP_ATTRIB_FAST_INTERRUPT                                   extern /* only this one because of no corresponding keyword */
+#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT                            static /* only this one because of no corresponding keyword */
+
+/* Default */
+#if BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name)                 extern void function_name(void);
+
+#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name)          void function_name(void);
+#else /* BSP_CFG_RTOS_USED != 4 */
+#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name)                 R_BSP_PRAGMA(interrupt function_name)\
+                                                                      extern void function_name(void);
+
+#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name)          R_BSP_PRAGMA(interrupt function_name)\
+                                                                      static void function_name(void);
+#endif /* BSP_CFG_RTOS_USED */
+
+#elif defined(__GNUC__)
+
+/* Standard */
+#define R_BSP_PRAGMA_INTERRUPT(function_name, vector)                 extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector)));
+#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector)          static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector), used));
+
+#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name)                extern void function_name(void) __attribute__((interrupt));
+#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name)         static void function_name(void) __attribute__((interrupt, used));
+
+#define R_BSP_ATTRIB_INTERRUPT                                        extern /* only this one because __attribute__((interrupt)) prevents GNURX from generating vector */
+#define R_BSP_ATTRIB_STATIC_INTERRUPT                                 static /* only this one because __attribute__((interrupt, used)) prevents GNURX from generating vector */
+
+/* Fast */
+#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vector)            extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector))) \
+                                                                                                      __attribute__((fast_interrupt));
+#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vector)     static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector), used)) \
+                                                                                                      __attribute__((fast_interrupt, used));
+
+#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name)           extern void function_name(void) __attribute__((fast_interrupt));
+#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name)    static void function_name(void) __attribute__((fast_interrupt, used));
+
+#define R_BSP_ATTRIB_FAST_INTERRUPT                                   extern /* __attribute__((interrupt(fast))) Not necessary,
+                                                                                but Don't forget a R_BSP_PRAGMA_FAST_INTERRUPT() declaration */
+#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT                            static /* __attribute__((interrupt(fast)), used) Not necessary, 
+                                                                                but Don't forget a R_BSP_PRAGMA_STATIC_FAST_INTERRUPT() declaration */
+
+/* Default */
+#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name)                 extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, "$default")));
+#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name)          static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, "$default"), used));
+
+#elif defined(__ICCRX__)
+
+/* Standard */
+#define R_BSP_PRAGMA_INTERRUPT(function_name, vect)                   R_BSP_PRAGMA(vector=vect)\
+                                                                      extern __interrupt void function_name(void);
+#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vect)            R_BSP_PRAGMA(vector=vect)\
+                                                                      static __interrupt void function_name(void);
+
+#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name)                extern __interrupt void function_name(void);
+#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name)         static __interrupt void function_name(void);
+
+#define R_BSP_ATTRIB_INTERRUPT                                        extern __interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */
+#define R_BSP_ATTRIB_STATIC_INTERRUPT                                 static __interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */
+
+/* Fast */
+#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vect)              R_BSP_PRAGMA(vector=vect)\
+                                                                      extern __fast_interrupt void function_name(void);
+#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vect)       R_BSP_PRAGMA(vector=vect)\
+                                                                      static __fast_interrupt void function_name(void);
+
+#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name)           extern __fast_interrupt void function_name(void);
+#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name)    static __fast_interrupt void function_name(void);
+
+#define R_BSP_ATTRIB_FAST_INTERRUPT                                   extern __fast_interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */
+#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT                            static __fast_interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */
+
+/* Default */
+#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name)                 extern __interrupt void function_name(void);
+#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name)          static __interrupt void function_name(void);
+
+#endif
+
+/* ---------- Inline Expansion of Function ---------- */
+#if defined(__CCRX__)
+
+#define R_BSP_PRAGMA_INLINE(function_name)           R_BSP_PRAGMA(inline function_name)\
+                                                     extern
+#define R_BSP_PRAGMA_STATIC_INLINE(function_name)    R_BSP_PRAGMA(inline function_name)\
+                                                     static
+
+#elif defined(__GNUC__)
+
+#define R_BSP_PRAGMA_INLINE(function_name)           inline extern __attribute__((always_inline))
+#define R_BSP_PRAGMA_STATIC_INLINE(function_name)    inline static __attribute__((always_inline))
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_PRAGMA_INLINE(function_name)           R_BSP_PRAGMA(inline=forced)\
+                                                     extern
+#define R_BSP_PRAGMA_STATIC_INLINE(function_name)    R_BSP_PRAGMA(inline=forced)\
+                                                     static
+
+#endif
+
+/* ---------- Inline Expansion of Assembly-Language Function (part1) ---------- */
+#if defined(__CCRX__)
+
+#define R_BSP_PRAGMA_INLINE_ASM(function_name)           R_BSP_PRAGMA(inline_asm function_name)\
+                                                         extern
+#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name)    R_BSP_PRAGMA(inline_asm function_name)\
+                                                         static
+
+#define R_BSP_ATTRIB_INLINE_ASM                          extern /* only this one because of no corresponding keyword */
+#define R_BSP_ATTRIB_STATIC_INLINE_ASM                   static /* only this one because of no corresponding keyword */
+
+#elif defined(__GNUC__)
+
+/* Using inline assembler without operands and clobbered resources is dangerous but using it with them is too difficult. */
+
+#define R_BSP_PRAGMA_INLINE_ASM(function_name)           extern __attribute__((naked, noinline))
+#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name)    static __attribute__((naked, noinline))
+
+#define R_BSP_ATTRIB_INLINE_ASM                          extern /* only this one because of no corresponding keyword */
+#define R_BSP_ATTRIB_STATIC_INLINE_ASM                   static /* only this one because of no corresponding keyword */
+
+#elif defined(__ICCRX__)
+
+/* Using inline assembler without operands and clobbered resources is dangerous but using it with them is too difficult. */
+
+#define R_BSP_PRAGMA_INLINE_ASM(function_name)           R_BSP_PRAGMA(inline=never)\
+                                                         extern
+#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name)    R_BSP_PRAGMA(inline=never)\
+                                                         static
+
+#define R_BSP_ATTRIB_INLINE_ASM                          extern /* ICCRX requires __task not only at a function declaration but also at a function definition */
+#define R_BSP_ATTRIB_STATIC_INLINE_ASM                   static /* ICCRX requires __task not only at a function declaration but also at a function definition */
+
+#endif
+
+/* ---------- Inline Expansion of Assembly-Language Function (part2) ---------- */
+#if defined(__CDT_PARSER__)
+
+#define R_BSP_ASM(...)            /* none */
+#define R_BSP_ASM_LAB_NEXT(n)     /* none */
+#define R_BSP_ASM_LAB_PREV(n)     /* none */
+#define R_BSP_ASM_LAB(n_colon)    /* none */
+#define R_BSP_ASM_BEGIN           /* none */
+#define R_BSP_ASM_END             /* none */
+
+#else
+
+#if defined(__CCRX__)
+
+#if !defined(__cplusplus)
+#define R_BSP_ASM(...)            __VA_ARGS__
+#else
+/* CC-RX' C++ mode does not support variadic macros */
+#endif
+#define R_BSP_ASM_LAB_NEXT(n)     ?+
+#define R_BSP_ASM_LAB_PREV(n)     ?-
+#define R_BSP_ASM_LAB(n_colon)    R_BSP_ASM(?:)
+#define R_BSP_ASM_BEGIN           /* none */
+#define R_BSP_ASM_END             /* none */
+
+#elif defined(__GNUC__)
+
+#define _R_BSP_ASM(...)           #__VA_ARGS__
+#define R_BSP_ASM(...)            _R_BSP_ASM(__VA_ARGS__\n)
+#define R_BSP_ASM_LAB_NEXT(n)     ?+
+#define R_BSP_ASM_LAB_PREV(n)     ?-
+#define R_BSP_ASM_LAB(n_colon)    R_BSP_ASM(?:)
+#define R_BSP_ASM_BEGIN           __asm__ volatile (
+#define R_BSP_ASM_END             R_BSP_ASM(rts));
+
+#elif defined(__ICCRX__)
+
+#define _R_BSP_ASM(...)           #__VA_ARGS__
+#define R_BSP_ASM(...)            _R_BSP_ASM(__VA_ARGS__\n)
+#define R_BSP_ASM_LAB_NEXT(n)     _lab##n
+#define R_BSP_ASM_LAB_PREV(n)     _lab##n
+#define R_BSP_ASM_LAB(n_colon)    R_BSP_ASM(_lab##n_colon)
+#define R_BSP_ASM_BEGIN           asm(
+#define R_BSP_ASM_END             );
+
+#endif
+
+#endif /* defined(__CDT_PARSER__) */
+
+/* ---------- Inline Expansion of Assembly-Language Function (part3) ---------- */
+#if defined(__CCRX__)
+
+#define R_BSP_ASM_INTERNAL_USED(p)        /* no way */
+#define R_BSP_ASM_INTERNAL_NOT_USED(p)    /* no way */
+
+#elif defined(__GNUC__)
+
+#define R_BSP_ASM_INTERNAL_USED(p)        ((void)(p));
+#define R_BSP_ASM_INTERNAL_NOT_USED(p)    ((void)(p));
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_ASM_INTERNAL_USED(p)        ((void)(p));
+#define R_BSP_ASM_INTERNAL_NOT_USED(p)    ((void)(p));
+
+#endif
+
+/* ---------- Bit Field Order Specification ---------- */
+
+/* ---------- bit_order=left ---------- */
+#if defined(__CCRX__)
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                           bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                           bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                           bf30, bf31)\
+struct {\
+R_BSP_PRAGMA(bit_order left)\
+    struct {\
+        bf0;\
+        bf1;\
+        bf2;\
+        bf3;\
+        bf4;\
+        bf5;\
+        bf6;\
+        bf7;\
+        bf8;\
+        bf9;\
+        bf10;\
+        bf11;\
+        bf12;\
+        bf13;\
+        bf14;\
+        bf15;\
+        bf16;\
+        bf17;\
+        bf18;\
+        bf19;\
+        bf20;\
+        bf21;\
+        bf22;\
+        bf23;\
+        bf24;\
+        bf25;\
+        bf26;\
+        bf27;\
+        bf28;\
+        bf29;\
+        bf30;\
+        bf31;\
+    };\
+R_BSP_PRAGMA(bit_order)\
+}
+
+#elif defined(__GNUC__)
+
+#if defined(__LIT)
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                           bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                           bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                           bf30, bf31)\
+struct {\
+    bf31;\
+    bf30;\
+    bf29;\
+    bf28;\
+    bf27;\
+    bf26;\
+    bf25;\
+    bf24;\
+    bf23;\
+    bf22;\
+    bf21;\
+    bf20;\
+    bf19;\
+    bf18;\
+    bf17;\
+    bf16;\
+    bf15;\
+    bf14;\
+    bf13;\
+    bf12;\
+    bf11;\
+    bf10;\
+    bf9;\
+    bf8;\
+    bf7;\
+    bf6;\
+    bf5;\
+    bf4;\
+    bf3;\
+    bf2;\
+    bf1;\
+    bf0;\
+}
+
+#else /* defined(__LIT) */
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                           bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                           bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                           bf30, bf31)\
+struct {\
+    bf0;\
+    bf1;\
+    bf2;\
+    bf3;\
+    bf4;\
+    bf5;\
+    bf6;\
+    bf7;\
+    bf8;\
+    bf9;\
+    bf10;\
+    bf11;\
+    bf12;\
+    bf13;\
+    bf14;\
+    bf15;\
+    bf16;\
+    bf17;\
+    bf18;\
+    bf19;\
+    bf20;\
+    bf21;\
+    bf22;\
+    bf23;\
+    bf24;\
+    bf25;\
+    bf26;\
+    bf27;\
+    bf28;\
+    bf29;\
+    bf30;\
+    bf31;\
+}
+
+#endif /* defined(__LIT) */
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                           bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                           bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                           bf30, bf31)\
+struct {\
+R_BSP_PRAGMA(bitfields=reversed_disjoint_types)\
+    struct {\
+        bf0;\
+        bf1;\
+        bf2;\
+        bf3;\
+        bf4;\
+        bf5;\
+        bf6;\
+        bf7;\
+        bf8;\
+        bf9;\
+        bf10;\
+        bf11;\
+        bf12;\
+        bf13;\
+        bf14;\
+        bf15;\
+        bf16;\
+        bf17;\
+        bf18;\
+        bf19;\
+        bf20;\
+        bf21;\
+        bf22;\
+        bf23;\
+        bf24;\
+        bf25;\
+        bf26;\
+        bf27;\
+        bf28;\
+        bf29;\
+        bf30;\
+        bf31;\
+    };\
+R_BSP_PRAGMA(bitfields=default)\
+}
+
+#endif /* defined(__ICCRX__) */
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_1(bf0)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_2(bf0, bf1)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_3(bf0, bf1, bf2)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_4(bf0, bf1, bf2, bf3)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_5(bf0, bf1, bf2, bf3, bf4)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_6(bf0, bf1, bf2, bf3, bf4, bf5)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_7(bf0, bf1, bf2, bf3, bf4, bf5, bf6)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_8(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_9(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_10(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_11(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_12(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_13(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_14(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_15(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_16(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_17(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_18(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_19(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_20(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_21(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_22(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_23(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_24(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_25(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_26(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_27(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_28(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, bf27, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_29(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, bf27, bf28, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_30(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, bf27, bf28, bf29, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_31(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                                bf30)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, bf27, bf28, bf29, bf30, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_32(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                                bf30, bf31)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, bf27, bf28, bf29, bf30, bf31) \
+
+/* ---------- bit_order=right ---------- */
+#if defined(__CCRX__)
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                            bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                            bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                            bf30, bf31)\
+struct {\
+R_BSP_PRAGMA(bit_order right)\
+    struct {\
+        bf0;\
+        bf1;\
+        bf2;\
+        bf3;\
+        bf4;\
+        bf5;\
+        bf6;\
+        bf7;\
+        bf8;\
+        bf9;\
+        bf10;\
+        bf11;\
+        bf12;\
+        bf13;\
+        bf14;\
+        bf15;\
+        bf16;\
+        bf17;\
+        bf18;\
+        bf19;\
+        bf20;\
+        bf21;\
+        bf22;\
+        bf23;\
+        bf24;\
+        bf25;\
+        bf26;\
+        bf27;\
+        bf28;\
+        bf29;\
+        bf30;\
+        bf31;\
+    };\
+R_BSP_PRAGMA(bit_order)\
+}
+
+#elif defined(__GNUC__)
+
+#if defined(__LIT)
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                            bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                            bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                            bf30, bf31)\
+struct {\
+    bf0;\
+    bf1;\
+    bf2;\
+    bf3;\
+    bf4;\
+    bf5;\
+    bf6;\
+    bf7;\
+    bf8;\
+    bf9;\
+    bf10;\
+    bf11;\
+    bf12;\
+    bf13;\
+    bf14;\
+    bf15;\
+    bf16;\
+    bf17;\
+    bf18;\
+    bf19;\
+    bf20;\
+    bf21;\
+    bf22;\
+    bf23;\
+    bf24;\
+    bf25;\
+    bf26;\
+    bf27;\
+    bf28;\
+    bf29;\
+    bf30;\
+    bf31;\
+}
+
+#else /* defined(__LIT) */
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                            bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                            bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                            bf30, bf31)\
+struct {\
+    bf31;\
+    bf30;\
+    bf29;\
+    bf28;\
+    bf27;\
+    bf26;\
+    bf25;\
+    bf24;\
+    bf23;\
+    bf22;\
+    bf21;\
+    bf20;\
+    bf19;\
+    bf18;\
+    bf17;\
+    bf16;\
+    bf15;\
+    bf14;\
+    bf13;\
+    bf12;\
+    bf11;\
+    bf10;\
+    bf9;\
+    bf8;\
+    bf7;\
+    bf6;\
+    bf5;\
+    bf4;\
+    bf3;\
+    bf2;\
+    bf1;\
+    bf0;\
+}
+
+#endif /* defined(__LIT) */
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                            bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                            bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                            bf30, bf31)\
+struct {\
+R_BSP_PRAGMA(bitfields=disjoint_types)\
+    struct {\
+        bf0;\
+        bf1;\
+        bf2;\
+        bf3;\
+        bf4;\
+        bf5;\
+        bf6;\
+        bf7;\
+        bf8;\
+        bf9;\
+        bf10;\
+        bf11;\
+        bf12;\
+        bf13;\
+        bf14;\
+        bf15;\
+        bf16;\
+        bf17;\
+        bf18;\
+        bf19;\
+        bf20;\
+        bf21;\
+        bf22;\
+        bf23;\
+        bf24;\
+        bf25;\
+        bf26;\
+        bf27;\
+        bf28;\
+        bf29;\
+        bf30;\
+        bf31;\
+    };\
+R_BSP_PRAGMA(bitfields=default)\
+}
+
+#endif /* defined(__ICCRX__) */
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_1(bf0)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_2(bf0, bf1)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_3(bf0, bf1, bf2)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_4(bf0, bf1, bf2, bf3)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_5(bf0, bf1, bf2, bf3, bf4)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_6(bf0, bf1, bf2, bf3, bf4, bf5)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_7(bf0, bf1, bf2, bf3, bf4, bf5, bf6)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_8(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_9(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_10(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_11(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_12(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_13(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_14(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_15(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_16(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_17(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_18(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_19(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_20(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_21(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, uint8_t :0, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_22(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, uint8_t :0, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_23(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, uint8_t :0, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_24(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_25(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_26(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_27(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_28(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, bf27, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_29(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, bf27, bf28, uint8_t :0, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_30(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, bf27, bf28, bf29, uint8_t :0, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_31(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                                bf30)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, bf27, bf28, bf29, bf30, uint8_t :0) \
+
+#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_32(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \
+                                                bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \
+                                                bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \
+                                                bf30, bf31)\
+ R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \
+ bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \
+ bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \
+ bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \
+ bf24, bf25, bf26, bf27, bf28, bf29, bf30, bf31) \
+
+/* ---------- Alignment Value Specification for Structure Members and Class Members ---------- */
+#if defined(__CCRX__)
+
+#define R_BSP_PRAGMA_PACK          R_BSP_PRAGMA(pack)
+#define R_BSP_PRAGMA_UNPACK        R_BSP_PRAGMA(unpack)
+#define R_BSP_PRAGMA_PACKOPTION    R_BSP_PRAGMA(packoption)
+
+#elif defined(__GNUC__)
+
+#define R_BSP_PRAGMA_PACK          R_BSP_PRAGMA(pack(1))
+#define R_BSP_PRAGMA_UNPACK        R_BSP_PRAGMA(pack(4))
+#define R_BSP_PRAGMA_PACKOPTION    R_BSP_PRAGMA(pack())
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_PRAGMA_PACK          R_BSP_PRAGMA(pack(1))
+#define R_BSP_PRAGMA_UNPACK        R_BSP_PRAGMA(pack(4))
+#define R_BSP_PRAGMA_PACKOPTION    R_BSP_PRAGMA(pack())
+
+#endif
+
+/* ========== Rename Functions ========== */
+
+#if defined(__CCRX__)
+
+#define R_BSP_POR_FUNCTION(name)            extern void name(void)
+#define R_BSP_POWER_ON_RESET_FUNCTION       PowerON_Reset_PC
+#define R_BSP_STARTUP_FUNCTION              PowerON_Reset_PC
+
+#define R_BSP_UB_POR_FUNCTION(name)         extern void name(void)
+#define R_BSP_UB_POWER_ON_RESET_FUNCTION    PowerON_Reset_PC
+
+#define R_BSP_MAIN_FUNCTION                 main
+
+/* #define _INITSCT */
+/* #define excep_supervisor_inst_isr */
+/* #define excep_access_isr */
+/* #define excep_undefined_inst_isr */
+/* #define excep_floating_point_isr */
+/* #define non_maskable_isr */
+/* #define undefined_interrupt_source_isr */
+
+#elif defined(__GNUC__)
+
+#define R_BSP_POR_FUNCTION(name)            extern void name(void)
+#define R_BSP_POWER_ON_RESET_FUNCTION       PowerON_Reset_PC
+#define R_BSP_STARTUP_FUNCTION              PowerON_Reset_PC_Prg
+
+#define R_BSP_UB_POR_FUNCTION(name)         extern void name(void)
+#define R_BSP_UB_POWER_ON_RESET_FUNCTION    PowerON_Reset_PC
+
+#define R_BSP_MAIN_FUNCTION                 main
+
+/* #define _INITSCT */
+/* #define excep_supervisor_inst_isr */
+/* #define excep_access_isr */
+/* #define excep_undefined_inst_isr */
+/* #define excep_floating_point_isr */
+/* #define non_maskable_isr */
+/* #define undefined_interrupt_source_isr */
+
+#elif defined(__ICCRX__)
+
+#define R_BSP_POR_FUNCTION(name)            extern int name(void)
+#define R_BSP_POWER_ON_RESET_FUNCTION       _iar_program_start
+#define R_BSP_STARTUP_FUNCTION              __low_level_init
+
+#define R_BSP_UB_POR_FUNCTION(name)         extern int name(void)
+#define R_BSP_UB_POWER_ON_RESET_FUNCTION    _iar_program_start
+
+#define R_BSP_MAIN_FUNCTION                 _iar_main_call
+
+#define _INITSCT                            __iar_data_init2
+#define excep_supervisor_inst_isr           __privileged_handler
+#define excep_access_isr                    __excep_access_inst
+#define excep_undefined_inst_isr            __undefined_handler
+#define excep_floating_point_isr            _float_placeholder
+#define non_maskable_isr                    __NMI_handler
+#define undefined_interrupt_source_isr      __undefined_interrupt_source_handler
+
+#endif
+
+#endif /* R_RX_COMPILER_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c
new file mode 100644
index 00000000..d344aed0
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c
@@ -0,0 +1,994 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_rx_intrinsic_functions.c
+* Description  : Defines built-in functions that are in CCRX but not in the GCC and IAR compiler.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+*         : 26.07.2019 1.01     Fixed the below functions.
+*                               - R_BSP_MulAndAccOperation_2byte
+*                               - R_BSP_MulAndAccOperation_FixedPoint1
+*                               - R_BSP_MulAndAccOperation_FixedPoint2
+*                               Added the below functions.
+*                               - R_BSP_CalcSine_Cosine
+*                               - R_BSP_CalcAtan_SquareRoot
+*         : 31.07.2019 1.02     Modified the compile condition of the below functions.
+*                               - R_BSP_InitTFU
+*                               - R_BSP_CalcSine_Cosine
+*                               - R_BSP_CalcAtan_SquareRoot
+*         : 10.12.2019 1.03     Fixed the below functions.
+*                               - R_BSP_MulAndAccOperation_2byte
+*                               - R_BSP_MulAndAccOperation_FixedPoint1
+*                               - R_BSP_MulAndAccOperation_FixedPoint2
+*         : 17.12.2019 1.04     Modified the comment of description.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_rx_compiler.h"
+#include "r_rx_intrinsic_functions.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_bpsw(uint32_t *data);
+R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_bpc(uint32_t *data);
+#ifdef BSP_MCU_EXCEPTION_TABLE
+R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_extb(uint32_t *data);
+#endif /* BSP_MCU_EXCEPTION_TABLE */
+R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_move_from_acc_hi_long(uint32_t *data);
+R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_move_from_acc_mi_long(uint32_t *data);
+#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT
+#ifdef __DPFPU
+R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_dpsw(uint32_t *data);
+R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_decnt(uint32_t *data);
+R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_depc(uint32_t *ret);
+#endif
+#endif
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_Max
+* Description  : Selects the greater of two input values.
+* Arguments    : data1 - Input value 1.
+*                data2 - Input value 2.
+* Return Value : The greater value of data1 and data2.
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+signed long R_BSP_Max(signed long data1, signed long data2)
+{
+    return (data1 > data2)? data1 : data2;
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_Min
+* Description  : Selects the smaller of two input values.
+* Arguments    : data1 - Input value 1.
+*                data2 - Input value 2.
+* Return Value : The smaller value of data1 and data2.
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+signed long R_BSP_Min(signed long data1, signed long data2)
+{
+    return (data1 < data2)? data1 : data2;
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_MulAndAccOperation_B
+* Description  : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of 
+*                multiply-and-accumulate operations specified by count, and the start addresses of values to be 
+*                multiplied specified by addr1 and addr2.
+* Arguments    : init   - Initial value.
+*                count  - Count of multiply-and-accumulate operations.
+*                *addr1 - Start address of values 1 to be multiplied.
+*                *addr2 - Start address of values 2 to be multiplied.
+* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1)
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2)
+{
+    long long result = init;
+    unsigned long index;
+    for(index = 0; index < count; index++)
+    {
+        result += addr1[index] * addr2[index];
+    }
+    return result;
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_MulAndAccOperation_W
+* Description  : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of
+*                multiply-and-accumulate operations specified by count, and the start addresses of values to be 
+*                multiplied specified by addr1 and addr2.
+* Arguments    : init   - Initial value.
+*                count  - Count of multiply-and-accumulate operations.
+*                *addr1 - Start address of values 1 to be multiplied.
+*                *addr2 - Start address of values 2 to be multiplied.
+* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1)
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2)
+{
+    long long result = init;
+    unsigned long index;
+    for(index = 0; index < count; index++)
+    {
+        result += addr1[index] * addr2[index];
+    }
+    return result;
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_MulAndAccOperation_L
+* Description  : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of
+*                multiply-and-accumulate operations specified by count, and the start addresses of values to be 
+*                multiplied specified by addr1 and addr2.
+* Arguments    : init   - Initial value.
+*                count  - Count of multiply-and-accumulate operations.
+*                *addr1 - Start address of values 1 to be multiplied.
+*                *addr2 - Start address of values 2 to be multiplied.
+* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1)
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2)
+{
+    long long result = init;
+    unsigned long index;
+    for(index = 0; index < count; index++)
+    {
+        result += addr1[index] * addr2[index];
+    }
+    return result;
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_RotateLeftWithCarry
+* Description  : Rotates data including the C flag to left by one bit. 
+*                The bit pushed out of the operand is set to the C flag.
+* Arguments    : data - Data to be rotated to left.
+* Return Value : data - Result of 1-bit left rotation of data including the C flag.
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+unsigned long R_BSP_RotateLeftWithCarry(unsigned long data)
+{
+    __asm("rolc %0":"=r"(data) : "r"(data):); 
+    return data;
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_RotateRightWithCarry
+* Description  : Rotates data including the C flag to right by one bit.
+*                The bit pushed out of the operand is set to the C flag.
+* Arguments    : data - Data to be rotated to right.
+* Return Value : data - Result of 1-bit right rotation of data including the C flag.
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+unsigned long R_BSP_RotateRightWithCarry(unsigned long data)
+{
+    __asm("rorc %0":"=r"(data) : "r"(data):);
+    return data;
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_RotateLeft
+* Description  : Rotates data to left by the specified number of bits.
+*                The bit pushed out of the operand is set to the C flag.
+* Arguments    : data - Data to be rotated to left.
+*                num - Number of bits to be rotated.
+* Return Value : data - Result of num-bit left rotation of data.
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num)
+{
+    __asm("rotl %1, %0":"=r"(data) : "r"(num),"0"(data) :); 
+    return data;
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_RotateRight
+* Description  : Rotates data to right by the specified number of bits.
+*                The bit pushed out of the operand is set to the C flag.
+* Arguments    : data - Data to be rotated to right.
+*                num - Number of bits to be rotated.
+* Return Value : result - Result of num-bit right rotation of data.
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+unsigned long R_BSP_RotateRight(unsigned long data, unsigned long num)
+{
+    __asm("rotr %1, %0":"=r"(data) : "r"(num),"0"(data) :); 
+    return data;
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_SignedMultiplication
+* Description  : Performs signed multiplication of significant 64 bits.
+* Arguments    : data 1 - Input value 1.
+*                data 2 - Input value 2.
+* Return Value : Result of signed multiplication. (signed 64-bit value)
+***********************************************************************************************************************/
+#if defined(__GNUC__) || defined(__ICCRX__)
+signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2)
+{
+    return ((signed long long)data1) * ((signed long long)data2);
+}
+#endif /* defined(__GNUC__) || defined(__ICCRX__)  */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_UnsignedMultiplication
+* Description  : Performs unsigned multiplication of significant 64 bits.
+* Arguments    : data 1 - Input value 1.
+*                data 2 - Input value 2.
+* Return Value : Result of unsigned multiplication. (unsigned 64-bit value)
+***********************************************************************************************************************/
+#if defined(__GNUC__) || defined(__ICCRX__)
+unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2)
+{
+    return ((unsigned long long)data1) * ((unsigned long long)data2);
+}
+#endif /* defined(__GNUC__) || defined(__ICCRX__)  */
+
+/***********************************************************************************************************************
+* Function name: R_BSP_ChangeToUserMode
+* Description  : Switches to user mode. The PSW will be changed as following.
+*                Before Execution                                       After Execution
+*                PSW.PM                 PSW.U                           PSW.PM              PSW.U
+*                0 (supervisor mode)    0 (interrupt stack)     -->     1 (user mode)       1 (user stack)
+*                0 (supervisor mode)    1 (user stack)          -->     1 (user mode)       1 (user stack)
+*                1 (user mode)          1 (user stack)          -->     NO CHANGE
+*                1 (user mode)          0 (interrupt stack))    <==     N/A
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_ChangeToUserMode)
+void R_BSP_ChangeToUserMode(void)
+{
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(;_R_BSP_Change_PSW_PM_to_UserMode:                                                                   )
+    R_BSP_ASM(    PUSH.L  R1          ; push the R1 value                                                          )
+    R_BSP_ASM(    MVFC    PSW, R1     ; get the current PSW value                                                  )
+    R_BSP_ASM(    BTST    #20, R1     ; check PSW.PM                                                               )
+    R_BSP_ASM(    BNE.B   R_BSP_ASM_LAB_NEXT(0);_psw_pm_is_user_mode                                               )
+    R_BSP_ASM(;_psw_pm_is_supervisor_mode:                                                                         )
+    R_BSP_ASM(    BSET    #20, R1     ; change PM = 0(Supervisor Mode) --> 1(User Mode)                            )
+    R_BSP_ASM(    PUSH.L  R2          ; push the R2 value                                                          )
+    R_BSP_ASM(    MOV.L   R0, R2      ; move the current SP value to the R2 value                                  )
+    R_BSP_ASM(    XCHG    8[R2].L, R1 ; exchange the value of R2 destination address and the R1 value              )
+    R_BSP_ASM(                        ; (exchange the return address value of caller and the PSW value)            )
+    R_BSP_ASM(    XCHG    4[R2].L, R1 ; exchange the value of R2 destination address and the R1 value              )
+    R_BSP_ASM(                        ; (exchange the R1 value of stack and the return address value of caller)    )
+    R_BSP_ASM(    POP     R2          ; pop the R2 value of stack                                                  )
+    R_BSP_ASM(    RTE                                                                                              )
+    R_BSP_ASM_LAB(0:;_psw_pm_is_user_mode:                                                                         )
+    R_BSP_ASM(    POP     R1          ; pop the R1 value of stack                                                  )
+    R_BSP_ASM(    ;RTS                                                                                             )
+    R_BSP_ASM_END
+} /* End of function R_BSP_ChangeToUserMode() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_SetACC
+* Description  : Sets a value to ACC.
+* Arguments    : data - Value to be set to ACC.
+* Return Value : none
+***********************************************************************************************************************/
+#if defined(__GNUC__) || defined(__ICCRX__)
+void R_BSP_SetACC(signed long long data)
+{
+#if defined(__GNUC__)
+    __builtin_rx_mvtachi(data >> 32);
+    __builtin_rx_mvtaclo(data & 0xFFFFFFFF);
+#elif defined(__ICCRX__)
+    int32_t data_hi;
+    int32_t data_lo;
+
+    data_hi = (int32_t)(data >> 32);
+    data_lo = (int32_t)(data & 0x00000000FFFFFFFF);
+
+    R_BSP_MoveToAccHiLong(data_hi);
+    R_BSP_MoveToAccLoLong(data_lo);
+#endif /* defined(__GNUC__) || defined(__ICCRX__)  */
+}
+#endif /* defined(__GNUC__) || defined(__ICCRX__)  */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_GetACC
+* Description  : Refers to the ACC value.
+* Arguments    : none
+* Return Value : result - ACC value.
+***********************************************************************************************************************/
+#if defined(__GNUC__) || defined(__ICCRX__)
+signed long long R_BSP_GetACC(void)
+{
+#if defined(__GNUC__)
+    signed long long result = ((signed long long)__builtin_rx_mvfachi()) << 32;
+    result |= (((signed long long)__builtin_rx_mvfacmi()) << 16) & 0xFFFF0000;
+    return result;
+#elif defined(__ICCRX__)
+    int64_t result;
+
+    result = ((int64_t)R_BSP_MoveFromAccHiLong()) << 32;
+    result |= (((int64_t)R_BSP_MoveFromAccMiLong()) << 16) & 0xFFFF0000;
+
+    return result;
+#endif /* defined(__GNUC__) || defined(__ICCRX__)  */
+}
+#endif /* defined(__GNUC__) || defined(__ICCRX__)  */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_MulAndAccOperation_2byte
+* Description  : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as
+*                four bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, 
+*                MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as
+*                48-bit data. After all multiply-and-accumulate operations have finished, the contents of ACC are 
+*                fetched by the MVFACMI instruction and used as the return value of the intrinsic function.
+* Arguments    : data1 - Start address of values 1 to be multiplied.
+*                data2 - Start address of values 2 to be multiplied.
+*                count - Count of multiply-and-accumulate operations.
+* Return Value : S(data1[n] * data2[n]) result.
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+long R_BSP_MulAndAccOperation_2byte(short* data1, short* data2, unsigned long count)
+{
+    register signed long *ldata1 = (signed long *)data1;
+    register signed long *ldata2 = (signed long *)data2;
+    /* this is much more then an "intrinsic", no inline asm because of loop */
+    /* will implement this.. interesting function as described in ccrx manual */
+    __builtin_rx_mullo(0, 0);
+    while (count > 1)
+    {
+        __builtin_rx_maclo(*ldata1, *ldata2);
+        __builtin_rx_machi(*ldata1, *ldata2);
+        ldata1++;
+        ldata2++;
+        count -= 2;
+    }
+    if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2);
+    return __builtin_rx_mvfacmi();
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_MulAndAccOperation_FixedPoint1
+* Description  : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as
+*                two bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, 
+*                MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as
+*                48-bit data. After all multiply-and-accumulate operations have finished, rounding is applied to the 
+*                multiply-and-accumulate operation result of ACC.
+*                The macw1 function performs rounding with the "RACW #1" instruction.
+* Arguments    : data1 - Start address of values 1 to be multiplied.
+*                data2 - Start address of values 2 to be multiplied.
+*                count - Count of multiply-and-accumulate operations.
+* Return Value : Value obtained by rounding the multiply-and-accumulate operation result with the RACW instruction.
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+short R_BSP_MulAndAccOperation_FixedPoint1(short* data1, short* data2, unsigned long count)
+{
+    register signed long *ldata1 = (signed long *)data1;
+    register signed long *ldata2 = (signed long *)data2;
+    /* this is much more then an "intrinsic", no inline asm because of loop */
+    /* will implement this.. interesting function as described in ccrx manual */
+    __builtin_rx_mullo(0, 0);
+    while (count > 1)
+    {
+        __builtin_rx_maclo(*ldata1, *ldata2);
+        __builtin_rx_machi(*ldata1, *ldata2);
+        ldata1++;
+        ldata2++;
+        count -= 2;
+    }
+    if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2);
+    __builtin_rx_racw(1);
+    return __builtin_rx_mvfachi();
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_MulAndAccOperation_FixedPoint2
+* Description  : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as
+*                two bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, 
+*                MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as
+*                48-bit data. After all multiply-and-accumulate operations have finished, rounding is applied to the 
+*                multiply-and-accumulate operation result of ACC.
+*                the macw2 function performs rounding with the "RACW #2" instruction.
+* Arguments    : data1 - Start address of values 1 to be multiplied.
+*                data2 - Start address of values 2 to be multiplied.
+*                count - Count of multiply-and-accumulate operations.
+* Return Value : Value obtained by rounding the multiply-and-accumulate operation result with the RACW instruction.
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+short R_BSP_MulAndAccOperation_FixedPoint2(short* data1, short* data2, unsigned long count)
+{
+    register signed long *ldata1 = (signed long *)data1;
+    register signed long *ldata2 = (signed long *)data2;
+    /* this is much more then an "intrinsic", no inline asm because of loop */
+    /* will implement this.. interesting function as described in ccrx manual */
+    __builtin_rx_mullo(0, 0);
+    while (count > 1)
+    {
+        __builtin_rx_maclo(*ldata1, *ldata2);
+        __builtin_rx_machi(*ldata1, *ldata2);
+        ldata1++;
+        ldata2++;
+        count -= 2;
+    }
+    if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2);
+    __builtin_rx_racw(2);
+    return __builtin_rx_mvfachi();
+}
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_SetBPSW
+* Description  : Sets a value to BPSW.
+* Arguments    : data - Value to be set.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetBPSW)
+void R_BSP_SetBPSW(uint32_t data)
+{
+    R_BSP_ASM_INTERNAL_USED(data)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    MVTC    R1, BPSW    )
+    R_BSP_ASM_END
+} /* End of function R_BSP_SetBPSW() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_get_bpsw
+* Description  : Refers to the BPSW value.
+* Arguments    : ret - Return value address.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_bpsw)
+void bsp_get_bpsw(uint32_t *ret)
+{
+    R_BSP_ASM_INTERNAL_USED(ret)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSH.L     R2           )
+    R_BSP_ASM(    MVFC       BPSW, R2     )
+    R_BSP_ASM(    MOV.L      R2, [R1]     )
+    R_BSP_ASM(    POP        R2           )
+    R_BSP_ASM_END
+} /* End of function bsp_get_bpsw() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_GetBPSW
+* Description  : Refers to the BPSW value.
+* Arguments    : none
+* Return Value : BPSW value.
+* Note         : This function exists to avoid code analysis errors. Because, when inline assembler function has
+*                a return value, the error of "No return, in function returning non-void" occurs.
+***********************************************************************************************************************/
+uint32_t R_BSP_GetBPSW(void)
+{
+    uint32_t ret;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    bsp_get_bpsw((uint32_t *)&ret);
+    return ret;
+} /* End of function R_BSP_GetBPSW() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_SetBPC
+* Description  : Sets a value to BPC.
+* Arguments    : data - Value to be set.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetBPC)
+void R_BSP_SetBPC(void *data)
+{
+    R_BSP_ASM_INTERNAL_USED(data)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    MVTC    R1, BPC    )
+    R_BSP_ASM_END
+} /* End of function R_BSP_SetBPC() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_get_bpc
+* Description  : Refers to the BPC value.
+* Arguments    : ret - Return value address.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_bpc)
+void bsp_get_bpc(uint32_t *ret)
+{
+    R_BSP_ASM_INTERNAL_USED(ret)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSH.L     R2           )
+    R_BSP_ASM(    MVFC       BPC, R2      )
+    R_BSP_ASM(    MOV.L      R2, [R1]     )
+    R_BSP_ASM(    POP        R2           )
+    R_BSP_ASM_END
+} /* End of function bsp_get_bpc() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_GetBPC
+* Description  : Refers to the BPC value.
+* Arguments    : none
+* Return Value : BPC value
+* Note         : This function exists to avoid code analysis errors. Because, when inline assembler function has
+*                a return value, the error of "No return, in function returning non-void" occurs.
+***********************************************************************************************************************/
+void *R_BSP_GetBPC(void)
+{
+    uint32_t ret;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    bsp_get_bpc((uint32_t *)&ret);
+
+    /* Casting is valid because it matches the type to the right side or return. */
+    return (void *)ret;
+} /* End of function R_BSP_GetBPC() */
+
+#ifdef BSP_MCU_EXCEPTION_TABLE
+/***********************************************************************************************************************
+* Function Name: R_BSP_SetEXTB
+* Description  : Sets a value for EXTB.
+* Arguments    : data - Value to be set.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetEXTB)
+void R_BSP_SetEXTB(void *data)
+{
+    R_BSP_ASM_INTERNAL_USED(data)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    MVTC    R1, EXTB    )
+    R_BSP_ASM_END
+} /* End of function R_BSP_SetEXTB() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_get_extb
+* Description  : Refers to the EXTB value.
+* Arguments    : ret - Return value address.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_extb)
+void bsp_get_extb(uint32_t *ret)
+{
+    R_BSP_ASM_INTERNAL_USED(ret)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSH.L     R2           )
+    R_BSP_ASM(    MVFC       EXTB, R2     )
+    R_BSP_ASM(    MOV.L      R2, [R1]     )
+    R_BSP_ASM(    POP        R2           )
+    R_BSP_ASM_END
+} /* End of function bsp_get_extb() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_GetEXTB
+* Description  : Refers to the EXTB value.
+* Arguments    : none
+* Return Value : EXTB value.
+* Note         : This function exists to avoid code analysis errors. Because, when inline assembler function has
+*                a return value, the error of "No return, in function returning non-void" occurs.
+***********************************************************************************************************************/
+void *R_BSP_GetEXTB(void)
+{
+    uint32_t ret;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    bsp_get_extb((uint32_t *)&ret);
+
+    /* Casting is valid because it matches the type to the right side or return. */
+    return (void *)ret;
+} /* End of function R_BSP_GetEXTB() */
+#endif /* BSP_MCU_EXCEPTION_TABLE */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_MoveToAccHiLong
+* Description  : This function moves the contents of src to the higher-order 32 bits of the accumulator.
+* Arguments    : data - Input value.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_MoveToAccHiLong)
+void R_BSP_MoveToAccHiLong(int32_t data)
+{
+    R_BSP_ASM_INTERNAL_USED(data)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    MVTACHI    R1    )
+    R_BSP_ASM_END
+} /* End of function R_BSP_MoveToAccHiLong() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_MoveToAccLoLong
+* Description  : This function moves the contents of src to the lower-order 32 bits of the accumulator.
+* Arguments    : data - Input value.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_MoveToAccLoLong)
+void R_BSP_MoveToAccLoLong(int32_t data)
+{
+    R_BSP_ASM_INTERNAL_USED(data)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    MVTACLO    R1    )
+    R_BSP_ASM_END
+} /* End of function R_BSP_MoveToAccLoLong() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_move_from_acc_hi_long
+* Description  : This function moves the higher-order 32 bits of the accumulator to dest.
+* Arguments    : ret - Return value address.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_move_from_acc_hi_long)
+void bsp_move_from_acc_hi_long(uint32_t *ret)
+{
+    R_BSP_ASM_INTERNAL_USED(ret)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSH.L     R2           )
+    R_BSP_ASM(    MVFACHI    R2           )
+    R_BSP_ASM(    MOV.L      R2, [R1]     )
+    R_BSP_ASM(    POP        R2           )
+    R_BSP_ASM_END
+} /* End of function bsp_move_from_acc_hi_long() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_MoveFromAccHiLong
+* Description  : This function moves the higher-order 32 bits of the accumulator to dest.
+* Arguments    : none
+* Return Value : The higher-order 32 bits of the accumulator.
+* Note         : This function exists to avoid code analysis errors. Because, when inline assembler function has
+*                a return value, the error of "No return, in function returning non-void" occurs.
+***********************************************************************************************************************/
+int32_t R_BSP_MoveFromAccHiLong(void)
+{
+    int32_t ret;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    bsp_move_from_acc_hi_long((uint32_t *)&ret);
+    return ret;
+} /* End of function R_BSP_MoveFromAccHiLong() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_move_from_acc_mi_long
+* Description  : This function moves the contents of bits 47 to 16 of the accumulator to dest.
+* Arguments    : ret - Return value address.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_move_from_acc_mi_long)
+void bsp_move_from_acc_mi_long(uint32_t *ret)
+{
+    R_BSP_ASM_INTERNAL_USED(ret)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSH.L     R2           )
+    R_BSP_ASM(    MVFACMI    R2           )
+    R_BSP_ASM(    MOV.L      R2, [R1]     )
+    R_BSP_ASM(    POP        R2           )
+    R_BSP_ASM_END
+} /* End of function bsp_move_from_acc_mi_long() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_MoveFromAccMiLong
+* Description  : This function moves the contents of bits 47 to 16 of the accumulator to dest.
+* Arguments    : none
+* Return Value : The contents of bits 47 to 16 of the accumulator.
+* Note         : This function exists to avoid code analysis errors. Because, when inline assembler function has
+*                a return value, the error of "No return, in function returning non-void" occurs.
+***********************************************************************************************************************/
+int32_t R_BSP_MoveFromAccMiLong(void)
+{
+    int32_t ret;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    bsp_move_from_acc_mi_long((uint32_t *)&ret);
+    return ret;
+} /* End of function R_BSP_MoveFromAccMiLong() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_BitSet
+* Description  : Sets the specified one bit in the specified 1-byte area to 1.
+* Arguments    : data - Address of the target 1-byte area
+*                bit  - Position of the bit to be manipulated
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitSet)
+void R_BSP_BitSet(uint8_t *data, uint32_t bit)
+{
+    R_BSP_ASM_INTERNAL_USED(data)
+    R_BSP_ASM_INTERNAL_USED(bit)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    BSET    R2, [R1]    )
+    R_BSP_ASM_END
+} /* End of function R_BSP_BitSet() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_BitClear
+* Description  : Sets the specified one bit in the specified 1-byte area to 0.
+* Arguments    : data - Address of the target 1-byte area
+*                bit  - Position of the bit to be manipulated
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitClear)
+void R_BSP_BitClear(uint8_t *data, uint32_t bit)
+{
+    R_BSP_ASM_INTERNAL_USED(data)
+    R_BSP_ASM_INTERNAL_USED(bit)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    BCLR    R2, [R1]    )
+    R_BSP_ASM_END
+} /* End of function R_BSP_BitClear() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_BitReverse
+* Description  : Reverses the value of the specified one bit in the specified 1-byte area.
+* Arguments    : data - Address of the target 1-byte area
+*                bit  - Position of the bit to be manipulated
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitReverse)
+void R_BSP_BitReverse(uint8_t *data, uint32_t bit)
+{
+    R_BSP_ASM_INTERNAL_USED(data)
+    R_BSP_ASM_INTERNAL_USED(bit)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    BNOT    R2, [R1]    )
+    R_BSP_ASM_END
+} /* End of function R_BSP_BitReverse() */
+
+#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT
+#ifdef __DPFPU
+/***********************************************************************************************************************
+* Function Name: R_BSP_SetDPSW
+* Description  : Sets a value to DPSW.
+* Arguments    : data - Value to be set.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetDPSW)
+void R_BSP_SetDPSW(uint32_t data)
+{
+    R_BSP_ASM_INTERNAL_USED(data)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    MVTDC   R1, DPSW    )
+    R_BSP_ASM_END
+} /* End of function R_BSP_SetDPSW() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_get_dpsw
+* Description  : Refers to the DPSW value.
+* Arguments    : ret - Return value address.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_dpsw)
+void bsp_get_dpsw(uint32_t *ret)
+{
+    R_BSP_ASM_INTERNAL_USED(ret)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSH.L     R2           )
+    R_BSP_ASM(    MVFDC      DPSW, R2     )
+    R_BSP_ASM(    MOV.L      R2, [R1]     )
+    R_BSP_ASM(    POP        R2           )
+    R_BSP_ASM_END
+} /* End of function bsp_get_dpsw() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_GetDPSW
+* Description  : Refers to the DPSW value.
+* Arguments    : none
+* Return Value : DPSW value.
+* Note         : This function exists to avoid code analysis errors. Because, when inline assembler function has
+*                a return value, the error of "No return, in function returning non-void" occurs.
+***********************************************************************************************************************/
+uint32_t R_BSP_GetDPSW(void)
+{
+    uint32_t ret;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    bsp_get_dpsw((uint32_t *)&ret);
+    return ret;
+} /* End of function R_BSP_GetDPSW() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_SetDECNT
+* Description  : Sets a value to DECNT.
+* Arguments    : data - Value to be set.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetDECNT)
+void R_BSP_SetDECNT(uint32_t data)
+{
+    R_BSP_ASM_INTERNAL_USED(data)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    MVTDC   R1, DECNT    )
+    R_BSP_ASM_END
+} /* End of function R_BSP_SetDECNT() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_get_decnt
+* Description  : Refers to the DECNT value.
+* Arguments    : ret - Return value address.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_decnt)
+void bsp_get_decnt(uint32_t *ret)
+{
+    R_BSP_ASM_INTERNAL_USED(ret)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSH.L     R2           )
+    R_BSP_ASM(    MVFDC      DECNT, R2    )
+    R_BSP_ASM(    MOV.L      R2, [R1]     )
+    R_BSP_ASM(    POP        R2           )
+    R_BSP_ASM_END
+} /* End of function bsp_get_decnt() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_GetDECNT
+* Description  : Refers to the DECNT value.
+* Arguments    : none
+* Return Value : DECNT value.
+* Note         : This function exists to avoid code analysis errors. Because, when inline assembler function has
+*                a return value, the error of "No return, in function returning non-void" occurs.
+***********************************************************************************************************************/
+uint32_t R_BSP_GetDECNT(void)
+{
+    uint32_t ret;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    bsp_get_decnt((uint32_t *)&ret);
+    return ret;
+} /* End of function R_BSP_GetDECNT() */
+
+/***********************************************************************************************************************
+* Function Name: bsp_get_depc
+* Description  : Refers to the DEPC value.
+* Arguments    : ret - Return value address.
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_depc)
+void bsp_get_depc(uint32_t *ret)
+{
+    R_BSP_ASM_INTERNAL_USED(ret)
+
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSH.L     R2           )
+    R_BSP_ASM(    MVFDC      DEPC, R2     )
+    R_BSP_ASM(    MOV.L      R2, [R1]     )
+    R_BSP_ASM(    POP        R2           )
+    R_BSP_ASM_END
+} /* End of function bsp_get_decnt() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_GetDEPC
+* Description  : Refers to the DEPC value.
+* Arguments    : none
+* Return Value : DEPC value.
+* Note         : This function exists to avoid code analysis errors. Because, when inline assembler function has
+*                a return value, the error of "No return, in function returning non-void" occurs.
+***********************************************************************************************************************/
+void *R_BSP_GetDEPC(void)
+{
+    uint32_t ret;
+
+    /* Casting is valid because it matches the type to the right side or argument. */
+    bsp_get_depc((uint32_t *)&ret);
+    return (void *)ret;
+} /* End of function R_BSP_GetDECNT() */
+#endif /* __DPFPU */
+#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */
+
+#ifdef BSP_MCU_TRIGONOMETRIC
+#ifdef __TFU
+/***********************************************************************************************************************
+* Function Name: R_BSP_InitTFU
+* Description  : Initialize arithmetic unit for trigonometric functions.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_InitTFU)
+void R_BSP_InitTFU(void)
+{
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSH.L    R1             )
+    R_BSP_ASM(    MOV.L     #81400H, R1    )
+    R_BSP_ASM(    MOV.B     #7, [R1]       )
+    R_BSP_ASM(    MOV.B     #7, 1[R1]      )
+    R_BSP_ASM(    POP       R1             )
+    R_BSP_ASM_END
+} /* End of function R_BSP_InitTFU() */
+
+#ifdef __FPU
+/***********************************************************************************************************************
+* Function Name: R_BSP_CalcSine_Cosine
+* Description  : Uses the trigonometric function unit to calculate the sine and cosine of an angle at the same time
+*                (single precision).
+* Arguments    : f - Value in radians from which to calculate the sine and cosine
+*              : sin - Address for storing the result of the sine operation
+*              : cos - Address for storing the result of the cosine operation
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcSine_Cosine)
+void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos)
+{
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSH.L    R4             )
+    R_BSP_ASM(    MOV.L     #81410H, R4    )
+    R_BSP_ASM(    MOV.L     R1, 4[R4]      )
+    R_BSP_ASM(    MOV.L     4[R4], [R2]    )
+    R_BSP_ASM(    MOV.L     [R4], [R3]     )
+    R_BSP_ASM(    POP       R4             )
+    R_BSP_ASM_END
+} /* End of function R_BSP_CalcSine_Cosine() */
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_CalcAtan_SquareRoot
+* Description  : Uses the trigonometric function unit to calculate the arc tangent of x and y and the square root of 
+*                the sum of squares of these values at the same time (single precision).
+* Arguments    : y - Coordinate y (the numerator of the tangent)
+*                x - Coordinate x (the denominator of the tangent)
+*                atan2 - Address for storing the result of the arc tangent operation for y/x
+*                hypot - Address for storing the result of the square root of the sum of squares of x and y
+* Return Value : none
+***********************************************************************************************************************/
+R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcAtan_SquareRoot)
+void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot)
+{
+    R_BSP_ASM_BEGIN
+    R_BSP_ASM(    PUSHM     R5-R6              )
+    R_BSP_ASM(    MOV.L     #81418H, R5        )
+    R_BSP_ASM(    MOV.L     R2, [R5]           )
+    R_BSP_ASM(    MOV.L     R1, 4[R5]          )
+    R_BSP_ASM(    MOV.L     4[R5], [R3]        )
+    R_BSP_ASM(    MOV.L     [R5], R6           )
+    R_BSP_ASM(    FMUL      #3F1B74EEH, R6     )
+    R_BSP_ASM(    MOV.L     R6, [R4]           )
+    R_BSP_ASM(    POPM      R5-R6              )
+    R_BSP_ASM_END
+} /* End of function R_BSP_CalcAtan_SquareRoot() */
+#endif /* __FPU */
+#endif /* __TFU */
+#endif /* BSP_MCU_TRIGONOMETRIC */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h
new file mode 100644
index 00000000..1f418eaa
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h
@@ -0,0 +1,822 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_rx_intrinsic_functions.h
+* Description  : This is a file for integrating the definitions of built-in functions that differ for each compilers.
+*                Replace different functions for each compiler.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+*         : 26.07.2019 1.10     Added the following function.
+*                               - R_BSP_SINCOSF
+*                               - R_BSP_ATAN2HYPOTF
+*                               - R_BSP_CalcSine_Cosine
+*                               - R_BSP_CalcAtan_SquareRoot
+*         : 31.07.2019 1.11     Modified the compile condition of the below functions.
+*                               - R_BSP_InitTFU
+*                               - R_BSP_CalcSine_Cosine
+*                               - R_BSP_CalcAtan_SquareRoot
+*         : 08.10.2019 1.12     Modified the followind definition of intrinsic function of TFU for ICCRX.
+*                               - R_BSP_INIT_TFU
+*                               - R_BSP_SINCOSF
+*                               - R_BSP_ATAN2HYPOTF
+*         : 17.12.2019 1.13     Modified the comment of description.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef R_RX_INTRINSIC_FUNCTIONS_H
+#define R_RX_INTRINSIC_FUNCTIONS_H
+
+/* ---------- Maximum value and minimum value ---------- */
+#if defined(__CCRX__)
+
+/* signed long max(signed long data1, signed long data2) */
+#define R_BSP_MAX(x, y)    max((signed long)(x), (signed long)(y))
+/* signed long min(signed long data1, signed long data2) */
+#define R_BSP_MIN(x, y)    min((signed long)(x), (signed long)(y))
+
+#elif defined(__GNUC__)
+
+/* signed long R_BSP_Max(signed long data1, signed long data2) (This macro uses API function of BSP.) */
+#define R_BSP_MAX(x, y)    R_BSP_Max((signed long)(x), (signed long)(y))
+/* signed long R_BSP_Min(signed long data1, signed long data2) (This macro uses API function of BSP.) */
+#define R_BSP_MIN(x, y)    R_BSP_Min((signed long)(x), (signed long)(y))
+
+#elif defined(__ICCRX__)
+
+/* signed long   __MAX(signed long, signed long) */
+#define R_BSP_MAX(x, y)    __MAX((signed long)(x), (signed long)(y))
+/* signed long   __MIN(signed long, signed long) */
+#define R_BSP_MIN(x, y)    __MIN((signed long)(x), (signed long)(y))
+
+#endif
+
+/* ---------- Byte switch ---------- */
+#if defined(__CCRX__)
+
+/* unsigned long revl(unsigned long data) */
+#define R_BSP_REVL(x)    revl((unsigned long)(x))
+/* unsigned long revw(unsigned long data) */
+#define R_BSP_REVW(x)    revw((unsigned long)(x))
+
+#elif defined(__GNUC__)
+
+/* uint32_t __builtin_bswap32(uint32_t x) */
+#define R_BSP_REVL(x)    __builtin_bswap32((uint32_t)(x))
+/* int __builtin_rx_revw(int) */
+#define R_BSP_REVW(x)    (unsigned long)__builtin_rx_revw((int)(x))
+
+#elif defined(__ICCRX__)
+
+/* unsigned long __REVL(unsigned long) */
+#define R_BSP_REVL(x)    __REVL((unsigned long)(x))
+/* unsigned long __REVW(unsigned long) */
+#define R_BSP_REVW(x)    __REVW((unsigned long)(x))
+
+#endif
+
+/* ---------- Data Exchange ---------- */
+#if defined(__CCRX__)
+
+/* void xchg(signed long *data1, signed long *data2) */
+#define R_BSP_EXCHANGE(x, y)    xchg((signed long *)(x), (signed long *)(y))
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_xchg (int *, int *) */
+#define R_BSP_EXCHANGE(x, y)    __builtin_rx_xchg((int *)(x), (int *)(y))
+
+#elif defined(__ICCRX__)
+
+/* void _builtin_xchg(signed long *, signed long *) */
+#define R_BSP_EXCHANGE(x, y)    _builtin_xchg((signed long *)(x), (signed long *)(y))
+
+#endif
+
+/* ---------- Multiply-and-accumulate operation ---------- */
+#if defined(__CCRX__)
+
+/* long long rmpab(long long init, unsigned long count, signed char *addr1, signed char *addr2) */
+#define R_BSP_RMPAB(w, x, y, z)    rmpab((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z))
+/* long long rmpaw(long long init, unsigned long count, short *addr1, short *addr2) */
+#define R_BSP_RMPAW(w, x, y, z)    rmpaw((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z))
+/* long long rmpal(long long init, unsigned long count, long *addr1, long *addr2) */
+#define R_BSP_RMPAL(w, x, y, z)    rmpal((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z))
+
+#elif defined(__GNUC__)
+
+/* long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2)
+   (This macro uses API function of BSP.) */
+#define R_BSP_RMPAB(w, x, y, z)    R_BSP_MulAndAccOperation_B((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z))
+/* long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2)
+   (This macro uses API function of BSP.) */
+#define R_BSP_RMPAW(w, x, y, z)    R_BSP_MulAndAccOperation_W((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z))
+/* long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2)
+   (This macro uses API function of BSP.) */
+#define R_BSP_RMPAL(w, x, y, z)    R_BSP_MulAndAccOperation_L((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z))
+
+#elif defined(__ICCRX__)
+
+/* long long rmpab(long long init, unsigned long count, signed char *addr1, signed char *addr2) */
+#define R_BSP_RMPAB(w, x, y, z)    rmpab((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z))
+/* long long rmpaw(long long init, unsigned long count, short *addr1, short *addr2) */
+#define R_BSP_RMPAW(w, x, y, z)    rmpaw((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z))
+/* long long rmpal(long long init, unsigned long count, long *addr1, long *addr2) */
+#define R_BSP_RMPAL(w, x, y, z)    rmpal((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z))
+
+#endif
+
+/* ---------- Rotation ---------- */
+#if defined(__CCRX__)
+
+/* unsigned long rolc(unsigned long data) */
+#define R_BSP_ROLC(x)    rolc((unsigned long)(x))
+/* unsigned long rorc(unsigned long data) */
+#define R_BSP_RORC(x)    rorc((unsigned long)(x))
+/* unsigned long rotl(unsigned long data, unsigned long num) */
+#define R_BSP_ROTL(x, y)    rotl((unsigned long)(x), (unsigned long)(y))
+/* unsigned long rotr (unsigned long data, unsigned long num) */
+#define R_BSP_ROTR(x, y)    rotr((unsigned long)(x), (unsigned long)(y))
+
+#elif defined(__GNUC__)
+
+/* unsigned long R_BSP_RotateLeftWithCarry(unsigned long data) (This macro uses API function of BSP.) */
+#define R_BSP_ROLC(x)    R_BSP_RotateLeftWithCarry((unsigned long)(x))
+/* unsigned long R_BSP_RotateRightWithCarry(unsigned long data) (This macro uses API function of BSP.) */
+#define R_BSP_RORC(x)    R_BSP_RotateRightWithCarry((unsigned long)(x))
+/* unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num) (This macro uses API function of BSP.) */
+#define R_BSP_ROTL(x, y)    R_BSP_RotateLeft((unsigned long)(x), (unsigned long)(y))
+/* unsigned long R_BSP_RotateRight (unsigned long data, unsigned long num) (This macro uses API function of BSP.) */
+#define R_BSP_ROTR(x, y)    R_BSP_RotateRight((unsigned long)(x), (unsigned long)(y))
+
+#elif defined(__ICCRX__)
+
+/* unsigned long __ROLC(unsigned long) */
+#define R_BSP_ROLC(x)    __ROLC((unsigned long)(x))
+/* unsigned long __RORC(unsigned long) */
+#define R_BSP_RORC(x)    __RORC((unsigned long)(x))
+/* unsigned long __ROTL(unsigned long, unsigned long) */
+#define R_BSP_ROTL(x, y)    __ROTL((unsigned long)(y), (unsigned long)(x))
+/* unsigned long __ROTR(unsigned long, unsigned long) */
+#define R_BSP_ROTR(x, y)    __ROTR((unsigned long)(y), (unsigned long)(x))
+
+#endif
+
+/* ---------- Special Instructions ---------- */
+#if defined(__CCRX__)
+
+/* void brk(void) */
+#define R_BSP_BRK()    brk()
+/* void int_exception(signed long num) */
+#define R_BSP_INT(x)   int_exception((signed long)(x))
+/* void wait(void) */
+#define R_BSP_WAIT()   wait()
+/* void nop(void) */
+#define R_BSP_NOP()    nop()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_brk (void)  */
+#define R_BSP_BRK()    __builtin_rx_brk()
+/* void __builtin_rx_int (int) */
+#define R_BSP_INT(x)   __builtin_rx_int((int)(x))
+/* void __builtin_rx_wait (void) */
+#define R_BSP_WAIT()   __builtin_rx_wait()
+/* __asm("nop") */
+#define R_BSP_NOP()    __asm("nop")
+
+#elif defined(__ICCRX__)
+
+/* void __break(void) */
+#define R_BSP_BRK()    __break()
+/* void __software_interrupt(unsigned char) */
+#define R_BSP_INT(x)   __software_interrupt((unsigned char)(x))
+/* void __wait_for_interrupt(void) */
+#define R_BSP_WAIT()   __wait_for_interrupt()
+/* void __no_operation(void) */
+#define R_BSP_NOP()    __no_operation()
+
+#endif
+
+/* ---------- Processor interrupt priority level (IPL) ---------- */
+#if defined(__CCRX__)
+
+/* void set_ipl(signed long level) */
+#define R_BSP_SET_IPL(x)    set_ipl((signed long)(x))
+/* unsigned char get_ipl(void) */
+#define R_BSP_GET_IPL()     get_ipl()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_mvtipl (int) */
+#define R_BSP_SET_IPL(x)    __builtin_rx_mvtipl((int)(x))
+/* uint32_t R_BSP_CpuInterruptLevelRead (void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_IPL()     (unsigned char)R_BSP_CpuInterruptLevelRead()
+
+#elif defined(__ICCRX__)
+
+/* void __set_interrupt_level(__ilevel_t) */
+#define R_BSP_SET_IPL(x)    __set_interrupt_level((__ilevel_t)(x))
+/* __ilevel_t __get_interrupt_level(void) */
+#define R_BSP_GET_IPL()     (unsigned char)__get_interrupt_level()
+
+#endif
+
+/* ---------- Processor status word (PSW) ---------- */
+#if defined(__CCRX__)
+
+/* void set_psw(unsigned long data) */
+#define R_BSP_SET_PSW(x)    set_psw((unsigned long)(x))
+/* unsigned long get_psw(void) */
+#define R_BSP_GET_PSW()     get_psw()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_mvtc (int reg, int val) */
+#define R_BSP_SET_PSW(x)    __builtin_rx_mvtc(0x0, (int)(x))
+/* int __builtin_rx_mvfc (int) */
+#define R_BSP_GET_PSW()     (unsigned long)__builtin_rx_mvfc(0x0)
+
+#elif defined(__ICCRX__)
+
+/* void __set_PSW_register(unsigned long) */
+#define R_BSP_SET_PSW(x)    __set_PSW_register((unsigned long)(x))
+/* unsigned long __get_PSW_register(void) */
+#define R_BSP_GET_PSW()     __get_PSW_register()
+
+#endif
+
+/* ---------- Floating-point status word (FPSW) ---------- */
+#ifdef __FPU
+#if defined(__CCRX__)
+
+/* void set_fpsw(unsigned long data) */
+#define R_BSP_SET_FPSW(x)    set_fpsw((unsigned long)(x))
+/* unsigned long get_fpsw(void) */
+#define R_BSP_GET_FPSW()     get_fpsw()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_mvtc (int reg, int val) */
+#define R_BSP_SET_FPSW(x)    __builtin_rx_mvtc(0x3, (int)(x))
+/* int __builtin_rx_mvfc (int) */
+#define R_BSP_GET_FPSW()    (unsigned long)__builtin_rx_mvfc(0x3)
+
+#elif defined(__ICCRX__)
+
+/* void __set_FPSW_register(unsigned long) */
+#define R_BSP_SET_FPSW(x)    __set_FPSW_register((unsigned long)(x))
+/* unsigned long __get_FPSW_register(void) */
+#define R_BSP_GET_FPSW()     __get_FPSW_register()
+
+#endif
+#endif
+
+/* ---------- User Stack Pointer (USP) ---------- */
+#if defined(__CCRX__)
+
+/* void set_usp(void *data) */
+#define R_BSP_SET_USP(x)    set_usp((void *)(x))
+/* void *get_usp(void) */
+#define R_BSP_GET_USP()     get_usp()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_mvtc (int reg, int val) */
+#define R_BSP_SET_USP(x)    __builtin_rx_mvtc(0x2, (int)(x))
+/* int __builtin_rx_mvfc (int) */
+#define R_BSP_GET_USP()     (void *)__builtin_rx_mvfc(0x2)
+
+#elif defined(__ICCRX__)
+
+/* void __set_USP_register(unsigned long) */
+#define R_BSP_SET_USP(x)    __set_USP_register((unsigned long)(x))
+/* unsigned long __get_USP_register(void) */
+#define R_BSP_GET_USP()     (void *)__get_USP_register()
+
+#endif
+
+/* ---------- Interrupt Stack Pointer (ISP) ---------- */
+#if defined(__CCRX__)
+
+/* void set_isp(void *data) */
+#define R_BSP_SET_ISP(x)    set_isp((void *)(x))
+/* void *get_isp(void) */
+#define R_BSP_GET_ISP()     get_isp()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_mvtc (int reg, int val) */
+#define R_BSP_SET_ISP(x)    __builtin_rx_mvtc(0xA, (int)(x))
+/* int __builtin_rx_mvfc (int) */
+#define R_BSP_GET_ISP()     (void *)__builtin_rx_mvfc(0xA)
+
+#elif defined(__ICCRX__)
+
+/* void __set_ISP_register(unsigned long) */
+#define R_BSP_SET_ISP(x)    __set_ISP_register((unsigned long)(x))
+/* unsigned long __get_ISP_register(void) */
+#define R_BSP_GET_ISP()     (void *)__get_ISP_register()
+
+#endif
+
+/* ---------- Interrupt Table Register (INTB) ---------- */
+#if defined(__CCRX__)
+
+/* void set_intb(void *data) */
+#define R_BSP_SET_INTB(x)    set_intb((void *)(x))
+/* void *get_intb(void) */
+#define R_BSP_GET_INTB()     get_intb()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_mvtc (int reg, int val) */
+#define R_BSP_SET_INTB(x)    __builtin_rx_mvtc(0xC, (int)(x))
+/* int __builtin_rx_mvfc (int) */
+#define R_BSP_GET_INTB()     (void *)__builtin_rx_mvfc(0xC)
+
+#elif defined(__ICCRX__)
+
+/* void __set_interrupt_table(unsigned long address) */
+#define R_BSP_SET_INTB(x)    __set_interrupt_table((unsigned long)(x))
+/* unsigned long __get_interrupt_table(void); */
+#define R_BSP_GET_INTB()     (void *)__get_interrupt_table()
+
+#endif
+
+/* ---------- Backup PSW (BPSW) ---------- */
+#if defined(__CCRX__)
+
+/* void set_bpsw(unsigned long data) */
+#define R_BSP_SET_BPSW(x)    set_bpsw((unsigned long)(x))
+/* unsigned long get_bpsw(void) */
+#define R_BSP_GET_BPSW()     get_bpsw()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_mvtc (int reg, int val) */
+#define R_BSP_SET_BPSW(x)    __builtin_rx_mvtc(0x8, (int)(x))
+/* int __builtin_rx_mvfc (int) */
+#define R_BSP_GET_BPSW()     (unsigned long)__builtin_rx_mvfc(0x8)
+
+#elif defined(__ICCRX__)
+
+/* void R_BSP_SetBPSW(uint32_t data) (This macro uses API function of BSP.) */
+#define R_BSP_SET_BPSW(x)    R_BSP_SetBPSW((uint32_t)(x))
+/* uint32_t R_BSP_GetBPSW(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_BPSW()     R_BSP_GetBPSW()
+
+#endif
+
+/* ---------- Backup PC (BPC) ---------- */
+#if defined(__CCRX__)
+
+/* void set_bpc(void *data) */
+#define R_BSP_SET_BPC(x)    set_bpc((void *)(x))
+/* void *get_bpc(void) */
+#define R_BSP_GET_BPC()     get_bpc()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_mvtc (int reg, int val) */
+#define R_BSP_SET_BPC(x)    __builtin_rx_mvtc(0x9, (int)(x))
+/* int __builtin_rx_mvfc (int) */
+#define R_BSP_GET_BPC()     (void *)__builtin_rx_mvfc(0x9)
+
+#elif defined(__ICCRX__)
+
+/* void R_BSP_SetBPC(void * data) (This macro uses API function of BSP.) */
+#define R_BSP_SET_BPC(x)    R_BSP_SetBPC((void *)(x))
+/* void *R_BSP_GetBPC(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_BPC()     R_BSP_GetBPC()
+
+#endif
+
+/* ---------- Fast Interrupt Vector Register (FINTV) ---------- */
+#if defined(__CCRX__)
+
+/* void set_fintv(void *data) */
+#define R_BSP_SET_FINTV(x)    set_fintv((void *)(x))
+/* void *get_fintv(void) */
+#define R_BSP_GET_FINTV()     get_fintv()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_mvtc (int reg, int val) */
+#define R_BSP_SET_FINTV(x)    __builtin_rx_mvtc(0xB, (int)(x))
+/* int __builtin_rx_mvfc (int) */
+#define R_BSP_GET_FINTV()     (void *)__builtin_rx_mvfc(0xB)
+
+#elif defined(__ICCRX__)
+
+/* void __set_FINTV_register(__fast_int_f) */
+#define R_BSP_SET_FINTV(x)    __set_FINTV_register((__fast_int_f)(x))
+/* __fast_int_f __get_FINTV_register(void) */
+#define R_BSP_GET_FINTV()     (void *)__get_FINTV_register()
+
+#endif
+
+/* ---------- Significant 64-bit multiplication ---------- */
+#if defined(__CCRX__)
+
+/* signed long long emul(signed long data1, signed long data2) */
+#define R_BSP_EMUL(x, y)    emul((signed long)(x), (signed long)(y))
+/* unsigned long long emulu(unsigned long data1, unsigned long data2) */
+#define R_BSP_EMULU(x, y)   emulu((unsigned long)(x), (unsigned long)(y))
+
+#elif defined(__GNUC__)
+
+/* signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2)
+   (This macro uses API function of BSP.) */
+#define R_BSP_EMUL(x, y)    R_BSP_SignedMultiplication((signed long)(x), (signed long)(y))
+/* unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2)
+   (This macro uses API function of BSP.) */
+#define R_BSP_EMULU(x, y)   R_BSP_UnsignedMultiplication((unsigned long)(x), (unsigned long)(y))
+
+#elif defined(__ICCRX__)
+
+/* signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2)
+   (This macro uses API function of BSP.) */
+#define R_BSP_EMUL(x, y)    R_BSP_SignedMultiplication((signed long)(x), (signed long)(y))
+/* unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2)
+   (This macro uses API function of BSP.) */
+#define R_BSP_EMULU(x, y)   R_BSP_UnsignedMultiplication((unsigned long)(x), (unsigned long)(y))
+
+#endif
+
+/* ---------- Processor mode (PM) ---------- */
+#if defined(__CCRX__)
+
+/* void chg_pmusr(void) */
+#define R_BSP_CHG_PMUSR()    chg_pmusr()
+
+#elif defined(__GNUC__)
+
+/* void R_BSP_ChangeToUserMode(void) (This macro uses API function of BSP.) */
+#define R_BSP_CHG_PMUSR()    R_BSP_ChangeToUserMode()
+
+#elif defined(__ICCRX__)
+
+/* void R_BSP_ChangeToUserMode(void) (This macro uses API function of BSP.) */
+#define R_BSP_CHG_PMUSR()    R_BSP_ChangeToUserMode()
+
+#endif
+
+/* ---------- Accumulator (ACC) ---------- */
+#if defined(__CCRX__)
+
+/* void set_acc(signed long long data) */
+#define R_BSP_SET_ACC(x)    set_acc((signed long long)(x))
+/* signed long long get_acc(void) */
+#define R_BSP_GET_ACC()     get_acc()
+
+#elif defined(__GNUC__)
+
+/* void R_BSP_SetACC(signed long long data) (This macro uses API function of BSP.) */
+#define R_BSP_SET_ACC(x)    R_BSP_SetACC((signed long long)(x))
+/* signed long long R_BSP_GetACC(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_ACC()     R_BSP_GetACC()
+
+#elif defined(__ICCRX__)
+
+/* void R_BSP_SetACC(signed long long data) (This macro uses API function of BSP.) */
+#define R_BSP_SET_ACC(x)    R_BSP_SetACC((signed long long)(x))
+/* signed long long R_BSP_GetACC(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_ACC()     R_BSP_GetACC()
+
+#endif
+
+/* ---------- Control of the interrupt enable bits ---------- */
+#if defined(__CCRX__)
+
+/* void setpsw_i(void) */
+#define R_BSP_SETPSW_I()    setpsw_i()
+/* void clrpsw_i(void) */
+#define R_BSP_CLRPSW_I()    clrpsw_i()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_setpsw (int) */
+#define R_BSP_SETPSW_I()    __builtin_rx_setpsw('I')
+/* void __builtin_rx_clrpsw (int) */
+#define R_BSP_CLRPSW_I()    __builtin_rx_clrpsw('I')
+
+#elif defined(__ICCRX__)
+
+/* void __enable_interrupt(void) */
+#define R_BSP_SETPSW_I()    __enable_interrupt()
+/* void __disable_interrupt(void) */
+#define R_BSP_CLRPSW_I()    __disable_interrupt()
+
+#endif
+
+/* ---------- Multiply-and-accumulate operation ---------- */
+#if defined(__CCRX__)
+
+/* long macl(short *data1, short *data2, unsigned long count) */
+#define R_BSP_MACL(x, y, z)     macl((short *)(x), (short *)(y), (unsigned long)(z))
+/* short macw1(short *data1, short *data2, unsigned long count) */
+#define R_BSP_MACW1(x, y, z)    macw1((short *)(x), (short *)(y), (unsigned long)(z))
+/* short macw2(short *data1, short *data2, unsigned long count) */
+#define R_BSP_MACW2(x, y, z)    macw2((short *)(x), (short *)(y), (unsigned long)(z))
+
+#elif defined(__GNUC__)
+
+/* long R_BSP_MulAndAccOperation_2byte(short *data1, short *data2, unsigned long count)
+   (This macro uses API function of BSP.) */
+#define R_BSP_MACL(x, y, z)     R_BSP_MulAndAccOperation_2byte((short *)(x), (short *)(y), (unsigned long)(z))
+/* short R_BSP_MulAndAccOperation_FixedPoint1(short *data1, short *data2, unsigned long count)
+   (This macro uses API function of BSP.) */
+#define R_BSP_MACW1(x, y, z)    R_BSP_MulAndAccOperation_FixedPoint1((short *)(x), (short *)(y), (unsigned long)(z))
+/* short R_BSP_MulAndAccOperation_FixedPoint2(short *data1, short *data2, unsigned long count)
+   (This macro uses API function of BSP.) */
+#define R_BSP_MACW2(x, y, z)    R_BSP_MulAndAccOperation_FixedPoint2((short *)(x), (short *)(y), (unsigned long)(z))
+
+#elif defined(__ICCRX__)
+
+/* long __macl(short * data1, short * data2, unsigned long count) */
+#define R_BSP_MACL(x, y, z)     __macl((short *)(x), (short *)(y), (unsigned long)(z))
+/* short __macw1(short * data1, short * data2, unsigned long count) */
+#define R_BSP_MACW1(x, y, z)    __macw1((short *)(x), (short *)(y), (unsigned long)(z))
+/* short __macw2(short * data1, short * data2, unsigned long count) */
+#define R_BSP_MACW2(x, y, z)    __macw2((short *)(x), (short *)(y), (unsigned long)(z))
+
+#endif
+
+/* ---------- Exception Table Register (EXTB) ---------- */
+#ifdef BSP_MCU_EXCEPTION_TABLE
+#if defined(__CCRX__)
+
+/* void set_extb(void *data) */
+#define R_BSP_SET_EXTB(x)    set_extb((void *)(x))
+/* void *get_extb(void) */
+#define R_BSP_GET_EXTB()     get_extb()
+
+#elif defined(__GNUC__)
+
+/* void __builtin_rx_mvtc (int reg, int val) */
+#define R_BSP_SET_EXTB(x)    __builtin_rx_mvtc(0xD, (int)(x))
+/* int __builtin_rx_mvfc (int) */
+#define R_BSP_GET_EXTB()     (void *)__builtin_rx_mvfc(0xD)
+
+#elif defined(__ICCRX__)
+
+/* void R_BSP_SetEXTB(void * data) (This macro uses API function of BSP.) */
+#define R_BSP_SET_EXTB(x)    R_BSP_SetEXTB((void *)(x))
+/* void *R_BSP_GetEXTB(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_EXTB()     R_BSP_GetEXTB()
+
+#endif
+#endif
+
+/* ---------- Bit Manipulation ---------- */
+#if defined(__CCRX__)
+
+/* void __bclr(unsigned char *data, unsigned long bit) */
+#define R_BSP_BIT_CLEAR(x, y)      __bclr((unsigned char *)(x), (unsigned long)(y))
+/* void __bset(unsigned char *data, unsigned long bit) */
+#define R_BSP_BIT_SET(x, y)        __bset((unsigned char *)(x), (unsigned long)(y))
+/* void __bnot(unsigned char *data, unsigned long bit) */
+#define R_BSP_BIT_REVERSE(x, y)    __bnot((unsigned char *)(x), (unsigned long)(y))
+
+#elif defined(__GNUC__)
+
+/* void R_BSP_BitClear(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */
+#define R_BSP_BIT_CLEAR(x, y)      R_BSP_BitClear((uint8_t *)(x), (uint32_t)(y))
+/* void R_BSP_BitSet(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */
+#define R_BSP_BIT_SET(x, y)        R_BSP_BitSet((uint8_t *)(x), (uint32_t)(y))
+/* void R_BSP_BitReverse(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */
+#define R_BSP_BIT_REVERSE(x, y)    R_BSP_BitReverse((uint8_t *)(x), (uint32_t)(y))
+
+#elif defined(__ICCRX__)
+
+/* void R_BSP_BitClear(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */
+#define R_BSP_BIT_CLEAR(x, y)      R_BSP_BitClear((uint8_t *)(x), (uint32_t)(y))
+/* void R_BSP_BitSet(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */
+#define R_BSP_BIT_SET(x, y)        R_BSP_BitSet((uint8_t *)(x), (uint32_t)(y))
+/* void R_BSP_BitReverse(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */
+#define R_BSP_BIT_REVERSE(x, y)    R_BSP_BitReverse((uint8_t *)(x), (uint32_t)(y))
+
+#endif
+
+#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT
+#ifdef __DPFPU
+/* ---------- Double-Precision Floating-Point Status Word (DPSW) ---------- */
+#if defined(__CCRX__)
+
+/* void set_dpsw(unsigned long data) */
+#define R_BSP_SET_DPSW(x)    __set_dpsw((unsigned long)(x))
+/* unsigned long get_dpsw(void) */
+#define R_BSP_GET_DPSW()     __get_dpsw()
+
+#elif defined(__GNUC__)
+
+/* void R_BSP_SetDPSW(uint32_t data) (This macro uses API function of BSP.) */
+#define R_BSP_SET_DPSW(x)    R_BSP_SetDPSW((uint32_t)(x))
+/* uint32_t R_BSP_GetDPSW(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_DPSW()     R_BSP_GetDPSW()
+
+#elif defined(__ICCRX__)
+
+/* void R_BSP_SetDPSW(uint32_t data) (This macro uses API function of BSP.) */
+#define R_BSP_SET_DPSW(x)    R_BSP_SetDPSW((uint32_t)(x))
+/* uint32_t R_BSP_GetDPSW(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_DPSW()     R_BSP_GetDPSW()
+
+#endif
+
+/* ---------- Double-precision floating-point exception handling operation control register (DECNT) ---------- */
+#if defined(__CCRX__)
+
+/* void __set_decnt(unsigned long data) */
+#define R_BSP_SET_DECNT(x)    __set_decnt((unsigned long)(x))
+/* unsigned long __get_decnt(void) */
+#define R_BSP_GET_DECNT()     __get_decnt()
+
+#elif defined(__GNUC__)
+
+/* void R_BSP_SetDECNT(uint32_t data) (This macro uses API function of BSP.) */
+#define R_BSP_SET_DECNT(x)    R_BSP_SetDECNT((uint32_t)(x))
+/* uint32_t R_BSP_GetDECNT(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_DECNT()     R_BSP_GetDECNT()
+
+#elif defined(__ICCRX__)
+
+/* void R_BSP_SetDECNT(uint32_t data) (This macro uses API function of BSP.) */
+#define R_BSP_SET_DECNT(x)    R_BSP_SetDECNT((uint32_t)(x))
+/* uint32_t R_BSP_GetDECNT(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_DECNT()     R_BSP_GetDECNT()
+
+#endif
+
+/* ---------- Double-precision floating-point exception program counter (DEPC) ---------- */
+#if defined(__CCRX__)
+
+/* void *__get_depc(void) */
+#define R_BSP_GET_DEPC()     __get_depc()
+
+#elif defined(__GNUC__)
+
+/* void *R_BSP_GetDEPC(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_DEPC()     R_BSP_GetDEPC()
+
+#elif defined(__ICCRX__)
+
+/* void *R_BSP_GetDEPC(void) (This macro uses API function of BSP.) */
+#define R_BSP_GET_DEPC()     R_BSP_GetDEPC()
+
+#endif
+#endif /* __DPFPU */
+#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */
+
+/* ---------- Initializing Arithmetic Unit for Trigonometric Functions ---------- */
+#ifdef BSP_MCU_TRIGONOMETRIC
+#if defined(__CCRX__)
+
+/* void __init_tfu(void) */
+#define R_BSP_INIT_TFU()      __init_tfu()
+
+#elif defined(__GNUC__)
+
+/* void R_BSP_InitTFU(void) (This macro uses API function of BSP.) */
+#define R_BSP_INIT_TFU()      R_BSP_InitTFU()
+
+#elif defined(__ICCRX__)
+
+/* Invalid for ICCRX.
+   Because the initilaze function of TFU is called automatically when the TFU function is called. */
+#define R_BSP_INIT_TFU()      
+
+#endif
+
+/* ---------- Calculating the Sine and Cosine of an angle at the same time(single precision) ---------- */
+#if defined(__CCRX__)
+
+/* void __sincosf(float f, float *sin, float *cos) */
+#define R_BSP_SINCOSF(x, y, z)    __sincosf((float)(x), (float *)(y), (float *)(z))
+
+#elif defined(__GNUC__)
+
+/* void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) (This macro uses API function of BSP.) */
+#define R_BSP_SINCOSF(x, y, z)    R_BSP_CalcSine_Cosine((float)(x), (float *)(y), (float *)(z))
+
+#elif defined(__ICCRX__)
+
+/* void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) (This macro uses API function of BSP.) */
+#define R_BSP_SINCOSF(x, y, z)    __sincosf((float)(x), (float *)(y), (float *)(z))
+
+#endif
+
+/* ---------- Initializing Arithmetic Unit for Trigonometric Functions ---------- */
+#if defined(__CCRX__)
+
+/* void __atan2hypotf(float y, float x, float *atan2, float *hypot) */
+#define R_BSP_ATAN2HYPOTF(w, x, y, z)    __atan2hypotf((float)(w), (float)(x), (float *)(y), (float *)(z))
+
+#elif defined(__GNUC__)
+
+/* void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot)
+   (This macro uses API function of BSP.) */
+#define R_BSP_ATAN2HYPOTF(w, x, y, z)    R_BSP_CalcAtan_SquareRoot((float)(w), (float)(x), (float *)(y), (float *)(z))
+
+#elif defined(__ICCRX__)
+
+/* void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot)
+   (This macro uses API function of BSP.) */
+#define R_BSP_ATAN2HYPOTF(w, x, y, z)    __atan2hypotf((float)(w), (float)(x), (float *)(y), (float *)(z))
+
+#endif
+#endif /* BSP_MCU_TRIGONOMETRIC */
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+signed long R_BSP_Max(signed long data1, signed long data2);
+signed long R_BSP_Min(signed long data1, signed long data2);
+long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2);
+long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2);
+long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2);
+unsigned long R_BSP_RotateLeftWithCarry(unsigned long data);
+unsigned long R_BSP_RotateRightWithCarry(unsigned long data);
+unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num);
+unsigned long R_BSP_RotateRight(unsigned long data, unsigned long num);
+long R_BSP_MulAndAccOperation_2byte(short* data1, short* data2, unsigned long count);
+short R_BSP_MulAndAccOperation_FixedPoint1(short* data1, short* data2, unsigned long count);
+short R_BSP_MulAndAccOperation_FixedPoint2(short* data1, short* data2, unsigned long count);
+#endif /* defined(__GNUC__) */
+
+#if defined(__GNUC__) || defined(__ICCRX__)
+signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2);
+unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2);
+void R_BSP_SetACC(signed long long data);
+signed long long R_BSP_GetACC(void);
+#endif /* defined(__GNUC__) || defined(__ICCRX__)  */
+
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_ChangeToUserMode(void);
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetBPSW(uint32_t data);
+uint32_t R_BSP_GetBPSW(void);
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetBPC(void * data);
+void *R_BSP_GetBPC(void);
+#ifdef BSP_MCU_EXCEPTION_TABLE
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetEXTB(void * data);
+void *R_BSP_GetEXTB(void);
+#endif /* BSP_MCU_EXCEPTION_TABLE */
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitSet(uint8_t *data, uint32_t bit);
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitClear(uint8_t *data, uint32_t bit);
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitReverse(uint8_t *data, uint32_t bit);
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_MoveToAccHiLong(int32_t data);
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_MoveToAccLoLong(int32_t data);
+int32_t R_BSP_MoveFromAccHiLong(void);
+int32_t R_BSP_MoveFromAccMiLong(void);
+#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT
+#ifdef __DPFPU
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetDPSW(uint32_t data);
+uint32_t R_BSP_GetDPSW(void);
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetDECNT(uint32_t data);
+uint32_t R_BSP_GetDECNT(void);
+void *R_BSP_GetDEPC(void);
+#endif
+#endif
+#ifdef BSP_MCU_TRIGONOMETRIC
+#ifdef __TFU
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_InitTFU(void);
+#ifdef __FPU
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos);
+R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot);
+#endif /* __FPU */
+#endif /* __TFU */
+#endif
+
+/* End of multiple inclusion prevention macro */
+#endif  /* R_RX_INTRINSIC_FUNCTIONS_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_typedefs.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_typedefs.h
new file mode 100644
index 00000000..34f975d0
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/r_typedefs.h
@@ -0,0 +1,59 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_typedefs.h
+* Description  : This has fixed-width integer and bool support for compilers that are not C99 compliant and do not have
+*                the header files stdint.h, stdbool.h, and stddef.h.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 18.09.2012 1.00     First Release
+*         : 21.06.2013 1.10     Added NULL and size_t support.
+*         : 22.11.2013 1.11     Changed size_t to 'unsigned long' from 'unsigned int'.
+*         : 28.02.2019 1.12     Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef R_TYPEDEFS_H
+#define R_TYPEDEFS_H
+
+#define bool  (_Bool)
+#define false (0)
+#define true  (1)
+#define NULL  (0)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef signed char int8_t;
+typedef unsigned char uint8_t;
+typedef signed short int16_t;
+typedef unsigned short uint16_t;
+typedef signed long int32_t;
+typedef unsigned long uint32_t;
+typedef signed long long int64_t;
+typedef unsigned long long uint64_t;
+typedef unsigned int _Bool;
+typedef unsigned long size_t;
+
+#endif  /* End of multiple inclusion prevention macro */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/reset_program.S b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/reset_program.S
new file mode 100644
index 00000000..9b753709
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/reset_program.S
@@ -0,0 +1,183 @@
+;;/***********************************************************************************************************************
+;;* DISCLAIMER
+;;* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+;;* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+;;* applicable laws, including copyright laws. 
+;;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+;;* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+;;* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+;;* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+;;* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;;* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+;;* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+;;* following link:
+;;* http://www.renesas.com/disclaimer 
+;;*
+;;* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+;;***********************************************************************************************************************/
+;;/***********************************************************************************************************************
+;;* File Name    : reset_program.asm
+;;* Description  : Defines post-reset routines that are used to configure the MCU prior to the main program starting. 
+;;*                This is where the program counter starts on power-up or reset.
+;;***********************************************************************************************************************/
+;;/***********************************************************************************************************************
+;;* History : DD.MM.YYYY Version   Description
+;;*         : 28.02.2019 1.00      First Release
+;;***********************************************************************************************************************/
+
+    .if __GNUC__
+
+;;reset_program.asm
+
+    .list
+    .section .text
+    .global _PowerON_Reset_PC  ;;global Start routine
+    .global _PowerON_Reset     ;;for backward compatibility
+
+    .extern _PowerON_Reset_PC_Prg  ;;external Power ON Reset main function in RESETPRG.C
+    .extern _data
+    .extern _mdata
+    .extern _ebss
+    .extern _bss
+    .extern _edata
+    .extern _ustack
+    .extern _istack
+    .extern _exit
+
+
+_PowerON_Reset_PC :
+_PowerON_Reset :
+;;initialise user stack pointer
+    mvtc    #_ustack,USP
+
+;;initialise interrupt stack pointer
+    mvtc    #_istack,ISP
+
+;;jump to Power ON Reset main function in RESETPRG.C
+    bra     _PowerON_Reset_PC_Prg
+
+;;init section
+    .global __INITSCT
+    .type   __INITSCT,@function
+__INITSCT:
+
+;;load data section from ROM to RAM
+    pushm   r1-r3
+    mov     #_mdata,r2      ;;src ROM address of data section in R2
+    mov     #_data,r1       ;;dest start RAM address of data section in R1
+    mov     #_edata,r3      ;;end RAM address of data section in R3
+    sub     r1,r3           ;;size of data section in R3 (R3=R3-R1)
+    smovf                   ;;block copy R3 bytes from R2 to R1
+
+;;bss initialisation : zero out bss
+    mov    #00h,r2          ;;load R2 reg with zero
+    mov    #_ebss, r3       ;;store the end address of bss in R3
+    mov    #_bss, r1        ;;store the start address of bss in R1
+    sub    r1,r3            ;;size of bss section in R3 (R3=R3-R1)
+    sstr.b
+    popm    r1-r3
+    rts
+
+#ifdef CPPAPP
+
+;;init global class object
+    .global __CALL_INIT
+    .type   __CALL_INIT,@function
+__CALL_INIT:
+    bra      __rx_init
+
+    .global _rx_run_preinit_array
+    .type   _rx_run_preinit_array,@function
+_rx_run_preinit_array:
+    mov     #__preinit_array_start,r1
+    mov     #__preinit_array_end,r2
+    bra.a   _rx_run_inilist
+
+    .global _rx_run_init_array
+    .type   _rx_run_init_array,@function
+_rx_run_init_array:
+    mov     #__init_array_start,r1
+    mov     #__init_array_end,r2
+    mov     #4, r3
+    bra.a   _rx_run_inilist
+
+    .global _rx_run_fini_array
+    .type   _rx_run_fini_array,@function
+_rx_run_fini_array:
+    mov    #__fini_array_start,r2
+    mov    #__fini_array_end,r1
+    mov    #-4, r3
+    ;;fall through
+
+_rx_run_inilist:
+next_inilist:
+    cmp     r1,r2
+    beq.b   done_inilist
+    mov.l   [r1],r4
+    cmp     #-1, r4
+    beq.b   skip_inilist
+    cmp     #0, r4
+    beq.b   skip_inilist
+    pushm   r1-r3
+    jsr     r4
+    popm    r1-r3
+skip_inilist:
+    add     r3,r1
+    bra.b   next_inilist
+done_inilist:
+    rts
+
+    .section    .init,"ax"
+    .balign 4
+
+    .global     __rx_init
+__rx_init:
+
+    .section    .fini,"ax"
+    .balign 4
+
+    .global     __rx_fini
+__rx_fini:
+    bsr.a   _rx_run_fini_array
+
+    .section .sdata
+    .balign 4
+    .global __gp
+    .weak   __gp
+__gp:
+
+    .section .data
+    .global ___dso_handle
+    .weak   ___dso_handle
+___dso_handle:
+    .long    0
+
+     .section   .init,"ax"
+     bsr.a      _rx_run_preinit_array
+     bsr.a      _rx_run_init_array
+     rts
+
+    .global     __rx_init_end
+__rx_init_end:
+
+    .section    .fini,"ax"
+
+    rts
+    .global __rx_fini_end
+__rx_fini_end:
+
+#endif
+
+;;call to exit
+_exit:
+    bra  _loop_here
+_loop_here:
+    bra _loop_here
+
+    .text
+
+    .endif
+
+    .end
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/resetprg.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/resetprg.c
new file mode 100644
index 00000000..d6fa1bfc
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/resetprg.c
@@ -0,0 +1,365 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : resetprg.c
+* Description  : Defines post-reset routines that are used to configure the MCU prior to the main program starting. 
+*                This is where the program counter starts on power-up or reset.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 28.02.2019 3.00      Merged processing of all devices.
+*                                Added support for GNUC and ICCRX.
+*                                Fixed coding style.
+*                                Renamed following macro definitions.
+*                                - BSP_PRV_PSW_INIT
+*                                - BSP_PRV_FPSW_INIT
+*                                - BSP_PRV_FPU_ROUND
+*                                - BSP_PRV_FPU_DENOM
+*                                Added following macro definitions.
+*                                - BSP_PRV_DPSW_INIT
+*         : 26.07.2019 3.01      Added vbatt_voltage_stability_wait function.
+*         : 08.10.2019 3.10      Changed for added support of Renesas RTOS (RI600V4 or RI600PX).
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#if defined(__CCRX__)
+/* Defines MCU configuration functions used in this file */
+#include    <_h_c_lib.h>
+#endif /* defined(__CCRX__) */
+
+/* Define the target platform */
+#include    "platform.h"
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+
+#if BSP_CFG_RTOS_USED == 4  /* Renesas RI600V4 & RI600PX */
+
+#if BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600PX
+#pragma section P PS
+#pragma section B BS
+#pragma section C CS
+#pragma section D DS
+#else
+#include    "ri_cmt.h"    /*  Generated by cfg600 */
+#endif /* BSP_CFG_RENESAS_RTOS_USED */
+
+#else /* BSP_CFG_RTOS_USED!=4 */
+
+/* Declaration of stack size. */
+#if BSP_CFG_USER_STACK_ENABLE == 1
+R_BSP_PRAGMA_STACKSIZE_SU(BSP_CFG_USTACK_BYTES)
+#endif
+R_BSP_PRAGMA_STACKSIZE_SI(BSP_CFG_ISTACK_BYTES)
+
+#endif/* BSP_CFG_RTOS_USED */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */
+    #define BSP_PRV_PSW_INIT  (0x00000000)	/* Supervisor mode & Disable Interrupt */
+#else /* BSP_CFG_RTOS_USED!=4 */
+/* If the user chooses only 1 stack then the 'U' bit will not be set and the CPU will always use the interrupt stack. */
+#if BSP_CFG_USER_STACK_ENABLE == 1
+    #define BSP_PRV_PSW_INIT  (0x00030000)
+#else
+    #define BSP_PRV_PSW_INIT  (0x00010000)
+#endif
+#endif/* BSP_CFG_RTOS_USED */
+
+#if defined(__CCRX__) || defined(__GNUC__)
+
+#ifdef BSP_MCU_FLOATING_POINT
+    /* Initialize FPSW for floating-point operations */
+#define BSP_PRV_FPSW_INIT (0x00000000)  /* Currently nothing set by default. */
+#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT
+    /* Initialize DPSW for double-precision floating-point operations */
+#define BSP_PRV_DPSW_INIT (0x00000000)  /* Currently nothing set by default. */
+#endif
+
+#ifdef __ROZ
+#define BSP_PRV_FPU_ROUND (0x00000001)  /* Let FPSW RMbits=01 (round to zero) */
+#else
+#define BSP_PRV_FPU_ROUND (0x00000000)  /* Let FPSW RMbits=00 (round to nearest) */
+#endif
+#ifdef __DOFF
+#define BSP_PRV_FPU_DENOM (0x00000100)  /* Let FPSW DNbit=1 (denormal as zero) */
+#else
+#define BSP_PRV_FPU_DENOM (0x00000000)  /* Let FPSW DNbit=0 (denormal as is) */
+#endif
+#endif
+
+#endif /* defined(__CCRX__), defined(__GNUC__) */
+
+/***********************************************************************************************************************
+Pre-processor Directives
+***********************************************************************************************************************/
+/* Set this as the entry point from a power-on reset */
+#if defined(__CCRX__)
+#pragma entry PowerON_Reset_PC
+#endif /* defined(__CCRX__) */
+
+/***********************************************************************************************************************
+External function Prototypes
+***********************************************************************************************************************/
+/* Initialize C runtime environment */
+extern void _INITSCT(void);
+
+#if defined(CPPAPP)
+/* Initialize C++ global class object */
+extern void _CALL_INIT(void);
+#endif
+
+#if BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED != 0
+/* If user is requesting warm start callback functions then these are the prototypes. */
+void BSP_CFG_USER_WARM_START_PRE_C_FUNCTION(void);
+#endif
+
+#if BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED != 0
+/* If user is requesting warm start callback functions then these are the prototypes. */
+void BSP_CFG_USER_WARM_START_POST_C_FUNCTION(void);
+#endif
+
+#if BSP_CFG_RTOS_USED == 1  /* FreeRTOS */
+/* A function is used to create a main task, rtos's objects required to be available in advance. */
+extern void Processing_Before_Start_Kernel(void);
+#elif BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */
+/* kernel initialization routine */
+extern void vsta_knl(void);
+#endif/* BSP_CFG_RTOS_USED */
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* Power-on reset function declaration */
+R_BSP_POR_FUNCTION(R_BSP_STARTUP_FUNCTION);
+
+/* Main program function declaration */
+#if BSP_CFG_RTOS_USED == 0    /* Non-OS */
+extern void R_BSP_MAIN_FUNCTION(void);
+#endif
+
+/***********************************************************************************************************************
+* Function name: PowerON_Reset_PC
+* Description  : This function is the MCU's entry point from a power-on reset.
+*                The following steps are taken in the startup code:
+*                1. The User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) are both set immediately after entry 
+*                   to this function. The USP and ISP stack sizes are set in the file bsp_config.h.
+*                2. The interrupt vector base register is set to point to the beginning of the relocatable interrupt 
+*                   vector table.
+*                3. The MCU is setup for floating point operations by setting the initial value of the Floating Point 
+*                   Status Word (FPSW).
+*                4. The MCU operating frequency is set by configuring the Clock Generation Circuit (CGC) in
+*                   operating_frequency_set.
+*                5. Calls are made to functions to setup the C runtime environment which involves initializing all 
+*                   initialed data, zeroing all uninitialized variables, and configuring STDIO if used
+*                   (calls to _INITSCT and init_iolib).
+*                6. Board-specific hardware setup, including configuring I/O pins on the MCU, in hardware_setup.
+*                7. Global interrupts are enabled by setting the I bit in the Program Status Word (PSW), and the stack 
+*                   is switched from the ISP to the USP.  The initial Interrupt Priority Level is set to zero, enabling 
+*                   any interrupts with a priority greater than zero to be serviced.
+*                8. The processor is optionally switched to user mode.  To run in user mode, set the macro 
+*                   BSP_CFG_RUN_IN_USER_MODE above to a 1.
+*                9. The bus error interrupt is enabled to catch any accesses to invalid or reserved areas of memory.
+*
+*                Once this initialization is complete, the user's main() function is called.  It should not return.
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+R_BSP_POR_FUNCTION(R_BSP_STARTUP_FUNCTION)
+{
+    /* Stack pointers are setup prior to calling this function - see comments above */
+
+    /* You can use auto variables in this function but such variables other than register variables 
+     * will be unavailable after you change the stack from the I stack to the U stack (if change). */
+
+    /* The bss sections have not been cleared and the data sections have not been initialized 
+     * and constructors of C++ objects have not been executed until the _INITSCT() is executed. */
+#if defined(__GNUC__)
+#if BSP_CFG_USER_STACK_ENABLE == 1
+    INTERNAL_NOT_USED(ustack_area);
+#endif
+    INTERNAL_NOT_USED(istack_area);
+#endif
+
+#if defined(__CCRX__) || defined(__GNUC__)
+
+    /* Initialize the Interrupt Table Register */
+    R_BSP_SET_INTB(R_BSP_SECTOP_INTVECTTBL);
+
+#ifdef BSP_MCU_EXCEPTION_TABLE
+    /* Initialize the Exception Table Register */
+    R_BSP_SET_EXTB(R_BSP_SECTOP_EXCEPTVECTTBL);
+#endif
+
+#ifdef BSP_MCU_FLOATING_POINT
+#ifdef __FPU
+    /* Initialize the Floating-Point Status Word Register. */
+    R_BSP_SET_FPSW(BSP_PRV_FPSW_INIT | BSP_PRV_FPU_ROUND | BSP_PRV_FPU_DENOM);
+#endif
+#endif
+
+#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT
+#ifdef __DPFPU
+    /* Initialize the Double-Precision Floating-Point Status Word Register. */
+    R_BSP_SET_DPSW(BSP_PRV_DPSW_INIT | BSP_PRV_FPU_ROUND | BSP_PRV_FPU_DENOM);
+#endif
+#endif
+
+    /* Initializes the trigonometric function unit. */
+#ifdef BSP_MCU_TRIGONOMETRIC
+#ifdef __TFU
+    R_BSP_INIT_TFU();
+#endif
+#endif
+
+#endif /* defined(__CCRX__), defined(__GNUC__) */
+
+    /* Wait for power voltage stabilization of VBATT function. */
+#if (defined(BSP_CFG_VBATT_ENABLE) && (BSP_CFG_VBATT_ENABLE == 0))
+    vbatt_voltage_stability_wait();
+#endif
+
+    /* Switch to high-speed operation */ 
+    mcu_clock_setup();
+
+    /* If the warm start Pre C runtime callback is enabled, then call it. */
+#if BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED == 1
+    BSP_CFG_USER_WARM_START_PRE_C_FUNCTION();
+#endif
+
+    /* Initialize C runtime environment */
+    _INITSCT();
+
+#if defined(CPPAPP)
+    /* Initialize C++ global class object */
+    _CALL_INIT();
+#endif
+
+    /* Initialize RAM */
+    bsp_ram_initialize();
+
+    /* If the warm start Post C runtime callback is enabled, then call it. */
+#if BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED == 1
+    BSP_CFG_USER_WARM_START_POST_C_FUNCTION();
+#endif
+
+#if BSP_CFG_IO_LIB_ENABLE == 1
+    /* Comment this out if not using I/O lib */
+#if defined(__CCRX__)
+    init_iolib();
+#endif /* defined(__CCRX__) */
+#endif
+
+    /* Initialize MCU interrupt callbacks. */
+    bsp_interrupt_open();
+
+    /* Initialize register protection functionality. */
+    bsp_register_protect_open();
+
+    /* Configure the MCU and board hardware */
+    hardware_setup();
+
+    /* Enable interrupt and select the I stack or the U stack */
+    R_BSP_SET_PSW(BSP_PRV_PSW_INIT);
+
+#if BSP_CFG_RTOS_USED == 4  /* Renesas RI600V4 & RI600PX */
+    /* Does not change the MCU's user mode to user in Renesas RTOS. */
+#else /* BSP_CFG_RTOS_USED != 4 */
+#if BSP_CFG_RUN_IN_USER_MODE == 1
+    /* Change the MCU's user mode from supervisor to user */
+    #if BSP_CFG_USER_STACK_ENABLE == 1
+        R_BSP_CHG_PMUSR();
+    #else
+        #error "Settings of BSP_CFG_RUN_IN_USER_MODE and BSP_CFG_USER_STACK_ENABLE are inconsistent with each other."
+    #endif
+#endif /* BSP_CFG_RUN_IN_USER_MODE */
+#endif /* BSP_CFG_RTOS_USED */
+
+    /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */
+    R_BSP_InterruptControl(BSP_INT_SRC_BUS_ERROR, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR);
+
+#if BSP_CFG_RTOS_USED == 0    /* Non-OS */
+    /* Call the main program function (should not return) */
+    R_BSP_MAIN_FUNCTION();
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+    /* Lock the channel that system timer of RTOS is using. */
+    #if (((BSP_CFG_RTOS_SYSTEM_TIMER) >=0) && ((BSP_CFG_RTOS_SYSTEM_TIMER) <= 3))
+        if (R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + BSP_CFG_RTOS_SYSTEM_TIMER)) == false)
+        {
+            /* WAIT_LOOP */
+            while(1);
+        }
+    #else
+        #error "Setting BSP_CFG_RTOS_SYSTEM_TIMER is invalid."
+    #endif
+
+    /* Prepare the necessary tasks, FreeRTOS's resources... required to be executed at the beginning
+     * after vTaskStarScheduler() is called. Other tasks can also be created after starting scheduler at any time */
+    Processing_Before_Start_Kernel();
+
+    /* Call the kernel startup (should not return) */
+    vTaskStartScheduler();
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+#if BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600V4
+    /* Lock a timer resource by r_bsp, if using time function on RTOS. */
+    if(R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + _RI_CLOCK_TIMER)) == false)
+    {
+        /* WAIT_LOOP */
+        while(1);
+    }
+    /* Initialize CMT for RI600V4 */
+    _RI_init_cmt();
+#else
+    /* When RI600PX, the above are in _RI_init_cmt_knl called from the kernel. */
+#endif
+    /* Make sure to disable interrupt. */
+    R_BSP_CLRPSW_I();/* clrpsw_i() */
+    vsta_knl();
+#endif/* BSP_CFG_RTOS_USED */
+
+#if BSP_CFG_IO_LIB_ENABLE == 1
+    /* Comment this out if not using I/O lib - cleans up open files */
+#if defined(__CCRX__)
+    close_all();
+#endif /* defined(__CCRX__) */
+#endif
+
+    /* Infinite loop is intended here. */
+    /* WAIT_LOOP */
+    while(1)
+    {
+        /* Infinite loop. Put a breakpoint here if you want to catch an exit of main(). */
+        R_BSP_NOP();
+    }
+} /* End of function PowerON_Reset_PC() */
+
+#if BSP_CFG_RTOS_USED == 4  /* Renesas RI600V4 & RI600PX */
+/* Definition of Kernel data section */
+#include "kernel_ram.h"     /* generated by cfg600 */
+#include "kernel_rom.h"     /* generated by cfg600 */
+#endif/* BSP_CFG_RTOS_USED */
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/sbrk.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/sbrk.c
new file mode 100644
index 00000000..30bf1038
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/sbrk.c
@@ -0,0 +1,120 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : sbrk.c
+* Description  : Configures the MCU heap memory.  The size of the heap is defined by the macro HEAPSIZE below.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 3.00     Merged processing of all devices.
+*                               Added support for GNUC and ICCRX.
+*                               Fixed coding style.
+*         : 26.07.2019 3.01     Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "sbrk.h"
+
+/* Only use this file if heap is enabled in r_bsp_config. */
+#if BSP_CFG_HEAP_BYTES > 0
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+
+#if defined(__CCRX__) || defined(__GNUC__)
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* Declare memory heap area */
+static u_heap_type_t s_heap_area;
+
+/* End address allocated by sbrk (CC-RX and GNURX+NEWLIB) */
+static int8_t *sp_brk=(int8_t *)&s_heap_area;
+
+#if defined(__GNUC__)
+/* Start address of allocated heap area (GNURX+OPTLIB only) */
+int8_t *_heap_of_memory=(int8_t *)&s_heap_area;
+/* End address of allocated heap area (GNURX+OPTLIB only) */
+int8_t *_last_heap_object=(int8_t *)&s_heap_area;
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* Function name: sbrk
+* Description  : This function configures MCU memory area allocation. (CC-RX and GNURX+NEWLIB)
+* Arguments    : size - 
+*                    assigned area size
+* Return value : Start address of allocated area (pass)
+*                -1 (failure)
+***********************************************************************************************************************/
+int8_t  *sbrk(size_t size)
+{
+    int8_t  *p_area;
+
+    if ((sp_brk + size) > (s_heap_area.heap + BSP_CFG_HEAP_BYTES))
+    {
+        /* Empty area size  */
+        p_area = (int8_t *)-1;
+    }
+    else
+    {
+        /* Area assignment */
+        p_area = sp_brk;
+
+        /* End address update */
+        sp_brk += size;
+    }
+
+    /* Return result */
+    return p_area;
+} /* End of function sbrk() */
+
+#if defined(__GNUC__)
+/***********************************************************************************************************************
+* Function name: _top_of_heap
+* Description  : This function returns end address of reserved heap area. (GNURX+OPTLIB only)
+* Arguments    : none
+* Return value : End address of reserved heap area
+***********************************************************************************************************************/
+int8_t *_top_of_heap(void)
+{
+    return (int8_t *)(s_heap_area.heap + BSP_CFG_HEAP_BYTES);
+} /* End of function End of function sbrk()() */
+#endif /* defined(__GNUC__) */
+
+#endif /* defined(__CCRX__), defined(__GNUC__) */
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
+#endif /* BSP_CFG_HEAP_BYTES */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/sbrk.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/sbrk.h
new file mode 100644
index 00000000..c05b6d19
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/all/sbrk.h
@@ -0,0 +1,84 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : sbrk.h
+* Description  : Configures the MCU heap memory.  The size of the heap is defined by the macro HEAPSIZE below.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_bsp_common.h"
+#include "r_bsp_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef SBRK_H
+#define SBRK_H
+
+/* Only use this file if heap is enabled in r_bsp_config. */
+#if BSP_CFG_HEAP_BYTES > 0
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+
+#if defined(__CCRX__) || defined(__GNUC__)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef union
+{
+    int32_t  dummy;             /* Dummy for 4-byte boundary */
+    int8_t heap[BSP_CFG_HEAP_BYTES];    /* Declaration of the area managed by sbrk*/
+} u_heap_type_t;
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+/* const size_t _sbrk_size=      // Specifies the minimum unit of */
+/* the defined heap area */
+int8_t *_s1ptr;
+
+/* Memory allocation function prototype declaration (CC-RX and GNURX+NEWLIB) */
+int8_t  *sbrk(size_t size);
+
+#if defined(__GNUC__)
+/* Memory address function prototype declaration (GNURX+OPTLIB only) */
+int8_t  *_top_of_heap(void);
+#endif /* defined(__GNUC__) */
+
+#endif /* defined(__CCRX__), defined(__GNUC__) */
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
+#endif /* BSP_CFG_HEAP_BYTES */
+
+#endif  /* SBRK_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_clocks.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_clocks.c
new file mode 100644
index 00000000..3b717d52
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_clocks.c
@@ -0,0 +1,901 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_clocks.c
+* Description  : Contains clock specific routines
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 01.10.2016 1.00     First Release
+*         : 27.07.2018 1.01     Modified the comment of get_iclk_freq_hz.
+*         : 28.02.2019 2.00     Added clock setup.
+*                               Fixed cast of get_iclk_freq_hz function.
+*                               Deleted the rom cache setting.
+*                               (The rom cache setting moved to the hardware setup file (hwsetup.c).)
+*                               Fixed coding style.
+*                               Renamed following macro definitions.
+*                               - BSP_PRV_CKSEL_LOCO
+*                               - BSP_PRV_CKSEL_HOCO
+*                               - BSP_PRV_CKSEL_MAIN_OSC
+*                               - BSP_PRV_CKSEL_SUBCLOCK
+*                               - BSP_PRV_CKSEL_PLL
+*                               - BSP_PRV_NORMALIZE_X10
+*                               Deleted the error check of BSP_CFG_CLOCK_SOURCE in the clock_source_select function.
+*         : 17.12.2019 2.01     Fixed warning of clock_source_select function with IAR compiler.
+*         : 14.02.2020 2.02     Fixed warning of clock_source_select function with CCRX and IAR compiler.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define BSP_PRV_CKSEL_LOCO            (0x0)
+#define BSP_PRV_CKSEL_HOCO            (0x1)
+#define BSP_PRV_CKSEL_MAIN_OSC        (0x2)
+#define BSP_PRV_CKSEL_SUBCLOCK        (0x3)
+#define BSP_PRV_CKSEL_PLL             (0x4)
+
+#define BSP_PRV_NORMALIZE_X10  (10)   /* used to avoid floating point arithmetic */
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+static void operating_frequency_set(void);
+static void clock_source_select(void);
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
+/***********************************************************************************************************************
+* Function Name: get_iclk_freq_hz
+* Description  : Return the current ICLK frequency in Hz.  Called by R_BSP_GetIClkFreqHz().
+*                The system clock source can be changed at any time via SYSTEM.SCKCR3.BIT.CKSEL, so in order to
+*                determine the ICLK frequency we need to first find the current system clock source and then,
+*                in some cases where the clock source can be configured for multiple frequencies, calculate the
+*                frequency at which it is currently running.
+* Arguments    : None
+* Return Value : uint32_t - the iclk frequency in Hz
+***********************************************************************************************************************/
+uint32_t get_iclk_freq_hz(void)
+{
+    uint32_t sys_clock_src_freq;
+    uint32_t pll_multiplier;
+    uint32_t pll_source_freq;
+    uint32_t hoco_frequency[3] = {16000000, 18000000, 20000000};
+
+    /* Casting is valid because it matches the type to the retern value. */
+    uint8_t  cksel = (uint8_t)SYSTEM.SCKCR3.BIT.CKSEL;
+
+    switch (cksel)
+    {
+        case BSP_PRV_CKSEL_LOCO:
+            sys_clock_src_freq = BSP_LOCO_HZ;
+            break;
+
+        case BSP_PRV_CKSEL_HOCO:
+
+            /* Set HOCO frequency. */
+            sys_clock_src_freq = hoco_frequency[SYSTEM.HOCOCR2.BIT.HCFRQ];
+            break;
+
+        case BSP_PRV_CKSEL_MAIN_OSC:
+            sys_clock_src_freq = BSP_CFG_XTAL_HZ;
+            break;
+
+        case BSP_PRV_CKSEL_SUBCLOCK:
+            sys_clock_src_freq = BSP_SUB_CLOCK_HZ;
+            break;
+
+        case BSP_PRV_CKSEL_PLL:
+
+            /* The RX65N have two possible sources for the PLL */
+
+            /* Casting is valid because it matches the type to the retern value. */
+            pll_multiplier = ((((uint32_t)(SYSTEM.PLLCR.BIT.STC + 1)) * BSP_PRV_NORMALIZE_X10) / 2);
+
+            /* Default to the MAIN OSC as the PLL source */
+            pll_source_freq = BSP_CFG_XTAL_HZ;
+
+            /* If 1 then the HOCO is the PLL source */
+            if (0x1 == SYSTEM.PLLCR.BIT.PLLSRCSEL)
+            {
+                /* Set HOCO frequency. */
+                pll_source_freq = hoco_frequency[SYSTEM.HOCOCR2.BIT.HCFRQ];
+            }
+
+            /* Casting is valid because it matches the type to the retern value. */
+            sys_clock_src_freq = ((pll_source_freq / (((uint32_t)(SYSTEM.PLLCR.BIT.PLIDIV + 1)) * BSP_PRV_NORMALIZE_X10)) * pll_multiplier);
+            break;
+
+        default:
+
+            /* Should never arrive here. Use the Main OSC freq as a default... */
+            sys_clock_src_freq = BSP_CFG_XTAL_HZ;
+            break;
+    }
+
+    /* Finally, divide the system clock source frequency by the currently set ICLK divider to get the ICLK frequency */
+    return (sys_clock_src_freq / (uint32_t)(1 << SYSTEM.SCKCR.BIT.ICK));
+} /* End of function get_iclk_freq_hz() */
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+
+/***********************************************************************************************************************
+* Function name: mcu_clock_setup
+* Description  : Contains clock functions called at device restart.
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+void mcu_clock_setup(void)
+{
+    /* Switch to high-speed operation */
+    operating_frequency_set();
+} /* End of function mcu_clock_setup() */
+
+/***********************************************************************************************************************
+* Function name: operating_frequency_set
+* Description  : Configures the clock settings for each of the device clocks
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+static void operating_frequency_set (void)
+{
+    /* Used for constructing value to write to SCKCR, SCKCR2, and SCKCR3 registers. */
+    uint32_t tmp_clock = 0;
+
+    /* Protect off. */
+    SYSTEM.PRCR.WORD = 0xA50B;
+
+    /* Select the clock based upon user's choice. */
+    clock_source_select();
+
+    /* Figure out setting for FCK bits. */
+#if   BSP_CFG_FCK_DIV == 1
+    /* Do nothing since FCK bits should be 0. */
+#elif BSP_CFG_FCK_DIV == 2
+    tmp_clock |= 0x10000000;
+#elif BSP_CFG_FCK_DIV == 4
+    tmp_clock |= 0x20000000;
+#elif BSP_CFG_FCK_DIV == 8
+    tmp_clock |= 0x30000000;
+#elif BSP_CFG_FCK_DIV == 16
+    tmp_clock |= 0x40000000;
+#elif BSP_CFG_FCK_DIV == 32
+    tmp_clock |= 0x50000000;
+#elif BSP_CFG_FCK_DIV == 64
+    tmp_clock |= 0x60000000;
+#else
+    #error "Error! Invalid setting for BSP_CFG_FCK_DIV in r_bsp_config.h"
+#endif
+
+    /* Figure out setting for ICK bits. */
+#if   BSP_CFG_ICK_DIV == 1
+    /* Do nothing since ICK bits should be 0. */
+#elif BSP_CFG_ICK_DIV == 2
+    tmp_clock |= 0x01000000;
+#elif BSP_CFG_ICK_DIV == 4
+    tmp_clock |= 0x02000000;
+#elif BSP_CFG_ICK_DIV == 8
+    tmp_clock |= 0x03000000;
+#elif BSP_CFG_ICK_DIV == 16
+    tmp_clock |= 0x04000000;
+#elif BSP_CFG_ICK_DIV == 32
+    tmp_clock |= 0x05000000;
+#elif BSP_CFG_ICK_DIV == 64
+    tmp_clock |= 0x06000000;
+#else
+    #error "Error! Invalid setting for BSP_CFG_ICK_DIV in r_bsp_config.h"
+#endif
+
+    /* Figure out setting for BCK bits. */
+#if   BSP_CFG_BCK_DIV == 1
+    /* Do nothing since BCK bits should be 0. */
+#elif BSP_CFG_BCK_DIV == 2
+    tmp_clock |= 0x00010000;
+#elif BSP_CFG_BCK_DIV == 4
+    tmp_clock |= 0x00020000;
+#elif BSP_CFG_BCK_DIV == 8
+    tmp_clock |= 0x00030000;
+#elif BSP_CFG_BCK_DIV == 16
+    tmp_clock |= 0x00040000;
+#elif BSP_CFG_BCK_DIV == 32
+    tmp_clock |= 0x00050000;
+#elif BSP_CFG_BCK_DIV == 64
+    tmp_clock |= 0x00060000;
+#else
+    #error "Error! Invalid setting for BSP_CFG_BCK_DIV in r_bsp_config.h"
+#endif
+
+    /* Configure PSTOP1 bit for BCLK output. */
+#if BSP_CFG_BCLK_OUTPUT == 0
+    /* Set PSTOP1 bit */
+    tmp_clock |= 0x00800000;
+#elif BSP_CFG_BCLK_OUTPUT == 1
+    /* Clear PSTOP1 bit */
+    tmp_clock &= ~0x00800000;
+#elif BSP_CFG_BCLK_OUTPUT == 2
+    /* Clear PSTOP1 bit */
+    tmp_clock &= ~0x00800000;
+    /* Set BCLK divider bit */
+    SYSTEM.BCKCR.BIT.BCLKDIV = 1;
+
+    /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+       This is done to ensure that the register has been written before the next register access. The RX has a 
+       pipeline architecture so the next instruction could be executed before the previous write had finished.
+    */
+    if(1 ==  SYSTEM.BCKCR.BIT.BCLKDIV)
+    {
+        R_BSP_NOP();
+    }
+#else
+    #error "Error! Invalid setting for BSP_CFG_BCLK_OUTPUT in r_bsp_config.h"
+#endif
+
+    /* Configure PSTOP0 bit for SDCLK output. */
+#if BSP_CFG_SDCLK_OUTPUT == 0
+    /* Set PSTOP0 bit */
+    tmp_clock |= 0x00400000;
+#elif BSP_CFG_SDCLK_OUTPUT == 1
+    /* Clear PSTOP0 bit */
+    tmp_clock &= ~0x00400000;
+#else
+    #error "Error! Invalid setting for BSP_CFG_SDCLK_OUTPUT in r_bsp_config.h"
+#endif
+
+    /* Figure out setting for PCKA bits. */
+#if   BSP_CFG_PCKA_DIV == 1
+    /* Do nothing since PCKA bits should be 0. */
+#elif BSP_CFG_PCKA_DIV == 2
+    tmp_clock |= 0x00001000;
+#elif BSP_CFG_PCKA_DIV == 4
+    tmp_clock |= 0x00002000;
+#elif BSP_CFG_PCKA_DIV == 8
+    tmp_clock |= 0x00003000;
+#elif BSP_CFG_PCKA_DIV == 16
+    tmp_clock |= 0x00004000;
+#elif BSP_CFG_PCKA_DIV == 32
+    tmp_clock |= 0x00005000;
+#elif BSP_CFG_PCKA_DIV == 64
+    tmp_clock |= 0x00006000;
+#else
+    #error "Error! Invalid setting for BSP_CFG_PCKA_DIV in r_bsp_config.h"
+#endif
+
+    /* Figure out setting for PCKB bits. */
+#if   BSP_CFG_PCKB_DIV == 1
+    /* Do nothing since PCKB bits should be 0. */
+#elif BSP_CFG_PCKB_DIV == 2
+    tmp_clock |= 0x00000100;
+#elif BSP_CFG_PCKB_DIV == 4
+    tmp_clock |= 0x00000200;
+#elif BSP_CFG_PCKB_DIV == 8
+    tmp_clock |= 0x00000300;
+#elif BSP_CFG_PCKB_DIV == 16
+    tmp_clock |= 0x00000400;
+#elif BSP_CFG_PCKB_DIV == 32
+    tmp_clock |= 0x00000500;
+#elif BSP_CFG_PCKB_DIV == 64
+    tmp_clock |= 0x00000600;
+#else
+    #error "Error! Invalid setting for BSP_CFG_PCKB_DIV in r_bsp_config.h"
+#endif
+
+    /* Figure out setting for PCKC bits. */
+#if   BSP_CFG_PCKC_DIV == 1
+    /* Do nothing since PCKA bits should be 0. */
+#elif BSP_CFG_PCKC_DIV == 2
+    tmp_clock |= 0x00000010;
+#elif BSP_CFG_PCKC_DIV == 4
+    tmp_clock |= 0x00000020;
+#elif BSP_CFG_PCKC_DIV == 8
+    tmp_clock |= 0x00000030;
+#elif BSP_CFG_PCKC_DIV == 16
+    tmp_clock |= 0x00000040;
+#elif BSP_CFG_PCKC_DIV == 32
+    tmp_clock |= 0x00000050;
+#elif BSP_CFG_PCKC_DIV == 64
+    tmp_clock |= 0x00000060;
+#else
+    #error "Error! Invalid setting for BSP_CFG_PCKC_DIV in r_bsp_config.h"
+#endif
+
+    /* Figure out setting for PCKD bits. */
+#if   BSP_CFG_PCKD_DIV == 1
+    /* Do nothing since PCKD bits should be 0. */
+#elif BSP_CFG_PCKD_DIV == 2
+    tmp_clock |= 0x00000001;
+#elif BSP_CFG_PCKD_DIV == 4
+    tmp_clock |= 0x00000002;
+#elif BSP_CFG_PCKD_DIV == 8
+    tmp_clock |= 0x00000003;
+#elif BSP_CFG_PCKD_DIV == 16
+    tmp_clock |= 0x00000004;
+#elif BSP_CFG_PCKD_DIV == 32
+    tmp_clock |= 0x00000005;
+#elif BSP_CFG_PCKD_DIV == 64
+    tmp_clock |= 0x00000006;
+#else
+    #error "Error! Invalid setting for BSP_CFG_PCKD_DIV in r_bsp_config.h"
+#endif
+
+    /* Set SCKCR register. */
+    SYSTEM.SCKCR.LONG = tmp_clock;
+
+    /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+       This is done to ensure that the register has been written before the next register access. The RX has a 
+       pipeline architecture so the next instruction could be executed before the previous write had finished.
+    */
+    if(tmp_clock ==  SYSTEM.SCKCR.LONG)
+    {
+        R_BSP_NOP();
+    }
+
+    /* Re-init tmp_clock to use to set SCKCR2. */
+    tmp_clock = 0;
+
+    /* Figure out setting for UCK bits. */
+#if   BSP_CFG_UCK_DIV == 2
+    tmp_clock |= 0x00000011;
+#elif BSP_CFG_UCK_DIV == 3
+    tmp_clock |= 0x00000021;
+#elif BSP_CFG_UCK_DIV == 4
+    tmp_clock |= 0x00000031;
+#elif BSP_CFG_UCK_DIV == 5
+    tmp_clock |= 0x00000041;
+#else
+    #error "Error! Invalid setting for BSP_CFG_UCK_DIV in r_bsp_config.h"
+#endif
+
+    /* Set SCKCR2 register. */
+    SYSTEM.SCKCR2.WORD = (uint16_t)tmp_clock;
+
+    /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+       This is done to ensure that the register has been written before the next register access. The RX has a 
+       pipeline architecture so the next instruction could be executed before the previous write had finished.
+    */
+    if((uint16_t)tmp_clock ==  SYSTEM.SCKCR2.WORD)
+    {
+        R_BSP_NOP();
+    }
+
+    /* Choose clock source. Default for r_bsp_config.h is PLL. */
+    tmp_clock = ((uint16_t)BSP_CFG_CLOCK_SOURCE) << 8;
+
+    /* Casting is valid because it matches the type to the retern value. */
+    SYSTEM.SCKCR3.WORD = (uint16_t)tmp_clock;
+
+    /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+       This is done to ensure that the register has been written before the next register access. The RX has a 
+       pipeline architecture so the next instruction could be executed before the previous write had finished.
+    */
+    if((uint16_t)tmp_clock ==  SYSTEM.SCKCR3.WORD)
+    {
+        R_BSP_NOP();
+    }
+
+#if BSP_CFG_CLOCK_SOURCE != 0
+    /* We can now turn LOCO off since it is not going to be used. */
+    SYSTEM.LOCOCR.BYTE = 0x01;
+
+    /* Wait for five the LOCO cycles */
+    /* 5 count of LOCO : (1000000/216000)*5 = 23.148148148us
+       23 + 2 = 25us ("+2" is overhead cycle) */
+    R_BSP_SoftwareDelay((uint32_t)25, BSP_DELAY_MICROSECS);
+#endif
+
+    /* Protect on. */
+    SYSTEM.PRCR.WORD = 0xA500;
+} /* End of function operating_frequency_set() */
+
+/***********************************************************************************************************************
+* Function name: clock_source_select
+* Description  : Enables and disables clocks as chosen by the user. This function also implements the delays
+*                needed for the clocks to stabilize.
+* Arguments    : none
+* Return value : none
+***********************************************************************************************************************/
+static void clock_source_select (void)
+{
+    volatile uint8_t i;
+    volatile uint8_t dummy;
+#if (BSP_CFG_CLOCK_SOURCE == 3) || (BSP_CFG_RTC_ENABLE == 1)
+    uint8_t tmp;
+#endif
+
+    /* Main clock will be not oscillate in software standby or deep software standby modes. */
+    SYSTEM.MOFCR.BIT.MOFXIN = 0;
+
+    /* Set the oscillation source of the main clock oscillator. */
+    SYSTEM.MOFCR.BIT.MOSEL = BSP_CFG_MAIN_CLOCK_SOURCE;
+
+    /* Use HOCO if HOCO is chosen or if PLL is chosen with HOCO as source. */
+#if (BSP_CFG_CLOCK_SOURCE == 1) || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 1))
+    /* HOCO is chosen. Start it operating if it is not already operating. */
+    if (1 == SYSTEM.HOCOCR.BIT.HCSTP)
+    {
+        /* Turn on power to HOCO. */
+        SYSTEM.HOCOPCR.BYTE = 0x00;
+
+        /* Stop HOCO. */
+        SYSTEM.HOCOCR.BYTE = 0x01;
+
+        /* WAIT_LOOP */
+        while(1 == SYSTEM.OSCOVFSR.BIT.HCOVF)
+        {
+            /* The delay period needed is to make sure that the HOCO has stopped. */
+            R_BSP_NOP();
+        }
+
+        /* Set HOCO frequency. */
+        #if   (BSP_CFG_HOCO_FREQUENCY == 0)
+        SYSTEM.HOCOCR2.BYTE = 0x00;         //16MHz
+        #elif (BSP_CFG_HOCO_FREQUENCY == 1)
+        SYSTEM.HOCOCR2.BYTE = 0x01;         //18MHz
+        #elif (BSP_CFG_HOCO_FREQUENCY == 2)
+        SYSTEM.HOCOCR2.BYTE = 0x02;         //20MHz
+        #else
+            #error "Error! Invalid setting for BSP_CFG_HOCO_FREQUENCY in r_bsp_config.h"
+        #endif
+
+        /* HOCO is chosen. Start it operating. */
+        SYSTEM.HOCOCR.BYTE = 0x00;
+
+        /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+           This is done to ensure that the register has been written before the next register access. The RX has a 
+           pipeline architecture so the next instruction could be executed before the previous write had finished.
+         */
+        if(0x00 ==  SYSTEM.HOCOCR.BYTE)
+        {
+            R_BSP_NOP();
+        }
+    }
+
+    /* WAIT_LOOP */
+    while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF)
+    {
+        /* The delay period needed is to make sure that the HOCO has stabilized. */
+        R_BSP_NOP();
+    }
+#else /* (BSP_CFG_CLOCK_SOURCE != 1) || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 0)) */
+    /* If HOCO is already operating, it doesn't stop. */
+    if (1 == SYSTEM.HOCOCR.BIT.HCSTP)
+    {
+        /* Turn off power to HOCO. */
+        SYSTEM.HOCOPCR.BYTE = 0x01;
+    }
+    else
+    {
+        /* WAIT_LOOP */
+        while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF)
+        {
+            /* The delay period needed is to make sure that the HOCO has stabilized. */
+            R_BSP_NOP();
+        }
+    }
+#endif /* (BSP_CFG_CLOCK_SOURCE == 1) || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 1)) */
+
+    /* Use Main clock if Main clock is chosen or if PLL is chosen with Main clock as source. */
+#if (BSP_CFG_CLOCK_SOURCE == 2) || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 0))
+    /* Main clock oscillator is chosen. Start it operating. */
+
+    /* If the main oscillator is >10MHz then the main clock oscillator forced oscillation control register (MOFCR) must
+       be changed. */
+    if (BSP_CFG_XTAL_HZ > 20000000)
+    {
+        /* 20 - 24MHz. */
+        SYSTEM.MOFCR.BIT.MODRV2 = 0;
+    }
+    else if (BSP_CFG_XTAL_HZ > 16000000)
+    {
+        /* 16 - 20MHz. */
+        SYSTEM.MOFCR.BIT.MODRV2 = 1;
+    }
+    else if (BSP_CFG_XTAL_HZ > 8000000)
+    {
+        /* 8 - 16MHz. */
+        SYSTEM.MOFCR.BIT.MODRV2 = 2;
+    }
+    else
+    {
+        /* 8MHz. */
+        SYSTEM.MOFCR.BIT.MODRV2 = 3;
+    }
+
+    /* Set the oscillation stabilization wait time of the main clock oscillator. */
+#if BSP_CFG_MAIN_CLOCK_SOURCE == 0 /* Resonator */
+    SYSTEM.MOSCWTCR.BYTE = BSP_CFG_MOSC_WAIT_TIME;
+#elif BSP_CFG_MAIN_CLOCK_SOURCE == 1 /* External oscillator input */
+    SYSTEM.MOSCWTCR.BYTE = 0x00;
+#else
+    #error "Error! Invalid setting for BSP_CFG_MAIN_CLOCK_SOURCE in r_bsp_config.h"
+#endif
+
+    /* Set the main clock to operating. */
+    SYSTEM.MOSCCR.BYTE = 0x00;
+
+    /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+       This is done to ensure that the register has been written before the next register access. The RX has a 
+       pipeline architecture so the next instruction could be executed before the previous write had finished.
+     */
+    if(0x00 ==  SYSTEM.MOSCCR.BYTE)
+    {
+        R_BSP_NOP();
+    }
+
+    /* WAIT_LOOP */
+    while(0 == SYSTEM.OSCOVFSR.BIT.MOOVF)
+    {
+        /* The delay period needed is to make sure that the Main clock has stabilized. */
+        R_BSP_NOP();
+    }
+#else /* (BSP_CFG_CLOCK_SOURCE != 2) || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 1)) */
+    /* Main clock is stopped after reset. */
+#endif /* (BSP_CFG_CLOCK_SOURCE == 2) || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 0)) */
+
+    /* Sub-clock setting. */
+
+    /* Cold start setting */
+    if (0 == SYSTEM.RSTSR1.BIT.CWSF)
+    {
+        /* Stop the sub-clock oscillator */
+        /* RCR4 - RTC Control Register 4
+        b7:b1    Reserved - The write value should be 0.
+        b0       RCKSEL   - Count Source Select - Sub-clock oscillator is selected. */
+        RTC.RCR4.BIT.RCKSEL = 0;
+
+        /* WAIT_LOOP */
+        for (i = 0; i < 4; i++)
+        {
+            /* dummy read four times */
+            dummy = RTC.RCR4.BYTE;
+        }
+
+        /* Confirm that the written */
+        if (0 != RTC.RCR4.BIT.RCKSEL)
+        {
+            R_BSP_NOP();
+        }
+
+        /* RCR3 - RTC Control Register 3
+        b7:b4    Reserved - The write value should be 0.
+        b3:b1    RTCDV    - Sub-clock oscillator Drive Ability Control.
+        b0       RTCEN    - Sub-clock oscillator is stopped. */
+        RTC.RCR3.BIT.RTCEN = 0;
+
+        /* WAIT_LOOP */
+        for (i = 0; i < 4; i++)
+        {
+            /* dummy read four times */
+            dummy = RTC.RCR3.BYTE;
+        }
+
+        /* Confirm that the written */
+        if (0 != RTC.RCR3.BIT.RTCEN)
+        {
+            R_BSP_NOP();
+        }
+
+        /* SOSCCR - Sub-Clock Oscillator Control Register
+        b7:b1    Reserved - The write value should be 0.
+        b0       SOSTP    - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */
+        SYSTEM.SOSCCR.BYTE = 0x01;
+
+        /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+           This is done to ensure that the register has been written before the next register access. The RX has a 
+           pipeline architecture so the next instruction could be executed before the previous write had finished.
+         */
+        if (0x01 != SYSTEM.SOSCCR.BYTE)
+        {
+            R_BSP_NOP();
+        }
+
+        /* WAIT_LOOP */
+        while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF)
+        {        
+            /* The delay period needed is to make sure that the sub-clock has stopped. */
+            R_BSP_NOP();
+        }
+
+#if (BSP_CFG_CLOCK_SOURCE == 3) || (BSP_CFG_RTC_ENABLE == 1)
+        /* Set the drive capacity of the sub-clock oscillator */
+        #if   (BSP_CFG_SOSC_DRV_CAP == 0) /* Standard CL */
+            tmp = 0x06;
+        #elif (BSP_CFG_SOSC_DRV_CAP == 1) /* Low CL */
+            tmp = 0x01;
+        #else
+            #error "Error! Invalid setting for BSP_CFG_SOSC_DRV_CAP in r_bsp_config.h"
+        #endif
+
+        /* Set the Sub-Clock Oscillator Drive Capacity Control. */
+        RTC.RCR3.BIT.RTCDV = tmp;
+
+        /* WAIT_LOOP */
+        for (i = 0; i < 4; i++)
+        {
+            /* dummy read four times */
+            dummy = RTC.RCR3.BYTE;
+        }
+
+        /* Confirm that the written */
+        if (tmp != RTC.RCR3.BIT.RTCDV)
+        {
+            R_BSP_NOP();
+        }
+
+        /* Set wait time until the sub-clock oscillator stabilizes */
+        /* SOSCWTCR - Sub-Clock Oscillator Wait Control Register
+        b7:b5    Reserved - The write value should be 0.
+        b4:b0    SSTS - Sub-Clock Oscillator Waiting Time - Waiting time is 2.044ms(the maximum value of fLOCO). */
+        SYSTEM.SOSCWTCR.BYTE = BSP_CFG_SOSC_WAIT_TIME;
+
+        /* Operate the Sub-clock oscillator */
+        SYSTEM.SOSCCR.BYTE = 0x00;
+
+        /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+           This is done to ensure that the register has been written before the next register access. The RX has a 
+           pipeline architecture so the next instruction could be executed before the previous write had finished.
+         */
+        if (0x00 != SYSTEM.SOSCCR.BYTE)
+        {
+            R_BSP_NOP();
+        }
+
+        /* WAIT_LOOP */
+        while (1 != SYSTEM.OSCOVFSR.BIT.SOOVF)
+        {
+            /* The delay period needed is to make sure that the sub-clock  has stabilized. */
+            R_BSP_NOP();
+        }
+#endif /* (BSP_CFG_CLOCK_SOURCE == 3) || (BSP_CFG_RTC_ENABLE == 1) */
+
+#if BSP_CFG_RTC_ENABLE == 1
+        /* ---- Set wait time until the sub-clock oscillator stabilizes ---- */
+        SYSTEM.SOSCWTCR.BYTE = 0x00;
+
+        /* ---- Operate the sub-clock oscillator ---- */
+        RTC.RCR3.BIT.RTCEN = 1;
+
+        /* WAIT_LOOP */
+        for (i = 0; i < 4; i++)
+        {
+             /* dummy read four times */
+             dummy = RTC.RCR3.BIT.RTCEN;
+        }
+
+        /* Confirm that the written value can be read correctly. */
+        if (1 != RTC.RCR3.BIT.RTCEN)
+        {
+            R_BSP_NOP();
+        }
+#endif
+
+#if (BSP_CFG_CLOCK_SOURCE == 3) || (BSP_CFG_RTC_ENABLE == 1)
+        /* Wait for six the sub-clock cycles */
+        /* 6 count of sub-clock : (1000000/32768)*6=183.10546875us
+           In the case of LOCO frequency is 264kHz : 183.10546875/(1000000/264000)=48.33984375cycle
+           (48.33984375+2)*(1000000/240000)=209.7493489583333us ("+2" is overhead cycle) */
+        R_BSP_SoftwareDelay((uint32_t)210, BSP_DELAY_MICROSECS);
+#endif
+
+#if (BSP_CFG_CLOCK_SOURCE == 3) && (BSP_CFG_RTC_ENABLE == 0)
+        /* Stop prescaler and counter */
+        /* RCR2 - RTC Control Register 2
+        b7  CNTMD - Count Mode Select - The calendar count mode.
+        b6  HR24  - Hours Mode - The RTC operates in 24-hour mode.
+        b5  AADJP - Automatic Adjustment Period Select - The RADJ.ADJ[5:0] setting value is adjusted from 
+                                                           the count value of the prescaler every 10 seconds.
+        b4  AADJE - Automatic Adjustment Enable - Automatic adjustment is enabled.
+        b3  RTCOE - RTCOUT Output Enable - RTCOUT output enabled.
+        b2  ADJ30 - 30-Second Adjustment - 30-second adjustment is executed.
+        b1  RESET - RTC Software Reset - The prescaler and the target registers for RTC software reset are initialized.
+        b0  START - start - Prescaler is stopped. */
+        RTC.RCR2.BYTE &= 0x7E;
+
+        /* WAIT_LOOP */
+        while (0 != RTC.RCR2.BIT.START)
+        {
+            /* Confirm that the written value can be read correctly. */
+             R_BSP_NOP();
+        }
+
+        /* RTC Software Reset */
+        RTC.RCR2.BIT.RESET = 1;
+
+        /* WAIT_LOOP */
+        while (0 != RTC.RCR2.BIT.RESET)
+        {
+            /* Confirm that the written value can be read correctly. */
+            R_BSP_NOP();
+        }
+
+        /* An alarm interrupt request is disabled */
+        /* RCR1 - RTC Control Register 1
+        b7:b4  PES   - Periodic Interrupt Select - These bits specify the period for the periodic interrupt.
+        b3     RTCOS - RTCOUT Output Select - RTCOUT outputs 1 Hz.
+        b2     PIE   - Periodic Interrupt Enable - A periodic interrupt request is disabled.
+        b1     CIE   - Carry Interrupt Enable - A carry interrupt request is disabled.
+        b0     AIE   - Alarm Interrupt Enable - An alarm interrupt request is disabled. */
+        RTC.RCR1.BYTE &= 0xF8;
+
+        /* Wait for one the sub-clock cycles */
+        /* 1 count of sub-clock : (1000000/32768)=30.517578125us
+           In the case of LOCO frequency is 264kHz : 30.517578125/(1000000/264000)=8.056640625cycle
+           (8.056640625+2)*(1000000/240000)=41.902669270833us ("+2" is overhead cycle) */
+        R_BSP_SoftwareDelay((uint32_t)42, BSP_DELAY_MICROSECS);
+
+        /* Confirm that the written value can be read correctly. */
+        if (0x00 != (RTC.RCR1.BYTE & 0x07))
+        {
+            R_BSP_NOP();
+        }
+#endif /* (BSP_CFG_CLOCK_SOURCE == 3) && (BSP_CFG_RTC_ENABLE == 0) */
+    }
+    /* Warm start setting */
+    else
+    {
+#if (BSP_CFG_CLOCK_SOURCE == 3) || ((BSP_CFG_CLOCK_SOURCE != 3) && (BSP_CFG_RTC_ENABLE == 0))
+        /* SOSCCR - Sub-Clock Oscillator Control Register
+        b7:b1    Reserved - The write value should be 0.
+        b0       SOSTP    - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */
+        SYSTEM.SOSCCR.BYTE = 0x01;
+
+        /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+           This is done to ensure that the register has been written before the next register access. The RX has a 
+           pipeline architecture so the next instruction could be executed before the previous write had finished.
+         */
+        if (0x01 != SYSTEM.SOSCCR.BYTE)
+        {
+            R_BSP_NOP();
+        }
+
+        /* WAIT_LOOP */
+        while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF)
+        {
+            /* Confirm that the Sub clock stopped. */
+            R_BSP_NOP();
+        }
+#endif
+
+#if BSP_CFG_CLOCK_SOURCE == 3
+        /* Set wait time until the sub-clock oscillator stabilizes */
+        /* SOSCWTCR - Sub-Clock Oscillator Wait Control Register
+        b7:b5    Reserved - The write value should be 0.
+        b4:b0    SSTS - Sub-Clock Oscillator Waiting Time - Waiting time is 2.044ms(the maximum value of fLOCO). */
+        SYSTEM.SOSCWTCR.BYTE = BSP_CFG_SOSC_WAIT_TIME;
+
+        /* Operate the Sub-clock oscillator */
+        SYSTEM.SOSCCR.BYTE = 0x00;
+
+        /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+           This is done to ensure that the register has been written before the next register access. The RX has a 
+           pipeline architecture so the next instruction could be executed before the previous write had finished.
+         */
+        if (0x00 != SYSTEM.SOSCCR.BYTE)
+        {
+            R_BSP_NOP();
+        }
+#endif
+
+#if (BSP_CFG_CLOCK_SOURCE == 3) || (BSP_CFG_RTC_ENABLE == 1)
+        /* WAIT_LOOP */
+        while (1 != SYSTEM.OSCOVFSR.BIT.SOOVF)
+        {
+            /* The delay period needed is to make sure that the sub-clock  has stabilized. */
+            R_BSP_NOP();
+        }
+#endif
+
+#if BSP_CFG_RTC_ENABLE == 1
+        /* ---- Set wait time until the sub-clock oscillator stabilizes ---- */
+        SYSTEM.SOSCWTCR.BYTE = 0x00;
+#endif
+    }
+
+#if BSP_CFG_CLOCK_SOURCE == 4
+
+    /* Set PLL Input Divisor. */
+    SYSTEM.PLLCR.BIT.PLIDIV = BSP_CFG_PLL_DIV - 1;
+
+    #if BSP_CFG_PLL_SRC == 0
+    /* Clear PLL clock source if PLL clock source is Main clock. */
+    SYSTEM.PLLCR.BIT.PLLSRCSEL = 0;
+    #else
+    /* Set PLL clock source if PLL clock source is HOCO clock. */
+    SYSTEM.PLLCR.BIT.PLLSRCSEL = 1;
+    #endif
+
+    /* Set PLL Multiplier. */
+    SYSTEM.PLLCR.BIT.STC = ((uint8_t)((float)BSP_CFG_PLL_MUL * 2.0f)) - 1;
+
+    /* Set the PLL to operating. */
+    SYSTEM.PLLCR2.BYTE = 0x00;
+
+    /* WAIT_LOOP */
+    while(0 == SYSTEM.OSCOVFSR.BIT.PLOVF)
+    {
+        /* The delay period needed is to make sure that the PLL has stabilized. */
+        R_BSP_NOP();
+    }
+#else
+    /* PLL is stopped after reset. */
+#endif
+
+    /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn
+       it off until another clock has been enabled and is ready to use. */
+#if BSP_CFG_CLOCK_SOURCE == 0
+    /* LOCO is chosen. This is the default out of reset. */
+#else
+    /* LOCO is not chosen but it cannot be turned off yet since it is still being used. */
+#endif
+
+    /* RX65N has a ROMWT register which controls the cycle waiting for access to code flash memory.
+       It is set as zero coming out of reset.
+       When setting ICLK to [50 MHz < ICLK <= 100 MHz], set the ROMWT.ROMWT[1:0] bits to 01b.
+       When setting ICLK to [100 MHz < ICLK <= 120 MHz], set the ROMWT.ROMWT[1:0] bits to 10b. */
+    if (BSP_ICLK_HZ > BSP_MCU_ROMWT_FREQ_THRESHOLD_02)
+    {
+        /* Set the ROMWT.ROMWT[1:0] bits to 10b. */
+        SYSTEM.ROMWT.BYTE = 0x02;
+
+        /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+           This is done to ensure that the register has been written before the next register access. The RX has a 
+           pipeline architecture so the next instruction could be executed before the previous write had finished.
+        */
+        if(0x02 == SYSTEM.ROMWT.BYTE)
+        {
+            R_BSP_NOP();
+        }
+    }
+    else if (BSP_ICLK_HZ > BSP_MCU_ROMWT_FREQ_THRESHOLD_01)
+    {
+        /* Set the ROMWT.ROMWT[1:0] bits to 01b. */
+        SYSTEM.ROMWT.BYTE = 0x01;
+
+        /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual.
+           This is done to ensure that the register has been written before the next register access. The RX has a 
+           pipeline architecture so the next instruction could be executed before the previous write had finished.
+        */
+        if(0x01 == SYSTEM.ROMWT.BYTE)
+        {
+            R_BSP_NOP();
+        }
+    }
+    else
+    {
+        /* Do nothing. */
+        R_BSP_NOP();
+    }
+
+} /* End of function clock_source_select() */
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_clocks.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_clocks.h
new file mode 100644
index 00000000..1424d3c3
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_clocks.h
@@ -0,0 +1,51 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_clocks.h
+* Description  : Contains clock specific routines.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 28.02.2019 1.00     First Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef MCU_CLOCKS_H
+#define MCU_CLOCKS_H
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+uint32_t get_iclk_freq_hz(void);
+void mcu_clock_setup(void);
+
+/* End of multiple inclusion prevention macro */
+#endif
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_info.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_info.h
new file mode 100644
index 00000000..afe2a780
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_info.h
@@ -0,0 +1,294 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_info.h
+* Device(s)    : RX65N
+* Description  : Information about the MCU.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 01.10.2016 1.00      First Release
+*         : 15.05.2017 2.00      Deleted the following macro definition.
+*                                - BSP_MCU_RX651
+*                                Changed the name of the following macro definition, because there was a mistake
+*                                in the name of macro definition.
+*                                - BSP_PACKAGE_LFQFP144 - Changed package type from LQFP to LFQFP.
+*                                - BSP_PACKAGE_LFQFP100 - Changed package type from LQFP to LFQFP.
+*                                Changed the value of the following macro definition.
+*                                - BSP_CFG_MCU_PART_PACKAGE - Changed the value from 0x6 to 0xA.
+*                                Added the following macro definition.
+*                                - BSP_MCU_RX65N_2MB
+*                                - BSP_PACKAGE_LFQFP176
+*                                - BSP_PACKAGE_LFBGA176
+*                                - BSP_PACKAGE_TFLGA177
+*                                Added the following setting.
+*                                - Setting of 177 pins.
+*                                - Setting of 176 pins.
+*                                - Setting of 2-Mbyte ROM capacity.
+*                                - Setting of 1.5-Mbyte ROM capacity.
+*         : 01.12.2017 2.01      Added EBMAPCR register set value check.
+*         : 31.10.2018 2.02      Added the following macro definition.
+*                                - BSP_PACKAGE_LFQFP64
+*                                - BSP_PACKAGE_TFBGA64
+*                                Added the following setting.
+*                                - Setting of 64 pins.
+*         : 28.02.2019 3.00      Added macro definition of MCU functions.
+*                                Added the following macro definition.
+*                                - BSP_MCU_CPU_VERSION
+*                                - CPU_CYCLES_PER_LOOP
+*                                - BSP_MCU_ROMWT_FREQ_THRESHOLD_01
+*                                - BSP_MCU_ROMWT_FREQ_THRESHOLD_02
+*                                Added the error check of BSP_CFG_CLOCK_SOURCE.
+*                                Added the following enumeration constant.
+*                                - BSP_MCU_GROUP_INTERRUPT_BE0
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Gets MCU configuration information. */
+#include "r_bsp_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef MCU_INFO
+#define MCU_INFO
+
+/* MCU CPU Version */
+#define BSP_MCU_CPU_VERSION    (2)
+
+/* CPU cycles. Known number of RXv2 CPU cycles required to execute the delay_wait() loop */
+#define CPU_CYCLES_PER_LOOP    (4)
+
+/* MCU Series. */
+#if BSP_CFG_MCU_PART_SERIES == 0x0
+    #define BSP_MCU_SERIES_RX600    (1)
+#else
+    #error "ERROR - BSP_CFG_MCU_PART_SERIES - Unknown MCU Series chosen in r_bsp_config.h"
+#endif
+
+/* This macro means that this MCU is part of the RX65x collection of MCUs (i.e. RX651/N). */
+#define BSP_MCU_RX65_ALL            (1)
+
+/* MCU Group name. */
+#if BSP_CFG_MCU_PART_GROUP == 0x0
+    #define BSP_MCU_RX65N           (1)
+    #if (BSP_CFG_MCU_PART_MEMORY_SIZE == 0xC) || (BSP_CFG_MCU_PART_MEMORY_SIZE == 0xE)
+        #define BSP_MCU_RX65N_2MB   (1)
+    #endif
+#else
+    #error "ERROR - BSP_CFG_MCU_PART_GROUP - Unknown MCU Group chosen in r_bsp_config.h"
+#endif
+
+/* Package. */
+#if   BSP_CFG_MCU_PART_PACKAGE == 0x0
+    #define BSP_PACKAGE_LFQFP176    (1)
+    #define BSP_PACKAGE_PINS        (176)
+#elif BSP_CFG_MCU_PART_PACKAGE == 0x1
+    #define BSP_PACKAGE_LFBGA176    (1)
+    #define BSP_PACKAGE_PINS        (176)
+#elif BSP_CFG_MCU_PART_PACKAGE == 0x2
+    #define BSP_PACKAGE_TFLGA177    (1)
+    #define BSP_PACKAGE_PINS        (177)
+#elif BSP_CFG_MCU_PART_PACKAGE == 0x3
+    #define BSP_PACKAGE_LFQFP144    (1)
+    #define BSP_PACKAGE_PINS        (144)
+#elif BSP_CFG_MCU_PART_PACKAGE == 0x4
+    #define BSP_PACKAGE_TFLGA145    (1)
+    #define BSP_PACKAGE_PINS        (145)
+#elif BSP_CFG_MCU_PART_PACKAGE == 0x5
+    #define BSP_PACKAGE_LFQFP100    (1)
+    #define BSP_PACKAGE_PINS        (100)
+#elif BSP_CFG_MCU_PART_PACKAGE == 0x8
+    #define BSP_PACKAGE_LFQFP64     (1)
+    #define BSP_PACKAGE_PINS        (64)
+#elif BSP_CFG_MCU_PART_PACKAGE == 0xA
+    #define BSP_PACKAGE_TFLGA100    (1)
+    #define BSP_PACKAGE_PINS        (100)
+#elif BSP_CFG_MCU_PART_PACKAGE == 0xC
+    #define BSP_PACKAGE_TFBGA64     (1)
+    #define BSP_PACKAGE_PINS        (64)
+#else
+    #error "ERROR - BSP_CFG_MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h"
+#endif
+
+/* Memory size of your MCU. */
+#if   BSP_CFG_MCU_PART_MEMORY_SIZE == 0x4
+    #define BSP_ROM_SIZE_BYTES              (524288)
+    #define BSP_RAM_SIZE_BYTES              (262144)
+    #define BSP_DATA_FLASH_SIZE_BYTES       (0)
+#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x7
+    #define BSP_ROM_SIZE_BYTES              (786432)
+    #define BSP_RAM_SIZE_BYTES              (262144)
+    #define BSP_DATA_FLASH_SIZE_BYTES       (0)
+#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x9
+    #define BSP_ROM_SIZE_BYTES              (1048576)
+    #define BSP_RAM_SIZE_BYTES              (262144)
+    #define BSP_DATA_FLASH_SIZE_BYTES       (0)
+#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0xC
+    #define BSP_ROM_SIZE_BYTES              (1572864)
+    #define BSP_RAM_SIZE_BYTES              (655360)
+    #define BSP_DATA_FLASH_SIZE_BYTES       (32768)
+#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0xE
+    #define BSP_ROM_SIZE_BYTES              (2097152)
+    #define BSP_RAM_SIZE_BYTES              (655360)
+    #define BSP_DATA_FLASH_SIZE_BYTES       (32768)
+#else
+    #error "ERROR - BSP_CFG_MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h"
+#endif
+
+/* These macros define clock speeds for fixed speed clocks. */
+#define BSP_LOCO_HZ                         (240000)
+#define BSP_SUB_CLOCK_HZ                    (32768)
+
+/* Define frequency of HOCO. */
+#if   BSP_CFG_HOCO_FREQUENCY == 0
+    #define BSP_HOCO_HZ                     (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+    #define BSP_HOCO_HZ                     (18000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+    #define BSP_HOCO_HZ                     (20000000)
+#else
+    #error "ERROR - Invalid HOCO frequency chosen in r_bsp_config.h! Set valid value for BSP_CFG_HOCO_FREQUENCY."
+#endif
+
+/* Clock source select (CKSEL).
+   0 = Low Speed On-Chip Oscillator  (LOCO)
+   1 = High Speed On-Chip Oscillator (HOCO)
+   2 = Main Clock Oscillator
+   3 = Sub-Clock Oscillator
+   4 = PLL Circuit
+*/ 
+#if   BSP_CFG_CLOCK_SOURCE == 0
+    #define BSP_SELECTED_CLOCK_HZ       (BSP_LOCO_HZ)
+#elif BSP_CFG_CLOCK_SOURCE == 1
+    #define BSP_SELECTED_CLOCK_HZ       (BSP_HOCO_HZ)
+#elif BSP_CFG_CLOCK_SOURCE == 2
+    #define BSP_SELECTED_CLOCK_HZ       (BSP_CFG_XTAL_HZ)
+#elif BSP_CFG_CLOCK_SOURCE == 3
+    #define BSP_SELECTED_CLOCK_HZ       (BSP_SUB_CLOCK_HZ)
+#elif BSP_CFG_CLOCK_SOURCE == 4
+    #if   BSP_CFG_PLL_SRC == 0
+        #define BSP_SELECTED_CLOCK_HZ   ((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL)
+    #elif BSP_CFG_PLL_SRC == 1
+        #define BSP_SELECTED_CLOCK_HZ   ((BSP_HOCO_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL)
+    #else
+        #error "ERROR - Valid PLL clock source must be chosen in r_bsp_config.h using BSP_CFG_PLL_SRC macro."
+    #endif
+#else
+    #error "ERROR - BSP_CFG_CLOCK_SOURCE - Unknown clock source chosen in r_bsp_config.h"
+#endif
+
+#if defined(BSP_MCU_RX65N_2MB)
+/*    Extended Bus Master Priority setting
+   0 = GLCDC graphics 1 data read
+   1 = DRW2D texture data read
+   2 = DRW2D frame buffer data read write and display list data read
+   3 = GLCDC graphics 2 data read
+   4 = EDMAC
+   
+   Note : Settings other than above are prohibited.
+          Duplicate priority settings can not be made.
+*/
+#if (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_2ND_PRIORITY) ||\
+    (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\
+    (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\
+    (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\
+    (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\
+    (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\
+    (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\
+    (BSP_CFG_EBMAPCR_3RD_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\
+    (BSP_CFG_EBMAPCR_3RD_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\
+    (BSP_CFG_EBMAPCR_4TH_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY)
+ #error "Error! Invalid setting for Extended Bus Master Priority in r_bsp_config.h. Please check BSP_CFG_EX_BUS_1ST_PRIORITY to BSP_CFG_EX_BUS_5TH_PRIORITY"
+#endif
+#if (5 <= BSP_CFG_EBMAPCR_1ST_PRIORITY) ||\
+    (5 <= BSP_CFG_EBMAPCR_2ND_PRIORITY) ||\
+    (5 <= BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\
+    (5 <= BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\
+    (5 <= BSP_CFG_EBMAPCR_5TH_PRIORITY)
+ #error "Error! Invalid setting for Extended Bus Master Priority in r_bsp_config.h. Please check BSP_CFG_EX_BUS_1ST_PRIORITY to BSP_CFG_EX_BUS_5TH_PRIORITY"
+#endif
+#endif/* BSP_MCU_RX65N_2MB */
+
+/* System clock speed in Hz. */
+#define BSP_ICLK_HZ                 (BSP_SELECTED_CLOCK_HZ / BSP_CFG_ICK_DIV)
+/* Peripheral Module Clock A speed in Hz. Used for ETHERC and EDMAC. */
+#define BSP_PCLKA_HZ                (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKA_DIV)
+/* Peripheral Module Clock B speed in Hz. */
+#define BSP_PCLKB_HZ                (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKB_DIV)
+/* Peripheral Module Clock C speed in Hz. */
+#define BSP_PCLKC_HZ                (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKC_DIV)
+/* Peripheral Module Clock D speed in Hz. */
+#define BSP_PCLKD_HZ                (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKD_DIV)
+/* External bus clock speed in Hz. */
+#define BSP_BCLK_HZ                 (BSP_SELECTED_CLOCK_HZ / BSP_CFG_BCK_DIV)
+/* FlashIF clock speed in Hz. */
+#define BSP_FCLK_HZ                 (BSP_SELECTED_CLOCK_HZ / BSP_CFG_FCK_DIV)
+/* USB clock speed in Hz. */
+#define BSP_UCLK_HZ                 (BSP_SELECTED_CLOCK_HZ / BSP_CFG_UCK_DIV)
+
+/* Null argument definitions. */
+#define FIT_NO_FUNC                 ((void (*)(void *))0x10000000)  /* Reserved space on RX */
+#define FIT_NO_PTR                  ((void *)0x10000000)            /* Reserved space on RX */
+
+/* Mininum and maximum IPL levels available for this MCU. */
+#define BSP_MCU_IPL_MAX             (0xF)
+#define BSP_MCU_IPL_MIN             (0)
+
+/* Frequency threshold of rom wait cycle setting. */
+#define BSP_MCU_ROMWT_FREQ_THRESHOLD_01 (50000000)         /* ICLK > 50MHz requires ROMWT register update */
+#define BSP_MCU_ROMWT_FREQ_THRESHOLD_02 (100000000)        /* ICLK > 100MHz requires ROMWT register update */
+
+/* MCU functions */
+#define BSP_MCU_REGISTER_WRITE_PROTECTION
+#define BSP_MCU_RCPC_PRC0
+#define BSP_MCU_RCPC_PRC1
+#define BSP_MCU_RCPC_PRC3
+#define BSP_MCU_FLOATING_POINT
+#define BSP_MCU_EXCEPTION_TABLE
+#define BSP_MCU_GROUP_INTERRUPT
+#define BSP_MCU_GROUP_INTERRUPT_BE0
+#define BSP_MCU_GROUP_INTERRUPT_BL0
+#define BSP_MCU_GROUP_INTERRUPT_BL1
+#define BSP_MCU_GROUP_INTERRUPT_BL2
+#define BSP_MCU_GROUP_INTERRUPT_AL0
+#define BSP_MCU_GROUP_INTERRUPT_AL1
+#define BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT
+#define BSP_MCU_EXCEP_SUPERVISOR_INST_ISR
+#define BSP_MCU_EXCEP_ACCESS_ISR
+#define BSP_MCU_EXCEP_UNDEFINED_INST_ISR
+#define BSP_MCU_EXCEP_FLOATING_POINT_ISR
+#define BSP_MCU_NON_MASKABLE_ISR
+#define BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR
+#define BSP_MCU_BUS_ERROR_ISR
+
+#define BSP_MCU_NMI_EXC_NMI_PIN
+#define BSP_MCU_NMI_OSC_STOP_DETECT
+#define BSP_MCU_NMI_WDT_ERROR
+#define BSP_MCU_NMI_IWDT_ERROR
+#define BSP_MCU_NMI_LVD1
+#define BSP_MCU_NMI_LVD2
+#define BSP_MCU_NMI_RAM
+#define BSP_MCU_NMI_RAM_EXRAM
+
+#endif /* MCU_INFO */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_init.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_init.c
new file mode 100644
index 00000000..2eb1fa1e
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_init.c
@@ -0,0 +1,216 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_init.c
+* Description  : Performs initialization common to all MCUs in this Group
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 01.10.2016 1.00     First Release
+*         : 15.05.2017 2.00     Added port setting of 177 pins and 176 pins.
+*                               Added setting of PORTG.
+*         : 31.10.2018 2.01     Added port setting of 64 pins.
+*         : 28.02.2019 2.02     Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Get specifics on this MCU. */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* RX MCUs come in different packages and different pin counts. For MCUs that do not have the maximum number of pins
+ * for their group (e.g. MCU with 100 pins when maximum is 177 pins) these 'non-existent' pins that are not bonded out
+ * need to be initialized to save power. The macros below define the non-existent pins on each port for smaller
+ * pin count MCUs. If a pin is non-existent then its value is set to a 1. These values are then ORed into the
+ * direction registers to set non-existent pins as outputs which can help save power.
+ */
+#if   (BSP_PACKAGE_PINS == 177) || (BSP_PACKAGE_PINS == 176)
+    #define BSP_PRV_PORT0_NE_PIN_MASK     (0x50)    /* Missing pins: P04 P06 */
+    #define BSP_PRV_PORT1_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT2_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT3_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT4_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT5_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT6_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT7_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT8_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT9_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTA_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTB_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTC_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTD_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTE_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTF_NE_PIN_MASK     (0xC0)    /* Missing pins: PF6 PF7 */
+    #define BSP_PRV_PORTG_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTJ_NE_PIN_MASK     (0xD0)    /* Missing pins: PJ4 PJ6 PJ7 */
+#elif (BSP_PACKAGE_PINS == 145) || (BSP_PACKAGE_PINS == 144)
+    #define BSP_PRV_PORT0_NE_PIN_MASK     (0x50)    /* Missing pins: P04 P06 */
+    #define BSP_PRV_PORT1_NE_PIN_MASK     (0x03)    /* Missing pins: P10 P11 */
+    #define BSP_PRV_PORT2_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT3_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT4_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT5_NE_PIN_MASK     (0x80)    /* Missing pins: P57 */
+    #define BSP_PRV_PORT6_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT7_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT8_NE_PIN_MASK     (0x30)    /* Missing pins: P84 P85 */
+    #define BSP_PRV_PORT9_NE_PIN_MASK     (0xF0)    /* Missing pins: P94 P95 P96 P97 */
+    #define BSP_PRV_PORTA_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTB_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTC_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTD_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTE_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTF_NE_PIN_MASK     (0xDF)    /* Missing pins: PF0 PF1 PF2 PF3 PF4 PF6 PF7 */
+#if defined(BSP_MCU_RX65N_2MB)
+    #define BSP_PRV_PORTG_NE_PIN_MASK     (0xFF)    /* Missing pins: PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 */
+#endif
+    #define BSP_PRV_PORTJ_NE_PIN_MASK     (0xD7)    /* Missing pins: PJ0 PJ1 PJ2 PJ4 PJ6 PJ7 */
+#elif BSP_PACKAGE_PINS == 100
+    #define BSP_PRV_PORT0_NE_PIN_MASK     (0x5F)    /* Missing pins: P00 P01 P02 P03 P04 P06 */
+    #define BSP_PRV_PORT1_NE_PIN_MASK     (0x03)    /* Missing pins: P10 P11 */
+    #define BSP_PRV_PORT2_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT3_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT4_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORT5_NE_PIN_MASK     (0xC0)    /* Missing pins: P56 P57 */
+    #define BSP_PRV_PORT6_NE_PIN_MASK     (0xFF)    /* Missing pins: P60 P61 P62 P63 P64 P65 P66 P67 */
+    #define BSP_PRV_PORT7_NE_PIN_MASK     (0xFF)    /* Missing pins: P70 P71 P72 P73 P74 P75 P76 P77 */
+    #define BSP_PRV_PORT8_NE_PIN_MASK     (0xFF)    /* Missing pins: P80 P81 P82 P83 P84 P85 P86 P87 */
+    #define BSP_PRV_PORT9_NE_PIN_MASK     (0xFF)    /* Missing pins: P90 P91 P92 P93 P94 P95 P96 P97 */
+    #define BSP_PRV_PORTA_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTB_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTC_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTD_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTE_NE_PIN_MASK     (0x00)    /* Missing pins: None */
+    #define BSP_PRV_PORTF_NE_PIN_MASK     (0xFF)    /* Missing pins: PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 */
+#if defined(BSP_MCU_RX65N_2MB)
+    #define BSP_PRV_PORTG_NE_PIN_MASK     (0xFF)    /* Missing pins: PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 */
+#endif
+    #define BSP_PRV_PORTJ_NE_PIN_MASK     (0xF7)    /* Missing pins: PJ0 PJ1 PJ2 PJ4 PJ5 PJ6 PJ7 */
+#elif BSP_PACKAGE_PINS == 64
+    #if BSP_CFG_MCU_PART_PACKAGE == 0xC
+    #define BSP_PRV_PORT0_NE_PIN_MASK     (0xFF)    /* Missing pins: P00 P01 P02 P03 P04 P05 P06 P07 */
+    #else
+    #define BSP_PRV_PORT0_NE_PIN_MASK     (0xDF)    /* Missing pins: P00 P01 P02 P03 P04 P06 P07 */
+    #endif
+    #define BSP_PRV_PORT1_NE_PIN_MASK     (0x33)    /* Missing pins: P10 P11 P14 P15 */
+    #define BSP_PRV_PORT2_NE_PIN_MASK     (0x3F)    /* Missing pins: P20 P21 P22 P23 P24 P25 */
+    #define BSP_PRV_PORT3_NE_PIN_MASK     (0x0C)    /* Missing pins: P32 P33 */
+    #define BSP_PRV_PORT4_NE_PIN_MASK     (0xF0)    /* Missing pins: P44 P45 P46 P47 */
+    #define BSP_PRV_PORT5_NE_PIN_MASK     (0xF7)    /* Missing pins: P50 P51 P52 P54 P55 P56 P57 */
+    #define BSP_PRV_PORT6_NE_PIN_MASK     (0xFF)    /* Missing pins: P60 P61 P62 P63 P64 P65 P66 P67 */
+    #define BSP_PRV_PORT7_NE_PIN_MASK     (0xFF)    /* Missing pins: P70 P71 P72 P73 P74 P75 P76 P77 */
+    #define BSP_PRV_PORT8_NE_PIN_MASK     (0xFF)    /* Missing pins: P80 P81 P82 P83 P84 P85 P86 P87 */
+    #define BSP_PRV_PORT9_NE_PIN_MASK     (0xFF)    /* Missing pins: P90 P91 P92 P93 P94 P95 P96 P97 */
+    #define BSP_PRV_PORTA_NE_PIN_MASK     (0x29)    /* Missing pins: PA0 PA3 PA5 */
+    #define BSP_PRV_PORTB_NE_PIN_MASK     (0x1F)    /* Missing pins: PB0 PB1 PB2 PB3 PB4 */
+    #define BSP_PRV_PORTC_NE_PIN_MASK     (0x0C)    /* Missing pins: PC2 PC3 */
+    #define BSP_PRV_PORTD_NE_PIN_MASK     (0x03)    /* Missing pins: PD0 PD1 */
+    #define BSP_PRV_PORTE_NE_PIN_MASK     (0x38)    /* Missing pins: PE3 PE4 PE5 */
+    #define BSP_PRV_PORTF_NE_PIN_MASK     (0xFF)    /* Missing pins: PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 */
+    #define BSP_PRV_PORTG_NE_PIN_MASK     (0xFF)    /* Missing pins: PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 */
+    #define BSP_PRV_PORTJ_NE_PIN_MASK     (0xFF)    /* Missing pins: PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 */
+
+#else
+    #error "ERROR - This package is not defined in mcu_init.c"
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: bsp_non_existent_port_init
+* Description  : For MCUs that do not have the maximum number of pins for their group (e.g. MCU with 100 pins when
+*                maximum is 177 pins) these 'non-existent' pins that are not bonded out need to be initialized to save
+*                power.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+void bsp_non_existent_port_init (void)
+{
+    /* OR in missing pin masks from above. */
+
+    /* Set PORT0.PDR */
+    PORT0.PDR.BYTE |= BSP_PRV_PORT0_NE_PIN_MASK;
+
+    /* Set PORT1.PDR */
+    PORT1.PDR.BYTE |= BSP_PRV_PORT1_NE_PIN_MASK;
+
+    /* Set PORT2.PDR */
+    PORT2.PDR.BYTE |= BSP_PRV_PORT2_NE_PIN_MASK;
+
+    /* Set PORT3.PDR */
+    PORT3.PDR.BYTE |= BSP_PRV_PORT3_NE_PIN_MASK;
+
+    /* Set PORT4.PDR */
+    PORT4.PDR.BYTE |= BSP_PRV_PORT4_NE_PIN_MASK;
+
+    /* Set PORT5.PDR */
+    PORT5.PDR.BYTE |= BSP_PRV_PORT5_NE_PIN_MASK;
+
+    /* Set PORT6.PDR */
+    PORT6.PDR.BYTE |= BSP_PRV_PORT6_NE_PIN_MASK;
+
+    /* Set PORT7.PDR */
+    PORT7.PDR.BYTE |= BSP_PRV_PORT7_NE_PIN_MASK;
+
+    /* Set PORT8.PDR */
+    PORT8.PDR.BYTE |= BSP_PRV_PORT8_NE_PIN_MASK;
+
+    /* Set PORT9.PDR */
+    PORT9.PDR.BYTE |= BSP_PRV_PORT9_NE_PIN_MASK;
+
+    /* Set PORTA.PDR */
+    PORTA.PDR.BYTE |= BSP_PRV_PORTA_NE_PIN_MASK;
+
+    /* Set PORTB.PDR */
+    PORTB.PDR.BYTE |= BSP_PRV_PORTB_NE_PIN_MASK;
+
+    /* Set PORTC.PDR */
+    PORTC.PDR.BYTE |= BSP_PRV_PORTC_NE_PIN_MASK;
+
+    /* Set PORTD.PDR */
+    PORTD.PDR.BYTE |= BSP_PRV_PORTD_NE_PIN_MASK;
+
+    /* Set PORTE.PDR */
+    PORTE.PDR.BYTE |= BSP_PRV_PORTE_NE_PIN_MASK;
+
+    /* Set PORTF.PDR */
+    PORTF.PDR.BYTE |= BSP_PRV_PORTF_NE_PIN_MASK;
+#if defined(BSP_MCU_RX65N_2MB)
+
+    /* Set PORTG.PDR */
+    PORTG.PDR.BYTE |= BSP_PRV_PORTG_NE_PIN_MASK;
+#endif
+
+    /* Set PORTJ.PDR */
+    PORTJ.PDR.BYTE |= BSP_PRV_PORTJ_NE_PIN_MASK;
+} /* End of function bsp_non_existent_port_init() */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_init.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_init.h
new file mode 100644
index 00000000..b8756276
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_init.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_init.h
+* Description  : Performs initialization common to all MCUs in this Group
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 01.10.2016 1.00     First Release
+*         : 28.02.2019 1.01     Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef MCU_INIT_H
+#define MCU_INIT_H
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+void bsp_non_existent_port_init(void);      //r_bsp internal function. DO NOT CALL.
+
+#endif /* MCU_INIT_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_interrupts.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_interrupts.c
new file mode 100644
index 00000000..d889dd23
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_interrupts.c
@@ -0,0 +1,758 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_interrupts.c
+* Description  : This module is the control of the interrupt enable.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 01.10.2016 1.00      First Release
+*         : 15.05.2017 2.00      Added callback processing of the following group interrupt sources.
+*                                - RIIC1_EEI1
+*                                - RIIC1_TEI1
+*                                - GLCDC_VPOS
+*                                - GLCDC_GR1UF
+*                                - GLCDC_GR2UF
+*                                - DRW2D_DRW_IRQ
+*                                Changed calling order of callback function in group interrupts.
+*         : 27.07.2018 2.01      Added the comment to for statement.
+*         : 28.02.2019 3.00      Deleted the following functions. 
+*                                (The following functions moved to the common file (r_bsp_interrupts.c).)
+*                                - bsp_interrupt_open
+*                                - bsp_interrupt_group_enable_disable
+*                                  (And, changed the function name to bsp_gr_int_enable_disable.h.)
+*                                - R_BSP_InterruptWrite
+*                                - R_BSP_InterruptRead
+*                                - R_BSP_InterruptControl
+*                                Deleted the following definition.
+*                                (The following definition moved to the common file (r_bsp_common.h).)
+*                                - INTERNAL_NOT_USED(p)
+*                                Replaced the setting of IEN bit.
+*                                Added support for GNUC and ICCRX.
+*                                Fixed coding style.
+*                                Added support Group BE0 interrupts.
+*                                Modified the bsp_interrupt_group_enable_disable function.
+*                                Added the group_be0_handler_isr function.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Access to r_bsp. */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Let FPSW EV, EO, EZ, EU, EX=1 (FPU exceptions enabled.) */
+#define BSP_PRV_FPU_EXCEPTIONS_ENABLE       (0x00007C00)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl0_handler_isr, VECT(ICU,GROUPBL0))
+R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl1_handler_isr, VECT(ICU,GROUPBL1))
+R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl2_handler_isr, VECT(ICU,GROUPBL2))
+R_BSP_PRAGMA_STATIC_INTERRUPT(group_al0_handler_isr, VECT(ICU,GROUPAL0))
+R_BSP_PRAGMA_STATIC_INTERRUPT(group_al1_handler_isr, VECT(ICU,GROUPAL1))
+R_BSP_PRAGMA_STATIC_INTERRUPT(group_be0_handler_isr, VECT(ICU,GROUPBE0))
+
+/***********************************************************************************************************************
+* Function Name: bsp_interrupt_enable_disable
+* Description  : Either enables or disables an interrupt.
+* Arguments    : vector -
+*                    Which vector to enable or disable.
+*                enable -
+*                    Whether to enable or disable the interrupt.
+* Return Value : BSP_INT_SUCCESS -
+*                    Interrupt enabled or disabled.
+*                BSP_INT_ERR_UNSUPPORTED -
+*                    API does not support enabling/disabling for this vector.
+***********************************************************************************************************************/
+bsp_int_err_t bsp_interrupt_enable_disable (bsp_int_src_t vector, bool enable)
+{
+#ifdef __FPU
+    uint32_t      tmp_fpsw;
+#endif
+    bsp_int_err_t err = BSP_INT_SUCCESS;
+
+    switch (vector)
+    {
+        case (BSP_INT_SRC_BUS_ERROR):
+            if (true == enable)
+            {
+                /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */
+                /* Clear any pending interrupts */
+                IR(BSC,BUSERR) = 0;
+
+                /* Make this the highest priority interrupt (adjust as necessary for your application */
+                IPR(BSC,BUSERR) = 0x0F;
+
+                /* Enable the interrupt in the ICU*/
+                R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR));
+
+                /* Enable illegal address interrupt in the BSC */
+                BSC.BEREN.BIT.IGAEN = 1;
+
+                /* Enable timeout detection enable. */
+                BSC.BEREN.BIT.TOEN = 1;
+            }
+            else
+            {
+                /* Disable the bus error interrupt. */
+                /* Disable the interrupt in the ICU*/
+                R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR));
+
+                /* Disable illegal address interrupt in the BSC */
+                BSC.BEREN.BIT.IGAEN = 0;
+
+                /* Disable timeout detection enable. */
+                BSC.BEREN.BIT.TOEN = 0;
+            }
+            break;
+
+#ifdef __FPU
+        case (BSP_INT_SRC_EXC_FPU):
+
+            /* Get current FPSW. */
+            tmp_fpsw = (uint32_t)R_BSP_GET_FPSW();
+
+            if (true == enable)
+            {
+                /* Set the FPU exception flags. */
+                R_BSP_SET_FPSW((tmp_fpsw | (uint32_t)BSP_PRV_FPU_EXCEPTIONS_ENABLE));
+            }
+            else
+            {
+                /* Clear only the FPU exception flags. */
+                R_BSP_SET_FPSW((tmp_fpsw & (uint32_t)~BSP_PRV_FPU_EXCEPTIONS_ENABLE));
+            }
+            break;
+#endif
+
+        case (BSP_INT_SRC_EXC_NMI_PIN):
+            if (true == enable)
+            {
+                /* Enable NMI pin interrupt (cannot undo!) */
+                ICU.NMIER.BIT.NMIEN = 1;
+            }
+            else
+            {
+                /* NMI pin interrupts cannot be disabled after being enabled. */
+                err = BSP_INT_ERR_UNSUPPORTED;
+            }
+            break;
+
+        default:
+            err = BSP_INT_ERR_UNSUPPORTED;
+            break;
+    }
+
+    return err;
+} /* End of function bsp_interrupt_enable_disable() */
+
+/***********************************************************************************************************************
+* Function Name: group_bl0_handler_isr
+* Description  : Interrupt handler for Group BL0 interrupts. The way this code works is that for each possible interrupt
+*                in this group the following will be performed:
+*                1) Test to see if an interrupt is requested for this source
+*                2) If an interrupt is requested then the registered callback is called (if one is registered)
+*                NOTE: The interrupt request flag must be cleared in the peripheral.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl0_handler_isr (void)
+{
+    /* BL0 IS1 */
+    if (1 == ICU.GRPBL0.BIT.IS1)
+    {
+        /* BSP_INT_SRC_BL0_SCI0_ERI0 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI0_ERI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS0 */
+    if (1 == ICU.GRPBL0.BIT.IS0)
+    {
+        /* BSP_INT_SRC_BL0_SCI0_TEI0 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS3 */
+    if (1 == ICU.GRPBL0.BIT.IS3)
+    {
+        /* BSP_INT_SRC_BL0_SCI1_ERI1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_ERI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS2 */
+    if (1 == ICU.GRPBL0.BIT.IS2)
+    {
+        /* BSP_INT_SRC_BL0_SCI1_TEI1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS5 */
+    if (1 == ICU.GRPBL0.BIT.IS5)
+    {
+        /* BSP_INT_SRC_BL0_SCI2_ERI2 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI2_ERI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS4 */
+    if (1 == ICU.GRPBL0.BIT.IS4)
+    {
+        /* BSP_INT_SRC_BL0_SCI2_TEI2 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI2_TEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS7 */
+    if (1 == ICU.GRPBL0.BIT.IS7)
+    {
+        /* BSP_INT_SRC_BL0_SCI3_ERI3 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI3_ERI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS6 */
+    if (1 == ICU.GRPBL0.BIT.IS6)
+    {
+        /* BSP_INT_SRC_BL0_SCI3_TEI3 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI3_TEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS9 */
+    if (1 == ICU.GRPBL0.BIT.IS9)
+    {
+        /* BSP_INT_SRC_BL0_SCI4_ERI4 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI4_ERI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS8 */
+    if (1 == ICU.GRPBL0.BIT.IS8)
+    {
+        /* BSP_INT_SRC_BL0_SCI4_TEI4 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI4_TEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS11 */
+    if (1 == ICU.GRPBL0.BIT.IS11)
+    {
+        /* BSP_INT_SRC_BL0_SCI5_ERI5 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_ERI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS10 */
+    if (1 == ICU.GRPBL0.BIT.IS10)
+    {
+        /* BSP_INT_SRC_BL0_SCI5_TEI5 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_TEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS13 */
+    if (1 == ICU.GRPBL0.BIT.IS13)
+    {
+        /* BSP_INT_SRC_BL0_SCI6_ERI6 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_ERI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS12 */
+    if (1 == ICU.GRPBL0.BIT.IS12)
+    {
+        /* BSP_INT_SRC_BL0_SCI6_TEI6 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_TEI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS15 */
+    if (1 == ICU.GRPBL0.BIT.IS15)
+    {
+        /* BSP_INT_SRC_BL0_SCI7_ERI7 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI7_ERI7, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS14 */
+    if (1 == ICU.GRPBL0.BIT.IS14)
+    {
+        /* BSP_INT_SRC_BL0_SCI7_TEI7 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI7_TEI7, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS17 */
+    if (1 == ICU.GRPBL0.BIT.IS17)
+    {
+        /* BSP_INT_SRC_BL0_SCI12_ERI12 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_ERI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS16 */
+    if (1 == ICU.GRPBL0.BIT.IS16)
+    {
+        /* BSP_INT_SRC_BL0_SCI12_TEI12 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_TEI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS18 */
+    if (1 == ICU.GRPBL0.BIT.IS18)
+    {
+        /* BSP_INT_SRC_BL0_SCI12_SCIX0 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS19 */
+    if (1 == ICU.GRPBL0.BIT.IS19)
+    {
+        /* BSP_INT_SRC_BL0_SCI12_SCIX1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS20 */
+    if (1 == ICU.GRPBL0.BIT.IS20)
+    {
+        /* BSP_INT_SRC_BL0_SCI12_SCIX2 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS21 */
+    if (1 == ICU.GRPBL0.BIT.IS21)
+    {
+        /* BSP_INT_SRC_BL0_SCI12_SCIX3 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS24 */
+    if (1 == ICU.GRPBL0.BIT.IS24)
+    {
+        /* BSP_INT_SRC_BL0_QSPI_QSPSSLI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_QSPI_QSPSSLI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS26 */
+    if (1 == ICU.GRPBL0.BIT.IS26)
+    {
+        /* BSP_INT_SRC_BL0_CAC_FERRI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_FERRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS27 */
+    if (1 == ICU.GRPBL0.BIT.IS27)
+    {
+        /* BSP_INT_SRC_BL0_CAC_MENDI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_MENDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS28 */
+    if (1 == ICU.GRPBL0.BIT.IS28)
+    {
+        /* BSP_INT_SRC_BL0_CAC_OVFI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_OVFI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS29 */
+    if (1 == ICU.GRPBL0.BIT.IS29)
+    {
+        /* BSP_INT_SRC_BL0_DOC_DOPCI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_DOC_DOPCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS31 */
+    if (1 == ICU.GRPBL0.BIT.IS31)
+    {
+        /* BSP_INT_SRC_BL0_PDC_PCERI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_PDC_PCERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL0 IS30 */
+    if (1 == ICU.GRPBL0.BIT.IS30)
+    {
+        /* BSP_INT_SRC_BL0_PDC_PCFEI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL0_PDC_PCFEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+} /* End of function group_bl0_handler_isr() */
+
+/***********************************************************************************************************************
+* Function Name: group_bl1_handler_isr
+* Description  : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt
+*                in this group the following will be performed:
+*                1) Test to see if an interrupt is requested for this source
+*                2) If an interrupt is requested then the registered callback is called (if one is registered)
+*                NOTE: The interrupt request flag must be cleared in the peripheral.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl1_handler_isr (void)
+{
+    /* BL1 IS3 */
+    if (1 == ICU.GRPBL1.BIT.IS3)
+    {
+        /* BSP_INT_SRC_BL1_SDHI_CDETI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_CDETI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS4 */
+    if (1 == ICU.GRPBL1.BIT.IS4)
+    {
+        /* BSP_INT_SRC_BL1_SDHI_CACI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_CACI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS5 */
+    if (1 == ICU.GRPBL1.BIT.IS5)
+    {
+        /* BSP_INT_SRC_BL1_SDHI_SDACI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_SDACI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS6 */
+    if (1 == ICU.GRPBL1.BIT.IS6)
+    {
+        /* BSP_INT_SRC_BL1_MMCIF_CDETIO */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_CDETIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS7 */
+    if (1 == ICU.GRPBL1.BIT.IS7)
+    {
+        /* BSP_INT_SRC_BL1_MMCIF_ERRIO */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_ERRIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS8 */
+    if (1 == ICU.GRPBL1.BIT.IS8)
+    {
+        /* BSP_INT_SRC_BL1_MMCIF_ACCIO */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_ACCIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS9 */
+    if (1 == ICU.GRPBL1.BIT.IS9)
+    {
+        /* BSP_INT_SRC_BL1_POE3_OEI1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS10 */
+    if (1 == ICU.GRPBL1.BIT.IS10)
+    {
+        /* BSP_INT_SRC_BL1_POE3_OEI2 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS11 */
+    if (1 == ICU.GRPBL1.BIT.IS11)
+    {
+        /* BSP_INT_SRC_BL1_POE3_OEI3 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS12 */
+    if (1 == ICU.GRPBL1.BIT.IS12)
+    {
+        /* BSP_INT_SRC_BL1_POE3_OEI4 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS14 */
+    if (1 == ICU.GRPBL1.BIT.IS14)
+    {
+        /* BSP_INT_SRC_BL1_RIIC0_EEI0 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_EEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS13 */
+    if (1 == ICU.GRPBL1.BIT.IS13)
+    {
+        /* BSP_INT_SRC_BL1_RIIC0_TEI0 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS16 */
+    if (1 == ICU.GRPBL1.BIT.IS16)
+    {
+        /* BSP_INT_SRC_BL1_RIIC2_EEI2 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC2_EEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS15 */
+    if (1 == ICU.GRPBL1.BIT.IS15)
+    {
+        /* BSP_INT_SRC_BL1_RIIC2_TEI2 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC2_TEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS20 */
+    if (1 == ICU.GRPBL1.BIT.IS20)
+    {
+        /* BSP_INT_SRC_BL1_S12AD0_S12CMPAI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS21 */
+    if (1 == ICU.GRPBL1.BIT.IS21)
+    {
+        /* BSP_INT_SRC_BL1_S12AD0_S12CMPBI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS22 */
+    if (1 == ICU.GRPBL1.BIT.IS22)
+    {
+        /* BSP_INT_SRC_BL1_S12AD1_S12CMPAI1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS23 */
+    if (1 == ICU.GRPBL1.BIT.IS23)
+    {
+        /* BSP_INT_SRC_BL1_S12AD1_S12CMPBI1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS25 */
+    if (1 == ICU.GRPBL1.BIT.IS25)
+    {
+        /* BSP_INT_SRC_BL1_SCI8_ERI8 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_SCI8_ERI8, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS24 */
+    if (1 == ICU.GRPBL1.BIT.IS24)
+    {
+        /* BSP_INT_SRC_BL1_SCI8_TEI8 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_SCI8_TEI8, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS27 */
+    if (1 == ICU.GRPBL1.BIT.IS27)
+    {
+        /* BSP_INT_SRC_BL1_SCI9_ERI9 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_SCI9_ERI9, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS26 */
+    if (1 == ICU.GRPBL1.BIT.IS26)
+    {
+        /* BSP_INT_SRC_BL1_SCI9_TEI9 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_SCI9_TEI9, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS29 */
+    if (1 == ICU.GRPBL1.BIT.IS29)
+    {
+        /* BSP_INT_SRC_BL1_RIIC1_EEI1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC1_EEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BL1 IS28 */
+    if (1 == ICU.GRPBL1.BIT.IS28)
+    {
+        /* BSP_INT_SRC_BL1_RIIC1_TEI1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+} /* End of function group_bl1_handler_isr() */
+
+/***********************************************************************************************************************
+* Function Name: group_bl2_handler_isr
+* Description  : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt
+*                in this group the following will be performed:
+*                1) Test to see if an interrupt is requested for this source
+*                2) If an interrupt is requested then the registered callback is called (if one is registered)
+*                NOTE: The interrupt request flag must be cleared in the peripheral.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl2_handler_isr (void)
+{
+    /* BL2 IS0 */
+    if (1 == ICU.GRPBL2.BIT.IS0)
+    {
+        /* BSP_INT_SRC_BL2_SDSI_SDIOI */
+        R_BSP_InterruptControl(BSP_INT_SRC_BL2_SDSI_SDIOI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+} /* End of function group_bl2_handler_isr() */
+
+/***********************************************************************************************************************
+* Function Name: group_al0_handler_isr
+* Description  : Interrupt handler for Group AL0 interrupts. The way this code works is that for each possible interrupt
+*                in this group the following will be performed:
+*                1) Test to see if an interrupt is requested for this source
+*                2) If an interrupt is requested then the registered callback is called (if one is registered)
+*                NOTE: The interrupt request flag must be cleared in the peripheral.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+R_BSP_ATTRIB_STATIC_INTERRUPT void group_al0_handler_isr (void)
+{
+    /* AL0 IS9 */
+    if (1 == ICU.GRPAL0.BIT.IS9)
+    {
+        /* BSP_INT_SRC_AL0_SCI10_ERI10 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI10_ERI10, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL0 IS8 */
+    if (1 == ICU.GRPAL0.BIT.IS8)
+    {
+        /* BSP_INT_SRC_AL0_SCI10_TEI10 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI10_TEI10, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL0 IS13 */
+    if (1 == ICU.GRPAL0.BIT.IS13)
+    {
+        /* BSP_INT_SRC_AL0_SCI11_ERI11 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI11_ERI11, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL0 IS12 */
+    if (1 == ICU.GRPAL0.BIT.IS12)
+    {
+        /* BSP_INT_SRC_AL0_SCI11_TEI11 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI11_TEI11, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL0 IS17 */
+    if (1 == ICU.GRPAL0.BIT.IS17)
+    {
+        /* BSP_INT_SRC_AL0_RSPI0_SPEI0 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL0 IS16 */
+    if (1 == ICU.GRPAL0.BIT.IS16)
+    {
+        /* BSP_INT_SRC_AL0_RSPI0_SPII0 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPII0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL0 IS19 */
+    if (1 == ICU.GRPAL0.BIT.IS19)
+    {
+        /* BSP_INT_SRC_AL0_RSPI1_SPEI1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI1_SPEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL0 IS18 */
+    if (1 == ICU.GRPAL0.BIT.IS18)
+    {
+        /* BSP_INT_SRC_AL0_RSPI1_SPII1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI1_SPII1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL0 IS21 */
+    if (1 == ICU.GRPAL0.BIT.IS21)
+    {
+        /* BSP_INT_SRC_AL0_RSPI2_SPEI2 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI2_SPEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL0 IS20 */
+    if (1 == ICU.GRPAL0.BIT.IS20)
+    {
+        /* BSP_INT_SRC_AL0_RSPI2_SPII2 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI2_SPII2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+} /* End of function group_al0_handler_isr() */
+
+/***********************************************************************************************************************
+* Function Name: group_al1_handler_isr
+* Description  : Interrupt handler for Group AL1 interrupts. The way this code works is that for each possible interrupt
+*                in this group the following will be performed:
+*                1) Test to see if an interrupt is requested for this source
+*                2) If an interrupt is requested then the registered callback is called (if one is registered)
+*                NOTE: The interrupt request flag must be cleared in the peripheral.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+R_BSP_ATTRIB_STATIC_INTERRUPT void group_al1_handler_isr (void)
+{
+    /* AL1 IS4 */
+    if (1 == ICU.GRPAL1.BIT.IS4)
+    {
+        /* BSP_INT_SRC_AL1_EDMAC0_EINT0 */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL1_EDMAC0_EINT0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL1 IS9 */
+    if (1 == ICU.GRPAL1.BIT.IS9)
+    {
+        /* BSP_INT_SRC_AL1_GLCDC_GR1UF */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_GR1UF, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL1 IS10 */
+    if (1 == ICU.GRPAL1.BIT.IS10)
+    {
+        /* BSP_INT_SRC_AL1_GLCDC_GR2UF */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_GR2UF, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL1 IS8 */
+    if (1 == ICU.GRPAL1.BIT.IS8)
+    {
+        /* BSP_INT_SRC_AL1_GLCDC_VPOS */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_VPOS, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* AL1 IS11 */
+    if (1 == ICU.GRPAL1.BIT.IS11)
+    {
+        /* BSP_INT_SRC_AL1_DRW2D_DRW_IRQ */
+        R_BSP_InterruptControl(BSP_INT_SRC_AL1_DRW2D_DRW_IRQ, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+} /* End of function group_al1_handler_isr() */
+
+/***********************************************************************************************************************
+* Function Name: group_be0_handler_isr
+* Description  : Interrupt handler for Group BE0 interrupts. The way this code works is that for each possible interrupt
+*                in this group the following will be performed:
+*                1) Test to see if an interrupt is requested for this source
+*                2) If an interrupt is requested then the registered callback is called (if one is registered)
+*                NOTE: The interrupt request flag must be cleared in the peripheral.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+R_BSP_ATTRIB_STATIC_INTERRUPT void group_be0_handler_isr (void)
+{
+    /* BE0 IS0 */
+    if (1 == ICU.GRPBE0.BIT.IS0)
+    {
+        /* Clear the interrupt status flag. */
+        ICU.GCRBE0.BIT.CLR0 = 1;
+
+        /* BSP_INT_SRC_BE0_CAN0_ERS0 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN0_ERS0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+
+    /* BE0 IS1 */
+    if (1 == ICU.GRPBE0.BIT.IS1)
+    {
+        /* Clear the interrupt status flag. */
+        ICU.GCRBE0.BIT.CLR1 = 1;
+
+        /* BSP_INT_SRC_BE0_CAN1_ERS1 */
+        R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN1_ERS1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR);
+    }
+} /* End of function group_be0_handler_isr() */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_interrupts.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_interrupts.h
new file mode 100644
index 00000000..d74a64ed
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_interrupts.h
@@ -0,0 +1,254 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_interrupts.h
+* Description  : This module is the control of the interrupt enable.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 01.10.2016 1.00      First Release
+*         : 15.05.2017 2.00      Added the following enumeration constant.
+*                                - BSP_INT_SRC_EXRAM
+*                                - BSP_INT_SRC_BL1_RIIC1_TEI1
+*                                - BSP_INT_SRC_BL1_RIIC1_EEI1
+*                                - BSP_INT_SRC_AL1_GLCDC_VPOS
+*                                - BSP_INT_SRC_AL1_GLCDC_GR1UF
+*                                - BSP_INT_SRC_AL1_GLCDC_GR2UF
+*                                - BSP_INT_SRC_AL1_DRW2D_DRW_IRQ
+*         : 28.02.2019 2.00      Added the following prototype declaration.
+*                                - bsp_interrupt_enable_disable
+*                                Deleted the following prototype declarations. 
+*                                (The following prototype declarations moved to the common file (r_bsp_interrupts.h).)
+*                                - bsp_interrupt_open
+*                                - R_BSP_InterruptWrite
+*                                - R_BSP_InterruptRead
+*                                - R_BSP_InterruptControl
+*                                Added the following enumeration constant.
+*                                - BSP_INT_SRC_GR_INT_TOP
+*                                - BSP_INT_SRC_GR_INT_BE0_TOP
+*                                - BSP_INT_SRC_GR_INT_BL0_TOP
+*                                - BSP_INT_SRC_GR_INT_BL1_TOP
+*                                - BSP_INT_SRC_GR_INT_BL2_TOP
+*                                - BSP_INT_SRC_GR_INT_AL0_TOP
+*                                - BSP_INT_SRC_GR_INT_AL1_TOP
+*                                - BSP_INT_SRC_GR_INT_END
+*                                - BSP_INT_SRC_BE0_CAN0_ERS0
+*                                - BSP_INT_SRC_BE0_CAN1_ERS1
+*                                Fixed coding style.
+*         : 08.04.2019 2.01      Added the following enumeration constant.
+*                                - BSP_INT_SRC_GR_INT_IE0_TOP
+*         : 26.07.2019 2.10      Added the following command.
+*                                - BSP_INT_CMD_FIT_INTERRUPT_ENABLE
+*                                - BSP_INT_CMD_FIT_INTERRUPT_DISABLE
+*                                Added the following error code.
+*                                - BSP_INT_ERR_INVALID_IPL
+*                                Added the following enumeration constant.
+*                                - BSP_INT_SRC_EMPTY
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef MCU_INTERRUPTS_H
+#define MCU_INTERRUPTS_H
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+/* Available return codes. */
+typedef enum
+{
+    BSP_INT_SUCCESS = 0,
+    BSP_INT_ERR_NO_REGISTERED_CALLBACK,     /* There is not a registered callback for this interrupt source */
+    BSP_INT_ERR_INVALID_ARG,                /* Illegal argument input */
+    BSP_INT_ERR_UNSUPPORTED,                /* Operation is not supported by this API */
+    BSP_INT_ERR_GROUP_STILL_ENABLED,        /* Not all group interrupts were disabled so group interrupt was not 
+                                               disabled */
+    BSP_INT_ERR_INVALID_IPL                 /* Illegal IPL value input */
+} bsp_int_err_t;
+
+/* Available interrupts to register a callback for. */
+typedef enum
+{
+    BSP_INT_SRC_EXC_SUPERVISOR_INSTR = 0, /* Occurs when privileged instruction is executed in User Mode */
+    BSP_INT_SRC_EXC_UNDEFINED_INSTR,      /* Occurs when MCU encounters an unknown instruction */
+    BSP_INT_SRC_EXC_NMI_PIN,              /* NMI Pin interrupt */
+    BSP_INT_SRC_EXC_FPU,                  /* FPU exception */
+    BSP_INT_SRC_EXC_ACCESS,               /* Access exception */
+    BSP_INT_SRC_OSC_STOP_DETECT,          /* Oscillation stop is detected */
+    BSP_INT_SRC_WDT_ERROR,                /* WDT underflow/refresh error has occurred */
+    BSP_INT_SRC_IWDT_ERROR,               /* IWDT underflow/refresh error has occurred */
+    BSP_INT_SRC_LVD1,                     /* Voltage monitoring 1 interrupt */
+    BSP_INT_SRC_LVD2,                     /* Voltage monitoring 2 interrupt */
+    BSP_INT_SRC_UNDEFINED_INTERRUPT,      /* Interrupt has triggered for a vector that user did not write a handler. */
+    BSP_INT_SRC_BUS_ERROR,                /* Bus error: illegal address access or timeout */
+    BSP_INT_SRC_RAM,                      /* RAM error interrupt */
+    BSP_INT_SRC_EXRAM,                    /* EXRAM error interrupt */
+
+    BSP_INT_SRC_GR_INT_TOP,
+
+    /* IE0 Group Interrupts */
+    BSP_INT_SRC_GR_INT_IE0_TOP,
+
+    /* BE0 Group Interrupts */
+    BSP_INT_SRC_GR_INT_BE0_TOP,
+    BSP_INT_SRC_BE0_CAN0_ERS0,
+    BSP_INT_SRC_BE0_CAN1_ERS1,
+
+    /* BL0 Group Interrupts. */
+    BSP_INT_SRC_GR_INT_BL0_TOP,
+    BSP_INT_SRC_BL0_SCI0_TEI0,
+    BSP_INT_SRC_BL0_SCI0_ERI0,
+    BSP_INT_SRC_BL0_SCI1_TEI1,
+    BSP_INT_SRC_BL0_SCI1_ERI1,
+    BSP_INT_SRC_BL0_SCI2_TEI2,
+    BSP_INT_SRC_BL0_SCI2_ERI2,
+    BSP_INT_SRC_BL0_SCI3_TEI3,
+    BSP_INT_SRC_BL0_SCI3_ERI3,
+    BSP_INT_SRC_BL0_SCI4_TEI4,
+    BSP_INT_SRC_BL0_SCI4_ERI4,
+    BSP_INT_SRC_BL0_SCI5_TEI5,
+    BSP_INT_SRC_BL0_SCI5_ERI5,
+    BSP_INT_SRC_BL0_SCI6_TEI6,
+    BSP_INT_SRC_BL0_SCI6_ERI6,
+    BSP_INT_SRC_BL0_SCI7_TEI7,
+    BSP_INT_SRC_BL0_SCI7_ERI7,
+    BSP_INT_SRC_BL0_SCI12_TEI12,
+    BSP_INT_SRC_BL0_SCI12_ERI12,
+    BSP_INT_SRC_BL0_SCI12_SCIX0,
+    BSP_INT_SRC_BL0_SCI12_SCIX1,
+    BSP_INT_SRC_BL0_SCI12_SCIX2,
+    BSP_INT_SRC_BL0_SCI12_SCIX3,
+    BSP_INT_SRC_BL0_QSPI_QSPSSLI,
+    BSP_INT_SRC_BL0_CAC_FERRI,
+    BSP_INT_SRC_BL0_CAC_MENDI,
+    BSP_INT_SRC_BL0_CAC_OVFI,
+    BSP_INT_SRC_BL0_DOC_DOPCI,
+    BSP_INT_SRC_BL0_PDC_PCFEI,
+    BSP_INT_SRC_BL0_PDC_PCERI,
+
+    /* BL1 Group Interrupts. */
+    BSP_INT_SRC_GR_INT_BL1_TOP,
+    BSP_INT_SRC_BL1_SDHI_CDETI,
+    BSP_INT_SRC_BL1_SDHI_CACI,
+    BSP_INT_SRC_BL1_SDHI_SDACI,
+    BSP_INT_SRC_BL1_MMCIF_CDETIO,
+    BSP_INT_SRC_BL1_MMCIF_ERRIO,
+    BSP_INT_SRC_BL1_MMCIF_ACCIO,
+    BSP_INT_SRC_BL1_POE3_OEI1,
+    BSP_INT_SRC_BL1_POE3_OEI2,
+    BSP_INT_SRC_BL1_POE3_OEI3,
+    BSP_INT_SRC_BL1_POE3_OEI4,
+    BSP_INT_SRC_BL1_RIIC0_TEI0,
+    BSP_INT_SRC_BL1_RIIC0_EEI0,
+    BSP_INT_SRC_BL1_RIIC2_TEI2,
+    BSP_INT_SRC_BL1_RIIC2_EEI2,
+    BSP_INT_SRC_BL1_S12AD0_S12CMPAI,
+    BSP_INT_SRC_BL1_S12AD0_S12CMPBI,
+    BSP_INT_SRC_BL1_S12AD1_S12CMPAI1,
+    BSP_INT_SRC_BL1_S12AD1_S12CMPBI1,
+    BSP_INT_SRC_BL1_SCI8_TEI8,
+    BSP_INT_SRC_BL1_SCI8_ERI8,
+    BSP_INT_SRC_BL1_SCI9_TEI9,
+    BSP_INT_SRC_BL1_SCI9_ERI9,
+    BSP_INT_SRC_BL1_RIIC1_TEI1,
+    BSP_INT_SRC_BL1_RIIC1_EEI1,
+
+    /* BL2 Group Interrupts. */
+    BSP_INT_SRC_GR_INT_BL2_TOP,
+    BSP_INT_SRC_BL2_SDSI_SDIOI,
+
+    /* AL0 Group Interrupts. */
+    BSP_INT_SRC_GR_INT_AL0_TOP,
+    BSP_INT_SRC_AL0_SCI10_TEI10,
+    BSP_INT_SRC_AL0_SCI10_ERI10,
+    BSP_INT_SRC_AL0_SCI11_TEI11,
+    BSP_INT_SRC_AL0_SCI11_ERI11,
+    BSP_INT_SRC_AL0_RSPI0_SPII0,
+    BSP_INT_SRC_AL0_RSPI0_SPEI0,
+    BSP_INT_SRC_AL0_RSPI1_SPII1,
+    BSP_INT_SRC_AL0_RSPI1_SPEI1,
+    BSP_INT_SRC_AL0_RSPI2_SPII2,
+    BSP_INT_SRC_AL0_RSPI2_SPEI2,
+
+    /* AL1 Group Interrupts. */
+    BSP_INT_SRC_GR_INT_AL1_TOP,
+    BSP_INT_SRC_AL1_EDMAC0_EINT0,
+    BSP_INT_SRC_AL1_GLCDC_VPOS,
+    BSP_INT_SRC_AL1_GLCDC_GR1UF,
+    BSP_INT_SRC_AL1_GLCDC_GR2UF,
+    BSP_INT_SRC_AL1_DRW2D_DRW_IRQ,
+
+    BSP_INT_SRC_GR_INT_END,
+    BSP_INT_SRC_EMPTY,
+    BSP_INT_SRC_TOTAL_ITEMS               /* DO NOT MODIFY! This is used for sizing the interrupt callback array. */
+} bsp_int_src_t;
+
+/* Available commands for R_BSP_InterruptControl() function. */
+typedef enum
+{
+    BSP_INT_CMD_CALL_CALLBACK = 0,        /* Calls registered callback function if one exists */
+    BSP_INT_CMD_INTERRUPT_ENABLE,         /* Enables a given interrupt (Available for NMI pin, FPU, and Bus Error) */
+    BSP_INT_CMD_INTERRUPT_DISABLE,        /* Disables a given interrupt (Available for FPU, and Bus Error) */
+    BSP_INT_CMD_GROUP_INTERRUPT_ENABLE,   /* Enables a group interrupt when a group interrupt source is given. The
+                                             pdata argument should give the IPL to be used using the bsp_int_ctrl_t
+                                             type. If a group interrupt is enabled multiple times with different IPL
+                                             levels it will use the highest given IPL. */
+    BSP_INT_CMD_GROUP_INTERRUPT_DISABLE,  /* Disables a group interrupt when a group interrupt source is given.
+                                             This will only disable a group interrupt when all interrupt
+                                             sources for that group are already disabled. */
+    BSP_INT_CMD_FIT_INTERRUPT_ENABLE,     /* Enables interrupt by control of IPL. */
+    BSP_INT_CMD_FIT_INTERRUPT_DISABLE     /* Disables interrupt by control of IPL. */
+} bsp_int_cmd_t;
+
+/* Type to be used for pdata argument in Control function. */
+typedef union
+{
+    uint32_t ipl;                         /* Used at the following times.
+                                             - When enabling an interrupt to set that interrupt's priority level 
+                                               by BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command.
+                                             - When disabling an interrupt to save that interrupt's priority level 
+                                               by BSP_INT_CMD_FIT_INTERRUPT_DISABLE command.
+                                             - When enabling an interrupt to set that interrupt's priority level 
+                                               by BSP_INT_CMD_FIT_INTERRUPT_ENABLE command. */
+} bsp_int_ctrl_t;
+
+/* Easy to use typedef for callback functions. */
+typedef void (*bsp_int_cb_t)(void *);
+
+/* This structure is the common one that is passed as the 'void *' argument to callback functions when an
+ * exception occurs.
+ */
+typedef struct
+{
+    bsp_int_src_t vector;         /* Which vector caused this interrupt */
+} bsp_int_cb_args_t;
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+bsp_int_err_t bsp_interrupt_enable_disable(bsp_int_src_t vector, bool enable);
+
+#endif /* MCU_INTERRUPTS_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_locks.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_locks.h
new file mode 100644
index 00000000..d787898e
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_locks.h
@@ -0,0 +1,208 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_locks.h
+* Device(s)    : RX65N
+* Description  : This source file has 1 lock per MCU resource.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 01.10.2016 1.00     First Release
+*         : 15.05.2017 2.00     Added the following enumeration constant.
+*                               - BSP_LOCK_RIIC1
+*                               - BSP_LOCK_GLCDC
+*                               - BSP_LOCK_DRW2D
+*         : 27.07.2018 2.01     Added the following enumeration constant.
+*                               - BSP_LOCK_SMCI10
+*                               - BSP_LOCK_SMCI11
+*         : 28.02.2019 2.02     Deleted the following enumeration constant.
+*                               - BSP_LOCK_SMCIx (x = 0 to 12.)
+*                               Fixed coding style.
+*         : 08.10.2019 2.03     Added the following enumeration constant.
+*                               - BSP_LOCK_SWINT
+*                               - BSP_LOCK_SWINT2
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Gets MCU configuration information. */
+#include "r_bsp_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef MCU_LOCKS_H
+#define MCU_LOCKS_H
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+/* This enum defines all of the available hardware locks for this MCU. If you delete an entry out of this list then you
+   will decrease the size of the locks array but will not be able to use that lock. For example, if your design is not
+   using CAN at all then you can safely remove the BSP_LOCK_CAN# entries below. */
+typedef enum
+{
+    BSP_LOCK_BSC = 0,
+    BSP_LOCK_CAC,
+    BSP_LOCK_CAN0,
+    BSP_LOCK_CAN1,
+    BSP_LOCK_CMT,
+    BSP_LOCK_CMT0,
+    BSP_LOCK_CMT1,
+    BSP_LOCK_CMT2,
+    BSP_LOCK_CMT3,
+    BSP_LOCK_CMTW0,
+    BSP_LOCK_CMTW1,
+    BSP_LOCK_CRC,
+    BSP_LOCK_DA,
+    BSP_LOCK_DMAC,
+    BSP_LOCK_DMAC0,
+    BSP_LOCK_DMAC1,
+    BSP_LOCK_DMAC2,
+    BSP_LOCK_DMAC3,
+    BSP_LOCK_DMAC4,
+    BSP_LOCK_DMAC5,
+    BSP_LOCK_DMAC6,
+    BSP_LOCK_DMAC7,
+    BSP_LOCK_DOC,
+    BSP_LOCK_DTC,
+    BSP_LOCK_EDMAC0,
+    BSP_LOCK_ELC,
+    BSP_LOCK_ETHERC0,
+    BSP_LOCK_EXDMAC,
+    BSP_LOCK_EXDMAC0,
+    BSP_LOCK_EXDMAC1,
+    BSP_LOCK_FLASH,
+    BSP_LOCK_IRQ0,
+    BSP_LOCK_IRQ1,
+    BSP_LOCK_IRQ2,
+    BSP_LOCK_IRQ3,
+    BSP_LOCK_IRQ4,
+    BSP_LOCK_IRQ5,
+    BSP_LOCK_IRQ6,
+    BSP_LOCK_IRQ7,
+    BSP_LOCK_IRQ8,
+    BSP_LOCK_IRQ9,
+    BSP_LOCK_IRQ10,
+    BSP_LOCK_IRQ11,
+    BSP_LOCK_IRQ12,
+    BSP_LOCK_IRQ13,
+    BSP_LOCK_IRQ14,
+    BSP_LOCK_IRQ15,
+    BSP_LOCK_ICU,
+    BSP_LOCK_IWDT,
+    BSP_LOCK_MMC,
+    BSP_LOCK_MPC,
+    BSP_LOCK_MPU,
+    BSP_LOCK_MTU,
+    BSP_LOCK_MTU0,
+    BSP_LOCK_MTU1,
+    BSP_LOCK_MTU2,
+    BSP_LOCK_MTU3,
+    BSP_LOCK_MTU4,
+    BSP_LOCK_MTU5,
+    BSP_LOCK_MTU6,
+    BSP_LOCK_MTU7,
+    BSP_LOCK_MTU8,
+    BSP_LOCK_PDC,
+    BSP_LOCK_POE,
+    BSP_LOCK_PPG0,
+    BSP_LOCK_PPG1,
+    BSP_LOCK_QSPI,
+    BSP_LOCK_RAM,
+    BSP_LOCK_RIIC0,
+    BSP_LOCK_RIIC1,
+    BSP_LOCK_RIIC2,
+    BSP_LOCK_RSPI0,
+    BSP_LOCK_RSPI1,
+    BSP_LOCK_RSPI2,
+    BSP_LOCK_RTC,
+    BSP_LOCK_S12AD,
+    BSP_LOCK_S12AD1,
+    BSP_LOCK_SCI0,
+    BSP_LOCK_SCI1,
+    BSP_LOCK_SCI2,
+    BSP_LOCK_SCI3,
+    BSP_LOCK_SCI4,
+    BSP_LOCK_SCI5,
+    BSP_LOCK_SCI6,
+    BSP_LOCK_SCI7,
+    BSP_LOCK_SCI8,
+    BSP_LOCK_SCI9,
+    BSP_LOCK_SCI10,
+    BSP_LOCK_SCI11,
+    BSP_LOCK_SCI12,
+    BSP_LOCK_SDHI,
+    BSP_LOCK_SDSI,
+    BSP_LOCK_SYSTEM,
+    BSP_LOCK_TEMPS,
+    BSP_LOCK_TMR0,
+    BSP_LOCK_TMR1,
+    BSP_LOCK_TMR2,
+    BSP_LOCK_TMR3,
+    BSP_LOCK_TMR01,
+    BSP_LOCK_TMR23,
+    BSP_LOCK_TPU0,
+    BSP_LOCK_TPU1,
+    BSP_LOCK_TPU2,
+    BSP_LOCK_TPU3,
+    BSP_LOCK_TPU4,
+    BSP_LOCK_TPU5,
+    BSP_LOCK_TPUA,
+    BSP_LOCK_USB,
+    BSP_LOCK_USB0,
+    BSP_LOCK_WDT,
+    BSP_LOCK_FLASHCONST,
+    BSP_LOCK_TEMPSCONST,
+    BSP_LOCK_GLCDC,
+    BSP_LOCK_DRW2D,
+    BSP_LOCK_SWINT,
+    BSP_LOCK_SWINT2,
+    BSP_NUM_LOCKS //This entry is not a valid lock. It is used for sizing g_bsp_Locks[] array below. Do not touch!
+} mcu_lock_t;
+
+typedef struct
+{
+    /* The actual lock. int32_t is used because this is what the xchg() instruction takes as parameters. */
+    int32_t     lock;
+
+    /* Could add a ID for locking and unlocking. In this could protect against any function being able to unlock. */
+} bsp_lock_t;
+
+/***********************************************************************************************************************
+Error checking
+***********************************************************************************************************************/
+#if BSP_CFG_USER_LOCKING_ENABLED == 0
+#undef  BSP_CFG_USER_LOCKING_TYPE
+#define BSP_CFG_USER_LOCKING_TYPE       bsp_lock_t
+#else
+    #if !defined(BSP_CFG_USER_LOCKING_TYPE)
+    #error "R_BSP ERROR - If you are using your own locking mechanism then you must define BSP_CFG_USER_LOCKING_TYPE in r_bsp_config.h."
+    #endif
+#endif
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+extern BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[];
+
+#endif /* MCU_LOCKS_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_mapped_interrupts.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_mapped_interrupts.c
new file mode 100644
index 00000000..4b417818
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_mapped_interrupts.c
@@ -0,0 +1,715 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_mapped_interrupts.c
+* Description  : This module maps Interrupt A & B interrupts. Which interrupts are mapped depends on the macros in
+*                r_bsp_interrupt_config.h.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 01.10.2016 1.00      First Release
+*         : 15.05.2017 2.00      Changed the name of the following macro definition, because there was a mistake
+*                                in the name of macro definition.
+*                                 (XXX = BSP_MAPPED_INT_CFG_B_VECT, BSP_MAPPED_INT_CFG_A_VECT,
+*                                        BSP_PRV_INT_B_NUM, BSP_PRV_INT_A_NUM)
+*                                - From XXX_TPU0_TGI0V to XXX_TPU0_TCI0V.
+*                                - From XXX_TPU1_TGI1V to XXX_TPU1_TCI1V.
+*                                - From XXX_TPU1_TGI1U to XXX_TPU1_TCI1U.
+*                                - From XXX_TPU2_TGI2V to XXX_TPU2_TCI2V.
+*                                - From XXX_TPU2_TGI2U to XXX_TPU2_TCI2U.
+*                                - From XXX_TPU3_TGI3V to XXX_TPU3_TCI3V.
+*                                - From XXX_TPU4_TGI4V to XXX_TPU4_TCI4V.
+*                                - From XXX_TPU4_TGI4U to XXX_TPU4_TCI4U.
+*                                - From XXX_TPU5_TGI5V to XXX_TPU5_TCI5V.
+*                                - From XXX_TPU5_TGI5U to XXX_TPU5_TCI5U.
+*                                - From XXX_MTU0_TGIV0 to XXX_MTU0_TCIV0.
+*                                - From XXX_MTU1_TGIV1 to XXX_MTU1_TCIV1.
+*                                - From XXX_MTU1_TGIU1 to XXX_MTU1_TCIU1.
+*                                - From XXX_MTU2_TGIV2 to XXX_MTU2_TCIV2.
+*                                - From XXX_MTU2_TGIU2 to XXX_MTU2_TCIU2.
+*                                - From XXX_MTU3_TGIV3 to XXX_MTU3_TCIV3.
+*                                - From XXX_MTU4_TGIV4 to XXX_MTU4_TCIV4.
+*                                - From XXX_MTU6_TGIV6 to XXX_MTU6_TCIV6.
+*                                - From XXX_MTU7_TGIV7 to XXX_MTU7_TCIV7.
+*                                - From XXX_MTU8_TGIV8 to XXX_MTU8_TCIV8.
+*                                Added select processing of the following software configurable interrupt source.
+*                                - TSIP_PROC_BUSY
+*                                - TSIP_ROMOK
+*                                - TSIP_LONG_PLG
+*                                - TSIP_TEST_BUSY
+*                                - TSIP_WRRDY0
+*                                - TSIP_WRRDY1
+*                                - TSIP_WRRDY4
+*                                - TSIP_RDRDY0
+*                                - TSIP_RDRDY1
+*                                - TSIP_INTEGRATE_WRRDY
+*                                - TSIP_INTEGRATE_RDRDY
+*         : 28.02.2019 2.01      Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Access to r_bsp. */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+ 
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: bsp_mapped_interrupt_open
+* Description  : Initializes mapped interrupts. This code does the following for each possible mapped interrupt:
+*                1) PREPROCCESOR - Test to see if this interrupt is chosen to be used
+*                2) PREPROCESSOR - Figure out which interrupt select register needs to be written to
+*                3) RUNTIME C    - Set the appropriate select register with the number of this mapped interrupt
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void bsp_mapped_interrupt_open (void)
+{
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) = BSP_PRV_INT_B_NUM_CMT2_CMI2;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) = BSP_PRV_INT_B_NUM_CMT3_CMI3;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) = BSP_PRV_INT_B_NUM_TMR0_CMIA0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) = BSP_PRV_INT_B_NUM_TMR0_CMIB0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) = BSP_PRV_INT_B_NUM_TMR0_OVI0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) = BSP_PRV_INT_B_NUM_TMR1_CMIA1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) = BSP_PRV_INT_B_NUM_TMR1_CMIB1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) = BSP_PRV_INT_B_NUM_TMR1_OVI1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) = BSP_PRV_INT_B_NUM_TMR2_CMIA2;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) = BSP_PRV_INT_B_NUM_TMR2_CMIB2;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) = BSP_PRV_INT_B_NUM_TMR2_OVI2;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) = BSP_PRV_INT_B_NUM_TMR3_CMIA3;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) = BSP_PRV_INT_B_NUM_TMR3_CMIB3;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) = BSP_PRV_INT_B_NUM_TMR3_OVI3;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) = BSP_PRV_INT_B_NUM_TPU0_TGI0A;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) = BSP_PRV_INT_B_NUM_TPU0_TGI0B;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) = BSP_PRV_INT_B_NUM_TPU0_TGI0C;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) = BSP_PRV_INT_B_NUM_TPU0_TGI0D;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) = BSP_PRV_INT_B_NUM_TPU0_TCI0V;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) = BSP_PRV_INT_B_NUM_TPU1_TGI1A;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) = BSP_PRV_INT_B_NUM_TPU1_TGI1B;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) = BSP_PRV_INT_B_NUM_TPU1_TCI1V;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) = BSP_PRV_INT_B_NUM_TPU1_TCI1U;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) = BSP_PRV_INT_B_NUM_TPU2_TGI2A;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) = BSP_PRV_INT_B_NUM_TPU2_TGI2B;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) = BSP_PRV_INT_B_NUM_TPU2_TCI2V;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) = BSP_PRV_INT_B_NUM_TPU2_TCI2U;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) = BSP_PRV_INT_B_NUM_TPU3_TGI3A;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) = BSP_PRV_INT_B_NUM_TPU3_TGI3B;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) = BSP_PRV_INT_B_NUM_TPU3_TGI3C;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) = BSP_PRV_INT_B_NUM_TPU3_TGI3D;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) = BSP_PRV_INT_B_NUM_TPU3_TCI3V;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) = BSP_PRV_INT_B_NUM_TPU4_TGI4A;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) = BSP_PRV_INT_B_NUM_TPU4_TGI4B;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) = BSP_PRV_INT_B_NUM_TPU4_TCI4V;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) = BSP_PRV_INT_B_NUM_TPU4_TCI4U;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) = BSP_PRV_INT_B_NUM_TPU5_TGI5A;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) = BSP_PRV_INT_B_NUM_TPU5_TGI5B;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) = BSP_PRV_INT_B_NUM_TPU5_TCI5V;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) = BSP_PRV_INT_B_NUM_TPU5_TCI5U;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) = BSP_PRV_INT_B_NUM_CMTW0_IC0I0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) = BSP_PRV_INT_B_NUM_CMTW0_IC1I0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) = BSP_PRV_INT_B_NUM_CMTW0_OC0I0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) = BSP_PRV_INT_B_NUM_CMTW0_OC1I0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) = BSP_PRV_INT_B_NUM_CMTW1_IC0I1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) = BSP_PRV_INT_B_NUM_CMTW1_IC1I1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) = BSP_PRV_INT_B_NUM_CMTW1_OC0I1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) = BSP_PRV_INT_B_NUM_CMTW1_OC1I1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) = BSP_PRV_INT_B_NUM_RTC_CUP;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) = BSP_PRV_INT_B_NUM_CAN0_RXF0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) = BSP_PRV_INT_B_NUM_CAN0_TXF0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) = BSP_PRV_INT_B_NUM_CAN0_RXM0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) = BSP_PRV_INT_B_NUM_CAN0_TXM0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) = BSP_PRV_INT_B_NUM_CAN1_RXF1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) = BSP_PRV_INT_B_NUM_CAN1_TXF1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) = BSP_PRV_INT_B_NUM_CAN1_RXM1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) = BSP_PRV_INT_B_NUM_CAN1_TXM1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) = BSP_PRV_INT_B_NUM_USB0_USBI0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12ADI0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12GBADI0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12GCADI0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12ADI1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12GBADI1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12GCADI1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND) = BSP_PRV_INT_B_NUM_RNG_RNGEND;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) = BSP_PRV_INT_B_NUM_ELC_ELSR18I;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) = BSP_PRV_INT_B_NUM_ELC_ELSR19I;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) = BSP_PRV_INT_B_NUM_TSIP_PROC_BUSY;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) = BSP_PRV_INT_B_NUM_TSIP_ROMOK;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) = BSP_PRV_INT_B_NUM_TSIP_LONG_PLG;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) = BSP_PRV_INT_B_NUM_TSIP_TEST_BUSY;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) = BSP_PRV_INT_B_NUM_TSIP_WRRDY0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) = BSP_PRV_INT_B_NUM_TSIP_WRRDY1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) = BSP_PRV_INT_B_NUM_TSIP_WRRDY4;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) = BSP_PRV_INT_B_NUM_TSIP_RDRDY0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) = BSP_PRV_INT_B_NUM_TSIP_RDRDY1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) = BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_WRRDY;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) = BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_RDRDY;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) = BSP_PRV_INT_A_NUM_MTU0_TGIA0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) = BSP_PRV_INT_A_NUM_MTU0_TGIB0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) = BSP_PRV_INT_A_NUM_MTU0_TGIC0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) = BSP_PRV_INT_A_NUM_MTU0_TGID0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) = BSP_PRV_INT_A_NUM_MTU0_TCIV0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) = BSP_PRV_INT_A_NUM_MTU0_TGIE0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) = BSP_PRV_INT_A_NUM_MTU0_TGIF0;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) = BSP_PRV_INT_A_NUM_MTU1_TGIA1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) = BSP_PRV_INT_A_NUM_MTU1_TGIB1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) = BSP_PRV_INT_A_NUM_MTU1_TCIV1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) = BSP_PRV_INT_A_NUM_MTU1_TCIU1;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) = BSP_PRV_INT_A_NUM_MTU2_TGIA2;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) = BSP_PRV_INT_A_NUM_MTU2_TGIB2;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) = BSP_PRV_INT_A_NUM_MTU2_TCIV2;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) = BSP_PRV_INT_A_NUM_MTU2_TCIU2;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) = BSP_PRV_INT_A_NUM_MTU3_TGIA3;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) = BSP_PRV_INT_A_NUM_MTU3_TGIB3;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) = BSP_PRV_INT_A_NUM_MTU3_TGIC3;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) = BSP_PRV_INT_A_NUM_MTU3_TGID3;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) = BSP_PRV_INT_A_NUM_MTU3_TCIV3;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) = BSP_PRV_INT_A_NUM_MTU4_TGIA4;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) = BSP_PRV_INT_A_NUM_MTU4_TGIB4;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) = BSP_PRV_INT_A_NUM_MTU4_TGIC4;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) = BSP_PRV_INT_A_NUM_MTU4_TGID4;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) = BSP_PRV_INT_A_NUM_MTU4_TCIV4;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) = BSP_PRV_INT_A_NUM_MTU5_TGIU5;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) = BSP_PRV_INT_A_NUM_MTU5_TGIV5;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) = BSP_PRV_INT_A_NUM_MTU5_TGIW5;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) = BSP_PRV_INT_A_NUM_MTU6_TGIA6;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) = BSP_PRV_INT_A_NUM_MTU6_TGIB6;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) = BSP_PRV_INT_A_NUM_MTU6_TGIC6;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) = BSP_PRV_INT_A_NUM_MTU6_TGID6;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) = BSP_PRV_INT_A_NUM_MTU6_TCIV6;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) = BSP_PRV_INT_A_NUM_MTU7_TGIA7;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) = BSP_PRV_INT_A_NUM_MTU7_TGIB7;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) = BSP_PRV_INT_A_NUM_MTU7_TGIC7;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) = BSP_PRV_INT_A_NUM_MTU7_TGID7;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) = BSP_PRV_INT_A_NUM_MTU7_TCIV7;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) = BSP_PRV_INT_A_NUM_MTU8_TGIA8;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) = BSP_PRV_INT_A_NUM_MTU8_TGIB8;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) = BSP_PRV_INT_A_NUM_MTU8_TGIC8;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) = BSP_PRV_INT_A_NUM_MTU8_TGID8;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) = BSP_PRV_INT_A_NUM_MTU8_TCIV8;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY) = BSP_PRV_INT_A_NUM_AES_AESRDY;
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND)
+    /* Casting is valid because it matches the type to the right side or argument. */
+    BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND) = BSP_PRV_INT_A_NUM_AES_AESEND;
+#endif
+
+} /* End of function bsp_mapped_interrupt_open() */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_mapped_interrupts.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_mapped_interrupts.h
new file mode 100644
index 00000000..e1944d1b
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_mapped_interrupts.h
@@ -0,0 +1,1330 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_mapped_interrupts.c
+* Description  : This module maps Interrupt A & B interrupts. Which interrupts are mapped depends on the macros in
+*                r_bsp_interrupt_config.h.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 01.10.2016 1.00      First Release
+*         : 15.05.2017 2.00      Changed the name of the following macro definition, because there was a mistake
+*                                in the name of macro definition.
+*                                 (XXX = BSP_MAPPED_INT_CFG_B_VECT, BSP_MAPPED_INT_CFG_A_VECT, BSP_PRV_INT_B_NUM,
+*                                        BSP_PRV_INT_A_NUM, IR, DTCE, IER, IPR ,IEN, VECT)
+*                                - From XXX_TPU0_TGI0V to XXX_TPU0_TCI0V.
+*                                - From XXX_TPU1_TGI1V to XXX_TPU1_TCI1V.
+*                                - From XXX_TPU1_TGI1U to XXX_TPU1_TCI1U.
+*                                - From XXX_TPU2_TGI2V to XXX_TPU2_TCI2V.
+*                                - From XXX_TPU2_TGI2U to XXX_TPU2_TCI2U.
+*                                - From XXX_TPU3_TGI3V to XXX_TPU3_TCI3V.
+*                                - From XXX_TPU4_TGI4V to XXX_TPU4_TCI4V.
+*                                - From XXX_TPU4_TGI4U to XXX_TPU4_TCI4U.
+*                                - From XXX_TPU5_TGI5V to XXX_TPU5_TCI5V.
+*                                - From XXX_TPU5_TGI5U to XXX_TPU5_TCI5U.
+*                                - From XXX_MTU0_TGIV0 to XXX_MTU0_TCIV0.
+*                                - From XXX_MTU1_TGIV1 to XXX_MTU1_TCIV1.
+*                                - From XXX_MTU1_TGIU1 to XXX_MTU1_TCIU1.
+*                                - From XXX_MTU2_TGIV2 to XXX_MTU2_TCIV2.
+*                                - From XXX_MTU2_TGIU2 to XXX_MTU2_TCIU2.
+*                                - From XXX_MTU3_TGIV3 to XXX_MTU3_TCIV3.
+*                                - From XXX_MTU4_TGIV4 to XXX_MTU4_TCIV4.
+*                                - From XXX_MTU6_TGIV6 to XXX_MTU6_TCIV6.
+*                                - From XXX_MTU7_TGIV7 to XXX_MTU7_TCIV7.
+*                                - From XXX_MTU8_TGIV8 to XXX_MTU8_TCIV8.
+*                                Added the following macro definition.
+*                                 (XXX = BSP_PRV_INT_B_NUM , IR, DTCE, IER, IPR ,IEN, VECT)
+*                                - XXX_TSIP_PROC_BUSY
+*                                - XXX_TSIP_ROMOK
+*                                - XXX_TSIP_LONG_PLG 
+*                                - XXX_TSIP_TEST_BUSY
+*                                - XXX_TSIP_WRRDY0
+*                                - XXX_TSIP_WRRDY1
+*                                - XXX_TSIP_WRRDY4
+*                                - XXX_TSIP_RDRDY0
+*                                - XXX_TSIP_RDRDY1
+*                                - XXX_TSIP_INTEGRATE_WRRDY
+*                                - XXX_TSIP_INTEGRATE_RDRDY
+*         : 28.02.2019 2.01      Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef MCU_MAPPED_INTERRUPTS_H
+#define MCU_MAPPED_INTERRUPTS_H
+
+/* The following macros define the number for each interrupt request source as it pertains to being an Interrupt B or
+ * Interrupt A interrupt. These values are used when setting the interrupt select registers (i.e. SLIBXRn, SLIBrn, and
+ * SLIARn).
+ */
+/* Available Interrupt B Sources. */
+#define BSP_PRV_INT_B_NUM_CMT2_CMI2                                       1
+#define BSP_PRV_INT_B_NUM_CMT3_CMI3                                       2
+#define BSP_PRV_INT_B_NUM_TMR0_CMIA0                                      3
+#define BSP_PRV_INT_B_NUM_TMR0_CMIB0                                      4
+#define BSP_PRV_INT_B_NUM_TMR0_OVI0                                       5
+#define BSP_PRV_INT_B_NUM_TMR1_CMIA1                                      6
+#define BSP_PRV_INT_B_NUM_TMR1_CMIB1                                      7
+#define BSP_PRV_INT_B_NUM_TMR1_OVI1                                       8
+#define BSP_PRV_INT_B_NUM_TMR2_CMIA2                                      9
+#define BSP_PRV_INT_B_NUM_TMR2_CMIB2                                      10
+#define BSP_PRV_INT_B_NUM_TMR2_OVI2                                       11
+#define BSP_PRV_INT_B_NUM_TMR3_CMIA3                                      12
+#define BSP_PRV_INT_B_NUM_TMR3_CMIB3                                      13
+#define BSP_PRV_INT_B_NUM_TMR3_OVI3                                       14
+#define BSP_PRV_INT_B_NUM_TPU0_TGI0A                                      15
+#define BSP_PRV_INT_B_NUM_TPU0_TGI0B                                      16
+#define BSP_PRV_INT_B_NUM_TPU0_TGI0C                                      17
+#define BSP_PRV_INT_B_NUM_TPU0_TGI0D                                      18
+#define BSP_PRV_INT_B_NUM_TPU0_TCI0V                                      19
+#define BSP_PRV_INT_B_NUM_TPU1_TGI1A                                      20
+#define BSP_PRV_INT_B_NUM_TPU1_TGI1B                                      21
+#define BSP_PRV_INT_B_NUM_TPU1_TCI1V                                      22
+#define BSP_PRV_INT_B_NUM_TPU1_TCI1U                                      23
+#define BSP_PRV_INT_B_NUM_TPU2_TGI2A                                      24
+#define BSP_PRV_INT_B_NUM_TPU2_TGI2B                                      25
+#define BSP_PRV_INT_B_NUM_TPU2_TCI2V                                      26
+#define BSP_PRV_INT_B_NUM_TPU2_TCI2U                                      27
+#define BSP_PRV_INT_B_NUM_TPU3_TGI3A                                      28
+#define BSP_PRV_INT_B_NUM_TPU3_TGI3B                                      29
+#define BSP_PRV_INT_B_NUM_TPU3_TGI3C                                      30
+#define BSP_PRV_INT_B_NUM_TPU3_TGI3D                                      31
+#define BSP_PRV_INT_B_NUM_TPU3_TCI3V                                      32
+#define BSP_PRV_INT_B_NUM_TPU4_TGI4A                                      33
+#define BSP_PRV_INT_B_NUM_TPU4_TGI4B                                      34
+#define BSP_PRV_INT_B_NUM_TPU4_TCI4V                                      35
+#define BSP_PRV_INT_B_NUM_TPU4_TCI4U                                      36
+#define BSP_PRV_INT_B_NUM_TPU5_TGI5A                                      37
+#define BSP_PRV_INT_B_NUM_TPU5_TGI5B                                      38
+#define BSP_PRV_INT_B_NUM_TPU5_TCI5V                                      39
+#define BSP_PRV_INT_B_NUM_TPU5_TCI5U                                      40
+#define BSP_PRV_INT_B_NUM_CMTW0_IC0I0                                     41
+#define BSP_PRV_INT_B_NUM_CMTW0_IC1I0                                     42
+#define BSP_PRV_INT_B_NUM_CMTW0_OC0I0                                     43
+#define BSP_PRV_INT_B_NUM_CMTW0_OC1I0                                     44
+#define BSP_PRV_INT_B_NUM_CMTW1_IC0I1                                     45
+#define BSP_PRV_INT_B_NUM_CMTW1_IC1I1                                     46
+#define BSP_PRV_INT_B_NUM_CMTW1_OC0I1                                     47
+#define BSP_PRV_INT_B_NUM_CMTW1_OC1I1                                     48
+#define BSP_PRV_INT_B_NUM_RTC_CUP                                         49
+#define BSP_PRV_INT_B_NUM_CAN0_RXF0                                       50
+#define BSP_PRV_INT_B_NUM_CAN0_TXF0                                       51
+#define BSP_PRV_INT_B_NUM_CAN0_RXM0                                       52
+#define BSP_PRV_INT_B_NUM_CAN0_TXM0                                       53
+#define BSP_PRV_INT_B_NUM_CAN1_RXF1                                       54
+#define BSP_PRV_INT_B_NUM_CAN1_TXF1                                       55
+#define BSP_PRV_INT_B_NUM_CAN1_RXM1                                       56
+#define BSP_PRV_INT_B_NUM_CAN1_TXM1                                       57
+#define BSP_PRV_INT_B_NUM_USB0_USBI0                                      62
+#define BSP_PRV_INT_B_NUM_S12ADC0_S12ADI0                                 64
+#define BSP_PRV_INT_B_NUM_S12ADC0_S12GBADI0                               65
+#define BSP_PRV_INT_B_NUM_S12ADC0_S12GCADI0                               66
+#define BSP_PRV_INT_B_NUM_S12ADC1_S12ADI1                                 68
+#define BSP_PRV_INT_B_NUM_S12ADC1_S12GBADI1                               69
+#define BSP_PRV_INT_B_NUM_S12ADC1_S12GCADI1                               70
+#define BSP_PRV_INT_B_NUM_RNG_RNGEND                                      76
+#define BSP_PRV_INT_B_NUM_ELC_ELSR18I                                     79
+#define BSP_PRV_INT_B_NUM_ELC_ELSR19I                                     80
+#define BSP_PRV_INT_B_NUM_TSIP_PROC_BUSY                                  85
+#define BSP_PRV_INT_B_NUM_TSIP_ROMOK                                      86
+#define BSP_PRV_INT_B_NUM_TSIP_LONG_PLG                                   87
+#define BSP_PRV_INT_B_NUM_TSIP_TEST_BUSY                                  88
+#define BSP_PRV_INT_B_NUM_TSIP_WRRDY0                                     89
+#define BSP_PRV_INT_B_NUM_TSIP_WRRDY1                                     90
+#define BSP_PRV_INT_B_NUM_TSIP_WRRDY4                                     91
+#define BSP_PRV_INT_B_NUM_TSIP_RDRDY0                                     92
+#define BSP_PRV_INT_B_NUM_TSIP_RDRDY1                                     93
+#define BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_WRRDY                            94
+#define BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_RDRDY                            95
+
+/* Available Interrupt A Sources. */
+#define BSP_PRV_INT_A_NUM_MTU0_TGIA0                                      1
+#define BSP_PRV_INT_A_NUM_MTU0_TGIB0                                      2
+#define BSP_PRV_INT_A_NUM_MTU0_TGIC0                                      3
+#define BSP_PRV_INT_A_NUM_MTU0_TGID0                                      4
+#define BSP_PRV_INT_A_NUM_MTU0_TCIV0                                      5
+#define BSP_PRV_INT_A_NUM_MTU0_TGIE0                                      6
+#define BSP_PRV_INT_A_NUM_MTU0_TGIF0                                      7
+#define BSP_PRV_INT_A_NUM_MTU1_TGIA1                                      8
+#define BSP_PRV_INT_A_NUM_MTU1_TGIB1                                      9
+#define BSP_PRV_INT_A_NUM_MTU1_TCIV1                                      10
+#define BSP_PRV_INT_A_NUM_MTU1_TCIU1                                      11
+#define BSP_PRV_INT_A_NUM_MTU2_TGIA2                                      12
+#define BSP_PRV_INT_A_NUM_MTU2_TGIB2                                      13
+#define BSP_PRV_INT_A_NUM_MTU2_TCIV2                                      14
+#define BSP_PRV_INT_A_NUM_MTU2_TCIU2                                      15
+#define BSP_PRV_INT_A_NUM_MTU3_TGIA3                                      16
+#define BSP_PRV_INT_A_NUM_MTU3_TGIB3                                      17
+#define BSP_PRV_INT_A_NUM_MTU3_TGIC3                                      18
+#define BSP_PRV_INT_A_NUM_MTU3_TGID3                                      19
+#define BSP_PRV_INT_A_NUM_MTU3_TCIV3                                      20
+#define BSP_PRV_INT_A_NUM_MTU4_TGIA4                                      21
+#define BSP_PRV_INT_A_NUM_MTU4_TGIB4                                      22
+#define BSP_PRV_INT_A_NUM_MTU4_TGIC4                                      23
+#define BSP_PRV_INT_A_NUM_MTU4_TGID4                                      24
+#define BSP_PRV_INT_A_NUM_MTU4_TCIV4                                      25
+#define BSP_PRV_INT_A_NUM_MTU5_TGIU5                                      27
+#define BSP_PRV_INT_A_NUM_MTU5_TGIV5                                      28
+#define BSP_PRV_INT_A_NUM_MTU5_TGIW5                                      29
+#define BSP_PRV_INT_A_NUM_MTU6_TGIA6                                      30
+#define BSP_PRV_INT_A_NUM_MTU6_TGIB6                                      31
+#define BSP_PRV_INT_A_NUM_MTU6_TGIC6                                      32
+#define BSP_PRV_INT_A_NUM_MTU6_TGID6                                      33
+#define BSP_PRV_INT_A_NUM_MTU6_TCIV6                                      34
+#define BSP_PRV_INT_A_NUM_MTU7_TGIA7                                      35
+#define BSP_PRV_INT_A_NUM_MTU7_TGIB7                                      36
+#define BSP_PRV_INT_A_NUM_MTU7_TGIC7                                      37
+#define BSP_PRV_INT_A_NUM_MTU7_TGID7                                      38
+#define BSP_PRV_INT_A_NUM_MTU7_TCIV7                                      39
+#define BSP_PRV_INT_A_NUM_MTU8_TGIA8                                      41
+#define BSP_PRV_INT_A_NUM_MTU8_TGIB8                                      42
+#define BSP_PRV_INT_A_NUM_MTU8_TGIC8                                      43
+#define BSP_PRV_INT_A_NUM_MTU8_TGID8                                      44
+#define BSP_PRV_INT_A_NUM_MTU8_TCIV8                                      45
+#define BSP_PRV_INT_A_NUM_AES_AESRDY                                      88
+#define BSP_PRV_INT_A_NUM_AES_AESEND                                      89
+
+/* The appropriate macros will now be defined based on the vector selections made by the user.
+ * These are the same macros that are defined for constant-mapped interrupts (vectors 0-127). This means that the
+ * code can define, setup, and use mapped interrupts the same as would be done for constant-mapped interrupts.
+ */
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2)
+#define IR_CMT2_CMI2        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2)
+#define DTCE_CMT2_CMI2      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2)
+#define IER_CMT2_CMI2       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2)
+#define IPR_CMT2_CMI2       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2)
+#define IEN_CMT2_CMI2       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2)
+#define VECT_CMT2_CMI2      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3)
+#define IR_CMT3_CMI3        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3)
+#define DTCE_CMT3_CMI3      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3)
+#define IER_CMT3_CMI3       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3)
+#define IPR_CMT3_CMI3       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3)
+#define IEN_CMT3_CMI3       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3)
+#define VECT_CMT3_CMI3      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A)
+#define IR_TPU0_TGI0A        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A)
+#define DTCE_TPU0_TGI0A      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A)
+#define IER_TPU0_TGI0A       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A)
+#define IPR_TPU0_TGI0A       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A)
+#define IEN_TPU0_TGI0A       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A)
+#define VECT_TPU0_TGI0A      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B)
+#define IR_TPU0_TGI0B        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B)
+#define DTCE_TPU0_TGI0B      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B)
+#define IER_TPU0_TGI0B       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B)
+#define IPR_TPU0_TGI0B       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B)
+#define IEN_TPU0_TGI0B       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B)
+#define VECT_TPU0_TGI0B      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C)
+#define IR_TPU0_TGI0C        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C)
+#define DTCE_TPU0_TGI0C      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C)
+#define IER_TPU0_TGI0C       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C)
+#define IPR_TPU0_TGI0C       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C)
+#define IEN_TPU0_TGI0C       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C)
+#define VECT_TPU0_TGI0C      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D)
+#define IR_TPU0_TGI0D        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D)
+#define DTCE_TPU0_TGI0D      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D)
+#define IER_TPU0_TGI0D       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D)
+#define IPR_TPU0_TGI0D       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D)
+#define IEN_TPU0_TGI0D       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D)
+#define VECT_TPU0_TGI0D      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V)
+#define IR_TPU0_TCI0V        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V)
+#define DTCE_TPU0_TCI0V      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V)
+#define IER_TPU0_TCI0V       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V)
+#define IPR_TPU0_TCI0V       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V)
+#define IEN_TPU0_TCI0V       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V)
+#define VECT_TPU0_TCI0V      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B)
+#define IR_TPU1_TGI1B        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B)
+#define DTCE_TPU1_TGI1B      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B)
+#define IER_TPU1_TGI1B       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B)
+#define IPR_TPU1_TGI1B       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B)
+#define IEN_TPU1_TGI1B       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B)
+#define VECT_TPU1_TGI1B      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V)
+#define IR_TPU1_TCI1V        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V)
+#define DTCE_TPU1_TCI1V      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V)
+#define IER_TPU1_TCI1V       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V)
+#define IPR_TPU1_TCI1V       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V)
+#define IEN_TPU1_TCI1V       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V)
+#define VECT_TPU1_TCI1V      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U)
+#define IR_TPU1_TCI1U        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U)
+#define DTCE_TPU1_TCI1U      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U)
+#define IER_TPU1_TCI1U       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U)
+#define IPR_TPU1_TCI1U       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U)
+#define IEN_TPU1_TCI1U       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U)
+#define VECT_TPU1_TCI1U      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A)
+#define IR_TPU2_TGI2A        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A)
+#define DTCE_TPU2_TGI2A      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A)
+#define IER_TPU2_TGI2A       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A)
+#define IPR_TPU2_TGI2A       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A)
+#define IEN_TPU2_TGI2A       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A)
+#define VECT_TPU2_TGI2A      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B)
+#define IR_TPU2_TGI2B        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B)
+#define DTCE_TPU2_TGI2B      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B)
+#define IER_TPU2_TGI2B       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B)
+#define IPR_TPU2_TGI2B       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B)
+#define IEN_TPU2_TGI2B       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B)
+#define VECT_TPU2_TGI2B      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V)
+#define IR_TPU2_TCI2V        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V)
+#define DTCE_TPU2_TCI2V      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V)
+#define IER_TPU2_TCI2V       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V)
+#define IPR_TPU2_TCI2V       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V)
+#define IEN_TPU2_TCI2V       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V)
+#define VECT_TPU2_TCI2V      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U)
+#define IR_TPU2_TCI2U        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U)
+#define DTCE_TPU2_TCI2U      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U)
+#define IER_TPU2_TCI2U       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U)
+#define IPR_TPU2_TCI2U       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U)
+#define IEN_TPU2_TCI2U       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U)
+#define VECT_TPU2_TCI2U      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A)
+#define IR_TPU3_TGI3A        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A)
+#define DTCE_TPU3_TGI3A      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A)
+#define IER_TPU3_TGI3A       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A)
+#define IPR_TPU3_TGI3A       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A)
+#define IEN_TPU3_TGI3A       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A)
+#define VECT_TPU3_TGI3A      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B)
+#define IR_TPU3_TGI3B        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B)
+#define DTCE_TPU3_TGI3B      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B)
+#define IER_TPU3_TGI3B       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B)
+#define IPR_TPU3_TGI3B       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B)
+#define IEN_TPU3_TGI3B       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B)
+#define VECT_TPU3_TGI3B      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A)
+#define IR_TPU1_TGI1A        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A)
+#define DTCE_TPU1_TGI1A      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A)
+#define IER_TPU1_TGI1A       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A)
+#define IPR_TPU1_TGI1A       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A)
+#define IEN_TPU1_TGI1A       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A)
+#define VECT_TPU1_TGI1A      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C)
+#define IR_TPU3_TGI3C        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C)
+#define DTCE_TPU3_TGI3C      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C)
+#define IER_TPU3_TGI3C       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C)
+#define IPR_TPU3_TGI3C       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C)
+#define IEN_TPU3_TGI3C       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C)
+#define VECT_TPU3_TGI3C      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0)
+#define IR_TMR0_CMIA0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0)
+#define DTCE_TMR0_CMIA0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0)
+#define IER_TMR0_CMIA0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0)
+#define IPR_TMR0_CMIA0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0)
+#define IEN_TMR0_CMIA0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0)
+#define VECT_TMR0_CMIA0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0)
+#define IR_TMR0_CMIB0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0)
+#define DTCE_TMR0_CMIB0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0)
+#define IER_TMR0_CMIB0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0)
+#define IPR_TMR0_CMIB0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0)
+#define IEN_TMR0_CMIB0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0)
+#define VECT_TMR0_CMIB0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0)
+#define IR_TMR0_OVI0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0)
+#define DTCE_TMR0_OVI0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0)
+#define IER_TMR0_OVI0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0)
+#define IPR_TMR0_OVI0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0)
+#define IEN_TMR0_OVI0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0)
+#define VECT_TMR0_OVI0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1)
+#define IR_TMR1_CMIA1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1)
+#define DTCE_TMR1_CMIA1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1)
+#define IER_TMR1_CMIA1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1)
+#define IPR_TMR1_CMIA1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1)
+#define IEN_TMR1_CMIA1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1)
+#define VECT_TMR1_CMIA1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1)
+#define IR_TMR1_CMIB1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1)
+#define DTCE_TMR1_CMIB1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1)
+#define IER_TMR1_CMIB1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1)
+#define IPR_TMR1_CMIB1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1)
+#define IEN_TMR1_CMIB1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1)
+#define VECT_TMR1_CMIB1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1)
+#define IR_TMR1_OVI1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1)
+#define DTCE_TMR1_OVI1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1)
+#define IER_TMR1_OVI1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1)
+#define IPR_TMR1_OVI1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1)
+#define IEN_TMR1_OVI1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1)
+#define VECT_TMR1_OVI1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2)
+#define IR_TMR2_CMIA2        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2)
+#define DTCE_TMR2_CMIA2      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2)
+#define IER_TMR2_CMIA2       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2)
+#define IPR_TMR2_CMIA2       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2)
+#define IEN_TMR2_CMIA2       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2)
+#define VECT_TMR2_CMIA2      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2)
+#define IR_TMR2_CMIB2        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2)
+#define DTCE_TMR2_CMIB2      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2)
+#define IER_TMR2_CMIB2       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2)
+#define IPR_TMR2_CMIB2       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2)
+#define IEN_TMR2_CMIB2       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2)
+#define VECT_TMR2_CMIB2      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2)
+#define IR_TMR2_OVI2        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2)
+#define DTCE_TMR2_OVI2      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2)
+#define IER_TMR2_OVI2       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2)
+#define IPR_TMR2_OVI2       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2)
+#define IEN_TMR2_OVI2       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2)
+#define VECT_TMR2_OVI2      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3)
+#define IR_TMR3_CMIA3        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3)
+#define DTCE_TMR3_CMIA3      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3)
+#define IER_TMR3_CMIA3       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3)
+#define IPR_TMR3_CMIA3       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3)
+#define IEN_TMR3_CMIA3       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3)
+#define VECT_TMR3_CMIA3      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3)
+#define IR_TMR3_CMIB3        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3)
+#define DTCE_TMR3_CMIB3      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3)
+#define IER_TMR3_CMIB3       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3)
+#define IPR_TMR3_CMIB3       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3)
+#define IEN_TMR3_CMIB3       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3)
+#define VECT_TMR3_CMIB3      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3)
+#define IR_TMR3_OVI3        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3)
+#define DTCE_TMR3_OVI3      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3)
+#define IER_TMR3_OVI3       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3)
+#define IPR_TMR3_OVI3       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3)
+#define IEN_TMR3_OVI3       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3)
+#define VECT_TMR3_OVI3      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D)
+#define IR_TPU3_TGI3D        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D)
+#define DTCE_TPU3_TGI3D      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D)
+#define IER_TPU3_TGI3D       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D)
+#define IPR_TPU3_TGI3D       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D)
+#define IEN_TPU3_TGI3D       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D)
+#define VECT_TPU3_TGI3D      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V)
+#define IR_TPU3_TCI3V        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V)
+#define DTCE_TPU3_TCI3V      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V)
+#define IER_TPU3_TCI3V       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V)
+#define IPR_TPU3_TCI3V       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V)
+#define IEN_TPU3_TCI3V       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V)
+#define VECT_TPU3_TCI3V      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A)
+#define IR_TPU4_TGI4A        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A)
+#define DTCE_TPU4_TGI4A      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A)
+#define IER_TPU4_TGI4A       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A)
+#define IPR_TPU4_TGI4A       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A)
+#define IEN_TPU4_TGI4A       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A)
+#define VECT_TPU4_TGI4A      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B)
+#define IR_TPU4_TGI4B        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B)
+#define DTCE_TPU4_TGI4B      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B)
+#define IER_TPU4_TGI4B       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B)
+#define IPR_TPU4_TGI4B       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B)
+#define IEN_TPU4_TGI4B       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B)
+#define VECT_TPU4_TGI4B      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V)
+#define IR_TPU4_TCI4V        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V)
+#define DTCE_TPU4_TCI4V      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V)
+#define IER_TPU4_TCI4V       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V)
+#define IPR_TPU4_TCI4V       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V)
+#define IEN_TPU4_TCI4V       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V)
+#define VECT_TPU4_TCI4V      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U)
+#define IR_TPU4_TCI4U        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U)
+#define DTCE_TPU4_TCI4U      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U)
+#define IER_TPU4_TCI4U       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U)
+#define IPR_TPU4_TCI4U       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U)
+#define IEN_TPU4_TCI4U       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U)
+#define VECT_TPU4_TCI4U      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A)
+#define IR_TPU5_TGI5A        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A)
+#define DTCE_TPU5_TGI5A      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A)
+#define IER_TPU5_TGI5A       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A)
+#define IPR_TPU5_TGI5A       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A)
+#define IEN_TPU5_TGI5A       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A)
+#define VECT_TPU5_TGI5A      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B)
+#define IR_TPU5_TGI5B        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B)
+#define DTCE_TPU5_TGI5B      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B)
+#define IER_TPU5_TGI5B       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B)
+#define IPR_TPU5_TGI5B       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B)
+#define IEN_TPU5_TGI5B       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B)
+#define VECT_TPU5_TGI5B      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V)
+#define IR_TPU5_TCI5V        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V)
+#define DTCE_TPU5_TCI5V      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V)
+#define IER_TPU5_TCI5V       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V)
+#define IPR_TPU5_TCI5V       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V)
+#define IEN_TPU5_TCI5V       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V)
+#define VECT_TPU5_TCI5V      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U)
+#define IR_TPU5_TCI5U        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U)
+#define DTCE_TPU5_TCI5U      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U)
+#define IER_TPU5_TCI5U       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U)
+#define IPR_TPU5_TCI5U       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U)
+#define IEN_TPU5_TCI5U       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U)
+#define VECT_TPU5_TCI5U      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0)
+#define IR_CMTW0_IC0I0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0)
+#define DTCE_CMTW0_IC0I0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0)
+#define IER_CMTW0_IC0I0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0)
+#define IPR_CMTW0_IC0I0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0)
+#define IEN_CMTW0_IC0I0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0)
+#define VECT_CMTW0_IC0I0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0)
+#define IR_CMTW0_IC1I0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0)
+#define DTCE_CMTW0_IC1I0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0)
+#define IER_CMTW0_IC1I0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0)
+#define IPR_CMTW0_IC1I0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0)
+#define IEN_CMTW0_IC1I0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0)
+#define VECT_CMTW0_IC1I0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0)
+#define IR_CMTW0_OC0I0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0)
+#define DTCE_CMTW0_OC0I0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0)
+#define IER_CMTW0_OC0I0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0)
+#define IPR_CMTW0_OC0I0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0)
+#define IEN_CMTW0_OC0I0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0)
+#define VECT_CMTW0_OC0I0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0)
+#define IR_CMTW0_OC1I0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0)
+#define DTCE_CMTW0_OC1I0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0)
+#define IER_CMTW0_OC1I0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0)
+#define IPR_CMTW0_OC1I0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0)
+#define IEN_CMTW0_OC1I0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0)
+#define VECT_CMTW0_OC1I0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1)
+#define IR_CMTW1_IC0I1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1)
+#define DTCE_CMTW1_IC0I1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1)
+#define IER_CMTW1_IC0I1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1)
+#define IPR_CMTW1_IC0I1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1)
+#define IEN_CMTW1_IC0I1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1)
+#define VECT_CMTW1_IC0I1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1)
+#define IR_CMTW1_IC1I1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1)
+#define DTCE_CMTW1_IC1I1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1)
+#define IER_CMTW1_IC1I1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1)
+#define IPR_CMTW1_IC1I1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1)
+#define IEN_CMTW1_IC1I1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1)
+#define VECT_CMTW1_IC1I1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1)
+#define IR_CMTW1_OC0I1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1)
+#define DTCE_CMTW1_OC0I1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1)
+#define IER_CMTW1_OC0I1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1)
+#define IPR_CMTW1_OC0I1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1)
+#define IEN_CMTW1_OC0I1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1)
+#define VECT_CMTW1_OC0I1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1)
+#define IR_CMTW1_OC1I1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1)
+#define DTCE_CMTW1_OC1I1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1)
+#define IER_CMTW1_OC1I1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1)
+#define IPR_CMTW1_OC1I1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1)
+#define IEN_CMTW1_OC1I1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1)
+#define VECT_CMTW1_OC1I1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP)
+#define IR_RTC_CUP        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP)
+#define DTCE_RTC_CUP      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP)
+#define IER_RTC_CUP       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP)
+#define IPR_RTC_CUP       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP)
+#define IEN_RTC_CUP       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP)
+#define VECT_RTC_CUP      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0)
+#define IR_CAN0_RXF0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0)
+#define DTCE_CAN0_RXF0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0)
+#define IER_CAN0_RXF0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0)
+#define IPR_CAN0_RXF0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0)
+#define IEN_CAN0_RXF0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0)
+#define VECT_CAN0_RXF0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0)
+#define IR_CAN0_TXF0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0)
+#define DTCE_CAN0_TXF0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0)
+#define IER_CAN0_TXF0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0)
+#define IPR_CAN0_TXF0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0)
+#define IEN_CAN0_TXF0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0)
+#define VECT_CAN0_TXF0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0)
+#define IR_CAN0_RXM0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0)
+#define DTCE_CAN0_RXM0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0)
+#define IER_CAN0_RXM0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0)
+#define IPR_CAN0_RXM0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0)
+#define IEN_CAN0_RXM0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0)
+#define VECT_CAN0_RXM0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0)
+#define IR_CAN0_TXM0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0)
+#define DTCE_CAN0_TXM0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0)
+#define IER_CAN0_TXM0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0)
+#define IPR_CAN0_TXM0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0)
+#define IEN_CAN0_TXM0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0)
+#define VECT_CAN0_TXM0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1)
+#define IR_CAN1_RXF1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1)
+#define DTCE_CAN1_RXF1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1)
+#define IER_CAN1_RXF1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1)
+#define IPR_CAN1_RXF1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1)
+#define IEN_CAN1_RXF1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1)
+#define VECT_CAN1_RXF1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1)
+#define IR_CAN1_TXF1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1)
+#define DTCE_CAN1_TXF1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1)
+#define IER_CAN1_TXF1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1)
+#define IPR_CAN1_TXF1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1)
+#define IEN_CAN1_TXF1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1)
+#define VECT_CAN1_TXF1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1)
+#define IR_CAN1_RXM1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1)
+#define DTCE_CAN1_RXM1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1)
+#define IER_CAN1_RXM1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1)
+#define IPR_CAN1_RXM1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1)
+#define IEN_CAN1_RXM1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1)
+#define VECT_CAN1_RXM1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1)
+#define IR_CAN1_TXM1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1)
+#define DTCE_CAN1_TXM1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1)
+#define IER_CAN1_TXM1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1)
+#define IPR_CAN1_TXM1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1)
+#define IEN_CAN1_TXM1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1)
+#define VECT_CAN1_TXM1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0)
+#define IR_USB0_USBI0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0)
+#define DTCE_USB0_USBI0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0)
+#define IER_USB0_USBI0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0)
+#define IPR_USB0_USBI0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0)
+#define IEN_USB0_USBI0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0)
+#define VECT_USB0_USBI0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0)
+#define IR_S12ADC0_S12ADI0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0)
+#define DTCE_S12ADC0_S12ADI0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0)
+#define IER_S12ADC0_S12ADI0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0)
+#define IPR_S12ADC0_S12ADI0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0)
+#define IEN_S12ADC0_S12ADI0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0)
+#define VECT_S12ADC0_S12ADI0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0)
+#define IR_S12ADC0_S12GBADI0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0)
+#define DTCE_S12ADC0_S12GBADI0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0)
+#define IER_S12ADC0_S12GBADI0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0)
+#define IPR_S12ADC0_S12GBADI0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0)
+#define IEN_S12ADC0_S12GBADI0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0)
+#define VECT_S12ADC0_S12GBADI0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0)
+#define IR_S12ADC0_S12GCADI0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0)
+#define DTCE_S12ADC0_S12GCADI0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0)
+#define IER_S12ADC0_S12GCADI0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0)
+#define IPR_S12ADC0_S12GCADI0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0)
+#define IEN_S12ADC0_S12GCADI0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0)
+#define VECT_S12ADC0_S12GCADI0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1)
+#define IR_S12ADC1_S12ADI1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1)
+#define DTCE_S12ADC1_S12ADI1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1)
+#define IER_S12ADC1_S12ADI1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1)
+#define IPR_S12ADC1_S12ADI1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1)
+#define IEN_S12ADC1_S12ADI1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1)
+#define VECT_S12ADC1_S12ADI1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1)
+#define IR_S12ADC1_S12GBADI1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1)
+#define DTCE_S12ADC1_S12GBADI1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1)
+#define IER_S12ADC1_S12GBADI1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1)
+#define IPR_S12ADC1_S12GBADI1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1)
+#define IEN_S12ADC1_S12GBADI1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1)
+#define VECT_S12ADC1_S12GBADI1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1)
+#define IR_S12ADC1_S12GCADI1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1)
+#define DTCE_S12ADC1_S12GCADI1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1)
+#define IER_S12ADC1_S12GCADI1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1)
+#define IPR_S12ADC1_S12GCADI1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1)
+#define IEN_S12ADC1_S12GCADI1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1)
+#define VECT_S12ADC1_S12GCADI1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND)
+#define IR_RNG_RNGEND        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND)
+#define DTCE_RNG_RNGEND      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND)
+#define IER_RNG_RNGEND       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND)
+#define IPR_RNG_RNGEND       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND)
+#define IEN_RNG_RNGEND       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND)
+#define VECT_RNG_RNGEND      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I)
+#define IR_ELC_ELSR18I        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I)
+#define DTCE_ELC_ELSR18I      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I)
+#define IER_ELC_ELSR18I       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I)
+#define IPR_ELC_ELSR18I       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I)
+#define IEN_ELC_ELSR18I       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I)
+#define VECT_ELC_ELSR18I      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I)
+#define IR_ELC_ELSR19I        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I)
+#define DTCE_ELC_ELSR19I      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I)
+#define IER_ELC_ELSR19I       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I)
+#define IPR_ELC_ELSR19I       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I)
+#define IEN_ELC_ELSR19I       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I)
+#define VECT_ELC_ELSR19I      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY)
+#define IR_TSIP_PROC_BUSY        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY)
+#define DTCE_TSIP_PROC_BUSY      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY)
+#define IER_TSIP_PROC_BUSY       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY)
+#define IPR_TSIP_PROC_BUSY       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY)
+#define IEN_TSIP_PROC_BUSY       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY)
+#define VECT_TSIP_PROC_BUSY      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK)
+#define IR_TSIP_ROMOK        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK)
+#define DTCE_TSIP_ROMOK      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK)
+#define IER_TSIP_ROMOK       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK)
+#define IPR_TSIP_ROMOK       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK)
+#define IEN_TSIP_ROMOK       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK)
+#define VECT_TSIP_ROMOK      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG)
+#define IR_TSIP_LONG_PLG        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG)
+#define DTCE_TSIP_LONG_PLG      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG)
+#define IER_TSIP_LONG_PLG       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG)
+#define IPR_TSIP_LONG_PLG       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG)
+#define IEN_TSIP_LONG_PLG       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG)
+#define VECT_TSIP_LONG_PLG      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY)
+#define IR_TSIP_TEST_BUSY        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY)
+#define DTCE_TSIP_TEST_BUSY      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY)
+#define IER_TSIP_TEST_BUSY       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY)
+#define IPR_TSIP_TEST_BUSY       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY)
+#define IEN_TSIP_TEST_BUSY       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY)
+#define VECT_TSIP_TEST_BUSY      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0)
+#define IR_TSIP_WRRDY0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0)
+#define DTCE_TSIP_WRRDY0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0)
+#define IER_TSIP_WRRDY0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0)
+#define IPR_TSIP_WRRDY0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0)
+#define IEN_TSIP_WRRDY0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0)
+#define VECT_TSIP_WRRDY0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1)
+#define IR_TSIP_WRRDY1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1)
+#define DTCE_TSIP_WRRDY1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1)
+#define IER_TSIP_WRRDY1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1)
+#define IPR_TSIP_WRRDY1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1)
+#define IEN_TSIP_WRRDY1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1)
+#define VECT_TSIP_WRRDY1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4)
+#define IR_TSIP_WRRDY4        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4)
+#define DTCE_TSIP_WRRDY4      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4)
+#define IER_TSIP_WRRDY4       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4)
+#define IPR_TSIP_WRRDY4       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4)
+#define IEN_TSIP_WRRDY4       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4)
+#define VECT_TSIP_WRRDY4      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0)
+#define IR_TSIP_RDRDY0        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0)
+#define DTCE_TSIP_RDRDY0      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0)
+#define IER_TSIP_RDRDY0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0)
+#define IPR_TSIP_RDRDY0       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0)
+#define IEN_TSIP_RDRDY0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0)
+#define VECT_TSIP_RDRDY0      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1)
+#define IR_TSIP_RDRDY1        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1)
+#define DTCE_TSIP_RDRDY1      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1)
+#define IER_TSIP_RDRDY1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1)
+#define IPR_TSIP_RDRDY1       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1)
+#define IEN_TSIP_RDRDY1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1)
+#define VECT_TSIP_RDRDY1      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY)
+#define IR_TSIP_INTEGRATE_WRRDY        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY)
+#define DTCE_TSIP_INTEGRATE_WRRDY      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY)
+#define IER_TSIP_INTEGRATE_WRRDY       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY)
+#define IPR_TSIP_INTEGRATE_WRRDY       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY)
+#define IEN_TSIP_INTEGRATE_WRRDY       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY)
+#define VECT_TSIP_INTEGRATE_WRRDY      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY)
+#define IR_TSIP_INTEGRATE_RDRDY        BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY)
+#define DTCE_TSIP_INTEGRATE_RDRDY      BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY)
+#define IER_TSIP_INTEGRATE_RDRDY       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY)
+#define IPR_TSIP_INTEGRATE_RDRDY       BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY)
+#define IEN_TSIP_INTEGRATE_RDRDY       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY)
+#define VECT_TSIP_INTEGRATE_RDRDY      BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1)
+#define IR_MTU1_TGIA1        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1)
+#define DTCE_MTU1_TGIA1      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1)
+#define IER_MTU1_TGIA1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1)
+#define IPR_MTU1_TGIA1       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1)
+#define IEN_MTU1_TGIA1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1)
+#define VECT_MTU1_TGIA1      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0)
+#define IR_MTU0_TGIA0        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0)
+#define DTCE_MTU0_TGIA0      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0)
+#define IER_MTU0_TGIA0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0)
+#define IPR_MTU0_TGIA0       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0)
+#define IEN_MTU0_TGIA0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0)
+#define VECT_MTU0_TGIA0      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0)
+#define IR_MTU0_TGIB0        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0)
+#define DTCE_MTU0_TGIB0      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0)
+#define IER_MTU0_TGIB0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0)
+#define IPR_MTU0_TGIB0       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0)
+#define IEN_MTU0_TGIB0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0)
+#define VECT_MTU0_TGIB0      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0)
+#define IR_MTU0_TGIC0        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0)
+#define DTCE_MTU0_TGIC0      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0)
+#define IER_MTU0_TGIC0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0)
+#define IPR_MTU0_TGIC0       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0)
+#define IEN_MTU0_TGIC0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0)
+#define VECT_MTU0_TGIC0      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0)
+#define IR_MTU0_TGID0        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0)
+#define DTCE_MTU0_TGID0      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0)
+#define IER_MTU0_TGID0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0)
+#define IPR_MTU0_TGID0       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0)
+#define IEN_MTU0_TGID0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0)
+#define VECT_MTU0_TGID0      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0)
+#define IR_MTU0_TCIV0        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0)
+#define DTCE_MTU0_TCIV0      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0)
+#define IER_MTU0_TCIV0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0)
+#define IPR_MTU0_TCIV0       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0)
+#define IEN_MTU0_TCIV0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0)
+#define VECT_MTU0_TCIV0      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0)
+#define IR_MTU0_TGIE0        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0)
+#define DTCE_MTU0_TGIE0      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0)
+#define IER_MTU0_TGIE0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0)
+#define IPR_MTU0_TGIE0       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0)
+#define IEN_MTU0_TGIE0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0)
+#define VECT_MTU0_TGIE0      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0)
+#define IR_MTU0_TGIF0        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0)
+#define DTCE_MTU0_TGIF0      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0)
+#define IER_MTU0_TGIF0       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0)
+#define IPR_MTU0_TGIF0       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0)
+#define IEN_MTU0_TGIF0       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0)
+#define VECT_MTU0_TGIF0      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1)
+#define IR_MTU1_TGIB1        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1)
+#define DTCE_MTU1_TGIB1      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1)
+#define IER_MTU1_TGIB1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1)
+#define IPR_MTU1_TGIB1       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1)
+#define IEN_MTU1_TGIB1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1)
+#define VECT_MTU1_TGIB1      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1)
+#define IR_MTU1_TCIV1        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1)
+#define DTCE_MTU1_TCIV1      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1)
+#define IER_MTU1_TCIV1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1)
+#define IPR_MTU1_TCIV1       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1)
+#define IEN_MTU1_TCIV1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1)
+#define VECT_MTU1_TCIV1      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1)
+#define IR_MTU1_TCIU1        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1)
+#define DTCE_MTU1_TCIU1      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1)
+#define IER_MTU1_TCIU1       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1)
+#define IPR_MTU1_TCIU1       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1)
+#define IEN_MTU1_TCIU1       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1)
+#define VECT_MTU1_TCIU1      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2)
+#define IR_MTU2_TGIA2        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2)
+#define DTCE_MTU2_TGIA2      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2)
+#define IER_MTU2_TGIA2       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2)
+#define IPR_MTU2_TGIA2       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2)
+#define IEN_MTU2_TGIA2       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2)
+#define VECT_MTU2_TGIA2      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2)
+#define IR_MTU2_TGIB2        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2)
+#define DTCE_MTU2_TGIB2      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2)
+#define IER_MTU2_TGIB2       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2)
+#define IPR_MTU2_TGIB2       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2)
+#define IEN_MTU2_TGIB2       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2)
+#define VECT_MTU2_TGIB2      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2)
+#define IR_MTU2_TCIV2        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2)
+#define DTCE_MTU2_TCIV2      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2)
+#define IER_MTU2_TCIV2       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2)
+#define IPR_MTU2_TCIV2       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2)
+#define IEN_MTU2_TCIV2       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2)
+#define VECT_MTU2_TCIV2      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2)
+#define IR_MTU2_TCIU2        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2)
+#define DTCE_MTU2_TCIU2      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2)
+#define IER_MTU2_TCIU2       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2)
+#define IPR_MTU2_TCIU2       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2)
+#define IEN_MTU2_TCIU2       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2)
+#define VECT_MTU2_TCIU2      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3)
+#define IR_MTU3_TGIA3        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3)
+#define DTCE_MTU3_TGIA3      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3)
+#define IER_MTU3_TGIA3       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3)
+#define IPR_MTU3_TGIA3       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3)
+#define IEN_MTU3_TGIA3       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3)
+#define VECT_MTU3_TGIA3      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3)
+#define IR_MTU3_TGIB3        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3)
+#define DTCE_MTU3_TGIB3      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3)
+#define IER_MTU3_TGIB3       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3)
+#define IPR_MTU3_TGIB3       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3)
+#define IEN_MTU3_TGIB3       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3)
+#define VECT_MTU3_TGIB3      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3)
+#define IR_MTU3_TGIC3        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3)
+#define DTCE_MTU3_TGIC3      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3)
+#define IER_MTU3_TGIC3       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3)
+#define IPR_MTU3_TGIC3       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3)
+#define IEN_MTU3_TGIC3       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3)
+#define VECT_MTU3_TGIC3      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3)
+#define IR_MTU3_TGID3        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3)
+#define DTCE_MTU3_TGID3      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3)
+#define IER_MTU3_TGID3       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3)
+#define IPR_MTU3_TGID3       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3)
+#define IEN_MTU3_TGID3       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3)
+#define VECT_MTU3_TGID3      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3)
+#define IR_MTU3_TCIV3        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3)
+#define DTCE_MTU3_TCIV3      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3)
+#define IER_MTU3_TCIV3       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3)
+#define IPR_MTU3_TCIV3       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3)
+#define IEN_MTU3_TCIV3       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3)
+#define VECT_MTU3_TCIV3      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4)
+#define IR_MTU4_TGIA4        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4)
+#define DTCE_MTU4_TGIA4      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4)
+#define IER_MTU4_TGIA4       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4)
+#define IPR_MTU4_TGIA4       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4)
+#define IEN_MTU4_TGIA4       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4)
+#define VECT_MTU4_TGIA4      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4)
+#define IR_MTU4_TGIB4        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4)
+#define DTCE_MTU4_TGIB4      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4)
+#define IER_MTU4_TGIB4       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4)
+#define IPR_MTU4_TGIB4       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4)
+#define IEN_MTU4_TGIB4       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4)
+#define VECT_MTU4_TGIB4      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4)
+#define IR_MTU4_TGIC4        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4)
+#define DTCE_MTU4_TGIC4      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4)
+#define IER_MTU4_TGIC4       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4)
+#define IPR_MTU4_TGIC4       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4)
+#define IEN_MTU4_TGIC4       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4)
+#define VECT_MTU4_TGIC4      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4)
+#define IR_MTU4_TGID4        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4)
+#define DTCE_MTU4_TGID4      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4)
+#define IER_MTU4_TGID4       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4)
+#define IPR_MTU4_TGID4       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4)
+#define IEN_MTU4_TGID4       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4)
+#define VECT_MTU4_TGID4      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4)
+#define IR_MTU4_TCIV4        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4)
+#define DTCE_MTU4_TCIV4      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4)
+#define IER_MTU4_TCIV4       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4)
+#define IPR_MTU4_TCIV4       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4)
+#define IEN_MTU4_TCIV4       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4)
+#define VECT_MTU4_TCIV4      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5)
+#define IR_MTU5_TGIU5        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5)
+#define DTCE_MTU5_TGIU5      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5)
+#define IER_MTU5_TGIU5       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5)
+#define IPR_MTU5_TGIU5       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5)
+#define IEN_MTU5_TGIU5       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5)
+#define VECT_MTU5_TGIU5      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5)
+#define IR_MTU5_TGIV5        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5)
+#define DTCE_MTU5_TGIV5      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5)
+#define IER_MTU5_TGIV5       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5)
+#define IPR_MTU5_TGIV5       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5)
+#define IEN_MTU5_TGIV5       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5)
+#define VECT_MTU5_TGIV5      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5)
+#define IR_MTU5_TGIW5        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5)
+#define DTCE_MTU5_TGIW5      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5)
+#define IER_MTU5_TGIW5       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5)
+#define IPR_MTU5_TGIW5       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5)
+#define IEN_MTU5_TGIW5       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5)
+#define VECT_MTU5_TGIW5      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6)
+#define IR_MTU6_TGIA6        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6)
+#define DTCE_MTU6_TGIA6      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6)
+#define IER_MTU6_TGIA6       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6)
+#define IPR_MTU6_TGIA6       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6)
+#define IEN_MTU6_TGIA6       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6)
+#define VECT_MTU6_TGIA6      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6)
+#define IR_MTU6_TGIB6        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6)
+#define DTCE_MTU6_TGIB6      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6)
+#define IER_MTU6_TGIB6       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6)
+#define IPR_MTU6_TGIB6       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6)
+#define IEN_MTU6_TGIB6       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6)
+#define VECT_MTU6_TGIB6      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6)
+#define IR_MTU6_TGIC6        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6)
+#define DTCE_MTU6_TGIC6      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6)
+#define IER_MTU6_TGIC6       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6)
+#define IPR_MTU6_TGIC6       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6)
+#define IEN_MTU6_TGIC6       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6)
+#define VECT_MTU6_TGIC6      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6)
+#define IR_MTU6_TGID6        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6)
+#define DTCE_MTU6_TGID6      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6)
+#define IER_MTU6_TGID6       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6)
+#define IPR_MTU6_TGID6       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6)
+#define IEN_MTU6_TGID6       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6)
+#define VECT_MTU6_TGID6      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6)
+#define IR_MTU6_TCIV6        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6)
+#define DTCE_MTU6_TCIV6      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6)
+#define IER_MTU6_TCIV6       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6)
+#define IPR_MTU6_TCIV6       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6)
+#define IEN_MTU6_TCIV6       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6)
+#define VECT_MTU6_TCIV6      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7)
+#define IR_MTU7_TGIA7        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7)
+#define DTCE_MTU7_TGIA7      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7)
+#define IER_MTU7_TGIA7       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7)
+#define IPR_MTU7_TGIA7       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7)
+#define IEN_MTU7_TGIA7       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7)
+#define VECT_MTU7_TGIA7      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7)
+#define IR_MTU7_TGIB7        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7)
+#define DTCE_MTU7_TGIB7      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7)
+#define IER_MTU7_TGIB7       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7)
+#define IPR_MTU7_TGIB7       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7)
+#define IEN_MTU7_TGIB7       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7)
+#define VECT_MTU7_TGIB7      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7)
+#define IR_MTU7_TGIC7        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7)
+#define DTCE_MTU7_TGIC7      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7)
+#define IER_MTU7_TGIC7       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7)
+#define IPR_MTU7_TGIC7       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7)
+#define IEN_MTU7_TGIC7       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7)
+#define VECT_MTU7_TGIC7      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7)
+#define IR_MTU7_TGID7        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7)
+#define DTCE_MTU7_TGID7      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7)
+#define IER_MTU7_TGID7       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7)
+#define IPR_MTU7_TGID7       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7)
+#define IEN_MTU7_TGID7       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7)
+#define VECT_MTU7_TGID7      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7)
+#define IR_MTU7_TCIV7        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7)
+#define DTCE_MTU7_TCIV7      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7)
+#define IER_MTU7_TCIV7       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7)
+#define IPR_MTU7_TCIV7       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7)
+#define IEN_MTU7_TCIV7       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7)
+#define VECT_MTU7_TCIV7      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8)
+#define IR_MTU8_TGIA8        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8)
+#define DTCE_MTU8_TGIA8      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8)
+#define IER_MTU8_TGIA8       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8)
+#define IPR_MTU8_TGIA8       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8)
+#define IEN_MTU8_TGIA8       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8)
+#define VECT_MTU8_TGIA8      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8)
+#define IR_MTU8_TGIB8        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8)
+#define DTCE_MTU8_TGIB8      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8)
+#define IER_MTU8_TGIB8       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8)
+#define IPR_MTU8_TGIB8       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8)
+#define IEN_MTU8_TGIB8       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8)
+#define VECT_MTU8_TGIB8      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8)
+#define IR_MTU8_TGIC8        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8)
+#define DTCE_MTU8_TGIC8      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8)
+#define IER_MTU8_TGIC8       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8)
+#define IPR_MTU8_TGIC8       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8)
+#define IEN_MTU8_TGIC8       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8)
+#define VECT_MTU8_TGIC8      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8)
+#define IR_MTU8_TGID8        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8)
+#define DTCE_MTU8_TGID8      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8)
+#define IER_MTU8_TGID8       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8)
+#define IPR_MTU8_TGID8       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8)
+#define IEN_MTU8_TGID8       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8)
+#define VECT_MTU8_TGID8      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8)
+#define IR_MTU8_TCIV8        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8)
+#define DTCE_MTU8_TCIV8      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8)
+#define IER_MTU8_TCIV8       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8)
+#define IPR_MTU8_TCIV8       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8)
+#define IEN_MTU8_TCIV8       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8)
+#define VECT_MTU8_TCIV8      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY)
+#define IR_AES_AESRDY        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY)
+#define DTCE_AES_AESRDY      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY)
+#define IER_AES_AESRDY       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY)
+#define IPR_AES_AESRDY       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY)
+#define IEN_AES_AESRDY       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY)
+#define VECT_AES_AESRDY      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY)
+#endif
+
+#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND)
+#define IR_AES_AESEND        BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND)
+#define DTCE_AES_AESEND      BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND)
+#define IER_AES_AESEND       BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND)
+#define IPR_AES_AESEND       BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND)
+#define IEN_AES_AESEND       BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND)
+#define VECT_AES_AESEND      BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND)
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+void bsp_mapped_interrupt_open(void); //r_bsp internal function. DO NOT CALL.
+
+#endif /* MCU_MAPPED_INTERRUPTS_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_mapped_interrupts_private.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_mapped_interrupts_private.h
new file mode 100644
index 00000000..b3a2a86d
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/mcu_mapped_interrupts_private.h
@@ -0,0 +1,361 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : mcu_mapped_interrupts_private.h
+* Description  : This module contains macros used for mapping interrupts.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 01.10.2016 1.00     First Release
+*         : 28.02.2019 1.01     Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef MCU_MAPPED_INTERRUPTS_PRIVATE_H
+#define MCU_MAPPED_INTERRUPTS_PRIVATE_H
+
+/* These macros are calculated values for x % 8. These macros are used when preprocessor arithmetic cannot be used.
+ * For example, 'IEN0'-'IEN7' needs to be defined for a macro based on 'vector_number % 8' but preprocessor arithmetic
+ * is only evaluated at compile-time when it is used in a preprocessor conditional. For this reason the calculated
+ * value of 'vector_number % 8' must be calculated before compile-time.
+ */
+#define BSP_PRV_CALC_128_MOD_8               0
+#define BSP_PRV_CALC_129_MOD_8               1
+#define BSP_PRV_CALC_130_MOD_8               2
+#define BSP_PRV_CALC_131_MOD_8               3
+#define BSP_PRV_CALC_132_MOD_8               4
+#define BSP_PRV_CALC_133_MOD_8               5
+#define BSP_PRV_CALC_134_MOD_8               6
+#define BSP_PRV_CALC_135_MOD_8               7
+#define BSP_PRV_CALC_136_MOD_8               0
+#define BSP_PRV_CALC_137_MOD_8               1
+#define BSP_PRV_CALC_138_MOD_8               2
+#define BSP_PRV_CALC_139_MOD_8               3
+#define BSP_PRV_CALC_140_MOD_8               4
+#define BSP_PRV_CALC_141_MOD_8               5
+#define BSP_PRV_CALC_142_MOD_8               6
+#define BSP_PRV_CALC_143_MOD_8               7
+#define BSP_PRV_CALC_144_MOD_8               0
+#define BSP_PRV_CALC_145_MOD_8               1
+#define BSP_PRV_CALC_146_MOD_8               2
+#define BSP_PRV_CALC_147_MOD_8               3
+#define BSP_PRV_CALC_148_MOD_8               4
+#define BSP_PRV_CALC_149_MOD_8               5
+#define BSP_PRV_CALC_150_MOD_8               6
+#define BSP_PRV_CALC_151_MOD_8               7
+#define BSP_PRV_CALC_152_MOD_8               0
+#define BSP_PRV_CALC_153_MOD_8               1
+#define BSP_PRV_CALC_154_MOD_8               2
+#define BSP_PRV_CALC_155_MOD_8               3
+#define BSP_PRV_CALC_156_MOD_8               4
+#define BSP_PRV_CALC_157_MOD_8               5
+#define BSP_PRV_CALC_158_MOD_8               6
+#define BSP_PRV_CALC_159_MOD_8               7
+#define BSP_PRV_CALC_160_MOD_8               0
+#define BSP_PRV_CALC_161_MOD_8               1
+#define BSP_PRV_CALC_162_MOD_8               2
+#define BSP_PRV_CALC_163_MOD_8               3
+#define BSP_PRV_CALC_164_MOD_8               4
+#define BSP_PRV_CALC_165_MOD_8               5
+#define BSP_PRV_CALC_166_MOD_8               6
+#define BSP_PRV_CALC_167_MOD_8               7
+#define BSP_PRV_CALC_168_MOD_8               0
+#define BSP_PRV_CALC_169_MOD_8               1
+#define BSP_PRV_CALC_170_MOD_8               2
+#define BSP_PRV_CALC_171_MOD_8               3
+#define BSP_PRV_CALC_172_MOD_8               4
+#define BSP_PRV_CALC_173_MOD_8               5
+#define BSP_PRV_CALC_174_MOD_8               6
+#define BSP_PRV_CALC_175_MOD_8               7
+#define BSP_PRV_CALC_176_MOD_8               0
+#define BSP_PRV_CALC_177_MOD_8               1
+#define BSP_PRV_CALC_178_MOD_8               2
+#define BSP_PRV_CALC_179_MOD_8               3
+#define BSP_PRV_CALC_180_MOD_8               4
+#define BSP_PRV_CALC_181_MOD_8               5
+#define BSP_PRV_CALC_182_MOD_8               6
+#define BSP_PRV_CALC_183_MOD_8               7
+#define BSP_PRV_CALC_184_MOD_8               0
+#define BSP_PRV_CALC_185_MOD_8               1
+#define BSP_PRV_CALC_186_MOD_8               2
+#define BSP_PRV_CALC_187_MOD_8               3
+#define BSP_PRV_CALC_188_MOD_8               4
+#define BSP_PRV_CALC_189_MOD_8               5
+#define BSP_PRV_CALC_190_MOD_8               6
+#define BSP_PRV_CALC_191_MOD_8               7
+#define BSP_PRV_CALC_192_MOD_8               0
+#define BSP_PRV_CALC_193_MOD_8               1
+#define BSP_PRV_CALC_194_MOD_8               2
+#define BSP_PRV_CALC_195_MOD_8               3
+#define BSP_PRV_CALC_196_MOD_8               4
+#define BSP_PRV_CALC_197_MOD_8               5
+#define BSP_PRV_CALC_198_MOD_8               6
+#define BSP_PRV_CALC_199_MOD_8               7
+#define BSP_PRV_CALC_200_MOD_8               0
+#define BSP_PRV_CALC_201_MOD_8               1
+#define BSP_PRV_CALC_202_MOD_8               2
+#define BSP_PRV_CALC_203_MOD_8               3
+#define BSP_PRV_CALC_204_MOD_8               4
+#define BSP_PRV_CALC_205_MOD_8               5
+#define BSP_PRV_CALC_206_MOD_8               6
+#define BSP_PRV_CALC_207_MOD_8               7
+#define BSP_PRV_CALC_208_MOD_8               0
+#define BSP_PRV_CALC_209_MOD_8               1
+#define BSP_PRV_CALC_210_MOD_8               2
+#define BSP_PRV_CALC_211_MOD_8               3
+#define BSP_PRV_CALC_212_MOD_8               4
+#define BSP_PRV_CALC_213_MOD_8               5
+#define BSP_PRV_CALC_214_MOD_8               6
+#define BSP_PRV_CALC_215_MOD_8               7
+#define BSP_PRV_CALC_216_MOD_8               0
+#define BSP_PRV_CALC_217_MOD_8               1
+#define BSP_PRV_CALC_218_MOD_8               2
+#define BSP_PRV_CALC_219_MOD_8               3
+#define BSP_PRV_CALC_220_MOD_8               4
+#define BSP_PRV_CALC_221_MOD_8               5
+#define BSP_PRV_CALC_222_MOD_8               6
+#define BSP_PRV_CALC_223_MOD_8               7
+#define BSP_PRV_CALC_224_MOD_8               0
+#define BSP_PRV_CALC_225_MOD_8               1
+#define BSP_PRV_CALC_226_MOD_8               2
+#define BSP_PRV_CALC_227_MOD_8               3
+#define BSP_PRV_CALC_228_MOD_8               4
+#define BSP_PRV_CALC_229_MOD_8               5
+#define BSP_PRV_CALC_230_MOD_8               6
+#define BSP_PRV_CALC_231_MOD_8               7
+#define BSP_PRV_CALC_232_MOD_8               0
+#define BSP_PRV_CALC_233_MOD_8               1
+#define BSP_PRV_CALC_234_MOD_8               2
+#define BSP_PRV_CALC_235_MOD_8               3
+#define BSP_PRV_CALC_236_MOD_8               4
+#define BSP_PRV_CALC_237_MOD_8               5
+#define BSP_PRV_CALC_238_MOD_8               6
+#define BSP_PRV_CALC_239_MOD_8               7
+#define BSP_PRV_CALC_240_MOD_8               0
+#define BSP_PRV_CALC_241_MOD_8               1
+#define BSP_PRV_CALC_242_MOD_8               2
+#define BSP_PRV_CALC_243_MOD_8               3
+#define BSP_PRV_CALC_244_MOD_8               4
+#define BSP_PRV_CALC_245_MOD_8               5
+#define BSP_PRV_CALC_246_MOD_8               6
+#define BSP_PRV_CALC_247_MOD_8               7
+#define BSP_PRV_CALC_248_MOD_8               0
+#define BSP_PRV_CALC_249_MOD_8               1
+#define BSP_PRV_CALC_250_MOD_8               2
+#define BSP_PRV_CALC_251_MOD_8               3
+#define BSP_PRV_CALC_252_MOD_8               4
+#define BSP_PRV_CALC_253_MOD_8               5
+#define BSP_PRV_CALC_254_MOD_8               6
+#define BSP_PRV_CALC_255_MOD_8               7
+
+/* These macros are used to determine if the SLIBXRn or SLIBRn select register should be written to. */
+#define BSP_PRV_INT_B_SELECT_128        ICU.SLIBXR128.BYTE
+#define BSP_PRV_INT_B_SELECT_129        ICU.SLIBXR129.BYTE
+#define BSP_PRV_INT_B_SELECT_130        ICU.SLIBXR130.BYTE
+#define BSP_PRV_INT_B_SELECT_131        ICU.SLIBXR131.BYTE
+#define BSP_PRV_INT_B_SELECT_132        ICU.SLIBXR132.BYTE
+#define BSP_PRV_INT_B_SELECT_133        ICU.SLIBXR133.BYTE
+#define BSP_PRV_INT_B_SELECT_134        ICU.SLIBXR134.BYTE
+#define BSP_PRV_INT_B_SELECT_135        ICU.SLIBXR135.BYTE
+#define BSP_PRV_INT_B_SELECT_136        ICU.SLIBXR136.BYTE
+#define BSP_PRV_INT_B_SELECT_137        ICU.SLIBXR137.BYTE
+#define BSP_PRV_INT_B_SELECT_138        ICU.SLIBXR138.BYTE
+#define BSP_PRV_INT_B_SELECT_139        ICU.SLIBXR139.BYTE
+#define BSP_PRV_INT_B_SELECT_140        ICU.SLIBXR140.BYTE
+#define BSP_PRV_INT_B_SELECT_141        ICU.SLIBXR141.BYTE
+#define BSP_PRV_INT_B_SELECT_142        ICU.SLIBXR142.BYTE
+#define BSP_PRV_INT_B_SELECT_143        ICU.SLIBXR143.BYTE
+#define BSP_PRV_INT_B_SELECT_144        ICU.SLIBR144.BYTE
+#define BSP_PRV_INT_B_SELECT_145        ICU.SLIBR145.BYTE
+#define BSP_PRV_INT_B_SELECT_146        ICU.SLIBR146.BYTE
+#define BSP_PRV_INT_B_SELECT_147        ICU.SLIBR147.BYTE
+#define BSP_PRV_INT_B_SELECT_148        ICU.SLIBR148.BYTE
+#define BSP_PRV_INT_B_SELECT_149        ICU.SLIBR149.BYTE
+#define BSP_PRV_INT_B_SELECT_150        ICU.SLIBR150.BYTE
+#define BSP_PRV_INT_B_SELECT_151        ICU.SLIBR151.BYTE
+#define BSP_PRV_INT_B_SELECT_152        ICU.SLIBR152.BYTE
+#define BSP_PRV_INT_B_SELECT_153        ICU.SLIBR153.BYTE
+#define BSP_PRV_INT_B_SELECT_154        ICU.SLIBR154.BYTE
+#define BSP_PRV_INT_B_SELECT_155        ICU.SLIBR155.BYTE
+#define BSP_PRV_INT_B_SELECT_156        ICU.SLIBR156.BYTE
+#define BSP_PRV_INT_B_SELECT_157        ICU.SLIBR157.BYTE
+#define BSP_PRV_INT_B_SELECT_158        ICU.SLIBR158.BYTE
+#define BSP_PRV_INT_B_SELECT_159        ICU.SLIBR159.BYTE
+#define BSP_PRV_INT_B_SELECT_160        ICU.SLIBR160.BYTE
+#define BSP_PRV_INT_B_SELECT_161        ICU.SLIBR161.BYTE
+#define BSP_PRV_INT_B_SELECT_162        ICU.SLIBR162.BYTE
+#define BSP_PRV_INT_B_SELECT_163        ICU.SLIBR163.BYTE
+#define BSP_PRV_INT_B_SELECT_164        ICU.SLIBR164.BYTE
+#define BSP_PRV_INT_B_SELECT_165        ICU.SLIBR165.BYTE
+#define BSP_PRV_INT_B_SELECT_166        ICU.SLIBR166.BYTE
+#define BSP_PRV_INT_B_SELECT_167        ICU.SLIBR167.BYTE
+#define BSP_PRV_INT_B_SELECT_168        ICU.SLIBR168.BYTE
+#define BSP_PRV_INT_B_SELECT_169        ICU.SLIBR169.BYTE
+#define BSP_PRV_INT_B_SELECT_170        ICU.SLIBR170.BYTE
+#define BSP_PRV_INT_B_SELECT_171        ICU.SLIBR171.BYTE
+#define BSP_PRV_INT_B_SELECT_172        ICU.SLIBR172.BYTE
+#define BSP_PRV_INT_B_SELECT_173        ICU.SLIBR173.BYTE
+#define BSP_PRV_INT_B_SELECT_174        ICU.SLIBR174.BYTE
+#define BSP_PRV_INT_B_SELECT_175        ICU.SLIBR175.BYTE
+#define BSP_PRV_INT_B_SELECT_176        ICU.SLIBR176.BYTE
+#define BSP_PRV_INT_B_SELECT_177        ICU.SLIBR177.BYTE
+#define BSP_PRV_INT_B_SELECT_178        ICU.SLIBR178.BYTE
+#define BSP_PRV_INT_B_SELECT_179        ICU.SLIBR179.BYTE
+#define BSP_PRV_INT_B_SELECT_180        ICU.SLIBR180.BYTE
+#define BSP_PRV_INT_B_SELECT_181        ICU.SLIBR181.BYTE
+#define BSP_PRV_INT_B_SELECT_182        ICU.SLIBR182.BYTE
+#define BSP_PRV_INT_B_SELECT_183        ICU.SLIBR183.BYTE
+#define BSP_PRV_INT_B_SELECT_184        ICU.SLIBR184.BYTE
+#define BSP_PRV_INT_B_SELECT_185        ICU.SLIBR185.BYTE
+#define BSP_PRV_INT_B_SELECT_186        ICU.SLIBR186.BYTE
+#define BSP_PRV_INT_B_SELECT_187        ICU.SLIBR187.BYTE
+#define BSP_PRV_INT_B_SELECT_188        ICU.SLIBR188.BYTE
+#define BSP_PRV_INT_B_SELECT_189        ICU.SLIBR189.BYTE
+#define BSP_PRV_INT_B_SELECT_190        ICU.SLIBR190.BYTE
+#define BSP_PRV_INT_B_SELECT_191        ICU.SLIBR191.BYTE
+#define BSP_PRV_INT_B_SELECT_192        ICU.SLIBR192.BYTE
+#define BSP_PRV_INT_B_SELECT_193        ICU.SLIBR193.BYTE
+#define BSP_PRV_INT_B_SELECT_194        ICU.SLIBR194.BYTE
+#define BSP_PRV_INT_B_SELECT_195        ICU.SLIBR195.BYTE
+#define BSP_PRV_INT_B_SELECT_196        ICU.SLIBR196.BYTE
+#define BSP_PRV_INT_B_SELECT_197        ICU.SLIBR197.BYTE
+#define BSP_PRV_INT_B_SELECT_198        ICU.SLIBR198.BYTE
+#define BSP_PRV_INT_B_SELECT_199        ICU.SLIBR199.BYTE
+#define BSP_PRV_INT_B_SELECT_200        ICU.SLIBR200.BYTE
+#define BSP_PRV_INT_B_SELECT_201        ICU.SLIBR201.BYTE
+#define BSP_PRV_INT_B_SELECT_202        ICU.SLIBR202.BYTE
+#define BSP_PRV_INT_B_SELECT_203        ICU.SLIBR203.BYTE
+#define BSP_PRV_INT_B_SELECT_204        ICU.SLIBR204.BYTE
+#define BSP_PRV_INT_B_SELECT_205        ICU.SLIBR205.BYTE
+#define BSP_PRV_INT_B_SELECT_206        ICU.SLIBR206.BYTE
+#define BSP_PRV_INT_B_SELECT_207        ICU.SLIBR207.BYTE
+/* Interrupt A interrupts are also defined even though there is only 1 select register. */
+#define BSP_PRV_INT_A_SELECT_208        ICU.SLIAR208.BYTE
+#define BSP_PRV_INT_A_SELECT_209        ICU.SLIAR209.BYTE
+#define BSP_PRV_INT_A_SELECT_210        ICU.SLIAR210.BYTE
+#define BSP_PRV_INT_A_SELECT_211        ICU.SLIAR211.BYTE
+#define BSP_PRV_INT_A_SELECT_212        ICU.SLIAR212.BYTE
+#define BSP_PRV_INT_A_SELECT_213        ICU.SLIAR213.BYTE
+#define BSP_PRV_INT_A_SELECT_214        ICU.SLIAR214.BYTE
+#define BSP_PRV_INT_A_SELECT_215        ICU.SLIAR215.BYTE
+#define BSP_PRV_INT_A_SELECT_216        ICU.SLIAR216.BYTE
+#define BSP_PRV_INT_A_SELECT_217        ICU.SLIAR217.BYTE
+#define BSP_PRV_INT_A_SELECT_218        ICU.SLIAR218.BYTE
+#define BSP_PRV_INT_A_SELECT_219        ICU.SLIAR219.BYTE
+#define BSP_PRV_INT_A_SELECT_220        ICU.SLIAR220.BYTE
+#define BSP_PRV_INT_A_SELECT_221        ICU.SLIAR221.BYTE
+#define BSP_PRV_INT_A_SELECT_222        ICU.SLIAR222.BYTE
+#define BSP_PRV_INT_A_SELECT_223        ICU.SLIAR223.BYTE
+#define BSP_PRV_INT_A_SELECT_224        ICU.SLIAR224.BYTE
+#define BSP_PRV_INT_A_SELECT_225        ICU.SLIAR225.BYTE
+#define BSP_PRV_INT_A_SELECT_226        ICU.SLIAR226.BYTE
+#define BSP_PRV_INT_A_SELECT_227        ICU.SLIAR227.BYTE
+#define BSP_PRV_INT_A_SELECT_228        ICU.SLIAR228.BYTE
+#define BSP_PRV_INT_A_SELECT_229        ICU.SLIAR229.BYTE
+#define BSP_PRV_INT_A_SELECT_230        ICU.SLIAR230.BYTE
+#define BSP_PRV_INT_A_SELECT_231        ICU.SLIAR231.BYTE
+#define BSP_PRV_INT_A_SELECT_232        ICU.SLIAR232.BYTE
+#define BSP_PRV_INT_A_SELECT_233        ICU.SLIAR233.BYTE
+#define BSP_PRV_INT_A_SELECT_234        ICU.SLIAR234.BYTE
+#define BSP_PRV_INT_A_SELECT_235        ICU.SLIAR235.BYTE
+#define BSP_PRV_INT_A_SELECT_236        ICU.SLIAR236.BYTE
+#define BSP_PRV_INT_A_SELECT_237        ICU.SLIAR237.BYTE
+#define BSP_PRV_INT_A_SELECT_238        ICU.SLIAR238.BYTE
+#define BSP_PRV_INT_A_SELECT_239        ICU.SLIAR239.BYTE
+#define BSP_PRV_INT_A_SELECT_240        ICU.SLIAR240.BYTE
+#define BSP_PRV_INT_A_SELECT_241        ICU.SLIAR241.BYTE
+#define BSP_PRV_INT_A_SELECT_242        ICU.SLIAR242.BYTE
+#define BSP_PRV_INT_A_SELECT_243        ICU.SLIAR243.BYTE
+#define BSP_PRV_INT_A_SELECT_244        ICU.SLIAR244.BYTE
+#define BSP_PRV_INT_A_SELECT_245        ICU.SLIAR245.BYTE
+#define BSP_PRV_INT_A_SELECT_246        ICU.SLIAR246.BYTE
+#define BSP_PRV_INT_A_SELECT_247        ICU.SLIAR247.BYTE
+#define BSP_PRV_INT_A_SELECT_248        ICU.SLIAR248.BYTE
+#define BSP_PRV_INT_A_SELECT_249        ICU.SLIAR249.BYTE
+#define BSP_PRV_INT_A_SELECT_250        ICU.SLIAR250.BYTE
+#define BSP_PRV_INT_A_SELECT_251        ICU.SLIAR251.BYTE
+#define BSP_PRV_INT_A_SELECT_252        ICU.SLIAR252.BYTE
+#define BSP_PRV_INT_A_SELECT_253        ICU.SLIAR253.BYTE
+#define BSP_PRV_INT_A_SELECT_254        ICU.SLIAR254.BYTE
+#define BSP_PRV_INT_A_SELECT_255        ICU.SLIAR255.BYTE
+
+/* Start and end of Interrupt B and A vectors. */
+#define BSP_PRV_B_INT_VECTOR_START           (128)
+#define BSP_PRV_B_INT_VECTOR_END             (207)
+#define BSP_PRV_A_INT_VECTOR_START           (208)
+#define BSP_PRV_A_INT_VECTOR_END             (255)
+
+/* Start and end of Interrupt B select registers. */
+#define BSP_PRV_SLIBXR_START                 (128)
+#define BSP_PRV_SLIBXR_END                   (143)
+#define BSP_PRV_SLIBR_START                  (144)
+#define BSP_PRV_SLIBR_END                    (207)
+
+/* Starting IER register for mapped interrupts. This is used for calculating the IER register based on the
+ * given vector number.
+ */
+#define BSP_PRV_MAP_INT_IER_START            (0x10)
+
+/* These are used in function-like macros to expand to letters. */
+#define BSP_PRV_A   A
+#define BSP_PRV_B   B
+
+/* Test to see if chosen vector is valid for a mapped interrupt. */
+#define BSP_PRV_VALID_MAP_INT(x, y)          (((y + 0) >= BSP_PRV_ ## x ## _INT_VECTOR_START) && \
+                                              ((y + 0) <= BSP_PRV_ ## x ## _INT_VECTOR_END))
+
+/* Calculation for getting IER register. */
+#define BSP_PRIV_CALC_IER_REG(x)             (((x - BSP_PRV_B_INT_VECTOR_START)/8) + BSP_PRV_MAP_INT_IER_START)
+
+/* These macros generate the macros needed to use the function-like macros from iodefine.h */
+#define BSP_PRV_IR(x, y)       _BSP_PRV_IR(x, y)
+#define _BSP_PRV_IR(x, y)      IR_PERI ## x ## _INT ## x ## y
+#define BSP_PRV_DTCE(x, y)     _BSP_PRV_DTCE(x, y)
+#define _BSP_PRV_DTCE(x, y)    DTCE_PERI ## x ## _INT ## x ## y
+#define BSP_PRV_IPR(x, y)      _BSP_PRV_IPR(x, y)
+#define _BSP_PRV_IPR(x, y)     IPR_PERI ## x ## _INT ## x ## y
+#define BSP_PRV_VECT(x, y)     _BSP_PRV_VECT(x, y)
+#define _BSP_PRV_VECT(x, y)    VECT_PERI ## x ## _INT ## x ## y
+
+#define BSP_PRV_IEN(x)         _BSP_PRV_IEN(x)
+#define _BSP_PRV_IEN(x)        __BSP_PRV_IEN(BSP_PRV_CALC_ ## x ## _MOD_8)
+#define __BSP_PRV_IEN(x)       ___BSP_PRV_IEN(x)
+#define ___BSP_PRV_IEN(x)      IEN ## x
+
+/* Chooses the correct interrupt select register. */
+#define BSP_PRV_INT_SELECT(x, y)         _BSP_PRV_INT_SELECT(x, y)
+#define _BSP_PRV_INT_SELECT(x, y)        BSP_PRV_INT_ ## x ## _SELECT_ ## y
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+
+#endif /* MCU_MAPPED_INTERRUPTS_PRIVATE_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/r_bsp_cpu.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/r_bsp_cpu.h
new file mode 100644
index 00000000..03a0abe7
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/r_bsp_cpu.h
@@ -0,0 +1,90 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_cpu.h
+* Description  : This module implements CPU specific functions. An example is enabling/disabling interrupts.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 01.10.2016 1.00     First Release
+*         : 15.05.2017 2.00     Changed comments of the following enumeration.
+*                               - bsp_reg_protect_t
+*         : 28.02.2019 3.00     Added bsp_ram_initialize function.
+*                               Fixed coding style.
+*         : 26.07.2019 3.01     Added R_BSP_SoftwareReset function.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef CPU_H
+#define CPU_H
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+/* The different types of registers that can be protected. */
+typedef enum
+{
+    /* PRC0
+       Enables writing to the registers related to the clock generation circuit: SCKCR, SCKCR2, SCKCR3, PLLCR,
+       PLLCR2, BCKCR, MOSCCR, SOSCCR, LOCOCR, ILOCOCR, HOCOCR, HOCOCR2, OSTDCR, OSTDSR. */
+    BSP_REG_PROTECT_CGC = 0,
+
+    /* PRC1
+       Enables writing to the registers related to operating modes, low power consumption, the clock generation circuit,
+       and software reset: SYSCR0, SYSCR1, SBYCR, MSTPCRA, MSTPCRB, MSTPCRC, MSTPCRD, OPCCR, RSTCKCR,
+       DPSBYCR, DPSIER0, DPSIER1, DPSIER2, DPSIER3, DPSIFR0, DPSIFR1, DPSIFR2, DPSIFR3,
+       DPSIEGR0, DPSIEGR1, DPSIEGR2, DPSIEGR3, MOSCWTCR, SOSCWTCR, MOFCR, HOCOPCR, SWRR. */
+    BSP_REG_PROTECT_LPC_CGC_SWR,
+
+    /* PRC3
+       Enables writing to the registers related to the LVD:LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0,
+       LVD2CR1, LVD2SR. */
+    BSP_REG_PROTECT_LVD,
+
+    /* MPC.PWPR
+       Enables writing to MPC's PFS registers. */
+    BSP_REG_PROTECT_MPC,
+
+    /* This entry is used for getting the number of enum items. This must be the last entry. DO NOT REMOVE THIS ENTRY!*/
+    BSP_REG_PROTECT_TOTAL_ITEMS
+} bsp_reg_protect_t;
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+void     R_BSP_InterruptsDisable(void);
+void     R_BSP_InterruptsEnable(void);
+uint32_t R_BSP_CpuInterruptLevelRead(void);
+bool     R_BSP_CpuInterruptLevelWrite(uint32_t level);
+void     R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect);
+void     R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect);
+void     R_BSP_SoftwareReset(void);
+
+void     bsp_register_protect_open(void); //r_bsp internal function. DO NOT CALL.
+void     bsp_ram_initialize(void);
+
+#endif /* CPU_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/r_bsp_locking.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/r_bsp_locking.h
new file mode 100644
index 00000000..a7ef2a5b
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/r_bsp_locking.h
@@ -0,0 +1,68 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_locking.h
+* Description  : This implements a locking mechanism that can be used by all code. The locking is done atomically so
+*                common resources can be accessed safely.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 01.10.2016 1.00     First Release
+*         : 28.02.2019 1.01     Fixed coding style.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* Lock types. */
+#include "mcu_locks.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef LOCKING_H
+#define LOCKING_H
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+bool R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * const plock);
+bool R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * const plock);
+bool R_BSP_HardwareLock(mcu_lock_t const hw_index);
+bool R_BSP_HardwareUnlock(mcu_lock_t const hw_index);
+
+#if BSP_CFG_USER_LOCKING_ENABLED != 0
+/* Is user is using their own lock functions then these are the prototypes. */
+bool BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock);
+bool BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock);
+bool BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t const hw_index);
+bool BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t const hw_index);
+#endif
+
+#endif /* LOCKING_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/register_access/gnuc/iodefine.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/register_access/gnuc/iodefine.h
new file mode 100644
index 00000000..92b12cf5
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/register_access/gnuc/iodefine.h
@@ -0,0 +1,30815 @@
+                                                                          
+                                                                           
+                                                                           
+                                                                           
+                                                                           
+                                                                           
+                                                                           
+                                                                           
+                                                                           
+                                                                           
+                                                                           
+                                                                           
+                                                                           
+                                                                          
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/*******************************************************************************
+*
+* Device     : RX/RX600/RX65N
+*
+* File Name  : iodefine.h
+*
+* Abstract   : Definition of I/O Register.
+*
+* History    : V0.5B  (2015-11-25)  [Hardware Manual Revision : 0.50]
+*            : V0.5C  (2015-12-04)  [Hardware Manual Revision : 0.50]
+*            : V0.5D  (2015-12-29)  [Hardware Manual Revision : 0.50]
+*            : V0.8   (2016-04-19)  [Hardware Manual Revision : 0.80]
+*            : V0.8A  (2016-06-03)  [Hardware Manual Revision : 0.80]
+*            : V0.8B  (2016-06-16)  [Hardware Manual Revision : 0.80]
+*            : V1.0   (2016-06-20)  [Hardware Manual Revision : 1.00]
+*            : V1.0A  (2016-08-03)  [Hardware Manual Revision : 1.00]
+*            : V1.5   (2016-11-07)  [Hardware Manual Revision : 1.00]
+*            : V1.5A  (2016-12-15)  [Hardware Manual Revision : 1.00]
+*            : V1.5B  (2017-03-22)  [Hardware Manual Revision : 1.00]
+*            : V2.0   (2017-04-21)  [Hardware Manual Revision : 2.00]
+*            : V2.0A  (2017-10-23)  [Hardware Manual Revision : 2.00]
+*            : V2.2   (2018-10-26)  [Hardware Manual Revision : 2.10]
+*            : V2.30  (2019-07-26)  [Hardware Manual Revision : 2.30]
+*
+* NOTE       : THIS IS A TYPICAL EXAMPLE.
+*
+*  Copyright(c) 2019 Renesas Electronics Corporation.
+*
+*********************************************************************************/
+/********************************************************************************/
+/*                                                                              */
+/*  DESCRIPTION : Definition of ICU Register                                    */
+/*  CPU TYPE    : RX65N                                                         */
+/*                                                                              */
+/*  Usage : IR,DTCER,IER,IPR of ICU Register                                    */
+/*     The following IR, DTCE, IEN, IPR macro functions simplify usage.         */
+/*     The bit access operation is "Bit_Name(interrupt source,name)".           */
+/*     A part of the name can be omitted.                                       */
+/*     for example :                                                            */
+/*       IR(BSC,BUSERR) = 0;     expands to :                                   */
+/*         ICU.IR[16].BIT.IR = 0;                                               */
+/*                                                                              */
+/*       DTCE(ICU,IRQ0) = 1;     expands to :                                   */
+/*         ICU.DTCER[64].BIT.DTCE = 1;                                          */
+/*                                                                              */
+/*       IEN(CMT0,CMI0) = 1;     expands to :                                   */
+/*         ICU.IER[0x03].BIT.IEN4 = 1;                                          */
+/*                                                                              */
+/*       IPR(ICU,SWINT2) = 2;    expands to :                                   */
+/*       IPR(ICU,SWI   ) = 2;    // SWINT2,SWINT share IPR level.               */
+/*         ICU.IPR[3].BIT.IPR = 2;                                              */
+/*                                                                              */
+/*  Usage : #pragma interrupt Function_Identifier(vect=**)                      */
+/*     The number of vector is "(interrupt source, name)".                      */
+/*     for example :                                                            */
+/*       #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0))          expands to :  */
+/*         #pragma interrupt INT_IRQ0(vect=64)                                  */
+/*       #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0))    expands to :  */
+/*         #pragma interrupt INT_CMT0_CMI0(vect=28)                             */
+/*                                                                              */
+/*  Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register                          */
+/*     The bit access operation is "MSTP(name)".                                */
+/*     The name that can be used is a macro name defined with "iodefine.h".     */
+/*     for example :                                                            */
+/*       MSTP(TMR2) = 0;    // TMR2,TMR3,TMR23                    expands to :  */
+/*         SYSTEM.MSTPCRA.BIT.MSTPA4  = 0;                                      */
+/*       MSTP(SCI0) = 0;    // SCI0,SMCI0                         expands to :  */
+/*         SYSTEM.MSTPCRB.BIT.MSTPB31 = 0;                                      */
+/*       MSTP(MTU4) = 0;    // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,...   expands to :  */
+/*         SYSTEM.MSTPCRA.BIT.MSTPA9  = 0;                                      */
+/*       MSTP(TPU4) = 0;    // TPU0,TPU1,TPU2,TPU3,TPU4,TPU5,TPUA expands to :  */
+/*         SYSTEM.MSTPCRA.BIT.MSTPA13 = 0;                                      */
+/*       MSTP(CMT3) = 0;    // CMT2,CMT3                          expands to :  */
+/*         SYSTEM.MSTPCRA.BIT.MSTPA14 = 0;                                      */
+/*                                                                              */
+/*                                                                              */
+/********************************************************************************/
+#ifndef __RX65NIODEFINE_HEADER__
+#define __RX65NIODEFINE_HEADER__
+
+#define	IEN_BSC_BUSERR		IEN0
+#define	IEN_RAM_RAMERR		IEN2
+#define	IEN_FCU_FIFERR		IEN5
+#define	IEN_FCU_FRDYI		IEN7
+#define	IEN_ICU_SWINT2		IEN2
+#define	IEN_ICU_SWINT		IEN3
+#define	IEN_CMT0_CMI0		IEN4
+#define	IEN_CMT1_CMI1		IEN5
+#define	IEN_CMTW0_CMWI0		IEN6
+#define	IEN_CMTW1_CMWI1		IEN7
+#define	IEN_USB0_D0FIFO0	IEN2
+#define	IEN_USB0_D1FIFO0	IEN3
+#define	IEN_RSPI0_SPRI0		IEN6
+#define	IEN_RSPI0_SPTI0		IEN7
+#define	IEN_RSPI1_SPRI1		IEN0
+#define	IEN_RSPI1_SPTI1		IEN1
+#define	IEN_QSPI_SPRI		IEN2
+#define	IEN_QSPI_SPTI		IEN3
+#define	IEN_SDHI_SBFAI		IEN4
+#define	IEN_MMCIF_MBFAI		IEN5
+#define	IEN_RIIC1_RXI1		IEN2
+#define	IEN_RIIC1_TXI1		IEN3
+#define	IEN_RIIC0_RXI0		IEN4
+#define	IEN_RIIC0_TXI0		IEN5
+#define	IEN_RIIC2_RXI2		IEN6
+#define	IEN_RIIC2_TXI2		IEN7
+#define	IEN_SCI0_RXI0		IEN2
+#define	IEN_SCI0_TXI0		IEN3
+#define	IEN_SCI1_RXI1		IEN4
+#define	IEN_SCI1_TXI1		IEN5
+#define	IEN_SCI2_RXI2		IEN6
+#define	IEN_SCI2_TXI2		IEN7
+#define	IEN_ICU_IRQ0		IEN0
+#define	IEN_ICU_IRQ1		IEN1
+#define	IEN_ICU_IRQ2		IEN2
+#define	IEN_ICU_IRQ3		IEN3
+#define	IEN_ICU_IRQ4		IEN4
+#define	IEN_ICU_IRQ5		IEN5
+#define	IEN_ICU_IRQ6		IEN6
+#define	IEN_ICU_IRQ7		IEN7
+#define	IEN_ICU_IRQ8		IEN0
+#define	IEN_ICU_IRQ9		IEN1
+#define	IEN_ICU_IRQ10		IEN2
+#define	IEN_ICU_IRQ11		IEN3
+#define	IEN_ICU_IRQ12		IEN4
+#define	IEN_ICU_IRQ13		IEN5
+#define	IEN_ICU_IRQ14		IEN6
+#define	IEN_ICU_IRQ15		IEN7
+#define	IEN_SCI3_RXI3		IEN0
+#define	IEN_SCI3_TXI3		IEN1
+#define	IEN_SCI4_RXI4		IEN2
+#define	IEN_SCI4_TXI4		IEN3
+#define	IEN_SCI5_RXI5		IEN4
+#define	IEN_SCI5_TXI5		IEN5
+#define	IEN_SCI6_RXI6		IEN6
+#define	IEN_SCI6_TXI6		IEN7
+#define	IEN_LVD1_LVD1		IEN0
+#define	IEN_LVD2_LVD2		IEN1
+#define	IEN_USB0_USBR0		IEN2
+#define	IEN_RTC_ALM			IEN4
+#define	IEN_RTC_PRD			IEN5
+#define	IEN_IWDT_IWUNI		IEN7
+#define	IEN_WDT_WUNI		IEN0
+#define	IEN_PDC_PCDFI		IEN1
+#define	IEN_SCI7_RXI7		IEN2
+#define	IEN_SCI7_TXI7		IEN3
+#define	IEN_SCI8_RXI8		IEN4
+#define	IEN_SCI8_TXI8		IEN5
+#define	IEN_SCI9_RXI9		IEN6
+#define	IEN_SCI9_TXI9		IEN7
+#define	IEN_SCI10_RXI10		IEN0
+#define	IEN_SCI10_TXI10		IEN1
+#define	IEN_ICU_GROUPBE0	IEN2
+#define	IEN_ICU_GROUPBL2	IEN3
+#define	IEN_RSPI2_SPRI2		IEN4
+#define	IEN_RSPI2_SPTI2		IEN5
+#define	IEN_ICU_GROUPBL0	IEN6
+#define	IEN_ICU_GROUPBL1	IEN7
+#define	IEN_ICU_GROUPAL0	IEN0
+#define	IEN_ICU_GROUPAL1	IEN1
+#define	IEN_SCI11_RXI11		IEN2
+#define	IEN_SCI11_TXI11		IEN3
+#define	IEN_SCI12_RXI12		IEN4
+#define	IEN_SCI12_TXI12		IEN5
+#define	IEN_DMAC_DMAC0I		IEN0
+#define	IEN_DMAC_DMAC1I		IEN1
+#define	IEN_DMAC_DMAC2I		IEN2
+#define	IEN_DMAC_DMAC3I		IEN3
+#define	IEN_DMAC_DMAC74I	IEN4
+#define	IEN_OST_OSTDI		IEN5
+#define	IEN_EXDMAC_EXDMAC0I	IEN6
+#define	IEN_EXDMAC_EXDMAC1I	IEN7
+#define	IEN_PERIB_INTB128	IEN0
+#define	IEN_PERIB_INTB129	IEN1
+#define	IEN_PERIB_INTB130	IEN2
+#define	IEN_PERIB_INTB131	IEN3
+#define	IEN_PERIB_INTB132	IEN4
+#define	IEN_PERIB_INTB133	IEN5
+#define	IEN_PERIB_INTB134	IEN6
+#define	IEN_PERIB_INTB135	IEN7
+#define	IEN_PERIB_INTB136	IEN0
+#define	IEN_PERIB_INTB137	IEN1
+#define	IEN_PERIB_INTB138	IEN2
+#define	IEN_PERIB_INTB139	IEN3
+#define	IEN_PERIB_INTB140	IEN4
+#define	IEN_PERIB_INTB141	IEN5
+#define	IEN_PERIB_INTB142	IEN6
+#define	IEN_PERIB_INTB143	IEN7
+#define	IEN_PERIB_INTB144	IEN0
+#define	IEN_PERIB_INTB145	IEN1
+#define	IEN_PERIB_INTB146	IEN2
+#define	IEN_PERIB_INTB147	IEN3
+#define	IEN_PERIB_INTB148	IEN4
+#define	IEN_PERIB_INTB149	IEN5
+#define	IEN_PERIB_INTB150	IEN6
+#define	IEN_PERIB_INTB151	IEN7
+#define	IEN_PERIB_INTB152	IEN0
+#define	IEN_PERIB_INTB153	IEN1
+#define	IEN_PERIB_INTB154	IEN2
+#define	IEN_PERIB_INTB155	IEN3
+#define	IEN_PERIB_INTB156	IEN4
+#define	IEN_PERIB_INTB157	IEN5
+#define	IEN_PERIB_INTB158	IEN6
+#define	IEN_PERIB_INTB159	IEN7
+#define	IEN_PERIB_INTB160	IEN0
+#define	IEN_PERIB_INTB161	IEN1
+#define	IEN_PERIB_INTB162	IEN2
+#define	IEN_PERIB_INTB163	IEN3
+#define	IEN_PERIB_INTB164	IEN4
+#define	IEN_PERIB_INTB165	IEN5
+#define	IEN_PERIB_INTB166	IEN6
+#define	IEN_PERIB_INTB167	IEN7
+#define	IEN_PERIB_INTB168	IEN0
+#define	IEN_PERIB_INTB169	IEN1
+#define	IEN_PERIB_INTB170	IEN2
+#define	IEN_PERIB_INTB171	IEN3
+#define	IEN_PERIB_INTB172	IEN4
+#define	IEN_PERIB_INTB173	IEN5
+#define	IEN_PERIB_INTB174	IEN6
+#define	IEN_PERIB_INTB175	IEN7
+#define	IEN_PERIB_INTB176	IEN0
+#define	IEN_PERIB_INTB177	IEN1
+#define	IEN_PERIB_INTB178	IEN2
+#define	IEN_PERIB_INTB179	IEN3
+#define	IEN_PERIB_INTB180	IEN4
+#define	IEN_PERIB_INTB181	IEN5
+#define	IEN_PERIB_INTB182	IEN6
+#define	IEN_PERIB_INTB183	IEN7
+#define	IEN_PERIB_INTB184	IEN0
+#define	IEN_PERIB_INTB185	IEN1
+#define	IEN_PERIB_INTB186	IEN2
+#define	IEN_PERIB_INTB187	IEN3
+#define	IEN_PERIB_INTB188	IEN4
+#define	IEN_PERIB_INTB189	IEN5
+#define	IEN_PERIB_INTB190	IEN6
+#define	IEN_PERIB_INTB191	IEN7
+#define	IEN_PERIB_INTB192	IEN0
+#define	IEN_PERIB_INTB193	IEN1
+#define	IEN_PERIB_INTB194	IEN2
+#define	IEN_PERIB_INTB195	IEN3
+#define	IEN_PERIB_INTB196	IEN4
+#define	IEN_PERIB_INTB197	IEN5
+#define	IEN_PERIB_INTB198	IEN6
+#define	IEN_PERIB_INTB199	IEN7
+#define	IEN_PERIB_INTB200	IEN0
+#define	IEN_PERIB_INTB201	IEN1
+#define	IEN_PERIB_INTB202	IEN2
+#define	IEN_PERIB_INTB203	IEN3
+#define	IEN_PERIB_INTB204	IEN4
+#define	IEN_PERIB_INTB205	IEN5
+#define	IEN_PERIB_INTB206	IEN6
+#define	IEN_PERIB_INTB207	IEN7
+#define	IEN_PERIA_INTA208	IEN0
+#define	IEN_PERIA_INTA209	IEN1
+#define	IEN_PERIA_INTA210	IEN2
+#define	IEN_PERIA_INTA211	IEN3
+#define	IEN_PERIA_INTA212	IEN4
+#define	IEN_PERIA_INTA213	IEN5
+#define	IEN_PERIA_INTA214	IEN6
+#define	IEN_PERIA_INTA215	IEN7
+#define	IEN_PERIA_INTA216	IEN0
+#define	IEN_PERIA_INTA217	IEN1
+#define	IEN_PERIA_INTA218	IEN2
+#define	IEN_PERIA_INTA219	IEN3
+#define	IEN_PERIA_INTA220	IEN4
+#define	IEN_PERIA_INTA221	IEN5
+#define	IEN_PERIA_INTA222	IEN6
+#define	IEN_PERIA_INTA223	IEN7
+#define	IEN_PERIA_INTA224	IEN0
+#define	IEN_PERIA_INTA225	IEN1
+#define	IEN_PERIA_INTA226	IEN2
+#define	IEN_PERIA_INTA227	IEN3
+#define	IEN_PERIA_INTA228	IEN4
+#define	IEN_PERIA_INTA229	IEN5
+#define	IEN_PERIA_INTA230	IEN6
+#define	IEN_PERIA_INTA231	IEN7
+#define	IEN_PERIA_INTA232	IEN0
+#define	IEN_PERIA_INTA233	IEN1
+#define	IEN_PERIA_INTA234	IEN2
+#define	IEN_PERIA_INTA235	IEN3
+#define	IEN_PERIA_INTA236	IEN4
+#define	IEN_PERIA_INTA237	IEN5
+#define	IEN_PERIA_INTA238	IEN6
+#define	IEN_PERIA_INTA239	IEN7
+#define	IEN_PERIA_INTA240	IEN0
+#define	IEN_PERIA_INTA241	IEN1
+#define	IEN_PERIA_INTA242	IEN2
+#define	IEN_PERIA_INTA243	IEN3
+#define	IEN_PERIA_INTA244	IEN4
+#define	IEN_PERIA_INTA245	IEN5
+#define	IEN_PERIA_INTA246	IEN6
+#define	IEN_PERIA_INTA247	IEN7
+#define	IEN_PERIA_INTA248	IEN0
+#define	IEN_PERIA_INTA249	IEN1
+#define	IEN_PERIA_INTA250	IEN2
+#define	IEN_PERIA_INTA251	IEN3
+#define	IEN_PERIA_INTA252	IEN4
+#define	IEN_PERIA_INTA253	IEN5
+#define	IEN_PERIA_INTA254	IEN6
+#define	IEN_PERIA_INTA255	IEN7
+
+#define	VECT_BSC_BUSERR		16
+#define	VECT_RAM_RAMERR		18
+#define	VECT_FCU_FIFERR		21
+#define	VECT_FCU_FRDYI		23
+#define	VECT_ICU_SWINT2		26
+#define	VECT_ICU_SWINT		27
+#define	VECT_CMT0_CMI0		28
+#define	VECT_CMT1_CMI1		29
+#define	VECT_CMTW0_CMWI0	30
+#define	VECT_CMTW1_CMWI1	31
+#define	VECT_USB0_D0FIFO0	34
+#define	VECT_USB0_D1FIFO0	35
+#define	VECT_RSPI0_SPRI0	38
+#define	VECT_RSPI0_SPTI0	39
+#define	VECT_RSPI1_SPRI1	40
+#define	VECT_RSPI1_SPTI1	41
+#define	VECT_QSPI_SPRI		42
+#define	VECT_QSPI_SPTI		43
+#define	VECT_SDHI_SBFAI		44
+#define	VECT_MMCIF_MBFAI	45
+#define	VECT_RIIC1_RXI1		50
+#define	VECT_RIIC1_TXI1		51
+#define	VECT_RIIC0_RXI0		52
+#define	VECT_RIIC0_TXI0		53
+#define	VECT_RIIC2_RXI2		54
+#define	VECT_RIIC2_TXI2		55
+#define	VECT_SCI0_RXI0		58
+#define	VECT_SCI0_TXI0		59
+#define	VECT_SCI1_RXI1		60
+#define	VECT_SCI1_TXI1		61
+#define	VECT_SCI2_RXI2		62
+#define	VECT_SCI2_TXI2		63
+#define	VECT_ICU_IRQ0		64
+#define	VECT_ICU_IRQ1		65
+#define	VECT_ICU_IRQ2		66
+#define	VECT_ICU_IRQ3		67
+#define	VECT_ICU_IRQ4		68
+#define	VECT_ICU_IRQ5		69
+#define	VECT_ICU_IRQ6		70
+#define	VECT_ICU_IRQ7		71
+#define	VECT_ICU_IRQ8		72
+#define	VECT_ICU_IRQ9		73
+#define	VECT_ICU_IRQ10		74
+#define	VECT_ICU_IRQ11		75
+#define	VECT_ICU_IRQ12		76
+#define	VECT_ICU_IRQ13		77
+#define	VECT_ICU_IRQ14		78
+#define	VECT_ICU_IRQ15		79
+#define	VECT_SCI3_RXI3		80
+#define	VECT_SCI3_TXI3		81
+#define	VECT_SCI4_RXI4		82
+#define	VECT_SCI4_TXI4		83
+#define	VECT_SCI5_RXI5		84
+#define	VECT_SCI5_TXI5		85
+#define	VECT_SCI6_RXI6		86
+#define	VECT_SCI6_TXI6		87
+#define	VECT_LVD1_LVD1		88
+#define	VECT_LVD2_LVD2		89
+#define	VECT_USB0_USBR0		90
+#define	VECT_RTC_ALM		92
+#define	VECT_RTC_PRD		93
+#define	VECT_IWDT_IWUNI		95
+#define	VECT_WDT_WUNI		96
+#define	VECT_PDC_PCDFI		97
+#define	VECT_SCI7_RXI7		98
+#define	VECT_SCI7_TXI7		99
+#define	VECT_SCI8_RXI8		100
+#define	VECT_SCI8_TXI8		101
+#define	VECT_SCI9_RXI9		102
+#define	VECT_SCI9_TXI9		103
+#define	VECT_SCI10_RXI10	104
+#define	VECT_SCI10_TXI10	105
+#define	VECT_ICU_GROUPBE0	106
+#define	VECT_ICU_GROUPBL2	107
+#define	VECT_RSPI2_SPRI2	108
+#define	VECT_RSPI2_SPTI2	109
+#define	VECT_ICU_GROUPBL0	110
+#define	VECT_ICU_GROUPBL1	111
+#define	VECT_ICU_GROUPAL0	112
+#define	VECT_ICU_GROUPAL1	113
+#define	VECT_SCI11_RXI11	114
+#define	VECT_SCI11_TXI11	115
+#define	VECT_SCI12_RXI12	116
+#define	VECT_SCI12_TXI12	117
+#define	VECT_DMAC_DMAC0I	120
+#define	VECT_DMAC_DMAC1I	121
+#define	VECT_DMAC_DMAC2I	122
+#define	VECT_DMAC_DMAC3I	123
+#define	VECT_DMAC_DMAC74I	124
+#define	VECT_OST_OSTDI		125
+#define	VECT_EXDMAC_EXDMAC0I	126
+#define	VECT_EXDMAC_EXDMAC1I	127
+#define	VECT_PERIB_INTB128	128
+#define	VECT_PERIB_INTB129	129
+#define	VECT_PERIB_INTB130	130
+#define	VECT_PERIB_INTB131	131
+#define	VECT_PERIB_INTB132	132
+#define	VECT_PERIB_INTB133	133
+#define	VECT_PERIB_INTB134	134
+#define	VECT_PERIB_INTB135	135
+#define	VECT_PERIB_INTB136	136
+#define	VECT_PERIB_INTB137	137
+#define	VECT_PERIB_INTB138	138
+#define	VECT_PERIB_INTB139	139
+#define	VECT_PERIB_INTB140	140
+#define	VECT_PERIB_INTB141	141
+#define	VECT_PERIB_INTB142	142
+#define	VECT_PERIB_INTB143	143
+#define	VECT_PERIB_INTB144	144
+#define	VECT_PERIB_INTB145	145
+#define	VECT_PERIB_INTB146	146
+#define	VECT_PERIB_INTB147	147
+#define	VECT_PERIB_INTB148	148
+#define	VECT_PERIB_INTB149	149
+#define	VECT_PERIB_INTB150	150
+#define	VECT_PERIB_INTB151	151
+#define	VECT_PERIB_INTB152	152
+#define	VECT_PERIB_INTB153	153
+#define	VECT_PERIB_INTB154	154
+#define	VECT_PERIB_INTB155	155
+#define	VECT_PERIB_INTB156	156
+#define	VECT_PERIB_INTB157	157
+#define	VECT_PERIB_INTB158	158
+#define	VECT_PERIB_INTB159	159
+#define	VECT_PERIB_INTB160	160
+#define	VECT_PERIB_INTB161	161
+#define	VECT_PERIB_INTB162	162
+#define	VECT_PERIB_INTB163	163
+#define	VECT_PERIB_INTB164	164
+#define	VECT_PERIB_INTB165	165
+#define	VECT_PERIB_INTB166	166
+#define	VECT_PERIB_INTB167	167
+#define	VECT_PERIB_INTB168	168
+#define	VECT_PERIB_INTB169	169
+#define	VECT_PERIB_INTB170	170
+#define	VECT_PERIB_INTB171	171
+#define	VECT_PERIB_INTB172	172
+#define	VECT_PERIB_INTB173	173
+#define	VECT_PERIB_INTB174	174
+#define	VECT_PERIB_INTB175	175
+#define	VECT_PERIB_INTB176	176
+#define	VECT_PERIB_INTB177	177
+#define	VECT_PERIB_INTB178	178
+#define	VECT_PERIB_INTB179	179
+#define	VECT_PERIB_INTB180	180
+#define	VECT_PERIB_INTB181	181
+#define	VECT_PERIB_INTB182	182
+#define	VECT_PERIB_INTB183	183
+#define	VECT_PERIB_INTB184	184
+#define	VECT_PERIB_INTB185	185
+#define	VECT_PERIB_INTB186	186
+#define	VECT_PERIB_INTB187	187
+#define	VECT_PERIB_INTB188	188
+#define	VECT_PERIB_INTB189	189
+#define	VECT_PERIB_INTB190	190
+#define	VECT_PERIB_INTB191	191
+#define	VECT_PERIB_INTB192	192
+#define	VECT_PERIB_INTB193	193
+#define	VECT_PERIB_INTB194	194
+#define	VECT_PERIB_INTB195	195
+#define	VECT_PERIB_INTB196	196
+#define	VECT_PERIB_INTB197	197
+#define	VECT_PERIB_INTB198	198
+#define	VECT_PERIB_INTB199	199
+#define	VECT_PERIB_INTB200	200
+#define	VECT_PERIB_INTB201	201
+#define	VECT_PERIB_INTB202	202
+#define	VECT_PERIB_INTB203	203
+#define	VECT_PERIB_INTB204	204
+#define	VECT_PERIB_INTB205	205
+#define	VECT_PERIB_INTB206	206
+#define	VECT_PERIB_INTB207	207
+#define	VECT_PERIA_INTA208	208
+#define	VECT_PERIA_INTA209	209
+#define	VECT_PERIA_INTA210	210
+#define	VECT_PERIA_INTA211	211
+#define	VECT_PERIA_INTA212	212
+#define	VECT_PERIA_INTA213	213
+#define	VECT_PERIA_INTA214	214
+#define	VECT_PERIA_INTA215	215
+#define	VECT_PERIA_INTA216	216
+#define	VECT_PERIA_INTA217	217
+#define	VECT_PERIA_INTA218	218
+#define	VECT_PERIA_INTA219	219
+#define	VECT_PERIA_INTA220	220
+#define	VECT_PERIA_INTA221	221
+#define	VECT_PERIA_INTA222	222
+#define	VECT_PERIA_INTA223	223
+#define	VECT_PERIA_INTA224	224
+#define	VECT_PERIA_INTA225	225
+#define	VECT_PERIA_INTA226	226
+#define	VECT_PERIA_INTA227	227
+#define	VECT_PERIA_INTA228	228
+#define	VECT_PERIA_INTA229	229
+#define	VECT_PERIA_INTA230	230
+#define	VECT_PERIA_INTA231	231
+#define	VECT_PERIA_INTA232	232
+#define	VECT_PERIA_INTA233	233
+#define	VECT_PERIA_INTA234	234
+#define	VECT_PERIA_INTA235	235
+#define	VECT_PERIA_INTA236	236
+#define	VECT_PERIA_INTA237	237
+#define	VECT_PERIA_INTA238	238
+#define	VECT_PERIA_INTA239	239
+#define	VECT_PERIA_INTA240	240
+#define	VECT_PERIA_INTA241	241
+#define	VECT_PERIA_INTA242	242
+#define	VECT_PERIA_INTA243	243
+#define	VECT_PERIA_INTA244	244
+#define	VECT_PERIA_INTA245	245
+#define	VECT_PERIA_INTA246	246
+#define	VECT_PERIA_INTA247	247
+#define	VECT_PERIA_INTA248	248
+#define	VECT_PERIA_INTA249	249
+#define	VECT_PERIA_INTA250	250
+#define	VECT_PERIA_INTA251	251
+#define	VECT_PERIA_INTA252	252
+#define	VECT_PERIA_INTA253	253
+#define	VECT_PERIA_INTA254	254
+#define	VECT_PERIA_INTA255	255
+
+#define	MSTP_EXDMAC		SYSTEM.MSTPCRA.BIT.MSTPA29
+#define	MSTP_EXDMAC0	SYSTEM.MSTPCRA.BIT.MSTPA29
+#define	MSTP_EXDMAC1	SYSTEM.MSTPCRA.BIT.MSTPA29
+#define	MSTP_DMAC		SYSTEM.MSTPCRA.BIT.MSTPA28
+#define	MSTP_DMAC0		SYSTEM.MSTPCRA.BIT.MSTPA28
+#define	MSTP_DMAC1		SYSTEM.MSTPCRA.BIT.MSTPA28
+#define	MSTP_DMAC2		SYSTEM.MSTPCRA.BIT.MSTPA28
+#define	MSTP_DMAC3		SYSTEM.MSTPCRA.BIT.MSTPA28
+#define	MSTP_DMAC4		SYSTEM.MSTPCRA.BIT.MSTPA28
+#define	MSTP_DMAC5		SYSTEM.MSTPCRA.BIT.MSTPA28
+#define	MSTP_DMAC6		SYSTEM.MSTPCRA.BIT.MSTPA28
+#define	MSTP_DMAC7		SYSTEM.MSTPCRA.BIT.MSTPA28
+#define	MSTP_DTC		SYSTEM.MSTPCRA.BIT.MSTPA28
+#define	MSTP_DA			SYSTEM.MSTPCRA.BIT.MSTPA19
+#define	MSTP_S12AD		SYSTEM.MSTPCRA.BIT.MSTPA17
+#define	MSTP_S12AD1		SYSTEM.MSTPCRA.BIT.MSTPA16
+#define	MSTP_CMT0		SYSTEM.MSTPCRA.BIT.MSTPA15
+#define	MSTP_CMT1		SYSTEM.MSTPCRA.BIT.MSTPA15
+#define	MSTP_CMT2		SYSTEM.MSTPCRA.BIT.MSTPA14
+#define	MSTP_CMT3		SYSTEM.MSTPCRA.BIT.MSTPA14
+#define	MSTP_TPU0		SYSTEM.MSTPCRA.BIT.MSTPA13
+#define	MSTP_TPU1		SYSTEM.MSTPCRA.BIT.MSTPA13
+#define	MSTP_TPU2		SYSTEM.MSTPCRA.BIT.MSTPA13
+#define	MSTP_TPU3		SYSTEM.MSTPCRA.BIT.MSTPA13
+#define	MSTP_TPU4		SYSTEM.MSTPCRA.BIT.MSTPA13
+#define	MSTP_TPU5		SYSTEM.MSTPCRA.BIT.MSTPA13
+#define	MSTP_TPUA		SYSTEM.MSTPCRA.BIT.MSTPA13
+#define	MSTP_PPG0		SYSTEM.MSTPCRA.BIT.MSTPA11
+#define	MSTP_PPG1		SYSTEM.MSTPCRA.BIT.MSTPA10
+#define	MSTP_MTU		SYSTEM.MSTPCRA.BIT.MSTPA9
+#define	MSTP_MTU0		SYSTEM.MSTPCRA.BIT.MSTPA9
+#define	MSTP_MTU1		SYSTEM.MSTPCRA.BIT.MSTPA9
+#define	MSTP_MTU2		SYSTEM.MSTPCRA.BIT.MSTPA9
+#define	MSTP_MTU3		SYSTEM.MSTPCRA.BIT.MSTPA9
+#define	MSTP_MTU4		SYSTEM.MSTPCRA.BIT.MSTPA9
+#define	MSTP_MTU5		SYSTEM.MSTPCRA.BIT.MSTPA9
+#define	MSTP_MTU6		SYSTEM.MSTPCRA.BIT.MSTPA9
+#define	MSTP_MTU7		SYSTEM.MSTPCRA.BIT.MSTPA9
+#define	MSTP_MTU8		SYSTEM.MSTPCRA.BIT.MSTPA9
+#define	MSTP_TMR0		SYSTEM.MSTPCRA.BIT.MSTPA5
+#define	MSTP_TMR1		SYSTEM.MSTPCRA.BIT.MSTPA5
+#define	MSTP_TMR01		SYSTEM.MSTPCRA.BIT.MSTPA5
+#define	MSTP_TMR2		SYSTEM.MSTPCRA.BIT.MSTPA4
+#define	MSTP_TMR3		SYSTEM.MSTPCRA.BIT.MSTPA4
+#define	MSTP_TMR23		SYSTEM.MSTPCRA.BIT.MSTPA4
+#define	MSTP_CMTW0		SYSTEM.MSTPCRA.BIT.MSTPA1
+#define	MSTP_CMTW1		SYSTEM.MSTPCRA.BIT.MSTPA0
+#define	MSTP_SCI0		SYSTEM.MSTPCRB.BIT.MSTPB31
+#define	MSTP_SMCI0		SYSTEM.MSTPCRB.BIT.MSTPB31
+#define	MSTP_SCI1		SYSTEM.MSTPCRB.BIT.MSTPB30
+#define	MSTP_SMCI1		SYSTEM.MSTPCRB.BIT.MSTPB30
+#define	MSTP_SCI2		SYSTEM.MSTPCRB.BIT.MSTPB29
+#define	MSTP_SMCI2		SYSTEM.MSTPCRB.BIT.MSTPB29
+#define	MSTP_SCI3		SYSTEM.MSTPCRB.BIT.MSTPB28
+#define	MSTP_SMCI3		SYSTEM.MSTPCRB.BIT.MSTPB28
+#define	MSTP_SCI4		SYSTEM.MSTPCRB.BIT.MSTPB27
+#define	MSTP_SMCI4		SYSTEM.MSTPCRB.BIT.MSTPB27
+#define	MSTP_SCI5		SYSTEM.MSTPCRB.BIT.MSTPB26
+#define	MSTP_SMCI5		SYSTEM.MSTPCRB.BIT.MSTPB26
+#define	MSTP_SCI6		SYSTEM.MSTPCRB.BIT.MSTPB25
+#define	MSTP_SMCI6		SYSTEM.MSTPCRB.BIT.MSTPB25
+#define	MSTP_SCI7		SYSTEM.MSTPCRB.BIT.MSTPB24
+#define	MSTP_SMCI7		SYSTEM.MSTPCRB.BIT.MSTPB24
+#define	MSTP_CRC		SYSTEM.MSTPCRB.BIT.MSTPB23
+#define	MSTP_PDC		SYSTEM.MSTPCRB.BIT.MSTPB22
+#define	MSTP_RIIC0		SYSTEM.MSTPCRB.BIT.MSTPB21
+#define	MSTP_RIIC1		SYSTEM.MSTPCRB.BIT.MSTPB20
+#define	MSTP_USB0		SYSTEM.MSTPCRB.BIT.MSTPB19
+#define	MSTP_RSPI0		SYSTEM.MSTPCRB.BIT.MSTPB17
+#define	MSTP_RSPI1		SYSTEM.MSTPCRB.BIT.MSTPB16
+#define	MSTP_ETHERC0	SYSTEM.MSTPCRB.BIT.MSTPB15
+#define	MSTP_EDMAC0		SYSTEM.MSTPCRB.BIT.MSTPB15
+#define	MSTP_ELC		SYSTEM.MSTPCRB.BIT.MSTPB9
+#define	MSTP_TEMPS		SYSTEM.MSTPCRB.BIT.MSTPB8
+#define	MSTP_DOC		SYSTEM.MSTPCRB.BIT.MSTPB6
+#define	MSTP_SCI12		SYSTEM.MSTPCRB.BIT.MSTPB4
+#define	MSTP_SMCI12		SYSTEM.MSTPCRB.BIT.MSTPB4
+#define	MSTP_CAN1		SYSTEM.MSTPCRB.BIT.MSTPB1
+#define	MSTP_CAN0		SYSTEM.MSTPCRB.BIT.MSTPB0
+#define	MSTP_GLCDC		SYSTEM.MSTPCRC.BIT.MSTPC29
+#define	MSTP_DRW2D		SYSTEM.MSTPCRC.BIT.MSTPC28
+#define	MSTP_SCI8		SYSTEM.MSTPCRC.BIT.MSTPC27
+#define	MSTP_SMCI8		SYSTEM.MSTPCRC.BIT.MSTPC27
+#define	MSTP_SCI9		SYSTEM.MSTPCRC.BIT.MSTPC26
+#define	MSTP_SMCI9		SYSTEM.MSTPCRC.BIT.MSTPC26
+#define	MSTP_SCI10		SYSTEM.MSTPCRC.BIT.MSTPC25
+#define	MSTP_SMCI10		SYSTEM.MSTPCRC.BIT.MSTPC25
+#define	MSTP_SCI11		SYSTEM.MSTPCRC.BIT.MSTPC24
+#define	MSTP_SMCI11		SYSTEM.MSTPCRC.BIT.MSTPC24
+#define	MSTP_QSPI		SYSTEM.MSTPCRC.BIT.MSTPC23
+#define	MSTP_RSPI2		SYSTEM.MSTPCRC.BIT.MSTPC22
+#define	MSTP_CAC		SYSTEM.MSTPCRC.BIT.MSTPC19
+#define	MSTP_RIIC2		SYSTEM.MSTPCRC.BIT.MSTPC17
+#define	MSTP_STBYRAM	SYSTEM.MSTPCRC.BIT.MSTPC7
+#define	MSTP_RAM2		SYSTEM.MSTPCRC.BIT.MSTPC2
+#define	MSTP_RAM0		SYSTEM.MSTPCRC.BIT.MSTPC0
+#define	MSTP_TSIP		SYSTEM.MSTPCRD.BIT.MSTPD27
+#define	MSTP_MMCIF		SYSTEM.MSTPCRD.BIT.MSTPD21
+#define	MSTP_SDHI		SYSTEM.MSTPCRD.BIT.MSTPD19
+#define	MSTP_SDSI		SYSTEM.MSTPCRD.BIT.MSTPD13
+
+#define	IS_CAN0_ERS0		IS0
+#define	IS_CAN1_ERS1		IS1
+#define	IS_SCI0_TEI0		IS0
+#define	IS_SCI0_ERI0		IS1
+#define	IS_SCI1_TEI1		IS2
+#define	IS_SCI1_ERI1		IS3
+#define	IS_SCI2_TEI2		IS4
+#define	IS_SCI2_ERI2		IS5
+#define	IS_SCI3_TEI3		IS6
+#define	IS_SCI3_ERI3		IS7
+#define	IS_SCI4_TEI4		IS8
+#define	IS_SCI4_ERI4		IS9
+#define	IS_SCI5_TEI5		IS10
+#define	IS_SCI5_ERI5		IS11
+#define	IS_SCI6_TEI6		IS12
+#define	IS_SCI6_ERI6		IS13
+#define	IS_SCI7_TEI7		IS14
+#define	IS_SCI7_ERI7		IS15
+#define	IS_SCI12_TEI12		IS16
+#define	IS_SCI12_ERI12		IS17
+#define	IS_SCI12_SCIX0		IS18
+#define	IS_SCI12_SCIX1		IS19
+#define	IS_SCI12_SCIX2		IS20
+#define	IS_SCI12_SCIX3		IS21
+#define	IS_QSPI_QSPSSLI		IS24
+#define	IS_CAC_FERRI		IS26
+#define	IS_CAC_MENDI		IS27
+#define	IS_CAC_OVFI			IS28
+#define	IS_DOC_DOPCI		IS29
+#define	IS_PDC_PCFEI		IS30
+#define	IS_PDC_PCERI		IS31
+#define	IS_SDHI_CDETI		IS3
+#define	IS_SDHI_CACI		IS4
+#define	IS_SDHI_SDACI		IS5
+#define	IS_MMCIF_CDETIO		IS6
+#define	IS_MMCIF_ERRIO		IS7
+#define	IS_MMCIF_ACCIO		IS8
+#define	IS_POE3_OEI1		IS9
+#define	IS_POE3_OEI2		IS10
+#define	IS_POE3_OEI3		IS11
+#define	IS_POE3_OEI4		IS12
+#define	IS_RIIC0_TEI0		IS13
+#define	IS_RIIC0_EEI0		IS14
+#define	IS_RIIC2_TEI2		IS15
+#define	IS_RIIC2_EEI2		IS16
+#define	IS_S12AD_S12CMPAI	IS20
+#define	IS_S12AD_S12CMPBI	IS21
+#define	IS_S12AD1_S12CMPAI1	IS22
+#define	IS_S12AD1_S12CMPBI1	IS23
+#define	IS_SCI8_TEI8		IS24
+#define	IS_SCI8_ERI8		IS25
+#define	IS_SCI9_TEI9		IS26
+#define	IS_SCI9_ERI9		IS27
+#define	IS_RIIC1_TEI1		IS28
+#define	IS_RIIC1_EEI1		IS29
+#define	IS_SDSI_SDIOI		IS0
+#define	IS_SCI10_TEI10		IS8
+#define	IS_SCI10_ERI10		IS9
+#define	IS_SCI11_TEI11		IS12
+#define	IS_SCI11_ERI11		IS13
+#define	IS_RSPI0_SPII0		IS16
+#define	IS_RSPI0_SPEI0		IS17
+#define	IS_RSPI1_SPII1		IS18
+#define	IS_RSPI1_SPEI1		IS19
+#define	IS_RSPI2_SPII2		IS20
+#define	IS_RSPI2_SPEI2		IS21
+#define	IS_EDMAC0_EINT0		IS4
+#define	IS_GLCDC_VPOS		IS8
+#define	IS_GLCDC_GR1UF		IS9
+#define	IS_GLCDC_GR2UF		IS10
+#define	IS_DRW2D_DRWIRQ		IS11
+
+#define	EN_CAN0_ERS0		EN0
+#define	EN_CAN1_ERS1		EN1
+#define	EN_SCI0_TEI0		EN0
+#define	EN_SCI0_ERI0		EN1
+#define	EN_SCI1_TEI1		EN2
+#define	EN_SCI1_ERI1		EN3
+#define	EN_SCI2_TEI2		EN4
+#define	EN_SCI2_ERI2		EN5
+#define	EN_SCI3_TEI3		EN6
+#define	EN_SCI3_ERI3		EN7
+#define	EN_SCI4_TEI4		EN8
+#define	EN_SCI4_ERI4		EN9
+#define	EN_SCI5_TEI5		EN10
+#define	EN_SCI5_ERI5		EN11
+#define	EN_SCI6_TEI6		EN12
+#define	EN_SCI6_ERI6		EN13
+#define	EN_SCI7_TEI7		EN14
+#define	EN_SCI7_ERI7		EN15
+#define	EN_SCI12_TEI12		EN16
+#define	EN_SCI12_ERI12		EN17
+#define	EN_SCI12_SCIX0		EN18
+#define	EN_SCI12_SCIX1		EN19
+#define	EN_SCI12_SCIX2		EN20
+#define	EN_SCI12_SCIX3		EN21
+#define	EN_QSPI_QSPSSLI		EN24
+#define	EN_CAC_FERRI		EN26
+#define	EN_CAC_MENDI		EN27
+#define	EN_CAC_OVFI			EN28
+#define	EN_DOC_DOPCI		EN29
+#define	EN_PDC_PCFEI		EN30
+#define	EN_PDC_PCERI		EN31
+#define	EN_SDHI_CDETI		EN3
+#define	EN_SDHI_CACI		EN4
+#define	EN_SDHI_SDACI		EN5
+#define	EN_MMCIF_CDETIO		EN6
+#define	EN_MMCIF_ERRIO		EN7
+#define	EN_MMCIF_ACCIO		EN8
+#define	EN_POE3_OEI1		EN9
+#define	EN_POE3_OEI2		EN10
+#define	EN_POE3_OEI3		EN11
+#define	EN_POE3_OEI4		EN12
+#define	EN_RIIC0_TEI0		EN13
+#define	EN_RIIC0_EEI0		EN14
+#define	EN_RIIC2_TEI2		EN15
+#define	EN_RIIC2_EEI2		EN16
+#define	EN_S12AD_S12CMPAI	EN20
+#define	EN_S12AD_S12CMPBI	EN21
+#define	EN_S12AD1_S12CMPAI1	EN22
+#define	EN_S12AD1_S12CMPBI1	EN23
+#define	EN_SCI8_TEI8		EN24
+#define	EN_SCI8_ERI8		EN25
+#define	EN_SCI9_TEI9		EN26
+#define	EN_SCI9_ERI9		EN27
+#define	EN_RIIC1_TEI1		EN28
+#define	EN_RIIC1_EEI1		EN29
+#define	EN_SDSI_SDIOI		EN0
+#define	EN_SCI10_TEI10		EN8
+#define	EN_SCI10_ERI10		EN9
+#define	EN_SCI11_TEI11		EN12
+#define	EN_SCI11_ERI11		EN13
+#define	EN_RSPI0_SPII0		EN16
+#define	EN_RSPI0_SPEI0		EN17
+#define	EN_RSPI1_SPII1		EN18
+#define	EN_RSPI1_SPEI1		EN19
+#define	EN_RSPI2_SPII2		EN20
+#define	EN_RSPI2_SPEI2		EN21
+#define	EN_EDMAC0_EINT0		EN4
+#define	EN_GLCDC_VPOS		EN8
+#define	EN_GLCDC_GR1UF		EN9
+#define	EN_GLCDC_GR2UF		EN10
+#define	EN_DRW2D_DRWIRQ		EN11
+
+#define	CLR_CAN0_ERS0		CLR0
+#define	CLR_CAN1_ERS1		CLR1
+
+#define	GEN_CAN0_ERS0			GENBE0
+#define	GEN_CAN1_ERS1			GENBE0
+#define	GEN_SCI0_TEI0			GENBL0
+#define	GEN_SCI0_ERI0			GENBL0
+#define	GEN_SCI1_TEI1			GENBL0
+#define	GEN_SCI1_ERI1			GENBL0
+#define	GEN_SCI2_TEI2			GENBL0
+#define	GEN_SCI2_ERI2			GENBL0
+#define	GEN_SCI3_TEI3			GENBL0
+#define	GEN_SCI3_ERI3			GENBL0
+#define	GEN_SCI4_TEI4			GENBL0
+#define	GEN_SCI4_ERI4			GENBL0
+#define	GEN_SCI5_TEI5			GENBL0
+#define	GEN_SCI5_ERI5			GENBL0
+#define	GEN_SCI6_TEI6			GENBL0
+#define	GEN_SCI6_ERI6			GENBL0
+#define	GEN_SCI7_TEI7			GENBL0
+#define	GEN_SCI7_ERI7			GENBL0
+#define	GEN_SCI12_TEI12			GENBL0
+#define	GEN_SCI12_ERI12			GENBL0
+#define	GEN_SCI12_SCIX0			GENBL0
+#define	GEN_SCI12_SCIX1			GENBL0
+#define	GEN_SCI12_SCIX2			GENBL0
+#define	GEN_SCI12_SCIX3			GENBL0
+#define	GEN_QSPI_QSPSSLI		GENBL0
+#define	GEN_CAC_FERRI			GENBL0
+#define	GEN_CAC_MENDI			GENBL0
+#define	GEN_CAC_OVFI			GENBL0
+#define	GEN_DOC_DOPCI			GENBL0
+#define	GEN_PDC_PCFEI			GENBL0
+#define	GEN_PDC_PCERI			GENBL0
+#define	GEN_SDHI_CDETI			GENBL1
+#define	GEN_SDHI_CACI			GENBL1
+#define	GEN_SDHI_SDACI			GENBL1
+#define	GEN_MMCIF_CDETIO		GENBL1
+#define	GEN_MMCIF_ERRIO			GENBL1
+#define	GEN_MMCIF_ACCIO			GENBL1
+#define	GEN_POE3_OEI1			GENBL1
+#define	GEN_POE3_OEI2			GENBL1
+#define	GEN_POE3_OEI3			GENBL1
+#define	GEN_POE3_OEI4			GENBL1
+#define	GEN_RIIC0_TEI0			GENBL1
+#define	GEN_RIIC0_EEI0			GENBL1
+#define	GEN_RIIC2_TEI2			GENBL1
+#define	GEN_RIIC2_EEI2			GENBL1
+#define	GEN_S12AD_S12CMPAI		GENBL1
+#define	GEN_S12AD_S12CMPBI		GENBL1
+#define	GEN_S12AD1_S12CMPAI1	GENBL1
+#define	GEN_S12AD1_S12CMPBI1	GENBL1
+#define	GEN_SCI8_TEI8			GENBL1
+#define	GEN_SCI8_ERI8			GENBL1
+#define	GEN_SCI9_TEI9			GENBL1
+#define	GEN_SCI9_ERI9			GENBL1
+#define	GEN_RIIC1_TEI1			GENBL1
+#define	GEN_RIIC1_EEI1			GENBL1
+#define	GEN_SDSI_SDIOI			GENBL2
+#define	GEN_SCI10_TEI10			GENAL0
+#define	GEN_SCI10_ERI10			GENAL0
+#define	GEN_SCI11_TEI11			GENAL0
+#define	GEN_SCI11_ERI11			GENAL0
+#define	GEN_RSPI0_SPII0			GENAL0
+#define	GEN_RSPI0_SPEI0			GENAL0
+#define	GEN_RSPI1_SPII1			GENAL0
+#define	GEN_RSPI1_SPEI1			GENAL0
+#define	GEN_RSPI2_SPII2			GENAL0
+#define	GEN_RSPI2_SPEI2			GENAL0
+#define	GEN_EDMAC0_EINT0		GENAL1
+#define	GEN_GLCDC_VPOS			GENAL1
+#define	GEN_GLCDC_GR1UF			GENAL1
+#define	GEN_GLCDC_GR2UF			GENAL1
+#define	GEN_DRW2D_DRWIRQ		GENAL1
+
+#define	GRP_CAN0_ERS0			GRPBE0
+#define	GRP_CAN1_ERS1			GRPBE0
+#define	GRP_SCI0_TEI0			GRPBL0
+#define	GRP_SCI0_ERI0			GRPBL0
+#define	GRP_SCI1_TEI1			GRPBL0
+#define	GRP_SCI1_ERI1			GRPBL0
+#define	GRP_SCI2_TEI2			GRPBL0
+#define	GRP_SCI2_ERI2			GRPBL0
+#define	GRP_SCI3_TEI3			GRPBL0
+#define	GRP_SCI3_ERI3			GRPBL0
+#define	GRP_SCI4_TEI4			GRPBL0
+#define	GRP_SCI4_ERI4			GRPBL0
+#define	GRP_SCI5_TEI5			GRPBL0
+#define	GRP_SCI5_ERI5			GRPBL0
+#define	GRP_SCI6_TEI6			GRPBL0
+#define	GRP_SCI6_ERI6			GRPBL0
+#define	GRP_SCI7_TEI7			GRPBL0
+#define	GRP_SCI7_ERI7			GRPBL0
+#define	GRP_SCI12_TEI12			GRPBL0
+#define	GRP_SCI12_ERI12			GRPBL0
+#define	GRP_SCI12_SCIX0			GRPBL0
+#define	GRP_SCI12_SCIX1			GRPBL0
+#define	GRP_SCI12_SCIX2			GRPBL0
+#define	GRP_SCI12_SCIX3			GRPBL0
+#define	GRP_QSPI_QSPSSLI		GRPBL0
+#define	GRP_CAC_FERRI			GRPBL0
+#define	GRP_CAC_MENDI			GRPBL0
+#define	GRP_CAC_OVFI			GRPBL0
+#define	GRP_DOC_DOPCI			GRPBL0
+#define	GRP_PDC_PCFEI			GRPBL0
+#define	GRP_PDC_PCERI			GRPBL0
+#define	GRP_SDHI_CDETI			GRPBL1
+#define	GRP_SDHI_CACI			GRPBL1
+#define	GRP_SDHI_SDACI			GRPBL1
+#define	GRP_MMCIF_CDETIO		GRPBL1
+#define	GRP_MMCIF_ERRIO			GRPBL1
+#define	GRP_MMCIF_ACCIO			GRPBL1
+#define	GRP_POE3_OEI1			GRPBL1
+#define	GRP_POE3_OEI2			GRPBL1
+#define	GRP_POE3_OEI3			GRPBL1
+#define	GRP_POE3_OEI4			GRPBL1
+#define	GRP_RIIC0_TEI0			GRPBL1
+#define	GRP_RIIC0_EEI0			GRPBL1
+#define	GRP_RIIC2_TEI2			GRPBL1
+#define	GRP_RIIC2_EEI2			GRPBL1
+#define	GRP_S12AD_S12CMPAI		GRPBL1
+#define	GRP_S12AD_S12CMPBI		GRPBL1
+#define	GRP_S12AD1_S12CMPAI1	GRPBL1
+#define	GRP_S12AD1_S12CMPBI1	GRPBL1
+#define	GRP_SCI8_TEI8			GRPBL1
+#define	GRP_SCI8_ERI8			GRPBL1
+#define	GRP_SCI9_TEI9			GRPBL1
+#define	GRP_SCI9_ERI9			GRPBL1
+#define	GRP_RIIC1_TEI1			GRPBL1
+#define	GRP_RIIC1_EEI1			GRPBL1
+#define	GRP_SDSI_SDIOI			GRPBL2
+#define	GRP_SCI10_TEI10			GRPAL0
+#define	GRP_SCI10_ERI10			GRPAL0
+#define	GRP_SCI11_TEI11			GRPAL0
+#define	GRP_SCI11_ERI11			GRPAL0
+#define	GRP_RSPI0_SPII0			GRPAL0
+#define	GRP_RSPI0_SPEI0			GRPAL0
+#define	GRP_RSPI1_SPII1			GRPAL0
+#define	GRP_RSPI1_SPEI1			GRPAL0
+#define	GRP_RSPI2_SPII2			GRPAL0
+#define	GRP_RSPI2_SPEI2			GRPAL0
+#define	GRP_EDMAC0_EINT0		GRPAL1
+#define	GRP_GLCDC_VPOS			GRPAL1
+#define	GRP_GLCDC_GR1UF			GRPAL1
+#define	GRP_GLCDC_GR2UF			GRPAL1
+#define	GRP_DRW2D_DRWIRQ		GRPAL1
+
+#define	GCR_CAN0_ERS0			GCRBE0
+#define	GCR_CAN1_ERS1			GCRBE0
+
+#define	__IR( x )		ICU.IR[ IR ## x ].BIT.IR
+#define	 _IR( x )		__IR( x )
+#define	  IR( x , y )	_IR( _ ## x ## _ ## y )
+#define	__DTCE( x )		ICU.DTCER[ DTCE ## x ].BIT.DTCE
+#define	 _DTCE( x )		__DTCE( x )
+#define	  DTCE( x , y )	_DTCE( _ ## x ## _ ## y )
+#define	__IEN( x )		ICU.IER[ IER ## x ].BIT.IEN ## x
+#define	 _IEN( x )		__IEN( x )
+#define	  IEN( x , y )	_IEN( _ ## x ## _ ## y )
+#define	__IPR( x )		ICU.IPR[ IPR ## x ].BIT.IPR
+#define	 _IPR( x )		__IPR( x )
+#define	  IPR( x , y )	_IPR( _ ## x ## _ ## y )
+#define	__VECT( x )		VECT ## x
+#define	 _VECT( x )		__VECT( x )
+#define	  VECT( x , y )	_VECT( _ ## x ## _ ## y )
+#define	__MSTP( x )		MSTP ## x
+#define	 _MSTP( x )		__MSTP( x )
+#define	  MSTP( x )		_MSTP( _ ## x )
+
+#define	__IS( x )		ICU.GRP ## x.BIT.IS ## x
+#define	 _IS( x )		__IS( x )
+#define	  IS( x , y )	_IS( _ ## x ## _ ## y )
+#define	__EN( x )		ICU.GEN ## x.BIT.EN ## x
+#define	 _EN( x )		__EN( x )
+#define	  EN( x , y )	_EN( _ ## x ## _ ## y )
+#define	__CLR( x )		ICU.GCR ## x.BIT.CLR ## x
+#define	 _CLR( x )		__CLR( x )
+#define	  CLR( x , y )	_CLR( _ ## x ## _ ## y )
+
+#define	BSC			(*(volatile struct st_bsc      *)0x81300)
+#define	CAC			(*(volatile struct st_cac      *)0x8B000)
+#define	CAN0		(*(volatile struct st_can      *)0x90200)
+#define	CAN1		(*(volatile struct st_can      *)0x91200)
+#define	CMT			(*(volatile struct st_cmt      *)0x88000)
+#define	CMT0		(*(volatile struct st_cmt0     *)0x88002)
+#define	CMT1		(*(volatile struct st_cmt0     *)0x88008)
+#define	CMT2		(*(volatile struct st_cmt0     *)0x88012)
+#define	CMT3		(*(volatile struct st_cmt0     *)0x88018)
+#define	CMTW0		(*(volatile struct st_cmtw     *)0x94200)
+#define	CMTW1		(*(volatile struct st_cmtw     *)0x94280)
+#define	CRC			(*(volatile struct st_crc      *)0x88280)
+#define	DA			(*(volatile struct st_da       *)0x88040)
+#define	DMAC		(*(volatile struct st_dmac     *)0x82200)
+#define	DMAC0		(*(volatile struct st_dmac0    *)0x82000)
+#define	DMAC1		(*(volatile struct st_dmac1    *)0x82040)
+#define	DMAC2		(*(volatile struct st_dmac1    *)0x82080)
+#define	DMAC3		(*(volatile struct st_dmac1    *)0x820C0)
+#define	DMAC4		(*(volatile struct st_dmac1    *)0x82100)
+#define	DMAC5		(*(volatile struct st_dmac1    *)0x82140)
+#define	DMAC6		(*(volatile struct st_dmac1    *)0x82180)
+#define	DMAC7		(*(volatile struct st_dmac1    *)0x821C0)
+#define	DOC			(*(volatile struct st_doc      *)0x8B080)
+#define	DRW2D		(*(volatile struct st_drw2d    *)0xE3000)
+#define	DTC			(*(volatile struct st_dtc      *)0x82400)
+#define	EDMAC0		(*(volatile struct st_edmac    *)0xC0000)
+#define	ELC			(*(volatile struct st_elc      *)0x8B100)
+#define	ETHERC0		(*(volatile struct st_etherc   *)0xC0100)
+#define	EXDMAC		(*(volatile struct st_exdmac   *)0x82A00)
+#define	EXDMAC0		(*(volatile struct st_exdmac0  *)0x82800)
+#define	EXDMAC1		(*(volatile struct st_exdmac1  *)0x82840)
+#define	FLASH		(*(volatile struct st_flash    *)0x81000)
+#define	GLCDC		(*(volatile struct st_glcdc    *)0xE0000)
+#define	ICU			(*(volatile struct st_icu      *)0x87000)
+#define	IWDT		(*(volatile struct st_iwdt     *)0x88030)
+#define	MMCIF		(*(volatile struct st_mmcif    *)0x88500)
+#define	MPC			(*(volatile struct st_mpc      *)0x8C100)
+#define	MPU			(*(volatile struct st_mpu      *)0x86400)
+#define	MTU			(*(volatile struct st_mtu      *)0xC120A)
+#define	MTU0		(*(volatile struct st_mtu0     *)0xC1290)
+#define	MTU1		(*(volatile struct st_mtu1     *)0xC1290)
+#define	MTU2		(*(volatile struct st_mtu2     *)0xC1292)
+#define	MTU3		(*(volatile struct st_mtu3     *)0xC1200)
+#define	MTU4		(*(volatile struct st_mtu4     *)0xC1200)
+#define	MTU5		(*(volatile struct st_mtu5     *)0xC1A94)
+#define	MTU6		(*(volatile struct st_mtu6     *)0xC1A00)
+#define	MTU7		(*(volatile struct st_mtu7     *)0xC1A00)
+#define	MTU8		(*(volatile struct st_mtu8     *)0xC1298)
+#define	OFSM		(*(volatile struct st_ofsm     *)0xFE7F5D00)
+#define	PDC			(*(volatile struct st_pdc      *)0xA0500)
+#define	POE3		(*(volatile struct st_poe      *)0x8C4C0)
+#define	PORT0		(*(volatile struct st_port0    *)0x8C000)
+#define	PORT1		(*(volatile struct st_port1    *)0x8C001)
+#define	PORT2		(*(volatile struct st_port2    *)0x8C002)
+#define	PORT3		(*(volatile struct st_port3    *)0x8C003)
+#define	PORT4		(*(volatile struct st_port4    *)0x8C004)
+#define	PORT5		(*(volatile struct st_port5    *)0x8C005)
+#define	PORT6		(*(volatile struct st_port6    *)0x8C006)
+#define	PORT7		(*(volatile struct st_port7    *)0x8C007)
+#define	PORT8		(*(volatile struct st_port8    *)0x8C008)
+#define	PORT9		(*(volatile struct st_port9    *)0x8C009)
+#define	PORTA		(*(volatile struct st_porta    *)0x8C00A)
+#define	PORTB		(*(volatile struct st_portb    *)0x8C00B)
+#define	PORTC		(*(volatile struct st_portc    *)0x8C00C)
+#define	PORTD		(*(volatile struct st_portd    *)0x8C00D)
+#define	PORTE		(*(volatile struct st_porte    *)0x8C00E)
+#define	PORTF		(*(volatile struct st_portf    *)0x8C00F)
+#define	PORTG		(*(volatile struct st_portg    *)0x8C010)
+#define	PORTJ		(*(volatile struct st_portj    *)0x8C012)
+#define	PPG0		(*(volatile struct st_ppg0     *)0x881E6)
+#define	PPG1		(*(volatile struct st_ppg1     *)0x881F0)
+#define	QSPI		(*(volatile struct st_qspi     *)0x89E00)
+#define	RAM			(*(volatile struct st_ram      *)0x81200)
+#define	RIIC0		(*(volatile struct st_riic     *)0x88300)
+#define	RIIC1		(*(volatile struct st_riic     *)0x88320)
+#define	RIIC2		(*(volatile struct st_riic     *)0x88340)
+#define	RSPI0		(*(volatile struct st_rspi     *)0xD0100)
+#define	RSPI1		(*(volatile struct st_rspi     *)0xD0140)
+#define	RSPI2		(*(volatile struct st_rspi     *)0xD0300)
+#define	RTC			(*(volatile struct st_rtc      *)0x8C400)
+#define	S12AD		(*(volatile struct st_s12ad    *)0x89000)
+#define	S12AD1		(*(volatile struct st_s12ad1   *)0x89100)
+#define	SCI0		(*(volatile struct st_sci0     *)0x8A000)
+#define	SCI1		(*(volatile struct st_sci0     *)0x8A020)
+#define	SCI2		(*(volatile struct st_sci0     *)0x8A040)
+#define	SCI3		(*(volatile struct st_sci0     *)0x8A060)
+#define	SCI4		(*(volatile struct st_sci0     *)0x8A080)
+#define	SCI5		(*(volatile struct st_sci0     *)0x8A0A0)
+#define	SCI6		(*(volatile struct st_sci0     *)0x8A0C0)
+#define	SCI7		(*(volatile struct st_sci0     *)0x8A0E0)
+#define	SCI8		(*(volatile struct st_sci0     *)0x8A100)
+#define	SCI9		(*(volatile struct st_sci0     *)0x8A120)
+#define	SCI10		(*(volatile struct st_sci10    *)0xD0040)
+#define	SCI11		(*(volatile struct st_sci10    *)0xD0060)
+#define	SCI12		(*(volatile struct st_sci12    *)0x8B300)
+#define	SDHI		(*(volatile struct st_sdhi     *)0x8AC00)
+#define	SDSI		(*(volatile struct st_sdsi     *)0x95000)
+#define	SMCI0		(*(volatile struct st_smci0    *)0x8A000)
+#define	SMCI1		(*(volatile struct st_smci0    *)0x8A020)
+#define	SMCI2		(*(volatile struct st_smci0    *)0x8A040)
+#define	SMCI3		(*(volatile struct st_smci0    *)0x8A060)
+#define	SMCI4		(*(volatile struct st_smci0    *)0x8A080)
+#define	SMCI5		(*(volatile struct st_smci0    *)0x8A0A0)
+#define	SMCI6		(*(volatile struct st_smci0    *)0x8A0C0)
+#define	SMCI7		(*(volatile struct st_smci0    *)0x8A0E0)
+#define	SMCI8		(*(volatile struct st_smci0    *)0x8A100)
+#define	SMCI9		(*(volatile struct st_smci0    *)0x8A120)
+#define	SMCI10		(*(volatile struct st_smci10   *)0xD0040)
+#define	SMCI11		(*(volatile struct st_smci10   *)0xD0060)
+#define	SMCI12		(*(volatile struct st_smci0    *)0x8B300)
+#define	SYSTEM		(*(volatile struct st_system   *)0x80000)
+#define	TEMPS		(*(volatile struct st_temps    *)0x8C500)
+#define	TMR0		(*(volatile struct st_tmr0     *)0x88200)
+#define	TMR1		(*(volatile struct st_tmr1     *)0x88201)
+#define	TMR2		(*(volatile struct st_tmr0     *)0x88210)
+#define	TMR3		(*(volatile struct st_tmr1     *)0x88211)
+#define	TMR01		(*(volatile struct st_tmr01    *)0x88204)
+#define	TMR23		(*(volatile struct st_tmr01    *)0x88214)
+#define	TPU0		(*(volatile struct st_tpu0     *)0x88108)
+#define	TPU1		(*(volatile struct st_tpu1     *)0x88108)
+#define	TPU2		(*(volatile struct st_tpu2     *)0x8810A)
+#define	TPU3		(*(volatile struct st_tpu3     *)0x8810A)
+#define	TPU4		(*(volatile struct st_tpu4     *)0x8810C)
+#define	TPU5		(*(volatile struct st_tpu5     *)0x8810C)
+#define	TPUA		(*(volatile struct st_tpua     *)0x88100)
+#define	USB			(*(volatile struct st_usb      *)0xA0400)
+#define	USB0		(*(volatile struct st_usb0     *)0xA0000)
+#define	WDT			(*(volatile struct st_wdt      *)0x88020)
+#define	FLASHCONST	(*(volatile struct st_flashconst  *)0xFE7F7D90)
+#define	TEMPSCONST	(*(volatile struct st_tempsconst  *)0xFE7F7D7C)
+
+typedef enum enum_ir {
+IR_BSC_BUSERR=16,IR_RAM_RAMERR=18,
+IR_FCU_FIFERR=21,IR_FCU_FRDYI=23,
+IR_ICU_SWINT2=26,IR_ICU_SWINT,
+IR_CMT0_CMI0,
+IR_CMT1_CMI1,
+IR_CMTW0_CMWI0,
+IR_CMTW1_CMWI1,
+IR_USB0_D0FIFO0=34,IR_USB0_D1FIFO0,
+IR_RSPI0_SPRI0=38,IR_RSPI0_SPTI0,
+IR_RSPI1_SPRI1,IR_RSPI1_SPTI1,
+IR_QSPI_SPRI,IR_QSPI_SPTI,
+IR_SDHI_SBFAI,
+IR_MMCIF_MBFAI,
+IR_RIIC1_RXI1=50,IR_RIIC1_TXI1,
+IR_RIIC0_RXI0,IR_RIIC0_TXI0,
+IR_RIIC2_RXI2,IR_RIIC2_TXI2,
+IR_SCI0_RXI0=58,IR_SCI0_TXI0,
+IR_SCI1_RXI1,IR_SCI1_TXI1,
+IR_SCI2_RXI2,IR_SCI2_TXI2,
+IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,
+IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15,
+IR_SCI3_RXI3,IR_SCI3_TXI3,
+IR_SCI4_RXI4,IR_SCI4_TXI4,
+IR_SCI5_RXI5,IR_SCI5_TXI5,
+IR_SCI6_RXI6,IR_SCI6_TXI6,
+IR_LVD1_LVD1,
+IR_LVD2_LVD2,
+IR_USB0_USBR0,
+IR_RTC_ALM=92,IR_RTC_PRD,
+IR_IWDT_IWUNI=95,
+IR_WDT_WUNI,
+IR_PDC_PCDFI,
+IR_SCI7_RXI7,IR_SCI7_TXI7,
+IR_SCI8_RXI8,IR_SCI8_TXI8,
+IR_SCI9_RXI9,IR_SCI9_TXI9,
+IR_SCI10_RXI10,IR_SCI10_TXI10,
+IR_ICU_GROUPBE0,IR_ICU_GROUPBL2,
+IR_RSPI2_SPRI2,IR_RSPI2_SPTI2,
+IR_ICU_GROUPBL0,IR_ICU_GROUPBL1,IR_ICU_GROUPAL0,IR_ICU_GROUPAL1,
+IR_SCI11_RXI11,IR_SCI11_TXI11,
+IR_SCI12_RXI12,IR_SCI12_TXI12,
+IR_DMAC_DMAC0I=120,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I,IR_DMAC_DMAC74I,
+IR_OST_OSTDI,
+IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I,
+IR_PERIB_INTB128,IR_PERIB_INTB129,IR_PERIB_INTB130,IR_PERIB_INTB131,IR_PERIB_INTB132,
+IR_PERIB_INTB133,IR_PERIB_INTB134,IR_PERIB_INTB135,IR_PERIB_INTB136,IR_PERIB_INTB137,
+IR_PERIB_INTB138,IR_PERIB_INTB139,IR_PERIB_INTB140,IR_PERIB_INTB141,IR_PERIB_INTB142,
+IR_PERIB_INTB143,IR_PERIB_INTB144,IR_PERIB_INTB145,IR_PERIB_INTB146,IR_PERIB_INTB147,
+IR_PERIB_INTB148,IR_PERIB_INTB149,IR_PERIB_INTB150,IR_PERIB_INTB151,IR_PERIB_INTB152,
+IR_PERIB_INTB153,IR_PERIB_INTB154,IR_PERIB_INTB155,IR_PERIB_INTB156,IR_PERIB_INTB157,
+IR_PERIB_INTB158,IR_PERIB_INTB159,IR_PERIB_INTB160,IR_PERIB_INTB161,IR_PERIB_INTB162,
+IR_PERIB_INTB163,IR_PERIB_INTB164,IR_PERIB_INTB165,IR_PERIB_INTB166,IR_PERIB_INTB167,
+IR_PERIB_INTB168,IR_PERIB_INTB169,IR_PERIB_INTB170,IR_PERIB_INTB171,IR_PERIB_INTB172,
+IR_PERIB_INTB173,IR_PERIB_INTB174,IR_PERIB_INTB175,IR_PERIB_INTB176,IR_PERIB_INTB177,
+IR_PERIB_INTB178,IR_PERIB_INTB179,IR_PERIB_INTB180,IR_PERIB_INTB181,IR_PERIB_INTB182,
+IR_PERIB_INTB183,IR_PERIB_INTB184,IR_PERIB_INTB185,IR_PERIB_INTB186,IR_PERIB_INTB187,
+IR_PERIB_INTB188,IR_PERIB_INTB189,IR_PERIB_INTB190,IR_PERIB_INTB191,IR_PERIB_INTB192,
+IR_PERIB_INTB193,IR_PERIB_INTB194,IR_PERIB_INTB195,IR_PERIB_INTB196,IR_PERIB_INTB197,
+IR_PERIB_INTB198,IR_PERIB_INTB199,IR_PERIB_INTB200,IR_PERIB_INTB201,IR_PERIB_INTB202,
+IR_PERIB_INTB203,IR_PERIB_INTB204,IR_PERIB_INTB205,IR_PERIB_INTB206,IR_PERIB_INTB207,
+IR_PERIA_INTA208,IR_PERIA_INTA209,IR_PERIA_INTA210,IR_PERIA_INTA211,IR_PERIA_INTA212,
+IR_PERIA_INTA213,IR_PERIA_INTA214,IR_PERIA_INTA215,IR_PERIA_INTA216,IR_PERIA_INTA217,
+IR_PERIA_INTA218,IR_PERIA_INTA219,IR_PERIA_INTA220,IR_PERIA_INTA221,IR_PERIA_INTA222,
+IR_PERIA_INTA223,IR_PERIA_INTA224,IR_PERIA_INTA225,IR_PERIA_INTA226,IR_PERIA_INTA227,
+IR_PERIA_INTA228,IR_PERIA_INTA229,IR_PERIA_INTA230,IR_PERIA_INTA231,IR_PERIA_INTA232,
+IR_PERIA_INTA233,IR_PERIA_INTA234,IR_PERIA_INTA235,IR_PERIA_INTA236,IR_PERIA_INTA237,
+IR_PERIA_INTA238,IR_PERIA_INTA239,IR_PERIA_INTA240,IR_PERIA_INTA241,IR_PERIA_INTA242,
+IR_PERIA_INTA243,IR_PERIA_INTA244,IR_PERIA_INTA245,IR_PERIA_INTA246,IR_PERIA_INTA247,
+IR_PERIA_INTA248,IR_PERIA_INTA249,IR_PERIA_INTA250,IR_PERIA_INTA251,IR_PERIA_INTA252,
+IR_PERIA_INTA253,IR_PERIA_INTA254,IR_PERIA_INTA255
+} enum_ir_t;
+
+typedef enum enum_dtce {
+DTCE_ICU_SWINT2=26,DTCE_ICU_SWINT,
+DTCE_CMT0_CMI0,
+DTCE_CMT1_CMI1,
+DTCE_CMTW0_CMWI0,
+DTCE_CMTW1_CMWI1,
+DTCE_USB0_D0FIFO0=34,DTCE_USB0_D1FIFO0,
+DTCE_RSPI0_SPRI0=38,DTCE_RSPI0_SPTI0,
+DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1,
+DTCE_QSPI_SPRI,DTCE_QSPI_SPTI,
+DTCE_SDHI_SBFAI,
+DTCE_MMCIF_MBFAI,
+DTCE_RIIC1_RXI1=50,DTCE_RIIC1_TXI1,
+DTCE_RIIC0_RXI0,DTCE_RIIC0_TXI0,
+DTCE_RIIC2_RXI2,DTCE_RIIC2_TXI2,
+DTCE_SCI0_RXI0=58,DTCE_SCI0_TXI0,
+DTCE_SCI1_RXI1,DTCE_SCI1_TXI1,
+DTCE_SCI2_RXI2,DTCE_SCI2_TXI2,
+DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,
+DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15,
+DTCE_SCI3_RXI3,DTCE_SCI3_TXI3,
+DTCE_SCI4_RXI4,DTCE_SCI4_TXI4,
+DTCE_SCI5_RXI5,DTCE_SCI5_TXI5,
+DTCE_SCI6_RXI6,DTCE_SCI6_TXI6,
+DTCE_PDC_PCDFI=97,
+DTCE_SCI7_RXI7,DTCE_SCI7_TXI7,
+DTCE_SCI8_RXI8,DTCE_SCI8_TXI8,
+DTCE_SCI9_RXI9,DTCE_SCI9_TXI9,
+DTCE_SCI10_RXI10,DTCE_SCI10_TXI10,
+DTCE_RSPI2_SPRI2=108,DTCE_RSPI2_SPTI2,
+DTCE_SCI11_RXI11=114,DTCE_SCI11_TXI11,
+DTCE_SCI12_RXI12,DTCE_SCI12_TXI12,
+DTCE_DMAC_DMAC0I=120,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I,
+DTCE_EXDMAC_EXDMAC0I=126,DTCE_EXDMAC_EXDMAC1I,
+DTCE_PERIB_INTB128,DTCE_PERIB_INTB129,DTCE_PERIB_INTB130,DTCE_PERIB_INTB131,DTCE_PERIB_INTB132,
+DTCE_PERIB_INTB133,DTCE_PERIB_INTB134,DTCE_PERIB_INTB135,DTCE_PERIB_INTB136,DTCE_PERIB_INTB137,
+DTCE_PERIB_INTB138,DTCE_PERIB_INTB139,DTCE_PERIB_INTB140,DTCE_PERIB_INTB141,DTCE_PERIB_INTB142,
+DTCE_PERIB_INTB143,DTCE_PERIB_INTB144,DTCE_PERIB_INTB145,DTCE_PERIB_INTB146,DTCE_PERIB_INTB147,
+DTCE_PERIB_INTB148,DTCE_PERIB_INTB149,DTCE_PERIB_INTB150,DTCE_PERIB_INTB151,DTCE_PERIB_INTB152,
+DTCE_PERIB_INTB153,DTCE_PERIB_INTB154,DTCE_PERIB_INTB155,DTCE_PERIB_INTB156,DTCE_PERIB_INTB157,
+DTCE_PERIB_INTB158,DTCE_PERIB_INTB159,DTCE_PERIB_INTB160,DTCE_PERIB_INTB161,DTCE_PERIB_INTB162,
+DTCE_PERIB_INTB163,DTCE_PERIB_INTB164,DTCE_PERIB_INTB165,DTCE_PERIB_INTB166,DTCE_PERIB_INTB167,
+DTCE_PERIB_INTB168,DTCE_PERIB_INTB169,DTCE_PERIB_INTB170,DTCE_PERIB_INTB171,DTCE_PERIB_INTB172,
+DTCE_PERIB_INTB173,DTCE_PERIB_INTB174,DTCE_PERIB_INTB175,DTCE_PERIB_INTB176,DTCE_PERIB_INTB177,
+DTCE_PERIB_INTB178,DTCE_PERIB_INTB179,DTCE_PERIB_INTB180,DTCE_PERIB_INTB181,DTCE_PERIB_INTB182,
+DTCE_PERIB_INTB183,DTCE_PERIB_INTB184,DTCE_PERIB_INTB185,DTCE_PERIB_INTB186,DTCE_PERIB_INTB187,
+DTCE_PERIB_INTB188,DTCE_PERIB_INTB189,DTCE_PERIB_INTB190,DTCE_PERIB_INTB191,DTCE_PERIB_INTB192,
+DTCE_PERIB_INTB193,DTCE_PERIB_INTB194,DTCE_PERIB_INTB195,DTCE_PERIB_INTB196,DTCE_PERIB_INTB197,
+DTCE_PERIB_INTB198,DTCE_PERIB_INTB199,DTCE_PERIB_INTB200,DTCE_PERIB_INTB201,DTCE_PERIB_INTB202,
+DTCE_PERIB_INTB203,DTCE_PERIB_INTB204,DTCE_PERIB_INTB205,DTCE_PERIB_INTB206,DTCE_PERIB_INTB207,
+DTCE_PERIA_INTA208,DTCE_PERIA_INTA209,DTCE_PERIA_INTA210,DTCE_PERIA_INTA211,DTCE_PERIA_INTA212,
+DTCE_PERIA_INTA213,DTCE_PERIA_INTA214,DTCE_PERIA_INTA215,DTCE_PERIA_INTA216,DTCE_PERIA_INTA217,
+DTCE_PERIA_INTA218,DTCE_PERIA_INTA219,DTCE_PERIA_INTA220,DTCE_PERIA_INTA221,DTCE_PERIA_INTA222,
+DTCE_PERIA_INTA223,DTCE_PERIA_INTA224,DTCE_PERIA_INTA225,DTCE_PERIA_INTA226,DTCE_PERIA_INTA227,
+DTCE_PERIA_INTA228,DTCE_PERIA_INTA229,DTCE_PERIA_INTA230,DTCE_PERIA_INTA231,DTCE_PERIA_INTA232,
+DTCE_PERIA_INTA233,DTCE_PERIA_INTA234,DTCE_PERIA_INTA235,DTCE_PERIA_INTA236,DTCE_PERIA_INTA237,
+DTCE_PERIA_INTA238,DTCE_PERIA_INTA239,DTCE_PERIA_INTA240,DTCE_PERIA_INTA241,DTCE_PERIA_INTA242,
+DTCE_PERIA_INTA243,DTCE_PERIA_INTA244,DTCE_PERIA_INTA245,DTCE_PERIA_INTA246,DTCE_PERIA_INTA247,
+DTCE_PERIA_INTA248,DTCE_PERIA_INTA249,DTCE_PERIA_INTA250,DTCE_PERIA_INTA251,DTCE_PERIA_INTA252,
+DTCE_PERIA_INTA253,DTCE_PERIA_INTA254,DTCE_PERIA_INTA255
+} enum_dtce_t;
+
+typedef enum enum_ier {
+IER_BSC_BUSERR=0x02,
+IER_RAM_RAMERR=0x02,
+IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02,
+IER_ICU_SWINT2=0x03,IER_ICU_SWINT=0x03,
+IER_CMT0_CMI0=0x03,
+IER_CMT1_CMI1=0x03,
+IER_CMTW0_CMWI0=0x03,
+IER_CMTW1_CMWI1=0x03,
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,
+IER_RSPI0_SPRI0=0x04,IER_RSPI0_SPTI0=0x04,
+IER_RSPI1_SPRI1=0x05,IER_RSPI1_SPTI1=0x05,
+IER_QSPI_SPRI=0x05,IER_QSPI_SPTI=0x05,
+IER_SDHI_SBFAI=0x05,
+IER_MMCIF_MBFAI=0x05,
+IER_RIIC1_RXI1=0x06,IER_RIIC1_TXI1=0x06,
+IER_RIIC0_RXI0=0x06,IER_RIIC0_TXI0=0x06,
+IER_RIIC2_RXI2=0x06,IER_RIIC2_TXI2=0x06,
+IER_SCI0_RXI0=0x07,IER_SCI0_TXI0=0x07,
+IER_SCI1_RXI1=0x07,IER_SCI1_TXI1=0x07,
+IER_SCI2_RXI2=0x07,IER_SCI2_TXI2=0x07,
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,
+IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09,
+IER_SCI3_RXI3=0x0A,IER_SCI3_TXI3=0x0A,
+IER_SCI4_RXI4=0x0A,IER_SCI4_TXI4=0x0A,
+IER_SCI5_RXI5=0x0A,IER_SCI5_TXI5=0x0A,
+IER_SCI6_RXI6=0x0A,IER_SCI6_TXI6=0x0A,
+IER_LVD1_LVD1=0x0B,
+IER_LVD2_LVD2=0x0B,
+IER_USB0_USBR0=0x0B,
+IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,
+IER_IWDT_IWUNI=0x0B,
+IER_WDT_WUNI=0x0C,
+IER_PDC_PCDFI=0x0C,
+IER_SCI7_RXI7=0x0C,IER_SCI7_TXI7=0x0C,
+IER_SCI8_RXI8=0x0C,IER_SCI8_TXI8=0x0C,
+IER_SCI9_RXI9=0x0C,IER_SCI9_TXI9=0x0C,
+IER_SCI10_RXI10=0x0D,IER_SCI10_TXI10=0x0D,
+IER_ICU_GROUPBE0=0x0D,IER_ICU_GROUPBL2=0x0D,
+IER_RSPI2_SPRI2=0x0D,IER_RSPI2_SPTI2=0x0D,
+IER_ICU_GROUPBL0=0x0D,IER_ICU_GROUPBL1=0x0D,IER_ICU_GROUPAL0=0x0E,IER_ICU_GROUPAL1=0x0E,
+IER_SCI11_RXI11=0x0E,IER_SCI11_TXI11=0x0E,
+IER_SCI12_RXI12=0x0E,IER_SCI12_TXI12=0x0E,
+IER_DMAC_DMAC0I=0x0F,IER_DMAC_DMAC1I=0x0F,IER_DMAC_DMAC2I=0x0F,IER_DMAC_DMAC3I=0x0F,IER_DMAC_DMAC74I=0x0F,
+IER_OST_OSTDI=0x0F,
+IER_EXDMAC_EXDMAC0I=0x0F,IER_EXDMAC_EXDMAC1I=0x0F,
+IER_PERIB_INTB128=0x10,IER_PERIB_INTB129=0x10,IER_PERIB_INTB130=0x10,IER_PERIB_INTB131=0x10,IER_PERIB_INTB132=0x10,
+IER_PERIB_INTB133=0x10,IER_PERIB_INTB134=0x10,IER_PERIB_INTB135=0x10,IER_PERIB_INTB136=0x11,IER_PERIB_INTB137=0x11,
+IER_PERIB_INTB138=0x11,IER_PERIB_INTB139=0x11,IER_PERIB_INTB140=0x11,IER_PERIB_INTB141=0x11,IER_PERIB_INTB142=0x11,
+IER_PERIB_INTB143=0x11,IER_PERIB_INTB144=0x12,IER_PERIB_INTB145=0x12,IER_PERIB_INTB146=0x12,IER_PERIB_INTB147=0x12,
+IER_PERIB_INTB148=0x12,IER_PERIB_INTB149=0x12,IER_PERIB_INTB150=0x12,IER_PERIB_INTB151=0x12,IER_PERIB_INTB152=0x13,
+IER_PERIB_INTB153=0x13,IER_PERIB_INTB154=0x13,IER_PERIB_INTB155=0x13,IER_PERIB_INTB156=0x13,IER_PERIB_INTB157=0x13,
+IER_PERIB_INTB158=0x13,IER_PERIB_INTB159=0x13,IER_PERIB_INTB160=0x14,IER_PERIB_INTB161=0x14,IER_PERIB_INTB162=0x14,
+IER_PERIB_INTB163=0x14,IER_PERIB_INTB164=0x14,IER_PERIB_INTB165=0x14,IER_PERIB_INTB166=0x14,IER_PERIB_INTB167=0x14,
+IER_PERIB_INTB168=0x15,IER_PERIB_INTB169=0x15,IER_PERIB_INTB170=0x15,IER_PERIB_INTB171=0x15,IER_PERIB_INTB172=0x15,
+IER_PERIB_INTB173=0x15,IER_PERIB_INTB174=0x15,IER_PERIB_INTB175=0x15,IER_PERIB_INTB176=0x16,IER_PERIB_INTB177=0x16,
+IER_PERIB_INTB178=0x16,IER_PERIB_INTB179=0x16,IER_PERIB_INTB180=0x16,IER_PERIB_INTB181=0x16,IER_PERIB_INTB182=0x16,
+IER_PERIB_INTB183=0x16,IER_PERIB_INTB184=0x17,IER_PERIB_INTB185=0x17,IER_PERIB_INTB186=0x17,IER_PERIB_INTB187=0x17,
+IER_PERIB_INTB188=0x17,IER_PERIB_INTB189=0x17,IER_PERIB_INTB190=0x17,IER_PERIB_INTB191=0x17,IER_PERIB_INTB192=0x18,
+IER_PERIB_INTB193=0x18,IER_PERIB_INTB194=0x18,IER_PERIB_INTB195=0x18,IER_PERIB_INTB196=0x18,IER_PERIB_INTB197=0x18,
+IER_PERIB_INTB198=0x18,IER_PERIB_INTB199=0x18,IER_PERIB_INTB200=0x19,IER_PERIB_INTB201=0x19,IER_PERIB_INTB202=0x19,
+IER_PERIB_INTB203=0x19,IER_PERIB_INTB204=0x19,IER_PERIB_INTB205=0x19,IER_PERIB_INTB206=0x19,IER_PERIB_INTB207=0x19,
+IER_PERIA_INTA208=0x1A,IER_PERIA_INTA209=0x1A,IER_PERIA_INTA210=0x1A,IER_PERIA_INTA211=0x1A,IER_PERIA_INTA212=0x1A,
+IER_PERIA_INTA213=0x1A,IER_PERIA_INTA214=0x1A,IER_PERIA_INTA215=0x1A,IER_PERIA_INTA216=0x1B,IER_PERIA_INTA217=0x1B,
+IER_PERIA_INTA218=0x1B,IER_PERIA_INTA219=0x1B,IER_PERIA_INTA220=0x1B,IER_PERIA_INTA221=0x1B,IER_PERIA_INTA222=0x1B,
+IER_PERIA_INTA223=0x1B,IER_PERIA_INTA224=0x1C,IER_PERIA_INTA225=0x1C,IER_PERIA_INTA226=0x1C,IER_PERIA_INTA227=0x1C,
+IER_PERIA_INTA228=0x1C,IER_PERIA_INTA229=0x1C,IER_PERIA_INTA230=0x1C,IER_PERIA_INTA231=0x1C,IER_PERIA_INTA232=0x1D,
+IER_PERIA_INTA233=0x1D,IER_PERIA_INTA234=0x1D,IER_PERIA_INTA235=0x1D,IER_PERIA_INTA236=0x1D,IER_PERIA_INTA237=0x1D,
+IER_PERIA_INTA238=0x1D,IER_PERIA_INTA239=0x1D,IER_PERIA_INTA240=0x1E,IER_PERIA_INTA241=0x1E,IER_PERIA_INTA242=0x1E,
+IER_PERIA_INTA243=0x1E,IER_PERIA_INTA244=0x1E,IER_PERIA_INTA245=0x1E,IER_PERIA_INTA246=0x1E,IER_PERIA_INTA247=0x1E,
+IER_PERIA_INTA248=0x1F,IER_PERIA_INTA249=0x1F,IER_PERIA_INTA250=0x1F,IER_PERIA_INTA251=0x1F,IER_PERIA_INTA252=0x1F,
+IER_PERIA_INTA253=0x1F,IER_PERIA_INTA254=0x1F,IER_PERIA_INTA255=0x1F
+} enum_ier_t;
+
+typedef enum enum_ipr {
+IPR_BSC_BUSERR=0,
+IPR_RAM_RAMERR=0,
+IPR_FCU_FIFERR=1,IPR_FCU_FRDYI=2,
+IPR_ICU_SWINT2=3,IPR_ICU_SWINT=3,
+IPR_CMT0_CMI0=4,
+IPR_CMT1_CMI1=5,
+IPR_CMTW0_CMWI0=6,
+IPR_CMTW1_CMWI1=7,
+IPR_USB0_D0FIFO0=34,IPR_USB0_D1FIFO0=35,
+IPR_RSPI0_SPRI0=38,IPR_RSPI0_SPTI0=39,
+IPR_RSPI1_SPRI1=40,IPR_RSPI1_SPTI1=41,
+IPR_QSPI_SPRI=42,IPR_QSPI_SPTI=43,
+IPR_SDHI_SBFAI=44,
+IPR_MMCIF_MBFAI=45,
+IPR_RIIC1_RXI1=50,IPR_RIIC1_TXI1=51,
+IPR_RIIC0_RXI0=52,IPR_RIIC0_TXI0=53,
+IPR_RIIC2_RXI2=54,IPR_RIIC2_TXI2=55,
+IPR_SCI0_RXI0=58,IPR_SCI0_TXI0=59,
+IPR_SCI1_RXI1=60,IPR_SCI1_TXI1=61,
+IPR_SCI2_RXI2=62,IPR_SCI2_TXI2=63,
+IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,
+IPR_ICU_IRQ8=72,IPR_ICU_IRQ9=73,IPR_ICU_IRQ10=74,IPR_ICU_IRQ11=75,IPR_ICU_IRQ12=76,IPR_ICU_IRQ13=77,IPR_ICU_IRQ14=78,IPR_ICU_IRQ15=79,
+IPR_SCI3_RXI3=80,IPR_SCI3_TXI3=81,
+IPR_SCI4_RXI4=82,IPR_SCI4_TXI4=83,
+IPR_SCI5_RXI5=84,IPR_SCI5_TXI5=85,
+IPR_SCI6_RXI6=86,IPR_SCI6_TXI6=87,
+IPR_LVD1_LVD1=88,
+IPR_LVD2_LVD2=89,
+IPR_USB0_USBR0=90,
+IPR_RTC_ALM=92,IPR_RTC_PRD=93,
+IPR_IWDT_IWUNI=95,
+IPR_WDT_WUNI=96,
+IPR_PDC_PCDFI=97,
+IPR_SCI7_RXI7=98,IPR_SCI7_TXI7=99,
+IPR_SCI8_RXI8=100,IPR_SCI8_TXI8=101,
+IPR_SCI9_RXI9=102,IPR_SCI9_TXI9=103,
+IPR_SCI10_RXI10=104,IPR_SCI10_TXI10=105,
+IPR_ICU_GROUPBE0=106,IPR_ICU_GROUPBL2=107,
+IPR_RSPI2_SPRI2=108,IPR_RSPI2_SPTI2=109,
+IPR_ICU_GROUPBL0=110,IPR_ICU_GROUPBL1=111,IPR_ICU_GROUPAL0=112,IPR_ICU_GROUPAL1=113,
+IPR_SCI11_RXI11=114,IPR_SCI11_TXI11=115,
+IPR_SCI12_RXI12=116,IPR_SCI12_TXI12=117,
+IPR_DMAC_DMAC0I=120,IPR_DMAC_DMAC1I=121,IPR_DMAC_DMAC2I=122,IPR_DMAC_DMAC3I=123,IPR_DMAC_DMAC74I=124,
+IPR_OST_OSTDI=125,
+IPR_EXDMAC_EXDMAC0I=126,IPR_EXDMAC_EXDMAC1I=127,
+IPR_PERIB_INTB128=128,IPR_PERIB_INTB129=129,IPR_PERIB_INTB130=130,IPR_PERIB_INTB131=131,IPR_PERIB_INTB132=132,
+IPR_PERIB_INTB133=133,IPR_PERIB_INTB134=134,IPR_PERIB_INTB135=135,IPR_PERIB_INTB136=136,IPR_PERIB_INTB137=137,
+IPR_PERIB_INTB138=138,IPR_PERIB_INTB139=139,IPR_PERIB_INTB140=140,IPR_PERIB_INTB141=141,IPR_PERIB_INTB142=142,
+IPR_PERIB_INTB143=143,IPR_PERIB_INTB144=144,IPR_PERIB_INTB145=145,IPR_PERIB_INTB146=146,IPR_PERIB_INTB147=147,
+IPR_PERIB_INTB148=148,IPR_PERIB_INTB149=149,IPR_PERIB_INTB150=150,IPR_PERIB_INTB151=151,IPR_PERIB_INTB152=152,
+IPR_PERIB_INTB153=153,IPR_PERIB_INTB154=154,IPR_PERIB_INTB155=155,IPR_PERIB_INTB156=156,IPR_PERIB_INTB157=157,
+IPR_PERIB_INTB158=158,IPR_PERIB_INTB159=159,IPR_PERIB_INTB160=160,IPR_PERIB_INTB161=161,IPR_PERIB_INTB162=162,
+IPR_PERIB_INTB163=163,IPR_PERIB_INTB164=164,IPR_PERIB_INTB165=165,IPR_PERIB_INTB166=166,IPR_PERIB_INTB167=167,
+IPR_PERIB_INTB168=168,IPR_PERIB_INTB169=169,IPR_PERIB_INTB170=170,IPR_PERIB_INTB171=171,IPR_PERIB_INTB172=172,
+IPR_PERIB_INTB173=173,IPR_PERIB_INTB174=174,IPR_PERIB_INTB175=175,IPR_PERIB_INTB176=176,IPR_PERIB_INTB177=177,
+IPR_PERIB_INTB178=178,IPR_PERIB_INTB179=179,IPR_PERIB_INTB180=180,IPR_PERIB_INTB181=181,IPR_PERIB_INTB182=182,
+IPR_PERIB_INTB183=183,IPR_PERIB_INTB184=184,IPR_PERIB_INTB185=185,IPR_PERIB_INTB186=186,IPR_PERIB_INTB187=187,
+IPR_PERIB_INTB188=188,IPR_PERIB_INTB189=189,IPR_PERIB_INTB190=190,IPR_PERIB_INTB191=191,IPR_PERIB_INTB192=192,
+IPR_PERIB_INTB193=193,IPR_PERIB_INTB194=194,IPR_PERIB_INTB195=195,IPR_PERIB_INTB196=196,IPR_PERIB_INTB197=197,
+IPR_PERIB_INTB198=198,IPR_PERIB_INTB199=199,IPR_PERIB_INTB200=200,IPR_PERIB_INTB201=201,IPR_PERIB_INTB202=202,
+IPR_PERIB_INTB203=203,IPR_PERIB_INTB204=204,IPR_PERIB_INTB205=205,IPR_PERIB_INTB206=206,IPR_PERIB_INTB207=207,
+IPR_PERIA_INTA208=208,IPR_PERIA_INTA209=209,IPR_PERIA_INTA210=210,IPR_PERIA_INTA211=211,IPR_PERIA_INTA212=212,
+IPR_PERIA_INTA213=213,IPR_PERIA_INTA214=214,IPR_PERIA_INTA215=215,IPR_PERIA_INTA216=216,IPR_PERIA_INTA217=217,
+IPR_PERIA_INTA218=218,IPR_PERIA_INTA219=219,IPR_PERIA_INTA220=220,IPR_PERIA_INTA221=221,IPR_PERIA_INTA222=222,
+IPR_PERIA_INTA223=223,IPR_PERIA_INTA224=224,IPR_PERIA_INTA225=225,IPR_PERIA_INTA226=226,IPR_PERIA_INTA227=227,
+IPR_PERIA_INTA228=228,IPR_PERIA_INTA229=229,IPR_PERIA_INTA230=230,IPR_PERIA_INTA231=231,IPR_PERIA_INTA232=232,
+IPR_PERIA_INTA233=233,IPR_PERIA_INTA234=234,IPR_PERIA_INTA235=235,IPR_PERIA_INTA236=236,IPR_PERIA_INTA237=237,
+IPR_PERIA_INTA238=238,IPR_PERIA_INTA239=239,IPR_PERIA_INTA240=240,IPR_PERIA_INTA241=241,IPR_PERIA_INTA242=242,
+IPR_PERIA_INTA243=243,IPR_PERIA_INTA244=244,IPR_PERIA_INTA245=245,IPR_PERIA_INTA246=246,IPR_PERIA_INTA247=247,
+IPR_PERIA_INTA248=248,IPR_PERIA_INTA249=249,IPR_PERIA_INTA250=250,IPR_PERIA_INTA251=251,IPR_PERIA_INTA252=252,
+IPR_PERIA_INTA253=253,IPR_PERIA_INTA254=254,IPR_PERIA_INTA255=255,
+IPR_ICU_SWI=3,
+IPR_CMT0_=4,
+IPR_CMT1_=5,
+IPR_CMTW0_=6,
+IPR_CMTW1_=7,
+IPR_SDHI_=44,
+IPR_MMCIF_=45,
+IPR_LVD1_=88,
+IPR_LVD2_=89,
+IPR_IWDT_=95,
+IPR_WDT_=96,
+IPR_PDC_=97,
+IPR_OST_=125
+} enum_ipr_t;
+
+
+#pragma pack(4)
+
+
+typedef struct st_bsc {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char STSCLR : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char STSCLR : 1;
+#endif
+	} BIT;
+	} BERCLR;
+	char           wk0[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IGAEN : 1;
+			unsigned char TOEN : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char TOEN : 1;
+			unsigned char IGAEN : 1;
+#endif
+	} BIT;
+	} BEREN;
+	char           wk1[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IA : 1;
+			unsigned char TO : 1;
+			unsigned char  : 2;
+			unsigned char MST : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char MST : 3;
+			unsigned char  : 2;
+			unsigned char TO : 1;
+			unsigned char IA : 1;
+#endif
+	} BIT;
+	} BERSR1;
+	char           wk2[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 3;
+			unsigned short ADDR : 13;
+#else
+			unsigned short ADDR : 13;
+			unsigned short  : 3;
+#endif
+	} BIT;
+	} BERSR2;
+	char           wk3[4];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short BPRA : 2;
+			unsigned short BPRO : 2;
+			unsigned short BPIB : 2;
+			unsigned short BPGB : 2;
+			unsigned short BPHB : 2;
+			unsigned short BPFB : 2;
+			unsigned short BPEB : 2;
+			unsigned short  : 2;
+#else
+			unsigned short  : 2;
+			unsigned short BPEB : 2;
+			unsigned short BPFB : 2;
+			unsigned short BPHB : 2;
+			unsigned short BPGB : 2;
+			unsigned short BPIB : 2;
+			unsigned short BPRO : 2;
+			unsigned short BPRA : 2;
+#endif
+	} BIT;
+	} BUSPRI;
+	char           wk4[7408];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short WRMOD : 1;
+			unsigned short  : 2;
+			unsigned short EWENB : 1;
+			unsigned short  : 4;
+			unsigned short PRENB : 1;
+			unsigned short PWENB : 1;
+			unsigned short  : 5;
+			unsigned short PRMOD : 1;
+#else
+			unsigned short PRMOD : 1;
+			unsigned short  : 5;
+			unsigned short PWENB : 1;
+			unsigned short PRENB : 1;
+			unsigned short  : 4;
+			unsigned short EWENB : 1;
+			unsigned short  : 2;
+			unsigned short WRMOD : 1;
+#endif
+	} BIT;
+	} CS0MOD;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSPWWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPWWAIT : 3;
+#endif
+	} BIT;
+	} CS0WCR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSROFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long AWAIT : 2;
+			unsigned long  : 2;
+			unsigned long RDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long RDON : 3;
+			unsigned long  : 2;
+			unsigned long AWAIT : 2;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSROFF : 3;
+#endif
+	} BIT;
+	} CS0WCR2;
+	char           wk5[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short WRMOD : 1;
+			unsigned short  : 2;
+			unsigned short EWENB : 1;
+			unsigned short  : 4;
+			unsigned short PRENB : 1;
+			unsigned short PWENB : 1;
+			unsigned short  : 5;
+			unsigned short PRMOD : 1;
+#else
+			unsigned short PRMOD : 1;
+			unsigned short  : 5;
+			unsigned short PWENB : 1;
+			unsigned short PRENB : 1;
+			unsigned short  : 4;
+			unsigned short EWENB : 1;
+			unsigned short  : 2;
+			unsigned short WRMOD : 1;
+#endif
+	} BIT;
+	} CS1MOD;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSPWWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPWWAIT : 3;
+#endif
+	} BIT;
+	} CS1WCR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSROFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long AWAIT : 2;
+			unsigned long  : 2;
+			unsigned long RDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long RDON : 3;
+			unsigned long  : 2;
+			unsigned long AWAIT : 2;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSROFF : 3;
+#endif
+	} BIT;
+	} CS1WCR2;
+	char           wk6[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short WRMOD : 1;
+			unsigned short  : 2;
+			unsigned short EWENB : 1;
+			unsigned short  : 4;
+			unsigned short PRENB : 1;
+			unsigned short PWENB : 1;
+			unsigned short  : 5;
+			unsigned short PRMOD : 1;
+#else
+			unsigned short PRMOD : 1;
+			unsigned short  : 5;
+			unsigned short PWENB : 1;
+			unsigned short PRENB : 1;
+			unsigned short  : 4;
+			unsigned short EWENB : 1;
+			unsigned short  : 2;
+			unsigned short WRMOD : 1;
+#endif
+	} BIT;
+	} CS2MOD;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSPWWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPWWAIT : 3;
+#endif
+	} BIT;
+	} CS2WCR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSROFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long AWAIT : 2;
+			unsigned long  : 2;
+			unsigned long RDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long RDON : 3;
+			unsigned long  : 2;
+			unsigned long AWAIT : 2;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSROFF : 3;
+#endif
+	} BIT;
+	} CS2WCR2;
+	char           wk7[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short WRMOD : 1;
+			unsigned short  : 2;
+			unsigned short EWENB : 1;
+			unsigned short  : 4;
+			unsigned short PRENB : 1;
+			unsigned short PWENB : 1;
+			unsigned short  : 5;
+			unsigned short PRMOD : 1;
+#else
+			unsigned short PRMOD : 1;
+			unsigned short  : 5;
+			unsigned short PWENB : 1;
+			unsigned short PRENB : 1;
+			unsigned short  : 4;
+			unsigned short EWENB : 1;
+			unsigned short  : 2;
+			unsigned short WRMOD : 1;
+#endif
+	} BIT;
+	} CS3MOD;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSPWWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPWWAIT : 3;
+#endif
+	} BIT;
+	} CS3WCR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSROFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long AWAIT : 2;
+			unsigned long  : 2;
+			unsigned long RDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long RDON : 3;
+			unsigned long  : 2;
+			unsigned long AWAIT : 2;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSROFF : 3;
+#endif
+	} BIT;
+	} CS3WCR2;
+	char           wk8[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short WRMOD : 1;
+			unsigned short  : 2;
+			unsigned short EWENB : 1;
+			unsigned short  : 4;
+			unsigned short PRENB : 1;
+			unsigned short PWENB : 1;
+			unsigned short  : 5;
+			unsigned short PRMOD : 1;
+#else
+			unsigned short PRMOD : 1;
+			unsigned short  : 5;
+			unsigned short PWENB : 1;
+			unsigned short PRENB : 1;
+			unsigned short  : 4;
+			unsigned short EWENB : 1;
+			unsigned short  : 2;
+			unsigned short WRMOD : 1;
+#endif
+	} BIT;
+	} CS4MOD;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSPWWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPWWAIT : 3;
+#endif
+	} BIT;
+	} CS4WCR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSROFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long AWAIT : 2;
+			unsigned long  : 2;
+			unsigned long RDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long RDON : 3;
+			unsigned long  : 2;
+			unsigned long AWAIT : 2;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSROFF : 3;
+#endif
+	} BIT;
+	} CS4WCR2;
+	char           wk9[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short WRMOD : 1;
+			unsigned short  : 2;
+			unsigned short EWENB : 1;
+			unsigned short  : 4;
+			unsigned short PRENB : 1;
+			unsigned short PWENB : 1;
+			unsigned short  : 5;
+			unsigned short PRMOD : 1;
+#else
+			unsigned short PRMOD : 1;
+			unsigned short  : 5;
+			unsigned short PWENB : 1;
+			unsigned short PRENB : 1;
+			unsigned short  : 4;
+			unsigned short EWENB : 1;
+			unsigned short  : 2;
+			unsigned short WRMOD : 1;
+#endif
+	} BIT;
+	} CS5MOD;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSPWWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPWWAIT : 3;
+#endif
+	} BIT;
+	} CS5WCR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSROFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long AWAIT : 2;
+			unsigned long  : 2;
+			unsigned long RDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long RDON : 3;
+			unsigned long  : 2;
+			unsigned long AWAIT : 2;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSROFF : 3;
+#endif
+	} BIT;
+	} CS5WCR2;
+	char           wk10[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short WRMOD : 1;
+			unsigned short  : 2;
+			unsigned short EWENB : 1;
+			unsigned short  : 4;
+			unsigned short PRENB : 1;
+			unsigned short PWENB : 1;
+			unsigned short  : 5;
+			unsigned short PRMOD : 1;
+#else
+			unsigned short PRMOD : 1;
+			unsigned short  : 5;
+			unsigned short PWENB : 1;
+			unsigned short PRENB : 1;
+			unsigned short  : 4;
+			unsigned short EWENB : 1;
+			unsigned short  : 2;
+			unsigned short WRMOD : 1;
+#endif
+	} BIT;
+	} CS6MOD;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSPWWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPWWAIT : 3;
+#endif
+	} BIT;
+	} CS6WCR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSROFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long AWAIT : 2;
+			unsigned long  : 2;
+			unsigned long RDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long RDON : 3;
+			unsigned long  : 2;
+			unsigned long AWAIT : 2;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSROFF : 3;
+#endif
+	} BIT;
+	} CS6WCR2;
+	char           wk11[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short WRMOD : 1;
+			unsigned short  : 2;
+			unsigned short EWENB : 1;
+			unsigned short  : 4;
+			unsigned short PRENB : 1;
+			unsigned short PWENB : 1;
+			unsigned short  : 5;
+			unsigned short PRMOD : 1;
+#else
+			unsigned short PRMOD : 1;
+			unsigned short  : 5;
+			unsigned short PWENB : 1;
+			unsigned short PRENB : 1;
+			unsigned short  : 4;
+			unsigned short EWENB : 1;
+			unsigned short  : 2;
+			unsigned short WRMOD : 1;
+#endif
+	} BIT;
+	} CS7MOD;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSPWWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long CSRWAIT : 5;
+			unsigned long  : 3;
+			unsigned long CSWWAIT : 5;
+			unsigned long  : 5;
+			unsigned long CSPRWAIT : 3;
+			unsigned long  : 5;
+			unsigned long CSPWWAIT : 3;
+#endif
+	} BIT;
+	} CS7WCR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CSROFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long AWAIT : 2;
+			unsigned long  : 2;
+			unsigned long RDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long CSON : 3;
+			unsigned long  : 1;
+			unsigned long WDON : 3;
+			unsigned long  : 1;
+			unsigned long WRON : 3;
+			unsigned long  : 1;
+			unsigned long RDON : 3;
+			unsigned long  : 2;
+			unsigned long AWAIT : 2;
+			unsigned long  : 1;
+			unsigned long WDOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSWOFF : 3;
+			unsigned long  : 1;
+			unsigned long CSROFF : 3;
+#endif
+	} BIT;
+	} CS7WCR2;
+	char           wk12[1926];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short EXENB : 1;
+			unsigned short  : 3;
+			unsigned short BSIZE : 2;
+			unsigned short  : 2;
+			unsigned short EMODE : 1;
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+			unsigned short EMODE : 1;
+			unsigned short  : 2;
+			unsigned short BSIZE : 2;
+			unsigned short  : 3;
+			unsigned short EXENB : 1;
+#endif
+	} BIT;
+	} CS0CR;
+	char           wk13[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RRCV : 4;
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+			unsigned short RRCV : 4;
+#endif
+	} BIT;
+	} CS0REC;
+	char           wk14[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short EXENB : 1;
+			unsigned short  : 3;
+			unsigned short BSIZE : 2;
+			unsigned short  : 2;
+			unsigned short EMODE : 1;
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+			unsigned short EMODE : 1;
+			unsigned short  : 2;
+			unsigned short BSIZE : 2;
+			unsigned short  : 3;
+			unsigned short EXENB : 1;
+#endif
+	} BIT;
+	} CS1CR;
+	char           wk15[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RRCV : 4;
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+			unsigned short RRCV : 4;
+#endif
+	} BIT;
+	} CS1REC;
+	char           wk16[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short EXENB : 1;
+			unsigned short  : 3;
+			unsigned short BSIZE : 2;
+			unsigned short  : 2;
+			unsigned short EMODE : 1;
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+			unsigned short EMODE : 1;
+			unsigned short  : 2;
+			unsigned short BSIZE : 2;
+			unsigned short  : 3;
+			unsigned short EXENB : 1;
+#endif
+	} BIT;
+	} CS2CR;
+	char           wk17[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RRCV : 4;
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+			unsigned short RRCV : 4;
+#endif
+	} BIT;
+	} CS2REC;
+	char           wk18[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short EXENB : 1;
+			unsigned short  : 3;
+			unsigned short BSIZE : 2;
+			unsigned short  : 2;
+			unsigned short EMODE : 1;
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+			unsigned short EMODE : 1;
+			unsigned short  : 2;
+			unsigned short BSIZE : 2;
+			unsigned short  : 3;
+			unsigned short EXENB : 1;
+#endif
+	} BIT;
+	} CS3CR;
+	char           wk19[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RRCV : 4;
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+			unsigned short RRCV : 4;
+#endif
+	} BIT;
+	} CS3REC;
+	char           wk20[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short EXENB : 1;
+			unsigned short  : 3;
+			unsigned short BSIZE : 2;
+			unsigned short  : 2;
+			unsigned short EMODE : 1;
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+			unsigned short EMODE : 1;
+			unsigned short  : 2;
+			unsigned short BSIZE : 2;
+			unsigned short  : 3;
+			unsigned short EXENB : 1;
+#endif
+	} BIT;
+	} CS4CR;
+	char           wk21[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RRCV : 4;
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+			unsigned short RRCV : 4;
+#endif
+	} BIT;
+	} CS4REC;
+	char           wk22[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short EXENB : 1;
+			unsigned short  : 3;
+			unsigned short BSIZE : 2;
+			unsigned short  : 2;
+			unsigned short EMODE : 1;
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+			unsigned short EMODE : 1;
+			unsigned short  : 2;
+			unsigned short BSIZE : 2;
+			unsigned short  : 3;
+			unsigned short EXENB : 1;
+#endif
+	} BIT;
+	} CS5CR;
+	char           wk23[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RRCV : 4;
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+			unsigned short RRCV : 4;
+#endif
+	} BIT;
+	} CS5REC;
+	char           wk24[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short EXENB : 1;
+			unsigned short  : 3;
+			unsigned short BSIZE : 2;
+			unsigned short  : 2;
+			unsigned short EMODE : 1;
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+			unsigned short EMODE : 1;
+			unsigned short  : 2;
+			unsigned short BSIZE : 2;
+			unsigned short  : 3;
+			unsigned short EXENB : 1;
+#endif
+	} BIT;
+	} CS6CR;
+	char           wk25[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RRCV : 4;
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+			unsigned short RRCV : 4;
+#endif
+	} BIT;
+	} CS6REC;
+	char           wk26[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short EXENB : 1;
+			unsigned short  : 3;
+			unsigned short BSIZE : 2;
+			unsigned short  : 2;
+			unsigned short EMODE : 1;
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short MPXEN : 1;
+			unsigned short  : 3;
+			unsigned short EMODE : 1;
+			unsigned short  : 2;
+			unsigned short BSIZE : 2;
+			unsigned short  : 3;
+			unsigned short EXENB : 1;
+#endif
+	} BIT;
+	} CS7CR;
+	char           wk27[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RRCV : 4;
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short WRCV : 4;
+			unsigned short  : 4;
+			unsigned short RRCV : 4;
+#endif
+	} BIT;
+	} CS7REC;
+	char           wk28[4];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RCVEN0 : 1;
+			unsigned short RCVEN1 : 1;
+			unsigned short RCVEN2 : 1;
+			unsigned short RCVEN3 : 1;
+			unsigned short RCVEN4 : 1;
+			unsigned short RCVEN5 : 1;
+			unsigned short RCVEN6 : 1;
+			unsigned short RCVEN7 : 1;
+			unsigned short RCVENM0 : 1;
+			unsigned short RCVENM1 : 1;
+			unsigned short RCVENM2 : 1;
+			unsigned short RCVENM3 : 1;
+			unsigned short RCVENM4 : 1;
+			unsigned short RCVENM5 : 1;
+			unsigned short RCVENM6 : 1;
+			unsigned short RCVENM7 : 1;
+#else
+			unsigned short RCVENM7 : 1;
+			unsigned short RCVENM6 : 1;
+			unsigned short RCVENM5 : 1;
+			unsigned short RCVENM4 : 1;
+			unsigned short RCVENM3 : 1;
+			unsigned short RCVENM2 : 1;
+			unsigned short RCVENM1 : 1;
+			unsigned short RCVENM0 : 1;
+			unsigned short RCVEN7 : 1;
+			unsigned short RCVEN6 : 1;
+			unsigned short RCVEN5 : 1;
+			unsigned short RCVEN4 : 1;
+			unsigned short RCVEN3 : 1;
+			unsigned short RCVEN2 : 1;
+			unsigned short RCVEN1 : 1;
+			unsigned short RCVEN0 : 1;
+#endif
+	} BIT;
+	} CSRECEN;
+	char           wk29[894];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char EXENB : 1;
+			unsigned char  : 3;
+			unsigned char BSIZE : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char BSIZE : 2;
+			unsigned char  : 3;
+			unsigned char EXENB : 1;
+#endif
+	} BIT;
+	} SDCCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char EMODE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char EMODE : 1;
+#endif
+	} BIT;
+	} SDCMOD;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char BE : 1;
+#endif
+	} BIT;
+	} SDAMOD;
+	char           wk30[13];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SFEN : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char SFEN : 1;
+#endif
+	} BIT;
+	} SDSELF;
+	char           wk31[3];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RFC : 12;
+			unsigned short REFW : 4;
+#else
+			unsigned short REFW : 4;
+			unsigned short RFC : 12;
+#endif
+	} BIT;
+	} SDRFCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RFEN : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char RFEN : 1;
+#endif
+	} BIT;
+	} SDRFEN;
+	char           wk32[9];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char INIRQ : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char INIRQ : 1;
+#endif
+	} BIT;
+	} SDICR;
+	char           wk33[3];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ARFI : 4;
+			unsigned short ARFC : 4;
+			unsigned short PRC : 3;
+			unsigned short  : 5;
+#else
+			unsigned short  : 5;
+			unsigned short PRC : 3;
+			unsigned short ARFC : 4;
+			unsigned short ARFI : 4;
+#endif
+	} BIT;
+	} SDIR;
+	char           wk34[26];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MXC : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char MXC : 2;
+#endif
+	} BIT;
+	} SDADR;
+	char           wk35[3];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CL : 3;
+			unsigned long  : 5;
+			unsigned long WR : 1;
+			unsigned long RP : 3;
+			unsigned long RCD : 2;
+			unsigned long  : 2;
+			unsigned long RAS : 3;
+			unsigned long  : 13;
+#else
+			unsigned long  : 13;
+			unsigned long RAS : 3;
+			unsigned long  : 2;
+			unsigned long RCD : 2;
+			unsigned long RP : 3;
+			unsigned long WR : 1;
+			unsigned long  : 5;
+			unsigned long CL : 3;
+#endif
+	} BIT;
+	} SDTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short MR : 15;
+			unsigned short  : 1;
+#else
+			unsigned short  : 1;
+			unsigned short MR : 15;
+#endif
+	} BIT;
+	} SDMOD;
+	char           wk36[6];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MRSST : 1;
+			unsigned char  : 2;
+			unsigned char INIST : 1;
+			unsigned char SRFST : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char SRFST : 1;
+			unsigned char INIST : 1;
+			unsigned char  : 2;
+			unsigned char MRSST : 1;
+#endif
+	} BIT;
+	} SDSR;
+	char           wk37[269231];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PR1SEL : 3;
+			unsigned long  : 1;
+			unsigned long PR2SEL : 3;
+			unsigned long  : 1;
+			unsigned long PR3SEL : 3;
+			unsigned long  : 1;
+			unsigned long PR4SEL : 3;
+			unsigned long  : 1;
+			unsigned long PR5SEL : 3;
+			unsigned long  : 10;
+			unsigned long RPSTOP : 1;
+			unsigned long  : 1;
+			unsigned long PRERR : 1;
+#else
+			unsigned long PRERR : 1;
+			unsigned long  : 1;
+			unsigned long RPSTOP : 1;
+			unsigned long  : 10;
+			unsigned long PR5SEL : 3;
+			unsigned long  : 1;
+			unsigned long PR4SEL : 3;
+			unsigned long  : 1;
+			unsigned long PR3SEL : 3;
+			unsigned long  : 1;
+			unsigned long PR2SEL : 3;
+			unsigned long  : 1;
+			unsigned long PR1SEL : 3;
+#endif
+	} BIT;
+	} EBMAPCR;
+} st_bsc_t;
+
+typedef struct st_cac {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CFME : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char CFME : 1;
+#endif
+	} BIT;
+	} CACR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CACREFE : 1;
+			unsigned char FMCS : 3;
+			unsigned char TCSS : 2;
+			unsigned char EDGES : 2;
+#else
+			unsigned char EDGES : 2;
+			unsigned char TCSS : 2;
+			unsigned char FMCS : 3;
+			unsigned char CACREFE : 1;
+#endif
+	} BIT;
+	} CACR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RPS : 1;
+			unsigned char RSCS : 3;
+			unsigned char RCDS : 2;
+			unsigned char DFS : 2;
+#else
+			unsigned char DFS : 2;
+			unsigned char RCDS : 2;
+			unsigned char RSCS : 3;
+			unsigned char RPS : 1;
+#endif
+	} BIT;
+	} CACR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char FERRIE : 1;
+			unsigned char MENDIE : 1;
+			unsigned char OVFIE : 1;
+			unsigned char  : 1;
+			unsigned char FERRFCL : 1;
+			unsigned char MENDFCL : 1;
+			unsigned char OVFFCL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char OVFFCL : 1;
+			unsigned char MENDFCL : 1;
+			unsigned char FERRFCL : 1;
+			unsigned char  : 1;
+			unsigned char OVFIE : 1;
+			unsigned char MENDIE : 1;
+			unsigned char FERRIE : 1;
+#endif
+	} BIT;
+	} CAICR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char FERRF : 1;
+			unsigned char MENDF : 1;
+			unsigned char OVFF : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char OVFF : 1;
+			unsigned char MENDF : 1;
+			unsigned char FERRF : 1;
+#endif
+	} BIT;
+	} CASTR;
+	char           wk0[1];
+	unsigned short CAULVR;
+	unsigned short CALLVR;
+	unsigned short CACNTBR;
+} st_cac_t;
+
+typedef struct st_can {
+	struct {
+		union {
+			unsigned long LONG;
+			struct {
+				unsigned short H;
+				unsigned short L;
+			} WORD;
+			struct {
+				unsigned char HH;
+				unsigned char HL;
+				unsigned char LH;
+				unsigned char LL;
+			} BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EID : 18;
+			unsigned long SID : 11;
+			unsigned long  : 1;
+			unsigned long RTR : 1;
+			unsigned long IDE : 1;
+#else
+			unsigned long IDE : 1;
+			unsigned long RTR : 1;
+			unsigned long  : 1;
+			unsigned long SID : 11;
+			unsigned long EID : 18;
+#endif
+	} BIT;
+		} ID;
+		unsigned short DLC;
+		unsigned char  DATA[8];
+		unsigned short TS;
+	} MB[32];
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned short H;
+			unsigned short L;
+		} WORD;
+		struct {
+			unsigned char HH;
+			unsigned char HL;
+			unsigned char LH;
+			unsigned char LL;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EID : 18;
+			unsigned long SID : 11;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long SID : 11;
+			unsigned long EID : 18;
+#endif
+	} BIT;
+	} MKR[8];
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned short H;
+			unsigned short L;
+		} WORD;
+		struct {
+			unsigned char HH;
+			unsigned char HL;
+			unsigned char LH;
+			unsigned char LL;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EID : 18;
+			unsigned long SID : 11;
+			unsigned long  : 1;
+			unsigned long RTR : 1;
+			unsigned long IDE : 1;
+#else
+			unsigned long IDE : 1;
+			unsigned long RTR : 1;
+			unsigned long  : 1;
+			unsigned long SID : 11;
+			unsigned long EID : 18;
+#endif
+	} BIT;
+	} FIDCR0;
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned short H;
+			unsigned short L;
+		} WORD;
+		struct {
+			unsigned char HH;
+			unsigned char HL;
+			unsigned char LH;
+			unsigned char LL;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EID : 18;
+			unsigned long SID : 11;
+			unsigned long  : 1;
+			unsigned long RTR : 1;
+			unsigned long IDE : 1;
+#else
+			unsigned long IDE : 1;
+			unsigned long RTR : 1;
+			unsigned long  : 1;
+			unsigned long SID : 11;
+			unsigned long EID : 18;
+#endif
+	} BIT;
+	} FIDCR1;
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned short H;
+			unsigned short L;
+		} WORD;
+		struct {
+			unsigned char HH;
+			unsigned char HL;
+			unsigned char LH;
+			unsigned char LL;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MB0 : 1;
+			unsigned long MB1 : 1;
+			unsigned long MB2 : 1;
+			unsigned long MB3 : 1;
+			unsigned long MB4 : 1;
+			unsigned long MB5 : 1;
+			unsigned long MB6 : 1;
+			unsigned long MB7 : 1;
+			unsigned long MB8 : 1;
+			unsigned long MB9 : 1;
+			unsigned long MB10 : 1;
+			unsigned long MB11 : 1;
+			unsigned long MB12 : 1;
+			unsigned long MB13 : 1;
+			unsigned long MB14 : 1;
+			unsigned long MB15 : 1;
+			unsigned long MB16 : 1;
+			unsigned long MB17 : 1;
+			unsigned long MB18 : 1;
+			unsigned long MB19 : 1;
+			unsigned long MB20 : 1;
+			unsigned long MB21 : 1;
+			unsigned long MB22 : 1;
+			unsigned long MB23 : 1;
+			unsigned long MB24 : 1;
+			unsigned long MB25 : 1;
+			unsigned long MB26 : 1;
+			unsigned long MB27 : 1;
+			unsigned long MB28 : 1;
+			unsigned long MB29 : 1;
+			unsigned long MB30 : 1;
+			unsigned long MB31 : 1;
+#else
+			unsigned long MB31 : 1;
+			unsigned long MB30 : 1;
+			unsigned long MB29 : 1;
+			unsigned long MB28 : 1;
+			unsigned long MB27 : 1;
+			unsigned long MB26 : 1;
+			unsigned long MB25 : 1;
+			unsigned long MB24 : 1;
+			unsigned long MB23 : 1;
+			unsigned long MB22 : 1;
+			unsigned long MB21 : 1;
+			unsigned long MB20 : 1;
+			unsigned long MB19 : 1;
+			unsigned long MB18 : 1;
+			unsigned long MB17 : 1;
+			unsigned long MB16 : 1;
+			unsigned long MB15 : 1;
+			unsigned long MB14 : 1;
+			unsigned long MB13 : 1;
+			unsigned long MB12 : 1;
+			unsigned long MB11 : 1;
+			unsigned long MB10 : 1;
+			unsigned long MB9 : 1;
+			unsigned long MB8 : 1;
+			unsigned long MB7 : 1;
+			unsigned long MB6 : 1;
+			unsigned long MB5 : 1;
+			unsigned long MB4 : 1;
+			unsigned long MB3 : 1;
+			unsigned long MB2 : 1;
+			unsigned long MB1 : 1;
+			unsigned long MB0 : 1;
+#endif
+	} BIT;
+	} MKIVLR;
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned short H;
+			unsigned short L;
+		} WORD;
+		struct {
+			unsigned char HH;
+			unsigned char HL;
+			unsigned char LH;
+			unsigned char LL;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MB0 : 1;
+			unsigned long MB1 : 1;
+			unsigned long MB2 : 1;
+			unsigned long MB3 : 1;
+			unsigned long MB4 : 1;
+			unsigned long MB5 : 1;
+			unsigned long MB6 : 1;
+			unsigned long MB7 : 1;
+			unsigned long MB8 : 1;
+			unsigned long MB9 : 1;
+			unsigned long MB10 : 1;
+			unsigned long MB11 : 1;
+			unsigned long MB12 : 1;
+			unsigned long MB13 : 1;
+			unsigned long MB14 : 1;
+			unsigned long MB15 : 1;
+			unsigned long MB16 : 1;
+			unsigned long MB17 : 1;
+			unsigned long MB18 : 1;
+			unsigned long MB19 : 1;
+			unsigned long MB20 : 1;
+			unsigned long MB21 : 1;
+			unsigned long MB22 : 1;
+			unsigned long MB23 : 1;
+			unsigned long MB24 : 1;
+			unsigned long MB25 : 1;
+			unsigned long MB26 : 1;
+			unsigned long MB27 : 1;
+			unsigned long MB28 : 1;
+			unsigned long MB29 : 1;
+			unsigned long MB30 : 1;
+			unsigned long MB31 : 1;
+#else
+			unsigned long MB31 : 1;
+			unsigned long MB30 : 1;
+			unsigned long MB29 : 1;
+			unsigned long MB28 : 1;
+			unsigned long MB27 : 1;
+			unsigned long MB26 : 1;
+			unsigned long MB25 : 1;
+			unsigned long MB24 : 1;
+			unsigned long MB23 : 1;
+			unsigned long MB22 : 1;
+			unsigned long MB21 : 1;
+			unsigned long MB20 : 1;
+			unsigned long MB19 : 1;
+			unsigned long MB18 : 1;
+			unsigned long MB17 : 1;
+			unsigned long MB16 : 1;
+			unsigned long MB15 : 1;
+			unsigned long MB14 : 1;
+			unsigned long MB13 : 1;
+			unsigned long MB12 : 1;
+			unsigned long MB11 : 1;
+			unsigned long MB10 : 1;
+			unsigned long MB9 : 1;
+			unsigned long MB8 : 1;
+			unsigned long MB7 : 1;
+			unsigned long MB6 : 1;
+			unsigned long MB5 : 1;
+			unsigned long MB4 : 1;
+			unsigned long MB3 : 1;
+			unsigned long MB2 : 1;
+			unsigned long MB1 : 1;
+			unsigned long MB0 : 1;
+#endif
+	} BIT;
+	} MIER;
+	char           wk0[1008];
+	union {
+		unsigned char BYTE;
+		union {
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SENTDATA : 1;
+			unsigned char TRMACTIVE : 1;
+			unsigned char TRMABT : 1;
+			unsigned char  : 1;
+			unsigned char ONESHOT : 1;
+			unsigned char  : 1;
+			unsigned char RECREQ : 1;
+			unsigned char TRMREQ : 1;
+#else
+			unsigned char TRMREQ : 1;
+			unsigned char RECREQ : 1;
+			unsigned char  : 1;
+			unsigned char ONESHOT : 1;
+			unsigned char  : 1;
+			unsigned char TRMABT : 1;
+			unsigned char TRMACTIVE : 1;
+			unsigned char SENTDATA : 1;
+#endif
+	} TX;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NEWDATA : 1;
+			unsigned char INVALDATA : 1;
+			unsigned char MSGLOST : 1;
+			unsigned char  : 1;
+			unsigned char ONESHOT : 1;
+			unsigned char  : 1;
+			unsigned char RECREQ : 1;
+			unsigned char TRMREQ : 1;
+#else
+			unsigned char TRMREQ : 1;
+			unsigned char RECREQ : 1;
+			unsigned char  : 1;
+			unsigned char ONESHOT : 1;
+			unsigned char  : 1;
+			unsigned char MSGLOST : 1;
+			unsigned char INVALDATA : 1;
+			unsigned char NEWDATA : 1;
+#endif
+	} RX;
+		} BIT;
+	} MCTL[32];
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char H;
+			unsigned char L;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short MBM : 1;
+			unsigned short IDFM : 2;
+			unsigned short MLM : 1;
+			unsigned short TPM : 1;
+			unsigned short TSRC : 1;
+			unsigned short TSPS : 2;
+			unsigned short CANM : 2;
+			unsigned short SLPM : 1;
+			unsigned short BOM : 2;
+			unsigned short RBOC : 1;
+			unsigned short  : 2;
+#else
+			unsigned short  : 2;
+			unsigned short RBOC : 1;
+			unsigned short BOM : 2;
+			unsigned short SLPM : 1;
+			unsigned short CANM : 2;
+			unsigned short TSPS : 2;
+			unsigned short TSRC : 1;
+			unsigned short TPM : 1;
+			unsigned short MLM : 1;
+			unsigned short IDFM : 2;
+			unsigned short MBM : 1;
+#endif
+	} BIT;
+	} CTLR;
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char H;
+			unsigned char L;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short NDST : 1;
+			unsigned short SDST : 1;
+			unsigned short RFST : 1;
+			unsigned short TFST : 1;
+			unsigned short NMLST : 1;
+			unsigned short FMLST : 1;
+			unsigned short TABST : 1;
+			unsigned short EST : 1;
+			unsigned short RSTST : 1;
+			unsigned short HLTST : 1;
+			unsigned short SLPST : 1;
+			unsigned short EPST : 1;
+			unsigned short BOST : 1;
+			unsigned short TRMST : 1;
+			unsigned short RECST : 1;
+			unsigned short  : 1;
+#else
+			unsigned short  : 1;
+			unsigned short RECST : 1;
+			unsigned short TRMST : 1;
+			unsigned short BOST : 1;
+			unsigned short EPST : 1;
+			unsigned short SLPST : 1;
+			unsigned short HLTST : 1;
+			unsigned short RSTST : 1;
+			unsigned short EST : 1;
+			unsigned short TABST : 1;
+			unsigned short FMLST : 1;
+			unsigned short NMLST : 1;
+			unsigned short TFST : 1;
+			unsigned short RFST : 1;
+			unsigned short SDST : 1;
+			unsigned short NDST : 1;
+#endif
+	} BIT;
+	} STR;
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned short H;
+			unsigned short L;
+		} WORD;
+		struct {
+			unsigned char HH;
+			unsigned char HL;
+			unsigned char LH;
+			unsigned char LL;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CCLKS : 1;
+			unsigned long  : 7;
+			unsigned long TSEG2 : 3;
+			unsigned long  : 1;
+			unsigned long SJW : 2;
+			unsigned long  : 2;
+			unsigned long BRP : 10;
+			unsigned long  : 2;
+			unsigned long TSEG1 : 4;
+#else
+			unsigned long TSEG1 : 4;
+			unsigned long  : 2;
+			unsigned long BRP : 10;
+			unsigned long  : 2;
+			unsigned long SJW : 2;
+			unsigned long  : 1;
+			unsigned long TSEG2 : 3;
+			unsigned long  : 7;
+			unsigned long CCLKS : 1;
+#endif
+	} BIT;
+	} BCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RFE : 1;
+			unsigned char RFUST : 3;
+			unsigned char RFMLF : 1;
+			unsigned char RFFST : 1;
+			unsigned char RFWST : 1;
+			unsigned char RFEST : 1;
+#else
+			unsigned char RFEST : 1;
+			unsigned char RFWST : 1;
+			unsigned char RFFST : 1;
+			unsigned char RFMLF : 1;
+			unsigned char RFUST : 3;
+			unsigned char RFE : 1;
+#endif
+	} BIT;
+	} RFCR;
+	unsigned char  RFPCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TFE : 1;
+			unsigned char TFUST : 3;
+			unsigned char  : 2;
+			unsigned char TFFST : 1;
+			unsigned char TFEST : 1;
+#else
+			unsigned char TFEST : 1;
+			unsigned char TFFST : 1;
+			unsigned char  : 2;
+			unsigned char TFUST : 3;
+			unsigned char TFE : 1;
+#endif
+	} BIT;
+	} TFCR;
+	unsigned char  TFPCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BEIE : 1;
+			unsigned char EWIE : 1;
+			unsigned char EPIE : 1;
+			unsigned char BOEIE : 1;
+			unsigned char BORIE : 1;
+			unsigned char ORIE : 1;
+			unsigned char OLIE : 1;
+			unsigned char BLIE : 1;
+#else
+			unsigned char BLIE : 1;
+			unsigned char OLIE : 1;
+			unsigned char ORIE : 1;
+			unsigned char BORIE : 1;
+			unsigned char BOEIE : 1;
+			unsigned char EPIE : 1;
+			unsigned char EWIE : 1;
+			unsigned char BEIE : 1;
+#endif
+	} BIT;
+	} EIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BEIF : 1;
+			unsigned char EWIF : 1;
+			unsigned char EPIF : 1;
+			unsigned char BOEIF : 1;
+			unsigned char BORIF : 1;
+			unsigned char ORIF : 1;
+			unsigned char OLIF : 1;
+			unsigned char BLIF : 1;
+#else
+			unsigned char BLIF : 1;
+			unsigned char OLIF : 1;
+			unsigned char ORIF : 1;
+			unsigned char BORIF : 1;
+			unsigned char BOEIF : 1;
+			unsigned char EPIF : 1;
+			unsigned char EWIF : 1;
+			unsigned char BEIF : 1;
+#endif
+	} BIT;
+	} EIFR;
+	unsigned char  RECR;
+	unsigned char  TECR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SEF : 1;
+			unsigned char FEF : 1;
+			unsigned char AEF : 1;
+			unsigned char CEF : 1;
+			unsigned char BE1F : 1;
+			unsigned char BE0F : 1;
+			unsigned char ADEF : 1;
+			unsigned char EDPM : 1;
+#else
+			unsigned char EDPM : 1;
+			unsigned char ADEF : 1;
+			unsigned char BE0F : 1;
+			unsigned char BE1F : 1;
+			unsigned char CEF : 1;
+			unsigned char AEF : 1;
+			unsigned char FEF : 1;
+			unsigned char SEF : 1;
+#endif
+	} BIT;
+	} ECSR;
+	unsigned char  CSSR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MBNST : 5;
+			unsigned char  : 2;
+			unsigned char SEST : 1;
+#else
+			unsigned char SEST : 1;
+			unsigned char  : 2;
+			unsigned char MBNST : 5;
+#endif
+	} BIT;
+	} MSSR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MBSM : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char MBSM : 2;
+#endif
+	} BIT;
+	} MSMR;
+	unsigned short TSR;
+	unsigned short AFSR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TSTE : 1;
+			unsigned char TSTM : 2;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TSTM : 2;
+			unsigned char TSTE : 1;
+#endif
+	} BIT;
+	} TCR;
+} st_can_t;
+
+typedef struct st_cmt {
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short STR0 : 1;
+			unsigned short STR1 : 1;
+			unsigned short  : 14;
+#else
+			unsigned short  : 14;
+			unsigned short STR1 : 1;
+			unsigned short STR0 : 1;
+#endif
+	} BIT;
+	} CMSTR0;
+	char           wk0[14];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short STR2 : 1;
+			unsigned short STR3 : 1;
+			unsigned short  : 14;
+#else
+			unsigned short  : 14;
+			unsigned short STR3 : 1;
+			unsigned short STR2 : 1;
+#endif
+	} BIT;
+	} CMSTR1;
+} st_cmt_t;
+
+typedef struct st_cmt0 {
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CKS : 2;
+			unsigned short  : 4;
+			unsigned short CMIE : 1;
+			unsigned short  : 9;
+#else
+			unsigned short  : 9;
+			unsigned short CMIE : 1;
+			unsigned short  : 4;
+			unsigned short CKS : 2;
+#endif
+	} BIT;
+	} CMCR;
+	unsigned short CMCNT;
+	unsigned short CMCOR;
+} st_cmt0_t;
+
+typedef struct st_cmtw {
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short STR : 1;
+			unsigned short  : 15;
+#else
+			unsigned short  : 15;
+			unsigned short STR : 1;
+#endif
+	} BIT;
+	} CMWSTR;
+	char           wk0[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CKS : 2;
+			unsigned short  : 1;
+			unsigned short CMWIE : 1;
+			unsigned short IC0IE : 1;
+			unsigned short IC1IE : 1;
+			unsigned short OC0IE : 1;
+			unsigned short OC1IE : 1;
+			unsigned short  : 1;
+			unsigned short CMS : 1;
+			unsigned short  : 3;
+			unsigned short CCLR : 3;
+#else
+			unsigned short CCLR : 3;
+			unsigned short  : 3;
+			unsigned short CMS : 1;
+			unsigned short  : 1;
+			unsigned short OC1IE : 1;
+			unsigned short OC0IE : 1;
+			unsigned short IC1IE : 1;
+			unsigned short IC0IE : 1;
+			unsigned short CMWIE : 1;
+			unsigned short  : 1;
+			unsigned short CKS : 2;
+#endif
+	} BIT;
+	} CMWCR;
+	char           wk1[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short IC0 : 2;
+			unsigned short IC1 : 2;
+			unsigned short IC0E : 1;
+			unsigned short IC1E : 1;
+			unsigned short  : 2;
+			unsigned short OC0 : 2;
+			unsigned short OC1 : 2;
+			unsigned short OC0E : 1;
+			unsigned short OC1E : 1;
+			unsigned short  : 1;
+			unsigned short CMWE : 1;
+#else
+			unsigned short CMWE : 1;
+			unsigned short  : 1;
+			unsigned short OC1E : 1;
+			unsigned short OC0E : 1;
+			unsigned short OC1 : 2;
+			unsigned short OC0 : 2;
+			unsigned short  : 2;
+			unsigned short IC1E : 1;
+			unsigned short IC0E : 1;
+			unsigned short IC1 : 2;
+			unsigned short IC0 : 2;
+#endif
+	} BIT;
+	} CMWIOR;
+	char           wk2[6];
+	unsigned long  CMWCNT;
+	unsigned long  CMWCOR;
+	unsigned long  CMWICR0;
+	unsigned long  CMWICR1;
+	unsigned long  CMWOCR0;
+	unsigned long  CMWOCR1;
+} st_cmtw_t;
+
+typedef struct st_crc {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char GPS : 3;
+			unsigned char  : 3;
+			unsigned char LMS : 1;
+			unsigned char DORCLR : 1;
+#else
+			unsigned char DORCLR : 1;
+			unsigned char LMS : 1;
+			unsigned char  : 3;
+			unsigned char GPS : 3;
+#endif
+	} BIT;
+	} CRCCR;
+	char           wk0[3];
+	union {
+		unsigned long LONG;
+		unsigned char BYTE;
+	} CRCDIR;
+	union {
+		unsigned long LONG;
+		unsigned short WORD;
+		unsigned char BYTE;
+	} CRCDOR;
+} st_crc_t;
+
+typedef struct st_da {
+	unsigned short DADR0;
+	unsigned short DADR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 5;
+			unsigned char DAE : 1;
+			unsigned char DAOE0 : 1;
+			unsigned char DAOE1 : 1;
+#else
+			unsigned char DAOE1 : 1;
+			unsigned char DAOE0 : 1;
+			unsigned char DAE : 1;
+			unsigned char  : 5;
+#endif
+	} BIT;
+	} DACR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char DPSEL : 1;
+#else
+			unsigned char DPSEL : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} DADPR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char DAADST : 1;
+#else
+			unsigned char DAADST : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} DAADSCR;
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char DAAMP0 : 1;
+			unsigned char DAAMP1 : 1;
+#else
+			unsigned char DAAMP1 : 1;
+			unsigned char DAAMP0 : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} DAAMPCR;
+	char           wk1[19];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char DAASW0 : 1;
+			unsigned char DAASW1 : 1;
+#else
+			unsigned char DAASW1 : 1;
+			unsigned char DAASW0 : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} DAASWCR;
+	char           wk2[17763];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 1;
+			unsigned char AMADSEL1 : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char AMADSEL1 : 1;
+			unsigned char  : 1;
+#endif
+	} BIT;
+	} DAADUSR;
+} st_da_t;
+
+typedef struct st_dmac {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DMST : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DMST : 1;
+#endif
+	} BIT;
+	} DMAST;
+	char           wk0[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 4;
+			unsigned char DMIS4 : 1;
+			unsigned char DMIS5 : 1;
+			unsigned char DMIS6 : 1;
+			unsigned char DMIS7 : 1;
+#else
+			unsigned char DMIS7 : 1;
+			unsigned char DMIS6 : 1;
+			unsigned char DMIS5 : 1;
+			unsigned char DMIS4 : 1;
+			unsigned char  : 4;
+#endif
+	} BIT;
+	} DMIST;
+} st_dmac_t;
+
+typedef struct st_dmac0 {
+	void          *DMSAR;
+	void          *DMDAR;
+	unsigned long  DMCRA;
+	unsigned short DMCRB;
+	char           wk0[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DCTG : 2;
+			unsigned short  : 6;
+			unsigned short SZ : 2;
+			unsigned short  : 2;
+			unsigned short DTS : 2;
+			unsigned short MD : 2;
+#else
+			unsigned short MD : 2;
+			unsigned short DTS : 2;
+			unsigned short  : 2;
+			unsigned short SZ : 2;
+			unsigned short  : 6;
+			unsigned short DCTG : 2;
+#endif
+	} BIT;
+	} DMTMD;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DARIE : 1;
+			unsigned char SARIE : 1;
+			unsigned char RPTIE : 1;
+			unsigned char ESIE : 1;
+			unsigned char DTIE : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char DTIE : 1;
+			unsigned char ESIE : 1;
+			unsigned char RPTIE : 1;
+			unsigned char SARIE : 1;
+			unsigned char DARIE : 1;
+#endif
+	} BIT;
+	} DMINT;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DARA : 5;
+			unsigned short  : 1;
+			unsigned short DM : 2;
+			unsigned short SARA : 5;
+			unsigned short  : 1;
+			unsigned short SM : 2;
+#else
+			unsigned short SM : 2;
+			unsigned short  : 1;
+			unsigned short SARA : 5;
+			unsigned short DM : 2;
+			unsigned short  : 1;
+			unsigned short DARA : 5;
+#endif
+	} BIT;
+	} DMAMD;
+	char           wk2[2];
+	unsigned long  DMOFR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DTE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DTE : 1;
+#endif
+	} BIT;
+	} DMCNT;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SWREQ : 1;
+			unsigned char  : 3;
+			unsigned char CLRS : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char CLRS : 1;
+			unsigned char  : 3;
+			unsigned char SWREQ : 1;
+#endif
+	} BIT;
+	} DMREQ;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ESIF : 1;
+			unsigned char  : 3;
+			unsigned char DTIF : 1;
+			unsigned char  : 2;
+			unsigned char ACT : 1;
+#else
+			unsigned char ACT : 1;
+			unsigned char  : 2;
+			unsigned char DTIF : 1;
+			unsigned char  : 3;
+			unsigned char ESIF : 1;
+#endif
+	} BIT;
+	} DMSTS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DISEL : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DISEL : 1;
+#endif
+	} BIT;
+	} DMCSL;
+} st_dmac0_t;
+
+typedef struct st_dmac1 {
+	void          *DMSAR;
+	void          *DMDAR;
+	unsigned long  DMCRA;
+	unsigned short DMCRB;
+	char           wk0[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DCTG : 2;
+			unsigned short  : 6;
+			unsigned short SZ : 2;
+			unsigned short  : 2;
+			unsigned short DTS : 2;
+			unsigned short MD : 2;
+#else
+			unsigned short MD : 2;
+			unsigned short DTS : 2;
+			unsigned short  : 2;
+			unsigned short SZ : 2;
+			unsigned short  : 6;
+			unsigned short DCTG : 2;
+#endif
+	} BIT;
+	} DMTMD;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DARIE : 1;
+			unsigned char SARIE : 1;
+			unsigned char RPTIE : 1;
+			unsigned char ESIE : 1;
+			unsigned char DTIE : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char DTIE : 1;
+			unsigned char ESIE : 1;
+			unsigned char RPTIE : 1;
+			unsigned char SARIE : 1;
+			unsigned char DARIE : 1;
+#endif
+	} BIT;
+	} DMINT;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DARA : 5;
+			unsigned short  : 1;
+			unsigned short DM : 2;
+			unsigned short SARA : 5;
+			unsigned short  : 1;
+			unsigned short SM : 2;
+#else
+			unsigned short SM : 2;
+			unsigned short  : 1;
+			unsigned short SARA : 5;
+			unsigned short DM : 2;
+			unsigned short  : 1;
+			unsigned short DARA : 5;
+#endif
+	} BIT;
+	} DMAMD;
+	char           wk2[6];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DTE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DTE : 1;
+#endif
+	} BIT;
+	} DMCNT;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SWREQ : 1;
+			unsigned char  : 3;
+			unsigned char CLRS : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char CLRS : 1;
+			unsigned char  : 3;
+			unsigned char SWREQ : 1;
+#endif
+	} BIT;
+	} DMREQ;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ESIF : 1;
+			unsigned char  : 3;
+			unsigned char DTIF : 1;
+			unsigned char  : 2;
+			unsigned char ACT : 1;
+#else
+			unsigned char ACT : 1;
+			unsigned char  : 2;
+			unsigned char DTIF : 1;
+			unsigned char  : 3;
+			unsigned char ESIF : 1;
+#endif
+	} BIT;
+	} DMSTS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DISEL : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DISEL : 1;
+#endif
+	} BIT;
+	} DMCSL;
+} st_dmac1_t;
+
+typedef struct st_doc {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OMS : 2;
+			unsigned char DCSEL : 1;
+			unsigned char  : 1;
+			unsigned char DOPCIE : 1;
+			unsigned char DOPCF : 1;
+			unsigned char DOPCFCL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char DOPCFCL : 1;
+			unsigned char DOPCF : 1;
+			unsigned char DOPCIE : 1;
+			unsigned char  : 1;
+			unsigned char DCSEL : 1;
+			unsigned char OMS : 2;
+#endif
+	} BIT;
+	} DOCR;
+	char           wk0[1];
+	unsigned short DODIR;
+	unsigned short DODSR;
+} st_doc_t;
+
+typedef struct st_drw2d {
+	union {
+		union {
+			unsigned long LONG;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long LIM1EN : 1;
+			unsigned long LIM2EN : 1;
+			unsigned long LIM3EN : 1;
+			unsigned long LIM4EN : 1;
+			unsigned long LIM5EN : 1;
+			unsigned long LIM6EN : 1;
+			unsigned long QUAD1EN : 1;
+			unsigned long QUAD2EN : 1;
+			unsigned long QUAD3EN : 1;
+			unsigned long LIM1TH : 1;
+			unsigned long LIM2TH : 1;
+			unsigned long LIM3TH : 1;
+			unsigned long LIM4TH : 1;
+			unsigned long LIM5TH : 1;
+			unsigned long LIM6TH : 1;
+			unsigned long BAND1EN : 1;
+			unsigned long BAND2EN : 1;
+			unsigned long UNION12 : 1;
+			unsigned long UNION34 : 1;
+			unsigned long UNION56 : 1;
+			unsigned long UNIONAB : 1;
+			unsigned long UNIONCD : 1;
+			unsigned long SPANABT : 1;
+			unsigned long SPANSTR : 1;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long SPANSTR : 1;
+			unsigned long SPANABT : 1;
+			unsigned long UNIONCD : 1;
+			unsigned long UNIONAB : 1;
+			unsigned long UNION56 : 1;
+			unsigned long UNION34 : 1;
+			unsigned long UNION12 : 1;
+			unsigned long BAND2EN : 1;
+			unsigned long BAND1EN : 1;
+			unsigned long LIM6TH : 1;
+			unsigned long LIM5TH : 1;
+			unsigned long LIM4TH : 1;
+			unsigned long LIM3TH : 1;
+			unsigned long LIM2TH : 1;
+			unsigned long LIM1TH : 1;
+			unsigned long QUAD3EN : 1;
+			unsigned long QUAD2EN : 1;
+			unsigned long QUAD1EN : 1;
+			unsigned long LIM6EN : 1;
+			unsigned long LIM5EN : 1;
+			unsigned long LIM4EN : 1;
+			unsigned long LIM3EN : 1;
+			unsigned long LIM2EN : 1;
+			unsigned long LIM1EN : 1;
+#endif
+	} BIT;
+		} CONTROL;
+		union {
+			unsigned long LONG;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long BSYENUM : 1;
+			unsigned long BSYWR : 1;
+			unsigned long CACHEDTY : 1;
+			unsigned long DLSTACT : 1;
+			unsigned long ENUIR : 1;
+			unsigned long DLIR : 1;
+			unsigned long  : 26;
+#else
+			unsigned long  : 26;
+			unsigned long DLIR : 1;
+			unsigned long ENUIR : 1;
+			unsigned long DLSTACT : 1;
+			unsigned long CACHEDTY : 1;
+			unsigned long BSYWR : 1;
+			unsigned long BSYENUM : 1;
+#endif
+	} BIT;
+		} STATUS;
+	};
+	union {
+		union {
+			unsigned long LONG;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PTNEN : 1;
+			unsigned long TEXENA : 1;
+			unsigned long PTNSRCL5 : 1;
+			unsigned long USEACB : 1;
+			unsigned long RDFMT2 : 2;
+			unsigned long BSFA : 1;
+			unsigned long BDFA : 1;
+			unsigned long WRFMT2 : 1;
+			unsigned long BSF : 1;
+			unsigned long BDF : 1;
+			unsigned long BSI : 1;
+			unsigned long BDI : 1;
+			unsigned long BC2 : 1;
+			unsigned long TEXCLPX : 1;
+			unsigned long TEXCLPY : 1;
+			unsigned long TEXFILTX : 1;
+			unsigned long TEXFILTY : 1;
+			unsigned long RDFMT : 2;
+			unsigned long WRFMT : 2;
+			unsigned long WRALPHA : 2;
+			unsigned long RLEEN : 1;
+			unsigned long CLUTEN : 1;
+			unsigned long COLKEYEN : 1;
+			unsigned long CLUTFORM : 1;
+			unsigned long BSIA : 1;
+			unsigned long BDIA : 1;
+			unsigned long RLEPIXW : 2;
+#else
+			unsigned long RLEPIXW : 2;
+			unsigned long BDIA : 1;
+			unsigned long BSIA : 1;
+			unsigned long CLUTFORM : 1;
+			unsigned long COLKEYEN : 1;
+			unsigned long CLUTEN : 1;
+			unsigned long RLEEN : 1;
+			unsigned long WRALPHA : 2;
+			unsigned long WRFMT : 2;
+			unsigned long RDFMT : 2;
+			unsigned long TEXFILTY : 1;
+			unsigned long TEXFILTX : 1;
+			unsigned long TEXCLPY : 1;
+			unsigned long TEXCLPX : 1;
+			unsigned long BC2 : 1;
+			unsigned long BDI : 1;
+			unsigned long BSI : 1;
+			unsigned long BDF : 1;
+			unsigned long BSF : 1;
+			unsigned long WRFMT2 : 1;
+			unsigned long BDFA : 1;
+			unsigned long BSFA : 1;
+			unsigned long RDFMT2 : 2;
+			unsigned long USEACB : 1;
+			unsigned long PTNSRCL5 : 1;
+			unsigned long TEXENA : 1;
+			unsigned long PTNEN : 1;
+#endif
+	} BIT;
+		} CONTROL2;
+		union {
+			unsigned long LONG;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long REV : 12;
+			unsigned long  : 5;
+			unsigned long DLR : 1;
+			unsigned long FBCACHE : 1;
+			unsigned long TXCACHE : 1;
+			unsigned long PERFCNT : 1;
+			unsigned long TEXCLUT : 1;
+			unsigned long  : 1;
+			unsigned long RLEUNIT : 1;
+			unsigned long TEXCLUT256 : 1;
+			unsigned long COLKEY : 1;
+			unsigned long  : 1;
+			unsigned long ACBLD : 1;
+			unsigned long  : 4;
+#else
+			unsigned long  : 4;
+			unsigned long ACBLD : 1;
+			unsigned long  : 1;
+			unsigned long COLKEY : 1;
+			unsigned long TEXCLUT256 : 1;
+			unsigned long RLEUNIT : 1;
+			unsigned long  : 1;
+			unsigned long TEXCLUT : 1;
+			unsigned long PERFCNT : 1;
+			unsigned long TXCACHE : 1;
+			unsigned long FBCACHE : 1;
+			unsigned long DLR : 1;
+			unsigned long  : 5;
+			unsigned long REV : 12;
+#endif
+	} BIT;
+		} HWVER;
+	};
+	char           wk0[8];
+	unsigned long  L1START;
+	unsigned long  L2START;
+	unsigned long  L3START;
+	unsigned long  L4START;
+	unsigned long  L5START;
+	unsigned long  L6START;
+	unsigned long  L1XADD;
+	unsigned long  L2XADD;
+	unsigned long  L3XADD;
+	unsigned long  L4XADD;
+	unsigned long  L5XADD;
+	unsigned long  L6XADD;
+	unsigned long  L1YADD;
+	unsigned long  L2YADD;
+	unsigned long  L3YADD;
+	unsigned long  L4YADD;
+	unsigned long  L5YADD;
+	unsigned long  L6YADD;
+	unsigned long  L1BAND;
+	unsigned long  L2BAND;
+	char           wk1[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long COL1B : 8;
+			unsigned long COL1G : 8;
+			unsigned long COL1R : 8;
+			unsigned long COL1A : 8;
+#else
+			unsigned long COL1A : 8;
+			unsigned long COL1R : 8;
+			unsigned long COL1G : 8;
+			unsigned long COL1B : 8;
+#endif
+	} BIT;
+	} COLOR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long COL2B : 8;
+			unsigned long COL2G : 8;
+			unsigned long COL2R : 8;
+			unsigned long COL2A : 8;
+#else
+			unsigned long COL2A : 8;
+			unsigned long COL2R : 8;
+			unsigned long COL2G : 8;
+			unsigned long COL2B : 8;
+#endif
+	} BIT;
+	} COLOR2;
+	char           wk2[8];
+	unsigned long  PATTERN;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long X : 16;
+			unsigned long Y : 16;
+#else
+			unsigned long Y : 16;
+			unsigned long X : 16;
+#endif
+	} BIT;
+	} SIZE;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PITCH : 16;
+			unsigned long SSD : 16;
+#else
+			unsigned long SSD : 16;
+			unsigned long PITCH : 16;
+#endif
+	} BIT;
+	} PITCH;
+	unsigned long  ORIGIN;
+	char           wk3[12];
+	unsigned long  LUST;
+	unsigned long  LUXADD;
+	unsigned long  LUYADD;
+	unsigned long  LVSTI;
+	unsigned long  LVSTF;
+	unsigned long  LVXADDI;
+	unsigned long  LVYADDI;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long LVXADDF : 16;
+			unsigned long LVYADDF : 16;
+#else
+			unsigned long LVYADDF : 16;
+			unsigned long LVXADDF : 16;
+#endif
+	} BIT;
+	} LVYXADDF;
+	char           wk4[4];
+	unsigned long  TEXPITCH;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TEXUMSK : 11;
+			unsigned long TEXVMSK : 21;
+#else
+			unsigned long TEXVMSK : 21;
+			unsigned long TEXUMSK : 11;
+#endif
+	} BIT;
+	} TEXMSK;
+	unsigned long  TEXORG;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ENUIREN : 1;
+			unsigned long DLIREN : 1;
+			unsigned long ENUIRCLR : 1;
+			unsigned long DLIRCLR : 1;
+			unsigned long  : 28;
+#else
+			unsigned long  : 28;
+			unsigned long DLIRCLR : 1;
+			unsigned long ENUIRCLR : 1;
+			unsigned long DLIREN : 1;
+			unsigned long ENUIREN : 1;
+#endif
+	} BIT;
+	} IRQCTL;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CENFX : 1;
+			unsigned long CFLUFX : 1;
+			unsigned long CENTX : 1;
+			unsigned long CFLUTX : 1;
+			unsigned long  : 28;
+#else
+			unsigned long  : 28;
+			unsigned long CFLUTX : 1;
+			unsigned long CENTX : 1;
+			unsigned long CFLUFX : 1;
+			unsigned long CENFX : 1;
+#endif
+	} BIT;
+	} CACHECTL;
+	unsigned long  DLISTST;
+	unsigned long  PERFCNT1;
+	unsigned long  PERFCNT2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TRG1 : 16;
+			unsigned long TRG2 : 16;
+#else
+			unsigned long TRG2 : 16;
+			unsigned long TRG1 : 16;
+#endif
+	} BIT;
+	} PERFTRG;
+	char           wk5[4];
+	unsigned long  TEXCLADDR;
+	unsigned long  TEXCLDATA;
+	unsigned long  TEXCLOFST;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long B : 8;
+			unsigned long G : 8;
+			unsigned long R : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long R : 8;
+			unsigned long G : 8;
+			unsigned long B : 8;
+#endif
+	} BIT;
+	} COLKEY;
+} st_drw2d_t;
+
+typedef struct st_dtc {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 4;
+			unsigned char RRS : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char RRS : 1;
+			unsigned char  : 4;
+#endif
+	} BIT;
+	} DTCCR;
+	char           wk0[3];
+	void          *DTCVBR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SHORT : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char SHORT : 1;
+#endif
+	} BIT;
+	} DTCADMOD;
+	char           wk1[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DTCST : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DTCST : 1;
+#endif
+	} BIT;
+	} DTCST;
+	char           wk2[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short VECN : 8;
+			unsigned short  : 7;
+			unsigned short ACT : 1;
+#else
+			unsigned short ACT : 1;
+			unsigned short  : 7;
+			unsigned short VECN : 8;
+#endif
+	} BIT;
+	} DTCSTS;
+	void          *DTCIBR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SQTFRL : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char SQTFRL : 1;
+#endif
+	} BIT;
+	} DTCOR;
+	char           wk3[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short VECN : 8;
+			unsigned short  : 7;
+			unsigned short ESPSEL : 1;
+#else
+			unsigned short ESPSEL : 1;
+			unsigned short  : 7;
+			unsigned short VECN : 8;
+#endif
+	} BIT;
+	} DTCSQE;
+	unsigned long  DTCDISP;
+} st_dtc_t;
+
+typedef struct st_edmac {
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long SWR : 1;
+			unsigned long  : 3;
+			unsigned long DL : 2;
+			unsigned long DE : 1;
+			unsigned long  : 25;
+#else
+			unsigned long  : 25;
+			unsigned long DE : 1;
+			unsigned long DL : 2;
+			unsigned long  : 3;
+			unsigned long SWR : 1;
+#endif
+	} BIT;
+	} EDMR;
+	char           wk0[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TR : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long TR : 1;
+#endif
+	} BIT;
+	} EDTRR;
+	char           wk1[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RR : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long RR : 1;
+#endif
+	} BIT;
+	} EDRRR;
+	char           wk2[4];
+	void          *TDLAR;
+	char           wk3[4];
+	void          *RDLAR;
+	char           wk4[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CERF : 1;
+			unsigned long PRE : 1;
+			unsigned long RTSF : 1;
+			unsigned long RTLF : 1;
+			unsigned long RRF : 1;
+			unsigned long  : 2;
+			unsigned long RMAF : 1;
+			unsigned long TRO : 1;
+			unsigned long CD : 1;
+			unsigned long DLC : 1;
+			unsigned long CND : 1;
+			unsigned long  : 4;
+			unsigned long RFOF : 1;
+			unsigned long RDE : 1;
+			unsigned long FR : 1;
+			unsigned long TFUF : 1;
+			unsigned long TDE : 1;
+			unsigned long TC : 1;
+			unsigned long ECI : 1;
+			unsigned long  : 1;
+			unsigned long RFCOF : 1;
+			unsigned long RABT : 1;
+			unsigned long TABT : 1;
+			unsigned long  : 3;
+			unsigned long TWB : 1;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long TWB : 1;
+			unsigned long  : 3;
+			unsigned long TABT : 1;
+			unsigned long RABT : 1;
+			unsigned long RFCOF : 1;
+			unsigned long  : 1;
+			unsigned long ECI : 1;
+			unsigned long TC : 1;
+			unsigned long TDE : 1;
+			unsigned long TFUF : 1;
+			unsigned long FR : 1;
+			unsigned long RDE : 1;
+			unsigned long RFOF : 1;
+			unsigned long  : 4;
+			unsigned long CND : 1;
+			unsigned long DLC : 1;
+			unsigned long CD : 1;
+			unsigned long TRO : 1;
+			unsigned long RMAF : 1;
+			unsigned long  : 2;
+			unsigned long RRF : 1;
+			unsigned long RTLF : 1;
+			unsigned long RTSF : 1;
+			unsigned long PRE : 1;
+			unsigned long CERF : 1;
+#endif
+	} BIT;
+	} EESR;
+	char           wk5[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CERFIP : 1;
+			unsigned long PREIP : 1;
+			unsigned long RTSFIP : 1;
+			unsigned long RTLFIP : 1;
+			unsigned long RRFIP : 1;
+			unsigned long  : 2;
+			unsigned long RMAFIP : 1;
+			unsigned long TROIP : 1;
+			unsigned long CDIP : 1;
+			unsigned long DLCIP : 1;
+			unsigned long CNDIP : 1;
+			unsigned long  : 4;
+			unsigned long RFOFIP : 1;
+			unsigned long RDEIP : 1;
+			unsigned long FRIP : 1;
+			unsigned long TFUFIP : 1;
+			unsigned long TDEIP : 1;
+			unsigned long TCIP : 1;
+			unsigned long ECIIP : 1;
+			unsigned long  : 1;
+			unsigned long RFCOFIP : 1;
+			unsigned long RABTIP : 1;
+			unsigned long TABTIP : 1;
+			unsigned long  : 3;
+			unsigned long TWBIP : 1;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long TWBIP : 1;
+			unsigned long  : 3;
+			unsigned long TABTIP : 1;
+			unsigned long RABTIP : 1;
+			unsigned long RFCOFIP : 1;
+			unsigned long  : 1;
+			unsigned long ECIIP : 1;
+			unsigned long TCIP : 1;
+			unsigned long TDEIP : 1;
+			unsigned long TFUFIP : 1;
+			unsigned long FRIP : 1;
+			unsigned long RDEIP : 1;
+			unsigned long RFOFIP : 1;
+			unsigned long  : 4;
+			unsigned long CNDIP : 1;
+			unsigned long DLCIP : 1;
+			unsigned long CDIP : 1;
+			unsigned long TROIP : 1;
+			unsigned long RMAFIP : 1;
+			unsigned long  : 2;
+			unsigned long RRFIP : 1;
+			unsigned long RTLFIP : 1;
+			unsigned long RTSFIP : 1;
+			unsigned long PREIP : 1;
+			unsigned long CERFIP : 1;
+#endif
+	} BIT;
+	} EESIPR;
+	char           wk6[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long RRFCE : 1;
+			unsigned long  : 2;
+			unsigned long RMAFCE : 1;
+			unsigned long  : 24;
+#else
+			unsigned long  : 24;
+			unsigned long RMAFCE : 1;
+			unsigned long  : 2;
+			unsigned long RRFCE : 1;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} TRSCER;
+	char           wk7[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MFC : 16;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long MFC : 16;
+#endif
+	} BIT;
+	} RMFCR;
+	char           wk8[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TFT : 11;
+			unsigned long  : 21;
+#else
+			unsigned long  : 21;
+			unsigned long TFT : 11;
+#endif
+	} BIT;
+	} TFTR;
+	char           wk9[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RFD : 5;
+			unsigned long  : 3;
+			unsigned long TFD : 5;
+			unsigned long  : 19;
+#else
+			unsigned long  : 19;
+			unsigned long TFD : 5;
+			unsigned long  : 3;
+			unsigned long RFD : 5;
+#endif
+	} BIT;
+	} FDR;
+	char           wk10[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RNR : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long RNR : 1;
+#endif
+	} BIT;
+	} RMCR;
+	char           wk11[8];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long UNDER : 16;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long UNDER : 16;
+#endif
+	} BIT;
+	} TFUCR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long OVER : 16;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long OVER : 16;
+#endif
+	} BIT;
+	} RFOCR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ELB : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long ELB : 1;
+#endif
+	} BIT;
+	} IOSR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RFDO : 3;
+			unsigned long  : 13;
+			unsigned long RFFO : 3;
+			unsigned long  : 13;
+#else
+			unsigned long  : 13;
+			unsigned long RFFO : 3;
+			unsigned long  : 13;
+			unsigned long RFDO : 3;
+#endif
+	} BIT;
+	} FCFTR;
+	char           wk12[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PADR : 6;
+			unsigned long  : 10;
+			unsigned long PADS : 2;
+			unsigned long  : 14;
+#else
+			unsigned long  : 14;
+			unsigned long PADS : 2;
+			unsigned long  : 10;
+			unsigned long PADR : 6;
+#endif
+	} BIT;
+	} RPADIR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TIS : 1;
+			unsigned long  : 3;
+			unsigned long TIM : 1;
+			unsigned long  : 27;
+#else
+			unsigned long  : 27;
+			unsigned long TIM : 1;
+			unsigned long  : 3;
+			unsigned long TIS : 1;
+#endif
+	} BIT;
+	} TRIMD;
+	char           wk13[72];
+	void          *RBWAR;
+	void          *RDFAR;
+	char           wk14[4];
+	void          *TBRAR;
+	void          *TDFAR;
+} st_edmac_t;
+
+typedef struct st_elc {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char ELCON : 1;
+#else
+			unsigned char ELCON : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} ELCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR0;
+	char           wk0[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR4;
+	char           wk1[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR7;
+	char           wk2[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR10;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR11;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR12;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR13;
+	char           wk3[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR15;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR16;
+	char           wk4[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR18;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR19;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR20;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR21;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR22;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR23;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR24;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR25;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR26;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR27;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR28;
+	char           wk5[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MTU0MD : 2;
+			unsigned char  : 4;
+			unsigned char MTU3MD : 2;
+#else
+			unsigned char MTU3MD : 2;
+			unsigned char  : 4;
+			unsigned char MTU0MD : 2;
+#endif
+	} BIT;
+	} ELOPA;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MTU4MD : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char MTU4MD : 2;
+#endif
+	} BIT;
+	} ELOPB;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 2;
+			unsigned char CMT1MD : 2;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char CMT1MD : 2;
+			unsigned char  : 2;
+#endif
+	} BIT;
+	} ELOPC;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TMR0MD : 2;
+			unsigned char TMR1MD : 2;
+			unsigned char TMR2MD : 2;
+			unsigned char TMR3MD : 2;
+#else
+			unsigned char TMR3MD : 2;
+			unsigned char TMR2MD : 2;
+			unsigned char TMR1MD : 2;
+			unsigned char TMR0MD : 2;
+#endif
+	} BIT;
+	} ELOPD;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PGR0 : 1;
+			unsigned char PGR1 : 1;
+			unsigned char PGR2 : 1;
+			unsigned char PGR3 : 1;
+			unsigned char PGR4 : 1;
+			unsigned char PGR5 : 1;
+			unsigned char PGR6 : 1;
+			unsigned char PGR7 : 1;
+#else
+			unsigned char PGR7 : 1;
+			unsigned char PGR6 : 1;
+			unsigned char PGR5 : 1;
+			unsigned char PGR4 : 1;
+			unsigned char PGR3 : 1;
+			unsigned char PGR2 : 1;
+			unsigned char PGR1 : 1;
+			unsigned char PGR0 : 1;
+#endif
+	} BIT;
+	} PGR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PGR0 : 1;
+			unsigned char PGR1 : 1;
+			unsigned char PGR2 : 1;
+			unsigned char PGR3 : 1;
+			unsigned char PGR4 : 1;
+			unsigned char PGR5 : 1;
+			unsigned char PGR6 : 1;
+			unsigned char PGR7 : 1;
+#else
+			unsigned char PGR7 : 1;
+			unsigned char PGR6 : 1;
+			unsigned char PGR5 : 1;
+			unsigned char PGR4 : 1;
+			unsigned char PGR3 : 1;
+			unsigned char PGR2 : 1;
+			unsigned char PGR1 : 1;
+			unsigned char PGR0 : 1;
+#endif
+	} BIT;
+	} PGR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PGCI : 2;
+			unsigned char PGCOVE : 1;
+			unsigned char  : 1;
+			unsigned char PGCO : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PGCO : 3;
+			unsigned char  : 1;
+			unsigned char PGCOVE : 1;
+			unsigned char PGCI : 2;
+#endif
+	} BIT;
+	} PGC1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PGCI : 2;
+			unsigned char PGCOVE : 1;
+			unsigned char  : 1;
+			unsigned char PGCO : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PGCO : 3;
+			unsigned char  : 1;
+			unsigned char PGCOVE : 1;
+			unsigned char PGCI : 2;
+#endif
+	} BIT;
+	} PGC2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PDBF0 : 1;
+			unsigned char PDBF1 : 1;
+			unsigned char PDBF2 : 1;
+			unsigned char PDBF3 : 1;
+			unsigned char PDBF4 : 1;
+			unsigned char PDBF5 : 1;
+			unsigned char PDBF6 : 1;
+			unsigned char PDBF7 : 1;
+#else
+			unsigned char PDBF7 : 1;
+			unsigned char PDBF6 : 1;
+			unsigned char PDBF5 : 1;
+			unsigned char PDBF4 : 1;
+			unsigned char PDBF3 : 1;
+			unsigned char PDBF2 : 1;
+			unsigned char PDBF1 : 1;
+			unsigned char PDBF0 : 1;
+#endif
+	} BIT;
+	} PDBF1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PDBF0 : 1;
+			unsigned char PDBF1 : 1;
+			unsigned char PDBF2 : 1;
+			unsigned char PDBF3 : 1;
+			unsigned char PDBF4 : 1;
+			unsigned char PDBF5 : 1;
+			unsigned char PDBF6 : 1;
+			unsigned char PDBF7 : 1;
+#else
+			unsigned char PDBF7 : 1;
+			unsigned char PDBF6 : 1;
+			unsigned char PDBF5 : 1;
+			unsigned char PDBF4 : 1;
+			unsigned char PDBF3 : 1;
+			unsigned char PDBF2 : 1;
+			unsigned char PDBF1 : 1;
+			unsigned char PDBF0 : 1;
+#endif
+	} BIT;
+	} PDBF2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSB : 3;
+			unsigned char PSP : 2;
+			unsigned char PSM : 2;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PSM : 2;
+			unsigned char PSP : 2;
+			unsigned char PSB : 3;
+#endif
+	} BIT;
+	} PEL0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSB : 3;
+			unsigned char PSP : 2;
+			unsigned char PSM : 2;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PSM : 2;
+			unsigned char PSP : 2;
+			unsigned char PSB : 3;
+#endif
+	} BIT;
+	} PEL1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSB : 3;
+			unsigned char PSP : 2;
+			unsigned char PSM : 2;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PSM : 2;
+			unsigned char PSP : 2;
+			unsigned char PSB : 3;
+#endif
+	} BIT;
+	} PEL2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSB : 3;
+			unsigned char PSP : 2;
+			unsigned char PSM : 2;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PSM : 2;
+			unsigned char PSP : 2;
+			unsigned char PSB : 3;
+#endif
+	} BIT;
+	} PEL3;
+	union {
+		unsigned char BYTE;
+#ifdef IODEFINE_H_HISTORY
+		struct {
+			unsigned char WI:1;
+			unsigned char WE:1;
+			unsigned char :5;
+			unsigned char SEG:1;
+		} BIT;
+#endif
+	} ELSEGR;
+	char           wk6[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR33;
+	char           wk7[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR35;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR36;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR37;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR38;
+	char           wk8[6];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ELS : 8;
+#else
+			unsigned char ELS : 8;
+#endif
+	} BIT;
+	} ELSR45;
+	char           wk9[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPU0MD : 2;
+			unsigned char TPU1MD : 2;
+			unsigned char TPU2MD : 2;
+			unsigned char TPU3MD : 2;
+#else
+			unsigned char TPU3MD : 2;
+			unsigned char TPU2MD : 2;
+			unsigned char TPU1MD : 2;
+			unsigned char TPU0MD : 2;
+#endif
+	} BIT;
+	} ELOPF;
+	char           wk10[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMTW0MD : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char CMTW0MD : 2;
+#endif
+	} BIT;
+	} ELOPH;
+} st_elc_t;
+
+typedef struct st_etherc {
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PRM : 1;
+			unsigned long DM : 1;
+			unsigned long RTM : 1;
+			unsigned long ILB : 1;
+			unsigned long  : 1;
+			unsigned long TE : 1;
+			unsigned long RE : 1;
+			unsigned long  : 2;
+			unsigned long MPDE : 1;
+			unsigned long  : 2;
+			unsigned long PRCEF : 1;
+			unsigned long  : 3;
+			unsigned long TXF : 1;
+			unsigned long RXF : 1;
+			unsigned long PFR : 1;
+			unsigned long ZPF : 1;
+			unsigned long TPC : 1;
+			unsigned long  : 11;
+#else
+			unsigned long  : 11;
+			unsigned long TPC : 1;
+			unsigned long ZPF : 1;
+			unsigned long PFR : 1;
+			unsigned long RXF : 1;
+			unsigned long TXF : 1;
+			unsigned long  : 3;
+			unsigned long PRCEF : 1;
+			unsigned long  : 2;
+			unsigned long MPDE : 1;
+			unsigned long  : 2;
+			unsigned long RE : 1;
+			unsigned long TE : 1;
+			unsigned long  : 1;
+			unsigned long ILB : 1;
+			unsigned long RTM : 1;
+			unsigned long DM : 1;
+			unsigned long PRM : 1;
+#endif
+	} BIT;
+	} ECMR;
+	char           wk0[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RFL : 12;
+			unsigned long  : 20;
+#else
+			unsigned long  : 20;
+			unsigned long RFL : 12;
+#endif
+	} BIT;
+	} RFLR;
+	char           wk1[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ICD : 1;
+			unsigned long MPD : 1;
+			unsigned long LCHNG : 1;
+			unsigned long  : 1;
+			unsigned long PSRTO : 1;
+			unsigned long BFR : 1;
+			unsigned long  : 26;
+#else
+			unsigned long  : 26;
+			unsigned long BFR : 1;
+			unsigned long PSRTO : 1;
+			unsigned long  : 1;
+			unsigned long LCHNG : 1;
+			unsigned long MPD : 1;
+			unsigned long ICD : 1;
+#endif
+	} BIT;
+	} ECSR;
+	char           wk2[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ICDIP : 1;
+			unsigned long MPDIP : 1;
+			unsigned long LCHNGIP : 1;
+			unsigned long  : 1;
+			unsigned long PSRTOIP : 1;
+			unsigned long BFSIPR : 1;
+			unsigned long  : 26;
+#else
+			unsigned long  : 26;
+			unsigned long BFSIPR : 1;
+			unsigned long PSRTOIP : 1;
+			unsigned long  : 1;
+			unsigned long LCHNGIP : 1;
+			unsigned long MPDIP : 1;
+			unsigned long ICDIP : 1;
+#endif
+	} BIT;
+	} ECSIPR;
+	char           wk3[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MDC : 1;
+			unsigned long MMD : 1;
+			unsigned long MDO : 1;
+			unsigned long MDI : 1;
+			unsigned long  : 28;
+#else
+			unsigned long  : 28;
+			unsigned long MDI : 1;
+			unsigned long MDO : 1;
+			unsigned long MMD : 1;
+			unsigned long MDC : 1;
+#endif
+	} BIT;
+	} PIR;
+	char           wk4[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long LMON : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long LMON : 1;
+#endif
+	} BIT;
+	} PSR;
+	char           wk5[20];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RMD : 20;
+			unsigned long  : 12;
+#else
+			unsigned long  : 12;
+			unsigned long RMD : 20;
+#endif
+	} BIT;
+	} RDMLR;
+	char           wk6[12];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IPG : 5;
+			unsigned long  : 27;
+#else
+			unsigned long  : 27;
+			unsigned long IPG : 5;
+#endif
+	} BIT;
+	} IPGR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long AP : 16;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long AP : 16;
+#endif
+	} BIT;
+	} APR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MP : 16;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long MP : 16;
+#endif
+	} BIT;
+	} MPR;
+	char           wk7[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RPAUSE : 8;
+			unsigned long  : 24;
+#else
+			unsigned long  : 24;
+			unsigned long RPAUSE : 8;
+#endif
+	} BIT;
+	} RFCF;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TPAUSE : 16;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long TPAUSE : 16;
+#endif
+	} BIT;
+	} TPAUSER;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TXP : 8;
+			unsigned long  : 24;
+#else
+			unsigned long  : 24;
+			unsigned long TXP : 8;
+#endif
+	} BIT;
+	} TPAUSECR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long BCF : 16;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long BCF : 16;
+#endif
+	} BIT;
+	} BCFRR;
+	char           wk8[80];
+	unsigned long  MAHR;
+	char           wk9[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MA : 16;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long MA : 16;
+#endif
+	} BIT;
+	} MALR;
+	char           wk10[4];
+	unsigned long  TROCR;
+	unsigned long  CDCR;
+	unsigned long  LCCR;
+	unsigned long  CNDCR;
+	char           wk11[4];
+	unsigned long  CEFCR;
+	unsigned long  FRECR;
+	unsigned long  TSFRCR;
+	unsigned long  TLFRCR;
+	unsigned long  RFCR;
+	unsigned long  MAFCR;
+} st_etherc_t;
+
+typedef struct st_exdmac {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DMST : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DMST : 1;
+#endif
+	} BIT;
+	} EDMAST;
+	char           wk0[479];
+	unsigned long  CLSBR0;
+	unsigned long  CLSBR1;
+	unsigned long  CLSBR2;
+	unsigned long  CLSBR3;
+	unsigned long  CLSBR4;
+	unsigned long  CLSBR5;
+	unsigned long  CLSBR6;
+	unsigned long  CLSBR7;
+} st_exdmac_t;
+
+typedef struct st_exdmac0 {
+	void          *EDMSAR;
+	void          *EDMDAR;
+	unsigned long  EDMCRA;
+	unsigned short EDMCRB;
+	char           wk0[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DCTG : 2;
+			unsigned short  : 6;
+			unsigned short SZ : 2;
+			unsigned short  : 2;
+			unsigned short DTS : 2;
+			unsigned short MD : 2;
+#else
+			unsigned short MD : 2;
+			unsigned short DTS : 2;
+			unsigned short  : 2;
+			unsigned short SZ : 2;
+			unsigned short  : 6;
+			unsigned short DCTG : 2;
+#endif
+	} BIT;
+	} EDMTMD;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DACKSEL : 1;
+			unsigned char DACKW : 1;
+			unsigned char DACKE : 1;
+			unsigned char DACKS : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char DACKS : 1;
+			unsigned char DACKE : 1;
+			unsigned char DACKW : 1;
+			unsigned char DACKSEL : 1;
+#endif
+	} BIT;
+	} EDMOMD;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DARIE : 1;
+			unsigned char SARIE : 1;
+			unsigned char RPTIE : 1;
+			unsigned char ESIE : 1;
+			unsigned char DTIE : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char DTIE : 1;
+			unsigned char ESIE : 1;
+			unsigned char RPTIE : 1;
+			unsigned char SARIE : 1;
+			unsigned char DARIE : 1;
+#endif
+	} BIT;
+	} EDMINT;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DARA : 5;
+			unsigned long  : 1;
+			unsigned long DM : 2;
+			unsigned long SARA : 5;
+			unsigned long  : 1;
+			unsigned long SM : 2;
+			unsigned long DIR : 1;
+			unsigned long AMS : 1;
+			unsigned long  : 14;
+#else
+			unsigned long  : 14;
+			unsigned long AMS : 1;
+			unsigned long DIR : 1;
+			unsigned long SM : 2;
+			unsigned long  : 1;
+			unsigned long SARA : 5;
+			unsigned long DM : 2;
+			unsigned long  : 1;
+			unsigned long DARA : 5;
+#endif
+	} BIT;
+	} EDMAMD;
+	unsigned long  EDMOFR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DTE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DTE : 1;
+#endif
+	} BIT;
+	} EDMCNT;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SWREQ : 1;
+			unsigned char  : 3;
+			unsigned char CLRS : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char CLRS : 1;
+			unsigned char  : 3;
+			unsigned char SWREQ : 1;
+#endif
+	} BIT;
+	} EDMREQ;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ESIF : 1;
+			unsigned char  : 3;
+			unsigned char DTIF : 1;
+			unsigned char  : 2;
+			unsigned char ACT : 1;
+#else
+			unsigned char ACT : 1;
+			unsigned char  : 2;
+			unsigned char DTIF : 1;
+			unsigned char  : 3;
+			unsigned char ESIF : 1;
+#endif
+	} BIT;
+	} EDMSTS;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DREQS : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char DREQS : 2;
+#endif
+	} BIT;
+	} EDMRMD;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char EREQ : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char EREQ : 1;
+#endif
+	} BIT;
+	} EDMERF;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PREQ : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char PREQ : 1;
+#endif
+	} BIT;
+	} EDMPRF;
+} st_exdmac0_t;
+
+typedef struct st_exdmac1 {
+	void          *EDMSAR;
+	void          *EDMDAR;
+	unsigned long  EDMCRA;
+	unsigned short EDMCRB;
+	char           wk0[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DCTG : 2;
+			unsigned short  : 6;
+			unsigned short SZ : 2;
+			unsigned short  : 2;
+			unsigned short DTS : 2;
+			unsigned short MD : 2;
+#else
+			unsigned short MD : 2;
+			unsigned short DTS : 2;
+			unsigned short  : 2;
+			unsigned short SZ : 2;
+			unsigned short  : 6;
+			unsigned short DCTG : 2;
+#endif
+	} BIT;
+	} EDMTMD;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DACKSEL : 1;
+			unsigned char DACKW : 1;
+			unsigned char DACKE : 1;
+			unsigned char DACKS : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char DACKS : 1;
+			unsigned char DACKE : 1;
+			unsigned char DACKW : 1;
+			unsigned char DACKSEL : 1;
+#endif
+	} BIT;
+	} EDMOMD;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DARIE : 1;
+			unsigned char SARIE : 1;
+			unsigned char RPTIE : 1;
+			unsigned char ESIE : 1;
+			unsigned char DTIE : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char DTIE : 1;
+			unsigned char ESIE : 1;
+			unsigned char RPTIE : 1;
+			unsigned char SARIE : 1;
+			unsigned char DARIE : 1;
+#endif
+	} BIT;
+	} EDMINT;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DARA : 5;
+			unsigned long  : 1;
+			unsigned long DM : 2;
+			unsigned long SARA : 5;
+			unsigned long  : 1;
+			unsigned long SM : 2;
+			unsigned long DIR : 1;
+			unsigned long AMS : 1;
+			unsigned long  : 14;
+#else
+			unsigned long  : 14;
+			unsigned long AMS : 1;
+			unsigned long DIR : 1;
+			unsigned long SM : 2;
+			unsigned long  : 1;
+			unsigned long SARA : 5;
+			unsigned long DM : 2;
+			unsigned long  : 1;
+			unsigned long DARA : 5;
+#endif
+	} BIT;
+	} EDMAMD;
+	char           wk1[4];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DTE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DTE : 1;
+#endif
+	} BIT;
+	} EDMCNT;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SWREQ : 1;
+			unsigned char  : 3;
+			unsigned char CLRS : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char CLRS : 1;
+			unsigned char  : 3;
+			unsigned char SWREQ : 1;
+#endif
+	} BIT;
+	} EDMREQ;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ESIF : 1;
+			unsigned char  : 3;
+			unsigned char DTIF : 1;
+			unsigned char  : 2;
+			unsigned char ACT : 1;
+#else
+			unsigned char ACT : 1;
+			unsigned char  : 2;
+			unsigned char DTIF : 1;
+			unsigned char  : 3;
+			unsigned char ESIF : 1;
+#endif
+	} BIT;
+	} EDMSTS;
+	char           wk2[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DREQS : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char DREQS : 2;
+#endif
+	} BIT;
+	} EDMRMD;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char EREQ : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char EREQ : 1;
+#endif
+	} BIT;
+	} EDMERF;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PREQ : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char PREQ : 1;
+#endif
+	} BIT;
+	} EDMPRF;
+} st_exdmac1_t;
+
+typedef struct st_flash {
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ROMCEN : 1;
+			unsigned short  : 15;
+#else
+			unsigned short  : 15;
+			unsigned short ROMCEN : 1;
+#endif
+	} BIT;
+	} ROMCE;
+	char           wk0[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ROMCIV : 1;
+			unsigned short  : 15;
+#else
+			unsigned short  : 15;
+			unsigned short ROMCIV : 1;
+#endif
+	} BIT;
+	} ROMCIV;
+	char           wk1[45712];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char FLWE : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char FLWE : 2;
+#endif
+	} BIT;
+	} FWEPROR;
+	char           wk2[7798185];
+	unsigned char  EEPFCLK;
+	char           wk3[8143];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 3;
+			unsigned char DFAE : 1;
+			unsigned char CMDLK : 1;
+			unsigned char  : 2;
+			unsigned char CFAE : 1;
+#else
+			unsigned char CFAE : 1;
+			unsigned char  : 2;
+			unsigned char CMDLK : 1;
+			unsigned char DFAE : 1;
+			unsigned char  : 3;
+#endif
+	} BIT;
+	} FASTAT;
+	char           wk4[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 3;
+			unsigned char DFAEIE : 1;
+			unsigned char CMDLKIE : 1;
+			unsigned char  : 2;
+			unsigned char CFAEIE : 1;
+#else
+			unsigned char CFAEIE : 1;
+			unsigned char  : 2;
+			unsigned char CMDLKIE : 1;
+			unsigned char DFAEIE : 1;
+			unsigned char  : 3;
+#endif
+	} BIT;
+	} FAEINT;
+	char           wk5[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char FRDYIE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char FRDYIE : 1;
+#endif
+	} BIT;
+	} FRDYIE;
+	char           wk6[23];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FSADDR : 32;
+#else
+			unsigned long FSADDR : 32;
+#endif
+	} BIT;
+	} FSADDR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FEADDR : 32;
+#else
+			unsigned long FEADDR : 32;
+#endif
+	} BIT;
+	} FEADDR;
+	char           wk7[72];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 6;
+			unsigned long FLWEERR : 1;
+			unsigned long  : 1;
+			unsigned long PRGSPD : 1;
+			unsigned long ERSSPD : 1;
+			unsigned long DBFULL : 1;
+			unsigned long SUSRDY : 1;
+			unsigned long PRGERR : 1;
+			unsigned long ERSERR : 1;
+			unsigned long ILGLERR : 1;
+			unsigned long FRDY : 1;
+			unsigned long  : 4;
+			unsigned long OTERR : 1;
+			unsigned long SECERR : 1;
+			unsigned long FESETERR : 1;
+			unsigned long ILGCOMERR : 1;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long ILGCOMERR : 1;
+			unsigned long FESETERR : 1;
+			unsigned long SECERR : 1;
+			unsigned long OTERR : 1;
+			unsigned long  : 4;
+			unsigned long FRDY : 1;
+			unsigned long ILGLERR : 1;
+			unsigned long ERSERR : 1;
+			unsigned long PRGERR : 1;
+			unsigned long SUSRDY : 1;
+			unsigned long DBFULL : 1;
+			unsigned long ERSSPD : 1;
+			unsigned long PRGSPD : 1;
+			unsigned long  : 1;
+			unsigned long FLWEERR : 1;
+			unsigned long  : 6;
+#endif
+	} BIT;
+	} FSTATR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short FENTRYC : 1;
+			unsigned short  : 6;
+			unsigned short FENTRYD : 1;
+			unsigned short KEY : 8;
+#else
+			unsigned short KEY : 8;
+			unsigned short FENTRYD : 1;
+			unsigned short  : 6;
+			unsigned short FENTRYC : 1;
+#endif
+	} BIT;
+	} FENTRYR;
+	char           wk8[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short SUINIT : 1;
+			unsigned short  : 7;
+			unsigned short KEY : 8;
+#else
+			unsigned short KEY : 8;
+			unsigned short  : 7;
+			unsigned short SUINIT : 1;
+#endif
+	} BIT;
+	} FSUINITR;
+	char           wk9[18];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PCMDR : 8;
+			unsigned short CMDR : 8;
+#else
+			unsigned short CMDR : 8;
+			unsigned short PCMDR : 8;
+#endif
+	} BIT;
+	} FCMDR;
+	char           wk10[46];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCDIR : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char BCDIR : 1;
+#endif
+	} BIT;
+	} FBCCNT;
+	char           wk11[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCST : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char BCST : 1;
+#endif
+	} BIT;
+	} FBCSTAT;
+	char           wk12[3];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PSADR : 19;
+			unsigned long  : 13;
+#else
+			unsigned long  : 13;
+			unsigned long PSADR : 19;
+#endif
+	} BIT;
+	} FPSADDR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FAWS : 12;
+			unsigned long  : 3;
+			unsigned long FSPR : 1;
+			unsigned long FAWE : 12;
+			unsigned long  : 3;
+			unsigned long BTFLG : 1;
+#else
+			unsigned long BTFLG : 1;
+			unsigned long  : 3;
+			unsigned long FAWE : 12;
+			unsigned long FSPR : 1;
+			unsigned long  : 3;
+			unsigned long FAWS : 12;
+#endif
+	} BIT;
+	} FAWMON;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ESUSPMD : 1;
+			unsigned short  : 15;
+#else
+			unsigned short  : 15;
+			unsigned short ESUSPMD : 1;
+#endif
+	} BIT;
+	} FCPSR;
+	char           wk13[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PCKA : 8;
+			unsigned short KEY : 8;
+#else
+			unsigned short KEY : 8;
+			unsigned short PCKA : 8;
+#endif
+	} BIT;
+	} FPCKAR;
+	char           wk14[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short SAS : 2;
+			unsigned short  : 6;
+			unsigned short KEY : 8;
+#else
+			unsigned short KEY : 8;
+			unsigned short  : 6;
+			unsigned short SAS : 2;
+#endif
+	} BIT;
+	} FSUACR;
+} st_flash_t;
+
+typedef struct st_glcdc {
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long B : 8;
+			unsigned long G : 8;
+			unsigned long R : 8;
+			unsigned long A : 8;
+#else
+			unsigned long A : 8;
+			unsigned long R : 8;
+			unsigned long G : 8;
+			unsigned long B : 8;
+#endif
+	} BIT;
+	} GR1CLUT0[256];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long B : 8;
+			unsigned long G : 8;
+			unsigned long R : 8;
+			unsigned long A : 8;
+#else
+			unsigned long A : 8;
+			unsigned long R : 8;
+			unsigned long G : 8;
+			unsigned long B : 8;
+#endif
+	} BIT;
+	} GR1CLUT1[256];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long B : 8;
+			unsigned long G : 8;
+			unsigned long R : 8;
+			unsigned long A : 8;
+#else
+			unsigned long A : 8;
+			unsigned long R : 8;
+			unsigned long G : 8;
+			unsigned long B : 8;
+#endif
+	} BIT;
+	} GR2CLUT0[256];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long B : 8;
+			unsigned long G : 8;
+			unsigned long R : 8;
+			unsigned long A : 8;
+#else
+			unsigned long A : 8;
+			unsigned long R : 8;
+			unsigned long G : 8;
+			unsigned long B : 8;
+#endif
+	} BIT;
+	} GR2CLUT1[256];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EN : 1;
+			unsigned long  : 7;
+			unsigned long VEN : 1;
+			unsigned long  : 7;
+			unsigned long SWRST : 1;
+			unsigned long  : 15;
+#else
+			unsigned long  : 15;
+			unsigned long SWRST : 1;
+			unsigned long  : 7;
+			unsigned long VEN : 1;
+			unsigned long  : 7;
+			unsigned long EN : 1;
+#endif
+	} BIT;
+	} BGEN;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FH : 11;
+			unsigned long  : 5;
+			unsigned long FV : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long FV : 11;
+			unsigned long  : 5;
+			unsigned long FH : 11;
+#endif
+	} BIT;
+	} BGPERI;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long HP : 4;
+			unsigned long  : 12;
+			unsigned long VP : 4;
+			unsigned long  : 12;
+#else
+			unsigned long  : 12;
+			unsigned long VP : 4;
+			unsigned long  : 12;
+			unsigned long HP : 4;
+#endif
+	} BIT;
+	} BGSYNC;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VW : 11;
+			unsigned long  : 5;
+			unsigned long VP : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long VP : 11;
+			unsigned long  : 5;
+			unsigned long VW : 11;
+#endif
+	} BIT;
+	} BGVSIZE;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long HW : 11;
+			unsigned long  : 5;
+			unsigned long HP : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long HP : 11;
+			unsigned long  : 5;
+			unsigned long HW : 11;
+#endif
+	} BIT;
+	} BGHSIZE;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long B : 8;
+			unsigned long G : 8;
+			unsigned long R : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long R : 8;
+			unsigned long G : 8;
+			unsigned long B : 8;
+#endif
+	} BIT;
+	} BGCOLOR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EN : 1;
+			unsigned long  : 7;
+			unsigned long VEN : 1;
+			unsigned long  : 7;
+			unsigned long SWRST : 1;
+			unsigned long  : 15;
+#else
+			unsigned long  : 15;
+			unsigned long SWRST : 1;
+			unsigned long  : 7;
+			unsigned long VEN : 1;
+			unsigned long  : 7;
+			unsigned long EN : 1;
+#endif
+	} BIT;
+	} BGMON;
+	char           wk0[228];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VEN : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long VEN : 1;
+#endif
+	} BIT;
+	} GR1VEN;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RENB : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long RENB : 1;
+#endif
+	} BIT;
+	} GR1FLMRD;
+	char           wk1[4];
+	unsigned long  GR1FLM2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 16;
+			unsigned long LNOFF : 16;
+#else
+			unsigned long LNOFF : 16;
+			unsigned long  : 16;
+#endif
+	} BIT;
+	} GR1FLM3;
+	char           wk2[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DATANUM : 16;
+			unsigned long LNNUM : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long LNNUM : 11;
+			unsigned long DATANUM : 16;
+#endif
+	} BIT;
+	} GR1FLM5;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 28;
+			unsigned long FORMAT : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long FORMAT : 3;
+			unsigned long  : 28;
+#endif
+	} BIT;
+	} GR1FLM6;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DISPSEL : 2;
+			unsigned long  : 2;
+			unsigned long GRCDISPON : 1;
+			unsigned long  : 3;
+			unsigned long ARCDISPON : 1;
+			unsigned long  : 3;
+			unsigned long ARCON : 1;
+			unsigned long  : 19;
+#else
+			unsigned long  : 19;
+			unsigned long ARCON : 1;
+			unsigned long  : 3;
+			unsigned long ARCDISPON : 1;
+			unsigned long  : 3;
+			unsigned long GRCDISPON : 1;
+			unsigned long  : 2;
+			unsigned long DISPSEL : 2;
+#endif
+	} BIT;
+	} GR1AB1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GRCVW : 11;
+			unsigned long  : 5;
+			unsigned long GRCVS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GRCVS : 11;
+			unsigned long  : 5;
+			unsigned long GRCVW : 11;
+#endif
+	} BIT;
+	} GR1AB2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GRCHW : 11;
+			unsigned long  : 5;
+			unsigned long GRCHS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GRCHS : 11;
+			unsigned long  : 5;
+			unsigned long GRCHW : 11;
+#endif
+	} BIT;
+	} GR1AB3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ARCVW : 11;
+			unsigned long  : 5;
+			unsigned long ARCVS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long ARCVS : 11;
+			unsigned long  : 5;
+			unsigned long ARCVW : 11;
+#endif
+	} BIT;
+	} GR1AB4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ARCHW : 11;
+			unsigned long  : 5;
+			unsigned long ARCHS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long ARCHS : 11;
+			unsigned long  : 5;
+			unsigned long ARCHW : 11;
+#endif
+	} BIT;
+	} GR1AB5;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ARCRATE : 8;
+			unsigned long  : 8;
+			unsigned long ARCCOEF : 9;
+			unsigned long  : 7;
+#else
+			unsigned long  : 7;
+			unsigned long ARCCOEF : 9;
+			unsigned long  : 8;
+			unsigned long ARCRATE : 8;
+#endif
+	} BIT;
+	} GR1AB6;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CKON : 1;
+			unsigned long  : 15;
+			unsigned long ARCDEF : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long ARCDEF : 8;
+			unsigned long  : 15;
+			unsigned long CKON : 1;
+#endif
+	} BIT;
+	} GR1AB7;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CKKR : 8;
+			unsigned long CKKB : 8;
+			unsigned long CKKG : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long CKKG : 8;
+			unsigned long CKKB : 8;
+			unsigned long CKKR : 8;
+#endif
+	} BIT;
+	} GR1AB8;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CKR : 8;
+			unsigned long CKB : 8;
+			unsigned long CKG : 8;
+			unsigned long CKA : 8;
+#else
+			unsigned long CKA : 8;
+			unsigned long CKG : 8;
+			unsigned long CKB : 8;
+			unsigned long CKR : 8;
+#endif
+	} BIT;
+	} GR1AB9;
+	char           wk3[8];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long R : 8;
+			unsigned long B : 8;
+			unsigned long G : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long G : 8;
+			unsigned long B : 8;
+			unsigned long R : 8;
+#endif
+	} BIT;
+	} GR1BASE;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long LINE : 11;
+			unsigned long  : 5;
+			unsigned long SEL : 1;
+			unsigned long  : 15;
+#else
+			unsigned long  : 15;
+			unsigned long SEL : 1;
+			unsigned long  : 5;
+			unsigned long LINE : 11;
+#endif
+	} BIT;
+	} GR1CLUTINT;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ARCST : 1;
+			unsigned long  : 15;
+			unsigned long UFST : 1;
+			unsigned long  : 15;
+#else
+			unsigned long  : 15;
+			unsigned long UFST : 1;
+			unsigned long  : 15;
+			unsigned long ARCST : 1;
+#endif
+	} BIT;
+	} GR1MON;
+	char           wk4[168];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VEN : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long VEN : 1;
+#endif
+	} BIT;
+	} GR2VEN;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RENB : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long RENB : 1;
+#endif
+	} BIT;
+	} GR2FLMRD;
+	char           wk5[4];
+	unsigned long  GR2FLM2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 16;
+			unsigned long LNOFF : 16;
+#else
+			unsigned long LNOFF : 16;
+			unsigned long  : 16;
+#endif
+	} BIT;
+	} GR2FLM3;
+	char           wk6[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DATANUM : 16;
+			unsigned long LNNUM : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long LNNUM : 11;
+			unsigned long DATANUM : 16;
+#endif
+	} BIT;
+	} GR2FLM5;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 28;
+			unsigned long FORMAT : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long FORMAT : 3;
+			unsigned long  : 28;
+#endif
+	} BIT;
+	} GR2FLM6;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DISPSEL : 2;
+			unsigned long  : 2;
+			unsigned long GRCDISPON : 1;
+			unsigned long  : 3;
+			unsigned long ARCDISPON : 1;
+			unsigned long  : 3;
+			unsigned long ARCON : 1;
+			unsigned long  : 19;
+#else
+			unsigned long  : 19;
+			unsigned long ARCON : 1;
+			unsigned long  : 3;
+			unsigned long ARCDISPON : 1;
+			unsigned long  : 3;
+			unsigned long GRCDISPON : 1;
+			unsigned long  : 2;
+			unsigned long DISPSEL : 2;
+#endif
+	} BIT;
+	} GR2AB1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GRCVW : 11;
+			unsigned long  : 5;
+			unsigned long GRCVS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GRCVS : 11;
+			unsigned long  : 5;
+			unsigned long GRCVW : 11;
+#endif
+	} BIT;
+	} GR2AB2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GRCHW : 11;
+			unsigned long  : 5;
+			unsigned long GRCHS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GRCHS : 11;
+			unsigned long  : 5;
+			unsigned long GRCHW : 11;
+#endif
+	} BIT;
+	} GR2AB3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ARCVW : 11;
+			unsigned long  : 5;
+			unsigned long ARCVS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long ARCVS : 11;
+			unsigned long  : 5;
+			unsigned long ARCVW : 11;
+#endif
+	} BIT;
+	} GR2AB4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ARCHW : 11;
+			unsigned long  : 5;
+			unsigned long ARCHS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long ARCHS : 11;
+			unsigned long  : 5;
+			unsigned long ARCHW : 11;
+#endif
+	} BIT;
+	} GR2AB5;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ARCRATE : 8;
+			unsigned long  : 8;
+			unsigned long ARCCOEF : 9;
+			unsigned long  : 7;
+#else
+			unsigned long  : 7;
+			unsigned long ARCCOEF : 9;
+			unsigned long  : 8;
+			unsigned long ARCRATE : 8;
+#endif
+	} BIT;
+	} GR2AB6;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CKON : 1;
+			unsigned long  : 15;
+			unsigned long ARCDEF : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long ARCDEF : 8;
+			unsigned long  : 15;
+			unsigned long CKON : 1;
+#endif
+	} BIT;
+	} GR2AB7;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CKKR : 8;
+			unsigned long CKKB : 8;
+			unsigned long CKKG : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long CKKG : 8;
+			unsigned long CKKB : 8;
+			unsigned long CKKR : 8;
+#endif
+	} BIT;
+	} GR2AB8;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CKR : 8;
+			unsigned long CKB : 8;
+			unsigned long CKG : 8;
+			unsigned long CKA : 8;
+#else
+			unsigned long CKA : 8;
+			unsigned long CKG : 8;
+			unsigned long CKB : 8;
+			unsigned long CKR : 8;
+#endif
+	} BIT;
+	} GR2AB9;
+	char           wk7[8];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long R : 8;
+			unsigned long B : 8;
+			unsigned long G : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long G : 8;
+			unsigned long B : 8;
+			unsigned long R : 8;
+#endif
+	} BIT;
+	} GR2BASE;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long LINE : 11;
+			unsigned long  : 5;
+			unsigned long SEL : 1;
+			unsigned long  : 15;
+#else
+			unsigned long  : 15;
+			unsigned long SEL : 1;
+			unsigned long  : 5;
+			unsigned long LINE : 11;
+#endif
+	} BIT;
+	} GR2CLUTINT;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long ARCST : 1;
+			unsigned long  : 15;
+			unsigned long UFST : 1;
+			unsigned long  : 15;
+#else
+			unsigned long  : 15;
+			unsigned long UFST : 1;
+			unsigned long  : 15;
+			unsigned long ARCST : 1;
+#endif
+	} BIT;
+	} GR2MON;
+	char           wk8[168];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VEN : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long VEN : 1;
+#endif
+	} BIT;
+	} GAMGVEN;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAMON : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long GAMON : 1;
+#endif
+	} BIT;
+	} GAMSW;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN01 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN00 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN00 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN01 : 11;
+#endif
+	} BIT;
+	} GAMGLUT1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN03 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN02 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN02 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN03 : 11;
+#endif
+	} BIT;
+	} GAMGLUT2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN05 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN04 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN04 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN05 : 11;
+#endif
+	} BIT;
+	} GAMGLUT3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN07 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN06 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN06 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN07 : 11;
+#endif
+	} BIT;
+	} GAMGLUT4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN09 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN08 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN08 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN09 : 11;
+#endif
+	} BIT;
+	} GAMGLUT5;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN11 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN10 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN10 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN11 : 11;
+#endif
+	} BIT;
+	} GAMGLUT6;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN13 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN12 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN12 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN13 : 11;
+#endif
+	} BIT;
+	} GAMGLUT7;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN15 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN14 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN14 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN15 : 11;
+#endif
+	} BIT;
+	} GAMGLUT8;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH03 : 10;
+			unsigned long TH02 : 10;
+			unsigned long TH01 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH01 : 10;
+			unsigned long TH02 : 10;
+			unsigned long TH03 : 10;
+#endif
+	} BIT;
+	} GAMGAREA1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH06 : 10;
+			unsigned long TH05 : 10;
+			unsigned long TH04 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH04 : 10;
+			unsigned long TH05 : 10;
+			unsigned long TH06 : 10;
+#endif
+	} BIT;
+	} GAMGAREA2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH09 : 10;
+			unsigned long TH08 : 10;
+			unsigned long TH07 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH07 : 10;
+			unsigned long TH08 : 10;
+			unsigned long TH09 : 10;
+#endif
+	} BIT;
+	} GAMGAREA3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH12 : 10;
+			unsigned long TH11 : 10;
+			unsigned long TH10 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH10 : 10;
+			unsigned long TH11 : 10;
+			unsigned long TH12 : 10;
+#endif
+	} BIT;
+	} GAMGAREA4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH15 : 10;
+			unsigned long TH14 : 10;
+			unsigned long TH13 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH13 : 10;
+			unsigned long TH14 : 10;
+			unsigned long TH15 : 10;
+#endif
+	} BIT;
+	} GAMGAREA5;
+	char           wk9[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VEN : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long VEN : 1;
+#endif
+	} BIT;
+	} GAMBVEN;
+	char           wk10[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN01 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN00 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN00 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN01 : 11;
+#endif
+	} BIT;
+	} GAMBLUT1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN03 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN02 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN02 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN03 : 11;
+#endif
+	} BIT;
+	} GAMBLUT2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN05 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN04 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN04 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN05 : 11;
+#endif
+	} BIT;
+	} GAMBLUT3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN07 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN06 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN06 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN07 : 11;
+#endif
+	} BIT;
+	} GAMBLUT4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN09 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN08 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN08 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN09 : 11;
+#endif
+	} BIT;
+	} GAMBLUT5;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN11 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN10 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN10 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN11 : 11;
+#endif
+	} BIT;
+	} GAMBLUT6;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN13 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN12 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN12 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN13 : 11;
+#endif
+	} BIT;
+	} GAMBLUT7;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN15 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN14 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN14 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN15 : 11;
+#endif
+	} BIT;
+	} GAMBLUT8;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH03 : 10;
+			unsigned long TH02 : 10;
+			unsigned long TH01 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH01 : 10;
+			unsigned long TH02 : 10;
+			unsigned long TH03 : 10;
+#endif
+	} BIT;
+	} GAMBAREA1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH06 : 10;
+			unsigned long TH05 : 10;
+			unsigned long TH04 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH04 : 10;
+			unsigned long TH05 : 10;
+			unsigned long TH06 : 10;
+#endif
+	} BIT;
+	} GAMBAREA2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH09 : 10;
+			unsigned long TH08 : 10;
+			unsigned long TH07 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH07 : 10;
+			unsigned long TH08 : 10;
+			unsigned long TH09 : 10;
+#endif
+	} BIT;
+	} GAMBAREA3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH12 : 10;
+			unsigned long TH11 : 10;
+			unsigned long TH10 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH10 : 10;
+			unsigned long TH11 : 10;
+			unsigned long TH12 : 10;
+#endif
+	} BIT;
+	} GAMBAREA4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH15 : 10;
+			unsigned long TH14 : 10;
+			unsigned long TH13 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH13 : 10;
+			unsigned long TH14 : 10;
+			unsigned long TH15 : 10;
+#endif
+	} BIT;
+	} GAMBAREA5;
+	char           wk11[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VEN : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long VEN : 1;
+#endif
+	} BIT;
+	} GAMRVEN;
+	char           wk12[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN01 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN00 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN00 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN01 : 11;
+#endif
+	} BIT;
+	} GAMRLUT1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN03 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN02 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN02 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN03 : 11;
+#endif
+	} BIT;
+	} GAMRLUT2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN05 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN04 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN04 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN05 : 11;
+#endif
+	} BIT;
+	} GAMRLUT3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN07 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN06 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN06 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN07 : 11;
+#endif
+	} BIT;
+	} GAMRLUT4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN09 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN08 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN08 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN09 : 11;
+#endif
+	} BIT;
+	} GAMRLUT5;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN11 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN10 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN10 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN11 : 11;
+#endif
+	} BIT;
+	} GAMRLUT6;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN13 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN12 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN12 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN13 : 11;
+#endif
+	} BIT;
+	} GAMRLUT7;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long GAIN15 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN14 : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long GAIN14 : 11;
+			unsigned long  : 5;
+			unsigned long GAIN15 : 11;
+#endif
+	} BIT;
+	} GAMRLUT8;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH03 : 10;
+			unsigned long TH02 : 10;
+			unsigned long TH01 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH01 : 10;
+			unsigned long TH02 : 10;
+			unsigned long TH03 : 10;
+#endif
+	} BIT;
+	} GAMRAREA1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH06 : 10;
+			unsigned long TH05 : 10;
+			unsigned long TH04 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH04 : 10;
+			unsigned long TH05 : 10;
+			unsigned long TH06 : 10;
+#endif
+	} BIT;
+	} GAMRAREA2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH09 : 10;
+			unsigned long TH08 : 10;
+			unsigned long TH07 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH07 : 10;
+			unsigned long TH08 : 10;
+			unsigned long TH09 : 10;
+#endif
+	} BIT;
+	} GAMRAREA3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH12 : 10;
+			unsigned long TH11 : 10;
+			unsigned long TH10 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH10 : 10;
+			unsigned long TH11 : 10;
+			unsigned long TH12 : 10;
+#endif
+	} BIT;
+	} GAMRAREA4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long TH15 : 10;
+			unsigned long TH14 : 10;
+			unsigned long TH13 : 10;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long TH13 : 10;
+			unsigned long TH14 : 10;
+			unsigned long TH15 : 10;
+#endif
+	} BIT;
+	} GAMRAREA5;
+	char           wk13[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VEN : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long VEN : 1;
+#endif
+	} BIT;
+	} OUTVEN;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PHASE : 2;
+			unsigned long  : 2;
+			unsigned long DIRSEL : 1;
+			unsigned long  : 4;
+			unsigned long FRQSEL : 1;
+			unsigned long  : 2;
+			unsigned long FORMAT : 2;
+			unsigned long  : 10;
+			unsigned long SWAPON : 1;
+			unsigned long  : 3;
+			unsigned long ENDIANON : 1;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long ENDIANON : 1;
+			unsigned long  : 3;
+			unsigned long SWAPON : 1;
+			unsigned long  : 10;
+			unsigned long FORMAT : 2;
+			unsigned long  : 2;
+			unsigned long FRQSEL : 1;
+			unsigned long  : 4;
+			unsigned long DIRSEL : 1;
+			unsigned long  : 2;
+			unsigned long PHASE : 2;
+#endif
+	} BIT;
+	} OUTSET;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long BRTG : 10;
+			unsigned long  : 22;
+#else
+			unsigned long  : 22;
+			unsigned long BRTG : 10;
+#endif
+	} BIT;
+	} BRIGHT1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long BRTR : 10;
+			unsigned long  : 6;
+			unsigned long BRTB : 10;
+			unsigned long  : 6;
+#else
+			unsigned long  : 6;
+			unsigned long BRTB : 10;
+			unsigned long  : 6;
+			unsigned long BRTR : 10;
+#endif
+	} BIT;
+	} BRIGHT2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CONTR : 8;
+			unsigned long CONTB : 8;
+			unsigned long CONTG : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long CONTG : 8;
+			unsigned long CONTB : 8;
+			unsigned long CONTR : 8;
+#endif
+	} BIT;
+	} CONTRAST;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PD : 2;
+			unsigned long  : 2;
+			unsigned long PC : 2;
+			unsigned long  : 2;
+			unsigned long PB : 2;
+			unsigned long  : 2;
+			unsigned long PA : 2;
+			unsigned long  : 2;
+			unsigned long FORM : 2;
+			unsigned long  : 2;
+			unsigned long SEL : 2;
+			unsigned long  : 10;
+#else
+			unsigned long  : 10;
+			unsigned long SEL : 2;
+			unsigned long  : 2;
+			unsigned long FORM : 2;
+			unsigned long  : 2;
+			unsigned long PA : 2;
+			unsigned long  : 2;
+			unsigned long PB : 2;
+			unsigned long  : 2;
+			unsigned long PC : 2;
+			unsigned long  : 2;
+			unsigned long PD : 2;
+#endif
+	} BIT;
+	} PANELDTHA;
+	char           wk14[12];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 3;
+			unsigned long TCON3EDG : 1;
+			unsigned long TCON2EDG : 1;
+			unsigned long TCON1EDG : 1;
+			unsigned long TCON0EDG : 1;
+			unsigned long  : 1;
+			unsigned long LCDEDG : 1;
+			unsigned long  : 3;
+			unsigned long FRONTGAM : 1;
+			unsigned long  : 19;
+#else
+			unsigned long  : 19;
+			unsigned long FRONTGAM : 1;
+			unsigned long  : 3;
+			unsigned long LCDEDG : 1;
+			unsigned long  : 1;
+			unsigned long TCON0EDG : 1;
+			unsigned long TCON1EDG : 1;
+			unsigned long TCON2EDG : 1;
+			unsigned long TCON3EDG : 1;
+			unsigned long  : 3;
+#endif
+	} BIT;
+	} CLKPHASE;
+	char           wk15[28];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long OFFSET : 11;
+			unsigned long  : 5;
+			unsigned long HALF : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long HALF : 11;
+			unsigned long  : 5;
+			unsigned long OFFSET : 11;
+#endif
+	} BIT;
+	} TCONTIM;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VW : 11;
+			unsigned long  : 5;
+			unsigned long VS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long VS : 11;
+			unsigned long  : 5;
+			unsigned long VW : 11;
+#endif
+	} BIT;
+	} TCONSTVA1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long SEL : 3;
+			unsigned long  : 1;
+			unsigned long INV : 1;
+			unsigned long  : 27;
+#else
+			unsigned long  : 27;
+			unsigned long INV : 1;
+			unsigned long  : 1;
+			unsigned long SEL : 3;
+#endif
+	} BIT;
+	} TCONSTVA2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VW : 11;
+			unsigned long  : 5;
+			unsigned long VS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long VS : 11;
+			unsigned long  : 5;
+			unsigned long VW : 11;
+#endif
+	} BIT;
+	} TCONSTVB1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long SEL : 3;
+			unsigned long  : 1;
+			unsigned long INV : 1;
+			unsigned long  : 27;
+#else
+			unsigned long  : 27;
+			unsigned long INV : 1;
+			unsigned long  : 1;
+			unsigned long SEL : 3;
+#endif
+	} BIT;
+	} TCONSTVB2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long HW : 11;
+			unsigned long  : 5;
+			unsigned long HS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long HS : 11;
+			unsigned long  : 5;
+			unsigned long HW : 11;
+#endif
+	} BIT;
+	} TCONSTHA1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long SEL : 3;
+			unsigned long  : 1;
+			unsigned long INV : 1;
+			unsigned long  : 3;
+			unsigned long HSSEL : 1;
+			unsigned long  : 23;
+#else
+			unsigned long  : 23;
+			unsigned long HSSEL : 1;
+			unsigned long  : 3;
+			unsigned long INV : 1;
+			unsigned long  : 1;
+			unsigned long SEL : 3;
+#endif
+	} BIT;
+	} TCONSTHA2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long HW : 11;
+			unsigned long  : 5;
+			unsigned long HS : 11;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long HS : 11;
+			unsigned long  : 5;
+			unsigned long HW : 11;
+#endif
+	} BIT;
+	} TCONSTHB1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long SEL : 3;
+			unsigned long  : 1;
+			unsigned long INV : 1;
+			unsigned long  : 3;
+			unsigned long HSSEL : 1;
+			unsigned long  : 23;
+#else
+			unsigned long  : 23;
+			unsigned long HSSEL : 1;
+			unsigned long  : 3;
+			unsigned long INV : 1;
+			unsigned long  : 1;
+			unsigned long SEL : 3;
+#endif
+	} BIT;
+	} TCONSTHB2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long INV : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long INV : 1;
+#endif
+	} BIT;
+	} TCONDE;
+	char           wk16[20];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VPOSDTC : 1;
+			unsigned long GR1UFDTC : 1;
+			unsigned long GR2UFDTC : 1;
+			unsigned long  : 29;
+#else
+			unsigned long  : 29;
+			unsigned long GR2UFDTC : 1;
+			unsigned long GR1UFDTC : 1;
+			unsigned long VPOSDTC : 1;
+#endif
+	} BIT;
+	} DTCTEN;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VPOSINTEN : 1;
+			unsigned long GR1UFINTEN : 1;
+			unsigned long GR2UFINTEN : 1;
+			unsigned long  : 29;
+#else
+			unsigned long  : 29;
+			unsigned long GR2UFINTEN : 1;
+			unsigned long GR1UFINTEN : 1;
+			unsigned long VPOSINTEN : 1;
+#endif
+	} BIT;
+	} INTEN;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VPOSCLR : 1;
+			unsigned long GR1UFCLR : 1;
+			unsigned long GR2UFCLR : 1;
+			unsigned long  : 29;
+#else
+			unsigned long  : 29;
+			unsigned long GR2UFCLR : 1;
+			unsigned long GR1UFCLR : 1;
+			unsigned long VPOSCLR : 1;
+#endif
+	} BIT;
+	} STCLR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VPOS : 1;
+			unsigned long GR1UF : 1;
+			unsigned long GR2UF : 1;
+			unsigned long  : 29;
+#else
+			unsigned long  : 29;
+			unsigned long GR2UF : 1;
+			unsigned long GR1UF : 1;
+			unsigned long VPOS : 1;
+#endif
+	} BIT;
+	} STMON;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DCDR : 6;
+			unsigned long CLKEN : 1;
+			unsigned long  : 1;
+			unsigned long CLKSEL : 1;
+			unsigned long  : 3;
+			unsigned long PIXSEL : 1;
+			unsigned long  : 19;
+#else
+			unsigned long  : 19;
+			unsigned long PIXSEL : 1;
+			unsigned long  : 3;
+			unsigned long CLKSEL : 1;
+			unsigned long  : 1;
+			unsigned long CLKEN : 1;
+			unsigned long DCDR : 6;
+#endif
+	} BIT;
+	} PANELCLK;
+} st_glcdc_t;
+
+typedef struct st_icu {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IR : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char IR : 1;
+#endif
+	} BIT;
+	} IR[256];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DTCE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DTCE : 1;
+#endif
+	} BIT;
+	} DTCER[256];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IEN0 : 1;
+			unsigned char IEN1 : 1;
+			unsigned char IEN2 : 1;
+			unsigned char IEN3 : 1;
+			unsigned char IEN4 : 1;
+			unsigned char IEN5 : 1;
+			unsigned char IEN6 : 1;
+			unsigned char IEN7 : 1;
+#else
+			unsigned char IEN7 : 1;
+			unsigned char IEN6 : 1;
+			unsigned char IEN5 : 1;
+			unsigned char IEN4 : 1;
+			unsigned char IEN3 : 1;
+			unsigned char IEN2 : 1;
+			unsigned char IEN1 : 1;
+			unsigned char IEN0 : 1;
+#endif
+	} BIT;
+	} IER[32];
+	char           wk0[192];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SWINT : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char SWINT : 1;
+#endif
+	} BIT;
+	} SWINTR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SWINT2 : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char SWINT2 : 1;
+#endif
+	} BIT;
+	} SWINT2R;
+	char           wk1[14];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short FVCT : 8;
+			unsigned short  : 7;
+			unsigned short FIEN : 1;
+#else
+			unsigned short FIEN : 1;
+			unsigned short  : 7;
+			unsigned short FVCT : 8;
+#endif
+	} BIT;
+	} FIR;
+	char           wk2[14];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IPR : 4;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char IPR : 4;
+#endif
+	} BIT;
+	} IPR[256];
+	unsigned char  DMRSR0;
+	char           wk3[3];
+	unsigned char  DMRSR1;
+	char           wk4[3];
+	unsigned char  DMRSR2;
+	char           wk5[3];
+	unsigned char  DMRSR3;
+	char           wk6[3];
+	unsigned char  DMRSR4;
+	char           wk7[3];
+	unsigned char  DMRSR5;
+	char           wk8[3];
+	unsigned char  DMRSR6;
+	char           wk9[3];
+	unsigned char  DMRSR7;
+	char           wk10[227];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 2;
+			unsigned char IRQMD : 2;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char IRQMD : 2;
+			unsigned char  : 2;
+#endif
+	} BIT;
+	} IRQCR[16];
+	char           wk11[16];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char FLTEN0 : 1;
+			unsigned char FLTEN1 : 1;
+			unsigned char FLTEN2 : 1;
+			unsigned char FLTEN3 : 1;
+			unsigned char FLTEN4 : 1;
+			unsigned char FLTEN5 : 1;
+			unsigned char FLTEN6 : 1;
+			unsigned char FLTEN7 : 1;
+#else
+			unsigned char FLTEN7 : 1;
+			unsigned char FLTEN6 : 1;
+			unsigned char FLTEN5 : 1;
+			unsigned char FLTEN4 : 1;
+			unsigned char FLTEN3 : 1;
+			unsigned char FLTEN2 : 1;
+			unsigned char FLTEN1 : 1;
+			unsigned char FLTEN0 : 1;
+#endif
+	} BIT;
+	} IRQFLTE0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char FLTEN8 : 1;
+			unsigned char FLTEN9 : 1;
+			unsigned char FLTEN10 : 1;
+			unsigned char FLTEN11 : 1;
+			unsigned char FLTEN12 : 1;
+			unsigned char FLTEN13 : 1;
+			unsigned char FLTEN14 : 1;
+			unsigned char FLTEN15 : 1;
+#else
+			unsigned char FLTEN15 : 1;
+			unsigned char FLTEN14 : 1;
+			unsigned char FLTEN13 : 1;
+			unsigned char FLTEN12 : 1;
+			unsigned char FLTEN11 : 1;
+			unsigned char FLTEN10 : 1;
+			unsigned char FLTEN9 : 1;
+			unsigned char FLTEN8 : 1;
+#endif
+	} BIT;
+	} IRQFLTE1;
+	char           wk12[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short FCLKSEL0 : 2;
+			unsigned short FCLKSEL1 : 2;
+			unsigned short FCLKSEL2 : 2;
+			unsigned short FCLKSEL3 : 2;
+			unsigned short FCLKSEL4 : 2;
+			unsigned short FCLKSEL5 : 2;
+			unsigned short FCLKSEL6 : 2;
+			unsigned short FCLKSEL7 : 2;
+#else
+			unsigned short FCLKSEL7 : 2;
+			unsigned short FCLKSEL6 : 2;
+			unsigned short FCLKSEL5 : 2;
+			unsigned short FCLKSEL4 : 2;
+			unsigned short FCLKSEL3 : 2;
+			unsigned short FCLKSEL2 : 2;
+			unsigned short FCLKSEL1 : 2;
+			unsigned short FCLKSEL0 : 2;
+#endif
+	} BIT;
+	} IRQFLTC0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short FCLKSEL8 : 2;
+			unsigned short FCLKSEL9 : 2;
+			unsigned short FCLKSEL10 : 2;
+			unsigned short FCLKSEL11 : 2;
+			unsigned short FCLKSEL12 : 2;
+			unsigned short FCLKSEL13 : 2;
+			unsigned short FCLKSEL14 : 2;
+			unsigned short FCLKSEL15 : 2;
+#else
+			unsigned short FCLKSEL15 : 2;
+			unsigned short FCLKSEL14 : 2;
+			unsigned short FCLKSEL13 : 2;
+			unsigned short FCLKSEL12 : 2;
+			unsigned short FCLKSEL11 : 2;
+			unsigned short FCLKSEL10 : 2;
+			unsigned short FCLKSEL9 : 2;
+			unsigned short FCLKSEL8 : 2;
+#endif
+	} BIT;
+	} IRQFLTC1;
+	char           wk13[84];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NMIST : 1;
+			unsigned char OSTST : 1;
+			unsigned char WDTST : 1;
+			unsigned char IWDTST : 1;
+			unsigned char LVD1ST : 1;
+			unsigned char LVD2ST : 1;
+			unsigned char RAMST : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char RAMST : 1;
+			unsigned char LVD2ST : 1;
+			unsigned char LVD1ST : 1;
+			unsigned char IWDTST : 1;
+			unsigned char WDTST : 1;
+			unsigned char OSTST : 1;
+			unsigned char NMIST : 1;
+#endif
+	} BIT;
+	} NMISR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NMIEN : 1;
+			unsigned char OSTEN : 1;
+			unsigned char WDTEN : 1;
+			unsigned char IWDTEN : 1;
+			unsigned char LVD1EN : 1;
+			unsigned char LVD2EN : 1;
+			unsigned char RAMEN : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char RAMEN : 1;
+			unsigned char LVD2EN : 1;
+			unsigned char LVD1EN : 1;
+			unsigned char IWDTEN : 1;
+			unsigned char WDTEN : 1;
+			unsigned char OSTEN : 1;
+			unsigned char NMIEN : 1;
+#endif
+	} BIT;
+	} NMIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NMICLR : 1;
+			unsigned char OSTCLR : 1;
+			unsigned char WDTCLR : 1;
+			unsigned char IWDTCLR : 1;
+			unsigned char LVD1CLR : 1;
+			unsigned char LVD2CLR : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char LVD2CLR : 1;
+			unsigned char LVD1CLR : 1;
+			unsigned char IWDTCLR : 1;
+			unsigned char WDTCLR : 1;
+			unsigned char OSTCLR : 1;
+			unsigned char NMICLR : 1;
+#endif
+	} BIT;
+	} NMICLR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 3;
+			unsigned char NMIMD : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char NMIMD : 1;
+			unsigned char  : 3;
+#endif
+	} BIT;
+	} NMICR;
+	char           wk14[12];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFLTEN : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char NFLTEN : 1;
+#endif
+	} BIT;
+	} NMIFLTE;
+	char           wk15[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFCLKSEL : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char NFCLKSEL : 2;
+#endif
+	} BIT;
+	} NMIFLTC;
+	char           wk16[107];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IS0 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS31 : 1;
+#else
+			unsigned long IS31 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS0 : 1;
+#endif
+	} BIT;
+	} GRPBE0;
+	char           wk17[44];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IS0 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS31 : 1;
+#else
+			unsigned long IS31 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS0 : 1;
+#endif
+	} BIT;
+	} GRPBL0;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IS0 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS31 : 1;
+#else
+			unsigned long IS31 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS0 : 1;
+#endif
+	} BIT;
+	} GRPBL1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IS0 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS31 : 1;
+#else
+			unsigned long IS31 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS0 : 1;
+#endif
+	} BIT;
+	} GRPBL2;
+	char           wk18[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EN0 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN31 : 1;
+#else
+			unsigned long EN31 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN0 : 1;
+#endif
+	} BIT;
+	} GENBE0;
+	char           wk19[44];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EN0 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN31 : 1;
+#else
+			unsigned long EN31 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN0 : 1;
+#endif
+	} BIT;
+	} GENBL0;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EN0 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN31 : 1;
+#else
+			unsigned long EN31 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN0 : 1;
+#endif
+	} BIT;
+	} GENBL1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EN0 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN31 : 1;
+#else
+			unsigned long EN31 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN0 : 1;
+#endif
+	} BIT;
+	} GENBL2;
+	char           wk20[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CLR0 : 1;
+			unsigned long CLR1 : 1;
+			unsigned long CLR2 : 1;
+			unsigned long CLR3 : 1;
+			unsigned long CLR4 : 1;
+			unsigned long CLR5 : 1;
+			unsigned long CLR6 : 1;
+			unsigned long CLR7 : 1;
+			unsigned long CLR8 : 1;
+			unsigned long CLR9 : 1;
+			unsigned long CLR10 : 1;
+			unsigned long CLR11 : 1;
+			unsigned long CLR12 : 1;
+			unsigned long CLR13 : 1;
+			unsigned long CLR14 : 1;
+			unsigned long CLR15 : 1;
+			unsigned long CLR16 : 1;
+			unsigned long CLR17 : 1;
+			unsigned long CLR18 : 1;
+			unsigned long CLR19 : 1;
+			unsigned long CLR20 : 1;
+			unsigned long CLR21 : 1;
+			unsigned long CLR22 : 1;
+			unsigned long CLR23 : 1;
+			unsigned long CLR24 : 1;
+			unsigned long CLR25 : 1;
+			unsigned long CLR26 : 1;
+			unsigned long CLR27 : 1;
+			unsigned long CLR28 : 1;
+			unsigned long CLR29 : 1;
+			unsigned long CLR30 : 1;
+			unsigned long CLR31 : 1;
+#else
+			unsigned long CLR31 : 1;
+			unsigned long CLR30 : 1;
+			unsigned long CLR29 : 1;
+			unsigned long CLR28 : 1;
+			unsigned long CLR27 : 1;
+			unsigned long CLR26 : 1;
+			unsigned long CLR25 : 1;
+			unsigned long CLR24 : 1;
+			unsigned long CLR23 : 1;
+			unsigned long CLR22 : 1;
+			unsigned long CLR21 : 1;
+			unsigned long CLR20 : 1;
+			unsigned long CLR19 : 1;
+			unsigned long CLR18 : 1;
+			unsigned long CLR17 : 1;
+			unsigned long CLR16 : 1;
+			unsigned long CLR15 : 1;
+			unsigned long CLR14 : 1;
+			unsigned long CLR13 : 1;
+			unsigned long CLR12 : 1;
+			unsigned long CLR11 : 1;
+			unsigned long CLR10 : 1;
+			unsigned long CLR9 : 1;
+			unsigned long CLR8 : 1;
+			unsigned long CLR7 : 1;
+			unsigned long CLR6 : 1;
+			unsigned long CLR5 : 1;
+			unsigned long CLR4 : 1;
+			unsigned long CLR3 : 1;
+			unsigned long CLR2 : 1;
+			unsigned long CLR1 : 1;
+			unsigned long CLR0 : 1;
+#endif
+	} BIT;
+	} GCRBE0;
+	char           wk21[124];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBR3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBR4;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBR5;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBR6;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBR7;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBR8;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBR9;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBRA;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIBRB;
+	char           wk22[116];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR128;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR129;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR130;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR131;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR132;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR133;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR134;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR135;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR136;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR137;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR138;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR139;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR140;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR141;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR142;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBXR143;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR144;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR145;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR146;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR147;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR148;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR149;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR150;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR151;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR152;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR153;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR154;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR155;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR156;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR157;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR158;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR159;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR160;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR161;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR162;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR163;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR164;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR165;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR166;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR167;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR168;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR169;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR170;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR171;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR172;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR173;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR174;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR175;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR176;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR177;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR178;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR179;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR180;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR181;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR182;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR183;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR184;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR185;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR186;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR187;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR188;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR189;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR190;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR191;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR192;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR193;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR194;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR195;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR196;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR197;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR198;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR199;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR200;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR201;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR202;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR203;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR204;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR205;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR206;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLI : 8;
+#else
+			unsigned char SLI : 8;
+#endif
+	} BIT;
+	} SLIBR207;
+	char           wk23[96];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IS0 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS31 : 1;
+#else
+			unsigned long IS31 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS0 : 1;
+#endif
+	} BIT;
+	} GRPAL0;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IS0 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS31 : 1;
+#else
+			unsigned long IS31 : 1;
+			unsigned long IS30 : 1;
+			unsigned long IS29 : 1;
+			unsigned long IS28 : 1;
+			unsigned long IS27 : 1;
+			unsigned long IS26 : 1;
+			unsigned long IS25 : 1;
+			unsigned long IS24 : 1;
+			unsigned long IS23 : 1;
+			unsigned long IS22 : 1;
+			unsigned long IS21 : 1;
+			unsigned long IS20 : 1;
+			unsigned long IS19 : 1;
+			unsigned long IS18 : 1;
+			unsigned long IS17 : 1;
+			unsigned long IS16 : 1;
+			unsigned long IS15 : 1;
+			unsigned long IS14 : 1;
+			unsigned long IS13 : 1;
+			unsigned long IS12 : 1;
+			unsigned long IS11 : 1;
+			unsigned long IS10 : 1;
+			unsigned long IS9 : 1;
+			unsigned long IS8 : 1;
+			unsigned long IS7 : 1;
+			unsigned long IS6 : 1;
+			unsigned long IS5 : 1;
+			unsigned long IS4 : 1;
+			unsigned long IS3 : 1;
+			unsigned long IS2 : 1;
+			unsigned long IS1 : 1;
+			unsigned long IS0 : 1;
+#endif
+	} BIT;
+	} GRPAL1;
+	char           wk24[56];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EN0 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN31 : 1;
+#else
+			unsigned long EN31 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN0 : 1;
+#endif
+	} BIT;
+	} GENAL0;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long EN0 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN31 : 1;
+#else
+			unsigned long EN31 : 1;
+			unsigned long EN30 : 1;
+			unsigned long EN29 : 1;
+			unsigned long EN28 : 1;
+			unsigned long EN27 : 1;
+			unsigned long EN26 : 1;
+			unsigned long EN25 : 1;
+			unsigned long EN24 : 1;
+			unsigned long EN23 : 1;
+			unsigned long EN22 : 1;
+			unsigned long EN21 : 1;
+			unsigned long EN20 : 1;
+			unsigned long EN19 : 1;
+			unsigned long EN18 : 1;
+			unsigned long EN17 : 1;
+			unsigned long EN16 : 1;
+			unsigned long EN15 : 1;
+			unsigned long EN14 : 1;
+			unsigned long EN13 : 1;
+			unsigned long EN12 : 1;
+			unsigned long EN11 : 1;
+			unsigned long EN10 : 1;
+			unsigned long EN9 : 1;
+			unsigned long EN8 : 1;
+			unsigned long EN7 : 1;
+			unsigned long EN6 : 1;
+			unsigned long EN5 : 1;
+			unsigned long EN4 : 1;
+			unsigned long EN3 : 1;
+			unsigned long EN2 : 1;
+			unsigned long EN1 : 1;
+			unsigned long EN0 : 1;
+#endif
+	} BIT;
+	} GENAL1;
+	char           wk25[136];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIAR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIAR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIAR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIAR3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIAR4;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIAR5;
+	char           wk26[5];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PIR0 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR7 : 1;
+#else
+			unsigned char PIR7 : 1;
+			unsigned char PIR6 : 1;
+			unsigned char PIR5 : 1;
+			unsigned char PIR4 : 1;
+			unsigned char PIR3 : 1;
+			unsigned char PIR2 : 1;
+			unsigned char PIR1 : 1;
+			unsigned char PIR0 : 1;
+#endif
+	} BIT;
+	} PIARB;
+	char           wk27[196];
+	union {
+		unsigned char BYTE;
+	} SLIAR208;
+	union {
+		unsigned char BYTE;
+	} SLIAR209;
+	union {
+		unsigned char BYTE;
+	} SLIAR210;
+	union {
+		unsigned char BYTE;
+	} SLIAR211;
+	union {
+		unsigned char BYTE;
+	} SLIAR212;
+	union {
+		unsigned char BYTE;
+	} SLIAR213;
+	union {
+		unsigned char BYTE;
+	} SLIAR214;
+	union {
+		unsigned char BYTE;
+	} SLIAR215;
+	union {
+		unsigned char BYTE;
+	} SLIAR216;
+	union {
+		unsigned char BYTE;
+	} SLIAR217;
+	union {
+		unsigned char BYTE;
+	} SLIAR218;
+	union {
+		unsigned char BYTE;
+	} SLIAR219;
+	union {
+		unsigned char BYTE;
+	} SLIAR220;
+	union {
+		unsigned char BYTE;
+	} SLIAR221;
+	union {
+		unsigned char BYTE;
+	} SLIAR222;
+	union {
+		unsigned char BYTE;
+	} SLIAR223;
+	union {
+		unsigned char BYTE;
+	} SLIAR224;
+	union {
+		unsigned char BYTE;
+	} SLIAR225;
+	union {
+		unsigned char BYTE;
+	} SLIAR226;
+	union {
+		unsigned char BYTE;
+	} SLIAR227;
+	union {
+		unsigned char BYTE;
+	} SLIAR228;
+	union {
+		unsigned char BYTE;
+	} SLIAR229;
+	union {
+		unsigned char BYTE;
+	} SLIAR230;
+	union {
+		unsigned char BYTE;
+	} SLIAR231;
+	union {
+		unsigned char BYTE;
+	} SLIAR232;
+	union {
+		unsigned char BYTE;
+	} SLIAR233;
+	union {
+		unsigned char BYTE;
+	} SLIAR234;
+	union {
+		unsigned char BYTE;
+	} SLIAR235;
+	union {
+		unsigned char BYTE;
+	} SLIAR236;
+	union {
+		unsigned char BYTE;
+	} SLIAR237;
+	union {
+		unsigned char BYTE;
+	} SLIAR238;
+	union {
+		unsigned char BYTE;
+	} SLIAR239;
+	union {
+		unsigned char BYTE;
+	} SLIAR240;
+	union {
+		unsigned char BYTE;
+	} SLIAR241;
+	union {
+		unsigned char BYTE;
+	} SLIAR242;
+	union {
+		unsigned char BYTE;
+	} SLIAR243;
+	union {
+		unsigned char BYTE;
+	} SLIAR244;
+	union {
+		unsigned char BYTE;
+	} SLIAR245;
+	union {
+		unsigned char BYTE;
+	} SLIAR246;
+	union {
+		unsigned char BYTE;
+	} SLIAR247;
+	union {
+		unsigned char BYTE;
+	} SLIAR248;
+	union {
+		unsigned char BYTE;
+	} SLIAR249;
+	union {
+		unsigned char BYTE;
+	} SLIAR250;
+	union {
+		unsigned char BYTE;
+	} SLIAR251;
+	union {
+		unsigned char BYTE;
+	} SLIAR252;
+	union {
+		unsigned char BYTE;
+	} SLIAR253;
+	union {
+		unsigned char BYTE;
+	} SLIAR254;
+	union {
+		unsigned char BYTE;
+	} SLIAR255;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char WPRC : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char WPRC : 1;
+#endif
+	} BIT;
+	} SLIPRCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SELEXD0 : 1;
+			unsigned char SELEXD1 : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char SELEXD1 : 1;
+			unsigned char SELEXD0 : 1;
+#endif
+	} BIT;
+	} SELEXDR;
+} st_icu_t;
+
+typedef struct st_iwdt {
+	unsigned char  IWDTRR;
+	char           wk0[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short TOPS : 2;
+			unsigned short  : 2;
+			unsigned short CKS : 4;
+			unsigned short RPES : 2;
+			unsigned short  : 2;
+			unsigned short RPSS : 2;
+			unsigned short  : 2;
+#else
+			unsigned short  : 2;
+			unsigned short RPSS : 2;
+			unsigned short  : 2;
+			unsigned short RPES : 2;
+			unsigned short CKS : 4;
+			unsigned short  : 2;
+			unsigned short TOPS : 2;
+#endif
+	} BIT;
+	} IWDTCR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CNTVAL : 14;
+			unsigned short UNDFF : 1;
+			unsigned short REFEF : 1;
+#else
+			unsigned short REFEF : 1;
+			unsigned short UNDFF : 1;
+			unsigned short CNTVAL : 14;
+#endif
+	} BIT;
+	} IWDTSR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char RSTIRQS : 1;
+#else
+			unsigned char RSTIRQS : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} IWDTRCR;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char SLCSTP : 1;
+#else
+			unsigned char SLCSTP : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} IWDTCSTPR;
+} st_iwdt_t;
+
+typedef struct st_mmcif {
+	union {
+		unsigned long LONG;
+#ifdef IODEFINE_H_HISTORY
+		struct {
+			unsigned long :1;
+			unsigned long BOOT:1;
+			unsigned long CMD:6;
+			unsigned long RTYP:2;
+			unsigned long RBSY:1;
+			unsigned long :1;
+			unsigned long WDAT:1;
+			unsigned long DWEN:1;
+			unsigned long CMLTE:1;
+			unsigned long CMD12EN:1;
+			unsigned long RIDXC:2;
+			unsigned long RCRC7C:2;
+			unsigned long :1;
+			unsigned long CRC16C:1;
+			unsigned long BOOTACK:1;
+			unsigned long CRCSTE:1;
+			unsigned long TBIT:1;
+			unsigned long OPDM:1;
+			unsigned long :2;
+			unsigned long SBIT:1;
+			unsigned long :1;
+			unsigned long DATW:2;
+		} BIT;
+#endif
+	} CECMDSET;
+	char           wk0[4];
+	union {
+		unsigned long LONG;
+	} CEARG;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long C12ARG : 32;
+#else
+			unsigned long C12ARG : 32;
+#endif
+	} BIT;
+	} CEARGCMD12;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long BREAK : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long BREAK : 1;
+#endif
+	} BIT;
+	} CECMDCTRL;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long BLKSIZ : 16;
+			unsigned long BLKCNT : 16;
+#else
+			unsigned long BLKCNT : 16;
+			unsigned long BLKSIZ : 16;
+#endif
+	} BIT;
+	} CEBLOCKSET;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long SRWDTO : 4;
+			unsigned long SRBSYTO : 4;
+			unsigned long SRSPTO : 2;
+			unsigned long  : 2;
+			unsigned long CLKDIV : 4;
+			unsigned long  : 4;
+			unsigned long CLKEN : 1;
+			unsigned long  : 6;
+			unsigned long MMCBUSBSY : 1;
+#else
+			unsigned long MMCBUSBSY : 1;
+			unsigned long  : 6;
+			unsigned long CLKEN : 1;
+			unsigned long  : 4;
+			unsigned long CLKDIV : 4;
+			unsigned long  : 2;
+			unsigned long SRSPTO : 2;
+			unsigned long SRBSYTO : 4;
+			unsigned long SRWDTO : 4;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} CECLKCTRL;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 16;
+			unsigned long ATYP : 1;
+			unsigned long  : 7;
+			unsigned long DMAREN : 1;
+			unsigned long DMAWEN : 1;
+			unsigned long DMATYP : 1;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long DMATYP : 1;
+			unsigned long DMAWEN : 1;
+			unsigned long DMAREN : 1;
+			unsigned long  : 7;
+			unsigned long ATYP : 1;
+			unsigned long  : 16;
+#endif
+	} BIT;
+	} CEBUFACC;
+	unsigned long  CERESP3;
+	unsigned long  CERESP2;
+	unsigned long  CERESP1;
+	unsigned long  CERESP0;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RSP12 : 32;
+#else
+			unsigned long RSP12 : 32;
+#endif
+	} BIT;
+	} CERESPCMD12;
+	unsigned long  CEDATA;
+	char           wk1[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 16;
+			unsigned long SBTDATTO : 4;
+			unsigned long SFSTBTDATTO : 4;
+			unsigned long SBTACKTO : 4;
+			unsigned long SBTCLKDIV : 4;
+#else
+			unsigned long SBTCLKDIV : 4;
+			unsigned long SBTACKTO : 4;
+			unsigned long SFSTBTDATTO : 4;
+			unsigned long SBTDATTO : 4;
+			unsigned long  : 16;
+#endif
+	} BIT;
+	} CEBOOT;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RSPTO : 1;
+			unsigned long RBSYTO : 1;
+			unsigned long RDATTO : 1;
+			unsigned long WDATTO : 1;
+			unsigned long CRCSTO : 1;
+			unsigned long  : 3;
+			unsigned long RSPERR : 1;
+			unsigned long RIDXERR : 1;
+			unsigned long RDATERR : 1;
+			unsigned long WDATERR : 1;
+			unsigned long  : 2;
+			unsigned long BUFVIO : 1;
+			unsigned long CMDVIO : 1;
+			unsigned long CRSPE : 1;
+			unsigned long RBSYE : 1;
+			unsigned long  : 2;
+			unsigned long BUFREN : 1;
+			unsigned long BUFWEN : 1;
+			unsigned long BUFRE : 1;
+			unsigned long DTRANE : 1;
+			unsigned long CMD12CRE : 1;
+			unsigned long CMD12RBE : 1;
+			unsigned long CMD12DRE : 1;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long CMD12DRE : 1;
+			unsigned long CMD12RBE : 1;
+			unsigned long CMD12CRE : 1;
+			unsigned long DTRANE : 1;
+			unsigned long BUFRE : 1;
+			unsigned long BUFWEN : 1;
+			unsigned long BUFREN : 1;
+			unsigned long  : 2;
+			unsigned long RBSYE : 1;
+			unsigned long CRSPE : 1;
+			unsigned long CMDVIO : 1;
+			unsigned long BUFVIO : 1;
+			unsigned long  : 2;
+			unsigned long WDATERR : 1;
+			unsigned long RDATERR : 1;
+			unsigned long RIDXERR : 1;
+			unsigned long RSPERR : 1;
+			unsigned long  : 3;
+			unsigned long CRCSTO : 1;
+			unsigned long WDATTO : 1;
+			unsigned long RDATTO : 1;
+			unsigned long RBSYTO : 1;
+			unsigned long RSPTO : 1;
+#endif
+	} BIT;
+	} CEINT;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MRSPTO : 1;
+			unsigned long MRBSYTO : 1;
+			unsigned long MRDATTO : 1;
+			unsigned long MWDATTO : 1;
+			unsigned long MCRCSTO : 1;
+			unsigned long  : 3;
+			unsigned long MRSPERR : 1;
+			unsigned long MRIDXERR : 1;
+			unsigned long MRDATERR : 1;
+			unsigned long MWDATERR : 1;
+			unsigned long  : 2;
+			unsigned long MBUFVIO : 1;
+			unsigned long MCMDVIO : 1;
+			unsigned long MCRSPE : 1;
+			unsigned long MRBSYE : 1;
+			unsigned long  : 2;
+			unsigned long MBUFREN : 1;
+			unsigned long MBUFWEN : 1;
+			unsigned long MBUFRE : 1;
+			unsigned long MDTRANE : 1;
+			unsigned long MCMD12CRE : 1;
+			unsigned long MCMD12RBE : 1;
+			unsigned long MCMD12DRE : 1;
+			unsigned long  : 5;
+#else
+			unsigned long  : 5;
+			unsigned long MCMD12DRE : 1;
+			unsigned long MCMD12RBE : 1;
+			unsigned long MCMD12CRE : 1;
+			unsigned long MDTRANE : 1;
+			unsigned long MBUFRE : 1;
+			unsigned long MBUFWEN : 1;
+			unsigned long MBUFREN : 1;
+			unsigned long  : 2;
+			unsigned long MRBSYE : 1;
+			unsigned long MCRSPE : 1;
+			unsigned long MCMDVIO : 1;
+			unsigned long MBUFVIO : 1;
+			unsigned long  : 2;
+			unsigned long MWDATERR : 1;
+			unsigned long MRDATERR : 1;
+			unsigned long MRIDXERR : 1;
+			unsigned long MRSPERR : 1;
+			unsigned long  : 3;
+			unsigned long MCRCSTO : 1;
+			unsigned long MWDATTO : 1;
+			unsigned long MRDATTO : 1;
+			unsigned long MRBSYTO : 1;
+			unsigned long MRSPTO : 1;
+#endif
+	} BIT;
+	} CEINTEN;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RCVBLK : 16;
+			unsigned long DATSIG : 8;
+			unsigned long RSPIDX : 6;
+			unsigned long CMDSIG : 1;
+			unsigned long CMDSEQ : 1;
+#else
+			unsigned long CMDSEQ : 1;
+			unsigned long CMDSIG : 1;
+			unsigned long RSPIDX : 6;
+			unsigned long DATSIG : 8;
+			unsigned long RCVBLK : 16;
+#endif
+	} BIT;
+	} CEHOSTSTS1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 5;
+			unsigned long BTDATTO : 1;
+			unsigned long FSTBTDATTO : 1;
+			unsigned long BTACKTO : 1;
+			unsigned long STRSPTO : 1;
+			unsigned long AC12RSPTO : 1;
+			unsigned long RSPBSYTO : 1;
+			unsigned long AC12BSYTO : 1;
+			unsigned long CRCSTTO : 1;
+			unsigned long DATBSYTO : 1;
+			unsigned long STRDATTO : 1;
+			unsigned long  : 1;
+			unsigned long CRCST : 3;
+			unsigned long  : 1;
+			unsigned long BTACKEBE : 1;
+			unsigned long BTACKPATE : 1;
+			unsigned long RSPIDXE : 1;
+			unsigned long AC12IDXE : 1;
+			unsigned long RSPEBE : 1;
+			unsigned long AC12REBE : 1;
+			unsigned long RDATEBE : 1;
+			unsigned long CRCSTEBE : 1;
+			unsigned long RSPCRC7E : 1;
+			unsigned long AC12CRCE : 1;
+			unsigned long CRC16E : 1;
+			unsigned long CRCSTE : 1;
+#else
+			unsigned long CRCSTE : 1;
+			unsigned long CRC16E : 1;
+			unsigned long AC12CRCE : 1;
+			unsigned long RSPCRC7E : 1;
+			unsigned long CRCSTEBE : 1;
+			unsigned long RDATEBE : 1;
+			unsigned long AC12REBE : 1;
+			unsigned long RSPEBE : 1;
+			unsigned long AC12IDXE : 1;
+			unsigned long RSPIDXE : 1;
+			unsigned long BTACKPATE : 1;
+			unsigned long BTACKEBE : 1;
+			unsigned long  : 1;
+			unsigned long CRCST : 3;
+			unsigned long  : 1;
+			unsigned long STRDATTO : 1;
+			unsigned long DATBSYTO : 1;
+			unsigned long CRCSTTO : 1;
+			unsigned long AC12BSYTO : 1;
+			unsigned long RSPBSYTO : 1;
+			unsigned long AC12RSPTO : 1;
+			unsigned long STRSPTO : 1;
+			unsigned long BTACKTO : 1;
+			unsigned long FSTBTDATTO : 1;
+			unsigned long BTDATTO : 1;
+			unsigned long  : 5;
+#endif
+	} BIT;
+	} CEHOSTSTS2;
+	char           wk2[32];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long MCDFALL : 1;
+			unsigned long MCDRISE : 1;
+			unsigned long  : 6;
+			unsigned long CDFALL : 1;
+			unsigned long CDRISE : 1;
+			unsigned long CDSIG : 1;
+			unsigned long  : 17;
+#else
+			unsigned long  : 17;
+			unsigned long CDSIG : 1;
+			unsigned long CDRISE : 1;
+			unsigned long CDFALL : 1;
+			unsigned long  : 6;
+			unsigned long MCDRISE : 1;
+			unsigned long MCDFALL : 1;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} CEDETECT;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 19;
+			unsigned long CLKMAIN : 1;
+			unsigned long  : 1;
+			unsigned long RESNOUT : 1;
+			unsigned long  : 10;
+#else
+			unsigned long  : 10;
+			unsigned long RESNOUT : 1;
+			unsigned long  : 1;
+			unsigned long CLKMAIN : 1;
+			unsigned long  : 19;
+#endif
+	} BIT;
+	} CEADDMODE;
+	char           wk3[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VERSION : 16;
+			unsigned long  : 15;
+			unsigned long SWRST : 1;
+#else
+			unsigned long SWRST : 1;
+			unsigned long  : 15;
+			unsigned long VERSION : 16;
+#endif
+	} BIT;
+	} CEVERSION;
+} st_mmcif_t;
+
+typedef struct st_mpc {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CS0E : 1;
+			unsigned char CS1E : 1;
+			unsigned char CS2E : 1;
+			unsigned char CS3E : 1;
+			unsigned char CS4E : 1;
+			unsigned char CS5E : 1;
+			unsigned char CS6E : 1;
+			unsigned char CS7E : 1;
+#else
+			unsigned char CS7E : 1;
+			unsigned char CS6E : 1;
+			unsigned char CS5E : 1;
+			unsigned char CS4E : 1;
+			unsigned char CS3E : 1;
+			unsigned char CS2E : 1;
+			unsigned char CS1E : 1;
+			unsigned char CS0E : 1;
+#endif
+	} BIT;
+	} PFCSE;
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CS0S : 1;
+			unsigned char  : 1;
+			unsigned char CS1S : 2;
+			unsigned char CS2S : 2;
+			unsigned char CS3S : 2;
+#else
+			unsigned char CS3S : 2;
+			unsigned char CS2S : 2;
+			unsigned char CS1S : 2;
+			unsigned char  : 1;
+			unsigned char CS0S : 1;
+#endif
+	} BIT;
+	} PFCSS0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CS4S : 2;
+			unsigned char CS5S : 2;
+			unsigned char CS6S : 2;
+			unsigned char CS7S : 2;
+#else
+			unsigned char CS7S : 2;
+			unsigned char CS6S : 2;
+			unsigned char CS5S : 2;
+			unsigned char CS4S : 2;
+#endif
+	} BIT;
+	} PFCSS1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char A8E : 1;
+			unsigned char A9E : 1;
+			unsigned char A10E : 1;
+			unsigned char A11E : 1;
+			unsigned char A12E : 1;
+			unsigned char A13E : 1;
+			unsigned char A14E : 1;
+			unsigned char A15E : 1;
+#else
+			unsigned char A15E : 1;
+			unsigned char A14E : 1;
+			unsigned char A13E : 1;
+			unsigned char A12E : 1;
+			unsigned char A11E : 1;
+			unsigned char A10E : 1;
+			unsigned char A9E : 1;
+			unsigned char A8E : 1;
+#endif
+	} BIT;
+	} PFAOE0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char A16E : 1;
+			unsigned char A17E : 1;
+			unsigned char A18E : 1;
+			unsigned char A19E : 1;
+			unsigned char A20E : 1;
+			unsigned char A21E : 1;
+			unsigned char A22E : 1;
+			unsigned char A23E : 1;
+#else
+			unsigned char A23E : 1;
+			unsigned char A22E : 1;
+			unsigned char A21E : 1;
+			unsigned char A20E : 1;
+			unsigned char A19E : 1;
+			unsigned char A18E : 1;
+			unsigned char A17E : 1;
+			unsigned char A16E : 1;
+#endif
+	} BIT;
+	} PFAOE1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ADRLE : 1;
+			unsigned char ADRHMS : 1;
+			unsigned char ADRHMS2 : 1;
+			unsigned char BCLKO : 1;
+			unsigned char DHE : 1;
+			unsigned char DH32E : 1;
+			unsigned char WR1BC1E : 1;
+			unsigned char WR32BC32E : 1;
+#else
+			unsigned char WR32BC32E : 1;
+			unsigned char WR1BC1E : 1;
+			unsigned char DH32E : 1;
+			unsigned char DHE : 1;
+			unsigned char BCLKO : 1;
+			unsigned char ADRHMS2 : 1;
+			unsigned char ADRHMS : 1;
+			unsigned char ADRLE : 1;
+#endif
+	} BIT;
+	} PFBCR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char WAITS : 2;
+			unsigned char ALEOE : 1;
+			unsigned char ALES : 1;
+			unsigned char MDSDE : 1;
+			unsigned char  : 1;
+			unsigned char DQM1E : 1;
+			unsigned char SDCLKE : 1;
+#else
+			unsigned char SDCLKE : 1;
+			unsigned char DQM1E : 1;
+			unsigned char  : 1;
+			unsigned char MDSDE : 1;
+			unsigned char ALES : 1;
+			unsigned char ALEOE : 1;
+			unsigned char WAITS : 2;
+#endif
+	} BIT;
+	} PFBCR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char D0S : 2;
+			unsigned char D1S : 2;
+			unsigned char D2S : 2;
+			unsigned char D3S : 2;
+#else
+			unsigned char D3S : 2;
+			unsigned char D2S : 2;
+			unsigned char D1S : 2;
+			unsigned char D0S : 2;
+#endif
+	} BIT;
+	} PFBCR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DLHS : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DLHS : 1;
+#endif
+	} BIT;
+	} PFBCR3;
+	char           wk1[4];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 4;
+			unsigned char PHYMODE0 : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char PHYMODE0 : 1;
+			unsigned char  : 4;
+#endif
+	} BIT;
+	} PFENET;
+	char           wk2[16];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char PFSWE : 1;
+			unsigned char B0WI : 1;
+#else
+			unsigned char B0WI : 1;
+			unsigned char PFSWE : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} PWPR;
+	char           wk3[32];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P00PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P01PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P02PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} P03PFS;
+	char           wk4[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} P05PFS;
+	char           wk5[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P07PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P10PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P11PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P12PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P13PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P14PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P15PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P16PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P17PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P20PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P21PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P22PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P23PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P24PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P25PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P26PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P27PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P30PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P31PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P32PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P33PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P34PFS;
+	char           wk6[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} P40PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} P41PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} P42PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} P43PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} P44PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} P45PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} P46PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} P47PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P50PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P51PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P52PFS;
+	char           wk7[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P54PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P55PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P56PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P57PFS;
+	char           wk8[6];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P66PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P67PFS;
+	char           wk9[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P71PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P72PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P73PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P74PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P75PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P76PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P77PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P80PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P81PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P82PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P83PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P84PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P85PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P86PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P87PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char  : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P90PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char  : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P91PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char  : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P92PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char  : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} P93PFS;
+	char           wk10[4];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PA0PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PA1PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PA2PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PA3PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PA4PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PA5PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PA6PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PA7PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PB0PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PB1PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PB2PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PB3PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PB4PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PB5PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PB6PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PB7PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PC0PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PC1PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PC2PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PC3PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PC4PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PC5PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PC6PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PC7PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PD0PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PD1PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PD2PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PD3PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PD4PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PD5PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PD6PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PD7PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char  : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PE0PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char  : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PE1PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PE2PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char  : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PE3PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char  : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PE4PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PE5PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PE6PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char ISEL : 1;
+			unsigned char ASEL : 1;
+#else
+			unsigned char ASEL : 1;
+			unsigned char ISEL : 1;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PE7PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PF0PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PF1PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PF2PFS;
+	char           wk11[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char ISEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ISEL : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} PF5PFS;
+	char           wk12[18];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PJ0PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PJ1PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PJ2PFS;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PJ3PFS;
+	char           wk13[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PSEL : 6;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char PSEL : 6;
+#endif
+	} BIT;
+	} PJ5PFS;
+} st_mpc_t;
+
+typedef struct st_mpu {
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long RSPN : 28;
+#else
+			unsigned long RSPN : 28;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} RSPAGE0;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long V : 1;
+			unsigned long UAC : 3;
+			unsigned long REPN : 28;
+#else
+			unsigned long REPN : 28;
+			unsigned long UAC : 3;
+			unsigned long V : 1;
+#endif
+	} BIT;
+	} REPAGE0;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long RSPN : 28;
+#else
+			unsigned long RSPN : 28;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} RSPAGE1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long V : 1;
+			unsigned long UAC : 3;
+			unsigned long REPN : 28;
+#else
+			unsigned long REPN : 28;
+			unsigned long UAC : 3;
+			unsigned long V : 1;
+#endif
+	} BIT;
+	} REPAGE1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long RSPN : 28;
+#else
+			unsigned long RSPN : 28;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} RSPAGE2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long V : 1;
+			unsigned long UAC : 3;
+			unsigned long REPN : 28;
+#else
+			unsigned long REPN : 28;
+			unsigned long UAC : 3;
+			unsigned long V : 1;
+#endif
+	} BIT;
+	} REPAGE2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long RSPN : 28;
+#else
+			unsigned long RSPN : 28;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} RSPAGE3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long V : 1;
+			unsigned long UAC : 3;
+			unsigned long REPN : 28;
+#else
+			unsigned long REPN : 28;
+			unsigned long UAC : 3;
+			unsigned long V : 1;
+#endif
+	} BIT;
+	} REPAGE3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long RSPN : 28;
+#else
+			unsigned long RSPN : 28;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} RSPAGE4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long V : 1;
+			unsigned long UAC : 3;
+			unsigned long REPN : 28;
+#else
+			unsigned long REPN : 28;
+			unsigned long UAC : 3;
+			unsigned long V : 1;
+#endif
+	} BIT;
+	} REPAGE4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long RSPN : 28;
+#else
+			unsigned long RSPN : 28;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} RSPAGE5;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long V : 1;
+			unsigned long UAC : 3;
+			unsigned long REPN : 28;
+#else
+			unsigned long REPN : 28;
+			unsigned long UAC : 3;
+			unsigned long V : 1;
+#endif
+	} BIT;
+	} REPAGE5;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long RSPN : 28;
+#else
+			unsigned long RSPN : 28;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} RSPAGE6;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long V : 1;
+			unsigned long UAC : 3;
+			unsigned long REPN : 28;
+#else
+			unsigned long REPN : 28;
+			unsigned long UAC : 3;
+			unsigned long V : 1;
+#endif
+	} BIT;
+	} REPAGE6;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 4;
+			unsigned long RSPN : 28;
+#else
+			unsigned long RSPN : 28;
+			unsigned long  : 4;
+#endif
+	} BIT;
+	} RSPAGE7;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long V : 1;
+			unsigned long UAC : 3;
+			unsigned long REPN : 28;
+#else
+			unsigned long REPN : 28;
+			unsigned long UAC : 3;
+			unsigned long V : 1;
+#endif
+	} BIT;
+	} REPAGE7;
+	char           wk0[192];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MPEN : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long MPEN : 1;
+#endif
+	} BIT;
+	} MPEN;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 1;
+			unsigned long UBAC : 3;
+			unsigned long  : 28;
+#else
+			unsigned long  : 28;
+			unsigned long UBAC : 3;
+			unsigned long  : 1;
+#endif
+	} BIT;
+	} MPBAC;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CLR : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long CLR : 1;
+#endif
+	} BIT;
+	} MPECLR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IMPER : 1;
+			unsigned long DMPER : 1;
+			unsigned long DRW : 1;
+			unsigned long  : 29;
+#else
+			unsigned long  : 29;
+			unsigned long DRW : 1;
+			unsigned long DMPER : 1;
+			unsigned long IMPER : 1;
+#endif
+	} BIT;
+	} MPESTS;
+	char           wk1[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DEA : 32;
+#else
+			unsigned long DEA : 32;
+#endif
+	} BIT;
+	} MPDEA;
+	char           wk2[8];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long SA : 32;
+#else
+			unsigned long SA : 32;
+#endif
+	} BIT;
+	} MPSA;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short S : 1;
+			unsigned short  : 15;
+#else
+			unsigned short  : 15;
+			unsigned short S : 1;
+#endif
+	} BIT;
+	} MPOPS;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short INV : 1;
+			unsigned short  : 15;
+#else
+			unsigned short  : 15;
+			unsigned short INV : 1;
+#endif
+	} BIT;
+	} MPOPI;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 1;
+			unsigned long UHACI : 3;
+			unsigned long  : 12;
+			unsigned long HITI : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long HITI : 8;
+			unsigned long  : 12;
+			unsigned long UHACI : 3;
+			unsigned long  : 1;
+#endif
+	} BIT;
+	} MHITI;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 1;
+			unsigned long UHACD : 3;
+			unsigned long  : 12;
+			unsigned long HITD : 8;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long HITD : 8;
+			unsigned long  : 12;
+			unsigned long UHACD : 3;
+			unsigned long  : 1;
+#endif
+	} BIT;
+	} MHITD;
+} st_mpu_t;
+
+typedef struct st_mtu {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OE3B : 1;
+			unsigned char OE4A : 1;
+			unsigned char OE4B : 1;
+			unsigned char OE3D : 1;
+			unsigned char OE4C : 1;
+			unsigned char OE4D : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char OE4D : 1;
+			unsigned char OE4C : 1;
+			unsigned char OE3D : 1;
+			unsigned char OE4B : 1;
+			unsigned char OE4A : 1;
+			unsigned char OE3B : 1;
+#endif
+	} BIT;
+	} TOERA;
+	char           wk0[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char UF : 1;
+			unsigned char VF : 1;
+			unsigned char WF : 1;
+			unsigned char FB : 1;
+			unsigned char P : 1;
+			unsigned char N : 1;
+			unsigned char BDC : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char BDC : 1;
+			unsigned char N : 1;
+			unsigned char P : 1;
+			unsigned char FB : 1;
+			unsigned char WF : 1;
+			unsigned char VF : 1;
+			unsigned char UF : 1;
+#endif
+	} BIT;
+	} TGCRA;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OLSP : 1;
+			unsigned char OLSN : 1;
+			unsigned char TOCS : 1;
+			unsigned char TOCL : 1;
+			unsigned char  : 2;
+			unsigned char PSYE : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PSYE : 1;
+			unsigned char  : 2;
+			unsigned char TOCL : 1;
+			unsigned char TOCS : 1;
+			unsigned char OLSN : 1;
+			unsigned char OLSP : 1;
+#endif
+	} BIT;
+	} TOCR1A;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OLS1P : 1;
+			unsigned char OLS1N : 1;
+			unsigned char OLS2P : 1;
+			unsigned char OLS2N : 1;
+			unsigned char OLS3P : 1;
+			unsigned char OLS3N : 1;
+			unsigned char BF : 2;
+#else
+			unsigned char BF : 2;
+			unsigned char OLS3N : 1;
+			unsigned char OLS3P : 1;
+			unsigned char OLS2N : 1;
+			unsigned char OLS2P : 1;
+			unsigned char OLS1N : 1;
+			unsigned char OLS1P : 1;
+#endif
+	} BIT;
+	} TOCR2A;
+	char           wk1[4];
+	unsigned short TCDRA;
+	unsigned short TDDRA;
+	char           wk2[8];
+	unsigned short TCNTSA;
+	unsigned short TCBRA;
+	char           wk3[12];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char T4VCOR : 3;
+			unsigned char T4VEN : 1;
+			unsigned char T3ACOR : 3;
+			unsigned char T3AEN : 1;
+#else
+			unsigned char T3AEN : 1;
+			unsigned char T3ACOR : 3;
+			unsigned char T4VEN : 1;
+			unsigned char T4VCOR : 3;
+#endif
+	} BIT;
+	} TITCR1A;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char T4VCNT : 3;
+			unsigned char  : 1;
+			unsigned char T3ACNT : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char T3ACNT : 3;
+			unsigned char  : 1;
+			unsigned char T4VCNT : 3;
+#endif
+	} BIT;
+	} TITCNT1A;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BTE : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char BTE : 2;
+#endif
+	} BIT;
+	} TBTERA;
+	char           wk4[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TDER : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char TDER : 1;
+#endif
+	} BIT;
+	} TDERA;
+	char           wk5[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OLS1P : 1;
+			unsigned char OLS1N : 1;
+			unsigned char OLS2P : 1;
+			unsigned char OLS2N : 1;
+			unsigned char OLS3P : 1;
+			unsigned char OLS3N : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char OLS3N : 1;
+			unsigned char OLS3P : 1;
+			unsigned char OLS2N : 1;
+			unsigned char OLS2P : 1;
+			unsigned char OLS1N : 1;
+			unsigned char OLS1P : 1;
+#endif
+	} BIT;
+	} TOLBRA;
+	char           wk6[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TITM : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char TITM : 1;
+#endif
+	} BIT;
+	} TITMRA;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TRG4COR : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TRG4COR : 3;
+#endif
+	} BIT;
+	} TITCR2A;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TRG4CNT : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TRG4CNT : 3;
+#endif
+	} BIT;
+	} TITCNT2A;
+	char           wk7[35];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char WRE : 1;
+			unsigned char SCC : 1;
+			unsigned char  : 5;
+			unsigned char CCE : 1;
+#else
+			unsigned char CCE : 1;
+			unsigned char  : 5;
+			unsigned char SCC : 1;
+			unsigned char WRE : 1;
+#endif
+	} BIT;
+	} TWCRA;
+	char           wk8[15];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DRS : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DRS : 1;
+#endif
+	} BIT;
+	} TMDR2A;
+	char           wk9[15];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CST0 : 1;
+			unsigned char CST1 : 1;
+			unsigned char CST2 : 1;
+			unsigned char CST8 : 1;
+			unsigned char  : 2;
+			unsigned char CST3 : 1;
+			unsigned char CST4 : 1;
+#else
+			unsigned char CST4 : 1;
+			unsigned char CST3 : 1;
+			unsigned char  : 2;
+			unsigned char CST8 : 1;
+			unsigned char CST2 : 1;
+			unsigned char CST1 : 1;
+			unsigned char CST0 : 1;
+#endif
+	} BIT;
+	} TSTRA;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SYNC0 : 1;
+			unsigned char SYNC1 : 1;
+			unsigned char SYNC2 : 1;
+			unsigned char  : 3;
+			unsigned char SYNC3 : 1;
+			unsigned char SYNC4 : 1;
+#else
+			unsigned char SYNC4 : 1;
+			unsigned char SYNC3 : 1;
+			unsigned char  : 3;
+			unsigned char SYNC2 : 1;
+			unsigned char SYNC1 : 1;
+			unsigned char SYNC0 : 1;
+#endif
+	} BIT;
+	} TSYRA;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SCH7 : 1;
+			unsigned char SCH6 : 1;
+			unsigned char  : 1;
+			unsigned char SCH4 : 1;
+			unsigned char SCH3 : 1;
+			unsigned char SCH2 : 1;
+			unsigned char SCH1 : 1;
+			unsigned char SCH0 : 1;
+#else
+			unsigned char SCH0 : 1;
+			unsigned char SCH1 : 1;
+			unsigned char SCH2 : 1;
+			unsigned char SCH3 : 1;
+			unsigned char SCH4 : 1;
+			unsigned char  : 1;
+			unsigned char SCH6 : 1;
+			unsigned char SCH7 : 1;
+#endif
+	} BIT;
+	} TCSYSTR;
+	char           wk10[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RWE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char RWE : 1;
+#endif
+	} BIT;
+	} TRWERA;
+	char           wk11[1925];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OE6B : 1;
+			unsigned char OE7A : 1;
+			unsigned char OE7B : 1;
+			unsigned char OE6D : 1;
+			unsigned char OE7C : 1;
+			unsigned char OE7D : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char OE7D : 1;
+			unsigned char OE7C : 1;
+			unsigned char OE6D : 1;
+			unsigned char OE7B : 1;
+			unsigned char OE7A : 1;
+			unsigned char OE6B : 1;
+#endif
+	} BIT;
+	} TOERB;
+	char           wk12[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OLSP : 1;
+			unsigned char OLSN : 1;
+			unsigned char TOCS : 1;
+			unsigned char TOCL : 1;
+			unsigned char  : 2;
+			unsigned char PSYE : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PSYE : 1;
+			unsigned char  : 2;
+			unsigned char TOCL : 1;
+			unsigned char TOCS : 1;
+			unsigned char OLSN : 1;
+			unsigned char OLSP : 1;
+#endif
+	} BIT;
+	} TOCR1B;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OLS1P : 1;
+			unsigned char OLS1N : 1;
+			unsigned char OLS2P : 1;
+			unsigned char OLS2N : 1;
+			unsigned char OLS3P : 1;
+			unsigned char OLS3N : 1;
+			unsigned char BF : 2;
+#else
+			unsigned char BF : 2;
+			unsigned char OLS3N : 1;
+			unsigned char OLS3P : 1;
+			unsigned char OLS2N : 1;
+			unsigned char OLS2P : 1;
+			unsigned char OLS1N : 1;
+			unsigned char OLS1P : 1;
+#endif
+	} BIT;
+	} TOCR2B;
+	char           wk13[4];
+	unsigned short TCDRB;
+	unsigned short TDDRB;
+	char           wk14[8];
+	unsigned short TCNTSB;
+	unsigned short TCBRB;
+	char           wk15[12];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char T7VCOR : 3;
+			unsigned char T7VEN : 1;
+			unsigned char T6ACOR : 3;
+			unsigned char T6AEN : 1;
+#else
+			unsigned char T6AEN : 1;
+			unsigned char T6ACOR : 3;
+			unsigned char T7VEN : 1;
+			unsigned char T7VCOR : 3;
+#endif
+	} BIT;
+	} TITCR1B;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char T7VCNT : 3;
+			unsigned char  : 1;
+			unsigned char T6ACNT : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char T6ACNT : 3;
+			unsigned char  : 1;
+			unsigned char T7VCNT : 3;
+#endif
+	} BIT;
+	} TITCNT1B;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BTE : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char BTE : 2;
+#endif
+	} BIT;
+	} TBTERB;
+	char           wk16[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TDER : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char TDER : 1;
+#endif
+	} BIT;
+	} TDERB;
+	char           wk17[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OLS1P : 1;
+			unsigned char OLS1N : 1;
+			unsigned char OLS2P : 1;
+			unsigned char OLS2N : 1;
+			unsigned char OLS3P : 1;
+			unsigned char OLS3N : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char OLS3N : 1;
+			unsigned char OLS3P : 1;
+			unsigned char OLS2N : 1;
+			unsigned char OLS2P : 1;
+			unsigned char OLS1N : 1;
+			unsigned char OLS1P : 1;
+#endif
+	} BIT;
+	} TOLBRB;
+	char           wk18[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TITM : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char TITM : 1;
+#endif
+	} BIT;
+	} TITMRB;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TRG7COR : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TRG7COR : 3;
+#endif
+	} BIT;
+	} TITCR2B;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TRG7CNT : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TRG7CNT : 3;
+#endif
+	} BIT;
+	} TITCNT2B;
+	char           wk19[35];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char WRE : 1;
+			unsigned char SCC : 1;
+			unsigned char  : 5;
+			unsigned char CCE : 1;
+#else
+			unsigned char CCE : 1;
+			unsigned char  : 5;
+			unsigned char SCC : 1;
+			unsigned char WRE : 1;
+#endif
+	} BIT;
+	} TWCRB;
+	char           wk20[15];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DRS : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DRS : 1;
+#endif
+	} BIT;
+	} TMDR2B;
+	char           wk21[15];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char CST6 : 1;
+			unsigned char CST7 : 1;
+#else
+			unsigned char CST7 : 1;
+			unsigned char CST6 : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} TSTRB;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 6;
+			unsigned char SYNC6 : 1;
+			unsigned char SYNC7 : 1;
+#else
+			unsigned char SYNC7 : 1;
+			unsigned char SYNC6 : 1;
+			unsigned char  : 6;
+#endif
+	} BIT;
+	} TSYRB;
+	char           wk22[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RWE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char RWE : 1;
+#endif
+	} BIT;
+	} TRWERB;
+} st_mtu_t;
+
+typedef struct st_mtu0 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR0;
+	char           wk0[8];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCRC;
+	char           wk1[102];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 3;
+#else
+			unsigned char CCLR : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char BFA : 1;
+			unsigned char BFB : 1;
+			unsigned char BFE : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char BFE : 1;
+			unsigned char BFB : 1;
+			unsigned char BFA : 1;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIORH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 4;
+			unsigned char IOD : 4;
+#else
+			unsigned char IOD : 4;
+			unsigned char IOC : 4;
+#endif
+	} BIT;
+	} TIORL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIED : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TGIED : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	char           wk2[1];
+	unsigned short TCNT;
+	unsigned short TGRA;
+	unsigned short TGRB;
+	unsigned short TGRC;
+	unsigned short TGRD;
+	char           wk3[16];
+	unsigned short TGRE;
+	unsigned short TGRF;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEE : 1;
+			unsigned char TGIEF : 1;
+			unsigned char  : 5;
+			unsigned char TTGE2 : 1;
+#else
+			unsigned char TTGE2 : 1;
+			unsigned char  : 5;
+			unsigned char TGIEF : 1;
+			unsigned char TGIEE : 1;
+#endif
+	} BIT;
+	} TIER2;
+	char           wk4[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TTSA : 1;
+			unsigned char TTSB : 1;
+			unsigned char TTSE : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TTSE : 1;
+			unsigned char TTSB : 1;
+			unsigned char TTSA : 1;
+#endif
+	} BIT;
+	} TBTM;
+	char           wk5[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2;
+} st_mtu0_t;
+
+typedef struct st_mtu1 {
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR1;
+	char           wk1[238];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 2;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char CCLR : 2;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIOR;
+	char           wk2[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TCIEU : 1;
+			unsigned char  : 1;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char  : 1;
+			unsigned char TCIEU : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char TCFD : 1;
+#else
+			unsigned char TCFD : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} TSR;
+	unsigned short TCNT;
+	unsigned short TGRA;
+	unsigned short TGRB;
+	char           wk3[4];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char I1AE : 1;
+			unsigned char I1BE : 1;
+			unsigned char I2AE : 1;
+			unsigned char I2BE : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char I2BE : 1;
+			unsigned char I2AE : 1;
+			unsigned char I1BE : 1;
+			unsigned char I1AE : 1;
+#endif
+	} BIT;
+	} TICCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char LWA : 1;
+			unsigned char PHCKSEL : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char PHCKSEL : 1;
+			unsigned char LWA : 1;
+#endif
+	} BIT;
+	} TMDR3;
+	char           wk4[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char PCB : 2;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char PCB : 2;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2;
+	char           wk5[11];
+	unsigned long  TCNTLW;
+	unsigned long  TGRALW;
+	unsigned long  TGRBLW;
+} st_mtu1_t;
+
+typedef struct st_mtu2 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR2;
+	char           wk0[365];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 2;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char CCLR : 2;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIOR;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TCIEU : 1;
+			unsigned char  : 1;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char  : 1;
+			unsigned char TCIEU : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char TCFD : 1;
+#else
+			unsigned char TCFD : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} TSR;
+	unsigned short TCNT;
+	unsigned short TGRA;
+	unsigned short TGRB;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char PCB : 2;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char PCB : 2;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2;
+} st_mtu2_t;
+
+typedef struct st_mtu3 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 3;
+#else
+			unsigned char CCLR : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char BFA : 1;
+			unsigned char BFB : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char BFB : 1;
+			unsigned char BFA : 1;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR1;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIORH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 4;
+			unsigned char IOD : 4;
+#else
+			unsigned char IOD : 4;
+			unsigned char IOC : 4;
+#endif
+	} BIT;
+	} TIORL;
+	char           wk2[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIED : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TGIED : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	char           wk3[7];
+	unsigned short TCNT;
+	char           wk4[6];
+	unsigned short TGRA;
+	unsigned short TGRB;
+	char           wk5[8];
+	unsigned short TGRC;
+	unsigned short TGRD;
+	char           wk6[4];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char TCFD : 1;
+#else
+			unsigned char TCFD : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} TSR;
+	char           wk7[11];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TTSA : 1;
+			unsigned char TTSB : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char TTSB : 1;
+			unsigned char TTSA : 1;
+#endif
+	} BIT;
+	} TBTM;
+	char           wk8[19];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2;
+	char           wk9[37];
+	unsigned short TGRE;
+	char           wk10[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR3;
+} st_mtu3_t;
+
+typedef struct st_mtu4 {
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 3;
+#else
+			unsigned char CCLR : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char BFA : 1;
+			unsigned char BFB : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char BFB : 1;
+			unsigned char BFA : 1;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR1;
+	char           wk2[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIORH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 4;
+			unsigned char IOD : 4;
+#else
+			unsigned char IOD : 4;
+			unsigned char IOC : 4;
+#endif
+	} BIT;
+	} TIORL;
+	char           wk3[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIED : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 1;
+			unsigned char TTGE2 : 1;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char TTGE2 : 1;
+			unsigned char  : 1;
+			unsigned char TCIEV : 1;
+			unsigned char TGIED : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	char           wk4[8];
+	unsigned short TCNT;
+	char           wk5[8];
+	unsigned short TGRA;
+	unsigned short TGRB;
+	char           wk6[8];
+	unsigned short TGRC;
+	unsigned short TGRD;
+	char           wk7[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char TCFD : 1;
+#else
+			unsigned char TCFD : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} TSR;
+	char           wk8[11];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TTSA : 1;
+			unsigned char TTSB : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char TTSB : 1;
+			unsigned char TTSA : 1;
+#endif
+	} BIT;
+	} TBTM;
+	char           wk9[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ITB4VE : 1;
+			unsigned short ITB3AE : 1;
+			unsigned short ITA4VE : 1;
+			unsigned short ITA3AE : 1;
+			unsigned short DT4BE : 1;
+			unsigned short UT4BE : 1;
+			unsigned short DT4AE : 1;
+			unsigned short UT4AE : 1;
+			unsigned short  : 6;
+			unsigned short BF : 2;
+#else
+			unsigned short BF : 2;
+			unsigned short  : 6;
+			unsigned short UT4AE : 1;
+			unsigned short DT4AE : 1;
+			unsigned short UT4BE : 1;
+			unsigned short DT4BE : 1;
+			unsigned short ITA3AE : 1;
+			unsigned short ITA4VE : 1;
+			unsigned short ITB3AE : 1;
+			unsigned short ITB4VE : 1;
+#endif
+	} BIT;
+	} TADCR;
+	char           wk10[2];
+	unsigned short TADCORA;
+	unsigned short TADCORB;
+	unsigned short TADCOBRA;
+	unsigned short TADCOBRB;
+	char           wk11[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2;
+	char           wk12[38];
+	unsigned short TGRE;
+	unsigned short TGRF;
+	char           wk13[28];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR4;
+} st_mtu4_t;
+
+typedef struct st_mtu5 {
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFUEN : 1;
+			unsigned char NFVEN : 1;
+			unsigned char NFWEN : 1;
+			unsigned char  : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char  : 1;
+			unsigned char NFWEN : 1;
+			unsigned char NFVEN : 1;
+			unsigned char NFUEN : 1;
+#endif
+	} BIT;
+	} NFCR5;
+	char           wk1[490];
+	unsigned short TCNTU;
+	unsigned short TGRU;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char TPSC : 2;
+#endif
+	} BIT;
+	} TCRU;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char CKEG : 2;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2U;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 5;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char IOC : 5;
+#endif
+	} BIT;
+	} TIORU;
+	char           wk2[9];
+	unsigned short TCNTV;
+	unsigned short TGRV;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char TPSC : 2;
+#endif
+	} BIT;
+	} TCRV;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char CKEG : 2;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2V;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 5;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char IOC : 5;
+#endif
+	} BIT;
+	} TIORV;
+	char           wk3[9];
+	unsigned short TCNTW;
+	unsigned short TGRW;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char TPSC : 2;
+#endif
+	} BIT;
+	} TCRW;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char CKEG : 2;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2W;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 5;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char IOC : 5;
+#endif
+	} BIT;
+	} TIORW;
+	char           wk4[11];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIE5W : 1;
+			unsigned char TGIE5V : 1;
+			unsigned char TGIE5U : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TGIE5U : 1;
+			unsigned char TGIE5V : 1;
+			unsigned char TGIE5W : 1;
+#endif
+	} BIT;
+	} TIER;
+	char           wk5[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CSTW5 : 1;
+			unsigned char CSTV5 : 1;
+			unsigned char CSTU5 : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char CSTU5 : 1;
+			unsigned char CSTV5 : 1;
+			unsigned char CSTW5 : 1;
+#endif
+	} BIT;
+	} TSTR;
+	char           wk6[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMPCLR5W : 1;
+			unsigned char CMPCLR5V : 1;
+			unsigned char CMPCLR5U : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char CMPCLR5U : 1;
+			unsigned char CMPCLR5V : 1;
+			unsigned char CMPCLR5W : 1;
+#endif
+	} BIT;
+	} TCNTCMPCLR;
+} st_mtu5_t;
+
+typedef struct st_mtu6 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 3;
+#else
+			unsigned char CCLR : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char BFA : 1;
+			unsigned char BFB : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char BFB : 1;
+			unsigned char BFA : 1;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR1;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIORH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 4;
+			unsigned char IOD : 4;
+#else
+			unsigned char IOD : 4;
+			unsigned char IOC : 4;
+#endif
+	} BIT;
+	} TIORL;
+	char           wk2[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIED : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TGIED : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	char           wk3[7];
+	unsigned short TCNT;
+	char           wk4[6];
+	unsigned short TGRA;
+	unsigned short TGRB;
+	char           wk5[8];
+	unsigned short TGRC;
+	unsigned short TGRD;
+	char           wk6[4];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char TCFD : 1;
+#else
+			unsigned char TCFD : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} TSR;
+	char           wk7[11];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TTSA : 1;
+			unsigned char TTSB : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char TTSB : 1;
+			unsigned char TTSA : 1;
+#endif
+	} BIT;
+	} TBTM;
+	char           wk8[19];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2;
+	char           wk9[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CE2B : 1;
+			unsigned char CE2A : 1;
+			unsigned char CE1B : 1;
+			unsigned char CE1A : 1;
+			unsigned char CE0D : 1;
+			unsigned char CE0C : 1;
+			unsigned char CE0B : 1;
+			unsigned char CE0A : 1;
+#else
+			unsigned char CE0A : 1;
+			unsigned char CE0B : 1;
+			unsigned char CE0C : 1;
+			unsigned char CE0D : 1;
+			unsigned char CE1A : 1;
+			unsigned char CE1B : 1;
+			unsigned char CE2A : 1;
+			unsigned char CE2B : 1;
+#endif
+	} BIT;
+	} TSYCR;
+	char           wk10[33];
+	unsigned short TGRE;
+	char           wk11[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR6;
+} st_mtu6_t;
+
+typedef struct st_mtu7 {
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 3;
+#else
+			unsigned char CCLR : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char BFA : 1;
+			unsigned char BFB : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char BFB : 1;
+			unsigned char BFA : 1;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR1;
+	char           wk2[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIORH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 4;
+			unsigned char IOD : 4;
+#else
+			unsigned char IOD : 4;
+			unsigned char IOC : 4;
+#endif
+	} BIT;
+	} TIORL;
+	char           wk3[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIED : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 1;
+			unsigned char TTGE2 : 1;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char TTGE2 : 1;
+			unsigned char  : 1;
+			unsigned char TCIEV : 1;
+			unsigned char TGIED : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	char           wk4[8];
+	unsigned short TCNT;
+	char           wk5[8];
+	unsigned short TGRA;
+	unsigned short TGRB;
+	char           wk6[8];
+	unsigned short TGRC;
+	unsigned short TGRD;
+	char           wk7[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char TCFD : 1;
+#else
+			unsigned char TCFD : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} TSR;
+	char           wk8[11];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TTSA : 1;
+			unsigned char TTSB : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char TTSB : 1;
+			unsigned char TTSA : 1;
+#endif
+	} BIT;
+	} TBTM;
+	char           wk9[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ITB7VE : 1;
+			unsigned short ITB6AE : 1;
+			unsigned short ITA7VE : 1;
+			unsigned short ITA6AE : 1;
+			unsigned short DT7BE : 1;
+			unsigned short UT7BE : 1;
+			unsigned short DT7AE : 1;
+			unsigned short UT7AE : 1;
+			unsigned short  : 6;
+			unsigned short BF : 2;
+#else
+			unsigned short BF : 2;
+			unsigned short  : 6;
+			unsigned short UT7AE : 1;
+			unsigned short DT7AE : 1;
+			unsigned short UT7BE : 1;
+			unsigned short DT7BE : 1;
+			unsigned short ITA6AE : 1;
+			unsigned short ITA7VE : 1;
+			unsigned short ITB6AE : 1;
+			unsigned short ITB7VE : 1;
+#endif
+	} BIT;
+	} TADCR;
+	char           wk10[2];
+	unsigned short TADCORA;
+	unsigned short TADCORB;
+	unsigned short TADCOBRA;
+	unsigned short TADCOBRB;
+	char           wk11[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2;
+	char           wk12[38];
+	unsigned short TGRE;
+	unsigned short TGRF;
+	char           wk13[28];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR7;
+} st_mtu7_t;
+
+typedef struct st_mtu8 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR8;
+	char           wk0[871];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 3;
+#else
+			unsigned char CCLR : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char BFA : 1;
+			unsigned char BFB : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char BFB : 1;
+			unsigned char BFA : 1;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIORH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 4;
+			unsigned char IOD : 4;
+#else
+			unsigned char IOD : 4;
+			unsigned char IOC : 4;
+#endif
+	} BIT;
+	} TIORL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIED : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char TCIEV : 1;
+			unsigned char TGIED : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC2 : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char TPSC2 : 3;
+#endif
+	} BIT;
+	} TCR2;
+	char           wk2[1];
+	unsigned long  TCNT;
+	unsigned long  TGRA;
+	unsigned long  TGRB;
+	unsigned long  TGRC;
+	unsigned long  TGRD;
+} st_mtu8_t;
+
+typedef struct st_ofsm {
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MDE : 3;
+			unsigned long  : 1;
+			unsigned long BANKMD : 3;
+			unsigned long  : 25;
+#else
+			unsigned long  : 25;
+			unsigned long BANKMD : 3;
+			unsigned long  : 1;
+			unsigned long MDE : 3;
+#endif
+	} BIT;
+	} MDE;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 1;
+			unsigned long IWDTSTRT : 1;
+			unsigned long IWDTTOPS : 2;
+			unsigned long IWDTCKS : 4;
+			unsigned long IWDTRPES : 2;
+			unsigned long IWDTRPSS : 2;
+			unsigned long IWDTRSTIRQS : 1;
+			unsigned long  : 1;
+			unsigned long IWDTSLCSTP : 1;
+			unsigned long  : 2;
+			unsigned long WDTSTRT : 1;
+			unsigned long WDTTOPS : 2;
+			unsigned long WDTCKS : 4;
+			unsigned long WDTRPES : 2;
+			unsigned long WDTRPSS : 2;
+			unsigned long WDTRSTIRQS : 1;
+			unsigned long  : 3;
+#else
+			unsigned long  : 3;
+			unsigned long WDTRSTIRQS : 1;
+			unsigned long WDTRPSS : 2;
+			unsigned long WDTRPES : 2;
+			unsigned long WDTCKS : 4;
+			unsigned long WDTTOPS : 2;
+			unsigned long WDTSTRT : 1;
+			unsigned long  : 2;
+			unsigned long IWDTSLCSTP : 1;
+			unsigned long  : 1;
+			unsigned long IWDTRSTIRQS : 1;
+			unsigned long IWDTRPSS : 2;
+			unsigned long IWDTRPES : 2;
+			unsigned long IWDTCKS : 4;
+			unsigned long IWDTTOPS : 2;
+			unsigned long IWDTSTRT : 1;
+			unsigned long  : 1;
+#endif
+	} BIT;
+	} OFS0;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VDSEL : 2;
+			unsigned long LVDAS : 1;
+			unsigned long  : 5;
+			unsigned long HOCOEN : 1;
+			unsigned long  : 23;
+#else
+			unsigned long  : 23;
+			unsigned long HOCOEN : 1;
+			unsigned long  : 5;
+			unsigned long LVDAS : 1;
+			unsigned long VDSEL : 2;
+#endif
+	} BIT;
+	} OFS1;
+	char           wk0[4];
+	unsigned long  TMINF;
+	char           wk1[12];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long BANKSWP : 3;
+			unsigned long  : 29;
+#else
+			unsigned long  : 29;
+			unsigned long BANKSWP : 3;
+#endif
+	} BIT;
+	} BANKSEL;
+	char           wk2[28];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 27;
+			unsigned long SPE : 1;
+			unsigned long  : 4;
+#else
+			unsigned long  : 4;
+			unsigned long SPE : 1;
+			unsigned long  : 27;
+#endif
+	} BIT;
+	} SPCC;
+	char           wk3[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 24;
+			unsigned long TMEF : 3;
+			unsigned long  : 1;
+			unsigned long TMEFDB : 3;
+			unsigned long  : 1;
+#else
+			unsigned long  : 1;
+			unsigned long TMEFDB : 3;
+			unsigned long  : 1;
+			unsigned long TMEF : 3;
+			unsigned long  : 24;
+#endif
+	} BIT;
+	} TMEF;
+	char           wk4[4];
+	union {
+		struct {
+			unsigned long ID4:8;
+			unsigned long ID3:8;
+			unsigned long ID2:8;
+			unsigned long ID1:8;
+			unsigned long ID8:8;
+			unsigned long ID7:8;
+			unsigned long ID6:8;
+			unsigned long ID5:8;
+			unsigned long ID12:8;
+			unsigned long ID11:8;
+			unsigned long ID10:8;
+			unsigned long ID9:8;
+			unsigned long ID16:8;
+			unsigned long ID15:8;
+			unsigned long ID14:8;
+			unsigned long ID13:8;
+		} BIT;
+	} OSIS;
+	char           wk5[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FAWS : 12;
+			unsigned long  : 3;
+			unsigned long FSPR : 1;
+			unsigned long FAWE : 12;
+			unsigned long  : 3;
+			unsigned long BTFLG : 1;
+#else
+			unsigned long BTFLG : 1;
+			unsigned long  : 3;
+			unsigned long FAWE : 12;
+			unsigned long FSPR : 1;
+			unsigned long  : 3;
+			unsigned long FAWS : 12;
+#endif
+	} BIT;
+	} FAW;
+	char           wk6[8];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CODE : 32;
+#else
+			unsigned long CODE : 32;
+#endif
+	} BIT;
+	} ROMCODE;
+} st_ofsm_t;
+
+typedef struct st_pdc {
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PCKE : 1;
+			unsigned long VPS : 1;
+			unsigned long HPS : 1;
+			unsigned long PRST : 1;
+			unsigned long DFIE : 1;
+			unsigned long FEIE : 1;
+			unsigned long OVIE : 1;
+			unsigned long UDRIE : 1;
+			unsigned long VERIE : 1;
+			unsigned long HERIE : 1;
+			unsigned long PCKOE : 1;
+			unsigned long PCKDIV : 3;
+			unsigned long EDS : 1;
+			unsigned long  : 17;
+#else
+			unsigned long  : 17;
+			unsigned long EDS : 1;
+			unsigned long PCKDIV : 3;
+			unsigned long PCKOE : 1;
+			unsigned long HERIE : 1;
+			unsigned long VERIE : 1;
+			unsigned long UDRIE : 1;
+			unsigned long OVIE : 1;
+			unsigned long FEIE : 1;
+			unsigned long DFIE : 1;
+			unsigned long PRST : 1;
+			unsigned long HPS : 1;
+			unsigned long VPS : 1;
+			unsigned long PCKE : 1;
+#endif
+	} BIT;
+	} PCCR0;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PCE : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long PCE : 1;
+#endif
+	} BIT;
+	} PCCR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FBSY : 1;
+			unsigned long FEMPF : 1;
+			unsigned long FEF : 1;
+			unsigned long OVRF : 1;
+			unsigned long UDRF : 1;
+			unsigned long VERF : 1;
+			unsigned long HERF : 1;
+			unsigned long  : 25;
+#else
+			unsigned long  : 25;
+			unsigned long HERF : 1;
+			unsigned long VERF : 1;
+			unsigned long UDRF : 1;
+			unsigned long OVRF : 1;
+			unsigned long FEF : 1;
+			unsigned long FEMPF : 1;
+			unsigned long FBSY : 1;
+#endif
+	} BIT;
+	} PCSR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VSYNC : 1;
+			unsigned long HSYNC : 1;
+			unsigned long  : 30;
+#else
+			unsigned long  : 30;
+			unsigned long HSYNC : 1;
+			unsigned long VSYNC : 1;
+#endif
+	} BIT;
+	} PCMONR;
+	union {
+		unsigned long LONG;
+	} PCDR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long VST : 12;
+			unsigned long  : 4;
+			unsigned long VSZ : 12;
+			unsigned long  : 4;
+#else
+			unsigned long  : 4;
+			unsigned long VSZ : 12;
+			unsigned long  : 4;
+			unsigned long VST : 12;
+#endif
+	} BIT;
+	} VCR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long HST : 12;
+			unsigned long  : 4;
+			unsigned long HSZ : 12;
+			unsigned long  : 4;
+#else
+			unsigned long  : 4;
+			unsigned long HSZ : 12;
+			unsigned long  : 4;
+			unsigned long HST : 12;
+#endif
+	} BIT;
+	} HCR;
+} st_pdc_t;
+
+typedef struct st_poe {
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short POE0M : 2;
+			unsigned short  : 6;
+			unsigned short PIE1 : 1;
+			unsigned short  : 3;
+			unsigned short POE0F : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short POE0F : 1;
+			unsigned short  : 3;
+			unsigned short PIE1 : 1;
+			unsigned short  : 6;
+			unsigned short POE0M : 2;
+#endif
+	} BIT;
+	} ICSR1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 8;
+			unsigned short OIE1 : 1;
+			unsigned short OCE1 : 1;
+			unsigned short  : 5;
+			unsigned short OSF1 : 1;
+#else
+			unsigned short OSF1 : 1;
+			unsigned short  : 5;
+			unsigned short OCE1 : 1;
+			unsigned short OIE1 : 1;
+			unsigned short  : 8;
+#endif
+	} BIT;
+	} OCSR1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short POE4M : 2;
+			unsigned short  : 6;
+			unsigned short PIE2 : 1;
+			unsigned short  : 3;
+			unsigned short POE4F : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short POE4F : 1;
+			unsigned short  : 3;
+			unsigned short PIE2 : 1;
+			unsigned short  : 6;
+			unsigned short POE4M : 2;
+#endif
+	} BIT;
+	} ICSR2;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 8;
+			unsigned short OIE2 : 1;
+			unsigned short OCE2 : 1;
+			unsigned short  : 5;
+			unsigned short OSF2 : 1;
+#else
+			unsigned short OSF2 : 1;
+			unsigned short  : 5;
+			unsigned short OCE2 : 1;
+			unsigned short OIE2 : 1;
+			unsigned short  : 8;
+#endif
+	} BIT;
+	} OCSR2;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short POE8M : 2;
+			unsigned short  : 6;
+			unsigned short PIE3 : 1;
+			unsigned short POE8E : 1;
+			unsigned short  : 2;
+			unsigned short POE8F : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short POE8F : 1;
+			unsigned short  : 2;
+			unsigned short POE8E : 1;
+			unsigned short PIE3 : 1;
+			unsigned short  : 6;
+			unsigned short POE8M : 2;
+#endif
+	} BIT;
+	} ICSR3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MTUCH34HIZ : 1;
+			unsigned char MTUCH67HIZ : 1;
+			unsigned char MTUCH0HIZ : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char MTUCH0HIZ : 1;
+			unsigned char MTUCH67HIZ : 1;
+			unsigned char MTUCH34HIZ : 1;
+#endif
+	} BIT;
+	} SPOER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MTU0AZE : 1;
+			unsigned char MTU0BZE : 1;
+			unsigned char MTU0CZE : 1;
+			unsigned char MTU0DZE : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char MTU0DZE : 1;
+			unsigned char MTU0CZE : 1;
+			unsigned char MTU0BZE : 1;
+			unsigned char MTU0AZE : 1;
+#endif
+	} BIT;
+	} POECR1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short MTU7BDZE : 1;
+			unsigned short MTU7ACZE : 1;
+			unsigned short MTU6BDZE : 1;
+			unsigned short  : 5;
+			unsigned short MTU4BDZE : 1;
+			unsigned short MTU4ACZE : 1;
+			unsigned short MTU3BDZE : 1;
+			unsigned short  : 5;
+#else
+			unsigned short  : 5;
+			unsigned short MTU3BDZE : 1;
+			unsigned short MTU4ACZE : 1;
+			unsigned short MTU4BDZE : 1;
+			unsigned short  : 5;
+			unsigned short MTU6BDZE : 1;
+			unsigned short MTU7ACZE : 1;
+			unsigned short MTU7BDZE : 1;
+#endif
+	} BIT;
+	} POECR2;
+	char           wk0[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 2;
+			unsigned short IC2ADDMT34ZE : 1;
+			unsigned short IC3ADDMT34ZE : 1;
+			unsigned short IC4ADDMT34ZE : 1;
+			unsigned short IC5ADDMT34ZE : 1;
+			unsigned short  : 3;
+			unsigned short IC1ADDMT67ZE : 1;
+			unsigned short  : 1;
+			unsigned short IC3ADDMT67ZE : 1;
+			unsigned short IC4ADDMT67ZE : 1;
+			unsigned short IC5ADDMT67ZE : 1;
+			unsigned short  : 2;
+#else
+			unsigned short  : 2;
+			unsigned short IC5ADDMT67ZE : 1;
+			unsigned short IC4ADDMT67ZE : 1;
+			unsigned short IC3ADDMT67ZE : 1;
+			unsigned short  : 1;
+			unsigned short IC1ADDMT67ZE : 1;
+			unsigned short  : 3;
+			unsigned short IC5ADDMT34ZE : 1;
+			unsigned short IC4ADDMT34ZE : 1;
+			unsigned short IC3ADDMT34ZE : 1;
+			unsigned short IC2ADDMT34ZE : 1;
+			unsigned short  : 2;
+#endif
+	} BIT;
+	} POECR4;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 1;
+			unsigned short IC1ADDMT0ZE : 1;
+			unsigned short IC2ADDMT0ZE : 1;
+			unsigned short  : 1;
+			unsigned short IC4ADDMT0ZE : 1;
+			unsigned short IC5ADDMT0ZE : 1;
+			unsigned short  : 10;
+#else
+			unsigned short  : 10;
+			unsigned short IC5ADDMT0ZE : 1;
+			unsigned short IC4ADDMT0ZE : 1;
+			unsigned short  : 1;
+			unsigned short IC2ADDMT0ZE : 1;
+			unsigned short IC1ADDMT0ZE : 1;
+			unsigned short  : 1;
+#endif
+	} BIT;
+	} POECR5;
+	char           wk1[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short POE10M : 2;
+			unsigned short  : 6;
+			unsigned short PIE4 : 1;
+			unsigned short POE10E : 1;
+			unsigned short  : 2;
+			unsigned short POE10F : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short POE10F : 1;
+			unsigned short  : 2;
+			unsigned short POE10E : 1;
+			unsigned short PIE4 : 1;
+			unsigned short  : 6;
+			unsigned short POE10M : 2;
+#endif
+	} BIT;
+	} ICSR4;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short POE11M : 2;
+			unsigned short  : 6;
+			unsigned short PIE5 : 1;
+			unsigned short POE11E : 1;
+			unsigned short  : 2;
+			unsigned short POE11F : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short POE11F : 1;
+			unsigned short  : 2;
+			unsigned short POE11E : 1;
+			unsigned short PIE5 : 1;
+			unsigned short  : 6;
+			unsigned short POE11M : 2;
+#endif
+	} BIT;
+	} ICSR5;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short OLSG0A : 1;
+			unsigned short OLSG0B : 1;
+			unsigned short OLSG1A : 1;
+			unsigned short OLSG1B : 1;
+			unsigned short OLSG2A : 1;
+			unsigned short OLSG2B : 1;
+			unsigned short  : 1;
+			unsigned short OLSEN : 1;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short OLSEN : 1;
+			unsigned short  : 1;
+			unsigned short OLSG2B : 1;
+			unsigned short OLSG2A : 1;
+			unsigned short OLSG1B : 1;
+			unsigned short OLSG1A : 1;
+			unsigned short OLSG0B : 1;
+			unsigned short OLSG0A : 1;
+#endif
+	} BIT;
+	} ALR1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 9;
+			unsigned short OSTSTE : 1;
+			unsigned short  : 2;
+			unsigned short OSTSTF : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short OSTSTF : 1;
+			unsigned short  : 2;
+			unsigned short OSTSTE : 1;
+			unsigned short  : 9;
+#endif
+	} BIT;
+	} ICSR6;
+	char           wk2[6];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char M0ASEL : 4;
+			unsigned char M0BSEL : 4;
+#else
+			unsigned char M0BSEL : 4;
+			unsigned char M0ASEL : 4;
+#endif
+	} BIT;
+	} M0SELR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char M0CSEL : 4;
+			unsigned char M0DSEL : 4;
+#else
+			unsigned char M0DSEL : 4;
+			unsigned char M0CSEL : 4;
+#endif
+	} BIT;
+	} M0SELR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char M3BSEL : 4;
+			unsigned char M3DSEL : 4;
+#else
+			unsigned char M3DSEL : 4;
+			unsigned char M3BSEL : 4;
+#endif
+	} BIT;
+	} M3SELR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char M4ASEL : 4;
+			unsigned char M4CSEL : 4;
+#else
+			unsigned char M4CSEL : 4;
+			unsigned char M4ASEL : 4;
+#endif
+	} BIT;
+	} M4SELR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char M4BSEL : 4;
+			unsigned char M4DSEL : 4;
+#else
+			unsigned char M4DSEL : 4;
+			unsigned char M4BSEL : 4;
+#endif
+	} BIT;
+	} M4SELR2;
+	char           wk3[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char M6BSEL : 4;
+			unsigned char M6DSEL : 4;
+#else
+			unsigned char M6DSEL : 4;
+			unsigned char M6BSEL : 4;
+#endif
+	} BIT;
+	} M6SELR;
+} st_poe_t;
+
+typedef struct st_port0 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 2;
+			unsigned char B2 : 1;
+			unsigned char  : 3;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 3;
+			unsigned char B2 : 1;
+			unsigned char  : 2;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[62];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_port0_t;
+
+typedef struct st_port1 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[32];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[61];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char  : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 2;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char  : 2;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char  : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_port1_t;
+
+typedef struct st_port2 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[33];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[60];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 3;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char  : 3;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_port2_t;
+
+typedef struct st_port3 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[34];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 3;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 3;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[59];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[103];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_port3_t;
+
+typedef struct st_port4 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[35];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[58];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+} st_port4_t;
+
+typedef struct st_port5 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[36];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[57];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_port5_t;
+
+typedef struct st_port6 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[37];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[56];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+} st_port6_t;
+
+typedef struct st_port7 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[38];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[55];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 2;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 2;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_port7_t;
+
+typedef struct st_port8 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[39];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[54];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_port8_t;
+
+typedef struct st_port9 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[40];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[53];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_port9_t;
+
+typedef struct st_porta {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[41];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[52];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_porta_t;
+
+typedef struct st_portb {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[42];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[51];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_portb_t;
+
+typedef struct st_portc {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[43];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[50];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_portc_t;
+
+typedef struct st_portd {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[44];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[49];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_portd_t;
+
+typedef struct st_porte {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[45];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[48];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_porte_t;
+
+typedef struct st_portf {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[46];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[47];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+} st_portf_t;
+
+typedef struct st_portg {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[47];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[46];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char B4 : 1;
+			unsigned char B5 : 1;
+			unsigned char B6 : 1;
+			unsigned char B7 : 1;
+#else
+			unsigned char B7 : 1;
+			unsigned char B6 : 1;
+			unsigned char B5 : 1;
+			unsigned char B4 : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_portg_t;
+
+typedef struct st_portj {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PDR;
+	char           wk0[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PODR;
+	char           wk1[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PIDR;
+	char           wk2[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PMR;
+	char           wk3[49];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char B6 : 1;
+			unsigned char  : 1;
+			unsigned char B4 : 1;
+			unsigned char  : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} ODR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 2;
+			unsigned char B2 : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char B2 : 1;
+			unsigned char  : 2;
+#endif
+	} BIT;
+	} ODR1;
+	char           wk4[44];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char B3 : 1;
+			unsigned char  : 1;
+			unsigned char B5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char B5 : 1;
+			unsigned char  : 1;
+			unsigned char B3 : 1;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} PCR;
+	char           wk5[31];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR;
+	char           wk6[71];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char B0 : 1;
+			unsigned char B1 : 1;
+			unsigned char B2 : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char B2 : 1;
+			unsigned char B1 : 1;
+			unsigned char B0 : 1;
+#endif
+	} BIT;
+	} DSCR2;
+} st_portj_t;
+
+typedef struct st_ppg0 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char G0CMS : 2;
+			unsigned char G1CMS : 2;
+			unsigned char G2CMS : 2;
+			unsigned char G3CMS : 2;
+#else
+			unsigned char G3CMS : 2;
+			unsigned char G2CMS : 2;
+			unsigned char G1CMS : 2;
+			unsigned char G0CMS : 2;
+#endif
+	} BIT;
+	} PCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char G0NOV : 1;
+			unsigned char G1NOV : 1;
+			unsigned char G2NOV : 1;
+			unsigned char G3NOV : 1;
+			unsigned char G0INV : 1;
+			unsigned char G1INV : 1;
+			unsigned char G2INV : 1;
+			unsigned char G3INV : 1;
+#else
+			unsigned char G3INV : 1;
+			unsigned char G2INV : 1;
+			unsigned char G1INV : 1;
+			unsigned char G0INV : 1;
+			unsigned char G3NOV : 1;
+			unsigned char G2NOV : 1;
+			unsigned char G1NOV : 1;
+			unsigned char G0NOV : 1;
+#endif
+	} BIT;
+	} PMR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDER8 : 1;
+			unsigned char NDER9 : 1;
+			unsigned char NDER10 : 1;
+			unsigned char NDER11 : 1;
+			unsigned char NDER12 : 1;
+			unsigned char NDER13 : 1;
+			unsigned char NDER14 : 1;
+			unsigned char NDER15 : 1;
+#else
+			unsigned char NDER15 : 1;
+			unsigned char NDER14 : 1;
+			unsigned char NDER13 : 1;
+			unsigned char NDER12 : 1;
+			unsigned char NDER11 : 1;
+			unsigned char NDER10 : 1;
+			unsigned char NDER9 : 1;
+			unsigned char NDER8 : 1;
+#endif
+	} BIT;
+	} NDERH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDER0 : 1;
+			unsigned char NDER1 : 1;
+			unsigned char NDER2 : 1;
+			unsigned char NDER3 : 1;
+			unsigned char NDER4 : 1;
+			unsigned char NDER5 : 1;
+			unsigned char NDER6 : 1;
+			unsigned char NDER7 : 1;
+#else
+			unsigned char NDER7 : 1;
+			unsigned char NDER6 : 1;
+			unsigned char NDER5 : 1;
+			unsigned char NDER4 : 1;
+			unsigned char NDER3 : 1;
+			unsigned char NDER2 : 1;
+			unsigned char NDER1 : 1;
+			unsigned char NDER0 : 1;
+#endif
+	} BIT;
+	} NDERL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char POD8 : 1;
+			unsigned char POD9 : 1;
+			unsigned char POD10 : 1;
+			unsigned char POD11 : 1;
+			unsigned char POD12 : 1;
+			unsigned char POD13 : 1;
+			unsigned char POD14 : 1;
+			unsigned char POD15 : 1;
+#else
+			unsigned char POD15 : 1;
+			unsigned char POD14 : 1;
+			unsigned char POD13 : 1;
+			unsigned char POD12 : 1;
+			unsigned char POD11 : 1;
+			unsigned char POD10 : 1;
+			unsigned char POD9 : 1;
+			unsigned char POD8 : 1;
+#endif
+	} BIT;
+	} PODRH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char POD0 : 1;
+			unsigned char POD1 : 1;
+			unsigned char POD2 : 1;
+			unsigned char POD3 : 1;
+			unsigned char POD4 : 1;
+			unsigned char POD5 : 1;
+			unsigned char POD6 : 1;
+			unsigned char POD7 : 1;
+#else
+			unsigned char POD7 : 1;
+			unsigned char POD6 : 1;
+			unsigned char POD5 : 1;
+			unsigned char POD4 : 1;
+			unsigned char POD3 : 1;
+			unsigned char POD2 : 1;
+			unsigned char POD1 : 1;
+			unsigned char POD0 : 1;
+#endif
+	} BIT;
+	} PODRL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDR8 : 1;
+			unsigned char NDR9 : 1;
+			unsigned char NDR10 : 1;
+			unsigned char NDR11 : 1;
+			unsigned char NDR12 : 1;
+			unsigned char NDR13 : 1;
+			unsigned char NDR14 : 1;
+			unsigned char NDR15 : 1;
+#else
+			unsigned char NDR15 : 1;
+			unsigned char NDR14 : 1;
+			unsigned char NDR13 : 1;
+			unsigned char NDR12 : 1;
+			unsigned char NDR11 : 1;
+			unsigned char NDR10 : 1;
+			unsigned char NDR9 : 1;
+			unsigned char NDR8 : 1;
+#endif
+	} BIT;
+	} NDRH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDR0 : 1;
+			unsigned char NDR1 : 1;
+			unsigned char NDR2 : 1;
+			unsigned char NDR3 : 1;
+			unsigned char NDR4 : 1;
+			unsigned char NDR5 : 1;
+			unsigned char NDR6 : 1;
+			unsigned char NDR7 : 1;
+#else
+			unsigned char NDR7 : 1;
+			unsigned char NDR6 : 1;
+			unsigned char NDR5 : 1;
+			unsigned char NDR4 : 1;
+			unsigned char NDR3 : 1;
+			unsigned char NDR2 : 1;
+			unsigned char NDR1 : 1;
+			unsigned char NDR0 : 1;
+#endif
+	} BIT;
+	} NDRL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDR8 : 1;
+			unsigned char NDR9 : 1;
+			unsigned char NDR10 : 1;
+			unsigned char NDR11 : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char NDR11 : 1;
+			unsigned char NDR10 : 1;
+			unsigned char NDR9 : 1;
+			unsigned char NDR8 : 1;
+#endif
+	} BIT;
+	} NDRH2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDR0 : 1;
+			unsigned char NDR1 : 1;
+			unsigned char NDR2 : 1;
+			unsigned char NDR3 : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char NDR3 : 1;
+			unsigned char NDR2 : 1;
+			unsigned char NDR1 : 1;
+			unsigned char NDR0 : 1;
+#endif
+	} BIT;
+	} NDRL2;
+} st_ppg0_t;
+
+typedef struct st_ppg1 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PTRSL : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char PTRSL : 1;
+#endif
+	} BIT;
+	} PTRSLR;
+	char           wk0[5];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char G0CMS : 2;
+			unsigned char G1CMS : 2;
+			unsigned char G2CMS : 2;
+			unsigned char G3CMS : 2;
+#else
+			unsigned char G3CMS : 2;
+			unsigned char G2CMS : 2;
+			unsigned char G1CMS : 2;
+			unsigned char G0CMS : 2;
+#endif
+	} BIT;
+	} PCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char G0NOV : 1;
+			unsigned char G1NOV : 1;
+			unsigned char G2NOV : 1;
+			unsigned char G3NOV : 1;
+			unsigned char G0INV : 1;
+			unsigned char G1INV : 1;
+			unsigned char G2INV : 1;
+			unsigned char G3INV : 1;
+#else
+			unsigned char G3INV : 1;
+			unsigned char G2INV : 1;
+			unsigned char G1INV : 1;
+			unsigned char G0INV : 1;
+			unsigned char G3NOV : 1;
+			unsigned char G2NOV : 1;
+			unsigned char G1NOV : 1;
+			unsigned char G0NOV : 1;
+#endif
+	} BIT;
+	} PMR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDER24 : 1;
+			unsigned char NDER25 : 1;
+			unsigned char NDER26 : 1;
+			unsigned char NDER27 : 1;
+			unsigned char NDER28 : 1;
+			unsigned char NDER29 : 1;
+			unsigned char NDER30 : 1;
+			unsigned char NDER31 : 1;
+#else
+			unsigned char NDER31 : 1;
+			unsigned char NDER30 : 1;
+			unsigned char NDER29 : 1;
+			unsigned char NDER28 : 1;
+			unsigned char NDER27 : 1;
+			unsigned char NDER26 : 1;
+			unsigned char NDER25 : 1;
+			unsigned char NDER24 : 1;
+#endif
+	} BIT;
+	} NDERH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDER16 : 1;
+			unsigned char NDER17 : 1;
+			unsigned char NDER18 : 1;
+			unsigned char NDER19 : 1;
+			unsigned char NDER20 : 1;
+			unsigned char NDER21 : 1;
+			unsigned char NDER22 : 1;
+			unsigned char NDER23 : 1;
+#else
+			unsigned char NDER23 : 1;
+			unsigned char NDER22 : 1;
+			unsigned char NDER21 : 1;
+			unsigned char NDER20 : 1;
+			unsigned char NDER19 : 1;
+			unsigned char NDER18 : 1;
+			unsigned char NDER17 : 1;
+			unsigned char NDER16 : 1;
+#endif
+	} BIT;
+	} NDERL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char POD24 : 1;
+			unsigned char POD25 : 1;
+			unsigned char POD26 : 1;
+			unsigned char POD27 : 1;
+			unsigned char POD28 : 1;
+			unsigned char POD29 : 1;
+			unsigned char POD30 : 1;
+			unsigned char POD31 : 1;
+#else
+			unsigned char POD31 : 1;
+			unsigned char POD30 : 1;
+			unsigned char POD29 : 1;
+			unsigned char POD28 : 1;
+			unsigned char POD27 : 1;
+			unsigned char POD26 : 1;
+			unsigned char POD25 : 1;
+			unsigned char POD24 : 1;
+#endif
+	} BIT;
+	} PODRH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char POD16 : 1;
+			unsigned char POD17 : 1;
+			unsigned char POD18 : 1;
+			unsigned char POD19 : 1;
+			unsigned char POD20 : 1;
+			unsigned char POD21 : 1;
+			unsigned char POD22 : 1;
+			unsigned char POD23 : 1;
+#else
+			unsigned char POD23 : 1;
+			unsigned char POD22 : 1;
+			unsigned char POD21 : 1;
+			unsigned char POD20 : 1;
+			unsigned char POD19 : 1;
+			unsigned char POD18 : 1;
+			unsigned char POD17 : 1;
+			unsigned char POD16 : 1;
+#endif
+	} BIT;
+	} PODRL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDR24 : 1;
+			unsigned char NDR25 : 1;
+			unsigned char NDR26 : 1;
+			unsigned char NDR27 : 1;
+			unsigned char NDR28 : 1;
+			unsigned char NDR29 : 1;
+			unsigned char NDR30 : 1;
+			unsigned char NDR31 : 1;
+#else
+			unsigned char NDR31 : 1;
+			unsigned char NDR30 : 1;
+			unsigned char NDR29 : 1;
+			unsigned char NDR28 : 1;
+			unsigned char NDR27 : 1;
+			unsigned char NDR26 : 1;
+			unsigned char NDR25 : 1;
+			unsigned char NDR24 : 1;
+#endif
+	} BIT;
+	} NDRH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDR16 : 1;
+			unsigned char NDR17 : 1;
+			unsigned char NDR18 : 1;
+			unsigned char NDR19 : 1;
+			unsigned char NDR20 : 1;
+			unsigned char NDR21 : 1;
+			unsigned char NDR22 : 1;
+			unsigned char NDR23 : 1;
+#else
+			unsigned char NDR23 : 1;
+			unsigned char NDR22 : 1;
+			unsigned char NDR21 : 1;
+			unsigned char NDR20 : 1;
+			unsigned char NDR19 : 1;
+			unsigned char NDR18 : 1;
+			unsigned char NDR17 : 1;
+			unsigned char NDR16 : 1;
+#endif
+	} BIT;
+	} NDRL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDR24 : 1;
+			unsigned char NDR25 : 1;
+			unsigned char NDR26 : 1;
+			unsigned char NDR27 : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char NDR27 : 1;
+			unsigned char NDR26 : 1;
+			unsigned char NDR25 : 1;
+			unsigned char NDR24 : 1;
+#endif
+	} BIT;
+	} NDRH2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NDR16 : 1;
+			unsigned char NDR17 : 1;
+			unsigned char NDR18 : 1;
+			unsigned char NDR19 : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char NDR19 : 1;
+			unsigned char NDR18 : 1;
+			unsigned char NDR17 : 1;
+			unsigned char NDR16 : 1;
+#endif
+	} BIT;
+	} NDRL2;
+} st_ppg1_t;
+
+typedef struct st_qspi {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 1;
+			unsigned char SPSSLIE : 1;
+			unsigned char  : 1;
+			unsigned char MSTR : 1;
+			unsigned char  : 1;
+			unsigned char SPTIE : 1;
+			unsigned char SPE : 1;
+			unsigned char SPRIE : 1;
+#else
+			unsigned char SPRIE : 1;
+			unsigned char SPE : 1;
+			unsigned char SPTIE : 1;
+			unsigned char  : 1;
+			unsigned char MSTR : 1;
+			unsigned char  : 1;
+			unsigned char SPSSLIE : 1;
+			unsigned char  : 1;
+#endif
+	} BIT;
+	} SPCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SSLP : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char SSLP : 1;
+#endif
+	} BIT;
+	} SSLP;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPLP : 1;
+			unsigned char IO2FV : 1;
+			unsigned char IO3FV : 1;
+			unsigned char  : 1;
+			unsigned char MOIFV : 1;
+			unsigned char MOIFE : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char MOIFE : 1;
+			unsigned char MOIFV : 1;
+			unsigned char  : 1;
+			unsigned char IO3FV : 1;
+			unsigned char IO2FV : 1;
+			unsigned char SPLP : 1;
+#endif
+	} BIT;
+	} SPPCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 4;
+			unsigned char SPSSLF : 1;
+			unsigned char SPTEF : 1;
+			unsigned char TREND : 1;
+			unsigned char SPRFF : 1;
+#else
+			unsigned char SPRFF : 1;
+			unsigned char TREND : 1;
+			unsigned char SPTEF : 1;
+			unsigned char SPSSLF : 1;
+			unsigned char  : 4;
+#endif
+	} BIT;
+	} SPSR;
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned short H;
+		} WORD;
+		struct {
+			unsigned char HH;
+		} BYTE;
+	} SPDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPSC : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char SPSC : 2;
+#endif
+	} BIT;
+	} SPSCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPSS : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char SPSS : 2;
+#endif
+	} BIT;
+	} SPSSR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPBR0 : 1;
+			unsigned char SPBR1 : 1;
+			unsigned char SPBR2 : 1;
+			unsigned char SPBR3 : 1;
+			unsigned char SPBR4 : 1;
+			unsigned char SPBR5 : 1;
+			unsigned char SPBR6 : 1;
+			unsigned char SPBR7 : 1;
+#else
+			unsigned char SPBR7 : 1;
+			unsigned char SPBR6 : 1;
+			unsigned char SPBR5 : 1;
+			unsigned char SPBR4 : 1;
+			unsigned char SPBR3 : 1;
+			unsigned char SPBR2 : 1;
+			unsigned char SPBR1 : 1;
+			unsigned char SPBR0 : 1;
+#endif
+	} BIT;
+	} SPBR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char TXDMY : 1;
+#else
+			unsigned char TXDMY : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} SPDCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SCKDL : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SCKDL : 3;
+#endif
+	} BIT;
+	} SPCKD;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLNDL : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SLNDL : 3;
+#endif
+	} BIT;
+	} SSLND;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPNDL : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SPNDL : 3;
+#endif
+	} BIT;
+	} SPND;
+	char           wk0[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SPRW : 1;
+			unsigned short SPIMOD : 2;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SPIMOD : 2;
+			unsigned short SPRW : 1;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SPRW : 1;
+			unsigned short SPIMOD : 2;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SPIMOD : 2;
+			unsigned short SPRW : 1;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SPRW : 1;
+			unsigned short SPIMOD : 2;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SPIMOD : 2;
+			unsigned short SPRW : 1;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD2;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SPRW : 1;
+			unsigned short SPIMOD : 2;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SPIMOD : 2;
+			unsigned short SPRW : 1;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RXTRG : 3;
+			unsigned char TXTRGEX : 1;
+			unsigned char TXTRG : 2;
+			unsigned char RXRST : 1;
+			unsigned char TXRST : 1;
+#else
+			unsigned char TXRST : 1;
+			unsigned char RXRST : 1;
+			unsigned char TXTRG : 2;
+			unsigned char TXTRGEX : 1;
+			unsigned char RXTRG : 3;
+#endif
+	} BIT;
+	} SPBFCR;
+	char           wk1[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RXBC : 6;
+			unsigned short  : 2;
+			unsigned short TXBC : 6;
+			unsigned short  : 2;
+#else
+			unsigned short  : 2;
+			unsigned short TXBC : 6;
+			unsigned short  : 2;
+			unsigned short RXBC : 6;
+#endif
+	} BIT;
+	} SPBDCR;
+	unsigned long  SPBMUL0;
+	unsigned long  SPBMUL1;
+	unsigned long  SPBMUL2;
+	unsigned long  SPBMUL3;
+} st_qspi_t;
+
+typedef struct st_ram {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RAMMODE : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char RAMMODE : 2;
+#endif
+	} BIT;
+	} RAMMODE;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RAMERR : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char RAMERR : 1;
+#endif
+	} BIT;
+	} RAMSTS;
+	char           wk0[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RAMPRCR : 1;
+			unsigned char KW : 7;
+#else
+			unsigned char KW : 7;
+			unsigned char RAMPRCR : 1;
+#endif
+	} BIT;
+	} RAMPRCR;
+	char           wk1[3];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 3;
+			unsigned long READ : 16;
+			unsigned long  : 13;
+#else
+			unsigned long  : 13;
+			unsigned long READ : 16;
+			unsigned long  : 3;
+#endif
+	} BIT;
+	} RAMECAD;
+	char           wk2[52];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char EXRAMMODE : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char EXRAMMODE : 2;
+#endif
+	} BIT;
+	} EXRAMMODE;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char EXRAMERR : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char EXRAMERR : 1;
+#endif
+	} BIT;
+	} EXRAMSTS;
+	char           wk3[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char EXRAMPRCR : 1;
+			unsigned char KW : 7;
+#else
+			unsigned char KW : 7;
+			unsigned char EXRAMPRCR : 1;
+#endif
+	} BIT;
+	} EXRAMPRCR;
+	char           wk4[3];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 3;
+			unsigned long READ : 16;
+			unsigned long  : 13;
+#else
+			unsigned long  : 13;
+			unsigned long READ : 16;
+			unsigned long  : 3;
+#endif
+	} BIT;
+	} EXRAMECAD;
+} st_ram_t;
+
+typedef struct st_riic {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SDAI : 1;
+			unsigned char SCLI : 1;
+			unsigned char SDAO : 1;
+			unsigned char SCLO : 1;
+			unsigned char SOWP : 1;
+			unsigned char CLO : 1;
+			unsigned char IICRST : 1;
+			unsigned char ICE : 1;
+#else
+			unsigned char ICE : 1;
+			unsigned char IICRST : 1;
+			unsigned char CLO : 1;
+			unsigned char SOWP : 1;
+			unsigned char SCLO : 1;
+			unsigned char SDAO : 1;
+			unsigned char SCLI : 1;
+			unsigned char SDAI : 1;
+#endif
+	} BIT;
+	} ICCR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 1;
+			unsigned char ST : 1;
+			unsigned char RS : 1;
+			unsigned char SP : 1;
+			unsigned char  : 1;
+			unsigned char TRS : 1;
+			unsigned char MST : 1;
+			unsigned char BBSY : 1;
+#else
+			unsigned char BBSY : 1;
+			unsigned char MST : 1;
+			unsigned char TRS : 1;
+			unsigned char  : 1;
+			unsigned char SP : 1;
+			unsigned char RS : 1;
+			unsigned char ST : 1;
+			unsigned char  : 1;
+#endif
+	} BIT;
+	} ICCR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BC : 3;
+			unsigned char BCWP : 1;
+			unsigned char CKS : 3;
+			unsigned char MTWP : 1;
+#else
+			unsigned char MTWP : 1;
+			unsigned char CKS : 3;
+			unsigned char BCWP : 1;
+			unsigned char BC : 3;
+#endif
+	} BIT;
+	} ICMR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TMOS : 1;
+			unsigned char TMOL : 1;
+			unsigned char TMOH : 1;
+			unsigned char  : 1;
+			unsigned char SDDL : 3;
+			unsigned char DLCS : 1;
+#else
+			unsigned char DLCS : 1;
+			unsigned char SDDL : 3;
+			unsigned char  : 1;
+			unsigned char TMOH : 1;
+			unsigned char TMOL : 1;
+			unsigned char TMOS : 1;
+#endif
+	} BIT;
+	} ICMR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NF : 2;
+			unsigned char ACKBR : 1;
+			unsigned char ACKBT : 1;
+			unsigned char ACKWP : 1;
+			unsigned char RDRFS : 1;
+			unsigned char WAIT : 1;
+			unsigned char SMBS : 1;
+#else
+			unsigned char SMBS : 1;
+			unsigned char WAIT : 1;
+			unsigned char RDRFS : 1;
+			unsigned char ACKWP : 1;
+			unsigned char ACKBT : 1;
+			unsigned char ACKBR : 1;
+			unsigned char NF : 2;
+#endif
+	} BIT;
+	} ICMR3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TMOE : 1;
+			unsigned char MALE : 1;
+			unsigned char NALE : 1;
+			unsigned char SALE : 1;
+			unsigned char NACKE : 1;
+			unsigned char NFE : 1;
+			unsigned char SCLE : 1;
+			unsigned char FMPE : 1;
+#else
+			unsigned char FMPE : 1;
+			unsigned char SCLE : 1;
+			unsigned char NFE : 1;
+			unsigned char NACKE : 1;
+			unsigned char SALE : 1;
+			unsigned char NALE : 1;
+			unsigned char MALE : 1;
+			unsigned char TMOE : 1;
+#endif
+	} BIT;
+	} ICFER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SAR0E : 1;
+			unsigned char SAR1E : 1;
+			unsigned char SAR2E : 1;
+			unsigned char GCAE : 1;
+			unsigned char  : 1;
+			unsigned char DIDE : 1;
+			unsigned char  : 1;
+			unsigned char HOAE : 1;
+#else
+			unsigned char HOAE : 1;
+			unsigned char  : 1;
+			unsigned char DIDE : 1;
+			unsigned char  : 1;
+			unsigned char GCAE : 1;
+			unsigned char SAR2E : 1;
+			unsigned char SAR1E : 1;
+			unsigned char SAR0E : 1;
+#endif
+	} BIT;
+	} ICSER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TMOIE : 1;
+			unsigned char ALIE : 1;
+			unsigned char STIE : 1;
+			unsigned char SPIE : 1;
+			unsigned char NAKIE : 1;
+			unsigned char RIE : 1;
+			unsigned char TEIE : 1;
+			unsigned char TIE : 1;
+#else
+			unsigned char TIE : 1;
+			unsigned char TEIE : 1;
+			unsigned char RIE : 1;
+			unsigned char NAKIE : 1;
+			unsigned char SPIE : 1;
+			unsigned char STIE : 1;
+			unsigned char ALIE : 1;
+			unsigned char TMOIE : 1;
+#endif
+	} BIT;
+	} ICIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char AAS0 : 1;
+			unsigned char AAS1 : 1;
+			unsigned char AAS2 : 1;
+			unsigned char GCA : 1;
+			unsigned char  : 1;
+			unsigned char DID : 1;
+			unsigned char  : 1;
+			unsigned char HOA : 1;
+#else
+			unsigned char HOA : 1;
+			unsigned char  : 1;
+			unsigned char DID : 1;
+			unsigned char  : 1;
+			unsigned char GCA : 1;
+			unsigned char AAS2 : 1;
+			unsigned char AAS1 : 1;
+			unsigned char AAS0 : 1;
+#endif
+	} BIT;
+	} ICSR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TMOF : 1;
+			unsigned char AL : 1;
+			unsigned char START : 1;
+			unsigned char STOP : 1;
+			unsigned char NACKF : 1;
+			unsigned char RDRF : 1;
+			unsigned char TEND : 1;
+			unsigned char TDRE : 1;
+#else
+			unsigned char TDRE : 1;
+			unsigned char TEND : 1;
+			unsigned char RDRF : 1;
+			unsigned char NACKF : 1;
+			unsigned char STOP : 1;
+			unsigned char START : 1;
+			unsigned char AL : 1;
+			unsigned char TMOF : 1;
+#endif
+	} BIT;
+	} ICSR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SVA0 : 1;
+			unsigned char SVA : 7;
+#else
+			unsigned char SVA : 7;
+			unsigned char SVA0 : 1;
+#endif
+	} BIT;
+	} SARL0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char FS : 1;
+			unsigned char SVA : 2;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SVA : 2;
+			unsigned char FS : 1;
+#endif
+	} BIT;
+	} SARU0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SVA0 : 1;
+			unsigned char SVA : 7;
+#else
+			unsigned char SVA : 7;
+			unsigned char SVA0 : 1;
+#endif
+	} BIT;
+	} SARL1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char FS : 1;
+			unsigned char SVA : 2;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SVA : 2;
+			unsigned char FS : 1;
+#endif
+	} BIT;
+	} SARU1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SVA0 : 1;
+			unsigned char SVA : 7;
+#else
+			unsigned char SVA : 7;
+			unsigned char SVA0 : 1;
+#endif
+	} BIT;
+	} SARL2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char FS : 1;
+			unsigned char SVA : 2;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SVA : 2;
+			unsigned char FS : 1;
+#endif
+	} BIT;
+	} SARU2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BRL : 5;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char BRL : 5;
+#endif
+	} BIT;
+	} ICBRL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BRH : 5;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char BRH : 5;
+#endif
+	} BIT;
+	} ICBRH;
+	unsigned char  ICDRT;
+	unsigned char  ICDRR;
+} st_riic_t;
+
+typedef struct st_rspi {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPMS : 1;
+			unsigned char TXMD : 1;
+			unsigned char MODFEN : 1;
+			unsigned char MSTR : 1;
+			unsigned char SPEIE : 1;
+			unsigned char SPTIE : 1;
+			unsigned char SPE : 1;
+			unsigned char SPRIE : 1;
+#else
+			unsigned char SPRIE : 1;
+			unsigned char SPE : 1;
+			unsigned char SPTIE : 1;
+			unsigned char SPEIE : 1;
+			unsigned char MSTR : 1;
+			unsigned char MODFEN : 1;
+			unsigned char TXMD : 1;
+			unsigned char SPMS : 1;
+#endif
+	} BIT;
+	} SPCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SSL0P : 1;
+			unsigned char SSL1P : 1;
+			unsigned char SSL2P : 1;
+			unsigned char SSL3P : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char SSL3P : 1;
+			unsigned char SSL2P : 1;
+			unsigned char SSL1P : 1;
+			unsigned char SSL0P : 1;
+#endif
+	} BIT;
+	} SSLP;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPLP : 1;
+			unsigned char SPLP2 : 1;
+			unsigned char  : 2;
+			unsigned char MOIFV : 1;
+			unsigned char MOIFE : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char MOIFE : 1;
+			unsigned char MOIFV : 1;
+			unsigned char  : 2;
+			unsigned char SPLP2 : 1;
+			unsigned char SPLP : 1;
+#endif
+	} BIT;
+	} SPPCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OVRF : 1;
+			unsigned char IDLNF : 1;
+			unsigned char MODF : 1;
+			unsigned char PERF : 1;
+			unsigned char UDRF : 1;
+			unsigned char SPTEF : 1;
+			unsigned char  : 1;
+			unsigned char SPRF : 1;
+#else
+			unsigned char SPRF : 1;
+			unsigned char  : 1;
+			unsigned char SPTEF : 1;
+			unsigned char UDRF : 1;
+			unsigned char PERF : 1;
+			unsigned char MODF : 1;
+			unsigned char IDLNF : 1;
+			unsigned char OVRF : 1;
+#endif
+	} BIT;
+	} SPSR;
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned short H;
+		} WORD;
+		struct {
+			unsigned char HH;
+		} BYTE;
+	} SPDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPSLN : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SPSLN : 3;
+#endif
+	} BIT;
+	} SPSCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPCP : 3;
+			unsigned char  : 1;
+			unsigned char SPECM : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char SPECM : 3;
+			unsigned char  : 1;
+			unsigned char SPCP : 3;
+#endif
+	} BIT;
+	} SPSSR;
+	unsigned char  SPBR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPFC : 2;
+			unsigned char  : 2;
+			unsigned char SPRDTD : 1;
+			unsigned char SPLW : 1;
+			unsigned char SPBYT : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char SPBYT : 1;
+			unsigned char SPLW : 1;
+			unsigned char SPRDTD : 1;
+			unsigned char  : 2;
+			unsigned char SPFC : 2;
+#endif
+	} BIT;
+	} SPDCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SCKDL : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SCKDL : 3;
+#endif
+	} BIT;
+	} SPCKD;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SLNDL : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SLNDL : 3;
+#endif
+	} BIT;
+	} SSLND;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPNDL : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SPNDL : 3;
+#endif
+	} BIT;
+	} SPND;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SPPE : 1;
+			unsigned char SPOE : 1;
+			unsigned char SPIIE : 1;
+			unsigned char PTE : 1;
+			unsigned char SCKASE : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char SCKASE : 1;
+			unsigned char PTE : 1;
+			unsigned char SPIIE : 1;
+			unsigned char SPOE : 1;
+			unsigned char SPPE : 1;
+#endif
+	} BIT;
+	} SPCR2;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SSLA : 3;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SSLA : 3;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SSLA : 3;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SSLA : 3;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SSLA : 3;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SSLA : 3;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD2;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SSLA : 3;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SSLA : 3;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD3;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SSLA : 3;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SSLA : 3;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD4;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SSLA : 3;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SSLA : 3;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD5;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SSLA : 3;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SSLA : 3;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD6;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CPHA : 1;
+			unsigned short CPOL : 1;
+			unsigned short BRDV : 2;
+			unsigned short SSLA : 3;
+			unsigned short SSLKP : 1;
+			unsigned short SPB : 4;
+			unsigned short LSBF : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SCKDEN : 1;
+#else
+			unsigned short SCKDEN : 1;
+			unsigned short SLNDEN : 1;
+			unsigned short SPNDEN : 1;
+			unsigned short LSBF : 1;
+			unsigned short SPB : 4;
+			unsigned short SSLKP : 1;
+			unsigned short SSLA : 3;
+			unsigned short BRDV : 2;
+			unsigned short CPOL : 1;
+			unsigned short CPHA : 1;
+#endif
+	} BIT;
+	} SPCMD7;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BYSW : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char BYSW : 1;
+#endif
+	} BIT;
+	} SPDCR2;
+} st_rspi_t;
+
+typedef struct st_rtc {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char F64HZ : 1;
+			unsigned char F32HZ : 1;
+			unsigned char F16HZ : 1;
+			unsigned char F8HZ : 1;
+			unsigned char F4HZ : 1;
+			unsigned char F2HZ : 1;
+			unsigned char F1HZ : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char F1HZ : 1;
+			unsigned char F2HZ : 1;
+			unsigned char F4HZ : 1;
+			unsigned char F8HZ : 1;
+			unsigned char F16HZ : 1;
+			unsigned char F32HZ : 1;
+			unsigned char F64HZ : 1;
+#endif
+	} BIT;
+	} R64CNT;
+	char           wk0[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SEC1 : 4;
+			unsigned char SEC10 : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char SEC10 : 3;
+			unsigned char SEC1 : 4;
+#endif
+	} BIT;
+		} RSECCNT;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNT : 8;
+#else
+			unsigned char BCNT : 8;
+#endif
+	} BIT;
+		} BCNT0;
+	};
+	char           wk1[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MIN1 : 4;
+			unsigned char MIN10 : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char MIN10 : 3;
+			unsigned char MIN1 : 4;
+#endif
+	} BIT;
+		} RMINCNT;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNT : 8;
+#else
+			unsigned char BCNT : 8;
+#endif
+	} BIT;
+		} BCNT1;
+	};
+	char           wk2[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char HR1 : 4;
+			unsigned char HR10 : 2;
+			unsigned char PM : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PM : 1;
+			unsigned char HR10 : 2;
+			unsigned char HR1 : 4;
+#endif
+	} BIT;
+		} RHRCNT;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNT : 8;
+#else
+			unsigned char BCNT : 8;
+#endif
+	} BIT;
+		} BCNT2;
+	};
+	char           wk3[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DAYW : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char DAYW : 3;
+#endif
+	} BIT;
+		} RWKCNT;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNT : 8;
+#else
+			unsigned char BCNT : 8;
+#endif
+	} BIT;
+		} BCNT3;
+	};
+	char           wk4[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DATE1 : 4;
+			unsigned char DATE10 : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char DATE10 : 2;
+			unsigned char DATE1 : 4;
+#endif
+	} BIT;
+	} RDAYCNT;
+	char           wk5[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MON1 : 4;
+			unsigned char MON10 : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char MON10 : 1;
+			unsigned char MON1 : 4;
+#endif
+	} BIT;
+	} RMONCNT;
+	char           wk6[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short YR1 : 4;
+			unsigned short YR10 : 4;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short YR10 : 4;
+			unsigned short YR1 : 4;
+#endif
+	} BIT;
+	} RYRCNT;
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SEC1 : 4;
+			unsigned char SEC10 : 3;
+			unsigned char ENB : 1;
+#else
+			unsigned char ENB : 1;
+			unsigned char SEC10 : 3;
+			unsigned char SEC1 : 4;
+#endif
+	} BIT;
+		} RSECAR;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTAR : 8;
+#else
+			unsigned char BCNTAR : 8;
+#endif
+	} BIT;
+		} BCNT0AR;
+	};
+	char           wk7[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MIN1 : 4;
+			unsigned char MIN10 : 3;
+			unsigned char ENB : 1;
+#else
+			unsigned char ENB : 1;
+			unsigned char MIN10 : 3;
+			unsigned char MIN1 : 4;
+#endif
+	} BIT;
+		} RMINAR;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTAR : 8;
+#else
+			unsigned char BCNTAR : 8;
+#endif
+	} BIT;
+		} BCNT1AR;
+	};
+	char           wk8[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char HR1 : 4;
+			unsigned char HR10 : 2;
+			unsigned char PM : 1;
+			unsigned char ENB : 1;
+#else
+			unsigned char ENB : 1;
+			unsigned char PM : 1;
+			unsigned char HR10 : 2;
+			unsigned char HR1 : 4;
+#endif
+	} BIT;
+		} RHRAR;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTAR : 8;
+#else
+			unsigned char BCNTAR : 8;
+#endif
+	} BIT;
+		} BCNT2AR;
+	};
+	char           wk9[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DAYW : 3;
+			unsigned char  : 4;
+			unsigned char ENB : 1;
+#else
+			unsigned char ENB : 1;
+			unsigned char  : 4;
+			unsigned char DAYW : 3;
+#endif
+	} BIT;
+		} RWKAR;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTAR : 8;
+#else
+			unsigned char BCNTAR : 8;
+#endif
+	} BIT;
+		} BCNT3AR;
+	};
+	char           wk10[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DATE1 : 4;
+			unsigned char DATE10 : 2;
+			unsigned char  : 1;
+			unsigned char ENB : 1;
+#else
+			unsigned char ENB : 1;
+			unsigned char  : 1;
+			unsigned char DATE10 : 2;
+			unsigned char DATE1 : 4;
+#endif
+	} BIT;
+		} RDAYAR;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ENB : 8;
+#else
+			unsigned char ENB : 8;
+#endif
+	} BIT;
+		} BCNT0AER;
+	};
+	char           wk11[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MON1 : 4;
+			unsigned char MON10 : 1;
+			unsigned char  : 2;
+			unsigned char ENB : 1;
+#else
+			unsigned char ENB : 1;
+			unsigned char  : 2;
+			unsigned char MON10 : 1;
+			unsigned char MON1 : 4;
+#endif
+	} BIT;
+		} RMONAR;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ENB : 8;
+#else
+			unsigned char ENB : 8;
+#endif
+	} BIT;
+		} BCNT1AER;
+	};
+	char           wk12[1];
+	union {
+		union {
+			unsigned short WORD;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short YR1 : 4;
+			unsigned short YR10 : 4;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short YR10 : 4;
+			unsigned short YR1 : 4;
+#endif
+	} BIT;
+		} RYRAR;
+		union {
+			unsigned short WORD;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ENB : 8;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short ENB : 8;
+#endif
+	} BIT;
+		} BCNT2AER;
+	};
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char ENB : 1;
+#else
+			unsigned char ENB : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+		} RYRAREN;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ENB : 8;
+#else
+			unsigned char ENB : 8;
+#endif
+	} BIT;
+		} BCNT3AER;
+	};
+	char           wk13[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char AIE : 1;
+			unsigned char CIE : 1;
+			unsigned char PIE : 1;
+			unsigned char RTCOS : 1;
+			unsigned char PES : 4;
+#else
+			unsigned char PES : 4;
+			unsigned char RTCOS : 1;
+			unsigned char PIE : 1;
+			unsigned char CIE : 1;
+			unsigned char AIE : 1;
+#endif
+	} BIT;
+	} RCR1;
+	char           wk14[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char START : 1;
+			unsigned char RESET : 1;
+			unsigned char ADJ30 : 1;
+			unsigned char RTCOE : 1;
+			unsigned char AADJE : 1;
+			unsigned char AADJP : 1;
+			unsigned char HR24 : 1;
+			unsigned char CNTMD : 1;
+#else
+			unsigned char CNTMD : 1;
+			unsigned char HR24 : 1;
+			unsigned char AADJP : 1;
+			unsigned char AADJE : 1;
+			unsigned char RTCOE : 1;
+			unsigned char ADJ30 : 1;
+			unsigned char RESET : 1;
+			unsigned char START : 1;
+#endif
+	} BIT;
+	} RCR2;
+	char           wk15[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RTCEN : 1;
+			unsigned char RTCDV : 3;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char RTCDV : 3;
+			unsigned char RTCEN : 1;
+#endif
+	} BIT;
+	} RCR3;
+	char           wk16[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RCKSEL : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char RCKSEL : 1;
+#endif
+	} BIT;
+	} RCR4;
+	char           wk17[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RFC : 1;
+			unsigned short  : 15;
+#else
+			unsigned short  : 15;
+			unsigned short RFC : 1;
+#endif
+	} BIT;
+	} RFRH;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RFC : 16;
+#else
+			unsigned short RFC : 16;
+#endif
+	} BIT;
+	} RFRL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ADJ : 6;
+			unsigned char PMADJ : 2;
+#else
+			unsigned char PMADJ : 2;
+			unsigned char ADJ : 6;
+#endif
+	} BIT;
+	} RADJ;
+	char           wk18[17];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TCCT : 2;
+			unsigned char TCST : 1;
+			unsigned char  : 1;
+			unsigned char TCNF : 2;
+			unsigned char  : 1;
+			unsigned char TCEN : 1;
+#else
+			unsigned char TCEN : 1;
+			unsigned char  : 1;
+			unsigned char TCNF : 2;
+			unsigned char  : 1;
+			unsigned char TCST : 1;
+			unsigned char TCCT : 2;
+#endif
+	} BIT;
+	} RTCCR0;
+	char           wk19[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TCCT : 2;
+			unsigned char TCST : 1;
+			unsigned char  : 1;
+			unsigned char TCNF : 2;
+			unsigned char  : 1;
+			unsigned char TCEN : 1;
+#else
+			unsigned char TCEN : 1;
+			unsigned char  : 1;
+			unsigned char TCNF : 2;
+			unsigned char  : 1;
+			unsigned char TCST : 1;
+			unsigned char TCCT : 2;
+#endif
+	} BIT;
+	} RTCCR1;
+	char           wk20[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TCCT : 2;
+			unsigned char TCST : 1;
+			unsigned char  : 1;
+			unsigned char TCNF : 2;
+			unsigned char  : 1;
+			unsigned char TCEN : 1;
+#else
+			unsigned char TCEN : 1;
+			unsigned char  : 1;
+			unsigned char TCNF : 2;
+			unsigned char  : 1;
+			unsigned char TCST : 1;
+			unsigned char TCCT : 2;
+#endif
+	} BIT;
+	} RTCCR2;
+	char           wk21[13];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SEC1 : 4;
+			unsigned char SEC10 : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char SEC10 : 3;
+			unsigned char SEC1 : 4;
+#endif
+	} BIT;
+		} RSECCP0;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP0 : 8;
+#else
+			unsigned char BCNTCP0 : 8;
+#endif
+	} BIT;
+		} BCNT0CP0;
+	};
+	char           wk22[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MIN1 : 4;
+			unsigned char MIN10 : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char MIN10 : 3;
+			unsigned char MIN1 : 4;
+#endif
+	} BIT;
+		} RMINCP0;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP0 : 8;
+#else
+			unsigned char BCNTCP0 : 8;
+#endif
+	} BIT;
+		} BCNT1CP0;
+	};
+	char           wk23[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char HR1 : 4;
+			unsigned char HR10 : 2;
+			unsigned char PM : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PM : 1;
+			unsigned char HR10 : 2;
+			unsigned char HR1 : 4;
+#endif
+	} BIT;
+		} RHRCP0;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP0 : 8;
+#else
+			unsigned char BCNTCP0 : 8;
+#endif
+	} BIT;
+		} BCNT2CP0;
+	};
+	char           wk24[3];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DATE1 : 4;
+			unsigned char DATE10 : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char DATE10 : 2;
+			unsigned char DATE1 : 4;
+#endif
+	} BIT;
+		} RDAYCP0;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP0 : 8;
+#else
+			unsigned char BCNTCP0 : 8;
+#endif
+	} BIT;
+		} BCNT3CP0;
+	};
+	char           wk25[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MON1 : 4;
+			unsigned char MON10 : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char MON10 : 1;
+			unsigned char MON1 : 4;
+#endif
+	} BIT;
+	} RMONCP0;
+	char           wk26[5];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SEC1 : 4;
+			unsigned char SEC10 : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char SEC10 : 3;
+			unsigned char SEC1 : 4;
+#endif
+	} BIT;
+		} RSECCP1;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP1 : 8;
+#else
+			unsigned char BCNTCP1 : 8;
+#endif
+	} BIT;
+		} BCNT0CP1;
+	};
+	char           wk27[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MIN1 : 4;
+			unsigned char MIN10 : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char MIN10 : 3;
+			unsigned char MIN1 : 4;
+#endif
+	} BIT;
+		} RMINCP1;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP1 : 8;
+#else
+			unsigned char BCNTCP1 : 8;
+#endif
+	} BIT;
+		} BCNT1CP1;
+	};
+	char           wk28[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char HR1 : 4;
+			unsigned char HR10 : 2;
+			unsigned char PM : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PM : 1;
+			unsigned char HR10 : 2;
+			unsigned char HR1 : 4;
+#endif
+	} BIT;
+		} RHRCP1;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP1 : 8;
+#else
+			unsigned char BCNTCP1 : 8;
+#endif
+	} BIT;
+		} BCNT2CP1;
+	};
+	char           wk29[3];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DATE1 : 4;
+			unsigned char DATE10 : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char DATE10 : 2;
+			unsigned char DATE1 : 4;
+#endif
+	} BIT;
+		} RDAYCP1;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP1 : 8;
+#else
+			unsigned char BCNTCP1 : 8;
+#endif
+	} BIT;
+		} BCNT3CP1;
+	};
+	char           wk30[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MON1 : 4;
+			unsigned char MON10 : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char MON10 : 1;
+			unsigned char MON1 : 4;
+#endif
+	} BIT;
+	} RMONCP1;
+	char           wk31[5];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SEC1 : 4;
+			unsigned char SEC10 : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char SEC10 : 3;
+			unsigned char SEC1 : 4;
+#endif
+	} BIT;
+		} RSECCP2;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP2 : 8;
+#else
+			unsigned char BCNTCP2 : 8;
+#endif
+	} BIT;
+		} BCNT0CP2;
+	};
+	char           wk32[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MIN1 : 4;
+			unsigned char MIN10 : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char MIN10 : 3;
+			unsigned char MIN1 : 4;
+#endif
+	} BIT;
+		} RMINCP2;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP2 : 8;
+#else
+			unsigned char BCNTCP2 : 8;
+#endif
+	} BIT;
+		} BCNT1CP2;
+	};
+	char           wk33[1];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char HR1 : 4;
+			unsigned char HR10 : 2;
+			unsigned char PM : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char PM : 1;
+			unsigned char HR10 : 2;
+			unsigned char HR1 : 4;
+#endif
+	} BIT;
+		} RHRCP2;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP2 : 8;
+#else
+			unsigned char BCNTCP2 : 8;
+#endif
+	} BIT;
+		} BCNT2CP2;
+	};
+	char           wk34[3];
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DATE1 : 4;
+			unsigned char DATE10 : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char DATE10 : 2;
+			unsigned char DATE1 : 4;
+#endif
+	} BIT;
+		} RDAYCP2;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCNTCP2 : 8;
+#else
+			unsigned char BCNTCP2 : 8;
+#endif
+	} BIT;
+		} BCNT3CP2;
+	};
+	char           wk35[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MON1 : 4;
+			unsigned char MON10 : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char MON10 : 1;
+			unsigned char MON1 : 4;
+#endif
+	} BIT;
+	} RMONCP2;
+} st_rtc_t;
+
+typedef struct st_s12ad {
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DBLANS : 5;
+			unsigned short  : 1;
+			unsigned short GBADIE : 1;
+			unsigned short DBLE : 1;
+			unsigned short EXTRG : 1;
+			unsigned short TRGE : 1;
+			unsigned short  : 2;
+			unsigned short ADIE : 1;
+			unsigned short ADCS : 2;
+			unsigned short ADST : 1;
+#else
+			unsigned short ADST : 1;
+			unsigned short ADCS : 2;
+			unsigned short ADIE : 1;
+			unsigned short  : 2;
+			unsigned short TRGE : 1;
+			unsigned short EXTRG : 1;
+			unsigned short DBLE : 1;
+			unsigned short GBADIE : 1;
+			unsigned short  : 1;
+			unsigned short DBLANS : 5;
+#endif
+	} BIT;
+	} ADCSR;
+	char           wk0[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ANSA000 : 1;
+			unsigned short ANSA001 : 1;
+			unsigned short ANSA002 : 1;
+			unsigned short ANSA003 : 1;
+			unsigned short ANSA004 : 1;
+			unsigned short ANSA005 : 1;
+			unsigned short ANSA006 : 1;
+			unsigned short ANSA007 : 1;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short ANSA007 : 1;
+			unsigned short ANSA006 : 1;
+			unsigned short ANSA005 : 1;
+			unsigned short ANSA004 : 1;
+			unsigned short ANSA003 : 1;
+			unsigned short ANSA002 : 1;
+			unsigned short ANSA001 : 1;
+			unsigned short ANSA000 : 1;
+#endif
+	} BIT;
+	} ADANSA0;
+	char           wk1[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ADS000 : 1;
+			unsigned short ADS001 : 1;
+			unsigned short ADS002 : 1;
+			unsigned short ADS003 : 1;
+			unsigned short ADS004 : 1;
+			unsigned short ADS005 : 1;
+			unsigned short ADS006 : 1;
+			unsigned short ADS007 : 1;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short ADS007 : 1;
+			unsigned short ADS006 : 1;
+			unsigned short ADS005 : 1;
+			unsigned short ADS004 : 1;
+			unsigned short ADS003 : 1;
+			unsigned short ADS002 : 1;
+			unsigned short ADS001 : 1;
+			unsigned short ADS000 : 1;
+#endif
+	} BIT;
+	} ADADS0;
+	char           wk2[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ADC : 3;
+			unsigned char  : 4;
+			unsigned char AVEE : 1;
+#else
+			unsigned char AVEE : 1;
+			unsigned char  : 4;
+			unsigned char ADC : 3;
+#endif
+	} BIT;
+	} ADADC;
+	char           wk3[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 1;
+			unsigned short ADPRC : 2;
+			unsigned short  : 2;
+			unsigned short ACE : 1;
+			unsigned short  : 2;
+			unsigned short DIAGVAL : 2;
+			unsigned short DIAGLD : 1;
+			unsigned short DIAGM : 1;
+			unsigned short  : 3;
+			unsigned short ADRFMT : 1;
+#else
+			unsigned short ADRFMT : 1;
+			unsigned short  : 3;
+			unsigned short DIAGM : 1;
+			unsigned short DIAGLD : 1;
+			unsigned short DIAGVAL : 2;
+			unsigned short  : 2;
+			unsigned short ACE : 1;
+			unsigned short  : 2;
+			unsigned short ADPRC : 2;
+			unsigned short  : 1;
+#endif
+	} BIT;
+	} ADCER;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short TRSB : 6;
+			unsigned short  : 2;
+			unsigned short TRSA : 6;
+			unsigned short  : 2;
+#else
+			unsigned short  : 2;
+			unsigned short TRSA : 6;
+			unsigned short  : 2;
+			unsigned short TRSB : 6;
+#endif
+	} BIT;
+	} ADSTRGR;
+	char           wk4[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ANSB000 : 1;
+			unsigned short ANSB001 : 1;
+			unsigned short ANSB002 : 1;
+			unsigned short ANSB003 : 1;
+			unsigned short ANSB004 : 1;
+			unsigned short ANSB005 : 1;
+			unsigned short ANSB006 : 1;
+			unsigned short ANSB007 : 1;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short ANSB007 : 1;
+			unsigned short ANSB006 : 1;
+			unsigned short ANSB005 : 1;
+			unsigned short ANSB004 : 1;
+			unsigned short ANSB003 : 1;
+			unsigned short ANSB002 : 1;
+			unsigned short ANSB001 : 1;
+			unsigned short ANSB000 : 1;
+#endif
+	} BIT;
+	} ADANSB0;
+	char           wk5[2];
+	union {
+		unsigned short WORD;
+	} ADDBLDR;
+	char           wk6[4];
+	union {
+		unsigned short WORD;
+		union {
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short AD : 12;
+			unsigned short  : 2;
+			unsigned short DIAGST : 2;
+#else
+			unsigned short DIAGST : 2;
+			unsigned short  : 2;
+			unsigned short AD : 12;
+#endif
+	} RIGHT;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DIAGST : 2;
+			unsigned short  : 2;
+			unsigned short AD : 12;
+#else
+			unsigned short AD : 12;
+			unsigned short  : 2;
+			unsigned short DIAGST : 2;
+#endif
+	} LEFT;
+		} BIT;
+	} ADRD;
+	unsigned short ADDR0;
+	unsigned short ADDR1;
+	unsigned short ADDR2;
+	unsigned short ADDR3;
+	unsigned short ADDR4;
+	unsigned short ADDR5;
+	unsigned short ADDR6;
+	unsigned short ADDR7;
+	char           wk7[51];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PRO : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char PRO : 2;
+#endif
+	} BIT;
+	} ADSAMPR;
+	char           wk8[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short SSTSH : 8;
+			unsigned short SHANS : 3;
+			unsigned short  : 5;
+#else
+			unsigned short  : 5;
+			unsigned short SHANS : 3;
+			unsigned short SSTSH : 8;
+#endif
+	} BIT;
+	} ADSHCR;
+	char           wk9[6];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 5;
+			unsigned short SAM : 1;
+			unsigned short  : 10;
+#else
+			unsigned short  : 10;
+			unsigned short SAM : 1;
+			unsigned short  : 5;
+#endif
+	} BIT;
+	} ADSAM;
+	char           wk10[10];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ADNDIS : 5;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char ADNDIS : 5;
+#endif
+	} BIT;
+	} ADDISCR;
+	char           wk11[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SHMD : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char SHMD : 1;
+#endif
+	} BIT;
+	} ADSHMSR;
+	char           wk12[3];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PGS : 1;
+			unsigned short GBRSCN : 1;
+			unsigned short  : 12;
+			unsigned short LGRRS : 1;
+			unsigned short GBRP : 1;
+#else
+			unsigned short GBRP : 1;
+			unsigned short LGRRS : 1;
+			unsigned short  : 12;
+			unsigned short GBRSCN : 1;
+			unsigned short PGS : 1;
+#endif
+	} BIT;
+	} ADGSPCR;
+	char           wk13[2];
+	unsigned short ADDBLDRA;
+	unsigned short ADDBLDRB;
+	char           wk14[4];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MONCOMB : 1;
+			unsigned char  : 3;
+			unsigned char MONCMPA : 1;
+			unsigned char MONCMPB : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char MONCMPB : 1;
+			unsigned char MONCMPA : 1;
+			unsigned char  : 3;
+			unsigned char MONCOMB : 1;
+#endif
+	} BIT;
+	} ADWINMON;
+	char           wk15[3];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPAB : 2;
+			unsigned short  : 7;
+			unsigned short CMPBE : 1;
+			unsigned short  : 1;
+			unsigned short CMPAE : 1;
+			unsigned short  : 1;
+			unsigned short CMPBIE : 1;
+			unsigned short WCMPE : 1;
+			unsigned short CMPAIE : 1;
+#else
+			unsigned short CMPAIE : 1;
+			unsigned short WCMPE : 1;
+			unsigned short CMPBIE : 1;
+			unsigned short  : 1;
+			unsigned short CMPAE : 1;
+			unsigned short  : 1;
+			unsigned short CMPBE : 1;
+			unsigned short  : 7;
+			unsigned short CMPAB : 2;
+#endif
+	} BIT;
+	} ADCMPCR;
+	char           wk16[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPCHA000 : 1;
+			unsigned short CMPCHA001 : 1;
+			unsigned short CMPCHA002 : 1;
+			unsigned short CMPCHA003 : 1;
+			unsigned short CMPCHA004 : 1;
+			unsigned short CMPCHA005 : 1;
+			unsigned short CMPCHA006 : 1;
+			unsigned short CMPCHA007 : 1;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short CMPCHA007 : 1;
+			unsigned short CMPCHA006 : 1;
+			unsigned short CMPCHA005 : 1;
+			unsigned short CMPCHA004 : 1;
+			unsigned short CMPCHA003 : 1;
+			unsigned short CMPCHA002 : 1;
+			unsigned short CMPCHA001 : 1;
+			unsigned short CMPCHA000 : 1;
+#endif
+	} BIT;
+	} ADCMPANSR0;
+	char           wk17[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPLCHA000 : 1;
+			unsigned short CMPLCHA001 : 1;
+			unsigned short CMPLCHA002 : 1;
+			unsigned short CMPLCHA003 : 1;
+			unsigned short CMPLCHA004 : 1;
+			unsigned short CMPLCHA005 : 1;
+			unsigned short CMPLCHA006 : 1;
+			unsigned short CMPLCHA007 : 1;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short CMPLCHA007 : 1;
+			unsigned short CMPLCHA006 : 1;
+			unsigned short CMPLCHA005 : 1;
+			unsigned short CMPLCHA004 : 1;
+			unsigned short CMPLCHA003 : 1;
+			unsigned short CMPLCHA002 : 1;
+			unsigned short CMPLCHA001 : 1;
+			unsigned short CMPLCHA000 : 1;
+#endif
+	} BIT;
+	} ADCMPLR0;
+	char           wk18[2];
+	unsigned short ADCMPDR0;
+	unsigned short ADCMPDR1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPSTCHA000 : 1;
+			unsigned short CMPSTCHA001 : 1;
+			unsigned short CMPSTCHA002 : 1;
+			unsigned short CMPSTCHA003 : 1;
+			unsigned short CMPSTCHA004 : 1;
+			unsigned short CMPSTCHA005 : 1;
+			unsigned short CMPSTCHA006 : 1;
+			unsigned short CMPSTCHA007 : 1;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short CMPSTCHA007 : 1;
+			unsigned short CMPSTCHA006 : 1;
+			unsigned short CMPSTCHA005 : 1;
+			unsigned short CMPSTCHA004 : 1;
+			unsigned short CMPSTCHA003 : 1;
+			unsigned short CMPSTCHA002 : 1;
+			unsigned short CMPSTCHA001 : 1;
+			unsigned short CMPSTCHA000 : 1;
+#endif
+	} BIT;
+	} ADCMPSR0;
+	char           wk19[4];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMPCHB : 6;
+			unsigned char  : 1;
+			unsigned char CMPLB : 1;
+#else
+			unsigned char CMPLB : 1;
+			unsigned char  : 1;
+			unsigned char CMPCHB : 6;
+#endif
+	} BIT;
+	} ADCMPBNSR;
+	char           wk20[1];
+	unsigned short ADWINLLB;
+	unsigned short ADWINULB;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMPSTB : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char CMPSTB : 1;
+#endif
+	} BIT;
+	} ADCMPBSR;
+	char           wk21[39];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ANSC000 : 1;
+			unsigned short ANSC001 : 1;
+			unsigned short ANSC002 : 1;
+			unsigned short ANSC003 : 1;
+			unsigned short ANSC004 : 1;
+			unsigned short ANSC005 : 1;
+			unsigned short ANSC006 : 1;
+			unsigned short ANSC007 : 1;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short ANSC007 : 1;
+			unsigned short ANSC006 : 1;
+			unsigned short ANSC005 : 1;
+			unsigned short ANSC004 : 1;
+			unsigned short ANSC003 : 1;
+			unsigned short ANSC002 : 1;
+			unsigned short ANSC001 : 1;
+			unsigned short ANSC000 : 1;
+#endif
+	} BIT;
+	} ADANSC0;
+	char           wk22[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TRSC : 6;
+			unsigned char GCADIE : 1;
+			unsigned char GRCE : 1;
+#else
+			unsigned char GRCE : 1;
+			unsigned char GCADIE : 1;
+			unsigned char TRSC : 6;
+#endif
+	} BIT;
+	} ADGCTRGR;
+	char           wk23[6];
+	unsigned char  ADSSTR0;
+	unsigned char  ADSSTR1;
+	unsigned char  ADSSTR2;
+	unsigned char  ADSSTR3;
+	unsigned char  ADSSTR4;
+	unsigned char  ADSSTR5;
+	unsigned char  ADSSTR6;
+	unsigned char  ADSSTR7;
+} st_s12ad_t;
+
+typedef struct st_s12ad1 {
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DBLANS : 5;
+			unsigned short  : 1;
+			unsigned short GBADIE : 1;
+			unsigned short DBLE : 1;
+			unsigned short EXTRG : 1;
+			unsigned short TRGE : 1;
+			unsigned short  : 2;
+			unsigned short ADIE : 1;
+			unsigned short ADCS : 2;
+			unsigned short ADST : 1;
+#else
+			unsigned short ADST : 1;
+			unsigned short ADCS : 2;
+			unsigned short ADIE : 1;
+			unsigned short  : 2;
+			unsigned short TRGE : 1;
+			unsigned short EXTRG : 1;
+			unsigned short DBLE : 1;
+			unsigned short GBADIE : 1;
+			unsigned short  : 1;
+			unsigned short DBLANS : 5;
+#endif
+	} BIT;
+	} ADCSR;
+	char           wk0[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ANSA000 : 1;
+			unsigned short ANSA001 : 1;
+			unsigned short ANSA002 : 1;
+			unsigned short ANSA003 : 1;
+			unsigned short ANSA004 : 1;
+			unsigned short ANSA005 : 1;
+			unsigned short ANSA006 : 1;
+			unsigned short ANSA007 : 1;
+			unsigned short ANSA008 : 1;
+			unsigned short ANSA009 : 1;
+			unsigned short ANSA010 : 1;
+			unsigned short ANSA011 : 1;
+			unsigned short ANSA012 : 1;
+			unsigned short ANSA013 : 1;
+			unsigned short ANSA014 : 1;
+			unsigned short ANSA015 : 1;
+#else
+			unsigned short ANSA015 : 1;
+			unsigned short ANSA014 : 1;
+			unsigned short ANSA013 : 1;
+			unsigned short ANSA012 : 1;
+			unsigned short ANSA011 : 1;
+			unsigned short ANSA010 : 1;
+			unsigned short ANSA009 : 1;
+			unsigned short ANSA008 : 1;
+			unsigned short ANSA007 : 1;
+			unsigned short ANSA006 : 1;
+			unsigned short ANSA005 : 1;
+			unsigned short ANSA004 : 1;
+			unsigned short ANSA003 : 1;
+			unsigned short ANSA002 : 1;
+			unsigned short ANSA001 : 1;
+			unsigned short ANSA000 : 1;
+#endif
+	} BIT;
+	} ADANSA0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ANSA100 : 1;
+			unsigned short ANSA101 : 1;
+			unsigned short ANSA102 : 1;
+			unsigned short ANSA103 : 1;
+			unsigned short ANSA104 : 1;
+			unsigned short  : 11;
+#else
+			unsigned short  : 11;
+			unsigned short ANSA104 : 1;
+			unsigned short ANSA103 : 1;
+			unsigned short ANSA102 : 1;
+			unsigned short ANSA101 : 1;
+			unsigned short ANSA100 : 1;
+#endif
+	} BIT;
+	} ADANSA1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ADS000 : 1;
+			unsigned short ADS001 : 1;
+			unsigned short ADS002 : 1;
+			unsigned short ADS003 : 1;
+			unsigned short ADS004 : 1;
+			unsigned short ADS005 : 1;
+			unsigned short ADS006 : 1;
+			unsigned short ADS007 : 1;
+			unsigned short ADS008 : 1;
+			unsigned short ADS009 : 1;
+			unsigned short ADS010 : 1;
+			unsigned short ADS011 : 1;
+			unsigned short ADS012 : 1;
+			unsigned short ADS013 : 1;
+			unsigned short ADS014 : 1;
+			unsigned short ADS015 : 1;
+#else
+			unsigned short ADS015 : 1;
+			unsigned short ADS014 : 1;
+			unsigned short ADS013 : 1;
+			unsigned short ADS012 : 1;
+			unsigned short ADS011 : 1;
+			unsigned short ADS010 : 1;
+			unsigned short ADS009 : 1;
+			unsigned short ADS008 : 1;
+			unsigned short ADS007 : 1;
+			unsigned short ADS006 : 1;
+			unsigned short ADS005 : 1;
+			unsigned short ADS004 : 1;
+			unsigned short ADS003 : 1;
+			unsigned short ADS002 : 1;
+			unsigned short ADS001 : 1;
+			unsigned short ADS000 : 1;
+#endif
+	} BIT;
+	} ADADS0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ADS100 : 1;
+			unsigned short ADS101 : 1;
+			unsigned short ADS102 : 1;
+			unsigned short ADS103 : 1;
+			unsigned short ADS104 : 1;
+			unsigned short  : 11;
+#else
+			unsigned short  : 11;
+			unsigned short ADS104 : 1;
+			unsigned short ADS103 : 1;
+			unsigned short ADS102 : 1;
+			unsigned short ADS101 : 1;
+			unsigned short ADS100 : 1;
+#endif
+	} BIT;
+	} ADADS1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ADC : 3;
+			unsigned char  : 4;
+			unsigned char AVEE : 1;
+#else
+			unsigned char AVEE : 1;
+			unsigned char  : 4;
+			unsigned char ADC : 3;
+#endif
+	} BIT;
+	} ADADC;
+	char           wk1[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 1;
+			unsigned short ADPRC : 2;
+			unsigned short  : 2;
+			unsigned short ACE : 1;
+			unsigned short  : 2;
+			unsigned short DIAGVAL : 2;
+			unsigned short DIAGLD : 1;
+			unsigned short DIAGM : 1;
+			unsigned short  : 3;
+			unsigned short ADRFMT : 1;
+#else
+			unsigned short ADRFMT : 1;
+			unsigned short  : 3;
+			unsigned short DIAGM : 1;
+			unsigned short DIAGLD : 1;
+			unsigned short DIAGVAL : 2;
+			unsigned short  : 2;
+			unsigned short ACE : 1;
+			unsigned short  : 2;
+			unsigned short ADPRC : 2;
+			unsigned short  : 1;
+#endif
+	} BIT;
+	} ADCER;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short TRSB : 6;
+			unsigned short  : 2;
+			unsigned short TRSA : 6;
+			unsigned short  : 2;
+#else
+			unsigned short  : 2;
+			unsigned short TRSA : 6;
+			unsigned short  : 2;
+			unsigned short TRSB : 6;
+#endif
+	} BIT;
+	} ADSTRGR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short TSSAD : 1;
+			unsigned short OCSAD : 1;
+			unsigned short  : 6;
+			unsigned short TSSA : 1;
+			unsigned short OCSA : 1;
+			unsigned short TSSB : 1;
+			unsigned short OCSB : 1;
+			unsigned short  : 1;
+			unsigned short EXSEL : 2;
+			unsigned short EXOEN : 1;
+#else
+			unsigned short EXOEN : 1;
+			unsigned short EXSEL : 2;
+			unsigned short  : 1;
+			unsigned short OCSB : 1;
+			unsigned short TSSB : 1;
+			unsigned short OCSA : 1;
+			unsigned short TSSA : 1;
+			unsigned short  : 6;
+			unsigned short OCSAD : 1;
+			unsigned short TSSAD : 1;
+#endif
+	} BIT;
+	} ADEXICR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ANSB000 : 1;
+			unsigned short ANSB001 : 1;
+			unsigned short ANSB002 : 1;
+			unsigned short ANSB003 : 1;
+			unsigned short ANSB004 : 1;
+			unsigned short ANSB005 : 1;
+			unsigned short ANSB006 : 1;
+			unsigned short ANSB007 : 1;
+			unsigned short ANSB008 : 1;
+			unsigned short ANSB009 : 1;
+			unsigned short ANSB010 : 1;
+			unsigned short ANSB011 : 1;
+			unsigned short ANSB012 : 1;
+			unsigned short ANSB013 : 1;
+			unsigned short ANSB014 : 1;
+			unsigned short ANSB015 : 1;
+#else
+			unsigned short ANSB015 : 1;
+			unsigned short ANSB014 : 1;
+			unsigned short ANSB013 : 1;
+			unsigned short ANSB012 : 1;
+			unsigned short ANSB011 : 1;
+			unsigned short ANSB010 : 1;
+			unsigned short ANSB009 : 1;
+			unsigned short ANSB008 : 1;
+			unsigned short ANSB007 : 1;
+			unsigned short ANSB006 : 1;
+			unsigned short ANSB005 : 1;
+			unsigned short ANSB004 : 1;
+			unsigned short ANSB003 : 1;
+			unsigned short ANSB002 : 1;
+			unsigned short ANSB001 : 1;
+			unsigned short ANSB000 : 1;
+#endif
+	} BIT;
+	} ADANSB0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ANSB100 : 1;
+			unsigned short ANSB101 : 1;
+			unsigned short ANSB102 : 1;
+			unsigned short ANSB103 : 1;
+			unsigned short ANSB104 : 1;
+			unsigned short  : 11;
+#else
+			unsigned short  : 11;
+			unsigned short ANSB104 : 1;
+			unsigned short ANSB103 : 1;
+			unsigned short ANSB102 : 1;
+			unsigned short ANSB101 : 1;
+			unsigned short ANSB100 : 1;
+#endif
+	} BIT;
+	} ADANSB1;
+	unsigned short ADDBLDR;
+	unsigned short ADTSDR;
+	unsigned short ADOCDR;
+	union {
+		unsigned short WORD;
+		union {
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short AD : 12;
+			unsigned short  : 2;
+			unsigned short DIAGST : 2;
+#else
+			unsigned short DIAGST : 2;
+			unsigned short  : 2;
+			unsigned short AD : 12;
+#endif
+	} RIGHT;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DIAGST : 2;
+			unsigned short  : 2;
+			unsigned short AD : 12;
+#else
+			unsigned short AD : 12;
+			unsigned short  : 2;
+			unsigned short DIAGST : 2;
+#endif
+	} LEFT;
+		} BIT;
+	} ADRD;
+	unsigned short ADDR0;
+	unsigned short ADDR1;
+	unsigned short ADDR2;
+	unsigned short ADDR3;
+	unsigned short ADDR4;
+	unsigned short ADDR5;
+	unsigned short ADDR6;
+	unsigned short ADDR7;
+	unsigned short ADDR8;
+	unsigned short ADDR9;
+	unsigned short ADDR10;
+	unsigned short ADDR11;
+	unsigned short ADDR12;
+	unsigned short ADDR13;
+	unsigned short ADDR14;
+	unsigned short ADDR15;
+	unsigned short ADDR16;
+	unsigned short ADDR17;
+	unsigned short ADDR18;
+	unsigned short ADDR19;
+	unsigned short ADDR20;
+	char           wk2[25];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PRO : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char PRO : 2;
+#endif
+	} BIT;
+	} ADSAMPR;
+	char           wk3[10];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 5;
+			unsigned short SAM : 1;
+			unsigned short  : 10;
+#else
+			unsigned short  : 10;
+			unsigned short SAM : 1;
+			unsigned short  : 5;
+#endif
+	} BIT;
+	} ADSAM;
+	char           wk4[10];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ADNDIS : 5;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char ADNDIS : 5;
+#endif
+	} BIT;
+	} ADDISCR;
+	char           wk5[5];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PGS : 1;
+			unsigned short GBRSCN : 1;
+			unsigned short  : 12;
+			unsigned short LGRRS : 1;
+			unsigned short GBRP : 1;
+#else
+			unsigned short GBRP : 1;
+			unsigned short LGRRS : 1;
+			unsigned short  : 12;
+			unsigned short GBRSCN : 1;
+			unsigned short PGS : 1;
+#endif
+	} BIT;
+	} ADGSPCR;
+	char           wk6[2];
+	unsigned short ADDBLDRA;
+	unsigned short ADDBLDRB;
+	char           wk7[4];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MONCOMB : 1;
+			unsigned char  : 3;
+			unsigned char MONCMPA : 1;
+			unsigned char MONCMPB : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char MONCMPB : 1;
+			unsigned char MONCMPA : 1;
+			unsigned char  : 3;
+			unsigned char MONCOMB : 1;
+#endif
+	} BIT;
+	} ADWINMON;
+	char           wk8[3];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPAB : 2;
+			unsigned short  : 7;
+			unsigned short CMPBE : 1;
+			unsigned short  : 1;
+			unsigned short CMPAE : 1;
+			unsigned short  : 1;
+			unsigned short CMPBIE : 1;
+			unsigned short WCMPE : 1;
+			unsigned short CMPAIE : 1;
+#else
+			unsigned short CMPAIE : 1;
+			unsigned short WCMPE : 1;
+			unsigned short CMPBIE : 1;
+			unsigned short  : 1;
+			unsigned short CMPAE : 1;
+			unsigned short  : 1;
+			unsigned short CMPBE : 1;
+			unsigned short  : 7;
+			unsigned short CMPAB : 2;
+#endif
+	} BIT;
+	} ADCMPCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMPSTS : 1;
+			unsigned char CMPSOC : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char CMPSOC : 1;
+			unsigned char CMPSTS : 1;
+#endif
+	} BIT;
+	} ADCMPANSER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMPLTS : 1;
+			unsigned char CMPLOC : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char CMPLOC : 1;
+			unsigned char CMPLTS : 1;
+#endif
+	} BIT;
+	} ADCMPLER;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPCHA000 : 1;
+			unsigned short CMPCHA001 : 1;
+			unsigned short CMPCHA002 : 1;
+			unsigned short CMPCHA003 : 1;
+			unsigned short CMPCHA004 : 1;
+			unsigned short CMPCHA005 : 1;
+			unsigned short CMPCHA006 : 1;
+			unsigned short CMPCHA007 : 1;
+			unsigned short CMPCHA008 : 1;
+			unsigned short CMPCHA009 : 1;
+			unsigned short CMPCHA010 : 1;
+			unsigned short CMPCHA011 : 1;
+			unsigned short CMPCHA012 : 1;
+			unsigned short CMPCHA013 : 1;
+			unsigned short CMPCHA014 : 1;
+			unsigned short CMPCHA015 : 1;
+#else
+			unsigned short CMPCHA015 : 1;
+			unsigned short CMPCHA014 : 1;
+			unsigned short CMPCHA013 : 1;
+			unsigned short CMPCHA012 : 1;
+			unsigned short CMPCHA011 : 1;
+			unsigned short CMPCHA010 : 1;
+			unsigned short CMPCHA009 : 1;
+			unsigned short CMPCHA008 : 1;
+			unsigned short CMPCHA007 : 1;
+			unsigned short CMPCHA006 : 1;
+			unsigned short CMPCHA005 : 1;
+			unsigned short CMPCHA004 : 1;
+			unsigned short CMPCHA003 : 1;
+			unsigned short CMPCHA002 : 1;
+			unsigned short CMPCHA001 : 1;
+			unsigned short CMPCHA000 : 1;
+#endif
+	} BIT;
+	} ADCMPANSR0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPCHA100 : 1;
+			unsigned short CMPCHA101 : 1;
+			unsigned short CMPCHA102 : 1;
+			unsigned short CMPCHA103 : 1;
+			unsigned short CMPCHA104 : 1;
+			unsigned short  : 11;
+#else
+			unsigned short  : 11;
+			unsigned short CMPCHA104 : 1;
+			unsigned short CMPCHA103 : 1;
+			unsigned short CMPCHA102 : 1;
+			unsigned short CMPCHA101 : 1;
+			unsigned short CMPCHA100 : 1;
+#endif
+	} BIT;
+	} ADCMPANSR1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPLCHA000 : 1;
+			unsigned short CMPLCHA001 : 1;
+			unsigned short CMPLCHA002 : 1;
+			unsigned short CMPLCHA003 : 1;
+			unsigned short CMPLCHA004 : 1;
+			unsigned short CMPLCHA005 : 1;
+			unsigned short CMPLCHA006 : 1;
+			unsigned short CMPLCHA007 : 1;
+			unsigned short CMPLCHA008 : 1;
+			unsigned short CMPLCHA009 : 1;
+			unsigned short CMPLCHA010 : 1;
+			unsigned short CMPLCHA011 : 1;
+			unsigned short CMPLCHA012 : 1;
+			unsigned short CMPLCHA013 : 1;
+			unsigned short CMPLCHA014 : 1;
+			unsigned short CMPLCHA015 : 1;
+#else
+			unsigned short CMPLCHA015 : 1;
+			unsigned short CMPLCHA014 : 1;
+			unsigned short CMPLCHA013 : 1;
+			unsigned short CMPLCHA012 : 1;
+			unsigned short CMPLCHA011 : 1;
+			unsigned short CMPLCHA010 : 1;
+			unsigned short CMPLCHA009 : 1;
+			unsigned short CMPLCHA008 : 1;
+			unsigned short CMPLCHA007 : 1;
+			unsigned short CMPLCHA006 : 1;
+			unsigned short CMPLCHA005 : 1;
+			unsigned short CMPLCHA004 : 1;
+			unsigned short CMPLCHA003 : 1;
+			unsigned short CMPLCHA002 : 1;
+			unsigned short CMPLCHA001 : 1;
+			unsigned short CMPLCHA000 : 1;
+#endif
+	} BIT;
+	} ADCMPLR0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPLCHA100 : 1;
+			unsigned short CMPLCHA101 : 1;
+			unsigned short CMPLCHA102 : 1;
+			unsigned short CMPLCHA103 : 1;
+			unsigned short CMPLCHA104 : 1;
+			unsigned short  : 11;
+#else
+			unsigned short  : 11;
+			unsigned short CMPLCHA104 : 1;
+			unsigned short CMPLCHA103 : 1;
+			unsigned short CMPLCHA102 : 1;
+			unsigned short CMPLCHA101 : 1;
+			unsigned short CMPLCHA100 : 1;
+#endif
+	} BIT;
+	} ADCMPLR1;
+	unsigned short ADCMPDR0;
+	unsigned short ADCMPDR1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPSTCHA000 : 1;
+			unsigned short CMPSTCHA001 : 1;
+			unsigned short CMPSTCHA002 : 1;
+			unsigned short CMPSTCHA003 : 1;
+			unsigned short CMPSTCHA004 : 1;
+			unsigned short CMPSTCHA005 : 1;
+			unsigned short CMPSTCHA006 : 1;
+			unsigned short CMPSTCHA007 : 1;
+			unsigned short CMPSTCHA008 : 1;
+			unsigned short CMPSTCHA009 : 1;
+			unsigned short CMPSTCHA010 : 1;
+			unsigned short CMPSTCHA011 : 1;
+			unsigned short CMPSTCHA012 : 1;
+			unsigned short CMPSTCHA013 : 1;
+			unsigned short CMPSTCHA014 : 1;
+			unsigned short CMPSTCHA015 : 1;
+#else
+			unsigned short CMPSTCHA015 : 1;
+			unsigned short CMPSTCHA014 : 1;
+			unsigned short CMPSTCHA013 : 1;
+			unsigned short CMPSTCHA012 : 1;
+			unsigned short CMPSTCHA011 : 1;
+			unsigned short CMPSTCHA010 : 1;
+			unsigned short CMPSTCHA009 : 1;
+			unsigned short CMPSTCHA008 : 1;
+			unsigned short CMPSTCHA007 : 1;
+			unsigned short CMPSTCHA006 : 1;
+			unsigned short CMPSTCHA005 : 1;
+			unsigned short CMPSTCHA004 : 1;
+			unsigned short CMPSTCHA003 : 1;
+			unsigned short CMPSTCHA002 : 1;
+			unsigned short CMPSTCHA001 : 1;
+			unsigned short CMPSTCHA000 : 1;
+#endif
+	} BIT;
+	} ADCMPSR0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPSTCHA100 : 1;
+			unsigned short CMPSTCHA101 : 1;
+			unsigned short CMPSTCHA102 : 1;
+			unsigned short CMPSTCHA103 : 1;
+			unsigned short CMPSTCHA104 : 1;
+			unsigned short  : 11;
+#else
+			unsigned short  : 11;
+			unsigned short CMPSTCHA104 : 1;
+			unsigned short CMPSTCHA103 : 1;
+			unsigned short CMPSTCHA102 : 1;
+			unsigned short CMPSTCHA101 : 1;
+			unsigned short CMPSTCHA100 : 1;
+#endif
+	} BIT;
+	} ADCMPSR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMPFTS : 1;
+			unsigned char CMPFOC : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char CMPFOC : 1;
+			unsigned char CMPFTS : 1;
+#endif
+	} BIT;
+	} ADCMPSER;
+	char           wk9[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMPCHB : 6;
+			unsigned char  : 1;
+			unsigned char CMPLB : 1;
+#else
+			unsigned char CMPLB : 1;
+			unsigned char  : 1;
+			unsigned char CMPCHB : 6;
+#endif
+	} BIT;
+	} ADCMPBNSR;
+	char           wk10[1];
+	unsigned short ADWINLLB;
+	unsigned short ADWINULB;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMPSTB : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char CMPSTB : 1;
+#endif
+	} BIT;
+	} ADCMPBSR;
+	char           wk11[39];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ANSC000 : 1;
+			unsigned short ANSC001 : 1;
+			unsigned short ANSC002 : 1;
+			unsigned short ANSC003 : 1;
+			unsigned short ANSC004 : 1;
+			unsigned short ANSC005 : 1;
+			unsigned short ANSC006 : 1;
+			unsigned short ANSC007 : 1;
+			unsigned short ANSC008 : 1;
+			unsigned short ANSC009 : 1;
+			unsigned short ANSC010 : 1;
+			unsigned short ANSC011 : 1;
+			unsigned short ANSC012 : 1;
+			unsigned short ANSC013 : 1;
+			unsigned short ANSC014 : 1;
+			unsigned short ANSC015 : 1;
+#else
+			unsigned short ANSC015 : 1;
+			unsigned short ANSC014 : 1;
+			unsigned short ANSC013 : 1;
+			unsigned short ANSC012 : 1;
+			unsigned short ANSC011 : 1;
+			unsigned short ANSC010 : 1;
+			unsigned short ANSC009 : 1;
+			unsigned short ANSC008 : 1;
+			unsigned short ANSC007 : 1;
+			unsigned short ANSC006 : 1;
+			unsigned short ANSC005 : 1;
+			unsigned short ANSC004 : 1;
+			unsigned short ANSC003 : 1;
+			unsigned short ANSC002 : 1;
+			unsigned short ANSC001 : 1;
+			unsigned short ANSC000 : 1;
+#endif
+	} BIT;
+	} ADANSC0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ANSC100 : 1;
+			unsigned short ANSC101 : 1;
+			unsigned short ANSC102 : 1;
+			unsigned short ANSC103 : 1;
+			unsigned short ANSC104 : 1;
+			unsigned short  : 11;
+#else
+			unsigned short  : 11;
+			unsigned short ANSC104 : 1;
+			unsigned short ANSC103 : 1;
+			unsigned short ANSC102 : 1;
+			unsigned short ANSC101 : 1;
+			unsigned short ANSC100 : 1;
+#endif
+	} BIT;
+	} ADANSC1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TSSC : 1;
+			unsigned char OCSC : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char OCSC : 1;
+			unsigned char TSSC : 1;
+#endif
+	} BIT;
+	} ADGCEXCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TRSC : 6;
+			unsigned char GCADIE : 1;
+			unsigned char GRCE : 1;
+#else
+			unsigned char GRCE : 1;
+			unsigned char GCADIE : 1;
+			unsigned char TRSC : 6;
+#endif
+	} BIT;
+	} ADGCTRGR;
+	char           wk12[3];
+	unsigned char  ADSSTRL;
+	unsigned char  ADSSTRT;
+	unsigned char  ADSSTRO;
+	unsigned char  ADSSTR0;
+	unsigned char  ADSSTR1;
+	unsigned char  ADSSTR2;
+	unsigned char  ADSSTR3;
+	unsigned char  ADSSTR4;
+	unsigned char  ADSSTR5;
+	unsigned char  ADSSTR6;
+	unsigned char  ADSSTR7;
+	unsigned char  ADSSTR8;
+	unsigned char  ADSSTR9;
+	unsigned char  ADSSTR10;
+	unsigned char  ADSSTR11;
+	unsigned char  ADSSTR12;
+	unsigned char  ADSSTR13;
+	unsigned char  ADSSTR14;
+	unsigned char  ADSSTR15;
+} st_s12ad1_t;
+
+typedef struct st_sci0 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKS : 2;
+			unsigned char MP : 1;
+			unsigned char STOP : 1;
+			unsigned char PM : 1;
+			unsigned char PE : 1;
+			unsigned char CHR : 1;
+			unsigned char CM : 1;
+#else
+			unsigned char CM : 1;
+			unsigned char CHR : 1;
+			unsigned char PE : 1;
+			unsigned char PM : 1;
+			unsigned char STOP : 1;
+			unsigned char MP : 1;
+			unsigned char CKS : 2;
+#endif
+	} BIT;
+	} SMR;
+	unsigned char  BRR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKE : 2;
+			unsigned char TEIE : 1;
+			unsigned char MPIE : 1;
+			unsigned char RE : 1;
+			unsigned char TE : 1;
+			unsigned char RIE : 1;
+			unsigned char TIE : 1;
+#else
+			unsigned char TIE : 1;
+			unsigned char RIE : 1;
+			unsigned char TE : 1;
+			unsigned char RE : 1;
+			unsigned char MPIE : 1;
+			unsigned char TEIE : 1;
+			unsigned char CKE : 2;
+#endif
+	} BIT;
+	} SCR;
+	unsigned char  TDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MPBT : 1;
+			unsigned char MPB : 1;
+			unsigned char TEND : 1;
+			unsigned char PER : 1;
+			unsigned char FER : 1;
+			unsigned char ORER : 1;
+			unsigned char RDRF : 1;
+			unsigned char TDRE : 1;
+#else
+			unsigned char TDRE : 1;
+			unsigned char RDRF : 1;
+			unsigned char ORER : 1;
+			unsigned char FER : 1;
+			unsigned char PER : 1;
+			unsigned char TEND : 1;
+			unsigned char MPB : 1;
+			unsigned char MPBT : 1;
+#endif
+	} BIT;
+	} SSR;
+	unsigned char  RDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SMIF : 1;
+			unsigned char  : 1;
+			unsigned char SINV : 1;
+			unsigned char SDIR : 1;
+			unsigned char CHR1 : 1;
+			unsigned char  : 2;
+			unsigned char BCP2 : 1;
+#else
+			unsigned char BCP2 : 1;
+			unsigned char  : 2;
+			unsigned char CHR1 : 1;
+			unsigned char SDIR : 1;
+			unsigned char SINV : 1;
+			unsigned char  : 1;
+			unsigned char SMIF : 1;
+#endif
+	} BIT;
+	} SCMR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ACS0 : 1;
+			unsigned char  : 1;
+			unsigned char BRME : 1;
+			unsigned char  : 1;
+			unsigned char ABCS : 1;
+			unsigned char NFEN : 1;
+			unsigned char BGDM : 1;
+			unsigned char RXDESEL : 1;
+#else
+			unsigned char RXDESEL : 1;
+			unsigned char BGDM : 1;
+			unsigned char NFEN : 1;
+			unsigned char ABCS : 1;
+			unsigned char  : 1;
+			unsigned char BRME : 1;
+			unsigned char  : 1;
+			unsigned char ACS0 : 1;
+#endif
+	} BIT;
+	} SEMR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFCS : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char NFCS : 3;
+#endif
+	} BIT;
+	} SNFR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICM : 1;
+			unsigned char  : 2;
+			unsigned char IICDL : 5;
+#else
+			unsigned char IICDL : 5;
+			unsigned char  : 2;
+			unsigned char IICM : 1;
+#endif
+	} BIT;
+	} SIMR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICINTM : 1;
+			unsigned char IICCSC : 1;
+			unsigned char  : 3;
+			unsigned char IICACKT : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char IICACKT : 1;
+			unsigned char  : 3;
+			unsigned char IICCSC : 1;
+			unsigned char IICINTM : 1;
+#endif
+	} BIT;
+	} SIMR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICSTAREQ : 1;
+			unsigned char IICRSTAREQ : 1;
+			unsigned char IICSTPREQ : 1;
+			unsigned char IICSTIF : 1;
+			unsigned char IICSDAS : 2;
+			unsigned char IICSCLS : 2;
+#else
+			unsigned char IICSCLS : 2;
+			unsigned char IICSDAS : 2;
+			unsigned char IICSTIF : 1;
+			unsigned char IICSTPREQ : 1;
+			unsigned char IICRSTAREQ : 1;
+			unsigned char IICSTAREQ : 1;
+#endif
+	} BIT;
+	} SIMR3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICACKR : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char IICACKR : 1;
+#endif
+	} BIT;
+	} SISR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SSE : 1;
+			unsigned char CTSE : 1;
+			unsigned char MSS : 1;
+			unsigned char  : 1;
+			unsigned char MFF : 1;
+			unsigned char  : 1;
+			unsigned char CKPOL : 1;
+			unsigned char CKPH : 1;
+#else
+			unsigned char CKPH : 1;
+			unsigned char CKPOL : 1;
+			unsigned char  : 1;
+			unsigned char MFF : 1;
+			unsigned char  : 1;
+			unsigned char MSS : 1;
+			unsigned char CTSE : 1;
+			unsigned char SSE : 1;
+#endif
+	} BIT;
+	} SPMR;
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char TDRH;
+			unsigned char TDRL;
+		} BYTE;
+	} TDRHL;
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char RDRH;
+			unsigned char RDRL;
+		} BYTE;
+	} RDRHL;
+	unsigned char  MDDR;
+} st_sci0_t;
+
+typedef struct st_sci10 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKS : 2;
+			unsigned char MP : 1;
+			unsigned char STOP : 1;
+			unsigned char PM : 1;
+			unsigned char PE : 1;
+			unsigned char CHR : 1;
+			unsigned char CM : 1;
+#else
+			unsigned char CM : 1;
+			unsigned char CHR : 1;
+			unsigned char PE : 1;
+			unsigned char PM : 1;
+			unsigned char STOP : 1;
+			unsigned char MP : 1;
+			unsigned char CKS : 2;
+#endif
+	} BIT;
+	} SMR;
+	unsigned char  BRR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKE : 2;
+			unsigned char TEIE : 1;
+			unsigned char MPIE : 1;
+			unsigned char RE : 1;
+			unsigned char TE : 1;
+			unsigned char RIE : 1;
+			unsigned char TIE : 1;
+#else
+			unsigned char TIE : 1;
+			unsigned char RIE : 1;
+			unsigned char TE : 1;
+			unsigned char RE : 1;
+			unsigned char MPIE : 1;
+			unsigned char TEIE : 1;
+			unsigned char CKE : 2;
+#endif
+	} BIT;
+	} SCR;
+	unsigned char  TDR;
+	union {
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MPBT : 1;
+			unsigned char MPB : 1;
+			unsigned char TEND : 1;
+			unsigned char PER : 1;
+			unsigned char FER : 1;
+			unsigned char ORER : 1;
+			unsigned char RDRF : 1;
+			unsigned char TDRE : 1;
+#else
+			unsigned char TDRE : 1;
+			unsigned char RDRF : 1;
+			unsigned char ORER : 1;
+			unsigned char FER : 1;
+			unsigned char PER : 1;
+			unsigned char TEND : 1;
+			unsigned char MPB : 1;
+			unsigned char MPBT : 1;
+#endif
+	} BIT;
+		} SSR;
+		union {
+			unsigned char BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DR : 1;
+			unsigned char  : 1;
+			unsigned char TEND : 1;
+			unsigned char PER : 1;
+			unsigned char FER : 1;
+			unsigned char ORER : 1;
+			unsigned char RDF : 1;
+			unsigned char TDFE : 1;
+#else
+			unsigned char TDFE : 1;
+			unsigned char RDF : 1;
+			unsigned char ORER : 1;
+			unsigned char FER : 1;
+			unsigned char PER : 1;
+			unsigned char TEND : 1;
+			unsigned char  : 1;
+			unsigned char DR : 1;
+#endif
+	} BIT;
+		} SSRFIFO;
+	};
+	unsigned char  RDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SMIF : 1;
+			unsigned char  : 1;
+			unsigned char SINV : 1;
+			unsigned char SDIR : 1;
+			unsigned char CHR1 : 1;
+			unsigned char  : 2;
+			unsigned char BCP2 : 1;
+#else
+			unsigned char BCP2 : 1;
+			unsigned char  : 2;
+			unsigned char CHR1 : 1;
+			unsigned char SDIR : 1;
+			unsigned char SINV : 1;
+			unsigned char  : 1;
+			unsigned char SMIF : 1;
+#endif
+	} BIT;
+	} SCMR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ACS0 : 1;
+			unsigned char  : 1;
+			unsigned char BRME : 1;
+			unsigned char  : 1;
+			unsigned char ABCS : 1;
+			unsigned char NFEN : 1;
+			unsigned char BGDM : 1;
+			unsigned char RXDESEL : 1;
+#else
+			unsigned char RXDESEL : 1;
+			unsigned char BGDM : 1;
+			unsigned char NFEN : 1;
+			unsigned char ABCS : 1;
+			unsigned char  : 1;
+			unsigned char BRME : 1;
+			unsigned char  : 1;
+			unsigned char ACS0 : 1;
+#endif
+	} BIT;
+	} SEMR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFCS : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char NFCS : 3;
+#endif
+	} BIT;
+	} SNFR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICM : 1;
+			unsigned char  : 2;
+			unsigned char IICDL : 5;
+#else
+			unsigned char IICDL : 5;
+			unsigned char  : 2;
+			unsigned char IICM : 1;
+#endif
+	} BIT;
+	} SIMR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICINTM : 1;
+			unsigned char IICCSC : 1;
+			unsigned char  : 3;
+			unsigned char IICACKT : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char IICACKT : 1;
+			unsigned char  : 3;
+			unsigned char IICCSC : 1;
+			unsigned char IICINTM : 1;
+#endif
+	} BIT;
+	} SIMR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICSTAREQ : 1;
+			unsigned char IICRSTAREQ : 1;
+			unsigned char IICSTPREQ : 1;
+			unsigned char IICSTIF : 1;
+			unsigned char IICSDAS : 2;
+			unsigned char IICSCLS : 2;
+#else
+			unsigned char IICSCLS : 2;
+			unsigned char IICSDAS : 2;
+			unsigned char IICSTIF : 1;
+			unsigned char IICSTPREQ : 1;
+			unsigned char IICRSTAREQ : 1;
+			unsigned char IICSTAREQ : 1;
+#endif
+	} BIT;
+	} SIMR3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICACKR : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char IICACKR : 1;
+#endif
+	} BIT;
+	} SISR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SSE : 1;
+			unsigned char CTSE : 1;
+			unsigned char MSS : 1;
+			unsigned char  : 1;
+			unsigned char MFF : 1;
+			unsigned char  : 1;
+			unsigned char CKPOL : 1;
+			unsigned char CKPH : 1;
+#else
+			unsigned char CKPH : 1;
+			unsigned char CKPOL : 1;
+			unsigned char  : 1;
+			unsigned char MFF : 1;
+			unsigned char  : 1;
+			unsigned char MSS : 1;
+			unsigned char CTSE : 1;
+			unsigned char SSE : 1;
+#endif
+	} BIT;
+	} SPMR;
+	union {
+		union {
+			unsigned short WORD;
+			struct {
+				unsigned char TDRH;
+				unsigned char TDRL;
+			} BYTE;
+		} TDRHL;
+		union {
+			unsigned short WORD;
+			struct {
+				unsigned char H;
+				unsigned char L;
+			} BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short TDAT : 9;
+			unsigned short MPBT : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short MPBT : 1;
+			unsigned short TDAT : 9;
+#endif
+	} BIT;
+		} FTDR;
+	};
+	union {
+		union {
+			unsigned short WORD;
+			struct {
+				unsigned char RDRH;
+				unsigned char RDRL;
+			} BYTE;
+		} RDRHL;
+		union {
+			unsigned short WORD;
+			struct {
+				unsigned char H;
+				unsigned char L;
+			} BYTE;
+			struct {
+				
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RDAT : 9;
+			unsigned short MPB : 1;
+			unsigned short DR : 1;
+			unsigned short PER : 1;
+			unsigned short FER : 1;
+			unsigned short ORER : 1;
+			unsigned short RDF : 1;
+			unsigned short  : 1;
+#else
+			unsigned short  : 1;
+			unsigned short RDF : 1;
+			unsigned short ORER : 1;
+			unsigned short FER : 1;
+			unsigned short PER : 1;
+			unsigned short DR : 1;
+			unsigned short MPB : 1;
+			unsigned short RDAT : 9;
+#endif
+	} BIT;
+		} FRDR;
+	};
+	unsigned char  MDDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DCMF : 1;
+			unsigned char  : 2;
+			unsigned char DPER : 1;
+			unsigned char DFER : 1;
+			unsigned char  : 1;
+			unsigned char IDSEL : 1;
+			unsigned char DCME : 1;
+#else
+			unsigned char DCME : 1;
+			unsigned char IDSEL : 1;
+			unsigned char  : 1;
+			unsigned char DFER : 1;
+			unsigned char DPER : 1;
+			unsigned char  : 2;
+			unsigned char DCMF : 1;
+#endif
+	} BIT;
+	} DCCR;
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char H;
+			unsigned char L;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short FM : 1;
+			unsigned short RFRST : 1;
+			unsigned short TFRST : 1;
+			unsigned short DRES : 1;
+			unsigned short TTRG : 4;
+			unsigned short RTRG : 4;
+			unsigned short RSTRG : 4;
+#else
+			unsigned short RSTRG : 4;
+			unsigned short RTRG : 4;
+			unsigned short TTRG : 4;
+			unsigned short DRES : 1;
+			unsigned short TFRST : 1;
+			unsigned short RFRST : 1;
+			unsigned short FM : 1;
+#endif
+	} BIT;
+	} FCR;
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char H;
+			unsigned char L;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short R : 5;
+			unsigned short  : 3;
+			unsigned short T : 5;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short T : 5;
+			unsigned short  : 3;
+			unsigned short R : 5;
+#endif
+	} BIT;
+	} FDR;
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char H;
+			unsigned char L;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ORER : 1;
+			unsigned short  : 1;
+			unsigned short FNUM : 5;
+			unsigned short  : 1;
+			unsigned short PNUM : 5;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short PNUM : 5;
+			unsigned short  : 1;
+			unsigned short FNUM : 5;
+			unsigned short  : 1;
+			unsigned short ORER : 1;
+#endif
+	} BIT;
+	} LSR;
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char H;
+			unsigned char L;
+		} BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMPD : 9;
+			unsigned short  : 7;
+#else
+			unsigned short  : 7;
+			unsigned short CMPD : 9;
+#endif
+	} BIT;
+	} CDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RXDMON : 1;
+			unsigned char SPB2DT : 1;
+			unsigned char SPB2IO : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SPB2IO : 1;
+			unsigned char SPB2DT : 1;
+			unsigned char RXDMON : 1;
+#endif
+	} BIT;
+	} SPTR;
+} st_sci10_t;
+
+typedef struct st_sci12 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKS : 2;
+			unsigned char MP : 1;
+			unsigned char STOP : 1;
+			unsigned char PM : 1;
+			unsigned char PE : 1;
+			unsigned char CHR : 1;
+			unsigned char CM : 1;
+#else
+			unsigned char CM : 1;
+			unsigned char CHR : 1;
+			unsigned char PE : 1;
+			unsigned char PM : 1;
+			unsigned char STOP : 1;
+			unsigned char MP : 1;
+			unsigned char CKS : 2;
+#endif
+	} BIT;
+	} SMR;
+	unsigned char  BRR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKE : 2;
+			unsigned char TEIE : 1;
+			unsigned char MPIE : 1;
+			unsigned char RE : 1;
+			unsigned char TE : 1;
+			unsigned char RIE : 1;
+			unsigned char TIE : 1;
+#else
+			unsigned char TIE : 1;
+			unsigned char RIE : 1;
+			unsigned char TE : 1;
+			unsigned char RE : 1;
+			unsigned char MPIE : 1;
+			unsigned char TEIE : 1;
+			unsigned char CKE : 2;
+#endif
+	} BIT;
+	} SCR;
+	unsigned char  TDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MPBT : 1;
+			unsigned char MPB : 1;
+			unsigned char TEND : 1;
+			unsigned char PER : 1;
+			unsigned char FER : 1;
+			unsigned char ORER : 1;
+			unsigned char RDRF : 1;
+			unsigned char TDRE : 1;
+#else
+			unsigned char TDRE : 1;
+			unsigned char RDRF : 1;
+			unsigned char ORER : 1;
+			unsigned char FER : 1;
+			unsigned char PER : 1;
+			unsigned char TEND : 1;
+			unsigned char MPB : 1;
+			unsigned char MPBT : 1;
+#endif
+	} BIT;
+	} SSR;
+	unsigned char  RDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SMIF : 1;
+			unsigned char  : 1;
+			unsigned char SINV : 1;
+			unsigned char SDIR : 1;
+			unsigned char CHR1 : 1;
+			unsigned char  : 2;
+			unsigned char BCP2 : 1;
+#else
+			unsigned char BCP2 : 1;
+			unsigned char  : 2;
+			unsigned char CHR1 : 1;
+			unsigned char SDIR : 1;
+			unsigned char SINV : 1;
+			unsigned char  : 1;
+			unsigned char SMIF : 1;
+#endif
+	} BIT;
+	} SCMR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ACS0 : 1;
+			unsigned char  : 1;
+			unsigned char BRME : 1;
+			unsigned char  : 1;
+			unsigned char ABCS : 1;
+			unsigned char NFEN : 1;
+			unsigned char BGDM : 1;
+			unsigned char RXDESEL : 1;
+#else
+			unsigned char RXDESEL : 1;
+			unsigned char BGDM : 1;
+			unsigned char NFEN : 1;
+			unsigned char ABCS : 1;
+			unsigned char  : 1;
+			unsigned char BRME : 1;
+			unsigned char  : 1;
+			unsigned char ACS0 : 1;
+#endif
+	} BIT;
+	} SEMR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFCS : 3;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char NFCS : 3;
+#endif
+	} BIT;
+	} SNFR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICM : 1;
+			unsigned char  : 2;
+			unsigned char IICDL : 5;
+#else
+			unsigned char IICDL : 5;
+			unsigned char  : 2;
+			unsigned char IICM : 1;
+#endif
+	} BIT;
+	} SIMR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICINTM : 1;
+			unsigned char IICCSC : 1;
+			unsigned char  : 3;
+			unsigned char IICACKT : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char IICACKT : 1;
+			unsigned char  : 3;
+			unsigned char IICCSC : 1;
+			unsigned char IICINTM : 1;
+#endif
+	} BIT;
+	} SIMR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICSTAREQ : 1;
+			unsigned char IICRSTAREQ : 1;
+			unsigned char IICSTPREQ : 1;
+			unsigned char IICSTIF : 1;
+			unsigned char IICSDAS : 2;
+			unsigned char IICSCLS : 2;
+#else
+			unsigned char IICSCLS : 2;
+			unsigned char IICSDAS : 2;
+			unsigned char IICSTIF : 1;
+			unsigned char IICSTPREQ : 1;
+			unsigned char IICRSTAREQ : 1;
+			unsigned char IICSTAREQ : 1;
+#endif
+	} BIT;
+	} SIMR3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IICACKR : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char IICACKR : 1;
+#endif
+	} BIT;
+	} SISR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SSE : 1;
+			unsigned char CTSE : 1;
+			unsigned char MSS : 1;
+			unsigned char  : 1;
+			unsigned char MFF : 1;
+			unsigned char  : 1;
+			unsigned char CKPOL : 1;
+			unsigned char CKPH : 1;
+#else
+			unsigned char CKPH : 1;
+			unsigned char CKPOL : 1;
+			unsigned char  : 1;
+			unsigned char MFF : 1;
+			unsigned char  : 1;
+			unsigned char MSS : 1;
+			unsigned char CTSE : 1;
+			unsigned char SSE : 1;
+#endif
+	} BIT;
+	} SPMR;
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char TDRH;
+			unsigned char TDRL;
+		} BYTE;
+	} TDRHL;
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char RDRH;
+			unsigned char RDRL;
+		} BYTE;
+	} RDRHL;
+	unsigned char  MDDR;
+	char           wk0[13];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ESME : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char ESME : 1;
+#endif
+	} BIT;
+	} ESMER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 1;
+			unsigned char SFSF : 1;
+			unsigned char RXDSF : 1;
+			unsigned char BRME : 1;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char BRME : 1;
+			unsigned char RXDSF : 1;
+			unsigned char SFSF : 1;
+			unsigned char  : 1;
+#endif
+	} BIT;
+	} CR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BFE : 1;
+			unsigned char CF0RE : 1;
+			unsigned char CF1DS : 2;
+			unsigned char PIBE : 1;
+			unsigned char PIBS : 3;
+#else
+			unsigned char PIBS : 3;
+			unsigned char PIBE : 1;
+			unsigned char CF1DS : 2;
+			unsigned char CF0RE : 1;
+			unsigned char BFE : 1;
+#endif
+	} BIT;
+	} CR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DFCS : 3;
+			unsigned char  : 1;
+			unsigned char BCCS : 2;
+			unsigned char RTS : 2;
+#else
+			unsigned char RTS : 2;
+			unsigned char BCCS : 2;
+			unsigned char  : 1;
+			unsigned char DFCS : 3;
+#endif
+	} BIT;
+	} CR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SDST : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char SDST : 1;
+#endif
+	} BIT;
+	} CR3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TXDXPS : 1;
+			unsigned char RXDXPS : 1;
+			unsigned char  : 2;
+			unsigned char SHARPS : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char SHARPS : 1;
+			unsigned char  : 2;
+			unsigned char RXDXPS : 1;
+			unsigned char TXDXPS : 1;
+#endif
+	} BIT;
+	} PCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BFDIE : 1;
+			unsigned char CF0MIE : 1;
+			unsigned char CF1MIE : 1;
+			unsigned char PIBDIE : 1;
+			unsigned char BCDIE : 1;
+			unsigned char AEDIE : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char AEDIE : 1;
+			unsigned char BCDIE : 1;
+			unsigned char PIBDIE : 1;
+			unsigned char CF1MIE : 1;
+			unsigned char CF0MIE : 1;
+			unsigned char BFDIE : 1;
+#endif
+	} BIT;
+	} ICR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BFDF : 1;
+			unsigned char CF0MF : 1;
+			unsigned char CF1MF : 1;
+			unsigned char PIBDF : 1;
+			unsigned char BCDF : 1;
+			unsigned char AEDF : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char AEDF : 1;
+			unsigned char BCDF : 1;
+			unsigned char PIBDF : 1;
+			unsigned char CF1MF : 1;
+			unsigned char CF0MF : 1;
+			unsigned char BFDF : 1;
+#endif
+	} BIT;
+	} STR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BFDCL : 1;
+			unsigned char CF0MCL : 1;
+			unsigned char CF1MCL : 1;
+			unsigned char PIBDCL : 1;
+			unsigned char BCDCL : 1;
+			unsigned char AEDCL : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char AEDCL : 1;
+			unsigned char BCDCL : 1;
+			unsigned char PIBDCL : 1;
+			unsigned char CF1MCL : 1;
+			unsigned char CF0MCL : 1;
+			unsigned char BFDCL : 1;
+#endif
+	} BIT;
+	} STCR;
+	unsigned char  CF0DR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CF0CE0 : 1;
+			unsigned char CF0CE1 : 1;
+			unsigned char CF0CE2 : 1;
+			unsigned char CF0CE3 : 1;
+			unsigned char CF0CE4 : 1;
+			unsigned char CF0CE5 : 1;
+			unsigned char CF0CE6 : 1;
+			unsigned char CF0CE7 : 1;
+#else
+			unsigned char CF0CE7 : 1;
+			unsigned char CF0CE6 : 1;
+			unsigned char CF0CE5 : 1;
+			unsigned char CF0CE4 : 1;
+			unsigned char CF0CE3 : 1;
+			unsigned char CF0CE2 : 1;
+			unsigned char CF0CE1 : 1;
+			unsigned char CF0CE0 : 1;
+#endif
+	} BIT;
+	} CF0CR;
+	unsigned char  CF0RR;
+	unsigned char  PCF1DR;
+	unsigned char  SCF1DR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CF1CE0 : 1;
+			unsigned char CF1CE1 : 1;
+			unsigned char CF1CE2 : 1;
+			unsigned char CF1CE3 : 1;
+			unsigned char CF1CE4 : 1;
+			unsigned char CF1CE5 : 1;
+			unsigned char CF1CE6 : 1;
+			unsigned char CF1CE7 : 1;
+#else
+			unsigned char CF1CE7 : 1;
+			unsigned char CF1CE6 : 1;
+			unsigned char CF1CE5 : 1;
+			unsigned char CF1CE4 : 1;
+			unsigned char CF1CE3 : 1;
+			unsigned char CF1CE2 : 1;
+			unsigned char CF1CE1 : 1;
+			unsigned char CF1CE0 : 1;
+#endif
+	} BIT;
+	} CF1CR;
+	unsigned char  CF1RR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TCST : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char TCST : 1;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TOMS : 2;
+			unsigned char  : 1;
+			unsigned char TWRC : 1;
+			unsigned char TCSS : 3;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char TCSS : 3;
+			unsigned char TWRC : 1;
+			unsigned char  : 1;
+			unsigned char TOMS : 2;
+#endif
+	} BIT;
+	} TMR;
+	unsigned char  TPRE;
+	unsigned char  TCNT;
+} st_sci12_t;
+
+typedef struct st_sdhi {
+	union {
+		unsigned long LONG;
+#ifdef IODEFINE_H_HISTORY
+		struct {
+			unsigned long :16;
+			unsigned long CMD12AT:2;
+			unsigned long TRSTP:1;
+			unsigned long CMDRW:1;
+			unsigned long CMDTP:1;
+			unsigned long RSPTP:3;
+			unsigned long ACMD:2;
+			unsigned long CMDIDX:6;
+		} BIT;
+#endif
+	} SDCMD;
+	char           wk0[4];
+	unsigned long  SDARG;
+	char           wk1[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long STP : 1;
+			unsigned long  : 7;
+			unsigned long SDBLKCNTEN : 1;
+			unsigned long  : 23;
+#else
+			unsigned long  : 23;
+			unsigned long SDBLKCNTEN : 1;
+			unsigned long  : 7;
+			unsigned long STP : 1;
+#endif
+	} BIT;
+	} SDSTOP;
+	unsigned long  SDBLKCNT;
+	unsigned long  SDRSP10;
+	char           wk2[4];
+	unsigned long  SDRSP32;
+	char           wk3[4];
+	unsigned long  SDRSP54;
+	char           wk4[4];
+	unsigned long  SDRSP76;
+	char           wk5[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RSPEND : 1;
+			unsigned long  : 1;
+			unsigned long ACEND : 1;
+			unsigned long SDCDRM : 1;
+			unsigned long SDCDIN : 1;
+			unsigned long SDCDMON : 1;
+			unsigned long  : 1;
+			unsigned long SDWPMON : 1;
+			unsigned long SDD3RM : 1;
+			unsigned long SDD3IN : 1;
+			unsigned long SDD3MON : 1;
+			unsigned long  : 21;
+#else
+			unsigned long  : 21;
+			unsigned long SDD3MON : 1;
+			unsigned long SDD3IN : 1;
+			unsigned long SDD3RM : 1;
+			unsigned long SDWPMON : 1;
+			unsigned long  : 1;
+			unsigned long SDCDMON : 1;
+			unsigned long SDCDIN : 1;
+			unsigned long SDCDRM : 1;
+			unsigned long ACEND : 1;
+			unsigned long  : 1;
+			unsigned long RSPEND : 1;
+#endif
+	} BIT;
+	} SDSTS1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CMDE : 1;
+			unsigned long CRCE : 1;
+			unsigned long ENDE : 1;
+			unsigned long DTO : 1;
+			unsigned long ILW : 1;
+			unsigned long ILR : 1;
+			unsigned long RSPTO : 1;
+			unsigned long SDD0MON : 1;
+			unsigned long BRE : 1;
+			unsigned long BWE : 1;
+			unsigned long  : 3;
+			unsigned long SDCLKCREN : 1;
+			unsigned long CBSY : 1;
+			unsigned long ILA : 1;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long ILA : 1;
+			unsigned long CBSY : 1;
+			unsigned long SDCLKCREN : 1;
+			unsigned long  : 3;
+			unsigned long BWE : 1;
+			unsigned long BRE : 1;
+			unsigned long SDD0MON : 1;
+			unsigned long RSPTO : 1;
+			unsigned long ILR : 1;
+			unsigned long ILW : 1;
+			unsigned long DTO : 1;
+			unsigned long ENDE : 1;
+			unsigned long CRCE : 1;
+			unsigned long CMDE : 1;
+#endif
+	} BIT;
+	} SDSTS2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RSPENDM : 1;
+			unsigned long  : 1;
+			unsigned long ACENDM : 1;
+			unsigned long SDCDRMM : 1;
+			unsigned long SDCDINM : 1;
+			unsigned long  : 3;
+			unsigned long SDD3RMM : 1;
+			unsigned long SDD3INM : 1;
+			unsigned long  : 22;
+#else
+			unsigned long  : 22;
+			unsigned long SDD3INM : 1;
+			unsigned long SDD3RMM : 1;
+			unsigned long  : 3;
+			unsigned long SDCDINM : 1;
+			unsigned long SDCDRMM : 1;
+			unsigned long ACENDM : 1;
+			unsigned long  : 1;
+			unsigned long RSPENDM : 1;
+#endif
+	} BIT;
+	} SDIMSK1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CMDEM : 1;
+			unsigned long CRCEM : 1;
+			unsigned long ENDEM : 1;
+			unsigned long DTTOM : 1;
+			unsigned long ILWM : 1;
+			unsigned long ILRM : 1;
+			unsigned long RSPTOM : 1;
+			unsigned long  : 1;
+			unsigned long BREM : 1;
+			unsigned long BWEM : 1;
+			unsigned long  : 5;
+			unsigned long ILAM : 1;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long ILAM : 1;
+			unsigned long  : 5;
+			unsigned long BWEM : 1;
+			unsigned long BREM : 1;
+			unsigned long  : 1;
+			unsigned long RSPTOM : 1;
+			unsigned long ILRM : 1;
+			unsigned long ILWM : 1;
+			unsigned long DTTOM : 1;
+			unsigned long ENDEM : 1;
+			unsigned long CRCEM : 1;
+			unsigned long CMDEM : 1;
+#endif
+	} BIT;
+	} SDIMSK2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CLKSEL : 8;
+			unsigned long CLKEN : 1;
+			unsigned long CLKCTRLEN : 1;
+			unsigned long  : 22;
+#else
+			unsigned long  : 22;
+			unsigned long CLKCTRLEN : 1;
+			unsigned long CLKEN : 1;
+			unsigned long CLKSEL : 8;
+#endif
+	} BIT;
+	} SDCLKCR;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long LEN : 10;
+			unsigned long  : 22;
+#else
+			unsigned long  : 22;
+			unsigned long LEN : 10;
+#endif
+	} BIT;
+	} SDSIZE;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CTOP : 4;
+			unsigned long TOP : 4;
+			unsigned long  : 7;
+			unsigned long WIDTH : 1;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long WIDTH : 1;
+			unsigned long  : 7;
+			unsigned long TOP : 4;
+			unsigned long CTOP : 4;
+#endif
+	} BIT;
+	} SDOPT;
+	char           wk6[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CMDE0 : 1;
+			unsigned long CMDE1 : 1;
+			unsigned long RSPLENE0 : 1;
+			unsigned long RSPLENE1 : 1;
+			unsigned long RDLENE : 1;
+			unsigned long CRCLENE : 1;
+			unsigned long  : 2;
+			unsigned long RSPCRCE0 : 1;
+			unsigned long RSPCRCE1 : 1;
+			unsigned long RDCRCE : 1;
+			unsigned long CRCTKE : 1;
+			unsigned long CRCTK : 3;
+			unsigned long  : 17;
+#else
+			unsigned long  : 17;
+			unsigned long CRCTK : 3;
+			unsigned long CRCTKE : 1;
+			unsigned long RDCRCE : 1;
+			unsigned long RSPCRCE1 : 1;
+			unsigned long RSPCRCE0 : 1;
+			unsigned long  : 2;
+			unsigned long CRCLENE : 1;
+			unsigned long RDLENE : 1;
+			unsigned long RSPLENE1 : 1;
+			unsigned long RSPLENE0 : 1;
+			unsigned long CMDE1 : 1;
+			unsigned long CMDE0 : 1;
+#endif
+	} BIT;
+	} SDERSTS1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RSPTO0 : 1;
+			unsigned long RSPTO1 : 1;
+			unsigned long BSYTO0 : 1;
+			unsigned long BSYTO1 : 1;
+			unsigned long RDTO : 1;
+			unsigned long CRCTO : 1;
+			unsigned long CRCBSYTO : 1;
+			unsigned long  : 25;
+#else
+			unsigned long  : 25;
+			unsigned long CRCBSYTO : 1;
+			unsigned long CRCTO : 1;
+			unsigned long RDTO : 1;
+			unsigned long BSYTO1 : 1;
+			unsigned long BSYTO0 : 1;
+			unsigned long RSPTO1 : 1;
+			unsigned long RSPTO0 : 1;
+#endif
+	} BIT;
+	} SDERSTS2;
+	unsigned long  SDBUFR;
+	char           wk7[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long INTEN : 1;
+			unsigned long  : 1;
+			unsigned long RWREQ : 1;
+			unsigned long  : 5;
+			unsigned long IOABT : 1;
+			unsigned long C52PUB : 1;
+			unsigned long  : 22;
+#else
+			unsigned long  : 22;
+			unsigned long C52PUB : 1;
+			unsigned long IOABT : 1;
+			unsigned long  : 5;
+			unsigned long RWREQ : 1;
+			unsigned long  : 1;
+			unsigned long INTEN : 1;
+#endif
+	} BIT;
+	} SDIOMD;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IOIRQ : 1;
+			unsigned long  : 13;
+			unsigned long EXPUB52 : 1;
+			unsigned long EXWT : 1;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long EXWT : 1;
+			unsigned long EXPUB52 : 1;
+			unsigned long  : 13;
+			unsigned long IOIRQ : 1;
+#endif
+	} BIT;
+	} SDIOSTS;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IOIRQM : 1;
+			unsigned long  : 13;
+			unsigned long EXPUB52M : 1;
+			unsigned long EXWTM : 1;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long EXWTM : 1;
+			unsigned long EXPUB52M : 1;
+			unsigned long  : 13;
+			unsigned long IOIRQM : 1;
+#endif
+	} BIT;
+	} SDIOIMSK;
+	char           wk8[316];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 1;
+			unsigned long DMAEN : 1;
+			unsigned long  : 30;
+#else
+			unsigned long  : 30;
+			unsigned long DMAEN : 1;
+			unsigned long  : 1;
+#endif
+	} BIT;
+	} SDDMAEN;
+	char           wk9[12];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long SDRST : 1;
+			unsigned long  : 31;
+#else
+			unsigned long  : 31;
+			unsigned long SDRST : 1;
+#endif
+	} BIT;
+	} SDRST;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long IP1 : 8;
+			unsigned long IP2 : 4;
+			unsigned long  : 2;
+			unsigned long CLKRAT : 1;
+			unsigned long CPRM : 1;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long CPRM : 1;
+			unsigned long CLKRAT : 1;
+			unsigned long  : 2;
+			unsigned long IP2 : 4;
+			unsigned long IP1 : 8;
+#endif
+	} BIT;
+	} SDVER;
+	char           wk10[24];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 6;
+			unsigned long BWSWP : 1;
+			unsigned long BRSWP : 1;
+			unsigned long  : 24;
+#else
+			unsigned long  : 24;
+			unsigned long BRSWP : 1;
+			unsigned long BWSWP : 1;
+			unsigned long  : 6;
+#endif
+	} BIT;
+	} SDSWAP;
+} st_sdhi_t;
+
+typedef struct st_sdsi {
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long  : 11;
+			unsigned long FN1ACC : 1;
+			unsigned long  : 20;
+#else
+			unsigned long  : 20;
+			unsigned long FN1ACC : 1;
+			unsigned long  : 11;
+#endif
+	} BIT;
+	} FN1ACCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMD52WIREN : 1;
+			unsigned char CMD53WIREN : 1;
+			unsigned char CMD53RIREN : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char CMD53RIREN : 1;
+			unsigned char CMD53WIREN : 1;
+			unsigned char CMD52WIREN : 1;
+#endif
+	} BIT;
+	} INTENCR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CMD52W : 1;
+			unsigned char CMD53W : 1;
+			unsigned char CMD53R : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char CMD53R : 1;
+			unsigned char CMD53W : 1;
+			unsigned char CMD52W : 1;
+#endif
+	} BIT;
+	} INTSR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SDCMDINDEX : 1;
+			unsigned char SDWNRFLG : 1;
+			unsigned char SDRAWFLG : 1;
+			unsigned char SDBMODE : 1;
+			unsigned char SDOPCODE : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char SDOPCODE : 1;
+			unsigned char SDBMODE : 1;
+			unsigned char SDRAWFLG : 1;
+			unsigned char SDWNRFLG : 1;
+			unsigned char SDCMDINDEX : 1;
+#endif
+	} BIT;
+	} SDCMDCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SDCMDACCADD : 8;
+#else
+			unsigned char SDCMDACCADD : 8;
+#endif
+	} BIT;
+	} SDCADD0R;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SDCMDACCADD : 8;
+#else
+			unsigned char SDCMDACCADD : 8;
+#endif
+	} BIT;
+	} SDCADD1R;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SDCMDACCADD : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char SDCMDACCADD : 1;
+#endif
+	} BIT;
+	} SDCADD2R;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOE1IOR1 : 1;
+			unsigned char EPS : 1;
+			unsigned char EMPC : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char EMPC : 1;
+			unsigned char EPS : 1;
+			unsigned char IOE1IOR1 : 1;
+#endif
+	} BIT;
+	} SDSICR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DMAEN : 1;
+			unsigned char DMALOCKEN : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char DMALOCKEN : 1;
+			unsigned char DMAEN : 1;
+#endif
+	} BIT;
+	} DMACR1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMD53BLK : 9;
+			unsigned short  : 7;
+#else
+			unsigned short  : 7;
+			unsigned short CMD53BLK : 9;
+#endif
+	} BIT;
+	} BLKCNT;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CMD53BYT : 12;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short CMD53BYT : 12;
+#endif
+	} BIT;
+	} BYTCNT;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DMAADD : 32;
+#else
+			unsigned long DMAADD : 32;
+#endif
+	} BIT;
+	} DMATRADDR;
+	char           wk0[236];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long RSWAP : 1;
+			unsigned long  : 1;
+			unsigned long WSWAP : 1;
+			unsigned long  : 1;
+			unsigned long REG5EN : 1;
+			unsigned long  : 27;
+#else
+			unsigned long  : 27;
+			unsigned long REG5EN : 1;
+			unsigned long  : 1;
+			unsigned long WSWAP : 1;
+			unsigned long  : 1;
+			unsigned long RSWAP : 1;
+#endif
+	} BIT;
+	} SDSICR2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long SRST : 1;
+			unsigned long  : 1;
+			unsigned long IOR0 : 1;
+			unsigned long CEN : 1;
+			unsigned long  : 14;
+			unsigned long SPS : 1;
+			unsigned long SMPC : 1;
+			unsigned long  : 12;
+#else
+			unsigned long  : 12;
+			unsigned long SMPC : 1;
+			unsigned long SPS : 1;
+			unsigned long  : 14;
+			unsigned long CEN : 1;
+			unsigned long IOR0 : 1;
+			unsigned long  : 1;
+			unsigned long SRST : 1;
+#endif
+	} BIT;
+	} SDSICR3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CDFEN : 1;
+			unsigned long CDREN : 1;
+			unsigned long DTEEN : 1;
+			unsigned long  : 29;
+#else
+			unsigned long  : 29;
+			unsigned long DTEEN : 1;
+			unsigned long CDREN : 1;
+			unsigned long CDFEN : 1;
+#endif
+	} BIT;
+	} INTENCR2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long CDF : 1;
+			unsigned long CDR : 1;
+			unsigned long DTE : 1;
+			unsigned long  : 29;
+#else
+			unsigned long  : 29;
+			unsigned long DTE : 1;
+			unsigned long CDR : 1;
+			unsigned long CDF : 1;
+#endif
+	} BIT;
+	} INTSR2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DMARSWAP : 2;
+			unsigned long DMAWSWAP : 2;
+			unsigned long  : 4;
+			unsigned long DMASDSEL : 1;
+			unsigned long  : 23;
+#else
+			unsigned long  : 23;
+			unsigned long DMASDSEL : 1;
+			unsigned long  : 4;
+			unsigned long DMAWSWAP : 2;
+			unsigned long DMARSWAP : 2;
+#endif
+	} BIT;
+	} DMACR2;
+	char           wk1[236];
+	unsigned long  CISDATAR[27];
+	char           wk2[4];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FBR1L : 4;
+			unsigned long  : 4;
+			unsigned long FBR1U : 8;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long FBR1U : 8;
+			unsigned long  : 4;
+			unsigned long FBR1L : 4;
+#endif
+	} BIT;
+	} FBR1;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FBR2 : 8;
+			unsigned long  : 24;
+#else
+			unsigned long  : 24;
+			unsigned long FBR2 : 8;
+#endif
+	} BIT;
+	} FBR2;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FBR3 : 16;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long FBR3 : 16;
+#endif
+	} BIT;
+	} FBR3;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FBR4 : 16;
+			unsigned long  : 16;
+#else
+			unsigned long  : 16;
+			unsigned long FBR4 : 16;
+#endif
+	} BIT;
+	} FBR4;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long FBR5 : 8;
+			unsigned long  : 24;
+#else
+			unsigned long  : 24;
+			unsigned long FBR5 : 8;
+#endif
+	} BIT;
+	} FBR5;
+	char           wk3[1404];
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned char HH;
+			unsigned char HL;
+			unsigned char LH;
+			unsigned char LL;
+		} BYTE;
+	} FN1DATAR1[64];
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned char HH;
+			unsigned char HL;
+			unsigned char LH;
+			unsigned char LL;
+		} BYTE;
+	} FN1DATAR2[64];
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned char HH;
+			unsigned char HL;
+			unsigned char LH;
+			unsigned char LL;
+		} BYTE;
+	} FN1DATAR3[64];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char INTVEC : 8;
+#else
+			unsigned char INTVEC : 8;
+#endif
+	} BIT;
+	} FN1INTVECR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char INTCTR : 8;
+#else
+			unsigned char INTCTR : 8;
+#endif
+	} BIT;
+	} FN1INTCLRR;
+	char           wk4[254];
+	union {
+		unsigned long LONG;
+		struct {
+			unsigned char HH;
+			unsigned char HL;
+			unsigned char LH;
+			unsigned char LL;
+		} BYTE;
+	} FN1DATAR5[256];
+} st_sdsi_t;
+
+typedef struct st_smci0 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKS : 2;
+			unsigned char BCP : 2;
+			unsigned char PM : 1;
+			unsigned char PE : 1;
+			unsigned char BLK : 1;
+			unsigned char GM : 1;
+#else
+			unsigned char GM : 1;
+			unsigned char BLK : 1;
+			unsigned char PE : 1;
+			unsigned char PM : 1;
+			unsigned char BCP : 2;
+			unsigned char CKS : 2;
+#endif
+	} BIT;
+	} SMR;
+	unsigned char  BRR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKE : 2;
+			unsigned char TEIE : 1;
+			unsigned char MPIE : 1;
+			unsigned char RE : 1;
+			unsigned char TE : 1;
+			unsigned char RIE : 1;
+			unsigned char TIE : 1;
+#else
+			unsigned char TIE : 1;
+			unsigned char RIE : 1;
+			unsigned char TE : 1;
+			unsigned char RE : 1;
+			unsigned char MPIE : 1;
+			unsigned char TEIE : 1;
+			unsigned char CKE : 2;
+#endif
+	} BIT;
+	} SCR;
+	unsigned char  TDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MPBT : 1;
+			unsigned char MPB : 1;
+			unsigned char TEND : 1;
+			unsigned char PER : 1;
+			unsigned char ERS : 1;
+			unsigned char ORER : 1;
+			unsigned char RDRF : 1;
+			unsigned char TDRE : 1;
+#else
+			unsigned char TDRE : 1;
+			unsigned char RDRF : 1;
+			unsigned char ORER : 1;
+			unsigned char ERS : 1;
+			unsigned char PER : 1;
+			unsigned char TEND : 1;
+			unsigned char MPB : 1;
+			unsigned char MPBT : 1;
+#endif
+	} BIT;
+	} SSR;
+	unsigned char  RDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SMIF : 1;
+			unsigned char  : 1;
+			unsigned char SINV : 1;
+			unsigned char SDIR : 1;
+			unsigned char CHR1 : 1;
+			unsigned char  : 2;
+			unsigned char BCP2 : 1;
+#else
+			unsigned char BCP2 : 1;
+			unsigned char  : 2;
+			unsigned char CHR1 : 1;
+			unsigned char SDIR : 1;
+			unsigned char SINV : 1;
+			unsigned char  : 1;
+			unsigned char SMIF : 1;
+#endif
+	} BIT;
+	} SCMR;
+} st_smci0_t;
+
+typedef struct st_smci10 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKS : 2;
+			unsigned char BCP : 2;
+			unsigned char PM : 1;
+			unsigned char PE : 1;
+			unsigned char BLK : 1;
+			unsigned char GM : 1;
+#else
+			unsigned char GM : 1;
+			unsigned char BLK : 1;
+			unsigned char PE : 1;
+			unsigned char PM : 1;
+			unsigned char BCP : 2;
+			unsigned char CKS : 2;
+#endif
+	} BIT;
+	} SMR;
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKE : 2;
+			unsigned char TEIE : 1;
+			unsigned char MPIE : 1;
+			unsigned char RE : 1;
+			unsigned char TE : 1;
+			unsigned char RIE : 1;
+			unsigned char TIE : 1;
+#else
+			unsigned char TIE : 1;
+			unsigned char RIE : 1;
+			unsigned char TE : 1;
+			unsigned char RE : 1;
+			unsigned char MPIE : 1;
+			unsigned char TEIE : 1;
+			unsigned char CKE : 2;
+#endif
+	} BIT;
+	} SCR;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MPBT : 1;
+			unsigned char MPB : 1;
+			unsigned char TEND : 1;
+			unsigned char PER : 1;
+			unsigned char ERS : 1;
+			unsigned char ORER : 1;
+			unsigned char RDRF : 1;
+			unsigned char TDRE : 1;
+#else
+			unsigned char TDRE : 1;
+			unsigned char RDRF : 1;
+			unsigned char ORER : 1;
+			unsigned char ERS : 1;
+			unsigned char PER : 1;
+			unsigned char TEND : 1;
+			unsigned char MPB : 1;
+			unsigned char MPBT : 1;
+#endif
+	} BIT;
+	} SSR;
+	char           wk2[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SMIF : 1;
+			unsigned char  : 1;
+			unsigned char SINV : 1;
+			unsigned char SDIR : 1;
+			unsigned char CHR1 : 1;
+			unsigned char  : 2;
+			unsigned char BCP2 : 1;
+#else
+			unsigned char BCP2 : 1;
+			unsigned char  : 2;
+			unsigned char CHR1 : 1;
+			unsigned char SDIR : 1;
+			unsigned char SINV : 1;
+			unsigned char  : 1;
+			unsigned char SMIF : 1;
+#endif
+	} BIT;
+	} SCMR;
+} st_smci10_t;
+
+typedef struct st_system {
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short MD : 1;
+			unsigned short  : 15;
+#else
+			unsigned short  : 15;
+			unsigned short MD : 1;
+#endif
+	} BIT;
+	} MDMONR;
+	char           wk0[4];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short ROME : 1;
+			unsigned short EXBE : 1;
+			unsigned short  : 6;
+			unsigned short KEY : 8;
+#else
+			unsigned short KEY : 8;
+			unsigned short  : 6;
+			unsigned short EXBE : 1;
+			unsigned short ROME : 1;
+#endif
+	} BIT;
+	} SYSCR0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RAME : 1;
+			unsigned short  : 6;
+			unsigned short SBYRAME : 1;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short SBYRAME : 1;
+			unsigned short  : 6;
+			unsigned short RAME : 1;
+#endif
+	} BIT;
+	} SYSCR1;
+	char           wk1[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 14;
+			unsigned short OPE : 1;
+			unsigned short SSBY : 1;
+#else
+			unsigned short SSBY : 1;
+			unsigned short OPE : 1;
+			unsigned short  : 14;
+#endif
+	} BIT;
+	} SBYCR;
+	char           wk2[2];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MSTPA0 : 1;
+			unsigned long MSTPA1 : 1;
+			unsigned long  : 2;
+			unsigned long MSTPA4 : 1;
+			unsigned long MSTPA5 : 1;
+			unsigned long  : 3;
+			unsigned long MSTPA9 : 1;
+			unsigned long MSTPA10 : 1;
+			unsigned long MSTPA11 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPA13 : 1;
+			unsigned long MSTPA14 : 1;
+			unsigned long MSTPA15 : 1;
+			unsigned long MSTPA16 : 1;
+			unsigned long MSTPA17 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPA19 : 1;
+			unsigned long  : 4;
+			unsigned long MSTPA24 : 1;
+			unsigned long  : 2;
+			unsigned long MSTPA27 : 1;
+			unsigned long MSTPA28 : 1;
+			unsigned long MSTPA29 : 1;
+			unsigned long  : 1;
+			unsigned long ACSE : 1;
+#else
+			unsigned long ACSE : 1;
+			unsigned long  : 1;
+			unsigned long MSTPA29 : 1;
+			unsigned long MSTPA28 : 1;
+			unsigned long MSTPA27 : 1;
+			unsigned long  : 2;
+			unsigned long MSTPA24 : 1;
+			unsigned long  : 4;
+			unsigned long MSTPA19 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPA17 : 1;
+			unsigned long MSTPA16 : 1;
+			unsigned long MSTPA15 : 1;
+			unsigned long MSTPA14 : 1;
+			unsigned long MSTPA13 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPA11 : 1;
+			unsigned long MSTPA10 : 1;
+			unsigned long MSTPA9 : 1;
+			unsigned long  : 3;
+			unsigned long MSTPA5 : 1;
+			unsigned long MSTPA4 : 1;
+			unsigned long  : 2;
+			unsigned long MSTPA1 : 1;
+			unsigned long MSTPA0 : 1;
+#endif
+	} BIT;
+	} MSTPCRA;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MSTPB0 : 1;
+			unsigned long MSTPB1 : 1;
+			unsigned long  : 2;
+			unsigned long MSTPB4 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPB6 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPB8 : 1;
+			unsigned long MSTPB9 : 1;
+			unsigned long  : 5;
+			unsigned long MSTPB15 : 1;
+			unsigned long MSTPB16 : 1;
+			unsigned long MSTPB17 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPB19 : 1;
+			unsigned long MSTPB20 : 1;
+			unsigned long MSTPB21 : 1;
+			unsigned long MSTPB22 : 1;
+			unsigned long MSTPB23 : 1;
+			unsigned long MSTPB24 : 1;
+			unsigned long MSTPB25 : 1;
+			unsigned long MSTPB26 : 1;
+			unsigned long MSTPB27 : 1;
+			unsigned long MSTPB28 : 1;
+			unsigned long MSTPB29 : 1;
+			unsigned long MSTPB30 : 1;
+			unsigned long MSTPB31 : 1;
+#else
+			unsigned long MSTPB31 : 1;
+			unsigned long MSTPB30 : 1;
+			unsigned long MSTPB29 : 1;
+			unsigned long MSTPB28 : 1;
+			unsigned long MSTPB27 : 1;
+			unsigned long MSTPB26 : 1;
+			unsigned long MSTPB25 : 1;
+			unsigned long MSTPB24 : 1;
+			unsigned long MSTPB23 : 1;
+			unsigned long MSTPB22 : 1;
+			unsigned long MSTPB21 : 1;
+			unsigned long MSTPB20 : 1;
+			unsigned long MSTPB19 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPB17 : 1;
+			unsigned long MSTPB16 : 1;
+			unsigned long MSTPB15 : 1;
+			unsigned long  : 5;
+			unsigned long MSTPB9 : 1;
+			unsigned long MSTPB8 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPB6 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPB4 : 1;
+			unsigned long  : 2;
+			unsigned long MSTPB1 : 1;
+			unsigned long MSTPB0 : 1;
+#endif
+	} BIT;
+	} MSTPCRB;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MSTPC0 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPC2 : 1;
+			unsigned long  : 4;
+			unsigned long MSTPC7 : 1;
+			unsigned long  : 9;
+			unsigned long MSTPC17 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPC19 : 1;
+			unsigned long  : 2;
+			unsigned long MSTPC22 : 1;
+			unsigned long MSTPC23 : 1;
+			unsigned long MSTPC24 : 1;
+			unsigned long MSTPC25 : 1;
+			unsigned long MSTPC26 : 1;
+			unsigned long MSTPC27 : 1;
+			unsigned long MSTPC28 : 1;
+			unsigned long MSTPC29 : 1;
+			unsigned long  : 2;
+#else
+			unsigned long  : 2;
+			unsigned long MSTPC29 : 1;
+			unsigned long MSTPC28 : 1;
+			unsigned long MSTPC27 : 1;
+			unsigned long MSTPC26 : 1;
+			unsigned long MSTPC25 : 1;
+			unsigned long MSTPC24 : 1;
+			unsigned long MSTPC23 : 1;
+			unsigned long MSTPC22 : 1;
+			unsigned long  : 2;
+			unsigned long MSTPC19 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPC17 : 1;
+			unsigned long  : 9;
+			unsigned long MSTPC7 : 1;
+			unsigned long  : 4;
+			unsigned long MSTPC2 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPC0 : 1;
+#endif
+	} BIT;
+	} MSTPCRC;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long MSTPD0 : 1;
+			unsigned long MSTPD1 : 1;
+			unsigned long MSTPD2 : 1;
+			unsigned long MSTPD3 : 1;
+			unsigned long MSTPD4 : 1;
+			unsigned long MSTPD5 : 1;
+			unsigned long MSTPD6 : 1;
+			unsigned long MSTPD7 : 1;
+			unsigned long  : 5;
+			unsigned long MSTPD13 : 1;
+			unsigned long  : 5;
+			unsigned long MSTPD19 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPD21 : 1;
+			unsigned long  : 5;
+			unsigned long MSTPD27 : 1;
+			unsigned long  : 4;
+#else
+			unsigned long  : 4;
+			unsigned long MSTPD27 : 1;
+			unsigned long  : 5;
+			unsigned long MSTPD21 : 1;
+			unsigned long  : 1;
+			unsigned long MSTPD19 : 1;
+			unsigned long  : 5;
+			unsigned long MSTPD13 : 1;
+			unsigned long  : 5;
+			unsigned long MSTPD7 : 1;
+			unsigned long MSTPD6 : 1;
+			unsigned long MSTPD5 : 1;
+			unsigned long MSTPD4 : 1;
+			unsigned long MSTPD3 : 1;
+			unsigned long MSTPD2 : 1;
+			unsigned long MSTPD1 : 1;
+			unsigned long MSTPD0 : 1;
+#endif
+	} BIT;
+	} MSTPCRD;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long PCKD : 4;
+			unsigned long PCKC : 4;
+			unsigned long PCKB : 4;
+			unsigned long PCKA : 4;
+			unsigned long BCK : 4;
+			unsigned long  : 2;
+			unsigned long PSTOP0 : 1;
+			unsigned long PSTOP1 : 1;
+			unsigned long ICK : 4;
+			unsigned long FCK : 4;
+#else
+			unsigned long FCK : 4;
+			unsigned long ICK : 4;
+			unsigned long PSTOP1 : 1;
+			unsigned long PSTOP0 : 1;
+			unsigned long  : 2;
+			unsigned long BCK : 4;
+			unsigned long PCKA : 4;
+			unsigned long PCKB : 4;
+			unsigned long PCKC : 4;
+			unsigned long PCKD : 4;
+#endif
+	} BIT;
+	} SCKCR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 4;
+			unsigned short UCK : 4;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short UCK : 4;
+			unsigned short  : 4;
+#endif
+	} BIT;
+	} SCKCR2;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 8;
+			unsigned short CKSEL : 3;
+			unsigned short  : 5;
+#else
+			unsigned short  : 5;
+			unsigned short CKSEL : 3;
+			unsigned short  : 8;
+#endif
+	} BIT;
+	} SCKCR3;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PLIDIV : 2;
+			unsigned short  : 2;
+			unsigned short PLLSRCSEL : 1;
+			unsigned short  : 3;
+			unsigned short STC : 6;
+			unsigned short  : 2;
+#else
+			unsigned short  : 2;
+			unsigned short STC : 6;
+			unsigned short  : 3;
+			unsigned short PLLSRCSEL : 1;
+			unsigned short  : 2;
+			unsigned short PLIDIV : 2;
+#endif
+	} BIT;
+	} PLLCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PLLEN : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char PLLEN : 1;
+#endif
+	} BIT;
+	} PLLCR2;
+	char           wk3[5];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char BCLKDIV : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char BCLKDIV : 1;
+#endif
+	} BIT;
+	} BCKCR;
+	char           wk4[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MOSTP : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char MOSTP : 1;
+#endif
+	} BIT;
+	} MOSCCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SOSTP : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char SOSTP : 1;
+#endif
+	} BIT;
+	} SOSCCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char LCSTP : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char LCSTP : 1;
+#endif
+	} BIT;
+	} LOCOCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ILCSTP : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char ILCSTP : 1;
+#endif
+	} BIT;
+	} ILOCOCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char HCSTP : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char HCSTP : 1;
+#endif
+	} BIT;
+	} HOCOCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char HCFRQ : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char HCFRQ : 2;
+#endif
+	} BIT;
+	} HOCOCR2;
+	char           wk5[4];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MOOVF : 1;
+			unsigned char SOOVF : 1;
+			unsigned char PLOVF : 1;
+			unsigned char HCOVF : 1;
+			unsigned char ILCOVF : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char ILCOVF : 1;
+			unsigned char HCOVF : 1;
+			unsigned char PLOVF : 1;
+			unsigned char SOOVF : 1;
+			unsigned char MOOVF : 1;
+#endif
+	} BIT;
+	} OSCOVFSR;
+	char           wk6[3];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OSTDIE : 1;
+			unsigned char  : 6;
+			unsigned char OSTDE : 1;
+#else
+			unsigned char OSTDE : 1;
+			unsigned char  : 6;
+			unsigned char OSTDIE : 1;
+#endif
+	} BIT;
+	} OSTDCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OSTDF : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char OSTDF : 1;
+#endif
+	} BIT;
+	} OSTDSR;
+	char           wk7[94];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OPCM : 3;
+			unsigned char  : 1;
+			unsigned char OPCMTSF : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char OPCMTSF : 1;
+			unsigned char  : 1;
+			unsigned char OPCM : 3;
+#endif
+	} BIT;
+	} OPCCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char RSTCKSEL : 3;
+			unsigned char  : 4;
+			unsigned char RSTCKEN : 1;
+#else
+			unsigned char RSTCKEN : 1;
+			unsigned char  : 4;
+			unsigned char RSTCKSEL : 3;
+#endif
+	} BIT;
+	} RSTCKCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MSTS : 8;
+#else
+			unsigned char MSTS : 8;
+#endif
+	} BIT;
+	} MOSCWTCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SSTS : 8;
+#else
+			unsigned char SSTS : 8;
+#endif
+	} BIT;
+	} SOSCWTCR;
+	char           wk8[28];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IWDTRF : 1;
+			unsigned char WDTRF : 1;
+			unsigned char SWRF : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char SWRF : 1;
+			unsigned char WDTRF : 1;
+			unsigned char IWDTRF : 1;
+#endif
+	} BIT;
+	} RSTSR2;
+	char           wk9[1];
+	unsigned short SWRR;
+	char           wk10[28];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char LVD1IDTSEL : 2;
+			unsigned char LVD1IRQSEL : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char LVD1IRQSEL : 1;
+			unsigned char LVD1IDTSEL : 2;
+#endif
+	} BIT;
+	} LVD1CR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char LVD1DET : 1;
+			unsigned char LVD1MON : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char LVD1MON : 1;
+			unsigned char LVD1DET : 1;
+#endif
+	} BIT;
+	} LVD1SR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char LVD2IDTSEL : 2;
+			unsigned char LVD2IRQSEL : 1;
+			unsigned char  : 5;
+#else
+			unsigned char  : 5;
+			unsigned char LVD2IRQSEL : 1;
+			unsigned char LVD2IDTSEL : 2;
+#endif
+	} BIT;
+	} LVD2CR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char LVD2DET : 1;
+			unsigned char LVD2MON : 1;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char LVD2MON : 1;
+			unsigned char LVD2DET : 1;
+#endif
+	} BIT;
+	} LVD2SR;
+	char           wk11[794];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PRC0 : 1;
+			unsigned short PRC1 : 1;
+			unsigned short  : 1;
+			unsigned short PRC3 : 1;
+			unsigned short  : 4;
+			unsigned short PRKEY : 8;
+#else
+			unsigned short PRKEY : 8;
+			unsigned short  : 4;
+			unsigned short PRC3 : 1;
+			unsigned short  : 1;
+			unsigned short PRC1 : 1;
+			unsigned short PRC0 : 1;
+#endif
+	} BIT;
+	} PRCR;
+	char           wk12[3100];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char ROMWT : 2;
+			unsigned char  : 6;
+#else
+			unsigned char  : 6;
+			unsigned char ROMWT : 2;
+#endif
+	} BIT;
+	} ROMWT;
+	char           wk13[45667];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DEEPCUT : 2;
+			unsigned char  : 4;
+			unsigned char IOKEEP : 1;
+			unsigned char DPSBY : 1;
+#else
+			unsigned char DPSBY : 1;
+			unsigned char IOKEEP : 1;
+			unsigned char  : 4;
+			unsigned char DEEPCUT : 2;
+#endif
+	} BIT;
+	} DPSBYCR;
+	char           wk14[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DIRQ0E : 1;
+			unsigned char DIRQ1E : 1;
+			unsigned char DIRQ2E : 1;
+			unsigned char DIRQ3E : 1;
+			unsigned char DIRQ4E : 1;
+			unsigned char DIRQ5E : 1;
+			unsigned char DIRQ6E : 1;
+			unsigned char DIRQ7E : 1;
+#else
+			unsigned char DIRQ7E : 1;
+			unsigned char DIRQ6E : 1;
+			unsigned char DIRQ5E : 1;
+			unsigned char DIRQ4E : 1;
+			unsigned char DIRQ3E : 1;
+			unsigned char DIRQ2E : 1;
+			unsigned char DIRQ1E : 1;
+			unsigned char DIRQ0E : 1;
+#endif
+	} BIT;
+	} DPSIER0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DIRQ8E : 1;
+			unsigned char DIRQ9E : 1;
+			unsigned char DIRQ10E : 1;
+			unsigned char DIRQ11E : 1;
+			unsigned char DIRQ12E : 1;
+			unsigned char DIRQ13E : 1;
+			unsigned char DIRQ14E : 1;
+			unsigned char DIRQ15E : 1;
+#else
+			unsigned char DIRQ15E : 1;
+			unsigned char DIRQ14E : 1;
+			unsigned char DIRQ13E : 1;
+			unsigned char DIRQ12E : 1;
+			unsigned char DIRQ11E : 1;
+			unsigned char DIRQ10E : 1;
+			unsigned char DIRQ9E : 1;
+			unsigned char DIRQ8E : 1;
+#endif
+	} BIT;
+	} DPSIER1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DLVD1IE : 1;
+			unsigned char DLVD2IE : 1;
+			unsigned char DRTCIIE : 1;
+			unsigned char DRTCAIE : 1;
+			unsigned char DNMIE : 1;
+			unsigned char DRIICDIE : 1;
+			unsigned char DRIICCIE : 1;
+			unsigned char DUSBIE : 1;
+#else
+			unsigned char DUSBIE : 1;
+			unsigned char DRIICCIE : 1;
+			unsigned char DRIICDIE : 1;
+			unsigned char DNMIE : 1;
+			unsigned char DRTCAIE : 1;
+			unsigned char DRTCIIE : 1;
+			unsigned char DLVD2IE : 1;
+			unsigned char DLVD1IE : 1;
+#endif
+	} BIT;
+	} DPSIER2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DCANIE : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DCANIE : 1;
+#endif
+	} BIT;
+	} DPSIER3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DIRQ0F : 1;
+			unsigned char DIRQ1F : 1;
+			unsigned char DIRQ2F : 1;
+			unsigned char DIRQ3F : 1;
+			unsigned char DIRQ4F : 1;
+			unsigned char DIRQ5F : 1;
+			unsigned char DIRQ6F : 1;
+			unsigned char DIRQ7F : 1;
+#else
+			unsigned char DIRQ7F : 1;
+			unsigned char DIRQ6F : 1;
+			unsigned char DIRQ5F : 1;
+			unsigned char DIRQ4F : 1;
+			unsigned char DIRQ3F : 1;
+			unsigned char DIRQ2F : 1;
+			unsigned char DIRQ1F : 1;
+			unsigned char DIRQ0F : 1;
+#endif
+	} BIT;
+	} DPSIFR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DIRQ8F : 1;
+			unsigned char DIRQ9F : 1;
+			unsigned char DIRQ10F : 1;
+			unsigned char DIRQ11F : 1;
+			unsigned char DIRQ12F : 1;
+			unsigned char DIRQ13F : 1;
+			unsigned char DIRQ14F : 1;
+			unsigned char DIRQ15F : 1;
+#else
+			unsigned char DIRQ15F : 1;
+			unsigned char DIRQ14F : 1;
+			unsigned char DIRQ13F : 1;
+			unsigned char DIRQ12F : 1;
+			unsigned char DIRQ11F : 1;
+			unsigned char DIRQ10F : 1;
+			unsigned char DIRQ9F : 1;
+			unsigned char DIRQ8F : 1;
+#endif
+	} BIT;
+	} DPSIFR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DLVD1IF : 1;
+			unsigned char DLVD2IF : 1;
+			unsigned char DRTCIIF : 1;
+			unsigned char DRTCAIF : 1;
+			unsigned char DNMIF : 1;
+			unsigned char DRIICDIF : 1;
+			unsigned char DRIICCIF : 1;
+			unsigned char DUSBIF : 1;
+#else
+			unsigned char DUSBIF : 1;
+			unsigned char DRIICCIF : 1;
+			unsigned char DRIICDIF : 1;
+			unsigned char DNMIF : 1;
+			unsigned char DRTCAIF : 1;
+			unsigned char DRTCIIF : 1;
+			unsigned char DLVD2IF : 1;
+			unsigned char DLVD1IF : 1;
+#endif
+	} BIT;
+	} DPSIFR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DCANIF : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DCANIF : 1;
+#endif
+	} BIT;
+	} DPSIFR3;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DIRQ0EG : 1;
+			unsigned char DIRQ1EG : 1;
+			unsigned char DIRQ2EG : 1;
+			unsigned char DIRQ3EG : 1;
+			unsigned char DIRQ4EG : 1;
+			unsigned char DIRQ5EG : 1;
+			unsigned char DIRQ6EG : 1;
+			unsigned char DIRQ7EG : 1;
+#else
+			unsigned char DIRQ7EG : 1;
+			unsigned char DIRQ6EG : 1;
+			unsigned char DIRQ5EG : 1;
+			unsigned char DIRQ4EG : 1;
+			unsigned char DIRQ3EG : 1;
+			unsigned char DIRQ2EG : 1;
+			unsigned char DIRQ1EG : 1;
+			unsigned char DIRQ0EG : 1;
+#endif
+	} BIT;
+	} DPSIEGR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DIRQ8EG : 1;
+			unsigned char DIRQ9EG : 1;
+			unsigned char DIRQ10EG : 1;
+			unsigned char DIRQ11EG : 1;
+			unsigned char DIRQ12EG : 1;
+			unsigned char DIRQ13EG : 1;
+			unsigned char DIRQ14EG : 1;
+			unsigned char DIRQ15EG : 1;
+#else
+			unsigned char DIRQ15EG : 1;
+			unsigned char DIRQ14EG : 1;
+			unsigned char DIRQ13EG : 1;
+			unsigned char DIRQ12EG : 1;
+			unsigned char DIRQ11EG : 1;
+			unsigned char DIRQ10EG : 1;
+			unsigned char DIRQ9EG : 1;
+			unsigned char DIRQ8EG : 1;
+#endif
+	} BIT;
+	} DPSIEGR1;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DLVD1EG : 1;
+			unsigned char DLVD2EG : 1;
+			unsigned char  : 2;
+			unsigned char DNMIEG : 1;
+			unsigned char DRIICDEG : 1;
+			unsigned char DRIICCEG : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char DRIICCEG : 1;
+			unsigned char DRIICDEG : 1;
+			unsigned char DNMIEG : 1;
+			unsigned char  : 2;
+			unsigned char DLVD2EG : 1;
+			unsigned char DLVD1EG : 1;
+#endif
+	} BIT;
+	} DPSIEGR2;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char DCANIEG : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char DCANIEG : 1;
+#endif
+	} BIT;
+	} DPSIEGR3;
+	char           wk15[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char PORF : 1;
+			unsigned char LVD0RF : 1;
+			unsigned char LVD1RF : 1;
+			unsigned char LVD2RF : 1;
+			unsigned char  : 3;
+			unsigned char DPSRSTF : 1;
+#else
+			unsigned char DPSRSTF : 1;
+			unsigned char  : 3;
+			unsigned char LVD2RF : 1;
+			unsigned char LVD1RF : 1;
+			unsigned char LVD0RF : 1;
+			unsigned char PORF : 1;
+#endif
+	} BIT;
+	} RSTSR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CWSF : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char CWSF : 1;
+#endif
+	} BIT;
+	} RSTSR1;
+	char           wk16[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MOFXIN : 1;
+			unsigned char  : 3;
+			unsigned char MODRV2 : 2;
+			unsigned char MOSEL : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char MOSEL : 1;
+			unsigned char MODRV2 : 2;
+			unsigned char  : 3;
+			unsigned char MOFXIN : 1;
+#endif
+	} BIT;
+	} MOFCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char HOCOPCNT : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char HOCOPCNT : 1;
+#endif
+	} BIT;
+	} HOCOPCR;
+	char           wk17[2];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 5;
+			unsigned char LVD1E : 1;
+			unsigned char LVD2E : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char LVD2E : 1;
+			unsigned char LVD1E : 1;
+			unsigned char  : 5;
+#endif
+	} BIT;
+	} LVCMPCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char LVD1LVL : 4;
+			unsigned char LVD2LVL : 4;
+#else
+			unsigned char LVD2LVL : 4;
+			unsigned char LVD1LVL : 4;
+#endif
+	} BIT;
+	} LVDLVLR;
+	char           wk18[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char LVD1RIE : 1;
+			unsigned char LVD1DFDIS : 1;
+			unsigned char LVD1CMPE : 1;
+			unsigned char  : 1;
+			unsigned char LVD1FSAMP : 2;
+			unsigned char LVD1RI : 1;
+			unsigned char LVD1RN : 1;
+#else
+			unsigned char LVD1RN : 1;
+			unsigned char LVD1RI : 1;
+			unsigned char LVD1FSAMP : 2;
+			unsigned char  : 1;
+			unsigned char LVD1CMPE : 1;
+			unsigned char LVD1DFDIS : 1;
+			unsigned char LVD1RIE : 1;
+#endif
+	} BIT;
+	} LVD1CR0;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char LVD2RIE : 1;
+			unsigned char LVD2DFDIS : 1;
+			unsigned char LVD2CMPE : 1;
+			unsigned char  : 1;
+			unsigned char LVD2FSAMP : 2;
+			unsigned char LVD2RI : 1;
+			unsigned char LVD2RN : 1;
+#else
+			unsigned char LVD2RN : 1;
+			unsigned char LVD2RI : 1;
+			unsigned char LVD2FSAMP : 2;
+			unsigned char  : 1;
+			unsigned char LVD2CMPE : 1;
+			unsigned char LVD2DFDIS : 1;
+			unsigned char LVD2RIE : 1;
+#endif
+	} BIT;
+	} LVD2CR0;
+	char           wk19[4];
+	unsigned char  DPSBKR[32];
+} st_system_t;
+
+typedef struct st_temps {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 4;
+			unsigned char TSOE : 1;
+			unsigned char  : 2;
+			unsigned char TSEN : 1;
+#else
+			unsigned char TSEN : 1;
+			unsigned char  : 2;
+			unsigned char TSOE : 1;
+			unsigned char  : 4;
+#endif
+	} BIT;
+	} TSCR;
+} st_temps_t;
+
+typedef struct st_tmr0 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 3;
+			unsigned char CCLR : 2;
+			unsigned char OVIE : 1;
+			unsigned char CMIEA : 1;
+			unsigned char CMIEB : 1;
+#else
+			unsigned char CMIEB : 1;
+			unsigned char CMIEA : 1;
+			unsigned char OVIE : 1;
+			unsigned char CCLR : 2;
+			unsigned char  : 3;
+#endif
+	} BIT;
+	} TCR;
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OSA : 2;
+			unsigned char OSB : 2;
+			unsigned char ADTE : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char ADTE : 1;
+			unsigned char OSB : 2;
+			unsigned char OSA : 2;
+#endif
+	} BIT;
+	} TCSR;
+	char           wk1[1];
+	unsigned char  TCORA;
+	char           wk2[1];
+	unsigned char  TCORB;
+	char           wk3[1];
+	unsigned char  TCNT;
+	char           wk4[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKS : 3;
+			unsigned char CSS : 2;
+			unsigned char  : 2;
+			unsigned char TMRIS : 1;
+#else
+			unsigned char TMRIS : 1;
+			unsigned char  : 2;
+			unsigned char CSS : 2;
+			unsigned char CKS : 3;
+#endif
+	} BIT;
+	} TCCR;
+	char           wk5[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TCS : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char TCS : 1;
+#endif
+	} BIT;
+	} TCSTR;
+} st_tmr0_t;
+
+typedef struct st_tmr1 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 3;
+			unsigned char CCLR : 2;
+			unsigned char OVIE : 1;
+			unsigned char CMIEA : 1;
+			unsigned char CMIEB : 1;
+#else
+			unsigned char CMIEB : 1;
+			unsigned char CMIEA : 1;
+			unsigned char OVIE : 1;
+			unsigned char CCLR : 2;
+			unsigned char  : 3;
+#endif
+	} BIT;
+	} TCR;
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char OSA : 2;
+			unsigned char OSB : 2;
+			unsigned char  : 4;
+#else
+			unsigned char  : 4;
+			unsigned char OSB : 2;
+			unsigned char OSA : 2;
+#endif
+	} BIT;
+	} TCSR;
+	char           wk1[1];
+	unsigned char  TCORA;
+	char           wk2[1];
+	unsigned char  TCORB;
+	char           wk3[1];
+	unsigned char  TCNT;
+	char           wk4[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CKS : 3;
+			unsigned char CSS : 2;
+			unsigned char  : 2;
+			unsigned char TMRIS : 1;
+#else
+			unsigned char TMRIS : 1;
+			unsigned char  : 2;
+			unsigned char CSS : 2;
+			unsigned char CKS : 3;
+#endif
+	} BIT;
+	} TCCR;
+	char           wk5[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TCS : 1;
+			unsigned char  : 7;
+#else
+			unsigned char  : 7;
+			unsigned char TCS : 1;
+#endif
+	} BIT;
+	} TCSTR;
+} st_tmr1_t;
+
+typedef struct st_tmr01 {
+	unsigned short TCORA;
+	unsigned short TCORB;
+	unsigned short TCNT;
+	unsigned short TCCR;
+} st_tmr01_t;
+
+typedef struct st_tpu0 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR;
+	char           wk0[7];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 3;
+#else
+			unsigned char CCLR : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char BFA : 1;
+			unsigned char BFB : 1;
+			unsigned char ICSELB : 1;
+			unsigned char ICSELD : 1;
+#else
+			unsigned char ICSELD : 1;
+			unsigned char ICSELB : 1;
+			unsigned char BFB : 1;
+			unsigned char BFA : 1;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIORH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 4;
+			unsigned char IOD : 4;
+#else
+			unsigned char IOD : 4;
+			unsigned char IOC : 4;
+#endif
+	} BIT;
+	} TIORL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIED : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TGIED : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGFA : 1;
+			unsigned char TGFB : 1;
+			unsigned char TGFC : 1;
+			unsigned char TGFD : 1;
+			unsigned char TCFV : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char TCFV : 1;
+			unsigned char TGFD : 1;
+			unsigned char TGFC : 1;
+			unsigned char TGFB : 1;
+			unsigned char TGFA : 1;
+#endif
+	} BIT;
+	} TSR;
+	unsigned short TCNT;
+	unsigned short TGRA;
+	unsigned short TGRB;
+	unsigned short TGRC;
+	unsigned short TGRD;
+} st_tpu0_t;
+
+typedef struct st_tpu1 {
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR;
+	char           wk1[22];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 2;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char CCLR : 2;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char  : 2;
+			unsigned char ICSELB : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ICSELB : 1;
+			unsigned char  : 2;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIOR;
+	char           wk2[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TCIEU : 1;
+			unsigned char  : 1;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char  : 1;
+			unsigned char TCIEU : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGFA : 1;
+			unsigned char TGFB : 1;
+			unsigned char  : 2;
+			unsigned char TCFV : 1;
+			unsigned char TCFU : 1;
+			unsigned char  : 1;
+			unsigned char TCFD : 1;
+#else
+			unsigned char TCFD : 1;
+			unsigned char  : 1;
+			unsigned char TCFU : 1;
+			unsigned char TCFV : 1;
+			unsigned char  : 2;
+			unsigned char TGFB : 1;
+			unsigned char TGFA : 1;
+#endif
+	} BIT;
+	} TSR;
+	unsigned short TCNT;
+	unsigned short TGRA;
+	unsigned short TGRB;
+} st_tpu1_t;
+
+typedef struct st_tpu2 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR;
+	char           wk0[37];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 2;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char CCLR : 2;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char  : 2;
+			unsigned char ICSELB : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ICSELB : 1;
+			unsigned char  : 2;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIOR;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TCIEU : 1;
+			unsigned char  : 1;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char  : 1;
+			unsigned char TCIEU : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGFA : 1;
+			unsigned char TGFB : 1;
+			unsigned char  : 2;
+			unsigned char TCFV : 1;
+			unsigned char TCFU : 1;
+			unsigned char  : 1;
+			unsigned char TCFD : 1;
+#else
+			unsigned char TCFD : 1;
+			unsigned char  : 1;
+			unsigned char TCFU : 1;
+			unsigned char TCFV : 1;
+			unsigned char  : 2;
+			unsigned char TGFB : 1;
+			unsigned char TGFA : 1;
+#endif
+	} BIT;
+	} TSR;
+	unsigned short TCNT;
+	unsigned short TGRA;
+	unsigned short TGRB;
+} st_tpu2_t;
+
+typedef struct st_tpu3 {
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFDEN : 1;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char NFDEN : 1;
+			unsigned char NFCEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR;
+	char           wk1[52];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 3;
+#else
+			unsigned char CCLR : 3;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char BFA : 1;
+			unsigned char BFB : 1;
+			unsigned char ICSELB : 1;
+			unsigned char ICSELD : 1;
+#else
+			unsigned char ICSELD : 1;
+			unsigned char ICSELB : 1;
+			unsigned char BFB : 1;
+			unsigned char BFA : 1;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIORH;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOC : 4;
+			unsigned char IOD : 4;
+#else
+			unsigned char IOD : 4;
+			unsigned char IOC : 4;
+#endif
+	} BIT;
+	} TIORL;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIED : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TGIED : 1;
+			unsigned char TGIEC : 1;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGFA : 1;
+			unsigned char TGFB : 1;
+			unsigned char TGFC : 1;
+			unsigned char TGFD : 1;
+			unsigned char TCFV : 1;
+			unsigned char  : 3;
+#else
+			unsigned char  : 3;
+			unsigned char TCFV : 1;
+			unsigned char TGFD : 1;
+			unsigned char TGFC : 1;
+			unsigned char TGFB : 1;
+			unsigned char TGFA : 1;
+#endif
+	} BIT;
+	} TSR;
+	unsigned short TCNT;
+	unsigned short TGRA;
+	unsigned short TGRB;
+	unsigned short TGRC;
+	unsigned short TGRD;
+} st_tpu3_t;
+
+typedef struct st_tpu4 {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR;
+	char           wk0[67];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 2;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char CCLR : 2;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char  : 2;
+			unsigned char ICSELB : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ICSELB : 1;
+			unsigned char  : 2;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIOR;
+	char           wk1[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TCIEU : 1;
+			unsigned char  : 1;
+			unsigned char TTGE : 1;
+#else
+			unsigned char TTGE : 1;
+			unsigned char  : 1;
+			unsigned char TCIEU : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGFA : 1;
+			unsigned char TGFB : 1;
+			unsigned char  : 2;
+			unsigned char TCFV : 1;
+			unsigned char TCFU : 1;
+			unsigned char  : 1;
+			unsigned char TCFD : 1;
+#else
+			unsigned char TCFD : 1;
+			unsigned char  : 1;
+			unsigned char TCFU : 1;
+			unsigned char TCFV : 1;
+			unsigned char  : 2;
+			unsigned char TGFB : 1;
+			unsigned char TGFA : 1;
+#endif
+	} BIT;
+	} TSR;
+	unsigned short TCNT;
+	unsigned short TGRA;
+	unsigned short TGRB;
+} st_tpu4_t;
+
+typedef struct st_tpu5 {
+	char           wk0[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char NFAEN : 1;
+			unsigned char NFBEN : 1;
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char NFCS : 2;
+			unsigned char  : 2;
+			unsigned char NFBEN : 1;
+			unsigned char NFAEN : 1;
+#endif
+	} BIT;
+	} NFCR;
+	char           wk1[82];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TPSC : 3;
+			unsigned char CKEG : 2;
+			unsigned char CCLR : 2;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char CCLR : 2;
+			unsigned char CKEG : 2;
+			unsigned char TPSC : 3;
+#endif
+	} BIT;
+	} TCR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char MD : 4;
+			unsigned char  : 2;
+			unsigned char ICSELB : 1;
+			unsigned char  : 1;
+#else
+			unsigned char  : 1;
+			unsigned char ICSELB : 1;
+			unsigned char  : 2;
+			unsigned char MD : 4;
+#endif
+	} BIT;
+	} TMDR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char IOA : 4;
+			unsigned char IOB : 4;
+#else
+			unsigned char IOB : 4;
+			unsigned char IOA : 4;
+#endif
+	} BIT;
+	} TIOR;
+	char           wk2[1];
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGIEA : 1;
+			unsigned char TGIEB : 1;
+			unsigned char  : 2;
+			unsigned char TCIEV : 1;
+			unsigned char TCIEU : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char TCIEU : 1;
+			unsigned char TCIEV : 1;
+			unsigned char  : 2;
+			unsigned char TGIEB : 1;
+			unsigned char TGIEA : 1;
+#endif
+	} BIT;
+	} TIER;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char TGFA : 1;
+			unsigned char TGFB : 1;
+			unsigned char  : 2;
+			unsigned char TCFV : 1;
+			unsigned char TCFU : 1;
+			unsigned char  : 1;
+			unsigned char TCFD : 1;
+#else
+			unsigned char TCFD : 1;
+			unsigned char  : 1;
+			unsigned char TCFU : 1;
+			unsigned char TCFV : 1;
+			unsigned char  : 2;
+			unsigned char TGFB : 1;
+			unsigned char TGFA : 1;
+#endif
+	} BIT;
+	} TSR;
+	unsigned short TCNT;
+	unsigned short TGRA;
+	unsigned short TGRB;
+} st_tpu5_t;
+
+typedef struct st_tpua {
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char CST0 : 1;
+			unsigned char CST1 : 1;
+			unsigned char CST2 : 1;
+			unsigned char CST3 : 1;
+			unsigned char CST4 : 1;
+			unsigned char CST5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char CST5 : 1;
+			unsigned char CST4 : 1;
+			unsigned char CST3 : 1;
+			unsigned char CST2 : 1;
+			unsigned char CST1 : 1;
+			unsigned char CST0 : 1;
+#endif
+	} BIT;
+	} TSTR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char SYNC0 : 1;
+			unsigned char SYNC1 : 1;
+			unsigned char SYNC2 : 1;
+			unsigned char SYNC3 : 1;
+			unsigned char SYNC4 : 1;
+			unsigned char SYNC5 : 1;
+			unsigned char  : 2;
+#else
+			unsigned char  : 2;
+			unsigned char SYNC5 : 1;
+			unsigned char SYNC4 : 1;
+			unsigned char SYNC3 : 1;
+			unsigned char SYNC2 : 1;
+			unsigned char SYNC1 : 1;
+			unsigned char SYNC0 : 1;
+#endif
+	} BIT;
+	} TSYR;
+} st_tpua_t;
+
+typedef struct st_usb {
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long SRPC0 : 1;
+			unsigned long RPUE0 : 1;
+			unsigned long  : 1;
+			unsigned long DRPD0 : 1;
+			unsigned long FIXPHY0 : 1;
+			unsigned long  : 11;
+			unsigned long DP0 : 1;
+			unsigned long DM0 : 1;
+			unsigned long  : 2;
+			unsigned long DOVCA0 : 1;
+			unsigned long DOVCB0 : 1;
+			unsigned long  : 1;
+			unsigned long DVBSTS0 : 1;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long DVBSTS0 : 1;
+			unsigned long  : 1;
+			unsigned long DOVCB0 : 1;
+			unsigned long DOVCA0 : 1;
+			unsigned long  : 2;
+			unsigned long DM0 : 1;
+			unsigned long DP0 : 1;
+			unsigned long  : 11;
+			unsigned long FIXPHY0 : 1;
+			unsigned long DRPD0 : 1;
+			unsigned long  : 1;
+			unsigned long RPUE0 : 1;
+			unsigned long SRPC0 : 1;
+#endif
+	} BIT;
+	} DPUSR0R;
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long DPINTE0 : 1;
+			unsigned long DMINTE0 : 1;
+			unsigned long  : 2;
+			unsigned long DOVRCRAE0 : 1;
+			unsigned long DOVRCRBE0 : 1;
+			unsigned long  : 1;
+			unsigned long DVBSE0 : 1;
+			unsigned long  : 8;
+			unsigned long DPINT0 : 1;
+			unsigned long DMINT0 : 1;
+			unsigned long  : 2;
+			unsigned long DOVRCRA0 : 1;
+			unsigned long DOVRCRB0 : 1;
+			unsigned long  : 1;
+			unsigned long DVBINT0 : 1;
+			unsigned long  : 8;
+#else
+			unsigned long  : 8;
+			unsigned long DVBINT0 : 1;
+			unsigned long  : 1;
+			unsigned long DOVRCRB0 : 1;
+			unsigned long DOVRCRA0 : 1;
+			unsigned long  : 2;
+			unsigned long DMINT0 : 1;
+			unsigned long DPINT0 : 1;
+			unsigned long  : 8;
+			unsigned long DVBSE0 : 1;
+			unsigned long  : 1;
+			unsigned long DOVRCRBE0 : 1;
+			unsigned long DOVRCRAE0 : 1;
+			unsigned long  : 2;
+			unsigned long DMINTE0 : 1;
+			unsigned long DPINTE0 : 1;
+#endif
+	} BIT;
+	} DPUSR1R;
+} st_usb_t;
+
+typedef struct st_usb0 {
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short USBE : 1;
+			unsigned short  : 3;
+			unsigned short DPRPU : 1;
+			unsigned short DRPD : 1;
+			unsigned short DCFM : 1;
+			unsigned short  : 3;
+			unsigned short SCKE : 1;
+			unsigned short  : 5;
+#else
+			unsigned short  : 5;
+			unsigned short SCKE : 1;
+			unsigned short  : 3;
+			unsigned short DCFM : 1;
+			unsigned short DRPD : 1;
+			unsigned short DPRPU : 1;
+			unsigned short  : 3;
+			unsigned short USBE : 1;
+#endif
+	} BIT;
+	} SYSCFG;
+	char           wk0[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short LNST : 2;
+			unsigned short IDMON : 1;
+			unsigned short  : 2;
+			unsigned short SOFEA : 1;
+			unsigned short HTACT : 1;
+			unsigned short  : 7;
+			unsigned short OVCMON : 2;
+#else
+			unsigned short OVCMON : 2;
+			unsigned short  : 7;
+			unsigned short HTACT : 1;
+			unsigned short SOFEA : 1;
+			unsigned short  : 2;
+			unsigned short IDMON : 1;
+			unsigned short LNST : 2;
+#endif
+	} BIT;
+	} SYSSTS0;
+	char           wk1[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short RHST : 3;
+			unsigned short  : 1;
+			unsigned short UACT : 1;
+			unsigned short RESUME : 1;
+			unsigned short USBRST : 1;
+			unsigned short RWUPE : 1;
+			unsigned short WKUP : 1;
+			unsigned short VBUSEN : 1;
+			unsigned short EXICEN : 1;
+			unsigned short HNPBTOA : 1;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short HNPBTOA : 1;
+			unsigned short EXICEN : 1;
+			unsigned short VBUSEN : 1;
+			unsigned short WKUP : 1;
+			unsigned short RWUPE : 1;
+			unsigned short USBRST : 1;
+			unsigned short RESUME : 1;
+			unsigned short UACT : 1;
+			unsigned short  : 1;
+			unsigned short RHST : 3;
+#endif
+	} BIT;
+	} DVSTCTR0;
+	char           wk2[10];
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char L;
+			unsigned char H;
+		} BYTE;
+	} CFIFO;
+	char           wk3[2];
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char L;
+			unsigned char H;
+		} BYTE;
+	} D0FIFO;
+	char           wk4[2];
+	union {
+		unsigned short WORD;
+		struct {
+			unsigned char L;
+			unsigned char H;
+		} BYTE;
+	} D1FIFO;
+	char           wk5[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CURPIPE : 4;
+			unsigned short  : 1;
+			unsigned short ISEL : 1;
+			unsigned short  : 2;
+			unsigned short BIGEND : 1;
+			unsigned short  : 1;
+			unsigned short MBW : 1;
+			unsigned short  : 3;
+			unsigned short REW : 1;
+			unsigned short RCNT : 1;
+#else
+			unsigned short RCNT : 1;
+			unsigned short REW : 1;
+			unsigned short  : 3;
+			unsigned short MBW : 1;
+			unsigned short  : 1;
+			unsigned short BIGEND : 1;
+			unsigned short  : 2;
+			unsigned short ISEL : 1;
+			unsigned short  : 1;
+			unsigned short CURPIPE : 4;
+#endif
+	} BIT;
+	} CFIFOSEL;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DTLN : 9;
+			unsigned short  : 4;
+			unsigned short FRDY : 1;
+			unsigned short BCLR : 1;
+			unsigned short BVAL : 1;
+#else
+			unsigned short BVAL : 1;
+			unsigned short BCLR : 1;
+			unsigned short FRDY : 1;
+			unsigned short  : 4;
+			unsigned short DTLN : 9;
+#endif
+	} BIT;
+	} CFIFOCTR;
+	char           wk6[4];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CURPIPE : 4;
+			unsigned short  : 4;
+			unsigned short BIGEND : 1;
+			unsigned short  : 1;
+			unsigned short MBW : 1;
+			unsigned short  : 1;
+			unsigned short DREQE : 1;
+			unsigned short DCLRM : 1;
+			unsigned short REW : 1;
+			unsigned short RCNT : 1;
+#else
+			unsigned short RCNT : 1;
+			unsigned short REW : 1;
+			unsigned short DCLRM : 1;
+			unsigned short DREQE : 1;
+			unsigned short  : 1;
+			unsigned short MBW : 1;
+			unsigned short  : 1;
+			unsigned short BIGEND : 1;
+			unsigned short  : 4;
+			unsigned short CURPIPE : 4;
+#endif
+	} BIT;
+	} D0FIFOSEL;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DTLN : 9;
+			unsigned short  : 4;
+			unsigned short FRDY : 1;
+			unsigned short BCLR : 1;
+			unsigned short BVAL : 1;
+#else
+			unsigned short BVAL : 1;
+			unsigned short BCLR : 1;
+			unsigned short FRDY : 1;
+			unsigned short  : 4;
+			unsigned short DTLN : 9;
+#endif
+	} BIT;
+	} D0FIFOCTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CURPIPE : 4;
+			unsigned short  : 4;
+			unsigned short BIGEND : 1;
+			unsigned short  : 1;
+			unsigned short MBW : 1;
+			unsigned short  : 1;
+			unsigned short DREQE : 1;
+			unsigned short DCLRM : 1;
+			unsigned short REW : 1;
+			unsigned short RCNT : 1;
+#else
+			unsigned short RCNT : 1;
+			unsigned short REW : 1;
+			unsigned short DCLRM : 1;
+			unsigned short DREQE : 1;
+			unsigned short  : 1;
+			unsigned short MBW : 1;
+			unsigned short  : 1;
+			unsigned short BIGEND : 1;
+			unsigned short  : 4;
+			unsigned short CURPIPE : 4;
+#endif
+	} BIT;
+	} D1FIFOSEL;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short DTLN : 9;
+			unsigned short  : 4;
+			unsigned short FRDY : 1;
+			unsigned short BCLR : 1;
+			unsigned short BVAL : 1;
+#else
+			unsigned short BVAL : 1;
+			unsigned short BCLR : 1;
+			unsigned short FRDY : 1;
+			unsigned short  : 4;
+			unsigned short DTLN : 9;
+#endif
+	} BIT;
+	} D1FIFOCTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 8;
+			unsigned short BRDYE : 1;
+			unsigned short NRDYE : 1;
+			unsigned short BEMPE : 1;
+			unsigned short CTRE : 1;
+			unsigned short DVSE : 1;
+			unsigned short SOFE : 1;
+			unsigned short RSME : 1;
+			unsigned short VBSE : 1;
+#else
+			unsigned short VBSE : 1;
+			unsigned short RSME : 1;
+			unsigned short SOFE : 1;
+			unsigned short DVSE : 1;
+			unsigned short CTRE : 1;
+			unsigned short BEMPE : 1;
+			unsigned short NRDYE : 1;
+			unsigned short BRDYE : 1;
+			unsigned short  : 8;
+#endif
+	} BIT;
+	} INTENB0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 4;
+			unsigned short SACKE : 1;
+			unsigned short SIGNE : 1;
+			unsigned short EOFERRE : 1;
+			unsigned short  : 4;
+			unsigned short ATTCHE : 1;
+			unsigned short DTCHE : 1;
+			unsigned short  : 1;
+			unsigned short BCHGE : 1;
+			unsigned short OVRCRE : 1;
+#else
+			unsigned short OVRCRE : 1;
+			unsigned short BCHGE : 1;
+			unsigned short  : 1;
+			unsigned short DTCHE : 1;
+			unsigned short ATTCHE : 1;
+			unsigned short  : 4;
+			unsigned short EOFERRE : 1;
+			unsigned short SIGNE : 1;
+			unsigned short SACKE : 1;
+			unsigned short  : 4;
+#endif
+	} BIT;
+	} INTENB1;
+	char           wk7[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PIPE0BRDYE : 1;
+			unsigned short PIPE1BRDYE : 1;
+			unsigned short PIPE2BRDYE : 1;
+			unsigned short PIPE3BRDYE : 1;
+			unsigned short PIPE4BRDYE : 1;
+			unsigned short PIPE5BRDYE : 1;
+			unsigned short PIPE6BRDYE : 1;
+			unsigned short PIPE7BRDYE : 1;
+			unsigned short PIPE8BRDYE : 1;
+			unsigned short PIPE9BRDYE : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short PIPE9BRDYE : 1;
+			unsigned short PIPE8BRDYE : 1;
+			unsigned short PIPE7BRDYE : 1;
+			unsigned short PIPE6BRDYE : 1;
+			unsigned short PIPE5BRDYE : 1;
+			unsigned short PIPE4BRDYE : 1;
+			unsigned short PIPE3BRDYE : 1;
+			unsigned short PIPE2BRDYE : 1;
+			unsigned short PIPE1BRDYE : 1;
+			unsigned short PIPE0BRDYE : 1;
+#endif
+	} BIT;
+	} BRDYENB;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PIPE0NRDYE : 1;
+			unsigned short PIPE1NRDYE : 1;
+			unsigned short PIPE2NRDYE : 1;
+			unsigned short PIPE3NRDYE : 1;
+			unsigned short PIPE4NRDYE : 1;
+			unsigned short PIPE5NRDYE : 1;
+			unsigned short PIPE6NRDYE : 1;
+			unsigned short PIPE7NRDYE : 1;
+			unsigned short PIPE8NRDYE : 1;
+			unsigned short PIPE9NRDYE : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short PIPE9NRDYE : 1;
+			unsigned short PIPE8NRDYE : 1;
+			unsigned short PIPE7NRDYE : 1;
+			unsigned short PIPE6NRDYE : 1;
+			unsigned short PIPE5NRDYE : 1;
+			unsigned short PIPE4NRDYE : 1;
+			unsigned short PIPE3NRDYE : 1;
+			unsigned short PIPE2NRDYE : 1;
+			unsigned short PIPE1NRDYE : 1;
+			unsigned short PIPE0NRDYE : 1;
+#endif
+	} BIT;
+	} NRDYENB;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PIPE0BEMPE : 1;
+			unsigned short PIPE1BEMPE : 1;
+			unsigned short PIPE2BEMPE : 1;
+			unsigned short PIPE3BEMPE : 1;
+			unsigned short PIPE4BEMPE : 1;
+			unsigned short PIPE5BEMPE : 1;
+			unsigned short PIPE6BEMPE : 1;
+			unsigned short PIPE7BEMPE : 1;
+			unsigned short PIPE8BEMPE : 1;
+			unsigned short PIPE9BEMPE : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short PIPE9BEMPE : 1;
+			unsigned short PIPE8BEMPE : 1;
+			unsigned short PIPE7BEMPE : 1;
+			unsigned short PIPE6BEMPE : 1;
+			unsigned short PIPE5BEMPE : 1;
+			unsigned short PIPE4BEMPE : 1;
+			unsigned short PIPE3BEMPE : 1;
+			unsigned short PIPE2BEMPE : 1;
+			unsigned short PIPE1BEMPE : 1;
+			unsigned short PIPE0BEMPE : 1;
+#endif
+	} BIT;
+	} BEMPENB;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 4;
+			unsigned short EDGESTS : 1;
+			unsigned short  : 1;
+			unsigned short BRDYM : 1;
+			unsigned short  : 1;
+			unsigned short TRNENSEL : 1;
+			unsigned short  : 7;
+#else
+			unsigned short  : 7;
+			unsigned short TRNENSEL : 1;
+			unsigned short  : 1;
+			unsigned short BRDYM : 1;
+			unsigned short  : 1;
+			unsigned short EDGESTS : 1;
+			unsigned short  : 4;
+#endif
+	} BIT;
+	} SOFCFG;
+	char           wk8[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CTSQ : 3;
+			unsigned short VALID : 1;
+			unsigned short DVSQ : 3;
+			unsigned short VBSTS : 1;
+			unsigned short BRDY : 1;
+			unsigned short NRDY : 1;
+			unsigned short BEMP : 1;
+			unsigned short CTRT : 1;
+			unsigned short DVST : 1;
+			unsigned short SOFR : 1;
+			unsigned short RESM : 1;
+			unsigned short VBINT : 1;
+#else
+			unsigned short VBINT : 1;
+			unsigned short RESM : 1;
+			unsigned short SOFR : 1;
+			unsigned short DVST : 1;
+			unsigned short CTRT : 1;
+			unsigned short BEMP : 1;
+			unsigned short NRDY : 1;
+			unsigned short BRDY : 1;
+			unsigned short VBSTS : 1;
+			unsigned short DVSQ : 3;
+			unsigned short VALID : 1;
+			unsigned short CTSQ : 3;
+#endif
+	} BIT;
+	} INTSTS0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 4;
+			unsigned short SACK : 1;
+			unsigned short SIGN : 1;
+			unsigned short EOFERR : 1;
+			unsigned short  : 4;
+			unsigned short ATTCH : 1;
+			unsigned short DTCH : 1;
+			unsigned short  : 1;
+			unsigned short BCHG : 1;
+			unsigned short OVRCR : 1;
+#else
+			unsigned short OVRCR : 1;
+			unsigned short BCHG : 1;
+			unsigned short  : 1;
+			unsigned short DTCH : 1;
+			unsigned short ATTCH : 1;
+			unsigned short  : 4;
+			unsigned short EOFERR : 1;
+			unsigned short SIGN : 1;
+			unsigned short SACK : 1;
+			unsigned short  : 4;
+#endif
+	} BIT;
+	} INTSTS1;
+	char           wk9[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PIPE0BRDY : 1;
+			unsigned short PIPE1BRDY : 1;
+			unsigned short PIPE2BRDY : 1;
+			unsigned short PIPE3BRDY : 1;
+			unsigned short PIPE4BRDY : 1;
+			unsigned short PIPE5BRDY : 1;
+			unsigned short PIPE6BRDY : 1;
+			unsigned short PIPE7BRDY : 1;
+			unsigned short PIPE8BRDY : 1;
+			unsigned short PIPE9BRDY : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short PIPE9BRDY : 1;
+			unsigned short PIPE8BRDY : 1;
+			unsigned short PIPE7BRDY : 1;
+			unsigned short PIPE6BRDY : 1;
+			unsigned short PIPE5BRDY : 1;
+			unsigned short PIPE4BRDY : 1;
+			unsigned short PIPE3BRDY : 1;
+			unsigned short PIPE2BRDY : 1;
+			unsigned short PIPE1BRDY : 1;
+			unsigned short PIPE0BRDY : 1;
+#endif
+	} BIT;
+	} BRDYSTS;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PIPE0NRDY : 1;
+			unsigned short PIPE1NRDY : 1;
+			unsigned short PIPE2NRDY : 1;
+			unsigned short PIPE3NRDY : 1;
+			unsigned short PIPE4NRDY : 1;
+			unsigned short PIPE5NRDY : 1;
+			unsigned short PIPE6NRDY : 1;
+			unsigned short PIPE7NRDY : 1;
+			unsigned short PIPE8NRDY : 1;
+			unsigned short PIPE9NRDY : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short PIPE9NRDY : 1;
+			unsigned short PIPE8NRDY : 1;
+			unsigned short PIPE7NRDY : 1;
+			unsigned short PIPE6NRDY : 1;
+			unsigned short PIPE5NRDY : 1;
+			unsigned short PIPE4NRDY : 1;
+			unsigned short PIPE3NRDY : 1;
+			unsigned short PIPE2NRDY : 1;
+			unsigned short PIPE1NRDY : 1;
+			unsigned short PIPE0NRDY : 1;
+#endif
+	} BIT;
+	} NRDYSTS;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PIPE0BEMP : 1;
+			unsigned short PIPE1BEMP : 1;
+			unsigned short PIPE2BEMP : 1;
+			unsigned short PIPE3BEMP : 1;
+			unsigned short PIPE4BEMP : 1;
+			unsigned short PIPE5BEMP : 1;
+			unsigned short PIPE6BEMP : 1;
+			unsigned short PIPE7BEMP : 1;
+			unsigned short PIPE8BEMP : 1;
+			unsigned short PIPE9BEMP : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short PIPE9BEMP : 1;
+			unsigned short PIPE8BEMP : 1;
+			unsigned short PIPE7BEMP : 1;
+			unsigned short PIPE6BEMP : 1;
+			unsigned short PIPE5BEMP : 1;
+			unsigned short PIPE4BEMP : 1;
+			unsigned short PIPE3BEMP : 1;
+			unsigned short PIPE2BEMP : 1;
+			unsigned short PIPE1BEMP : 1;
+			unsigned short PIPE0BEMP : 1;
+#endif
+	} BIT;
+	} BEMPSTS;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short FRNM : 11;
+			unsigned short  : 3;
+			unsigned short CRCE : 1;
+			unsigned short OVRN : 1;
+#else
+			unsigned short OVRN : 1;
+			unsigned short CRCE : 1;
+			unsigned short  : 3;
+			unsigned short FRNM : 11;
+#endif
+	} BIT;
+	} FRMNUM;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 15;
+			unsigned short DVCHG : 1;
+#else
+			unsigned short DVCHG : 1;
+			unsigned short  : 15;
+#endif
+	} BIT;
+	} DVCHGR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short USBADDR : 7;
+			unsigned short  : 1;
+			unsigned short STSRECOV : 4;
+			unsigned short  : 4;
+#else
+			unsigned short  : 4;
+			unsigned short STSRECOV : 4;
+			unsigned short  : 1;
+			unsigned short USBADDR : 7;
+#endif
+	} BIT;
+	} USBADDR;
+	char           wk10[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short BMREQUESTTYPE : 8;
+			unsigned short BREQUEST : 8;
+#else
+			unsigned short BREQUEST : 8;
+			unsigned short BMREQUESTTYPE : 8;
+#endif
+	} BIT;
+	} USBREQ;
+	unsigned short USBVAL;
+	unsigned short USBINDX;
+	unsigned short USBLENG;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 4;
+			unsigned short DIR : 1;
+			unsigned short  : 2;
+			unsigned short SHTNAK : 1;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short SHTNAK : 1;
+			unsigned short  : 2;
+			unsigned short DIR : 1;
+			unsigned short  : 4;
+#endif
+	} BIT;
+	} DCPCFG;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short MXPS : 7;
+			unsigned short  : 5;
+			unsigned short DEVSEL : 4;
+#else
+			unsigned short DEVSEL : 4;
+			unsigned short  : 5;
+			unsigned short MXPS : 7;
+#endif
+	} BIT;
+	} DCPMAXP;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PID : 2;
+			unsigned short CCPL : 1;
+			unsigned short  : 2;
+			unsigned short PBUSY : 1;
+			unsigned short SQMON : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQCLR : 1;
+			unsigned short  : 2;
+			unsigned short SUREQCLR : 1;
+			unsigned short  : 2;
+			unsigned short SUREQ : 1;
+			unsigned short BSTS : 1;
+#else
+			unsigned short BSTS : 1;
+			unsigned short SUREQ : 1;
+			unsigned short  : 2;
+			unsigned short SUREQCLR : 1;
+			unsigned short  : 2;
+			unsigned short SQCLR : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQMON : 1;
+			unsigned short PBUSY : 1;
+			unsigned short  : 2;
+			unsigned short CCPL : 1;
+			unsigned short PID : 2;
+#endif
+	} BIT;
+	} DCPCTR;
+	char           wk11[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PIPESEL : 4;
+			unsigned short  : 12;
+#else
+			unsigned short  : 12;
+			unsigned short PIPESEL : 4;
+#endif
+	} BIT;
+	} PIPESEL;
+	char           wk12[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short EPNUM : 4;
+			unsigned short DIR : 1;
+			unsigned short  : 2;
+			unsigned short SHTNAK : 1;
+			unsigned short  : 1;
+			unsigned short DBLB : 1;
+			unsigned short BFRE : 1;
+			unsigned short  : 3;
+			unsigned short TYPE : 2;
+#else
+			unsigned short TYPE : 2;
+			unsigned short  : 3;
+			unsigned short BFRE : 1;
+			unsigned short DBLB : 1;
+			unsigned short  : 1;
+			unsigned short SHTNAK : 1;
+			unsigned short  : 2;
+			unsigned short DIR : 1;
+			unsigned short EPNUM : 4;
+#endif
+	} BIT;
+	} PIPECFG;
+	char           wk13[2];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short MXPS : 9;
+			unsigned short  : 3;
+			unsigned short DEVSEL : 4;
+#else
+			unsigned short DEVSEL : 4;
+			unsigned short  : 3;
+			unsigned short MXPS : 9;
+#endif
+	} BIT;
+	} PIPEMAXP;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short IITV : 3;
+			unsigned short  : 9;
+			unsigned short IFIS : 1;
+			unsigned short  : 3;
+#else
+			unsigned short  : 3;
+			unsigned short IFIS : 1;
+			unsigned short  : 9;
+			unsigned short IITV : 3;
+#endif
+	} BIT;
+	} PIPEPERI;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PID : 2;
+			unsigned short  : 3;
+			unsigned short PBUSY : 1;
+			unsigned short SQMON : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQCLR : 1;
+			unsigned short ACLRM : 1;
+			unsigned short ATREPM : 1;
+			unsigned short  : 3;
+			unsigned short INBUFM : 1;
+			unsigned short BSTS : 1;
+#else
+			unsigned short BSTS : 1;
+			unsigned short INBUFM : 1;
+			unsigned short  : 3;
+			unsigned short ATREPM : 1;
+			unsigned short ACLRM : 1;
+			unsigned short SQCLR : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQMON : 1;
+			unsigned short PBUSY : 1;
+			unsigned short  : 3;
+			unsigned short PID : 2;
+#endif
+	} BIT;
+	} PIPE1CTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PID : 2;
+			unsigned short  : 3;
+			unsigned short PBUSY : 1;
+			unsigned short SQMON : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQCLR : 1;
+			unsigned short ACLRM : 1;
+			unsigned short ATREPM : 1;
+			unsigned short  : 3;
+			unsigned short INBUFM : 1;
+			unsigned short BSTS : 1;
+#else
+			unsigned short BSTS : 1;
+			unsigned short INBUFM : 1;
+			unsigned short  : 3;
+			unsigned short ATREPM : 1;
+			unsigned short ACLRM : 1;
+			unsigned short SQCLR : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQMON : 1;
+			unsigned short PBUSY : 1;
+			unsigned short  : 3;
+			unsigned short PID : 2;
+#endif
+	} BIT;
+	} PIPE2CTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PID : 2;
+			unsigned short  : 3;
+			unsigned short PBUSY : 1;
+			unsigned short SQMON : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQCLR : 1;
+			unsigned short ACLRM : 1;
+			unsigned short ATREPM : 1;
+			unsigned short  : 3;
+			unsigned short INBUFM : 1;
+			unsigned short BSTS : 1;
+#else
+			unsigned short BSTS : 1;
+			unsigned short INBUFM : 1;
+			unsigned short  : 3;
+			unsigned short ATREPM : 1;
+			unsigned short ACLRM : 1;
+			unsigned short SQCLR : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQMON : 1;
+			unsigned short PBUSY : 1;
+			unsigned short  : 3;
+			unsigned short PID : 2;
+#endif
+	} BIT;
+	} PIPE3CTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PID : 2;
+			unsigned short  : 3;
+			unsigned short PBUSY : 1;
+			unsigned short SQMON : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQCLR : 1;
+			unsigned short ACLRM : 1;
+			unsigned short ATREPM : 1;
+			unsigned short  : 3;
+			unsigned short INBUFM : 1;
+			unsigned short BSTS : 1;
+#else
+			unsigned short BSTS : 1;
+			unsigned short INBUFM : 1;
+			unsigned short  : 3;
+			unsigned short ATREPM : 1;
+			unsigned short ACLRM : 1;
+			unsigned short SQCLR : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQMON : 1;
+			unsigned short PBUSY : 1;
+			unsigned short  : 3;
+			unsigned short PID : 2;
+#endif
+	} BIT;
+	} PIPE4CTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PID : 2;
+			unsigned short  : 3;
+			unsigned short PBUSY : 1;
+			unsigned short SQMON : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQCLR : 1;
+			unsigned short ACLRM : 1;
+			unsigned short ATREPM : 1;
+			unsigned short  : 3;
+			unsigned short INBUFM : 1;
+			unsigned short BSTS : 1;
+#else
+			unsigned short BSTS : 1;
+			unsigned short INBUFM : 1;
+			unsigned short  : 3;
+			unsigned short ATREPM : 1;
+			unsigned short ACLRM : 1;
+			unsigned short SQCLR : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQMON : 1;
+			unsigned short PBUSY : 1;
+			unsigned short  : 3;
+			unsigned short PID : 2;
+#endif
+	} BIT;
+	} PIPE5CTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PID : 2;
+			unsigned short  : 3;
+			unsigned short PBUSY : 1;
+			unsigned short SQMON : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQCLR : 1;
+			unsigned short ACLRM : 1;
+			unsigned short  : 5;
+			unsigned short BSTS : 1;
+#else
+			unsigned short BSTS : 1;
+			unsigned short  : 5;
+			unsigned short ACLRM : 1;
+			unsigned short SQCLR : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQMON : 1;
+			unsigned short PBUSY : 1;
+			unsigned short  : 3;
+			unsigned short PID : 2;
+#endif
+	} BIT;
+	} PIPE6CTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PID : 2;
+			unsigned short  : 3;
+			unsigned short PBUSY : 1;
+			unsigned short SQMON : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQCLR : 1;
+			unsigned short ACLRM : 1;
+			unsigned short  : 5;
+			unsigned short BSTS : 1;
+#else
+			unsigned short BSTS : 1;
+			unsigned short  : 5;
+			unsigned short ACLRM : 1;
+			unsigned short SQCLR : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQMON : 1;
+			unsigned short PBUSY : 1;
+			unsigned short  : 3;
+			unsigned short PID : 2;
+#endif
+	} BIT;
+	} PIPE7CTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PID : 2;
+			unsigned short  : 3;
+			unsigned short PBUSY : 1;
+			unsigned short SQMON : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQCLR : 1;
+			unsigned short ACLRM : 1;
+			unsigned short  : 5;
+			unsigned short BSTS : 1;
+#else
+			unsigned short BSTS : 1;
+			unsigned short  : 5;
+			unsigned short ACLRM : 1;
+			unsigned short SQCLR : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQMON : 1;
+			unsigned short PBUSY : 1;
+			unsigned short  : 3;
+			unsigned short PID : 2;
+#endif
+	} BIT;
+	} PIPE8CTR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short PID : 2;
+			unsigned short  : 3;
+			unsigned short PBUSY : 1;
+			unsigned short SQMON : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQCLR : 1;
+			unsigned short ACLRM : 1;
+			unsigned short  : 5;
+			unsigned short BSTS : 1;
+#else
+			unsigned short BSTS : 1;
+			unsigned short  : 5;
+			unsigned short ACLRM : 1;
+			unsigned short SQCLR : 1;
+			unsigned short SQSET : 1;
+			unsigned short SQMON : 1;
+			unsigned short PBUSY : 1;
+			unsigned short  : 3;
+			unsigned short PID : 2;
+#endif
+	} BIT;
+	} PIPE9CTR;
+	char           wk14[14];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 8;
+			unsigned short TRCLR : 1;
+			unsigned short TRENB : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short TRENB : 1;
+			unsigned short TRCLR : 1;
+			unsigned short  : 8;
+#endif
+	} BIT;
+	} PIPE1TRE;
+	unsigned short PIPE1TRN;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 8;
+			unsigned short TRCLR : 1;
+			unsigned short TRENB : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short TRENB : 1;
+			unsigned short TRCLR : 1;
+			unsigned short  : 8;
+#endif
+	} BIT;
+	} PIPE2TRE;
+	unsigned short PIPE2TRN;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 8;
+			unsigned short TRCLR : 1;
+			unsigned short TRENB : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short TRENB : 1;
+			unsigned short TRCLR : 1;
+			unsigned short  : 8;
+#endif
+	} BIT;
+	} PIPE3TRE;
+	unsigned short PIPE3TRN;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 8;
+			unsigned short TRCLR : 1;
+			unsigned short TRENB : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short TRENB : 1;
+			unsigned short TRCLR : 1;
+			unsigned short  : 8;
+#endif
+	} BIT;
+	} PIPE4TRE;
+	unsigned short PIPE4TRN;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 8;
+			unsigned short TRCLR : 1;
+			unsigned short TRENB : 1;
+			unsigned short  : 6;
+#else
+			unsigned short  : 6;
+			unsigned short TRENB : 1;
+			unsigned short TRCLR : 1;
+			unsigned short  : 8;
+#endif
+	} BIT;
+	} PIPE5TRE;
+	unsigned short PIPE5TRN;
+	char           wk15[44];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 6;
+			unsigned short USBSPD : 2;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short USBSPD : 2;
+			unsigned short  : 6;
+#endif
+	} BIT;
+	} DEVADD0;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 6;
+			unsigned short USBSPD : 2;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short USBSPD : 2;
+			unsigned short  : 6;
+#endif
+	} BIT;
+	} DEVADD1;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 6;
+			unsigned short USBSPD : 2;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short USBSPD : 2;
+			unsigned short  : 6;
+#endif
+	} BIT;
+	} DEVADD2;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 6;
+			unsigned short USBSPD : 2;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short USBSPD : 2;
+			unsigned short  : 6;
+#endif
+	} BIT;
+	} DEVADD3;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 6;
+			unsigned short USBSPD : 2;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short USBSPD : 2;
+			unsigned short  : 6;
+#endif
+	} BIT;
+	} DEVADD4;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short  : 6;
+			unsigned short USBSPD : 2;
+			unsigned short  : 8;
+#else
+			unsigned short  : 8;
+			unsigned short USBSPD : 2;
+			unsigned short  : 6;
+#endif
+	} BIT;
+	} DEVADD5;
+	char           wk16[20];
+	union {
+		unsigned long LONG;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned long SLEWR00 : 1;
+			unsigned long SLEWR01 : 1;
+			unsigned long SLEWF00 : 1;
+			unsigned long SLEWF01 : 1;
+			unsigned long  : 28;
+#else
+			unsigned long  : 28;
+			unsigned long SLEWF01 : 1;
+			unsigned long SLEWF00 : 1;
+			unsigned long SLEWR01 : 1;
+			unsigned long SLEWR00 : 1;
+#endif
+	} BIT;
+	} PHYSLEW;
+} st_usb0_t;
+
+typedef struct st_wdt {
+	unsigned char  WDTRR;
+	char           wk0[1];
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short TOPS : 2;
+			unsigned short  : 2;
+			unsigned short CKS : 4;
+			unsigned short RPES : 2;
+			unsigned short  : 2;
+			unsigned short RPSS : 2;
+			unsigned short  : 2;
+#else
+			unsigned short  : 2;
+			unsigned short RPSS : 2;
+			unsigned short  : 2;
+			unsigned short RPES : 2;
+			unsigned short CKS : 4;
+			unsigned short  : 2;
+			unsigned short TOPS : 2;
+#endif
+	} BIT;
+	} WDTCR;
+	union {
+		unsigned short WORD;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned short CNTVAL : 14;
+			unsigned short UNDFF : 1;
+			unsigned short REFEF : 1;
+#else
+			unsigned short REFEF : 1;
+			unsigned short UNDFF : 1;
+			unsigned short CNTVAL : 14;
+#endif
+	} BIT;
+	} WDTSR;
+	union {
+		unsigned char BYTE;
+		struct {
+			
+#ifdef __RX_LITTLE_ENDIAN__
+			unsigned char  : 7;
+			unsigned char RSTIRQS : 1;
+#else
+			unsigned char RSTIRQS : 1;
+			unsigned char  : 7;
+#endif
+	} BIT;
+	} WDTRCR;
+} st_wdt_t;
+
+typedef struct st_flashconst {
+	unsigned long  UIDR0;
+	unsigned long  UIDR1;
+	unsigned long  UIDR2;
+	unsigned long  UIDR3;
+} st_flashconst_t;
+
+typedef struct st_tempsconst {
+	unsigned long  TSCDR;
+} st_tempsconst_t;
+
+
+#pragma pack()
+
+#endif
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/vecttbl.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/vecttbl.c
new file mode 100644
index 00000000..58ca3323
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/vecttbl.c
@@ -0,0 +1,229 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : vecttbl.c
+* Device(s)    : RX65N
+* Description  : Definition of the exception vector table, reset vector, and user boot options.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 01.10.2016 1.00      First Release
+*         : 15.05.2017 2.00      Deleted unnecessary comments.
+*                                Added the following setting.
+*                                - Setting of Expansion RAM.
+*                                - Setting of Bank Mode Select.
+*                                - Setting of Startup Bank Switch.
+*                                Added the bsp startup module disable function.
+*         : 27.07.2018 2.01      Modified the comment of START_BANK_VALUE.
+*                                Changed the setting of ID code protection.
+*         : 28.02.2019 3.00      Deleted exception functions.
+*                                (Exception functions moved to the common file (r_bsp_interrupts.c).)
+*                                Added support for GNUC and ICCRX.
+*                                Fixed coding style.
+*         : 31.07.2019 3.01      Fixed initialization for option-setting memory.
+*         : 08.10.2019 3.01      Changed for added support of Renesas RTOS (RI600V4 or RI600PX).
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* BSP configuration. */
+#include "platform.h"
+
+/* When using the user startup program, disable the following code. */
+#if BSP_CFG_STARTUP_DISABLE == 0
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+R_BSP_POR_FUNCTION(R_BSP_POWER_ON_RESET_FUNCTION);
+
+/***********************************************************************************************************************
+* The following array fills in the option function select registers, fixed vector table, and the ID code protection 
+* bytes.
+***********************************************************************************************************************/
+#ifdef __BIG
+    #define BSP_PRV_MDE_VALUE (0xfffffff8)    /* big */
+#else
+    #define BSP_PRV_MDE_VALUE (0xffffffff)    /* little */
+#endif
+
+#if defined(BSP_MCU_RX65N_2MB) /* In the case of 1.5 or 2Mbyte ROM capacity. */
+    #if BSP_CFG_CODE_FLASH_BANK_MODE == 0
+        #define BSP_PRV_BANK_MODE_VALUE (0xffffff8f)    /* dual */
+    #else
+        #define BSP_PRV_BANK_MODE_VALUE (0xffffffff)    /* linear */
+    #endif
+#else
+    #define BSP_PRV_BANK_MODE_VALUE (0xffffffff)    /* linear */
+#endif
+
+#if defined(BSP_MCU_RX65N_2MB) /* In the case of 1.5 or 2Mbyte ROM capacity. */
+    #if BSP_CFG_CODE_FLASH_START_BANK == 0
+        /* The address range of bank 1 from FFE00000h to FFEFFFFFh and bank 0 from FFF00000h to FFFFFFFFh. */
+        #define BSP_PRV_START_BANK_VALUE (0xffffffff)
+    #else
+        /* The address range of bank 1 from FFF00000h to FFFFFFFFh and bank 0 from FFE00000h to FFEFFFFFh. */
+        #define BSP_PRV_START_BANK_VALUE (0xfffffff8)
+    #endif
+#endif
+
+#if defined(__CCRX__)
+
+#pragma address __MDEreg     = 0xFE7F5D00
+#pragma address __OFS0reg    = 0xFE7F5D04
+#pragma address __OFS1reg    = 0xFE7F5D08
+#pragma address __TMINFreg   = 0xFE7F5D10
+#if defined(BSP_MCU_RX65N_2MB)
+#pragma address __BANKSELreg = 0xFE7F5D20
+#endif
+#pragma address __SPCCreg    = 0xFE7F5D40
+#pragma address __TMEFreg    = 0xFE7F5D48
+#pragma address __OSIS1reg   = 0xFE7F5D50
+#pragma address __OSIS2reg   = 0xFE7F5D54
+#pragma address __OSIS3reg   = 0xFE7F5D58
+#pragma address __OSIS4reg   = 0xFE7F5D5C
+#pragma address __FAWreg     = 0xFE7F5D64
+#pragma address __ROMCODEreg = 0xFE7F5D70
+
+const uint32_t __MDEreg     = (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE);
+const uint32_t __OFS0reg    = BSP_CFG_OFS0_REG_VALUE;
+const uint32_t __OFS1reg    = BSP_CFG_OFS1_REG_VALUE;
+const uint32_t __TMINFreg   = 0xffffffff;
+#if defined(BSP_MCU_RX65N_2MB)
+const uint32_t __BANKSELreg = BSP_PRV_START_BANK_VALUE;
+#endif
+const uint32_t __SPCCreg    = 0xffffffff;
+const uint32_t __TMEFreg    = BSP_CFG_TRUSTED_MODE_FUNCTION;
+const uint32_t __OSIS1reg   = BSP_CFG_ID_CODE_LONG_1;
+const uint32_t __OSIS2reg   = BSP_CFG_ID_CODE_LONG_2;
+const uint32_t __OSIS3reg   = BSP_CFG_ID_CODE_LONG_3;
+const uint32_t __OSIS4reg   = BSP_CFG_ID_CODE_LONG_4;
+const uint32_t __FAWreg     = BSP_CFG_FAW_REG_VALUE;
+const uint32_t __ROMCODEreg = BSP_CFG_ROMCODE_REG_VALUE;
+
+#elif defined(__GNUC__)
+
+const st_ofsm_sec_ofs1_t __ofsm_sec_ofs1   __attribute__ ((section(".ofs1"))) = {
+    (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE), /* __MDEreg */
+    BSP_CFG_OFS0_REG_VALUE, /* __OFS0reg */
+    BSP_CFG_OFS1_REG_VALUE  /* __OFS1reg */
+};
+const uint32_t __TMINFreg   __attribute__ ((section(".ofs2"))) = 0xffffffff;
+#if defined(BSP_MCU_RX65N_2MB)
+const uint32_t __BANKSELreg __attribute__ ((section(".ofs3"))) = BSP_PRV_START_BANK_VALUE;
+#endif
+const uint32_t __SPCCreg    __attribute__ ((section(".ofs4"))) = 0xffffffff;
+const uint32_t __TMEFreg    __attribute__ ((section(".ofs5"))) = BSP_CFG_TRUSTED_MODE_FUNCTION;
+const st_ofsm_sec_ofs6_t __ofsm_sec_ofs6   __attribute__ ((section(".ofs6"))) = {
+    BSP_CFG_ID_CODE_LONG_1, /* __OSIS1reg */
+    BSP_CFG_ID_CODE_LONG_2, /* __OSIS2reg */
+    BSP_CFG_ID_CODE_LONG_3, /* __OSIS3reg */
+    BSP_CFG_ID_CODE_LONG_4  /* __OSIS4reg */
+};
+const uint32_t __FAWreg     __attribute__ ((section(".ofs7"))) = BSP_CFG_FAW_REG_VALUE;
+const uint32_t __ROMCODEreg __attribute__ ((section(".ofs8"))) = BSP_CFG_ROMCODE_REG_VALUE;
+
+#elif defined(__ICCRX__)
+
+#pragma public_equ = "__MDE", (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE)
+#pragma public_equ = "__OFS0", BSP_CFG_OFS0_REG_VALUE
+#pragma public_equ = "__OFS1", BSP_CFG_OFS1_REG_VALUE
+#pragma public_equ = "__TMINF", 0xffffffff
+#if defined(BSP_MCU_RX65N_2MB)
+#pragma public_equ = "__BANKSEL", BSP_PRV_START_BANK_VALUE
+#endif
+#pragma public_equ = "__SPCC", 0xffffffff
+#pragma public_equ = "__TMEF", BSP_CFG_TRUSTED_MODE_FUNCTION
+#pragma public_equ = "__OSIS_1", BSP_CFG_ID_CODE_LONG_1
+#pragma public_equ = "__OSIS_2", BSP_CFG_ID_CODE_LONG_2
+#pragma public_equ = "__OSIS_3", BSP_CFG_ID_CODE_LONG_3
+#pragma public_equ = "__OSIS_4", BSP_CFG_ID_CODE_LONG_4
+#pragma public_equ = "__FAW", BSP_CFG_FAW_REG_VALUE
+#pragma public_equ = "__ROM_CODE", BSP_CFG_ROMCODE_REG_VALUE
+
+#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */
+
+/***********************************************************************************************************************
+* The following array fills in the exception vector table.
+***********************************************************************************************************************/
+#if BSP_CFG_RTOS_USED == 4  /* Renesas RI600V4 & RI600PX */
+     /* System configurator generates the ritble.src as interrupt & exception vector tables. */
+#else /* BSP_CFG_RTOS_USED!=4 */
+
+#if defined(__CCRX__) || defined(__GNUC__)
+R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT void (* const Except_Vectors[])(void) =
+{
+    /* Offset from EXTB: Reserved area - must be all 0xFF */
+    (void (*)(void))0xFFFFFFFF,  /* 0x00 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x04 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x08 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x0c - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x10 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x14 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x18 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x1c - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x20 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x24 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x28 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x2c - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x30 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x34 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x38 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x3c - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x40 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x44 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x48 - Reserved */
+    (void (*)(void))0xFFFFFFFF,  /* 0x4c - Reserved */
+
+    /* Exception vector table */
+    excep_supervisor_inst_isr,         /* 0x50  Exception(Supervisor Instruction) */
+    excep_access_isr,                  /* 0x54  Exception(Access exception) */
+    undefined_interrupt_source_isr,    /* 0x58  Reserved */
+    excep_undefined_inst_isr,          /* 0x5c  Exception(Undefined Instruction) */
+    undefined_interrupt_source_isr,    /* 0x60  Reserved */
+    excep_floating_point_isr,          /* 0x64  Exception(Floating Point) */
+    undefined_interrupt_source_isr,    /* 0x68  Reserved */
+    undefined_interrupt_source_isr,    /* 0x6c  Reserved */
+    undefined_interrupt_source_isr,    /* 0x70  Reserved */
+    undefined_interrupt_source_isr,    /* 0x74  Reserved */
+    non_maskable_isr,                  /* 0x78  NMI */
+};
+R_BSP_ATTRIB_SECTION_CHANGE_END
+#endif /* defined(__CCRX__), defined(__GNUC__) */
+
+/***********************************************************************************************************************
+* The following array fills in the reset vector.
+***********************************************************************************************************************/
+#if defined(__CCRX__) || defined(__GNUC__)
+R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT void (* const Reset_Vector[])(void) =
+{
+    R_BSP_POWER_ON_RESET_FUNCTION                   /* 0xfffffffc  RESET */
+};
+R_BSP_ATTRIB_SECTION_CHANGE_END
+#endif /* defined(__CCRX__), defined(__GNUC__) */
+
+#endif/* BSP_CFG_RTOS_USED */
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/vecttbl.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/vecttbl.h
new file mode 100644
index 00000000..68bf2c0b
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/mcu/rx65n/vecttbl.h
@@ -0,0 +1,66 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : vecttbl.h
+* Description  : Has function prototypes for exception callback functions.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 01.10.2016 1.00      First Release
+*         : 28.02.2019 1.01      Fixed coding style.
+*         : 31.07.2019 1.02      Added typedef for option-setting memory.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef VECTTBL_HEADER_INC
+#define VECTTBL_HEADER_INC
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+#if defined(__GNUC__)
+typedef struct st_ofsm_sec_ofs1
+{
+    uint32_t __MDEreg;
+    uint32_t __OFS0reg;
+    uint32_t __OFS1reg;
+} st_ofsm_sec_ofs1_t;
+
+typedef struct st_ofsm_sec_ofs6
+{
+    uint32_t __OSIS1reg;
+    uint32_t __OSIS2reg;
+    uint32_t __OSIS3reg;
+    uint32_t __OSIS4reg;
+} st_ofsm_sec_ofs6_t;
+#endif /* defined(__GNUC__) */
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+
+#endif /* VECTTBL_HEADER_INC */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/platform.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/platform.h
new file mode 100644
index 00000000..c11503ef
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/platform.h
@@ -0,0 +1,224 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : platform.h
+* Description  : The user chooses which MCU and board they are developing for in this file. If the board you are using
+*                is not listed below, please add your own or use the default 'User Board'.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 30.11.2011 1.00     First Release
+*         : 13.01.2012 1.10     Moved from having platform defined using macro definition, to having platform defined
+*                               by choosing an include path. This makes this file simpler and cleans up the issue
+*                               where HEW shows all header files for all platforms under 'Dependencies'.
+*         : 14.02.2012 1.20     Added RX210 BSP.
+*         : 18.04.2012 1.30     Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding
+*                               locking.c and locking.h in board folders. Also, r_bsp can now be configured through
+*                               r_bsp_config.h.
+*         : 26.06.2012 1.40     Added new options such as exception callbacks and the ability to choose your MCU using
+*                               its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort
+*                               to remove any extra files that the user would need to touch. Removed the flash_options.c
+*                               file and put its contents in vecttbl.c.
+*         : 17.07.2012 1.50     Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT 
+*                               macro options in r_bsp_config.h. Added some extra code to handle exceptions in
+*                               vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks.
+*         : 09.08.2012 1.60     Added IO_LIB_ENABLE macro to r_bsp_config_reference.h.
+*         : 14.11.2012 1.70     Added RSKRX62G, RSKRX63T, and RSKRX111 support.
+*         : 28.11.2012 2.00     Updated to be compliant with v1.00 r_bsp specification.
+*         : 21.01.2013 2.10     Added RSKRX63T_144PIN support.
+*         : 10.05.2013 2.20     Added new packages and memory variants to RX210. All iodefine.h files have been updated
+*                               to latest revisions. On reset, all MCUs will now initialize non-bonded out pins to
+*                               reduce current draw. r_bsp_common.c and .h files were added to support functionality
+*                               common to all BSPs. cpu.c and cpu.h files were added to all MCU groups to support
+*                               CPU functions such as enabling/disabling interrupts, setting the IPL, and controlling
+*                               register protection. mcu_init.c and mcu_init.h were add to all MCU groups to support
+*                               initialization functions that are common to a MCU group such as non-bonded pin init.
+*                               Choosing MCU endian has been removed from r_bsp_config.h and is now automatically
+*                               set based on compiler macros. RX-C, IAR, and GCC endian macros are supported. RX210
+*                               now has support for choosing HOCO frequency. All r_bsp_config.h files now have macro
+*                               for defining Vcc which is needed by some FIT modules. IRQ locks were added for all
+*                               MCU groups. BSP_PACKAGE_PINS macro was added to mcu_info.h which defines number of pins
+*                               for the currently chosen package. RX111 and RX210 now have the option of using the
+*                               r_cgc_rx module for clock management based on BSP_CFG_USE_CGC_MODULE macro in
+*                               r_bsp_config.h.
+*         : 31.05.2013 2.21     Added latest iodefine.h files for RX111 (v0.9a), RX630 (v1,50a), and RX63N (v1.60). Also
+*                               added 'doc' folder to root of r_bsp. Currently the only the document in there is the
+*                               preliminary version of the r_bsp User's Manual. For RX210, the ability to choose chip
+*                               version C was added to its r_bsp_config.h file.
+*         : 01.07.2013 2.30     Removed RSPI pin setup in RSKRX111 which caused excess current draw in low power
+*                               modes. Changed FIT_NO_PTR and FIT_NO_FUNC macros to 0x10000000 which works for all 
+*                               RX MCUs. Added ability for user to use 1 or 2 stacks for RX MCUs. Added new interrupt
+*                               handling features which allows for interrupt callback registration. This feature allows
+*                               all interrupts that map to the NMI vector to be used and replaces the static callback
+*                               definitions that were in r_bsp_config.h previously. RX111 information has been updated
+*                               according to v1.00 HW manual. This includes support for 40-pin packages. All compiler
+*                               messages and warnings for lowsrc.c have been cleaned up. Non-existent port init has
+*                               been moved to end of hardware_setup() to ensure user does not overwrite the settings.
+*                               Added blank lines between clock macros in r_bsp_config.h to aid in readability. Added
+*                               '(void *)' cast to FIT_NO_PTR to remove compiler warnings. All r_bsp.h files now include
+*                               r_bsp_common.h which has common includes (stdint.h, stddef.h, & stdbool.h) and uses
+*                               r_typedefs.h when C99 is not available. RX111 and RX210 MCUs have the option of using
+*                               the r_cgc_rx module for clock management. When this is used, the clock info macros in 
+*                               mcu_info.h (e.g. BSP_ICLK_HZ) will now make calls to the r_cgc_rx module instead of 
+*                               providing static info. For debug console output, lowlvl.src was replaced by lowlvl.c
+*                               (assembly converted to C source).
+*         : 10.02.2014 2.40     Added support for the RSKRX110, RPBRX111, RSKRX220, and HSBRX21AP. Made sure
+*                               in hwsetup.c files that the PMR registers are set after the MPC registers. Replaced
+*                               use of stdint.h, stdbool.h, and stddef.h with platform.h to remove compiler warnings.
+*                               Removed includes for machine.h since it is compiler specific and replaced with
+*                               platform.h. Fixed bug in resetprg.c for many boards where LOCO was not being turned off
+*                               when it was not being used. RX100 code now uses the oscillation stabilization flags
+*                               instead of SW delay loop. Changed size_t to unsigned long. Defined PRC2 in register
+*                               protection section for RX111. Fixed bug in non-existent pin setup for RX111. No
+*                               platform is chosen by default (used to be the RSKRX111). This makes it easier to
+*                               understand the problem when you build a new project and have not selected your platform.
+*         : 24.03.2014 2.50     Added support for the RSKRX64M.
+*         : 16.06.2014 2.60     Added version control for r_bsp_config.h Two user callback functions may now be 
+*                               configured allowing callbacks from PowerON_Reset_PC() for warm start detection.
+*                               Stdio charget() and charput() functions may now be redirected to user defined functions.
+*                               Added support for RSKRX631 and RDKRX631.
+*         : 05.08.2014 2.70     Added support for RSKRX113.
+*         : 29.09.2014 2.80     Added support for RSKRX71M.
+*         : 22.12.2014 2.90     Added support for RSKRX231.
+*         : 30.09.2015 3.00     Added support for RSSKRX23T and RSKRX23T.
+*         : 30.09.2015 3.01     Fix for RSKRX231 and RSKRX23T(RSSKRX23T).
+*         : 01.12.2015 3.10     Added support for RSKRX130.
+*         : 01.02.2016 3.20     Added support for RSKRX24T.
+*         : 29.02.2016 3.30     Added support for RSKRX230.
+*         : 01.10.2016 3.40     Added support for RSKRX65N.
+*         : 22.08.2016 3.50     Added support for RSKRX24U.
+*         : 15.05.2017 3.60     Added support for RSKRX65N-2MB.
+*                               Added support for GENERIC_RX65N.
+*                               Added support for RSKRX130-512KB.
+*         : 01.11.2017 3.70     Added support for GENERIC_RX130.
+*                               Added support for GENERIC_RX110.
+*                               Added support for GENERIC_RX111.
+*                               Added support for GENERIC_RX113.
+*                               Added support for GENERIC_RX230.
+*                               Added support for GENERIC_RX231.
+*                               Added support for GENERIC_RX23T.
+*                               Added support for GENERIC_RX24T.
+*                               Added support for GENERIC_RX24U.
+*                               Added support for GENERIC_RX64M.
+*                               Added support for GENERIC_RX71M.
+*                               Added support for ENVISIONRX65N.
+*         : 01.11.2017 3.71     Corrected typo in Rev3.70 BSP.
+*         : 01.07.2018 3.80     Added support for TARGETBOARDRX65N.
+*                               Added support for TARGETBOARDRX231.
+*                               Added support for TARGETBOARDRX130.
+*         : 27.07.2018 3.90     Added support for GENERIC_RX66T.
+*                               Deleted the below board folders, since other boards can all be substituted with 
+*                               GENERIC_RXxxx.
+*                               - RSKRX64M, RSKRX65N, RSKRX65N_2MB, TARGETBOARDRX65N, ENVISIONRX65N, RSKRX71M, 
+*                                 RSKRX230, RSKRX231, TARGETBOARDRX231, RSKRX110, RSKRX111, RPBRX111, RSKRX113, 
+*                                 RSKRX130, RSKRX130_512KB, and TARGETBOARDRX130
+*         : 31.10.2018 4.00     Added support for GENERIC_RX72T.
+*                               Deleted the below board folders, since other boards can all be substituted with 
+*                               GENERIC_RXxxx.
+*                               - RSSKRX23T, RSKRX23T, RSKRX24T, and RSKRX24U
+*         : 28.02.2019 5.00     Deleted the below board folders.
+*                               - RSKRX610, RSKRX62N, RSKRX62T, RSKRX62G, RDKRX62N, RSKRX630, RSKRX631, RSKRX63T_64PIN,
+*                                 RSKRX63T_144PIN, RDKRX63N, RDKRX631, RSKRX210, HSBRX21AP and RSKRX220
+*         : 29.03.2019 5.10     Added support for GENERIC_RX23W.
+*         : 08.04.2019 5.20     Added support for GENERIC_RX72M.
+*         : 26.07.2019 5.30     Added support for GENERIC_RX13T.
+*         : 31.07.2019 5.40     Added support for GENERIC_RX23E-A.
+*         : 08.10.2019 5.50     Added support for GENERIC_RX72N, and GENERIC_RX66N.
+*                               Deleted the board folders of RSKRX63N.
+***********************************************************************************************************************/
+
+/* Multiple inclusion prevention macro */
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+/***********************************************************************************************************************
+DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING.
+***********************************************************************************************************************/
+/* GENERIC_RX64M */
+//#include "./board/generic_rx64m/r_bsp.h"
+
+/* GENERIC_RX65N */
+#include "./board/generic_rx65n/r_bsp.h"
+
+/* GENERIC_RX66N */
+//#include "./board/generic_rx66n/r_bsp.h"
+
+/* GENERIC_RX66T */
+//#include "./board/generic_rx66t/r_bsp.h"
+
+/* GENERIC_RX71M */
+//#include "./board/generic_rx71m/r_bsp.h"
+
+/* GENERIC_RX72M */
+//#include "./board/generic_rx72m/r_bsp.h"
+
+/* GENERIC_RX72N */
+//#include "./board/generic_rx72n/r_bsp.h"
+
+/* GENERIC_RX72T */
+//#include "./board/generic_rx72t/r_bsp.h"
+
+/* GENERIC_RX230 */
+//#include "./board/generic_rx230/r_bsp.h"
+
+/* GENERIC_RX231 */
+//#include "./board/generic_rx231/r_bsp.h"
+
+/* GENERIC_RX23E-A */
+//#include "./board/generic_rx23e-a/r_bsp.h"
+
+/* GENERIC_RX23T */
+//#include "./board/generic_rx23t/r_bsp.h"
+
+/* GENERIC_RX23W */
+//#include "./board/generic_rx23w/r_bsp.h"
+
+/* GENERIC_RX24T */
+//#include "./board/generic_rx24t/r_bsp.h"
+
+/* GENERIC_RX24U */
+//#include "./board/generic_rx24u/r_bsp.h"
+
+/* GENERIC_RX111 */
+//#include "./board/generic_rx111/r_bsp.h"
+
+/* GENERIC_RX110 */
+//#include "./board/generic_rx110/r_bsp.h"
+
+/* GENERIC_RX113 */
+//#include "./board/generic_rx113/r_bsp.h"
+
+/* GENERIC_RX130 */
+//#include "./board/generic_rx130/r_bsp.h"
+
+/* GENERIC_RX13T */
+//#include "./board/generic_rx13t/r_bsp.h"
+
+/* User Board - Define your own board here. */
+//#include "./board/user/r_bsp.h"
+
+/***********************************************************************************************************************
+MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT
+***********************************************************************************************************************/
+#ifndef PLATFORM_DEFINED
+#error  "Error - No platform defined in platform.h!"
+#endif
+
+#endif /* PLATFORM_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/readme.txt b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/readme.txt
new file mode 100644
index 00000000..25aa74e4
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_bsp/readme.txt
@@ -0,0 +1,57 @@
+r_bsp Package
+=============
+
+Overview
+--------
+The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU
+information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder contains files 
+that are common to a MCU group. These files provide functionality such as easy register access, CPU functions,
+and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board
+and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help 
+configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each 
+supported board.  Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which 
+board they are using by uncommenting the include path that applies to their board. For example, if you are using the 
+RSK+RX62N then you would uncomment the #include "./board/rskrx62n/r_bsp.h" include path. Users are encouraged to add 
+their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a 
+reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it 
+to r_bsp_config.h, and use the options inside the file to configure the BSP for their project.
+
+
+Features
+--------
+* Provides foundation to build code on top of.
+* Provides MCU startup code.
+* Provides SFR access through iodefine.h
+* Stores details of MCU in 'mcu_info.h' to help configure Renesas middleware.
+* Easily configure BSP through r_bsp_config.h.
+* Choose MCU easily by inputting part number details in r_bsp_config.h.
+* Provides callbacks for MCU exceptions and the bus error interrupt.
+* Supports initializing non-bonded out pins to reduce power
+* Provides API to control CPU functions such as setting the IPL, enabling/disabling interrupts, and controlling 
+  register protection
+ 
+
+
+File Structure
+--------------
+r_bsp
+|   platform.h 
+|   readme.txt
+|
++---board
+|   +---generic_rx111
+|   |    :
+|   :
+|   \---user
+|
++---doc
+|   +---en
+|       r01an1685ej{VERSION_NUMBER}-rx-bsp.pdf
+|   +---ja
+|       r01an1685jj{VERSION_NUMBER}-rx-bsp.pdf
+|
+\---mcu
+    +---all
+    +---rx111
+    |    :
+    :
\ No newline at end of file
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/doc/en/r01an1856ej0470-rx-timer.pdf b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/doc/en/r01an1856ej0470-rx-timer.pdf
new file mode 100644
index 00000000..221dc526
Binary files /dev/null and b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/doc/en/r01an1856ej0470-rx-timer.pdf differ
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/doc/ja/r01an1856jj0470-rx-timer.pdf b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/doc/ja/r01an1856jj0470-rx-timer.pdf
new file mode 100644
index 00000000..e5ff869c
Binary files /dev/null and b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/doc/ja/r01an1856jj0470-rx-timer.pdf differ
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/r_cmt_rx_if.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/r_cmt_rx_if.h
new file mode 100644
index 00000000..62460de9
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/r_cmt_rx_if.h
@@ -0,0 +1,124 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer 
+*
+* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_cmt_rx_if.h
+* Description  : This module creates a timer tick using a CMT channel.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version Description               
+*         : 06.11.2013 2.10    First GSCE Release.
+*         : 22.04.2014 2.30    Updates for RX110, RX64M support.
+*         : 10.11.2014 2.40    Added support for RX113.
+*         : 12.04.2014 2.41    Updated demo project.
+*         : 12.04.2014 2.50    Updated demo project.
+*         : 01.04.2015 2.60    Added support for RX231.
+*         : 30.09.2015 2.70    Added support for RX23T.
+*         : 01.10.2015 2.80    Added support for RX130.
+*         : 01.12.2015 2.90    Added support for RX230, RX24T.
+*         : 15.06.2016 2.91    Added the demo of the RX64M group.
+*         : 01.10.2016 3.00    Added support for RX65N.
+*         : 19.12.2016 3.10    Added support for RX24U, RX24T(512KB).
+*         : 21.07.2017 3.20    Added support for RX65N-2M, RX130-512KB.
+*         : 31.10.2017 3.21    Added the demo for RX65N, RX65N-2M.
+*         : 28.09.2018 3.30    Added support for RX66T.
+*         : 16.11.2018 3.31    Added XML document number.
+*         : 01.02.2019 3.40    Added support for RX72T, RX65N-64pin.
+*                              Added new feature: get/set interrupt priority of CMT channel.
+*         : 20.05.2019 4.00    Added support for GNUC and ICCRX.
+*         : 28.06.2019 4.10    Added support for RX23W.
+*         : 15.08.2019 4.20    Added support for RX72M.
+*         : 25.11.2019 4.30    Added support RX13T, RX66N, RX72N.
+*         : 29.11.2019 4.31    Fixed issues in power_on() and power_off().
+*         : 31.03.2020 4.40    Added support for RX23E-A.
+*         : 29.05.2020 4.50    Added support BLE for RX23W; CMT2, CMT3 are protected for RX23W.
+*         : 30.06.2020 4.60    Changed revision to reflect demo upgrade.
+*         : 31.08.2020 4.70    Added condition for _RI_TRACE_TIMER macro
+*                              Fixed warning when using RI600V4 with device has 2 CMT channels
+***********************************************************************************************************************/
+#ifndef CMT_HEADER_FILE
+#define CMT_HEADER_FILE
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+#if R_BSP_VERSION_MAJOR < 5
+    #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher."
+#endif
+
+/* Version Number of API. */
+#define CMT_RX_VERSION_MAJOR            (4)
+#define CMT_RX_VERSION_MINOR            (70)
+
+/* This define is used with the R_CMT_Control() function if not channel needs to input. */
+#define CMT_RX_NO_CHANNEL               (0xFFFFFFFF)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+/* Commands that can be used with R_CMT_Control() function. */
+typedef enum
+{
+    CMT_RX_CMD_IS_CHANNEL_COUNTING = 0,    //Used for determining if a particular CMT channel is currently being used
+    CMT_RX_CMD_PAUSE,                      //Pause a running timer without releasing it
+    CMT_RX_CMD_RESTART,                    //Restart a paused timer from zero
+    CMT_RX_CMD_RESUME,                     //Restart a paused timer without zeroing it first
+    CMT_RX_CMD_GET_NUM_CHANNELS,           //Used for getting number of CMT channels on this MCU
+    CMT_RX_CMD_SET_PRIORITY,               //Set the interrupt priority of the CMT channel
+    CMT_RX_CMD_GET_PRIORITY                //Get the interrupt priority of the CMT channel
+} cmt_commands_t;
+
+/* CMT interrupt priority values that can be used with R_CMT_Control() function. */
+typedef enum
+{
+    CMT_PRIORITY_0 = 0, /* 0: Interrupt is disabled */
+    CMT_PRIORITY_1,     /* 1: Lowest interrupt priority */
+    CMT_PRIORITY_2,
+    CMT_PRIORITY_3,
+    CMT_PRIORITY_4,
+    CMT_PRIORITY_5,
+    CMT_PRIORITY_6,
+    CMT_PRIORITY_7,
+    CMT_PRIORITY_8,
+    CMT_PRIORITY_9,
+    CMT_PRIORITY_10,
+    CMT_PRIORITY_11,
+    CMT_PRIORITY_12,
+    CMT_PRIORITY_13,
+    CMT_PRIORITY_14,
+    CMT_PRIORITY_MAX     /* 15: Highest interrupt priority */
+} cmt_priority_t;
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+bool R_CMT_CreatePeriodic(uint32_t frequency_hz, void (* callback)(void * pdata), uint32_t * channel);
+bool R_CMT_CreatePeriodicAssignChannelPriority(uint32_t frequency_hz, void (* callback)(void * pdata), uint32_t channel, cmt_priority_t priority);
+bool R_CMT_CreateOneShot(uint32_t period_us, void (* callback)(void * pdata), uint32_t * channel);
+bool R_CMT_CreateOneShotAssignChannelPriority(uint32_t period_us, void (* callback)(void * pdata), uint32_t channel, cmt_priority_t priority);
+bool R_CMT_Control(uint32_t channel, cmt_commands_t command, void * pdata);
+bool R_CMT_Stop(uint32_t channel);
+uint32_t R_CMT_GetVersion(void);
+
+#endif /* CMT_HEADER_FILE */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/readme.txt b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/readme.txt
new file mode 100644
index 00000000..736b5221
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/readme.txt
@@ -0,0 +1,41 @@
+PLEASE REFER TO THE APPLICATION NOTE FOR THIS DRIVER FOR MORE INFORMATION
+
+r_cmt_rx
+=========
+
+Overview
+--------
+This module creates a timer tick using a CMT channel based on a frequency input by the user.
+
+
+Features
+--------
+* Create periodic or one-shot timer easily by passing in desired frequency/period
+* User is alerted through callback function
+* CMT channels are allocated dynamically.
+
+
+File Structure
+--------------
+r_cmt_rx
+|   readme.txt
+|   r_cmt_rx_if.h
+|
++---doc
+|   |
+|   +---en
+|   |   r01an1856ej{VERSION_NUMBER}-rx-timer.pdf
+|   |
+|   |
+|   +---ja
+|       r01an1856jj{VERSION_NUMBER}-rx-timer.pdf
+|
++---ref
+|       r_cmt_rx_config_reference.h
+|
+\---src
+        r_cmt_rx.c
+        
+r_config
+    r_cmt_rx_config.h
+            
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/ref/r_cmt_rx_config_reference.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/ref/r_cmt_rx_config_reference.h
new file mode 100644
index 00000000..5b5a9005
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/ref/r_cmt_rx_config_reference.h
@@ -0,0 +1,49 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer 
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.    
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_cmt_rx_config.h
+* Description  : Configures the r_cmt_rx code.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+*         : 06.11.2013 2.00    First GSCE Release.
+*         : 25.11.2019 4.30    Changed for FIT+RTOS
+*         : 31.08.2020 4.70    Added condition for _RI_TRACE_TIMER macro
+*                              Fixed warning when using RI600V4 with device has 2 CMT channels
+***********************************************************************************************************************/
+#ifndef CMT_CONFIG_HEADER_FILE
+#define CMT_CONFIG_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* The interrupt priority level to be used for CMT interrupts. */
+#define CMT_RX_CFG_IPR         (5)
+
+#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == 0) /* RI600V4 */
+#define _RI_TRACE_TIMER 1 /* RI600V4 uses CMT1 channel for the trace feature.*/
+#elif (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == 1) /* RI600PX */
+#include "r_bsp_config.h"
+#define _RI_TRACE_TIMER BSP_CFG_RTOS_SYSTEM_TIMER /* RI600PX does not actually have the trace feature.*/
+#else
+#define _RI_TRACE_TIMER 1 /* It’s guaranteed that definition _RI_TRACE_TIMER is never used unless BSP_CFG_RTOS_USED == 4.*/
+#endif
+
+#endif /* CMT_CONFIG_HEADER_FILE */
+
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/src/r_cmt_rx.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/src/r_cmt_rx.c
new file mode 100644
index 00000000..1706a7d8
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_cmt_rx/src/r_cmt_rx.c
@@ -0,0 +1,1852 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer 
+*
+* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_cmt_rx.c
+* Description  : This module creates timer ticks using CMT channels or one-shot events based on period in uS. 
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+*         : 06.11.2013 2.10    First GSCE Release.
+*         : 11.03.2014 2.20    Added support for RX110.
+*                              Fixes bug in R_CMT_Control CMT_RX_CMD_GET_NUM_CHANNELS command.
+*         : 22.04.2014 2.30    Added support for RX64M.
+*         : 10.11.2014 2.40    Added support for RX113.
+*         : 20.02.2015 2.50    Added support for RX71M.
+*         : 01.04.2015 2.60    Added support for RX231.
+*         : 30.09.2015 2.70    Added support for RX23T.
+*         : 01.10.2015 2.80    Added support for RX130.
+*         : 01.12.2015 2.90    Added support for RX230, RX24T.
+*         : 15.03.2016 3.00    Added support for RX65N.
+*         : 19.12.2016 3.10    Added support for RX24U, RX24T(512KB).
+*                              Fix to stop timer before callback function is executed.
+*         : 21.07.2017 3.20    Added support for RX65N-2M, RX130-512KB.
+*         : 28.09.2018 3.30    Added support for RX66T.
+*                              Added support for RTOS.
+*                              Fixed GSCE coding rule.
+*         : 01.02.2019 3.40    Added support for RX72T, RX65N-64pin
+*                              Added new feature: get/set interrupt priority of CMT channel.
+*         : 20.05.2019 4.00    Added support for GNUC and ICCRX.
+*         : 28.06.2019 4.10    Added support for RX23W.
+*         : 15.08.2019 4.20    Added support for RX72M.
+*                              Fixed warnings in IAR.
+*         : 25.11.2019 4.30    Added support RX13T, RX66N, RX72N.
+*                              Modified comment of API function to Doxygen style.
+*                              Added support for atomic control.
+*                              Removed support for Generation 1 devices.
+*                              Fixed to comply with GSCE Coding Standards Rev.6.00.
+*                              Changed for FIT+RTOS
+*         : 29.11.2019 4.31    Fixed issues in power_on() and power_off().
+*         : 31.03.2020 4.40    Added support for RX23E-A.
+*         : 29.05.2020 4.50    Added support BLE for RX23W; CMT2, CMT3 are protected for RX23W.
+*         : 31.08.2020 4.70    Fixed warning when using RI600V4 with device has 2 CMT channels
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+#include "r_cmt_rx_config.h" /* Configuration header file */
+#include "r_cmt_rx_if.h"     /* Interface header file */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Define the number of CMT channels based on MCU type. */
+#if defined(BSP_MCU_RX64_ALL) || defined(BSP_MCU_RX113) || defined(BSP_MCU_RX71_ALL)    || \
+    defined(BSP_MCU_RX231)    || defined(BSP_MCU_RX230) || defined(BSP_MCU_RX23W) || defined(BSP_MCU_RX23T)    ||\
+    defined(BSP_MCU_RX24_ALL) || defined(BSP_MCU_RX65_ALL) || defined(BSP_MCU_RX66_ALL) || defined(BSP_MCU_RX72_ALL)
+    #define CMT_RX_NUM_CHANNELS        (4)
+#elif defined(BSP_MCU_RX111)  || defined(BSP_MCU_RX110)    || defined(BSP_MCU_RX130)  || defined(BSP_MCU_RX13T) || defined(BSP_MCU_RX23E_A)
+    #define CMT_RX_NUM_CHANNELS        (2)
+#else
+    #error "Error! Number of channels for this MCU is not defined in r_cmt_rx.c"
+#endif
+
+#if defined(BSP_MCU_RX23W)
+#undef CMT_RX_NUM_CHANNELS
+#define CMT_RX_NUM_CHANNELS (2)
+#endif /* BSP_MCU_RX23W */
+
+/* Max number of ticks for counter without overflowing/underflowing. */
+#define CMT_RX_MAX_TIMER_TICKS         (0x10000)
+
+/* Starting with RX63x MCUs, there are 2 peripheral clocks: PCLKA and PCLKB. PCLKA is only used by the Ethernet block.
+   This means that PCLKB would match functionality of PCLK in RX62x devices as far as the CMT is concerned. */
+#if defined(BSP_MCU_RX11_ALL) || defined(BSP_MCU_RX64_ALL) || defined(BSP_MCU_RX71_ALL) || defined(BSP_MCU_RX113)    || \
+    defined(BSP_MCU_RX23_ALL) || defined(BSP_MCU_RX13_ALL) || defined(BSP_MCU_RX24_ALL) || \
+    defined(BSP_MCU_RX65_ALL) || defined(BSP_MCU_RX66_ALL) || defined(BSP_MCU_RX72_ALL)
+    #define CMT_PCLK_HZ                 (BSP_PCLKB_HZ)
+#else
+    #define CMT_PCLK_HZ                 (BSP_PCLK_HZ)
+#endif
+
+/* Which MCUs have register protection. */
+#if defined(BSP_MCU_RX11_ALL) || defined(BSP_MCU_RX64_ALL) || defined(BSP_MCU_RX71_ALL) || \
+    defined(BSP_MCU_RX23_ALL) || defined(BSP_MCU_RX13_ALL) || defined(BSP_MCU_RX24_ALL) || defined(BSP_MCU_RX65_ALL) || \
+    defined(BSP_MCU_RX66_ALL) || defined(BSP_MCU_RX72_ALL)
+    #define CMT_REG_PROTECT             (1)
+#else
+    #define CMT_REG_PROTECT             (0)
+#endif
+
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+/* Enum for current mode of CMT channel. */
+typedef enum
+{
+    CMT_RX_MODE_DISABLED = 0,
+    CMT_RX_MODE_PERIODIC,
+    CMT_RX_MODE_ONE_SHOT
+} cmt_modes_t;
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* Used to prevent having duplicate code for each channel. This only works if the channels are identical (just at 
+   different locations in memory). This is easy to tell by looking in iodefine.h and seeing if the same structure
+   was used for all channels. */
+static volatile struct st_cmt0 R_BSP_EVENACCESS_SFR * const g_cmt_channels[CMT_RX_NUM_CHANNELS] =
+{
+/* Currently all RX MCUs have either 2 or 4 CMT channels. */
+#if   CMT_RX_NUM_CHANNELS == 4
+    /* MCUs have 4 CMT channels. */
+    &CMT0, &CMT1, &CMT2, &CMT3
+#elif CMT_RX_NUM_CHANNELS == 2
+    &CMT0, &CMT1
+#else
+    #error "Error! r_cmt_rx is not setup for this many CMT channels. Please refer to g_cmt_channels[] in r_cmt_rx.c"
+#endif
+};
+
+/* Holds current mode of each CMT channel. */
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+static cmt_modes_t g_cmt_modes[CMT_RX_NUM_CHANNELS];
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+#if   CMT_RX_NUM_CHANNELS == 4
+    #if BSP_CFG_RTOS_SYSTEM_TIMER == 0
+        static cmt_modes_t g_cmt_modes[CMT_RX_NUM_CHANNELS] = {CMT_RX_MODE_PERIODIC, CMT_RX_MODE_DISABLED, CMT_RX_MODE_DISABLED, CMT_RX_MODE_DISABLED };
+    #elif BSP_CFG_RTOS_SYSTEM_TIMER == 1
+        static cmt_modes_t g_cmt_modes[CMT_RX_NUM_CHANNELS] = {CMT_RX_MODE_DISABLED, CMT_RX_MODE_PERIODIC, CMT_RX_MODE_DISABLED, CMT_RX_MODE_DISABLED };
+    #elif BSP_CFG_RTOS_SYSTEM_TIMER == 2
+        static cmt_modes_t g_cmt_modes[CMT_RX_NUM_CHANNELS] = {CMT_RX_MODE_DISABLED, CMT_RX_MODE_DISABLED, CMT_RX_MODE_PERIODIC, CMT_RX_MODE_DISABLED };
+    #elif BSP_CFG_RTOS_SYSTEM_TIMER == 3
+        static cmt_modes_t g_cmt_modes[CMT_RX_NUM_CHANNELS] = {CMT_RX_MODE_DISABLED, CMT_RX_MODE_DISABLED, CMT_RX_MODE_DISABLED, CMT_RX_MODE_PERIODIC };
+    #else
+        #error "Error! Invalid channel"
+    #endif
+#elif CMT_RX_NUM_CHANNELS == 2
+    #if BSP_CFG_RTOS_SYSTEM_TIMER == 0
+        static cmt_modes_t g_cmt_modes[CMT_RX_NUM_CHANNELS] = {CMT_RX_MODE_PERIODIC, CMT_RX_MODE_DISABLED };
+    #elif BSP_CFG_RTOS_SYSTEM_TIMER == 1
+        static cmt_modes_t g_cmt_modes[CMT_RX_NUM_CHANNELS] = {CMT_RX_MODE_DISABLED, CMT_RX_MODE_PERIODIC };
+    #else
+        #error "Error! Invalid channel"
+    #endif
+#else
+    #error "Error! r_cmt_rx is not setup for this many CMT channels. Please refer to g_cmt_channels[] in r_cmt_rx.c"
+#endif
+//#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+//#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+/* CMT 1 or 2 channels are reserved for System & Trace timer. */
+static cmt_modes_t g_cmt_modes[CMT_RX_NUM_CHANNELS] = {
+    /*---------- CMT0 initial value ----------*/
+#if BSP_CFG_RTOS_SYSTEM_TIMER==0 || _RI_TRACE_TIMER==0
+     CMT_RX_MODE_PERIODIC /* CMT0 is reserved for RI600V4/RI600PX. */
+#else
+     CMT_RX_MODE_DISABLED /* CMT0 is unused. */
+#endif
+    /*---------- CMT1 initial value ----------*/
+#if BSP_CFG_RTOS_SYSTEM_TIMER==1 || _RI_TRACE_TIMER==1
+    ,CMT_RX_MODE_PERIODIC  /* CMT1 is reserved for RI600V4/RI600PX. */
+#else
+    ,CMT_RX_MODE_DISABLED  /* CMT1 is unused. */
+#endif
+    /*-------------------- 2 pairs of CMT --------------------*/
+#if CMT_RX_NUM_CHANNELS > 2
+    /*---------- CMT2 initial value ----------*/
+#if BSP_CFG_RTOS_SYSTEM_TIMER == 2 || _RI_TRACE_TIMER==2
+    ,CMT_RX_MODE_PERIODIC /* CMT2 is reserved for RI600V4/RI600PX. */
+#else
+    ,CMT_RX_MODE_DISABLED /* CMT2 is unused. */
+#endif
+    /*---------- CMT3 initial value ----------*/
+#if BSP_CFG_RTOS_SYSTEM_TIMER == 3 || _RI_TRACE_TIMER==3
+    ,CMT_RX_MODE_PERIODIC  /* CMT3 is reserved for RI600V4/RI600PX. */
+#else
+    ,CMT_RX_MODE_DISABLED  /* CMT3 is unused. */
+#endif
+    /*--------------------------------------------------------*/
+#endif/* CMT_RX_NUM_CHANNELS */
+};
+#else /* Non-OS & others */
+static cmt_modes_t g_cmt_modes[CMT_RX_NUM_CHANNELS];
+#endif/* BSP_CFG_RTOS_USED */
+
+/* This array holds the available clock dividers. For example, if PCLK/8 is available, then '8' would be an entry.
+   Note that the index of the divider in the array should correspond to the bit setting used for the CKS[1:0] bitfield.
+   For example, 128 is at index 2 in the array and to choose PCLK/128 in the CMCR register you would set the CKS[1:0] 
+   bitfield to 2. */
+static const uint32_t g_cmt_clock_dividers[] = { 8, 32, 128, 512 };
+
+/* Array that holds user's callback functions. */
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+static void  (* g_cmt_callbacks[CMT_RX_NUM_CHANNELS])(void * pdata);
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+static void  (* g_cmt_callbacks[CMT_RX_NUM_CHANNELS])(void * pdata);
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+    #if CMT_RX_NUM_CHANNELS == 2
+        #if ((BSP_CFG_RTOS_SYSTEM_TIMER != 0 && _RI_TRACE_TIMER != 0) ||\
+            (BSP_CFG_RTOS_SYSTEM_TIMER != 1 && _RI_TRACE_TIMER != 1))
+static void  (* g_cmt_callbacks[CMT_RX_NUM_CHANNELS])(void * pdata);
+        #endif
+    #else
+            static void  (* g_cmt_callbacks[CMT_RX_NUM_CHANNELS])(void * pdata);
+    #endif
+#else
+            static void  (* g_cmt_callbacks[CMT_RX_NUM_CHANNELS])(void * pdata);
+#endif
+
+/* Internal functions. */
+static bool cmt_lock_state(void);
+static void cmt_unlock_state(void);
+static bool cmt_find_channel(uint32_t * channel);
+static void power_on(uint32_t channel);
+static void power_off(uint32_t channel);
+static void cmt_counter_start(uint32_t channel);
+static void cmt_counter_start_priority(uint32_t channel, cmt_priority_t priority);
+static void cmt_counter_stop(uint32_t channel);
+static bool cmt_setup_channel(uint32_t channel, uint32_t frequency_hz);
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+static void cmt_isr_common(uint32_t channel);
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+static void cmt_isr_common(uint32_t channel);
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+    #if CMT_RX_NUM_CHANNELS == 2
+        #if ((BSP_CFG_RTOS_SYSTEM_TIMER != 0 && _RI_TRACE_TIMER != 0) ||\
+            (BSP_CFG_RTOS_SYSTEM_TIMER != 1 && _RI_TRACE_TIMER != 1))
+            static void cmt_isr_common(uint32_t channel);
+        #endif
+    #else
+        static void cmt_isr_common(uint32_t channel);
+    #endif
+#else
+static void cmt_isr_common(uint32_t channel);
+#endif
+static bool cmt_create(uint32_t frequency_hz, void (* callback)(void * pdata), cmt_modes_t mode, uint32_t * channel);
+static bool cmt_create_priority(uint32_t frequency_hz, void (* callback)(void * pdata), cmt_modes_t mode, uint32_t channel, cmt_priority_t priority);
+
+/***********************************************************************************************************************
+* Function Name: R_CMT_CreatePeriodic
+********************************************************************************************************************//**
+* @brief This function finds an unused CMT channel, configures it for the requested frequency,
+* associates a user callback function with the timer’s interrupt, and powers up and starts the timer
+* @param[in] frequency_hz Desired frequency in Hz. The range and resolution of the timer is determined by settings of the peripheral clock.
+* The best pre-scaler for the CMT channel is chosen by the driver.\n
+* @param[in] callback Pointer to the user’s callback function.  It should receive a single void * argument.\n
+* @param[in] *channel The CMT FIT module finds the first CMT channel that is not in use and assigns it to the caller.
+* This allows multiple drivers to use the CMT driver without having to pre-assign all timer channels.
+* This argument provides a way for the driver to indicate back to the caller which channel has been assigned.\n
+* @retval true  Successful; CMT initialized
+* @retval false     No free CMT channels available, or invalid settings
+* @details The R_CMT_CreatePeriodic function finds an unused CMT channel, assigns it to the caller,
+* and registers a user callback function to be called upon compare match events.\n
+* The CMT is configured to generate compare matches at the frequency specified in the call.\n
+* @note 1.  Maximum periodic frequency\n
+* In hardware, the CMT timer maximum clocking speed is limited to PCLK/8.
+* However, when using the periodic timer function to generate a clock, be aware that interrupt and callback processing takes some time.
+* As requested frequency rises, interrupt and callback processing will take an increasing percentage of the processor’s time.
+* At some point, too much time is consumed to leave any time for other useful work.
+* So this will limit the maximum frequency that can be generated.
+*  The maximum practical frequency will depend on your system design, but in general, frequencies up to a few kilohertz are reasonable.\n
+*/
+bool R_CMT_CreatePeriodic (uint32_t frequency_hz, void (* callback)(void * pdata), uint32_t * channel)
+{
+    return cmt_create(frequency_hz, callback, CMT_RX_MODE_PERIODIC, channel);
+} 
+/* End of function R_CMT_CreatePeriodic */
+
+/***********************************************************************************************************************
+* Function Name: R_CMT_CreatePeriodicAssignChannelPriority
+* ******************************************************************************************************************//**
+* @brief This function configures desired CMT channel for the requested frequency and desired interrupt priority level,
+* associates a user callback function with the timer’s interrupt, powers up and starts the timer
+* @param[in] frequency_hz Desired frequency in Hz. The range and resolution of the timer is determined by settings of the peripheral clock.
+* The best pre-scaler for the CMT channel is chosen by the driver.\n
+* @param[in] callback Pointer to the user’s callback function. It should receive a single void * argument.\n
+* @param[in] channel Desired CMT channel that is used to configure.\n
+* @param[in] priority Desired priority level of timer’s interrupt:\n
+* CMT_PRIORITY_0: Interrupt is disabled\n
+* CMT_PRIORITY_1: Lowest interrupt priority\n
+* CMT_PRIORITY_2\n
+* CMT_PRIORITY_3\n
+* CMT_PRIORITY_4\n
+* CMT_PRIORITY_5\n
+* CMT_PRIORITY_6\n
+* CMT_PRIORITY_7\n
+* CMT_PRIORITY_8\n
+* CMT_PRIORITY_9\n
+* CMT_PRIORITY_10\n
+* CMT_PRIORITY_11\n
+* CMT_PRIORITY_12\n
+* CMT_PRIORITY_13\n
+* CMT_PRIORITY_14\n
+* CMT_PRIORITY_15: Highest interrupt priority\n
+* @retval true  Successful; CMT initialized\n
+* @retval false     No free CMT channels available, or invalid settings\n
+* @details The R_CMT_CreatePeriodicAssignChannelPriority assigns desired CMT channel to the caller with desired
+* interrupt priority level and registers a user callback function to be called upon compare match events.
+* The CMT is configured to generate compare matches at the frequency specified in the call.\n
+* @note 1.  Maximum periodic frequency\n
+* In hardware, the CMT timer maximum clocking speed is limited to PCLK/8.
+* However, when using the periodic timer function to generate a clock, be aware that interrupt and callback processing takes some time.
+* As requested frequency rises, interrupt and callback processing will take an increasing percentage of the processor’s time.
+* At some point, too much time is consumed to leave any time for other useful work.
+* So this will limit the maximum frequency that can be generated.
+*  The maximum practical frequency will depend on your system design, but in general, frequencies up to a few kilohertz are reasonable.\n
+*/
+bool R_CMT_CreatePeriodicAssignChannelPriority (uint32_t frequency_hz, void (* callback)(void * pdata), uint32_t channel, cmt_priority_t priority)
+{
+    return cmt_create_priority(frequency_hz, callback, CMT_RX_MODE_PERIODIC, channel, priority);
+}
+/* End of function R_CMT_CreatePeriodicAssignChannelPriority */
+
+/***********************************************************************************************************************
+* Function Name: R_CMT_CreateOneShot
+* ******************************************************************************************************************//**
+ @brief This function finds an unused CMT channel, configures it for the requested period,
+* associates a user callback function with the timer’s interrupt, and powers up and starts the timer
+* @param[in] period_us Desired period in microseconds.
+* The range and resolution of the timer is determined by settings of the peripheral clock.
+* The best pre-scaler for the CMT channel is chosen by the driver.\n
+* @param[in] callback Pointer to the user’s callback function.  It should data a single void * argument.\n
+* @param[in] channel The CMT FIT module finds the first CMT channel that is not in use and assigns it to the caller.
+* This allows multiple drivers to use the CMT driver without having to pre-assign all timer channels.
+* This argument provides a way for the driver to indicate back to the caller which channel has been assigned.\n
+* @retval true  Successful; CMT initialized\n
+* @retval false     No free CMT channels available, or invalid settings\n
+* @details The R_CMT_CreateOneShot function finds an unused CMT channel, assigns it to the caller,
+*  and registers a user callback function to be called upon the compare match event.\n
+* The CMT is configured to generate a compare match after the period specified in the call.
+* The timer is shut down after a single compare match event.\n
+*/
+bool R_CMT_CreateOneShot (uint32_t period_us, void (* callback)(void * pdata), uint32_t * channel)
+{    
+    return cmt_create((1000000/period_us), callback, CMT_RX_MODE_ONE_SHOT, channel);
+}
+/* End of function R_CMT_CreateOneShot */
+
+/***********************************************************************************************************************
+* Function Name: R_CMT_CreateOneShotAssignChannelPriority
+********************************************************************************************************************//**
+* @brief This function configures the desired CMT channel for the requested period with desired interrupt priority level,
+* associates a user callback function with the timer’s interrupt, powers up and starts the timer
+* @param[in] period_us Desired period in microseconds.
+* The range and resolution of the timer is determined by settings of the peripheral clock.
+* The best pre-scaler for the CMT channel is chosen by the driver.\n
+* @param[in] callback Pointer to the user’s callback function. It should data a single void * argument.\n
+* @param[in] channel Desired CMT channel that is used to configure.\n
+* @param[in] priority Desired priority level of timer’s interrupt:\n
+* CMT_PRIORITY_0: Interrupt is disabled\n
+* CMT_PRIORITY_1: Lowest interrupt priority\n
+* CMT_PRIORITY_2\n
+* CMT_PRIORITY_3\n
+* CMT_PRIORITY_4\n
+* CMT_PRIORITY_5\n
+* CMT_PRIORITY_6\n
+* CMT_PRIORITY_7\n
+* CMT_PRIORITY_8\n
+* CMT_PRIORITY_9\n
+* CMT_PRIORITY_10\n
+* CMT_PRIORITY_11\n
+* CMT_PRIORITY_12\n
+* CMT_PRIORITY_13\n
+* CMT_PRIORITY_14\n
+* CMT_PRIORITY_15: Highest interrupt priority\n
+* @retval true  Successful; CMT initialized\n
+* @retval false     No free CMT channels available, or invalid settings\n
+* @details The R_CMT_CreateOneShotAssignChannelPriority assigns the desired
+* CMT channel to the caller with desired interrupt priority level,
+* and registers a user callback function to be called upon the compare match event.
+* The CMT is configured to generate a compare match after the period specified in the call.
+* The timer is shut down after a single compare match event.\n
+* @note 1.  Invalid settings\n
+* The function will return false if one of the following invalid settings occurs:
+* invalid channel, invalid priority, channel was in used, or frequency could not be used.\n
+*/
+bool R_CMT_CreateOneShotAssignChannelPriority (uint32_t period_us, void (* callback)(void * pdata), uint32_t channel, cmt_priority_t priority)
+{
+    return cmt_create_priority((1000000/period_us), callback, CMT_RX_MODE_ONE_SHOT, channel, priority);
+}
+/* End of function R_CMT_CreateOneShotAssignChannelPriority */
+
+/***********************************************************************************************************************
+* Function Name: R_CMT_Stop
+********************************************************************************************************************//**
+* @brief Stops a CMT channel and powers down the CMT unit if possible
+* @param[in] channel The CMT timer channel to stop\n
+* @retval true  Successful; CMT closed\n
+* @retval false     Invalid settings \n
+* @details This function frees the CMT channel by clearing its assignment and disabling the associated interrupt.
+* The CMT channel cannot be used again until it has been reopened with either 
+* the R_CMT_CreatePeriodic or the R_CMT_CreateOneShot function.
+* If the CMT channel is already used as RTOS system timer, a call to this function with this CMT channel as channel,
+* will result in FALSE being returned
+*/
+bool R_CMT_Stop (uint32_t channel)
+{
+    /* Make sure valid channel number was input. */
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+    if (channel >= CMT_RX_NUM_CHANNELS)
+#elif BSP_CFG_RTOS_USED == 1        /* FreeRTOS */
+    if ((channel >= CMT_RX_NUM_CHANNELS) || (BSP_CFG_RTOS_SYSTEM_TIMER == channel))
+//#elif BSP_CFG_RTOS_USED == 2  /* SEGGER embOS */
+//#elif BSP_CFG_RTOS_USED == 3  /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED   == 4  /* Renesas RI600V4 & RI600PX */
+    if ((channel >= CMT_RX_NUM_CHANNELS) || (BSP_CFG_RTOS_SYSTEM_TIMER == channel) || (_RI_TRACE_TIMER == channel))
+#else /* Non-OS & others */
+    if (channel >= CMT_RX_NUM_CHANNELS)
+#endif/* BSP_CFG_RTOS_USED */
+    {
+        /* Invalid channel number was used.*/
+        /*In case using RX23W, Channel 2 and 3 are reserved by BLE FIT modules v.1.00*/
+        return false;
+    }
+
+    /* Stop counter. */
+    cmt_counter_stop(channel);
+
+    /* Turn off power to channel. */
+    power_off(channel);
+
+    /* Set mode to disabled. */
+    g_cmt_modes[channel] = CMT_RX_MODE_DISABLED;
+
+    /* Set channel as available. */
+    R_BSP_HardwareUnlock((mcu_lock_t)(BSP_LOCK_CMT0 + channel));
+
+    return true;
+} /* End of function R_CMT_Stop */
+
+/***********************************************************************************************************************
+* Function Name: R_CMT_Control
+********************************************************************************************************************//**
+* @brief This function provides various ways to control and monitor a CMT channel
+* @param[in] channel CMT channel number to control.\n
+* @param[in] command Command to execute:\n
+* CMT_RX_CMD_IS_CHANNEL_COUNTING\n
+* CMT_RX_CMD_PAUSE\n
+* CMT_RX_CMD_RESUME\n
+* CMT_RX_CMD_RESTART\n
+* CMT_RX_CMD_GET_NUM_CHANNELS\n
+* CMT_RX_CMD_SET_PRIORITY\n
+* CMT_RX_CMD_GET_PRIORITY\n
+* @param[in] *pdata
+* @retval true  The command completed properly. Check pdata
+* @retval false     The command did not complete properly
+* @details This function provides a number of commands:\n
+* CMT_RX_CMD_IS_CHANNEL_COUNTING tells if a CMT channel is currently running.  Check *pdata.\n
+* CMT_RX_CMD_PAUSE pauses a timer without closing it (without powering it off).\n
+* CMT_RX_CMD_RESUME restarts a paused timer without resetting the counter to zero\n
+* CMT_RX_CMD_RESTART restarts a paused timer after resetting the counter to zero\n
+* CMT_RX_CMD_GET_NUM_CHANNELS returns the total number of channels available\n
+* CMT_RX_CMD_SET_PRIORITY sets the interrupt priority of the CMT channel.\n
+* CMT_RX_CMD_GET_PRIORITY gets the interrupt priority of the CMT channel.\n
+* If the CMT channel is already used as RTOS system timer, a call to this function with this CMT channel as channel,
+* and any of CMT_RX_CMD_IS_CHANNEL_COUNTING, CMT_RX_CMD_PAUSE,
+* CMT_RX_CMD_RESUME, CMT_RX_CMD_RESTART as command, will result in FALSE being returned.
+*/
+bool R_CMT_Control (uint32_t channel, cmt_commands_t command, void * pdata)
+{
+    bool ret = true;
+    cmt_priority_t priority;
+
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+    if (CMT_RX_CMD_GET_NUM_CHANNELS == command)
+    {
+        /* Return the number of CMT channels on this MCU. */
+        *(uint32_t *)pdata = CMT_RX_NUM_CHANNELS;
+        ret = true;
+        return ret;
+    }
+    else if ((channel == BSP_CFG_RTOS_SYSTEM_TIMER) || (channel >= CMT_RX_NUM_CHANNELS))
+    {
+        /* Specified CMT channel is being used by RTOS or Invalid channel */
+        /* Modifying is NOT allowed for the other commands. */
+        ret = false;
+        return ret;
+    }
+    else
+    {
+        /* Do nothing. */
+    }
+//#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+//#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+
+    if (CMT_RX_CMD_GET_NUM_CHANNELS == command)
+    {
+        /* Return the number of CMT channels on this MCU. */
+        *(uint32_t *)pdata = CMT_RX_NUM_CHANNELS;
+        ret = true;
+        return ret;
+    }
+    else if ((channel == BSP_CFG_RTOS_SYSTEM_TIMER) || (channel == _RI_TRACE_TIMER) || (channel >= CMT_RX_NUM_CHANNELS))
+    {
+        /* Specified CMT channel is being used by RTOS or Invalid channel */
+        /* Modifying is NOT allowed for the other commands. */
+        ret = false;
+        return ret;
+    }
+    else
+    {
+        /* Do nothing. */
+    }
+#else /* Non-OS & others */
+#endif/* BSP_CFG_RTOS_USED */
+
+    /* Process command that was input. */
+    switch (command)
+    {
+        case CMT_RX_CMD_IS_CHANNEL_COUNTING:
+        {
+            /* Check input channel. */
+            if (channel < CMT_RX_NUM_CHANNELS)
+            {
+                /* Valid channel input. Is this channel currently counting? */
+                if (CMT_RX_MODE_DISABLED == g_cmt_modes[channel])
+                {
+                    /* pdata = false*/
+                    *(bool *)pdata = false;
+                }
+                else
+                {
+                    /* pdata = true*/
+                    *(bool *)pdata = true;
+                }
+            }
+            else
+            {
+                ret = false;
+            }
+            break;
+        }
+#if BSP_CFG_RTOS_USED == 0   /*Unreachable code because of checksabove*/
+        case CMT_RX_CMD_GET_NUM_CHANNELS:
+        {
+            /* number of CMT channels */
+            *(uint32_t *)pdata = CMT_RX_NUM_CHANNELS;
+            break;
+        }
+#endif
+        case CMT_RX_CMD_PAUSE:
+        {
+            if (channel < CMT_RX_NUM_CHANNELS)
+            {
+                /* Valid channel input. Is this channel currently counting? */
+                if (CMT_RX_MODE_DISABLED != g_cmt_modes[channel])
+                {
+
+                    switch (channel)
+                    {
+                        case 0:
+                        {
+                            /*CMT0.CMCNT count is stopped*/
+                            CMT.CMSTR0.BIT.STR0 = 0;
+                            break;
+                        }
+                        case 1:
+                        {
+                            /*CMT1.CMCNT count is stopped*/
+                            CMT.CMSTR0.BIT.STR1 = 0;
+                            break;
+                        }
+                        #if   CMT_RX_NUM_CHANNELS == 4
+                        case 2:
+                        {
+                            /*CMT2.CMCNT count is stopped*/
+                            CMT.CMSTR1.BIT.STR2 = 0;
+                            break;
+                        }
+                        case 3:
+                        {
+                            /*CMT3.CMCNT count is stopped*/
+                            CMT.CMSTR1.BIT.STR3 = 0;
+                            break;
+                        }
+                        #endif
+
+                        default:
+                        {
+                            break;
+                        }
+                    }
+                }
+            }
+            else
+            {
+                ret = false;
+            }
+            break;
+        }
+
+        /* Both restart and resume do the same thing, except restart zeros the counter first */ 
+        case CMT_RX_CMD_RESTART:
+        case CMT_RX_CMD_RESUME:
+        {
+            if (channel < CMT_RX_NUM_CHANNELS)
+            {
+                /* Stop the timer once to prevent an interrupt from occurring */
+                switch (channel)
+                {
+                    case 0:
+                    {
+                        /*CMT0.CMCNT count is stopped*/
+                        CMT.CMSTR0.BIT.STR0 = 0;
+                        break;
+                    }
+                    case 1:
+                    {
+                        /*CMT1.CMCNT count is stopped*/
+                        CMT.CMSTR0.BIT.STR1 = 0;
+                        break;
+                    }
+#if   CMT_RX_NUM_CHANNELS == 4
+                    case 2:
+                    {
+                        /*CMT2.CMCNT count is stopped*/
+                        CMT.CMSTR1.BIT.STR2 = 0;
+                        break;
+                    }
+                    case 3:
+                    {
+                        /*CMT3.CMCNT count is stopped*/
+                        CMT.CMSTR1.BIT.STR3 = 0;
+                        break;
+                    }
+#endif
+                    default:
+                    {
+                        break;
+                    }
+                }
+
+                /* Valid channel input. Is this channel currently counting? */
+                if (CMT_RX_MODE_DISABLED != g_cmt_modes[channel])
+                {
+
+                    if (CMT_RX_CMD_RESTART == command)
+                    {
+                      /* For restarting, clear counter. */
+                      (*g_cmt_channels[channel]).CMCNT = 0;
+                    }
+
+                    switch (channel)
+                    {
+                        case 0:
+                        {
+                            /*CMT0.CMCNT count is started*/
+                            CMT.CMSTR0.BIT.STR0 = 1;
+                            break;
+                        }
+                        case 1:
+                        {
+                            /*CMT1.CMCNT count is started*/
+                            CMT.CMSTR0.BIT.STR1 = 1;
+                            break;
+                        }
+#if   CMT_RX_NUM_CHANNELS == 4
+                        case 2:
+                        {
+                            /*CMT2.CMCNT count is started*/
+                            CMT.CMSTR1.BIT.STR2 = 1;
+                            break;
+                        }
+                        case 3:
+                        {
+                            /*CMT3.CMCNT count is started*/
+                            CMT.CMSTR1.BIT.STR3 = 1;
+                            break;
+                        }
+#endif
+                        default:
+                        {
+                            break;
+                        }
+                    }
+                }
+            }
+            else
+            {
+                ret = false;
+            }
+            break;
+        }
+        case CMT_RX_CMD_SET_PRIORITY:
+        {
+            /* Make sure that pdata is NOT NULL */
+            if (NULL == pdata)
+            {
+                ret = false;
+            }
+            else
+            {
+                /* Get input priority value from pdata */
+                priority = *(cmt_priority_t *)pdata;
+            }
+
+            /* Check if interrupt priority and channel are correct or not */
+            if (true == ret)
+            {
+                if ((CMT_PRIORITY_0 > (int8_t) priority)
+                 || (CMT_PRIORITY_MAX < priority)
+                 || (CMT_RX_NUM_CHANNELS <= channel))
+                {
+                    ret = false;
+                }
+            }
+
+            if (true == ret)
+            {
+                /* Acquire lock on input channel to check if it was created or not */
+                if (true == R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + channel)))
+                {
+                    /* Channel is NOT created yet, release lock on channel */
+                    R_BSP_HardwareUnlock((mcu_lock_t)(BSP_LOCK_CMT0 + channel));
+
+                    /* Set return value to false */
+                    ret = false;
+                }
+                else
+                {
+                    switch (channel)
+                    {
+                        case 0:
+                        {
+                            /* Set interrupt priority using ICU register. */
+                            IPR(CMT0, CMI0) = priority;
+                            break;
+                        }
+
+                        case 1:
+                        {
+                            /* Set interrupt priority using ICU register. */
+                            IPR(CMT1, CMI1) = priority;
+                            break;
+                        }
+
+#if CMT_RX_NUM_CHANNELS == 4
+                        case 2:
+                        {
+                            /* Set interrupt priority using ICU register. */
+                            IPR(CMT2, CMI2) = priority;
+                            break;
+                        }
+
+                        case 3:
+                        {
+                            /* Set interrupt priority using ICU register. */
+                            IPR(CMT3, CMI3) = priority;
+                            break;
+                        }
+
+#endif
+                        default:
+                        {
+                            /* Should never get here. */
+                            R_BSP_NOP();
+                            break;
+                        }
+                    }
+                }
+            }
+        }
+            break;
+        
+        case CMT_RX_CMD_GET_PRIORITY:
+        {
+            /* Make sure that CMT channel is correct, pdata is NOT NULL */
+            if ((CMT_RX_NUM_CHANNELS <= channel) || (NULL == pdata))
+            {
+                ret = false;
+            }
+            else
+            {
+                switch(channel)
+                {
+                    case 0:
+                    {
+                        /* Get priority of CMT channel 0 from IPR register */
+                        priority = (cmt_priority_t)IPR(CMT0, CMI0);
+                        break;
+                    }
+
+                    case 1:
+                    {
+                        /* Get priority of CMT channel 1 from IPR register */
+                        priority = (cmt_priority_t)IPR(CMT1, CMI1);
+                        break;
+                    }
+
+#if CMT_RX_NUM_CHANNELS == 4
+                    case 2:
+                    {
+                        /* Get priority of CMT channel 2 from IPR register */
+                        priority = (cmt_priority_t)IPR(CMT2, CMI2);
+                        break;
+                    }
+
+                    case 3:
+                    {
+                        /* Get priority of CMT channel 3 from IPR register */
+                        priority = (cmt_priority_t)IPR(CMT3, CMI3);
+                        break;
+                    }
+                    
+                    default:
+                    {
+                        /* Should never get here. */
+                        ret = false;
+                        break;
+                    }
+#endif
+                }
+
+                /* Update pdata value with priority for output */
+                *(cmt_priority_t *)pdata = priority;
+            }
+            break;
+        }
+
+        default:
+        {
+            ret = false;
+            break;
+        }
+    }
+
+    return ret;
+}
+/***********************************************************************************************************************
+* End of function R_CMT_Control
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: cmt_create
+* Description  : Sets up a CMT channel based on user input options.
+* Arguments    : frequency_hz -
+*                    Frequency in Hz of how often to call the callback function.
+*                callback -
+*                    Which function to call when timer expires.
+*                mode -
+*                    Current mode of CMT channel
+*                channel -
+*                    Pointer of where to store which channel was used.
+* Return Value : true - 
+*                    Channel initialized successfully.
+*                false -
+*                    Invalid channel or period could not be used.
+***********************************************************************************************************************/
+static bool cmt_create (uint32_t frequency_hz, void (* callback)(void * pdata), cmt_modes_t mode, uint32_t * channel)
+{
+    /* Return value. */
+    bool     ret = false;    
+
+    /* Grab state to make sure we do not interfere with another operation. */
+    if (cmt_lock_state() != true)
+    {
+        /* Another operation is already in progress. */
+        return false;
+    }
+
+    /* Was a channel found? */
+    if (false == cmt_find_channel(channel))
+    {
+        /* Channel not found or not available. */
+        ret = false;
+    }
+    else
+    {
+        /* Look to see if we can support this frequency. */
+        ret = cmt_setup_channel(*channel, frequency_hz);
+    
+        /* Set up ICU registers, save callback function, and start counter if valid divider was found. */
+        if (true == ret)
+        {        
+            /* Set mode of operation. */
+            g_cmt_modes[*channel] = mode;
+    
+            /* Save callback function to be used. */
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+            g_cmt_callbacks[*channel] = callback;
+#elif BSP_CFG_RTOS_USED == 1        /* FreeRTOS */
+            g_cmt_callbacks[*channel] = callback;
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+    #if CMT_RX_NUM_CHANNELS == 2
+        #if ((BSP_CFG_RTOS_SYSTEM_TIMER != 0 && _RI_TRACE_TIMER != 0) ||\
+            (BSP_CFG_RTOS_SYSTEM_TIMER != 1 && _RI_TRACE_TIMER != 1))
+            g_cmt_callbacks[*channel] = callback;
+        #endif
+    #else
+            g_cmt_callbacks[*channel] = callback;
+    #endif
+#else
+            g_cmt_callbacks[*channel] = callback;
+#endif
+
+    
+            /* Start channel counting. */
+            cmt_counter_start(*channel);
+        }
+        else
+        {
+            /* Could not support input frequency. Release lock on channel. */
+            R_BSP_HardwareUnlock((mcu_lock_t)(BSP_LOCK_CMT0 + (*channel)));
+        }
+    }
+
+    /* Release state so other operations can be performed. */
+    cmt_unlock_state();
+
+    return ret;
+}
+/* End of function cmt_create */
+
+/***********************************************************************************************************************
+* Function Name: cmt_create_priority
+* Description  : Sets up a CMT channel based on user input options with interrupt priority.
+* Arguments    : frequency_hz -
+*                    Frequency in Hz of how often to call the callback function.
+*                callback -
+*                    Which function to call when timer expires.
+*                mode -
+*                    Current mode of CMT channel
+*                channel -
+*                    Which channel is used to create.
+*                priority -
+*                    Which interrupt priority is used to assign.
+* Return Value : true -
+*                    Channel initialized successfully.
+*                false -
+*                    Invalid channel, invalid priority, channel was in used, or frequency could not be used.
+***********************************************************************************************************************/
+static bool cmt_create_priority (uint32_t frequency_hz, void (* callback)(void * pdata), cmt_modes_t mode, uint32_t channel, cmt_priority_t priority)
+{
+    /* Return value. */
+    bool     ret = false;
+
+    /* Check if interrupt priority and channel are correct or not. */
+    if ((CMT_PRIORITY_0 > (int8_t) priority) || (CMT_PRIORITY_MAX < priority) || (CMT_RX_NUM_CHANNELS <= channel))
+    {
+        return false;
+    }
+
+    /* Grab state to make sure we do not interfere with another operation. */
+    if (cmt_lock_state() != true)
+    {
+        /* Another operation is already in progress. */
+        return false;
+    }
+
+    /* Acquire lock on input channel. If return value is true then this channel is NOT in use. */
+    if (true == R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + channel)))
+    {
+        /* Look to see if we can support this frequency. */
+        ret = cmt_setup_channel(channel, frequency_hz);
+
+        /* Set up ICU registers, save callback function, and start counter if valid divider was found. */
+        if (true == ret)
+        {
+            /* Set mode of operation. */
+            g_cmt_modes[channel] = mode;
+
+            /* Save callback function to be used. */
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+            g_cmt_callbacks[channel] = callback;
+#elif BSP_CFG_RTOS_USED == 1        /* FreeRTOS */
+            g_cmt_callbacks[channel] = callback;
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+    #if CMT_RX_NUM_CHANNELS == 2
+        #if ((BSP_CFG_RTOS_SYSTEM_TIMER != 0 && _RI_TRACE_TIMER != 0) ||\
+            (BSP_CFG_RTOS_SYSTEM_TIMER != 1 && _RI_TRACE_TIMER != 1))
+            g_cmt_callbacks[channel] = callback;
+        #endif
+    #else
+            g_cmt_callbacks[channel] = callback;
+    #endif
+#else
+            g_cmt_callbacks[channel] = callback;
+#endif
+
+            /* Start channel counting. */
+            cmt_counter_start_priority(channel, priority);
+        }
+        else
+        {
+            /* Could not support input frequency. Release lock on channel. */
+            R_BSP_HardwareUnlock((mcu_lock_t)(BSP_LOCK_CMT0 + (channel)));
+        }
+    }
+
+    /* Release state so other operations can be performed. */
+    cmt_unlock_state();
+
+    return ret;
+}
+/* End of function cmt_create_priority */
+
+/***********************************************************************************************************************
+* Function Name: cmt_lock_state
+* Description  : Attempt to lock the state so that we right to perform an operation.
+* Arguments    : none
+* Return Value : true - 
+*                    State was obtained
+*                false - 
+*                    State was not obtained because code is busy with another on-going operation.
+***********************************************************************************************************************/
+static bool cmt_lock_state (void)
+{
+    bool ret;
+
+    /* Attempt to acquire lock. */
+    ret = R_BSP_HardwareLock(BSP_LOCK_CMT);
+
+    return ret;
+}
+/* End of function cmt_lock_state */
+
+/***********************************************************************************************************************
+* Function Name: cmt_unlock_state
+* Description  : Release state so that other operations can be performed.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+static void cmt_unlock_state (void)
+{
+    /* Release lock. */
+    R_BSP_HardwareUnlock(BSP_LOCK_CMT);
+}
+/* End of function cmt_unlock_state */
+
+/***********************************************************************************************************************
+* Function Name: cmt_find_channel
+* Description  : Attempt to find open CMT channel to use.
+* Arguments    : channel - 
+*                    Channel number if channel was found.
+* Return Value : true -
+*                    Channel was found and locked.
+*                false -
+*                    No channels available.
+***********************************************************************************************************************/
+static bool cmt_find_channel (uint32_t * channel)
+{
+    bool     channel_found = false;
+    uint32_t i;
+
+    /* Look for an available channel. */
+    /* WAIT_LOOP */
+    for (i = 0; i < CMT_RX_NUM_CHANNELS; i++)
+    {
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+        if (i == BSP_CFG_RTOS_SYSTEM_TIMER)
+        {
+            /* Found CMT channel is being used for RTOS. */
+            continue;
+        }
+//#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+//#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+        if (i == BSP_CFG_RTOS_SYSTEM_TIMER || i == _RI_TRACE_TIMER)
+        {
+            /* Found CMT channel is being used for RTOS. */
+            continue;
+        }
+#else /* Non-OS & others */
+#endif/* BSP_CFG_RTOS_USED */
+        /* Look for an available channel. */
+        if (true == R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + i)))
+        {
+            /* Channel found. */
+            *channel = i;
+            channel_found = true;
+            
+            break;            
+        }
+    }        
+
+    return channel_found;
+}
+/* End of function cmt_find_channel */
+
+/***********************************************************************************************************************
+* Function Name: power_on
+* Description  : Enables CMT channel.
+* Arguments    : channel - 
+*                    Channel number to enable.
+* Return Value : none
+***********************************************************************************************************************/
+static void power_on (uint32_t channel)
+{
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    bsp_int_ctrl_t int_ctrl;
+#endif
+
+#if CMT_REG_PROTECT == 1
+    /* Enable writing to MSTP registers. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR);
+#endif
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl);
+#endif
+
+    /* Enable selected CMT Channel. Go ahead and make sure counter is stopped too. */
+    switch (channel)
+    {
+        case 0:
+            {
+            /* Bring module out of stop state. */
+            MSTP(CMT0) = 0;
+
+            /* Stop counter. */
+            CMT.CMSTR0.BIT.STR0 = 0;
+            break;
+            }
+        case 1:
+            {
+            /* Bring module out of stop state. */
+            MSTP(CMT1) = 0;
+
+            /* Stop counter. */
+            CMT.CMSTR0.BIT.STR1 = 0;        
+            break;
+            }
+#if   CMT_RX_NUM_CHANNELS == 4
+        case 2:
+            {
+            /* Bring module out of stop state. */
+            MSTP(CMT2) = 0;
+
+            /* Stop counter. */
+            CMT.CMSTR1.BIT.STR2 = 0;        
+            break;
+            }
+        case 3:
+            {
+            /* Bring module out of stop state. */
+            MSTP(CMT3) = 0;
+
+            /* Stop counter. */
+            CMT.CMSTR1.BIT.STR3 = 0;       
+            break;
+            }
+#endif
+        default:
+            {
+            /* Should never get here. Valid channel number is checked above. */
+            break;
+            }
+    }
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl);
+#endif
+
+#if CMT_REG_PROTECT == 1
+
+    /* Disable writing to MSTP registers. */
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR);
+#endif
+}
+/***********************************************************************************************************************
+* End of function power_on
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: power_off
+* Description  : Disables CMT channel.
+* Arguments    : channel - 
+*                    Channel number to disable.
+* Return Value : none
+***********************************************************************************************************************/
+static void power_off (uint32_t channel)
+{
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    bsp_int_ctrl_t int_ctrl;
+#endif
+
+#if CMT_REG_PROTECT == 1
+
+    /* Enable writing to MSTP registers. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR);
+#endif
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl);
+#endif
+
+    /* Enable selected CMT Channel. Go ahead and make sure counter is stopped too. Since each MSTP bit controls
+       2 channels, make sure to only disable CMT unit when both channels are off. */
+    switch (channel)
+    {
+        case 0:
+            {
+            /* Stop counter. */
+            CMT.CMSTR0.BIT.STR0 = 0;
+
+            /* Only turn off CMT unit if both channels are off. */
+            if (CMT_RX_MODE_DISABLED == g_cmt_modes[1])
+            {
+                /* Put module in stop state. */
+                MSTP(CMT0) = 1;
+
+            }
+            break;
+            }
+        case 1:
+            {
+            /* Stop counter. */
+            CMT.CMSTR0.BIT.STR1 = 0;        
+
+            /* Only turn off CMT unit if both channels are off. */
+            if (CMT_RX_MODE_DISABLED == g_cmt_modes[0])
+            {
+                /* Put module in stop state. */
+                MSTP(CMT1) = 1;
+
+            }
+            break;
+            }
+#if   CMT_RX_NUM_CHANNELS == 4
+        case 2:
+            {
+            /* Stop counter. */
+            CMT.CMSTR1.BIT.STR2 = 0;        
+
+            /* Only turn off CMT unit if both channels are off. */
+            if (CMT_RX_MODE_DISABLED == g_cmt_modes[3])
+            {
+                /* Put module in stop state. */
+                MSTP(CMT2) = 1;
+
+            }
+            break;
+            }
+        case 3:
+            {
+            /* Stop counter. */
+            CMT.CMSTR1.BIT.STR3 = 0;       
+
+            /* Only turn off CMT unit if both channels are off. */
+            if (CMT_RX_MODE_DISABLED == g_cmt_modes[2])
+            {
+                /* Put module in stop state. */
+                MSTP(CMT3) = 1;
+
+            }
+            break;
+            }
+#endif
+        default:
+            {
+            /* Should never get here. Valid channel number is checked above. */
+            break;
+            }
+    }
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl);
+#endif
+
+#if CMT_REG_PROTECT == 1
+    /* Disable writing to MSTP registers. */
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR);
+#endif
+}
+/***********************************************************************************************************************
+* End of function power_off
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: cmt_counter_start
+* Description  : Starts a CMT channel counting.
+* Arguments    : channel -
+*                    Channel number to use.
+* Return Value : none
+***********************************************************************************************************************/
+static void cmt_counter_start (uint32_t channel)
+{
+    /* Enable compare match interrupt. */
+    (*g_cmt_channels[channel]).CMCR.BIT.CMIE = 1;
+
+    /* Clear counter. */
+    (*g_cmt_channels[channel]).CMCNT = 0;
+
+    /* Start counter channel. */
+    switch (channel)
+    {
+        case 0:
+            {
+            /* Setup ICU registers. */
+            IR(CMT0, CMI0)  = 0;                /* Clear any previously pending interrupts */
+            IPR(CMT0, CMI0) = CMT_RX_CFG_IPR;   /* Set interrupt priority */
+            R_BSP_InterruptRequestEnable(VECT(CMT0, CMI0));                /* Enable compare match interrupt */
+
+            /* Start counter. */
+            CMT.CMSTR0.BIT.STR0 = 1;
+            break;
+            }
+        case 1:
+            {
+            /* Setup ICU registers. */
+            IR(CMT1, CMI1)  = 0;                /* Clear any previously pending interrupts */
+            IPR(CMT1, CMI1) = CMT_RX_CFG_IPR;   /* Set interrupt priority */
+            R_BSP_InterruptRequestEnable(VECT(CMT1, CMI1));                /* Enable compare match interrupt */
+
+            /* Start counter. */
+            CMT.CMSTR0.BIT.STR1 = 1;
+            break;
+            }
+#if   CMT_RX_NUM_CHANNELS == 4
+        case 2:
+            {
+            /* Setup ICU registers. */
+            IR(CMT2, CMI2)  = 0;                /* Clear any previously pending interrupts */
+            IPR(CMT2, CMI2) = CMT_RX_CFG_IPR;   /* Set interrupt priority */
+            R_BSP_InterruptRequestEnable(VECT(CMT2, CMI2));                /* Enable compare match interrupt */
+
+            /* Start counter. */
+            CMT.CMSTR1.BIT.STR2 = 1;
+            break;
+            }
+        case 3:
+            {
+            /* Setup ICU registers. */
+            IR(CMT3, CMI3)  = 0;                /* Clear any previously pending interrupts */
+            IPR(CMT3, CMI3) = CMT_RX_CFG_IPR;   /* Set interrupt priority */
+            R_BSP_InterruptRequestEnable(VECT(CMT3, CMI3));                /* Enable compare match interrupt */
+
+            /* Start counter. */
+            CMT.CMSTR1.BIT.STR3 = 1;
+            break;
+            }
+#endif
+        default:
+        {
+            /* Should never get here. Valid channel number is checked above. */
+            break;
+        }
+    }
+}
+/***********************************************************************************************************************
+* End of function cmt_counter_start
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: cmt_counter_start_priority
+* Description  : Starts a CMT channel counting with interrupt priority.
+* Arguments    : channel -
+*                    Channel number to use.
+*                priority -
+*                    Which interrupt priority is used to assign.
+* Return Value : none
+***********************************************************************************************************************/
+static void cmt_counter_start_priority (uint32_t channel, cmt_priority_t priority)
+{
+    /* Enable compare match interrupt. */
+    (*g_cmt_channels[channel]).CMCR.BIT.CMIE = 1;
+
+    /* Clear counter. */
+    (*g_cmt_channels[channel]).CMCNT = 0;
+
+    /* Start counter channel. */
+    switch (channel)
+    {
+        case 0:
+            {
+            /* Setup ICU registers. */
+            IR(CMT0, CMI0)  = 0;                /* Clear any previously pending interrupts */
+            IPR(CMT0, CMI0) = priority;         /* Set interrupt priority */
+            R_BSP_InterruptRequestEnable(VECT(CMT0, CMI0));                /* Enable compare match interrupt */
+
+            /* Start counter. */
+            CMT.CMSTR0.BIT.STR0 = 1;
+            break;
+            }
+        case 1:
+            {
+            /* Setup ICU registers. */
+            IR(CMT1, CMI1)  = 0;                /* Clear any previously pending interrupts */
+            IPR(CMT1, CMI1) = priority;         /* Set interrupt priority */
+            R_BSP_InterruptRequestEnable(VECT(CMT1, CMI1));                /* Enable compare match interrupt */
+
+            /* Start counter. */
+            CMT.CMSTR0.BIT.STR1 = 1;
+            break;
+            }
+#if   CMT_RX_NUM_CHANNELS == 4
+        case 2:
+            {
+            /* Setup ICU registers. */
+            IR(CMT2, CMI2)  = 0;                /* Clear any previously pending interrupts */
+            IPR(CMT2, CMI2) = priority;         /* Set interrupt priority */
+            R_BSP_InterruptRequestEnable(VECT(CMT2, CMI2));                /* Enable compare match interrupt */
+
+            /* Start counter. */
+            CMT.CMSTR1.BIT.STR2 = 1;
+            break;
+            }
+        case 3:
+            {
+            /* Setup ICU registers. */
+            IR(CMT3, CMI3)  = 0;                /* Clear any previously pending interrupts */
+            IPR(CMT3, CMI3) = priority;         /* Set interrupt priority */
+            R_BSP_InterruptRequestEnable(VECT(CMT3, CMI3));                /* Enable compare match interrupt */
+
+            /* Start counter. */
+            CMT.CMSTR1.BIT.STR3 = 1;
+            break;
+            }
+#endif
+        default:
+        {
+            /* Should never get here. Valid channel number is checked above. */
+            break;
+        }
+    }
+}
+/***********************************************************************************************************************
+* End of function cmt_counter_start_priority
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: cmt_counter_stop
+* Description  : Stops a CMT channel counting.
+* Arguments    : channel -
+*                    Channel number to use.
+* Return Value : none
+***********************************************************************************************************************/
+static void cmt_counter_stop (uint32_t channel)
+{
+    /* Stop counter channel. */
+    switch (channel)
+    {
+        case 0:
+            {
+            /* Stop counter. */
+            CMT.CMSTR0.BIT.STR0 = 0;
+
+            /* Set ICU registers. */
+            R_BSP_InterruptRequestDisable(VECT(CMT0, CMI0));            /* Disable compare match interrupt */
+            IPR(CMT0, CMI0) = 0;            /* Set interrupt priority */
+            IR(CMT0, CMI0)  = 0;            /* Clear any previously pending interrupts */
+            break;
+            }
+        case 1:
+            {
+            /* Stop counter. */
+            CMT.CMSTR0.BIT.STR1 = 0;
+
+            /* Set ICU registers. */
+            R_BSP_InterruptRequestDisable(VECT(CMT1, CMI1));            /* Disable compare match interrupt */
+            IPR(CMT1, CMI1) = 0;            /* Set interrupt priority */
+            IR(CMT1, CMI1)  = 0;            /* Clear any previously pending interrupts */
+            break;
+            }
+#if   CMT_RX_NUM_CHANNELS == 4
+        case 2:
+            {
+            /* Stop counter. */
+            CMT.CMSTR1.BIT.STR2 = 0;
+
+            /* Set ICU registers. */
+            R_BSP_InterruptRequestDisable(VECT(CMT2, CMI2));            /* Disable compare match interrupt */
+            IPR(CMT2, CMI2) = 0;            /* Set interrupt priority */
+            IR(CMT2, CMI2)  = 0;            /* Clear any previously pending interrupts */
+            break;
+            }
+        case 3:
+            {
+            /* Stop counter. */
+            CMT.CMSTR1.BIT.STR3 = 0;
+
+            /* Set ICU registers. */
+            R_BSP_InterruptRequestDisable(VECT(CMT3, CMI3));            /* Disable compare match interrupt */
+            IPR(CMT3, CMI3) = 0;            /* Set interrupt priority */
+            IR(CMT3, CMI3)  = 0;            /* Clear any previously pending interrupts */
+            break;
+            }
+#endif
+        default:
+            {
+            /* Should never get here. Valid channel number is checked above. */
+            break;
+            }
+    }
+}
+/***********************************************************************************************************************
+* End of function cmt_counter_stop
+***********************************************************************************************************************/
+
+
+/***********************************************************************************************************************
+* Function Name: cmt_setup_channel
+* Description  : Sets dividers and counter so compare match occurs at input frequency.
+* Arguments    : channel - 
+*                    Channel number to use.
+*                frequency_hz -
+*                    Frequency at which to set CMT channel
+* Return Value : true -
+*                    Channel setup completed.
+*                false -
+*                    Channel setup failed.
+***********************************************************************************************************************/
+static bool cmt_setup_channel (uint32_t channel, uint32_t frequency_hz)
+{
+    uint32_t i;
+    bool     ret = false;
+
+    /* Requested frequency must not be higher than PCLK. */
+    if (((uint32_t)CMT_PCLK_HZ / 8) >= frequency_hz)
+    {
+        /* Choose clock. This is done by looking through the available dividers to see if we can match the frequency
+           input by the user. */
+        /* WAIT_LOOP */   
+        for (i = 0; i < ((sizeof(g_cmt_clock_dividers))/(sizeof(g_cmt_clock_dividers[0]))); i++)
+        {
+            /* Determine minimum frequency this divider can hit. For example, if a PCLK/8 is used and PCLK is 48MHz, then
+               the minimum frequency we can support is around 91.5Hz. This obtained by doing the following calculation:
+               (PCLK / divider) / max_counter_value
+               Example:
+               (48,000,000 / 8) / 65,536 = 91.5 */
+            if (frequency_hz > (((uint32_t)CMT_PCLK_HZ / g_cmt_clock_dividers[i]) / (uint32_t)CMT_RX_MAX_TIMER_TICKS))
+            {
+                /* Enable peripheral channel. */
+                power_on(channel);
+
+                /* We can use this divider. Figure out counter ticks needed for this frequency. */
+                (*g_cmt_channels[channel]).CMCOR = (uint16_t)((((uint32_t)CMT_PCLK_HZ /g_cmt_clock_dividers[i])/frequency_hz) -1 );
+
+
+                /* Set clock divider to be used. */
+                (*g_cmt_channels[channel]).CMCR.BIT.CKS = i;
+
+                /* Save that we did find a valid divider. */
+                ret = true;
+
+                /* No need to check other dividers. */
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+/***********************************************************************************************************************
+* End of function cmt_setup_channel
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: R_CMT_GetVersion
+********************************************************************************************************************//**
+* @brief This function returns the driver version number at runtime
+* @return Version number with major and minor version digits packed into a single 32-bit value.
+* @details The function returns the version of this module.
+* The version number is encoded such that the top 2 bytes are the major version number
+* and the bottom 2 bytes are the minor version number.
+*/
+uint32_t R_CMT_GetVersion (void)
+{
+    /* These version macros are defined in r_cmt_rx_if.h. */
+    return ((((uint32_t)CMT_RX_VERSION_MAJOR) << 16) | (uint32_t)CMT_RX_VERSION_MINOR);
+}
+/* End of function R_CMT_GetVersion */
+
+/***********************************************************************************************************************
+* Function Name: cmt_isr_common
+* Description  : Common part of ISR handling. Put here and made inline so changes will always apply to all channels.
+* Arguments    : channel -
+*                    Which channel this is for.
+* Return Value : none
+***********************************************************************************************************************/
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+R_BSP_PRAGMA_STATIC_INLINE(cmt_isr_common)
+void cmt_isr_common (uint32_t channel)
+{
+    /* If this is one-shot mode then stop timer. */
+    if (CMT_RX_MODE_ONE_SHOT == g_cmt_modes[channel])
+    {
+        R_CMT_Stop(channel);
+    }
+
+    /* Check for valid callback pointer before calling it. */
+    if ((NULL != g_cmt_callbacks[channel]) && ((uint32_t)FIT_NO_FUNC != (uint32_t)g_cmt_callbacks[channel]))
+    {
+        /* Valid callback found, jump to it. */
+        g_cmt_callbacks[channel]((void *)&channel);
+    }
+}
+/* End of function cmt_isr_common */
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+R_BSP_PRAGMA_STATIC_INLINE(cmt_isr_common)
+void cmt_isr_common (uint32_t channel)
+{
+    /* If this is one-shot mode then stop timer. */
+    if (CMT_RX_MODE_ONE_SHOT == g_cmt_modes[channel])
+    {
+        R_CMT_Stop(channel);
+    }
+
+    /* Check for valid callback pointer before calling it. */
+    if ((NULL != g_cmt_callbacks[channel]) && ((uint32_t)FIT_NO_FUNC != (uint32_t)g_cmt_callbacks[channel]))
+    {
+        /* Valid callback found, jump to it. */
+        g_cmt_callbacks[channel]((void *)&channel);
+    }
+}
+/* End of function cmt_isr_common */
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+    #if CMT_RX_NUM_CHANNELS == 2
+        #if ((BSP_CFG_RTOS_SYSTEM_TIMER != 0 && _RI_TRACE_TIMER != 0) ||\
+            (BSP_CFG_RTOS_SYSTEM_TIMER != 1 && _RI_TRACE_TIMER != 1))
+            R_BSP_PRAGMA_STATIC_INLINE(cmt_isr_common)
+            void cmt_isr_common (uint32_t channel)
+            {
+                /* If this is one-shot mode then stop timer. */
+                if (CMT_RX_MODE_ONE_SHOT == g_cmt_modes[channel])
+                {
+                    R_CMT_Stop(channel);
+                }
+
+                /* Check for valid callback pointer before calling it. */
+                if ((NULL != g_cmt_callbacks[channel]) && ((uint32_t)FIT_NO_FUNC != (uint32_t)g_cmt_callbacks[channel]))
+                {
+                    /* Valid callback found, jump to it. */
+                    g_cmt_callbacks[channel]((void *)&channel);
+                }
+            }
+            /* End of function cmt_isr_common */
+        #endif
+    #else
+        R_BSP_PRAGMA_STATIC_INLINE(cmt_isr_common)
+        void cmt_isr_common (uint32_t channel)
+        {
+            /* If this is one-shot mode then stop timer. */
+            if (CMT_RX_MODE_ONE_SHOT == g_cmt_modes[channel])
+            {
+                R_CMT_Stop(channel);
+            }
+
+            /* Check for valid callback pointer before calling it. */
+            if ((NULL != g_cmt_callbacks[channel]) && ((uint32_t)FIT_NO_FUNC != (uint32_t)g_cmt_callbacks[channel]))
+            {
+                /* Valid callback found, jump to it. */
+                g_cmt_callbacks[channel]((void *)&channel);
+            }
+        }
+        /* End of function cmt_isr_common */
+    #endif /* End of  CMT_RX_NUM_CHANNELS */
+#else /* Non-OS & others */
+    R_BSP_PRAGMA_STATIC_INLINE(cmt_isr_common)
+    void cmt_isr_common (uint32_t channel)
+    {
+        /* If this is one-shot mode then stop timer. */
+        if (CMT_RX_MODE_ONE_SHOT == g_cmt_modes[channel])
+        {
+            R_CMT_Stop(channel);
+        }
+
+        /* Check for valid callback pointer before calling it. */
+        if ((NULL != g_cmt_callbacks[channel]) && ((uint32_t)FIT_NO_FUNC != (uint32_t)g_cmt_callbacks[channel]))
+        {
+            /* Valid callback found, jump to it. */
+            g_cmt_callbacks[channel]((void *)&channel);
+        }
+    }
+#endif /* BSP_CFG_RTOS_USED */
+/* End of function cmt_isr_common */
+
+/***********************************************************************************************************************
+* Function Name: cmt0_isr
+* Description  : Interrupt when compare match for this channel occurs.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+R_BSP_PRAGMA_STATIC_INTERRUPT (cmt0_isr,VECT(CMT0, CMI0))
+R_BSP_ATTRIB_STATIC_INTERRUPT void cmt0_isr (void)
+{
+    cmt_isr_common(0);
+}
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+    #if (BSP_CFG_RTOS_SYSTEM_TIMER != 0)
+        R_BSP_PRAGMA_STATIC_INTERRUPT (cmt0_isr,VECT(CMT0, CMI0))
+        R_BSP_ATTRIB_STATIC_INTERRUPT void cmt0_isr (void)
+        {
+            cmt_isr_common(0);
+        }
+    #endif /* (BSP_CFG_RTOS_SYSTEM_TIMER != 0) */
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+    #if (BSP_CFG_RTOS_SYSTEM_TIMER != 0 && _RI_TRACE_TIMER != 0)
+        void cmt0_isr (void)
+        {
+            cmt_isr_common(0);
+        }
+    #endif /* (BSP_CFG_RTOS_SYSTEM_TIMER != 0 && _RI_TRACE_TIMER != 0) */
+#else /* Non-OS & others */
+R_BSP_PRAGMA_STATIC_INTERRUPT (cmt0_isr,VECT(CMT0, CMI0))
+R_BSP_ATTRIB_STATIC_INTERRUPT void cmt0_isr (void)
+{
+    cmt_isr_common(0);
+}
+#endif/* BSP_CFG_RTOS_USED */
+/* End of function cmt0_isr */
+
+/***********************************************************************************************************************
+* Function Name: cmt1_isr
+* Description  : Interrupt when compare match for this channel occurs.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+R_BSP_PRAGMA_STATIC_INTERRUPT (cmt1_isr,VECT(CMT1, CMI1))
+R_BSP_ATTRIB_STATIC_INTERRUPT void cmt1_isr (void)
+{
+    cmt_isr_common(1);
+}
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+    #if (BSP_CFG_RTOS_SYSTEM_TIMER != 1)
+        R_BSP_PRAGMA_STATIC_INTERRUPT (cmt1_isr,VECT(CMT1, CMI1))
+        R_BSP_ATTRIB_STATIC_INTERRUPT void cmt1_isr (void)
+        {
+            cmt_isr_common(1);
+        }
+    #endif /* (BSP_CFG_RTOS_SYSTEM_TIMER != 1) */
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+    #if (BSP_CFG_RTOS_SYSTEM_TIMER != 1 && _RI_TRACE_TIMER != 1)
+        void cmt1_isr (void)
+        {
+            cmt_isr_common(1);
+        }
+    #endif /* (BSP_CFG_RTOS_SYSTEM_TIMER != 1 && _RI_TRACE_TIMER != 1) */
+#else /* Non-OS & others */
+R_BSP_PRAGMA_STATIC_INTERRUPT (cmt1_isr,VECT(CMT1, CMI1))
+R_BSP_ATTRIB_STATIC_INTERRUPT void cmt1_isr (void)
+{
+    cmt_isr_common(1);
+}
+#endif/* BSP_CFG_RTOS_USED */
+/* End of function cmt1_isr */
+
+#if   CMT_RX_NUM_CHANNELS == 4
+
+/***********************************************************************************************************************
+* Function Name: cmt2_isr
+* Description  : Interrupt when compare match for this channel occurs.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+R_BSP_PRAGMA_STATIC_INTERRUPT(cmt2_isr,VECT(CMT2, CMI2))
+R_BSP_ATTRIB_STATIC_INTERRUPT void cmt2_isr (void)
+{
+    cmt_isr_common(2);
+}
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+    #if (BSP_CFG_RTOS_SYSTEM_TIMER != 2)
+        R_BSP_PRAGMA_STATIC_INTERRUPT(cmt2_isr,VECT(CMT2, CMI2))
+        R_BSP_ATTRIB_STATIC_INTERRUPT void cmt2_isr (void)
+        {
+            cmt_isr_common(2);
+        }
+    #endif /* (BSP_CFG_RTOS_SYSTEM_TIMER != 2) */
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+    #if (BSP_CFG_RTOS_SYSTEM_TIMER != 2 && _RI_TRACE_TIMER != 2)
+        void cmt2_isr (void)
+        {
+            cmt_isr_common(2);
+        }
+    #endif /* (BSP_CFG_RTOS_SYSTEM_TIMER != 2 && _RI_TRACE_TIMER != 2) */
+#else /* Non-OS & others */
+R_BSP_PRAGMA_STATIC_INTERRUPT(cmt2_isr,VECT(CMT2, CMI2))
+R_BSP_ATTRIB_STATIC_INTERRUPT void cmt2_isr (void)
+{
+    cmt_isr_common(2);
+}
+#endif/* BSP_CFG_RTOS_USED */
+/* End of function cmt2_isr */
+
+/***********************************************************************************************************************
+* Function Name: cmt3_isr
+* Description  : Interrupt when compare match for this channel occurs.
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+#if BSP_CFG_RTOS_USED == 0      /* Non-OS */
+R_BSP_PRAGMA_STATIC_INTERRUPT( cmt3_isr,VECT(CMT3, CMI3))
+R_BSP_ATTRIB_STATIC_INTERRUPT void cmt3_isr (void)
+{
+    cmt_isr_common(3);
+}
+#elif BSP_CFG_RTOS_USED == 1    /* FreeRTOS */
+    #if (BSP_CFG_RTOS_SYSTEM_TIMER != 3)
+        R_BSP_PRAGMA_STATIC_INTERRUPT (cmt3_isr,VECT(CMT3, CMI3))
+        R_BSP_ATTRIB_STATIC_INTERRUPT void cmt3_isr (void)
+        {
+            cmt_isr_common(3);
+        }
+    #endif /* (BSP_CFG_RTOS_SYSTEM_TIMER != 3) */
+#elif BSP_CFG_RTOS_USED == 2    /* SEGGER embOS */
+#elif BSP_CFG_RTOS_USED == 3    /* Micrium MicroC/OS */
+#elif BSP_CFG_RTOS_USED == 4    /* Renesas RI600V4 & RI600PX */
+    #if (BSP_CFG_RTOS_SYSTEM_TIMER != 3 && _RI_TRACE_TIMER != 3)
+        void cmt3_isr (void)
+        {
+            cmt_isr_common(3);
+        }
+    #endif /* (BSP_CFG_RTOS_SYSTEM_TIMER != 3 && _RI_TRACE_TIMER != 3) */
+#else /* Non-OS & others */
+R_BSP_PRAGMA_STATIC_INTERRUPT( cmt3_isr,VECT(CMT3, CMI3))
+R_BSP_ATTRIB_STATIC_INTERRUPT void cmt3_isr (void)
+{
+    cmt_isr_common(3);
+}
+#endif/* BSP_CFG_RTOS_USED */
+/* End of function cmt3_isr */
+#endif /* End of #if CMT_RX_NUM_CHANNELS == 4 */
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_bsp_config.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_bsp_config.h
new file mode 100644
index 00000000..7d9b9106
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_bsp_config.h
@@ -0,0 +1,655 @@
+/* Generated configuration header file - do not edit */
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_config_reference.h
+* Device(s)    : RX65N
+* Description  : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+*                somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+*                is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 15.05.2017 1.00      First Release
+*         : 01.12.2017 1.01      Added the following macro definition.
+*                                - BSP_CFG_EBMAPCR_1ST_PRIORITY
+*                                - BSP_CFG_EBMAPCR_2ND_PRIORITY
+*                                - BSP_CFG_EBMAPCR_3RD_PRIORITY
+*                                - BSP_CFG_EBMAPCR_4TH_PRIORITY
+*                                - BSP_CFG_EBMAPCR_5TH_PRIORITY
+*         : 01.07.2018 1.02      Added the following macro definition.
+*                                - BSP_CFG_CONFIGURATOR_SELECT
+*                                Add RTOS support. FreeRTOS. Define a timer for RTOS.
+*         : 27.07.2018 1.03      Modified the comment of PLL clock source.
+*                                Added the following macro definition for ID code protection.
+*                                 - BSP_CFG_ID_CODE_LONG_1
+*                                 - BSP_CFG_ID_CODE_LONG_2
+*                                 - BSP_CFG_ID_CODE_LONG_3
+*                                 - BSP_CFG_ID_CODE_LONG_4
+*                                Added the following macro definition.
+*                                 - BSP_CFG_FIT_IPL_MAX
+*         : 31.10.2018 1.04      Added support for RX651 with 64 pin package.
+*         : 28.02.2019 2.00      Added support for GNUC and ICCRX.
+*                                Fixed coding style.
+*         : 26.07.2019 2.01      Modified comment.
+*         : 08.10.2019 2.02      Added the following macro definition.
+*                                - BSP_CFG_SWINT_UNIT1_ENABLE
+*                                - BSP_CFG_SWINT_UNIT2_ENABLE
+*                                - BSP_CFG_SWINT_TASK_BUFFER_NUMBER
+*                                - BSP_CFG_SWINT_IPR_INITIAL_VALUE
+*                                Modified comment for added support of Renesas RTOS (RI600V4 or RI600PX).
+*                                Added the following macro definition.
+*                                - BSP_CFG_RENESAS_RTOS_USED
+*         : 31.07.2020 2.03      Modified comment.
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* NOTE:
+   The default settings are the same as when using RSKRX65N-2MB.
+   Change to the settings for the user board.
+*/
+
+/* Start up select
+   0 = Enable BSP startup program.
+   1 = Disable BSP startup program. (e.g. Using user startup program.)
+   NOTE: This setting is available only when using CCRX. */
+#define BSP_CFG_STARTUP_DISABLE (0)
+
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such 
+   as package and memory size.
+   To help parse this information, the part number will be defined using multiple macros.
+   R 5 F 56 5N E D D FP
+   | | | |  |  | | | |  Macro Name                             Description
+   | | | |  |  | | | |__BSP_CFG_MCU_PART_PACKAGE             = Package type, number of pins, and pin pitch
+   | | | |  |  | | |____not used                             = Products with wide temperature range
+   | | | |  |  | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included
+   | | | |  |  |________BSP_CFG_MCU_PART_MEMORY_SIZE         = ROM, RAM, and Data Flash Capacity
+   | | | |  |___________BSP_CFG_MCU_PART_GROUP               = Group name
+   | | | |______________BSP_CFG_MCU_PART_SERIES              = Series name
+   | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE         = Type of memory (Flash, ROMless)
+   | |__________________not used                             = Renesas MCU
+   |____________________not used                             = Renesas semiconductor product.
+*/
+
+/* Package type. Set the macro definition based on values below:
+   Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+   FC           = 0x0             = LFQFP/176/0.50
+   BG           = 0x1             = LFBGA/176/0.80
+   LC           = 0x2             = TFLGA/177/0.50
+   FB           = 0x3             = LFQFP/144/0.50
+   LK           = 0x4             = TFLGA/145/0.50
+   FP           = 0x5             = LFQFP/100/0.50
+   FM           = 0x8             = LFQFP/64/0.50
+   LJ           = 0xA             = TFLGA/100/0.65
+   BP           = 0xC             = TFBGA/64/0.50
+*/
+#define BSP_CFG_MCU_PART_PACKAGE        (0x0) /* Generated value. Do not edit this manually */
+
+/* Whether Encryption and SDHI/SDSI are included or not.
+   Character(s) = Value for macro = Description
+   A            = false           = Encryption module not included, SDHI/SDSI module not included
+   B            = false           = Encryption module not included, SDHI/SDSI module included
+   D            = false           = Encryption module not included, SDHI/SDSI module included, dual-bank structure
+   E            = true            = Encryption module included, SDHI/SDSI module not included
+   F            = true            = Encryption module included, SDHI/SDSI module included
+   H            = true            = Encryption module included, SDHI/SDSI module included, dual-bank structure
+*/
+#define BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED   (false) /* Generated value. Do not edit this manually */
+
+/* ROM, RAM, and Data Flash Capacity.
+   Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+   4            = 0x4             = 512KB/256KB/Not equipped
+   7            = 0x7             = 768KB/256KB/Not equipped
+   9            = 0x9             = 1MB/256KB/Not equipped
+   C            = 0xC             = 1.5MB/640KB/32KB
+   E            = 0xE             = 2MB/640KB/32KB
+   NOTE: When the RAM capacity is 640KB, the RAM areas are not contiguous.
+*/
+#define BSP_CFG_MCU_PART_MEMORY_SIZE    (0xE) /* Generated value. Do not edit this manually */
+
+/* Group name.
+   Character(s) = Value for macro = Description
+   5N/51        = 0x0             = RX65N Group/RX651 Group
+*/
+#define BSP_CFG_MCU_PART_GROUP          (0x0) /* Generated value. Do not edit this manually */
+
+/* Series name.
+   Character(s) = Value for macro = Description
+   56           = 0x0             = RX600 Series
+*/
+#define BSP_CFG_MCU_PART_SERIES         (0x0) /* Generated value. Do not edit this manually */
+
+/* Memory type.
+   Character(s) = Value for macro = Description
+   F            = 0x0             = Flash memory version
+*/
+#define BSP_CFG_MCU_PART_MEMORY_TYPE    (0x0) /* Generated value. Do not edit this manually */
+
+/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack.
+ * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU
+ * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how
+ * much stack space to allocate since the user does not have to worry about always having enough room on the
+ * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not
+ * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used).
+ * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then
+ * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings.
+ *
+ * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored.
+ * 1 = Use 2 stacks. User stack and interrupt stack will both be used.
+ * NOTE: This setting is available only when using CCRX and GNUC.
+ *       This is invalid when using Renesas RTOS with CCRX.
+ */
+#define BSP_CFG_USER_STACK_ENABLE       (1)
+
+/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */
+#if BSP_CFG_USER_STACK_ENABLE == 1
+/* User Stack size in bytes.
+ * NOTE: This setting is available only when using CCRX and GNUC.
+ *       This is invalid when using Renesas RTOS with CCRX. */
+#define BSP_CFG_USTACK_BYTES            (0x1000)
+#endif
+
+/* Interrupt Stack size in bytes.
+   NOTE: This setting is available only when using CCRX and GNUC. */
+#define BSP_CFG_ISTACK_BYTES            (0x400)
+
+/* Heap size in bytes.
+   To disable the heap you must follow these steps:
+   1) Set this macro (BSP_CFG_HEAP_BYTES) to 0.
+   2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0.
+   3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain 
+      settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio.
+      This will present a list of modules that can be included. Uncheck the box for stdio.h.
+   NOTE: This setting is available only when using CCRX and GNUC. */
+#define BSP_CFG_HEAP_BYTES              (0x400)
+
+/* Initializes C input & output library functions.
+   0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+   1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio.
+   NOTE: This setting is available only when using CCRX. */
+#define BSP_CFG_IO_LIB_ENABLE           (0)
+
+/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions
+   by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */
+#define BSP_CFG_USER_CHARGET_ENABLED    (0)
+#define BSP_CFG_USER_CHARGET_FUNCTION     my_sw_charget_function
+
+#define BSP_CFG_USER_CHARPUT_ENABLED    (1)
+#define BSP_CFG_USER_CHARPUT_FUNCTION     my_sw_charput_function
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+   on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+   0 = Stay in Supervisor mode.
+   1 = Switch to User mode.
+   NOTE: This is invalid when using Renesas RTOS with CCRX.
+*/
+#define BSP_CFG_RUN_IN_USER_MODE        (0)
+
+/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set 
+   this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for 
+   it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging.
+   If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using 
+   FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */
+/* Lowest 4-byte section, address 0xFE7F5D50. From MSB to LSB: ID code 4, ID code 3, ID code 2, ID code 1/Control Code.
+ */
+#define BSP_CFG_ID_CODE_LONG_1          (0xFFFFFFFF)
+/* 2nd ID Code section, address 0xFE7F5D54. From MSB to LSB: ID code 8, ID code 7, ID code 6, ID code 5. */
+#define BSP_CFG_ID_CODE_LONG_2          (0xFFFFFFFF)
+/* 3rd ID Code section, address 0xFE7F5D58. From MSB to LSB: ID code 12, ID code 11, ID code 10, ID code 9. */
+#define BSP_CFG_ID_CODE_LONG_3          (0xFFFFFFFF)
+/* 4th ID Code section, address 0xFE7F5D5C. From MSB to LSB: ID code 16, ID code 15, ID code 14, ID code 13. */
+#define BSP_CFG_ID_CODE_LONG_4          (0xFFFFFFFF)
+
+/* Clock source select (CKSEL).
+   0 = Low Speed On-Chip Oscillator  (LOCO)
+   1 = High Speed On-Chip Oscillator (HOCO)
+   2 = Main Clock Oscillator
+   3 = Sub-Clock Oscillator
+   4 = PLL Circuit
+*/
+#define BSP_CFG_CLOCK_SOURCE            (4) /* Generated value. Do not edit this manually */
+
+/* Main clock Oscillator Switching (MOSEL).
+   0 = Resonator
+   1 = External clock input
+*/
+#define BSP_CFG_MAIN_CLOCK_SOURCE       (0) /* Generated value. Do not edit this manually */
+
+/* The sub-clock oscillation control for using the RTC.
+   When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated.
+   0 = The RTC is not to be used.
+   1 = The RTC is to be used.
+*/
+#define BSP_CFG_RTC_ENABLE              (0) /* Generated value. Do not edit this manually */
+
+/* Sub-Clock Oscillator Drive Capacity Control (RTCDV).
+   0 = Drive capacity for standard CL. (default)
+   1 = Drive capacity for low CL.
+*/
+#define BSP_CFG_SOSC_DRV_CAP            (0) /* Generated value. Do not edit this manually */
+
+/* Clock configuration options.
+   The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+   multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the
+   ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, USB Clock is 48MHz,
+   and BCLK is 120MHz then the settings would be:
+
+   BSP_CFG_XTAL_HZ  = 24000000
+   BSP_CFG_PLL_DIV  = 1        (no division)
+   BSP_CFG_PLL_MUL  = 10.0     (24MHz x 10.0 = 240MHz)
+   BSP_CFG_ICK_DIV  = 2      : System Clock (ICLK)        = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV)  = 120MHz
+   BSP_CFG_PCKA_DIV = 2      : Peripheral Clock A (PCLKA) = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz
+   BSP_CFG_PCKB_DIV = 4      : Peripheral Clock B (PCLKB) = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz
+   BSP_CFG_PCKC_DIV = 4      : Peripheral Clock C (PCLKC) = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz
+   BSP_CFG_PCKD_DIV = 4      : Peripheral Clock D (PCLKD) = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz
+   BSP_CFG_FCK_DIV  = 4      : Flash IF Clock (FCLK)      = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV)  = 60MHz
+   BSP_CFG_BCK_DIV  = 2      : External Bus Clock (BCK)   = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV)  = 120MHz
+   BSP_CFG_UCK_DIV  = 5      : USB Clock (UCLK)           = 
+                               (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV)  = 48MHz
+*/
+
+/* Input clock frequency in Hz (XTAL or EXTAL). */
+#define BSP_CFG_XTAL_HZ                 (24000000) /* Generated value. Do not edit this manually */
+
+/* The HOCO can operate at several different frequencies. Choose which one using the macro below.
+   Available frequency settings:
+   0 = 16MHz (default)
+   1 = 18MHz
+   2 = 20MHz
+*/
+#define BSP_CFG_HOCO_FREQUENCY          (0) /* Generated value. Do not edit this manually */
+
+/* PLL clock source (PLLSRCSEL). Choose which clock source to input to the PLL circuit.
+   Available clock sources:
+   0 = Main clock (default)
+   1 = HOCO
+*/
+#define BSP_CFG_PLL_SRC                 (0) /* Generated value. Do not edit this manually */
+
+/* PLL Input Frequency Division Ratio Select (PLIDIV).
+   Available divisors = /1 (no division), /2, /3
+*/
+#define BSP_CFG_PLL_DIV                 (1) /* Generated value. Do not edit this manually */
+
+/* PLL Frequency Multiplication Factor Select (STC).
+   Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0)
+*/
+#define BSP_CFG_PLL_MUL                 (10.0) /* Generated value. Do not edit this manually */
+
+/* System Clock Divider (ICK).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_ICK_DIV                 (2) /* Generated value. Do not edit this manually */
+
+/* Peripheral Module Clock A Divider (PCKA).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKA_DIV                (2) /* Generated value. Do not edit this manually */
+
+/* Peripheral Module Clock B Divider (PCKB).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKB_DIV                (4) /* Generated value. Do not edit this manually */
+
+/* Peripheral Module Clock C Divider (PCKC).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKC_DIV                (4) /* Generated value. Do not edit this manually */
+
+/* Peripheral Module Clock D Divider (PCKD).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKD_DIV                (4) /* Generated value. Do not edit this manually */
+
+/* External Bus Clock Divider (BCLK).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_BCK_DIV                 (2) /* Generated value. Do not edit this manually */
+
+/* Flash IF Clock Divider (FCK).
+   Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_FCK_DIV                 (4) /* Generated value. Do not edit this manually */
+
+/* USB Clock Divider Select.
+   Available divisors = /2, /3, /4, /5
+*/
+#define BSP_CFG_UCK_DIV                 (2) /* Generated value. Do not edit this manually */
+
+/* Configure BCLK output pin (only effective when external bus enabled)
+   Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency
+*/
+#define BSP_CFG_BCLK_OUTPUT             (0) /* Generated value. Do not edit this manually */
+
+/* Configure SDCLK output pin (only effective when external bus enabled)
+   Values 0=no output, 1 = BCK frequency
+*/
+#define BSP_CFG_SDCLK_OUTPUT            (0) /* Generated value. Do not edit this manually */
+
+/* Main Clock Oscillator Wait Time (MOSCWTCR).
+   The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable 
+   oscillation by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below.
+
+   BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32
+   (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO)
+
+   If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives 
+   BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h).
+
+   NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator.
+         Set the BSP_CFG_MOSC_WAIT_TIME to 00h.
+*/
+#define BSP_CFG_MOSC_WAIT_TIME          (0x53) /* Generated value. Do not edit this manually */
+
+/* Sub-Clock Oscillator Wait Time (SOSCWTCR).
+   The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation
+   by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below.
+
+   BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384
+   (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO)
+
+   If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives
+    BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the  BSP_CFG_SOSC_WAIT_TIME bits to 33(21h).
+*/
+#define BSP_CFG_SOSC_WAIT_TIME          (0x21) /* Generated value. Do not edit this manually */
+
+/* ROM Cache Enable Register (ROMCE).
+   0 = ROM cache operation disabled.
+   1 = ROM cache operation enabled.
+*/
+#define BSP_CFG_ROM_CACHE_ENABLE        (0)
+
+/* Configure WDT and IWDT settings.
+   OFS0 - Option Function Select Register 0
+       b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1.
+       b28     WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+       b27:b26 WDTRPSS   - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+       b25:b24 WDTRPES   - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+       b23:b20 WDTCKS    - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256,
+                                                                 7=PCLKB/2048, 8=PCLKB/8192)
+       b19:b18 WDTTOPS   - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384)
+       b17     WDTSTRT   - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+       b16:b15 Reserved (set to 1)
+       b14     IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+       b13     Reserved (set to 1)
+       b12     IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+       b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+       b9:b8   IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+       b7:b4   IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+       b3:b2   IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384)
+       b1      IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+       b0      Reserved (set to 1)
+   Default value is 0xFFFFFFFF.
+*/
+#define BSP_CFG_OFS0_REG_VALUE  (0xFFFFFFFF) /* Generated value. Do not edit this manually */
+
+/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset.
+   OFS1 - Option Function Select Register 1
+       b31:b9 Reserved (set to 1)
+       b8     HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+       b7:b3  Reserved When reading, these bits return the value written by the user. The write value should be 1.
+       b2     LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled)
+       b1:b0  VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v)
+       NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz.
+             BSP_CFG_HOCO_FREQUENCY should be default value.
+   Default value is 0xFFFFFFFF.
+*/
+#define BSP_CFG_OFS1_REG_VALUE  (0xFFFFFFFF) /* Generated value. Do not edit this manually */
+
+/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 46 and 47 (in dual mode) in 
+   the code flash memory by third party software. This feature is disabled by default.
+   TMEF - TM Enable Flag Register
+       b31     Reserved (set to 1)
+       b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFEE 0000h to 
+                                                   FFEE FFFFh is enabled in dual mode.
+                                            - 111: The TM function in the address range from FFEE 0000h to 
+                                                   FFEE FFFFh is disabled in dual mode.
+       b27     Reserved (set to 1)
+       b26:b24 TMEF   - TM Enable - 000: TM function is enabled.
+                                  - 111: TM function is disabled.
+       b23:b0  Reserved (set to 1)
+       NOTE: If the dual bank function has not been incorporated in a device,
+             TMEFDB bits [b30:b26] are reserved area.
+   Default value is 0xFFFFFFFF.
+*/
+#define BSP_CFG_TRUSTED_MODE_FUNCTION  (0xFFFFFFFF)
+
+/* Configure FAW register is used to set the write protection flag and boot area select flag 
+   for setting the flash access window startaddress and flash access window end address.
+   FAW - Flash Access Window Setting Register
+       b31      BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area
+                                              - 1: FFFF E000h to FFFF FFFFh are used as the boot area
+       b30:b28  Reserved - When reading, these bits return the value written by the user.The write value should be 1.
+       b27:b16  FAWE - Flash Access Window End Address - Flash access window end address
+       b15      FSPR - Access Window Protection Flag - 0: With protection (P/E disabled)
+                                                     - 1: Without protection (P/E enabled)
+       b14:b12  Reserved - When reading, these bits return the value written by the user.The write value should be 1.
+       b11:b0   FAWS - Flash Access Window Start Address - Flash access window start address 
+       NOTE: Once 0 is written to this bit, the bit can never be restored to 1.
+             Therefore, the access window and the BTFLG bit never be set again or the TM function 
+             never be disabled once it has been enabled.
+             Exercise extra caution when handling the FSPR bit.
+   Default value is 0xFFFFFFFF.
+*/
+#define BSP_CFG_FAW_REG_VALUE  (0xFFFFFFFF)
+
+/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory
+   when the flash programmer is used during off-board programming.
+   ROMCODE - ROM Code Protection Register
+       b31:b0  ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1).
+                          0000 0001h: ROM code protection enabled (ROM code protection 2).
+                          Other than above: ROM code protection disabled.
+       Note: The ROMCODE register should be set in 32-bit units.
+   Default value is 0xFFFFFFFF.
+*/
+#define BSP_CFG_ROMCODE_REG_VALUE  (0xFFFFFFFF)
+
+/* Select the bank mode of dual-bank function of the code flash memory.
+   0 = Dual mode.
+   1 = Linear mode. (default)
+   NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro.
+         Default setting of the bank mode is linear mode.
+         If the dual bank function has not been incorporated in a device, this macro should be 1.
+*/
+#define BSP_CFG_CODE_FLASH_BANK_MODE    (1)
+
+/* Select the startup bank of the program when dual bank function is in dual mode.
+   0 = The address range of bank 1 from FFE00000h to FFEFFFFFh and bank 0 from FFF00000h to FFFFFFFFh. (default)
+   1 = The address range of bank 1 from FFF00000h to FFFFFFFFh and bank 0 from FFE00000h to FFEFFFFFh.
+   NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro.
+         Default setting of the start bank is bank0.
+         If the dual bank function has not been incorporated in a device, this macro should be 0.
+*/
+#define BSP_CFG_CODE_FLASH_START_BANK   (0)
+
+/* This macro lets other modules no if a RTOS is being used.
+   0 = RTOS is not used.
+   1 = FreeRTOS is used.
+   2 = embOS is used.(This is not available.)
+   3 = MicroC_OS is used.(This is not available.)
+   4 = Renesas ITRON OS (RI600V4 or RI600PX) is used.
+*/
+#define BSP_CFG_RTOS_USED               (0) /* Generated value. Do not edit this manually */
+
+/* This macro is used to select which Renesas ITRON OS.
+   0 = RI600V4 is used.
+   1 = RI600PX is used.
+*/
+#define BSP_CFG_RENESAS_RTOS_USED       (0)
+
+/* This macro is used to select which CMT channel used for system timer of RTOS.
+ * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */
+#if BSP_CFG_RTOS_USED != 0
+/* Setting value.
+ * 0      = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS).
+ * 1      = CMT channel 1 used for system timer of RTOS.
+ * 2      = CMT channel 2 used for system timer of RTOS.
+ * 3      = CMT channel 3 used for system timer of RTOS.
+ * Others = Invalid.
+ * NOTE: This is invalid when using Renesas RTOS with CCRX.
+ */
+#define BSP_CFG_RTOS_SYSTEM_TIMER       (0)
+#endif
+
+/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its
+   locking mechanisms then they can change this macro.
+   NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'.
+   0 = Use default locking (non-RTOS)
+   1 = Use user defined locking mechanism.
+*/
+#define BSP_CFG_USER_LOCKING_ENABLED    (0)
+
+/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef
+   that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be 
+   a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks.
+   NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored.
+   NOTE: Do not surround the type with parentheses '(' ')'.
+*/
+#define BSP_CFG_USER_LOCKING_TYPE       bsp_lock_t
+
+/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions
+   that will handle the locking and unlocking. These functions should be defined below.
+   If BSP_CFG_USER_LOCKING_ENABLED is != 0:
+   R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index)
+   R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index)
+       NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter.
+   R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call 
+   BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock)
+   R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call 
+   BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock)
+       NOTE:With these functions the actual address of the lock to use is passed as the parameter.
+   NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, 
+         return false.
+   NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored.
+   NOTE: Do not surround the type with parentheses '(' ')'.
+*/
+#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION      my_hw_locking_function
+#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION    my_hw_unlocking_function
+#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION      my_sw_locking_function
+#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION    my_sw_unlocking_function
+
+/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the
+   following callback definitions AND provide a call back function name for the respective callback
+   function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result
+   in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C
+   runtime environment by resetprg.
+   Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined
+   my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg.
+*/
+#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED    (0)
+#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION     my_sw_warmstart_prec_function
+
+#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED    (0)
+#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION    my_sw_warmstart_postc_function
+
+/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users
+   will want to disable this for production code. The reason for this would be to save execution time and code space.
+   This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its
+   own local macro for this same purpose. By default the local macros will take the global value from here though
+   they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter
+   checking should only used when inputs are known to be good and the increase in speed or decrease in code space is 
+   needed.
+   0 = Global setting for parameter checking is disabled.
+   1 = Global setting for parameter checking is enabled (Default).
+*/
+#define BSP_CFG_PARAM_CHECKING_ENABLE               (1)
+
+/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC
+   graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and
+   display list data read).
+   The default priority order in bsp is below
+   GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC.
+   Priority can be changed with this macro.
+
+   Extended Bus Master Priority setting
+   0 = GLCDC graphics 1 data read
+   1 = DRW2D texture data read
+   2 = DRW2D frame buffer data read write and display list data read
+   3 = GLCDC graphics 2 data read
+   4 = EDMAC
+
+   Note : This macro is only available for products with at least 1.5 Mbytes of code flash memory.
+          Settings other than above are prohibited.
+          Duplicate priority settings can not be made.
+*/
+#define BSP_CFG_EBMAPCR_1ST_PRIORITY                (0) /* Extended Bus Master 1st Priority Selection */
+#define BSP_CFG_EBMAPCR_2ND_PRIORITY                (3) /* Extended Bus Master 2nd Priority Selection */
+#define BSP_CFG_EBMAPCR_3RD_PRIORITY                (1) /* Extended Bus Master 3rd Priority Selection */
+#define BSP_CFG_EBMAPCR_4TH_PRIORITY                (2) /* Extended Bus Master 4th Priority Selection */
+#define BSP_CFG_EBMAPCR_5TH_PRIORITY                (4) /* Extended Bus Master 5th Priority Selection */
+
+/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This
+   macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */
+#define BSP_CFG_MCU_VCC_MV                          (3300) /* Generated value. Do not edit this manually */
+
+/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool.
+   When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0.
+   0 = Disabled (default)
+   1 = Smart Configurator initialization code used
+*/
+#define BSP_CFG_CONFIGURATOR_SELECT                 (1) /* Generated value. Do not edit this manually */
+
+/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other 
+   FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the 
+   specified interrupt priority level.
+   This macro sets the IPL. Range is 0x0 - 0xF.
+   Please set this macro more than IPR for other FIT module interrupts.
+   The default value is 0xF (maximum value).
+   Don't change if there is no special processing with higher priority than all fit modules.
+*/
+#define BSP_CFG_FIT_IPL_MAX                         (0xF)
+
+/* Software Interrupt (SWINT).
+   0 = Software interrupt is not used.
+   1 = Software interrupt is used.
+   NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. 
+*/
+#define BSP_CFG_SWINT_UNIT1_ENABLE    (0)
+#define BSP_CFG_SWINT_UNIT2_ENABLE    (0)
+
+/* Software Interrupt Task Buffer Number.
+   For software interrupt, this value is number of buffering user tasks.
+   So user can increase this value if user system would have many software interrupt tasks
+   and user system has enough buffer. This value requires 9 byte per task.
+   NOTE: This setting is common to all units. It can not be set individually. 
+         The maximum value is 254.
+*/
+#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER     (8)
+
+/* Initial value of the software interrupt priority.
+   For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF.
+   NOTE: This setting is common to all units. It can not be set individually. 
+         Please be careful that this setting is the initial value of the interrupt priority register(IPR).
+         It is possible to dynamically change the IPR.
+*/
+#define BSP_CFG_SWINT_IPR_INITIAL_VALUE     (0x1)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_bsp_config_readme.txt b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_bsp_config_readme.txt
new file mode 100644
index 00000000..6a9002cf
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_bsp_config_readme.txt
@@ -0,0 +1,12 @@
+FIT r_config folder
+-------------------
+The purpose of the r_config folder is to provide one place where the user can store all of their FIT configuration 
+files. Putting the files in one place makes them easy to find, backup, and put in a version control system.
+
+FIT Modules are distributed with a reference configuration file. These files end with '_reference.h'. For example,
+the reference configuration file for the r_bsp is named r_bsp_config_reference.h. Reference configuration files are 
+provided so that the user always has a known-good configuration to revert to. When adding a FIT Module to a project the
+user should copy this reference configuration file to this folder and remove '_reference' from the filename 
+(r_bsp_config_reference.h is renamed to r_bsp_config.h).  For the r_bsp the reference configuration file can be found in
+the 'board' folder for the currently chosen development board. For other FIT Modules the reference configuration file
+can be found in the 'ref' folder of the FIT Module.
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_bsp_interrupt_config.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_bsp_interrupt_config.h
new file mode 100644
index 00000000..39237823
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_bsp_interrupt_config.h
@@ -0,0 +1,214 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer 
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_bsp_interrupt_config.h
+* Description  : This module maps Interrupt A & B interrupts. More information on how this is done is given below.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version   Description
+*         : 01.10.2016 1.00      First Release
+*         : 15.05.2017 2.00      Changed the name of the following macro definition, because there was a mistake
+*                                in the name of macro definition.
+*                                - From XXX_TPU0_TGI0V to XXX_TPU0_TCI0V.
+*                                - From XXX_TPU1_TGI1V to XXX_TPU1_TCI1V.
+*                                - From XXX_TPU1_TGI1U to XXX_TPU1_TCI1U.
+*                                - From XXX_TPU2_TGI2V to XXX_TPU2_TCI2V.
+*                                - From XXX_TPU2_TGI2U to XXX_TPU2_TCI2U.
+*                                - From XXX_TPU3_TGI3V to XXX_TPU3_TCI3V.
+*                                - From XXX_TPU4_TGI4V to XXX_TPU4_TCI4V.
+*                                - From XXX_TPU4_TGI4U to XXX_TPU4_TCI4U.
+*                                - From XXX_TPU5_TGI5V to XXX_TPU5_TCI5V.
+*                                - From XXX_TPU5_TGI5U to XXX_TPU5_TCI5U.
+*                                - From XXX_MTU0_TGIV0 to XXX_MTU0_TCIV0.
+*                                - From XXX_MTU1_TGIV1 to XXX_MTU1_TCIV1.
+*                                - From XXX_MTU1_TGIU1 to XXX_MTU1_TCIU1.
+*                                - From XXX_MTU2_TGIV2 to XXX_MTU2_TCIV2.
+*                                - From XXX_MTU2_TGIU2 to XXX_MTU2_TCIU2.
+*                                - From XXX_MTU3_TGIV3 to XXX_MTU3_TCIV3.
+*                                - From XXX_MTU4_TGIV4 to XXX_MTU4_TCIV4.
+*                                - From XXX_MTU6_TGIV6 to XXX_MTU6_TCIV6.
+*                                - From XXX_MTU7_TGIV7 to XXX_MTU7_TCIV7.
+*                                - From XXX_MTU8_TGIV8 to XXX_MTU8_TCIV8.
+*                                Added select processing of the following software configurable interrupt source.
+*                                - TSIP_PROC_BUSY
+*                                - TSIP_ROMOK
+*                                - TSIP_LONG_PLG
+*                                - TSIP_TEST_BUSY
+*                                - TSIP_WRRDY0
+*                                - TSIP_WRRDY1
+*                                - TSIP_WRRDY4
+*                                - TSIP_RDRDY0
+*                                - TSIP_RDRDY1
+*                                - TSIP_INTEGRATE_WRRDY
+*                                - TSIP_INTEGRATE_RDRDY
+***********************************************************************************************************************/
+#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE
+#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you
+ * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you
+ * would do the following:
+ *
+ * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP                                 176
+ */
+
+/* Interrupt B Sources.
+ * -Valid vector numbers are 128-207.
+ * -There are more vector slots for B sources than actual B sources. By default all B sources are mapped.
+ * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default.
+ * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be
+ *  in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0'
+ *  interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots.
+ */
+#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2                               128
+#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3                               129
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0                              146
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0                              147
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0                               148
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1                              149
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1                              150
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1                               151
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2                              152
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2                              153
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2                               154
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3                              155
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3                              156
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3                               157
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A                              130
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B                              131
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C                              132
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D                              133
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V                              134
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A                              144
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B                              135
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V                              136
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U                              137
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A                              138
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B                              139
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V                              140
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U                              141
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A                              142
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B                              143
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C                              145
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D                              158
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V                              159
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A                              160
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B                              161
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V                              162
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U                              163
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A                              164
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B                              165
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V                              166
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U                              167
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0                             168
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0                             169
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0                             170
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0                             171
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1                             172
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1                             173
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1                             174
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1                             175
+#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP                                 176
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0                               177
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0                               178
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0                               179
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0                               180
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1                               181
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1                               182
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1                               183
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1                               184
+#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0                              185
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0                         186
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0                       187
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0                       188
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1                         189
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1                       190
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1                       191
+#define BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND                              192
+#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I                             193
+#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I                             194
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY                          195
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK                              196
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG                           197
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY                          198
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0                             199
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1                             200
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4                             201
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0                             202
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1                             203
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY                    204
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY                    205
+
+/* Interrupt A Sources.
+ * -Valid vector numbers are 208-255.
+ * -There are more A sources than A vector slots. By default none of the GPT interrupts are mapped.
+ * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default.
+ */
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0                              209
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0                              210
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0                              211
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0                              212
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0                              213
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0                              214
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0                              215
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1                              208
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1                              216
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1                              217
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1                              218
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2                              219
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2                              220
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2                              221
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2                              222
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3                              223
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3                              224
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3                              225
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3                              226
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3                              227
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4                              228
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4                              229
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4                              230
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4                              231
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4                              232
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5                              233
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5                              234
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5                              235
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6                              236
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6                              237
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6                              238
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6                              239
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6                              240
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7                              241
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7                              242
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7                              243
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7                              244
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7                              245
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8                              246
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8                              247
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8                              248
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8                              249
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8                              250
+#define BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY                              251
+#define BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND                              252
+
+#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_cmt_rx_config.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_cmt_rx_config.h
new file mode 100644
index 00000000..a01115bb
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_cmt_rx_config.h
@@ -0,0 +1,49 @@
+/* Generated configuration header file - do not edit */
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer 
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.    
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_cmt_rx_config.h
+* Description  : Configures the r_cmt_rx code.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+*         : 06.11.2013 2.00    First GSCE Release.
+*         : 25.11.2019 4.30    Changed for FIT+RTOS
+*         : 31.08.2020 4.70    Added condition for _RI_TRACE_TIMER macro
+***********************************************************************************************************************/
+#ifndef CMT_CONFIG_HEADER_FILE
+#define CMT_CONFIG_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* The interrupt priority level to be used for CMT interrupts. */
+#define CMT_RX_CFG_IPR         (5)
+
+#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == 0) /* RI600V4 */
+#define _RI_TRACE_TIMER 1 /* RI600V4 uses CMT1 channel for the trace feature.*/
+#elif (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == 1) /* RI600PX */
+#include "r_bsp_config.h"
+#define _RI_TRACE_TIMER BSP_CFG_RTOS_SYSTEM_TIMER /* RI600PX does not actually have the trace feature.*/
+#else
+#define _RI_TRACE_TIMER 1 /* It’s guaranteed that definition _RI_TRACE_TIMER is never used unless BSP_CFG_RTOS_USED == 4.*/
+#endif
+
+#endif /* CMT_CONFIG_HEADER_FILE */
+
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_ether_rx_config.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_ether_rx_config.h
new file mode 100644
index 00000000..b6cbf7c6
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_config/r_ether_rx_config.h
@@ -0,0 +1,149 @@
+/* Generated configuration header file - do not edit */
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name    : r_ether_rx_config.h
+ * Version      : 1.20
+ * Description  : Ethernet module device driver
+ ***********************************************************************************************************************/
+/**********************************************************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 22.07.2014 1.00     First Release
+ *         : 31.03.2016 1.01     Added changes for RX63N.
+ *         : 01.10.2016 1.02     Added changes for RX65N.
+ *         : 01.10.2017 1.03     Added changes for RX65N-2MB.
+ *         : 08.01.2018 1.04     Changed comment.
+ *         : 30.07.2019 1.17     Added changes for RX72M.
+ *         : 22.11.2019 1.20     Added changes for RX72N.
+ ***********************************************************************************************************************/
+
+/* Guards against multiple inclusion */
+#ifndef R_ETHER_RX_CONFIG_H
+    #define R_ETHER_RX_CONFIG_H
+
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+
+/* Ethernet interface select.
+ 0 = MII  (Media Independent Interface)
+ 1 = RMII (Reduced Media Independent Interface)
+ */
+    #define ETHER_CFG_MODE_SEL                          (0)
+
+/* PHY-LSI address setting for ETHER0/1.
+ Please set the value 31 ETHER_CFG_CH0_PHY_ADDRESS when use default setting of the RSK+RX63N.
+ Please set the value 30 ETHER_CFG_CH0_PHY_ADDRESS when use default setting of the RSK+RX65N/RSK+RX65N_2MB.
+ Please set the value 0 ETHER_CFG_CH0_PHY_ADDRESS and value 1 ETHER_CFG_CH1_PHY_ADDRESS when use default setting of the RSK+RX64M/RSK+RX71M.
+ Please set the value 1 ETHER_CFG_CH0_PHY_ADDRESS and value 2 ETHER_CFG_CH1_PHY_ADDRESS when use default setting of the RSK+RX72M.
+ Please set the value 1 ETHER_CFG_CH1_PHY_ADDRESS when use default setting of the RSK+RX72N.
+ */
+    #define ETHER_CFG_CH0_PHY_ADDRESS                   (30)     /* Please define the PHY-LSI address in the range of 0-31. */
+    #define ETHER_CFG_CH1_PHY_ADDRESS                   (1)     /* Please define the PHY-LSI address in the range of 0-31. */
+
+/* The number of Rx descriptors. */
+    #define ETHER_CFG_EMAC_RX_DESCRIPTORS               (8)
+
+/* The number of Tx descriptors. */
+    #define ETHER_CFG_EMAC_TX_DESCRIPTORS               (8)
+
+/* Please define the size of the sending and receiving buffer in the value where one frame can surely be stored 
+ because the driver is single-frame/single-buffer processing.  */
+    #define ETHER_CFG_BUFSIZE                           (1536)  /* Must be 32-byte aligned */
+
+/* EINT interrupt priority level. This definition is not used when EINT interrupt is assigned to Group interrupt. */
+    #define ETHER_CFG_EINT_INT_PRIORITY                 (2)     /* Please define the interruption level within the range of 1-15. */
+
+/* Group AL1 interrupt priority level. This definition is not used when EINT interrupt is assigned to Peripheral 
+ interrupt. */
+    #define ETHER_CFG_AL1_INT_PRIORTY                   (2)     /* Please define the interruption level within the range of 1-15. */
+
+/* The register bus of PHY0/1 for ETHER0/1 select
+ 0 = The access of the register of PHY uses ETHER0.
+ 1 = The access of the register of PHY uses ETHER1.
+
+ Please set the value 0 ETHER_CFG_CH0_PHY_ACCESS when use default setting of the RSK+RX63N.
+ Please set the value 0 ETHER_CFG_CH0_PHY_ACCESS when use default setting of the RSK+RX65N/RSK+RX65N_2MB.
+ Please set the value 1 ETHER_CFG_CH0_PHY_ACCESS and ETHER_CFG_CH1_PHY_ACCESS when use default setting of the RSK+RX64M/RSK+RX71M.
+ Please set the value 0 ETHER_CFG_CH0_PHY_ACCESS and ETHER_CFG_CH1_PHY_ACCESS when use default setting of the RSK+RX72M.
+ Please set the value 1 ETHER_CFG_CH1_PHY_ACCESS when use default setting of the RSK+RX72N.
+ */
+    #define ETHER_CFG_CH0_PHY_ACCESS                    (0)
+    #define ETHER_CFG_CH1_PHY_ACCESS                    (1)
+
+/* Define the access timing of MII/RMII register */
+    #define ETHER_CFG_PHY_MII_WAIT                      (8)     /* Plese define the value of 1 or more */
+
+/* Define the waiting time for reset completion of PHY-LSI */
+    #define ETHER_CFG_PHY_DELAY_RESET                   (0x00020000L)
+
+/**
+ * Link status read from LMON bit of ETHERC PSR register.  The state is hardware dependent.
+ */
+    #define ETHER_CFG_LINK_PRESENT                      (0)
+
+/*  Use LINKSTA signal for detect link status changes
+ 0 = unused  (use PHY-LSI status register)
+ 1 = use     (use LINKSTA signal)
+ */
+    #define ETHER_CFG_USE_LINKSTA                       (1)     /* This setting is reflected in all channels */
+
+/* Definition of whether or not to use KSZ8041NL of the Micrel Inc.
+ 0 = unused
+ 1 = use
+ */
+    #define ETHER_CFG_USE_PHY_KSZ8041NL                 (0)
+
+/* Definition of whether or not to use non blocking of PHY Management Station Operation
+ 0 = unused
+ 1 = use
+*/
+    #define ETHER_CFG_NON_BLOCKING                      (0)
+
+/* Define the clock of the PHY Management Station */
+    #define ETHER_CFG_PMGI_CLOCK                        (2500000)
+
+/* PHY Management Station Preamble Control
+ 0 = Disable
+ 1 = Enable
+ */
+    #define ETHER_CFG_PMGI_ENABLE_PREAMBLE              (0)
+
+/* Define the Hold Time Adjustment of the PHY Management Station */
+    #define ETHER_CFG_PMGI_HOLD_TIME                    (0)
+
+/* Define the Capture Time Adjustment of the PHY Management Station */
+    #define ETHER_CFG_PMGI_CAPTURE_TIME                 (0)
+
+/* PMGI interrupt priority level. This definition is not used when PMGI interrupt is assigned to Peripheral
+ interrupt. */
+    #define ETHER_CFG_PMGI_INT_PRIORTY                  (2)
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global variables
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+#endif /* R_ETHER_RX_CONFIG_H */
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/doc/en/r01an2009ej0121-rx-ether.pdf b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/doc/en/r01an2009ej0121-rx-ether.pdf
new file mode 100644
index 00000000..a4c2dffa
Binary files /dev/null and b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/doc/en/r01an2009ej0121-rx-ether.pdf differ
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/doc/ja/r01an2009jj0121-rx-ether.pdf b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/doc/ja/r01an2009jj0121-rx-ether.pdf
new file mode 100644
index 00000000..d20b179e
Binary files /dev/null and b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/doc/ja/r01an2009jj0121-rx-ether.pdf differ
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/r_ether_rx_if.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/r_ether_rx_if.h
new file mode 100644
index 00000000..882a3cce
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/r_ether_rx_if.h
@@ -0,0 +1,313 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+ * applicable laws, including copyright laws. 
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+ * following link:
+ * http://www.renesas.com/disclaimer 
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.    
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name    : r_ether_rx_if.h
+ * Version      : 1.21
+ * Description  : Ethernet module device driver
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 22.07.2014 1.00     First Release
+ *         : 16.12.2014 1.01     Made changes related to header file include.
+ *         : 27.03.2015 1.02     Changed minor version to '2'.
+ *         : 31.03.2016 1.03     Added changes for RX63N.
+ *         :                     Added changes for multicast frame filter and broadcast frame filter.
+ *         : 01.10.2016 1.04     Added changes for RX65N.
+ *         : 11.11.2016 1.05     Changed minor version to '12'
+ *         : 01.10.2017 1.06     Added changes for RX65N-2MB.
+ *         : 08.01.2018 1.07     Changed minor version to '14'.
+ *         : 07.05.2018 1.08     Changed minor version to '15'.
+ *         : 20.05.2019 1.16     Added support for GNUC and ICCRX.
+ *                               Fixed coding style.
+ *         : 30.07.2019 1.17     Changed minor version to '17'.
+ *         :                     Added changes for RX72M.
+ *         : 22.11.2019 1.20     Changed minor version to '20'.
+ *         :                     Added changes for RX72N.
+ *         :                     Added changes for RX66N.
+ *         :                     Deleted supoort for RX63N.
+ *         :                     Added support for NON_BLOCKING.
+ *         : 10.09.2020 1.21     Changed minor version to '21'.
+ ***********************************************************************************************************************/
+
+/* Guards against multiple inclusion */
+#ifndef R_ETHER_RX_IF_H
+    #define R_ETHER_RX_IF_H
+
+/***********************************************************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+    #include <stdint.h>
+
+    #include "platform.h"
+
+    #include "r_ether_rx_config.h"
+    #include "src/phy/phy.h"
+
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+#if R_BSP_VERSION_MAJOR < 5
+    #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher."
+#endif
+
+ /* Version Number of API. */
+    #define ETHER_RX_VERSION_MAJOR  (1)
+    #define ETHER_RX_VERSION_MINOR  (21)
+
+/* When using the Read functions, ETHER_NO_DATA is the return value that indicates that no received data. */
+    #define ETHER_NO_DATA           (0)
+
+/* The value of flag which indicates that the interrupt of Ethernet occur. */
+    #define ETHER_FLAG_OFF          (0)
+    #define ETHER_FLAG_ON           (1)
+    #define ETHER_FLAG_ON_LINK_ON   (3)
+    #define ETHER_FLAG_ON_LINK_OFF  (2)
+
+/* Channel definition of Ethernet */
+    #define ETHER_CHANNEL_0         (0)
+    #define ETHER_CHANNEL_1         (1)
+
+/* Channel definition of PMGI */
+    #define PMGI_CHANNEL_0          (0)
+    #define PMGI_CHANNEL_1          (1)
+
+/* receive data padding */
+    #define INSERT_POSITION_MAX     (0x3f)
+    #define INSERT_SIZE_MAX         (0x3)
+
+    #if (defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66N))
+        #define ETHER_CHANNEL_MAX       (1)
+    #elif (defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N))
+        #define ETHER_CHANNEL_MAX       (2)
+    #endif
+
+    #if (defined(BSP_MCU_RX66N))
+        #define PMGI_CHANNEL_MAX       (1)
+    #elif (defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N))
+        #define PMGI_CHANNEL_MAX       (2)
+    #endif
+
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+/* ETHER API error codes */
+typedef enum
+{
+    ETHER_SUCCESS = 0, /* Processing completed successfully */
+    ETHER_ERR_INVALID_PTR = -1, /* Value of the pointer is NULL or FIT_NO_PTR */
+    ETHER_ERR_INVALID_DATA = -2, /* Value of the argument is out of range */
+    ETHER_ERR_INVALID_CHAN = -3, /* Nonexistent channel number */
+    ETHER_ERR_INVALID_ARG = -4, /* Invalid argument */
+
+    ETHER_ERR_LINK = -5, /* Auto-negotiation is not completed, and transmission/reception is not
+     enabled. */
+    ETHER_ERR_MPDE = -6, /* As a Magic Packet is being detected, and transmission/reception is not
+     enabled. */
+    ETHER_ERR_TACT = -7, /* Transmit buffer is not empty. */
+    ETHER_ERR_CHAN_OPEN = -8, /* Indicates the Ethernet cannot be opened because it is being used
+     by another application */
+    ETHER_ERR_MC_FRAME = -9, /* Detect multicast frame when multicast frame filtering enable */
+    ETHER_ERR_RECV_ENABLE = -10, /* Enable receive function in ETHERC */
+    ETHER_ERR_LOCKED = -11, /* PMGI locked */
+    ETHER_ERR_OTHER = -12 /* Other error */
+} ether_return_t;
+
+/* Event code of callback function */
+typedef enum
+{
+    ETHER_CB_EVENT_ID_WAKEON_LAN, /* Magic packet detection */
+    ETHER_CB_EVENT_ID_LINK_ON, /* Link up detection */
+    ETHER_CB_EVENT_ID_LINK_OFF, /* Link down detection */
+} ether_cb_event_t;
+
+/* Structure of the callback function pointer */
+typedef struct
+{
+    void (*pcb_func) (void *); /* Callback function pointer */
+    void (*pcb_int_hnd) (void *); /* Interrupt handler function pointer */
+    void (*pcb_pmgi_hnd) (void *); /* Interrupt handler function pointer */
+} ether_cb_t;
+
+/* Structure to be used when decoding the argument of the callback function */
+typedef struct
+{
+    uint32_t         channel; /* ETHERC channel */
+    ether_cb_event_t event_id; /* Event code for callback function */
+    uint32_t         status_ecsr; /* ETHERC status register for interrupt handler */
+    uint32_t         status_eesr; /* ETHERC/EDMAC status register for interrupt handler */
+} ether_cb_arg_t;
+
+/* Parameters of the control function (1st argument) */
+typedef enum
+{
+    CONTROL_SET_CALLBACK, /* Callback function registration */
+    CONTROL_SET_PROMISCUOUS_MODE, /* Promiscuous mode setting */
+    CONTROL_SET_INT_HANDLER, /* Interrupt handler function registration */
+    CONTROL_POWER_ON, /* Cancel ETHERC/EDMAC module stop */
+    CONTROL_POWER_OFF, /* Transition to ETHERC/EDMAC module stop */
+    CONTROL_MULTICASTFRAME_FILTER, /* Multicast frame filter setting*/
+    CONTROL_BROADCASTFRAME_FILTER, /* Broadcast frame filter setting*/
+    CONTROL_RECEIVE_DATA_PADDING, /* Insert receive data padding */
+    CONTROL_SET_PMGI_CALLBACK   /* Set PMGI callback */
+} ether_cmd_t;
+
+typedef enum
+{
+    ETHER_PROMISCUOUS_OFF, /* ETHERC operates in standard mode */
+    ETHER_PROMISCUOUS_ON /* ETHERC operates in promiscuous mode */
+} ether_promiscuous_bit_t;
+
+typedef enum
+{
+    ETHER_MC_FILTER_OFF, /* Multicast frame filter disable */
+    ETHER_MC_FILTER_ON /* Multicast frame filter enable */
+} ether_mc_filter_t;
+
+typedef struct
+{
+    uint32_t                channel; /* ETHERC channel */
+    ether_promiscuous_bit_t bit; /* Promiscuous mode */
+} ether_promiscuous_t;
+
+typedef struct
+{
+    uint32_t          channel; /* ETHERC channel */
+    ether_mc_filter_t flag; /* Multicast frame filter */
+} ether_multicast_t;
+
+typedef struct
+{
+    uint32_t channel; /* ETHERC channel */
+    uint32_t counter; /* Continuous reception number of Broadcast frame */
+} ether_broadcast_t;
+
+
+typedef struct
+{
+    uint32_t    channel; /* ETHERC channel */
+    uint8_t     position; /* Padding insertion position */
+    uint8_t     size; /* Padding insertion size */
+}ether_recv_padding_t;
+
+/* Parameters of the control function (2nd argument) */
+typedef union
+{
+    ether_cb_t              ether_callback; /* Callback function pointer */
+    ether_promiscuous_t     * p_ether_promiscuous; /* Promiscuous mode setting */
+    ether_cb_t              ether_int_hnd; /* Interrupt handler function pointer */
+    uint32_t                channel; /* ETHERC channel number */
+    ether_multicast_t       * p_ether_multicast; /* Multicast frame filter setting */
+    ether_broadcast_t       * p_ether_broadcast; /* Broadcast frame filter setting */
+    ether_cb_t              pmgi_callback; /* PMGI callback function pointer */
+    ether_recv_padding_t    * padding_param; /* Receive data insert parameter */
+} ether_param_t;
+
+/* struct for PMGI */
+/* PMGI mode */
+typedef enum
+{
+    OPEN_ZC2 = 0,
+    CHECKLINK_ZC,
+    LINKPROCESS,
+    WAKEONLAN,
+    LINKPROCESS_OPEN_ZC2,
+    LINKPROCESS_CHECKLINK_ZC0,
+    LINKPROCESS_CHECKLINK_ZC1,
+    LINKPROCESS_CHECKLINK_ZC2,
+    WAKEONLAN_CHECKLINK_ZC,
+    WRITEPHY,
+    READPHY,
+    PMGI_MODE_NUM
+}pmgi_mode_t;
+
+/* PMGI step */
+typedef enum
+{
+    STEP0 = 0,
+    STEP1,
+    STEP2,
+    STEP3,
+    STEP4,
+    STEP5,
+    STEP6,
+    PMGI_STEP_NUM
+}pmgi_step_t;
+
+/* PMGI event */
+typedef enum
+{
+    PMGI_IDLE = 0,
+    PMGI_RUNNING = 1,
+    PMGI_COMPLETE = 2,
+    PMGI_ERROR = -1
+}pmgi_event_t;
+
+/*  */
+typedef struct
+{
+    ether_return_t (* p_func)(uint32_t ether_channel);
+} st_pmgi_interrupt_func_t;
+
+/* PMGI parameter */
+typedef struct
+{
+    BSP_CFG_USER_LOCKING_TYPE       locked;
+    pmgi_event_t                    event;
+    pmgi_mode_t                     mode;
+    pmgi_step_t                     step;
+    uint16_t                        read_data;
+    uint32_t                        reset_counter;
+    uint32_t                        ether_channel;
+}pmgi_param_t;
+
+/* Structure to be used when decoding the argument of the callback function */
+typedef struct
+{
+    uint32_t         channel; /* ETHERC channel */
+    pmgi_event_t     event; /* Event code for callback function */
+    pmgi_mode_t      mode; /* PMGI current mode */
+    uint16_t         reg_data; /* PHY register data for interrupt handler */
+} pmgi_cb_arg_t;
+
+/***********************************************************************************************************************
+ Exported global variables
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+void R_ETHER_Initial (void);
+ether_return_t R_ETHER_Open_ZC2 (uint32_t channel, const uint8_t mac_addr[], uint8_t pause);
+ether_return_t R_ETHER_Close_ZC2 (uint32_t channel);
+int32_t R_ETHER_Read (uint32_t channel, void *pbuf);
+int32_t R_ETHER_Read_ZC2 (uint32_t channel, void **pbuf);
+int32_t R_ETHER_Read_ZC2_BufRelease (uint32_t channel);
+ether_return_t R_ETHER_Write (uint32_t channel, void *pbuf, uint32_t len);
+ether_return_t R_ETHER_Write_ZC2_GetBuf (uint32_t channel, void **pbuf, uint16_t *pbuf_size);
+ether_return_t R_ETHER_Write_ZC2_SetBuf (uint32_t channel, const uint32_t len);
+ether_return_t R_ETHER_CheckLink_ZC (uint32_t channel);
+void R_ETHER_LinkProcess (uint32_t channel);
+ether_return_t R_ETHER_WakeOnLAN (uint32_t channel);
+ether_return_t R_ETHER_CheckWrite (uint32_t channel);
+ether_return_t R_ETHER_Control (ether_cmd_t const cmd, ether_param_t const control);
+ether_return_t R_ETHER_WritePHY(uint32_t channel, uint16_t address, uint16_t data);
+ether_return_t R_ETHER_ReadPHY(uint32_t channel, uint16_t address, uint16_t *p_data);
+uint32_t R_ETHER_GetVersion (void);
+
+#endif  /* R_ETHER_RX_IF_H*/
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/readme.txt b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/readme.txt
new file mode 100644
index 00000000..3e467439
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/readme.txt
@@ -0,0 +1,122 @@
+PLEASE REFER TO THE APPLICATION NOTE FOR THIS MIDDLEWARE FOR MORE INFORMATION
+
+r_ether_rx
+==========
+
+Document Number
+---------------
+R01AN2009EJ0121 (English version)
+R01AN2009JJ0121 (Japanese version)
+
+Version
+-------
+v1.21
+
+Overview
+--------
+The Ethernet FIT module uses an Ethernet controller (ETHERC) and an Ethernet controller DMA controller (EDMAC)
+to implement Ethernet/IEEE 802.3 frame transmission and reception. This module supports the following functions.
+  MII (Media Independent Interface) and RMII (Reduced Media Independent Interface)
+  An automatic negotiating function is used for the Ethernet PHY-LSI link.
+  The link state is detected using the link signals output by the Ethernet PHY-LSI.
+  The result of the automatic negotiation is acquired from the Ethernet PHY-LSI and the connection mode (full or half
+duplex, 10 or 100 Mbps transfer rate) is set in the ETHERC.
+This driver is tested and works with the following toolchain:
+  Renesas RX Toolchain v.3.02.00
+  GCC for Renesas RX 8.3.0
+  IAR C/C++ Compiler for Renesas RX 4.14.1
+All API calls and their supporting interface definitions are located in r_ether_rx_if.h.
+
+Features
+--------
+* Ethernet/IEEE 802.3 frame transmission and reception.
+
+Supported MCUs
+--------------
+* RX65N Group
+* RX64M Group
+* RX71M Group
+* RX72M Group
+* RX72N Group
+* RX66N Group
+
+Boards Tested On
+----------------
+* RSKRX65N
+* RSKRX65N_2MB
+* RSKRX64M
+* RSKRX71M
+* RSKRX72M
+* RSKRX72N
+
+Limitations
+-----------
+* None
+
+Peripherals Used Directly
+-------------------------
+* ETHERC
+* EDMAC
+
+Required Packages
+-----------------
+* r_bsp
+
+How to add to your project
+--------------------------
+Please refer to the Adding Firmware Integration Technology Modules to Projects.
+"r01an1723eu0121_rx.pdf/r01an1826ej0110_rx.pdf/r20an0451es0100-e2studio-sc.pdf"(Only English version)
+"r01an1723ju0121_rx.pdf/r01an1826jj0110_rx.pdf/r20an0451js0100-e2studio-sc.pdf"(Only Japanese version)
+
+
+Toolchain(s) Used
+-----------------
+* Renesas RX v3.02.00
+* GCC for Renesas RX 8.3.0
+* IAR C/C++ Compiler for Renesas RX 4.14.1
+
+File Structure
+--------------
+r_ether_rx
+|       readme.txt
+|       r_ether_rx_if.h
+|
++---doc
+|   |
+|   +---en
+|   |   r01an2009ej0121-rx-ether.pdf
+|   |
+|   \---ja
+|       r01an2009jj0121-rx-ether.pdf
+|
++---ref
+|       r_ether_config_reference.h
+|
+\---src
+    |   r_ether_rx.c
+    |   r_ether_rx_private.h
+    |
+    +---phy
+    |        phy.c
+    |        phy.h
+    |
+    \---targets
+        |
+        |
+        +---rx64m
+        |    r_ether_setting_rx64m.c
+        |
+        +---rx71m
+        |    r_ether_setting_rx71m.c
+        |
+        +---rx65n
+        |    r_ether_setting_rx65n.c
+        |
+        +---rx72m
+        |    r_ether_setting_rx72m.c
+        |
+        +---rx72n
+        |    r_ether_setting_rx72n.c
+        |    
+        \---rx66n
+             r_ether_setting_rx66n.c
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/ref/r_ether_rx_config_reference.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/ref/r_ether_rx_config_reference.h
new file mode 100644
index 00000000..b193d502
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/ref/r_ether_rx_config_reference.h
@@ -0,0 +1,148 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name    : r_ether_rx_config.h
+ * Version      : 1.20
+ * Description  : Ethernet module device driver
+ ***********************************************************************************************************************/
+/**********************************************************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 22.07.2014 1.00     First Release
+ *         : 31.03.2016 1.01     Added changes for RX63N.
+ *         : 01.10.2016 1.02     Added changes for RX65N.
+ *         : 01.10.2017 1.03     Added changes for RX65N-2MB.
+ *         : 08.01.2018 1.04     Changed comment.
+ *         : 30.07.2019 1.17     Added changes for RX72M.
+ *         : 22.11.2019 1.20     Added changes for RX72N.
+ ***********************************************************************************************************************/
+
+/* Guards against multiple inclusion */
+#ifndef R_ETHER_RX_CONFIG_H
+    #define R_ETHER_RX_CONFIG_H
+
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+
+/* Ethernet interface select.
+ 0 = MII  (Media Independent Interface)
+ 1 = RMII (Reduced Media Independent Interface)
+ */
+    #define ETHER_CFG_MODE_SEL                          (0)
+
+/* PHY-LSI address setting for ETHER0/1.
+ Please set the value 31 ETHER_CFG_CH0_PHY_ADDRESS when use default setting of the RSK+RX63N.
+ Please set the value 30 ETHER_CFG_CH0_PHY_ADDRESS when use default setting of the RSK+RX65N/RSK+RX65N_2MB.
+ Please set the value 0 ETHER_CFG_CH0_PHY_ADDRESS and value 1 ETHER_CFG_CH1_PHY_ADDRESS when use default setting of the RSK+RX64M/RSK+RX71M.
+ Please set the value 1 ETHER_CFG_CH0_PHY_ADDRESS and value 2 ETHER_CFG_CH1_PHY_ADDRESS when use default setting of the RSK+RX72M.
+ Please set the value 1 ETHER_CFG_CH1_PHY_ADDRESS when use default setting of the RSK+RX72N.
+ */
+    #define ETHER_CFG_CH0_PHY_ADDRESS                   (0)     /* Please define the PHY-LSI address in the range of 0-31. */
+    #define ETHER_CFG_CH1_PHY_ADDRESS                   (1)     /* Please define the PHY-LSI address in the range of 0-31. */
+
+/* The number of Rx descriptors. */
+    #define ETHER_CFG_EMAC_RX_DESCRIPTORS               (1)
+
+/* The number of Tx descriptors. */
+    #define ETHER_CFG_EMAC_TX_DESCRIPTORS               (1)
+
+/* Please define the size of the sending and receiving buffer in the value where one frame can surely be stored 
+ because the driver is single-frame/single-buffer processing.  */
+    #define ETHER_CFG_BUFSIZE                           (1536)  /* Must be 32-byte aligned */
+
+/* EINT interrupt priority level. This definition is not used when EINT interrupt is assigned to Group interrupt. */
+    #define ETHER_CFG_EINT_INT_PRIORITY                 (2)     /* Please define the interruption level within the range of 1-15. */
+
+/* Group AL1 interrupt priority level. This definition is not used when EINT interrupt is assigned to Peripheral 
+ interrupt. */
+    #define ETHER_CFG_AL1_INT_PRIORTY                   (2)     /* Please define the interruption level within the range of 1-15. */
+
+/* The register bus of PHY0/1 for ETHER0/1 select
+ 0 = The access of the register of PHY uses ETHER0.
+ 1 = The access of the register of PHY uses ETHER1.
+
+ Please set the value 0 ETHER_CFG_CH0_PHY_ACCESS when use default setting of the RSK+RX63N.
+ Please set the value 0 ETHER_CFG_CH0_PHY_ACCESS when use default setting of the RSK+RX65N/RSK+RX65N_2MB.
+ Please set the value 1 ETHER_CFG_CH0_PHY_ACCESS and ETHER_CFG_CH1_PHY_ACCESS when use default setting of the RSK+RX64M/RSK+RX71M.
+ Please set the value 0 ETHER_CFG_CH0_PHY_ACCESS and ETHER_CFG_CH1_PHY_ACCESS when use default setting of the RSK+RX72M.
+ Please set the value 1 ETHER_CFG_CH1_PHY_ACCESS when use default setting of the RSK+RX72N.
+ */
+    #define ETHER_CFG_CH0_PHY_ACCESS                    (1)
+    #define ETHER_CFG_CH1_PHY_ACCESS                    (1)
+
+/* Define the access timing of MII/RMII register */
+    #define ETHER_CFG_PHY_MII_WAIT                      (8)     /* Plese define the value of 1 or more */
+
+/* Define the waiting time for reset completion of PHY-LSI */
+    #define ETHER_CFG_PHY_DELAY_RESET                   (0x00020000L)
+
+/**
+ * Link status read from LMON bit of ETHERC PSR register.  The state is hardware dependent.
+ */
+    #define ETHER_CFG_LINK_PRESENT                      (0)
+
+/*  Use LINKSTA signal for detect link status changes
+ 0 = unused  (use PHY-LSI status register)
+ 1 = use     (use LINKSTA signal)
+ */
+    #define ETHER_CFG_USE_LINKSTA                       (1)     /* This setting is reflected in all channels */
+
+/* Definition of whether or not to use KSZ8041NL of the Micrel Inc.
+ 0 = unused
+ 1 = use
+ */
+    #define ETHER_CFG_USE_PHY_KSZ8041NL                 (0)
+
+/* Definition of whether or not to use non blocking of PHY Management Station Operation
+ 0 = unused
+ 1 = use
+*/
+    #define ETHER_CFG_NON_BLOCKING                      (0)
+
+/* Define the clock of the PHY Management Station */
+    #define ETHER_CFG_PMGI_CLOCK                        (2500000)
+
+/* PHY Management Station Preamble Control
+ 0 = Disable
+ 1 = Enable
+ */
+    #define ETHER_CFG_PMGI_ENABLE_PREAMBLE              (0)
+
+/* Define the Hold Time Adjustment of the PHY Management Station */
+    #define ETHER_CFG_PMGI_HOLD_TIME                    (0)
+
+/* Define the Capture Time Adjustment of the PHY Management Station */
+    #define ETHER_CFG_PMGI_CAPTURE_TIME                 (0)
+
+/* PMGI interrupt priority level. This definition is not used when PMGI interrupt is assigned to Peripheral
+ interrupt. */
+    #define ETHER_CFG_PMGI_INT_PRIORTY                  (2)
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global variables
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+#endif /* R_ETHER_RX_CONFIG_H */
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/phy/phy.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/phy/phy.c
new file mode 100644
index 00000000..985f8f18
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/phy/phy.c
@@ -0,0 +1,890 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+ * applicable laws, including copyright laws. 
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+ * following link:
+ * http://www.renesas.com/disclaimer 
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.    
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name    : phy.c
+ * Version      : 1.20
+ * Description  : Ethernet PHY device driver
+ ***********************************************************************************************************************/
+/**********************************************************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 22.07.2014 1.00     First Release
+ *         : 16.12.2014 1.01     Made changes related to header file include.
+ *         : 29.01.2015 1.02     Correction of ETHER_CFG_USE_PHY_KSZ8041NL.
+ *         : 31.03.2016 1.10     Added changes behavior of phy_get_link_status function depending on number of Ethernet channel.
+ *         : 20.05.2019 1.16     Added support for GNUC and ICCRX.
+ *                               Fixed coding style.
+ *         : 30.07.2019 1.17     Added WAIT LOOP.
+ *         : 22.11.2019 1.20     Added macro ETHER_CFG_NON_BLOCKING to choose whether to use PMGI.
+ *                               Added pmgi_initial, pmgi_access, pmgi_read_reg, pmgi_close function for NON-BLOCKING.
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+/* Access to peripherals and board defines. */
+#include "platform.h"
+
+#include "r_ether_rx_config.h"
+#include "src/r_ether_rx_private.h"
+#include "src/phy/phy.h"
+
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+/* Media Independent Interface */
+#define PHY_MII_ST                      (1)
+#define PHY_MII_READ                    (2)
+#define PHY_MII_WRITE                   (1)
+
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global variables (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Private global variables and functions
+ ***********************************************************************************************************************/
+#if ETHER_CFG_NON_BLOCKING == 0
+uint16_t phy_read (uint32_t ether_channel, uint16_t reg_addr);
+void phy_write (uint32_t ether_channel, uint16_t reg_addr, uint16_t data);
+static void phy_preamble (uint32_t ether_channel);
+static void phy_reg_set (uint32_t ether_channel, uint16_t reg_addr, int32_t option);
+static void phy_reg_read (uint32_t ether_channel, uint16_t *pdata);
+static void phy_reg_write (uint32_t ether_channel, uint16_t data);
+static void phy_trans_zto0 (uint32_t ether_channel);
+static void phy_trans_1to0 (uint32_t ether_channel);
+static void phy_mii_write1 (uint32_t ether_channel);
+static void phy_mii_write0 (uint32_t ether_channel);
+static int16_t phy_get_pir_address (uint32_t ether_channel, volatile uint32_t R_BSP_EVENACCESS_SFR ** pppir_addr);
+
+static uint16_t local_advertise[ETHER_CHANNEL_MAX]; /* the capabilities of the local link as PHY data */
+#endif
+
+/*
+ * Private global variables
+ */
+#if ETHER_CFG_NON_BLOCKING == 1
+
+  /* Used to prevent having duplicate code for each channel. This only works if the channels are identical (just at
+   different locations in memory). This is easy to tell by looking in iodefine.h and seeing if the same structure
+   was used for all channels. */
+volatile struct st_pmgi R_BSP_EVENACCESS_SFR * gp_pmgi_channels[PMGI_CHANNEL_MAX] =
+{
+/* Initialize the array for up to 3 channels. Add more as needed. */
+#if   PMGI_CHANNEL_MAX == 1
+    &PMGI0,
+#elif PMGI_CHANNEL_MAX == 2
+    &PMGI0, &PMGI1
+#endif
+};
+#endif
+/**
+ * Public functions
+ */
+#if ETHER_CFG_NON_BLOCKING == 0
+/***********************************************************************************************************************
+ * Function Name: phy_init
+ * Description  : Resets Ethernet PHY device
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : R_PHY_OK -
+ *                    
+ *                R_PHY_ERROR -
+ *                    
+ ***********************************************************************************************************************/
+int16_t phy_init (uint32_t ether_channel)
+{
+    uint16_t reg;
+    uint32_t count;
+
+    /* Reset PHY */
+    phy_write(ether_channel, PHY_REG_CONTROL, PHY_CONTROL_RESET);
+
+    count = 0;
+
+    /* Reset completion waiting */
+    do
+    {
+        reg = phy_read(ether_channel, PHY_REG_CONTROL);
+        count++;
+    } while ((reg & PHY_CONTROL_RESET) && (count < ETHER_CFG_PHY_DELAY_RESET));     /* WAIT_LOOP */
+
+    if (count < ETHER_CFG_PHY_DELAY_RESET)
+    {
+        /* 
+         * When KSZ8041NL of the Micrel, Inc. is used, 
+         * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default. 
+         * The setting of the pin is changed so that only the state of LINK is output. 
+         */
+#if ETHER_CFG_USE_PHY_KSZ8041NL != 0
+        reg = phy_read(ether_channel, PHY_REG_PHY_CONTROL_1);
+        reg &= ~0x8000;
+        reg |= 0x4000;
+        phy_write(ether_channel, PHY_REG_PHY_CONTROL_1, reg);
+#endif /* ETHER_CFG_USE_PHY_KSZ8041NL != 0 */
+
+        return R_PHY_OK;
+    }
+
+    return R_PHY_ERROR;
+} /* End of function phy_init() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_start_autonegotiate
+ * Description  : Starts auto-negotiate
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                pause -
+ *                    Using state of pause frames
+ * Return Value : none
+ ***********************************************************************************************************************/
+void phy_start_autonegotiate (uint32_t ether_channel, uint8_t pause)
+{
+    volatile uint16_t reg = 0;
+
+    /* Set local ability */
+    /* When pause frame is not used */
+    if (ETHER_FLAG_OFF == pause)
+    {
+        local_advertise[ether_channel] = ((((PHY_AN_ADVERTISEMENT_100F |
+        PHY_AN_ADVERTISEMENT_100H) |
+        PHY_AN_ADVERTISEMENT_10F) |
+        PHY_AN_ADVERTISEMENT_10H) |
+        PHY_AN_ADVERTISEMENT_SELECTOR);
+
+    }
+
+    /* When pause frame is used */
+    else
+    {
+        local_advertise[ether_channel] = ((((((PHY_AN_ADVERTISEMENT_ASM_DIR |
+        PHY_AN_ADVERTISEMENT_PAUSE) |
+        PHY_AN_ADVERTISEMENT_100F) |
+        PHY_AN_ADVERTISEMENT_100H) |
+        PHY_AN_ADVERTISEMENT_10F) |
+        PHY_AN_ADVERTISEMENT_10H) |
+        PHY_AN_ADVERTISEMENT_SELECTOR);
+    }
+
+    /* Configure what the PHY and the Ethernet controller on this board supports */
+    phy_write(ether_channel, PHY_REG_AN_ADVERTISEMENT, local_advertise[ether_channel]);
+    phy_write(ether_channel, PHY_REG_CONTROL, (PHY_CONTROL_AN_ENABLE |
+    PHY_CONTROL_AN_RESTART));
+
+    reg = phy_read(ether_channel, PHY_REG_AN_ADVERTISEMENT);
+
+} /* End of function phy_start_autonegotiate() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_set_autonegotiate
+ * Description  : reports the other side's physical capability
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *              : *pline_speed_duplex - 
+ *                    a pointer to the location of both the line speed and the duplex
+ *                *plocal_pause - 
+ *                    a pointer to the location to store the local pause bits.
+ *                *ppartner_pause - 
+ *                    a pointer to the location to store the partner pause bits.
+ * Return Value : R_PHY_OK -
+ *                    
+ *                R_PHY_ERROR -
+ *                    
+ * Note         : The value returned to local_pause and patner_pause is used 
+ *                as it is as an argument of ether_pause_resolution function. 
+ ***********************************************************************************************************************/
+int16_t phy_set_autonegotiate (uint32_t ether_channel, uint16_t *pline_speed_duplex, uint16_t *plocal_pause,
+        uint16_t *ppartner_pause)
+{
+    uint16_t reg;
+
+    /* Because reading the first time shows the previous state, the Link status bit is read twice. */
+    reg = phy_read(ether_channel, PHY_REG_STATUS);
+    reg = phy_read(ether_channel, PHY_REG_STATUS);
+
+    /* When the link isn't up, return error */
+    if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP))
+    {
+        R_BSP_NOP();
+        return R_PHY_ERROR;
+    }
+
+    /* Establish local pause capability */
+    if (PHY_AN_ADVERTISEMENT_PAUSE == (local_advertise[ether_channel] & PHY_AN_ADVERTISEMENT_PAUSE))
+    {
+        (*plocal_pause) |= (1 << 1);
+    }
+
+    if (PHY_AN_ADVERTISEMENT_ASM_DIR == (local_advertise[ether_channel] & PHY_AN_ADVERTISEMENT_ASM_DIR))
+    {
+        (*plocal_pause) |= 1;
+    }
+
+    /* When the auto-negotiation isn't completed, return error */
+    if (PHY_STATUS_AN_COMPLETE != (reg & PHY_STATUS_AN_COMPLETE))
+    {
+        return R_PHY_ERROR;
+    }
+    else
+    {
+        /* Get the link partner response */
+        reg = phy_read(ether_channel, PHY_REG_AN_LINK_PARTNER);
+
+        /* Establish partner pause capability */
+        if (PHY_AN_LINK_PARTNER_PAUSE == (reg & PHY_AN_LINK_PARTNER_PAUSE))
+        {
+            (*ppartner_pause) = (1 << 1);
+        }
+
+        if (PHY_AN_LINK_PARTNER_ASM_DIR == (reg & PHY_AN_LINK_PARTNER_ASM_DIR))
+        {
+            (*ppartner_pause) |= 1;
+        }
+
+        /* Establish the line speed and the duplex */
+        if (PHY_AN_LINK_PARTNER_10H == (reg & PHY_AN_LINK_PARTNER_10H))
+        {
+            (*pline_speed_duplex) = PHY_LINK_10H;
+        }
+
+        if (PHY_AN_LINK_PARTNER_10F == (reg & PHY_AN_LINK_PARTNER_10F))
+        {
+            (*pline_speed_duplex) = PHY_LINK_10F;
+        }
+
+        if (PHY_AN_LINK_PARTNER_100H == (reg & PHY_AN_LINK_PARTNER_100H))
+        {
+            (*pline_speed_duplex) = PHY_LINK_100H;
+        }
+
+        if (PHY_AN_LINK_PARTNER_100F == (reg & PHY_AN_LINK_PARTNER_100F))
+        {
+            (*pline_speed_duplex) = PHY_LINK_100F;
+        }
+
+        return R_PHY_OK;
+    }
+} /* End of function phy_set_autonegotiate() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_get_link_status 
+ * Description  : Returns the status of the physical link 
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : -1 if links is down, 0 otherwise 
+ ***********************************************************************************************************************/
+int16_t phy_get_link_status (uint32_t ether_channel)
+{
+    uint16_t reg;
+
+    /* Because reading the first time shows the previous state, the Link status bit is read twice. */
+    reg = phy_read(ether_channel, PHY_REG_STATUS);
+    reg = phy_read(ether_channel, PHY_REG_STATUS);
+
+    /* When the link isn't up, return error */
+    if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP))
+    {
+        R_BSP_NOP();
+
+        /* Link is down */
+        return R_PHY_ERROR;
+    }
+    else
+    {
+        /* Link is up */
+        return R_PHY_OK;
+    }
+} /* End of function phy_get_link_status() */
+
+/**
+ * Private functions
+ */
+
+/***********************************************************************************************************************
+ * Function Name: phy_read
+ * Description  : Reads a PHY register
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                reg_addr -
+ *                    address of the PHY register
+ * Return Value : read value
+ ***********************************************************************************************************************/
+uint16_t phy_read (uint32_t ether_channel, uint16_t reg_addr)
+{
+    uint16_t data;
+
+    /*
+     * The value is read from the PHY register by the frame format of MII Management Interface provided 
+     * for by Table 22-12 of 22.2.4.5 of IEEE 802.3-2008_section2. 
+     */
+    phy_preamble(ether_channel);
+    phy_reg_set(ether_channel, reg_addr, PHY_MII_READ);
+    phy_trans_zto0(ether_channel);
+    phy_reg_read(ether_channel, &data);
+    phy_trans_zto0(ether_channel);
+
+    return (data);
+} /* End of function phy_read() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_write
+ * Description  : Writes to a PHY register
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                reg_addr -
+ *                    address of the PHY register
+ *                data -
+ *                    value
+ * Return Value : none
+ ***********************************************************************************************************************/
+void phy_write (uint32_t ether_channel, uint16_t reg_addr, uint16_t data)
+{
+    /*
+     * The value is read from the PHY register by the frame format of MII Management Interface provided
+     * for by Table 22-12 of 22.2.4.5 of IEEE 802.3-2008_section2. 
+     */
+    phy_preamble(ether_channel);
+    phy_reg_set(ether_channel, reg_addr, PHY_MII_WRITE);
+    phy_trans_1to0(ether_channel);
+    phy_reg_write(ether_channel, data);
+    phy_trans_zto0(ether_channel);
+} /* End of function phy_write() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_preamble
+ * Description  : As preliminary preparation for access to the PHY module register,
+ *                "1" is output via the MII management interface.                  
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_preamble (uint32_t ether_channel)
+{
+    int16_t i;
+
+    /*
+     * The processing of PRE (preamble) about the frame format of MII Management Interface which is 
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    i = 32;
+    /* WAIT_LOOP */
+    while (i > 0)
+    {
+        phy_mii_write1(ether_channel);
+        i--;
+    }
+} /* End of function phy_preamble() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_reg_set
+ * Description  : Sets a PHY device to read or write mode
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                reg_addr -
+ *                    address of the PHY register
+ *                option -
+ *                    mode
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_reg_set (uint32_t ether_channel, uint16_t reg_addr, int32_t option)
+{
+    int32_t i;
+    uint16_t data;
+    int8_t phy_acc_channel;
+    const ether_control_t * pether_control;
+
+    /*
+     * The processing of ST (start of frame),OP (operation code), PHYAD (PHY Address), and 
+     * REGAD (Register Address)  about the frame format of MII Management Interface which is 
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    data = 0;
+    data = (PHY_MII_ST << 14); /* ST code    */
+
+    if (PHY_MII_READ == option)
+    {
+        data |= (PHY_MII_READ << 12); /* OP code(RD)  */
+    }
+    else
+    {
+        data |= (PHY_MII_WRITE << 12); /* OP code(WT)  */
+    }
+
+    phy_acc_channel = g_eth_control_ch[ether_channel].phy_access;
+
+    pether_control = g_eth_control_ch[ether_channel].pether_control;
+
+    data |= (uint16_t) (pether_control[phy_acc_channel].phy_address << 7); /* PHY Address  */
+
+    data |= (reg_addr << 2); /* Reg Address  */
+
+    i = 14;
+    /* WAIT_LOOP */
+    while (i > 0)
+    {
+        if (0 == (data & 0x8000))
+        {
+            phy_mii_write0(ether_channel);
+        }
+        else
+        {
+            phy_mii_write1(ether_channel);
+        }
+        data <<= 1;
+        i--;
+    }
+} /* End of function phy_reg_set() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_reg_read
+ * Description  : Reads PHY register through MII interface
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                pdata -
+ *                    pointer to store the data read
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_reg_read (uint32_t ether_channel, uint16_t *pdata)
+{
+    int32_t i;
+    int32_t j;
+    uint16_t reg_data;
+    int16_t ret;
+    volatile uint32_t R_BSP_EVENACCESS_SFR * petherc_pir;
+
+    ret = phy_get_pir_address(ether_channel, &petherc_pir);
+    if ( R_PHY_ERROR == ret)
+    {
+        return;
+    }
+
+    /*
+     * The processing of DATA (data) about reading of the frame format of MII Management Interface which is 
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    reg_data = 0;
+    i = 16;
+    /* WAIT_LOOP */
+    while (i > 0)
+    {
+        /* WAIT_LOOP */
+        for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+        {
+            (*petherc_pir) = 0x00000000;
+        }
+
+        /* WAIT_LOOP */
+        for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+        {
+            (*petherc_pir) = 0x00000001;
+        }
+        reg_data <<= 1;
+
+        reg_data |= (uint16_t) (((*petherc_pir) & 0x00000008) >> 3); /* MDI read  */
+
+        /* WAIT_LOOP */
+        for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+        {
+            (*petherc_pir) = 0x00000001;
+        }
+
+        /* WAIT_LOOP */
+        for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+        {
+            (*petherc_pir) = 0x00000000;
+        }
+
+        i--;
+    }
+    (*pdata) = reg_data;
+} /* End of function phy_reg_read() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_reg_write
+ * Description  : Writes to PHY register through MII interface
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                data -
+ *                    value to write
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_reg_write (uint32_t ether_channel, uint16_t data)
+{
+    int32_t i;
+
+    /*
+     * The processing of DATA (data) about writing of the frame format of MII Management Interface which is 
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    i = 16;
+    /* WAIT_LOOP */
+    while (i > 0)
+    {
+        if (0 == (data & 0x8000))
+        {
+            phy_mii_write0(ether_channel);
+        }
+        else
+        {
+            phy_mii_write1(ether_channel);
+        }
+        i--;
+        data <<= 1;
+    }
+} /* End of function phy_reg_write() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_trans_zto0
+ * Description  : Performs bus release so that PHY can drive data
+ *              : for read operation 
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_trans_zto0 (uint32_t ether_channel)
+{
+    int32_t j;
+    int16_t ret;
+    volatile uint32_t R_BSP_EVENACCESS_SFR * petherc_pir;
+
+    ret = phy_get_pir_address(ether_channel, &petherc_pir);
+    if ( R_PHY_ERROR == ret)
+    {
+        return;
+    }
+
+    /*
+     * The processing of TA (turnaround) about reading of the frame format of MII Management Interface which is 
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000000;
+    }
+
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000001;
+    }
+
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000001;
+    }
+
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000000;
+    }
+
+} /* End of function phy_trans_zto0() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_trans_1to0
+ * Description  : Switches data bus so MII interface can drive data
+ *              : for write operation 
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_trans_1to0 (uint32_t ether_channel)
+{
+    /*
+     * The processing of TA (turnaround) about writing of the frame format of MII Management Interface which is
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2".
+     */
+    phy_mii_write1(ether_channel);
+    phy_mii_write0(ether_channel);
+} /* End of function phy_trans_1to0() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_mii_write1
+ * Description  : Outputs 1 to the MII interface 
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_mii_write1 (uint32_t ether_channel)
+{
+    int32_t j;
+    int16_t ret;
+    volatile uint32_t R_BSP_EVENACCESS_SFR * petherc_pir;
+
+    ret = phy_get_pir_address(ether_channel, &petherc_pir);
+    if ( R_PHY_ERROR == ret)
+    {
+        return;
+    }
+
+    /*
+     * The processing of one bit about frame format of MII Management Interface which is 
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". 
+     * The data that 1 is output. 
+     */
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000006;
+    }
+
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000007;
+    }
+
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000007;
+    }
+
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000006;
+    }
+
+} /* End of function phy_mii_write1() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_mii_write0
+ * Description  : Outputs 0 to the MII interface 
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void phy_mii_write0 (uint32_t ether_channel)
+{
+    int32_t j;
+    int16_t ret;
+    volatile uint32_t R_BSP_EVENACCESS_SFR * petherc_pir;
+
+    ret = phy_get_pir_address(ether_channel, &petherc_pir);
+    if ( R_PHY_ERROR == ret)
+    {
+        return;
+    }
+
+    /*
+     * The processing of one bit about frame format of MII Management Interface which is 
+     * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". 
+     * The data that 0 is output. 
+     */
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000002;
+    }
+
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000003;
+    }
+
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000003;
+    }
+
+    /* WAIT_LOOP */
+    for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
+    {
+        (*petherc_pir) = 0x00000002;
+    }
+
+} /* End of function phy_mii_write0() */
+
+/***********************************************************************************************************************
+ * Function Name: phy_get_pir_address
+ * Description  : Get the address of the PHY interface register.
+ * Arguments    : ether_channel -
+ *                    Ethernet channel number
+ *                pppir_addr -
+ *                    Pointer of the PHY interface register
+ * Return Value : none
+ ***********************************************************************************************************************/
+static int16_t phy_get_pir_address (uint32_t ether_channel, volatile uint32_t R_BSP_EVENACCESS_SFR ** pppir_addr)
+{
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+    volatile uint32_t R_BSP_EVENACCESS_SFR * petherc_pir;
+
+    if (ETHER_CHANNEL_MAX <= ether_channel)
+    {
+        return R_PHY_ERROR;
+    }
+
+    pether_ch = g_eth_control_ch[ether_channel].pether_control;
+    phy_access = g_eth_control_ch[ether_channel].phy_access;
+    petherc_pir = pether_ch[phy_access].preg_pir;
+
+    (*pppir_addr) = petherc_pir;
+
+    return R_PHY_OK;
+} /* End of function phy_get_pir_address() */
+
+#endif /* End of ETHER_CFG_NON_BLOCKING == 0 */
+
+#if ETHER_CFG_NON_BLOCKING == 1
+/***********************************************************************************************************************
+ * Function Name: pmgi_initial
+ * Description  : PMGI initialze.
+ * Arguments    : pmgi_channel -
+ *                    PMGI channel number
+ * Return Value : R_PHY_OK      success
+                : R_PHY_ERROR   error
+ ***********************************************************************************************************************/
+int16_t pmgi_initial(uint16_t pmgi_channel)
+{
+    int32_t     f;  // Frequency
+    int32_t     n;  // n term in equation
+
+    /* set the frequency of MDC */
+    f = BSP_PCLKA_HZ;
+    n = (f/(ETHER_CFG_PMGI_CLOCK * 2)) - 1;
+
+    if ((n <= 0) || (n > 63))
+    {
+        return R_PHY_ERROR;
+    }
+    else
+    {
+        (*gp_pmgi_channels[pmgi_channel]).PMGCR.BIT.PSMCS = n;
+    }
+
+    /* set the preamble control bit */
+    (*gp_pmgi_channels[pmgi_channel]).PMGCR.BIT.PSMDP = ETHER_CFG_PMGI_ENABLE_PREAMBLE;
+
+    /* set the hold time adjustment */
+    (*gp_pmgi_channels[pmgi_channel]).PMGCR.BIT.PSMHT = ETHER_CFG_PMGI_HOLD_TIME;
+
+    /* set the capture time adjustment */
+    (*gp_pmgi_channels[pmgi_channel]).PMGCR.BIT.PSMCT = ETHER_CFG_PMGI_CAPTURE_TIME;
+
+#if ((ETHER_CFG_CH0_PHY_ACCESS == 0) || (ETHER_CFG_CH1_PHY_ACCESS == 0))
+    if (PMGI_CHANNEL_0 == pmgi_channel)
+    {
+        R_BSP_InterruptRequestEnable(VECT(PMGI0, PMGI0I));
+        IPR(PMGI0, PMGI0I) = ETHER_CFG_PMGI_INT_PRIORTY;
+    }
+#endif
+#if (PMGI_CHANNEL_MAX == 2)
+#if ((ETHER_CFG_CH0_PHY_ACCESS == 1) || (ETHER_CFG_CH1_PHY_ACCESS == 1))
+    if (PMGI_CHANNEL_1 == pmgi_channel)
+    {
+        R_BSP_InterruptRequestEnable(VECT(PMGI1, PMGI1I));
+        IPR(PMGI1, PMGI1I) = ETHER_CFG_PMGI_INT_PRIORTY;
+    }
+#endif
+#endif
+
+    return R_PHY_OK;
+} /* End of function pmgi_initial */
+
+/***********************************************************************************************************************
+ * Function Name: pmgi_read_reg
+ * Description  : read PMGI register.
+ * Arguments    : pmgi_channel -
+ *                    PMGI channel number
+ * Return Value : reg      register value
+ ***********************************************************************************************************************/
+uint16_t pmgi_read_reg(uint16_t pmgi_channel)
+{
+    uint16_t reg;
+
+    reg = (*gp_pmgi_channels[pmgi_channel]).PSMR.BIT.PRD;
+
+    return reg;
+} /*End of function pmgi_read_reg */
+
+/***********************************************************************************************************************
+ * Function Name: pmgi_close
+ * Description  : PMGI close.
+ * Arguments    : pmgi_channel -
+ *                    PMGI channel number
+ * Return Value : R_PHY_OK      success
+ ***********************************************************************************************************************/
+int16_t pmgi_close(uint16_t pmgi_channel)
+{
+#if ((ETHER_CFG_CH0_PHY_ACCESS == 0) || (ETHER_CFG_CH1_PHY_ACCESS == 0))
+    if (PMGI_CHANNEL_0 == pmgi_channel )
+    {
+        R_BSP_InterruptRequestDisable(VECT(PMGI0, PMGI0I));
+    }
+#endif
+#if (PMGI_CHANNEL_MAX == 2)
+#if ((ETHER_CFG_CH0_PHY_ACCESS == 1) || (ETHER_CFG_CH1_PHY_ACCESS == 1))
+    if (PMGI_CHANNEL_1 == pmgi_channel )
+    {
+        R_BSP_InterruptRequestDisable(VECT(PMGI1, PMGI1I));
+    }
+#endif
+#endif
+    return R_PHY_OK;
+} /* End of function pmgi_close */
+
+/***********************************************************************************************************************
+ * Function Name: pmgi_access
+ * Description  : PMGI access.
+ * Arguments    : channel -
+ *                    ETHER     channel number
+ *                    address   phy register address
+ *                    data      access data
+ *                    dir       access direction
+ * Return Value : R_PHY_OK      success
+                : R_PHY_ERROR   error
+ ***********************************************************************************************************************/
+int16_t pmgi_access(uint32_t channel, uint16_t address, uint16_t data, uint16_t dir)
+{
+    uint16_t pmgi_channel;
+
+    if (ETHER_CHANNEL_0 == channel)
+    {
+        pmgi_channel = ETHER_CFG_CH0_PHY_ACCESS;
+        (*gp_pmgi_channels[pmgi_channel]).PSMR.BIT.PDA = ETHER_CFG_CH0_PHY_ADDRESS;
+    }
+    else
+    {
+        pmgi_channel = ETHER_CFG_CH1_PHY_ACCESS;
+        (*gp_pmgi_channels[pmgi_channel]).PSMR.BIT.PDA = ETHER_CFG_CH1_PHY_ADDRESS;
+    }
+    (*gp_pmgi_channels[pmgi_channel]).PSMR.BIT.PSMAD = dir;
+    (*gp_pmgi_channels[pmgi_channel]).PSMR.BIT.PRA = address;
+
+    if (PMGI_WRITE == dir)
+    {
+        (*gp_pmgi_channels[pmgi_channel]).PSMR.BIT.PRD = data;
+    }
+
+    (*gp_pmgi_channels[pmgi_channel]).PSMR.BIT.PSME = PMGI_START;
+
+    return R_PHY_OK;
+} /*End of function pmgi_access */
+#endif /* End of ETHER_CFG_NON_BLOCKING == 1 */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/phy/phy.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/phy/phy.h
new file mode 100644
index 00000000..7b1f825a
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/phy/phy.h
@@ -0,0 +1,144 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+ * applicable laws, including copyright laws. 
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+ * following link:
+ * http://www.renesas.com/disclaimer 
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.    
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name    : phy.h
+ * Version      : 1.01
+ * Description  : Ethernet PHY device driver
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 22.07.2014 1.00     First Release
+ *         : 16.12.2014 1.01     Deleted header file include.
+ *         : 22.11.2019 1.20     Added the macro of the phy register
+ *                               Added PMGI API function
+ ***********************************************************************************************************************/
+
+/* Guards against multiple inclusion */
+#ifndef PHY_H
+    #define PHY_H
+
+/***********************************************************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+    #include <stdint.h>
+
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+/* PHY return definitions */
+    #define R_PHY_OK        (0)
+    #define R_PHY_ERROR     (-1)
+
+/* Standard PHY Registers */
+    #define PHY_REG_CONTROL                 (0)
+    #define PHY_REG_STATUS                  (1)
+    #define PHY_REG_IDENTIFIER1             (2)
+    #define PHY_REG_IDENTIFIER2             (3)
+    #define PHY_REG_AN_ADVERTISEMENT        (4)
+    #define PHY_REG_AN_LINK_PARTNER         (5)
+    #define PHY_REG_AN_EXPANSION            (6)
+
+/* Vendor Specific PHY Registers */
+#ifdef ETHER_CFG_USE_PHY_KSZ8041NL
+    #define PHY_REG_PHY_CONTROL_1           (0x1E)
+#endif /* MICREL_KSZ8041NL */
+
+/* Basic Mode Control Register Bit Definitions */
+    #define PHY_CONTROL_RESET               (1 << 15)
+    #define PHY_CONTROL_LOOPBACK            (1 << 14)
+    #define PHY_CONTROL_100_MBPS            (1 << 13)
+    #define PHY_CONTROL_AN_ENABLE           (1 << 12)
+    #define PHY_CONTROL_POWER_DOWN          (1 << 11)
+    #define PHY_CONTROL_ISOLATE             (1 << 10)
+    #define PHY_CONTROL_AN_RESTART          (1 << 9)
+    #define PHY_CONTROL_FULL_DUPLEX         (1 << 8)
+    #define PHY_CONTROL_COLLISION           (1 << 7)
+
+/* Basic Mode Status Register Bit Definitions */
+    #define PHY_STATUS_100_T4               (1 << 15)
+    #define PHY_STATUS_100F                 (1 << 14)
+    #define PHY_STATUS_100H                 (1 << 13)
+    #define PHY_STATUS_10F                  (1 << 12)
+    #define PHY_STATUS_10H                  (1 << 11)
+    #define PHY_STATUS_AN_COMPLETE          (1 << 5)
+    #define PHY_STATUS_RM_FAULT             (1 << 4)
+    #define PHY_STATUS_AN_ABILITY           (1 << 3)
+    #define PHY_STATUS_LINK_UP              (1 << 2)
+    #define PHY_STATUS_JABBER               (1 << 1)
+    #define PHY_STATUS_EX_CAPABILITY        (1 << 0)
+
+/* Auto Negotiation Advertisement Bit Definitions */
+    #define PHY_AN_ADVERTISEMENT_NEXT_PAGE  (1 << 15)
+    #define PHY_AN_ADVERTISEMENT_RM_FAULT   (1 << 13)
+    #define PHY_AN_ADVERTISEMENT_ASM_DIR    (1 << 11)
+    #define PHY_AN_ADVERTISEMENT_PAUSE      (1 << 10)
+    #define PHY_AN_ADVERTISEMENT_100_T4     (1 << 9)
+    #define PHY_AN_ADVERTISEMENT_100F       (1 << 8)
+    #define PHY_AN_ADVERTISEMENT_100H       (1 << 7)
+    #define PHY_AN_ADVERTISEMENT_10F        (1 << 6)
+    #define PHY_AN_ADVERTISEMENT_10H        (1 << 5)
+    #define PHY_AN_ADVERTISEMENT_SELECTOR   (1 << 0)
+
+/* Auto Negotiate Link Partner Ability Bit Definitions */
+    #define PHY_AN_LINK_PARTNER_NEXT_PAGE   (1 << 15)
+    #define PHY_AN_LINK_PARTNER_ACK         (1 << 14)
+    #define PHY_AN_LINK_PARTNER_RM_FAULT    (1 << 13)
+    #define PHY_AN_LINK_PARTNER_ASM_DIR     (1 << 11)
+    #define PHY_AN_LINK_PARTNER_PAUSE       (1 << 10)
+    #define PHY_AN_LINK_PARTNER_100_T4      (1 << 9)
+    #define PHY_AN_LINK_PARTNER_100F        (1 << 8)
+    #define PHY_AN_LINK_PARTNER_100H        (1 << 7)
+    #define PHY_AN_LINK_PARTNER_10F         (1 << 6)
+    #define PHY_AN_LINK_PARTNER_10H         (1 << 5)
+    #define PHY_AN_LINK_PARTNER_SELECTOR    (1 << 0)
+
+    #define PMGI_READ                       (0)
+    #define PMGI_WRITE                      (1)
+    #define PMGI_START                      (1)
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+typedef enum LinkStatE
+{
+    PHY_NO_LINK = 0, PHY_LINK_10H, PHY_LINK_10F, PHY_LINK_100H, PHY_LINK_100F
+} linkstat_t;
+
+/***********************************************************************************************************************
+ Exported global variables
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+ #if (ETHER_CFG_NON_BLOCKING == 0)
+int16_t phy_init (uint32_t channel);
+void phy_start_autonegotiate (uint32_t channel, uint8_t pause);
+int16_t phy_set_autonegotiate (uint32_t channel, uint16_t *pline_speed_duplex, uint16_t *plocal_pause,
+        uint16_t *ppartner_pause);
+int16_t phy_get_link_status (uint32_t channel);
+uint16_t phy_read (uint32_t ether_channel, uint16_t reg_addr);
+void phy_write (uint32_t ether_channel, uint16_t reg_addr, uint16_t data);
+#elif (ETHER_CFG_NON_BLOCKING == 1)
+int16_t pmgi_initial(uint16_t pmgi_channel);
+uint16_t pmgi_read_reg(uint16_t pmgi_channel);
+int16_t pmgi_close(uint16_t pmgi_channel);
+int16_t pmgi_access(uint32_t channel, uint16_t address, uint16_t data, uint16_t dir);
+#endif
+#endif /* PHY_H */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/r_ether_rx.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/r_ether_rx.c
new file mode 100644
index 00000000..6032195a
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/r_ether_rx.c
@@ -0,0 +1,4854 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+ * applicable laws, including copyright laws. 
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+ * following link:
+ * http://www.renesas.com/disclaimer 
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.    
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name    : r_ether_rx.c
+ * Version      : 1.20
+ * Description  : Ethernet module device driver
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 22.07.2014 1.00     First Release
+ *         : 16.12.2014 1.01     Made changes related to header file include.
+ *         : 27.03.2015 1.02     Changed the R_ETHER_LinkProcess() Function
+ *         : 31.03.2016 1.10     Added changes for MCU which have single channel Ethernet controller.
+ *         : 01.10.2016 1.11     Added changes for RX65N.
+ *         : 11.11.2016 1.12     The module is updated to fix the software issue.
+ *                               When R_ETHER_LinkProcess function is called, 
+ *                               there are cases when link up/link down are not processed successfully.
+ *                                 The issue occurs when ETHER_CFG_USE_LINKSTA is set to a value of 0.
+ *                               Corrected source code of the R_ETHER_Close_ZC2 function.
+ *                               Corrected source code of the R_ETHER_LinkProcess function.
+ *         : 01.10.2017 1.13     Removed ether_clear_icu_source function in R_ETHER_Close_ZC2 function.
+ *         : 07.05.2018 1.14     The module is updated to fix the software issues.
+ *                               (1) When R_ETHER_Read_ZC2 function or R_ETHER_Read function is called,
+ *                               there is case when the Ethernet frame cannot be received normally.
+ *                                 The issue occurs when R_ETHER_Read_ZC2 function or R_ETHER_Read function
+ *                                 is called in the interrupt function.
+ *                               Corrected source code of the R_ETHER_LinkProcess function.
+ *                               (2) When R_ETHER_LinkProcess function is called,
+ *                               there is case when link up processing is not completed normally.
+ *                                 The issue occurs When R_ETHER_LinkProcess function is called,
+ *                                 PHY auto-negotiation is not completed.
+ *                               Corrected source code of the R_ETHER_LinkProcess function.
+ *                               (3) When R_ETHER_Read_ZC2 function or R_ETHER_Read function is called,
+ *                               there is case when execution of function is not completed.
+ *                                 The issue occurs when R_ETHER_LinkProcess function is called
+ *                                 in the interrupt function.
+ *                               Corrected source code of the R_ETHER_Read_ZC2 function.
+ *         : 20.05.2019 1.16     Added support for GNUC and ICCRX.
+ *                               Fixed coding style.
+ *         : 30.07.2019 1.17     Added WAIT LOOP.
+ *                               Added changes for RX72M.
+ *                               The module is updated to fix the software issue.
+ *                               When R_ETHER_Read_ZC2_BufRelease function and R_ETHER_Read function are executed,
+ *                               data is received when the reception descriptor (RAM) operated by EDMAC and the 
+ *                               reception descriptor (RAM) operated by Ether FIT module are the same. There may occur  
+ *                               two phenomena:
+ *                               (1) Data loss for one frame of received data may occur.
+ *                               (2) Also, even if no data loss occurs, if an error frame is received, it may be 
+ *                                   erroneously recognized as a normal frame.
+ *         : 22.11.2019 1.20     The module is updated to solve the following problem.
+ *                               (1) Added changes for RX72N.
+ *                               (2) Added changes for RX66N.
+ *                               (3) Changed R_ETHER_Initial, R_ETHER_Open_ZC2, R_ETHER_Close_ZC2, R_ETHER_CheckLink_ZC,
+ *                                   R_ETHER_LinkProcess, R_ETHER_WakeOnLAN, R_ETHER_Control for NON-BLOCKING.
+ *                               (4) Added ether_set_pmgi_callback, get_pmgi_channel, pmgi_open_zc2_step0,  
+ *                                   pmgi_open_zc2_step1, pmgi_open_zc2_step2, pmgi_open_zc2_step3, pmgi_open_zc2_step4, 
+ *                                   pmgi_open_zc2_step5, pmgi_open_zc2_step6, pmgi_checklink_zc_step0,
+ *                                   pmgi_checklink_zc_step1, pmgi_linkprocess_step0,pmgi_linkprocess_step1, 
+ *                                   pmgi_linkprocess_step2, pmgi_wakeonlan_step0, pmgi_wakeonlan_step1,
+ *                                   pmgi_wakeonlan_step2, pmgi_writephy_step0, pmgi_readphy_step0, pmgi_modestep_invalid, 
+ *                                   R_ETHER_WritePHY, R_ETHER_ReadPHY, ether_pmgi0i_isr, ether_pmgi1i_isr, set_ether_channel
+ *                                   for NON-BLOCKING.
+ *                               (5) Added PmgiAccessFun_tbl for NON-BLOCKING.
+ *                               (6) Added local_advertise, g_local_pause_bits, g_phy_current_param for NON-BLOCKING.
+ *                               (7) Changed R_ETHER_Initial, R_ETHER_Control, ether_config_ethernet for insert padding 
+ *                                   into received data.
+ *                               (8) Added ether_receive_data_padding for insert padding into received data.
+ *                               (9) Added padding_insert_position and padding_insert_size for insert padding into 
+ *                                   received data.
+ *                               (10) Added support for atomic control.  
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+#include <string.h>
+
+/* Access to peripherals and board defines. */
+#include "platform.h"
+
+#include "r_ether_rx_if.h"
+#include "src/r_ether_rx_private.h"
+
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Exported global variables (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ Private global variables and functions
+ ***********************************************************************************************************************/
+#if (ETHER_CFG_NON_BLOCKING == 1)
+static uint16_t local_advertise[ETHER_CHANNEL_MAX]; /* the capabilities of the local link as PHY data */
+static uint16_t g_local_pause_bits[ETHER_CHANNEL_MAX];
+static pmgi_param_t g_phy_current_param[PMGI_CHANNEL_MAX];
+#endif
+
+static uint8_t padding_insert_position [ETHER_CHANNEL_MAX];
+static uint8_t padding_insert_size [ETHER_CHANNEL_MAX];
+
+/*
+ * Private global function prototypes
+ */
+static void ether_reset_mac (uint32_t channel);
+static void ether_init_descriptors (uint32_t channel);
+static void ether_config_ethernet (uint32_t channel, const uint8_t mode);
+static void ether_pause_resolution (uint16_t local_ability, uint16_t partner_ability, uint16_t *ptx_pause,
+        uint16_t *prx_pause);
+static void ether_configure_mac (uint32_t channel, const uint8_t mac_addr[], const uint8_t mode);
+#if (ETHER_CFG_NON_BLOCKING == 0)
+static ether_return_t ether_do_link (uint32_t channel, const uint8_t mode);
+#endif
+static ether_return_t ether_set_callback (ether_param_t const control);
+static ether_return_t ether_set_promiscuous_mode (ether_param_t const control);
+static ether_return_t ether_set_int_handler (ether_param_t const control);
+static ether_return_t ether_power_on (ether_param_t const control);
+static ether_return_t ether_power_off (ether_param_t const control);
+static ether_return_t power_on (uint32_t channel);
+static void power_off (uint32_t channel);
+static ether_return_t ether_set_multicastframe_filter (ether_param_t const control);
+static ether_return_t ether_set_broadcastframe_filter (ether_param_t const control);
+static ether_return_t ether_receive_data_padding (ether_param_t const control);
+
+#if (defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX72M) || \
+     defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N))
+static void ether_eint0 (void * pparam);
+#endif
+#if (defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N))
+static void ether_eint1(void * pparam);
+#endif
+
+static void ether_int_common (uint32_t channel);
+static ether_return_t power_on_control (uint32_t channel);
+static void power_off_control (uint32_t channel);
+static uint8_t check_mpde_bit (void);
+
+#if (ETHER_CFG_NON_BLOCKING == 1)
+static ether_return_t ether_set_pmgi_callback(ether_param_t const control);
+static uint16_t get_pmgi_channel(uint32_t channel);
+static void set_ether_channel(uint32_t channel);
+static ether_return_t pmgi_open_zc2_step0(uint32_t ether_channel);
+static ether_return_t pmgi_open_zc2_step1(uint32_t ether_channel);
+static ether_return_t pmgi_open_zc2_step2(uint32_t ether_channel);
+static ether_return_t pmgi_open_zc2_step3(uint32_t ether_channel);
+static ether_return_t pmgi_open_zc2_step4(uint32_t ether_channel);
+static ether_return_t pmgi_open_zc2_step5(uint32_t ether_channel);
+static ether_return_t pmgi_open_zc2_step6(uint32_t ether_channel);
+static ether_return_t pmgi_checklink_zc_step0(uint32_t ether_channel);
+static ether_return_t pmgi_checklink_zc_step1(uint32_t ether_channel);
+static ether_return_t pmgi_linkprocess_step0(uint32_t ether_channel);
+static ether_return_t pmgi_linkprocess_step1(uint32_t ether_channel);
+static ether_return_t pmgi_linkprocess_step2(uint32_t ether_channel);
+static ether_return_t pmgi_wakeonlan_step0(uint32_t ether_channel);
+static ether_return_t pmgi_wakeonlan_step1(uint32_t ether_channel);
+static ether_return_t pmgi_wakeonlan_step2(uint32_t ether_channel);
+static ether_return_t pmgi_writephy_step0(uint32_t ether_channel);
+static ether_return_t pmgi_readphy_step0(uint32_t ether_channel);
+static ether_return_t pmgi_modestep_invalid(uint32_t ether_channel);
+static const st_pmgi_interrupt_func_t PmgiAccessFun_tbl[PMGI_MODE_NUM][PMGI_STEP_NUM] =
+{
+    {
+        { pmgi_open_zc2_step0 },
+        { pmgi_open_zc2_step1 },
+        { pmgi_open_zc2_step2 },
+        { pmgi_open_zc2_step3 },
+        { pmgi_open_zc2_step4 },
+        { pmgi_open_zc2_step5 },
+        { pmgi_open_zc2_step6 },
+    },
+    {
+        { pmgi_checklink_zc_step0 },
+        { pmgi_checklink_zc_step1 },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+    },
+    {
+        { pmgi_linkprocess_step0 },
+        { pmgi_linkprocess_step1 },
+        { pmgi_linkprocess_step2 },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+    },
+    {
+        { pmgi_wakeonlan_step0 },
+        { pmgi_wakeonlan_step1 },
+        { pmgi_wakeonlan_step2 },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+    },
+    {
+        { pmgi_open_zc2_step0 },
+        { pmgi_open_zc2_step1 },
+        { pmgi_open_zc2_step2 },
+        { pmgi_open_zc2_step3 },
+        { pmgi_open_zc2_step4 },
+        { pmgi_open_zc2_step5 },
+        { pmgi_open_zc2_step6 },
+    },
+    {
+        { pmgi_checklink_zc_step0 },
+        { pmgi_checklink_zc_step1 },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+    },
+    {
+        { pmgi_checklink_zc_step0 },
+        { pmgi_checklink_zc_step1 },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+    },
+    {
+        { pmgi_checklink_zc_step0 },
+        { pmgi_checklink_zc_step1 },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+    },
+    {
+        { pmgi_checklink_zc_step0 },
+        { pmgi_checklink_zc_step1 },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+    },
+    {
+        { pmgi_writephy_step0 },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+    },
+    {
+        { pmgi_readphy_step0 },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+        { pmgi_modestep_invalid },
+    },
+};
+#endif /* (ETHER_CFG_NON_BLOCKING == 1) */
+/*
+ * Private global variables
+ */
+
+/* Pointer to the receive descriptors */
+#if (ETHER_CHANNEL_MAX == 1)
+static descriptor_t * papp_rx_desc[ETHER_CHANNEL_MAX] =
+{ NULL };
+#elif (ETHER_CHANNEL_MAX == 2)
+static descriptor_t * papp_rx_desc[ETHER_CHANNEL_MAX] =
+{   NULL, NULL};
+#endif
+
+/* Pointer to the transmit descriptors */
+#if (ETHER_CHANNEL_MAX == 1)
+static descriptor_t * papp_tx_desc[ETHER_CHANNEL_MAX] =
+{ NULL };
+#elif (ETHER_CHANNEL_MAX == 2)
+static descriptor_t * papp_tx_desc[ETHER_CHANNEL_MAX] =
+{   NULL, NULL};
+#endif
+
+/* Pointer to the callback function */
+static ether_cb_t cb_func;
+
+static bool is_entry = false;
+
+/* 
+ * The flag which control the pause frame.
+ *
+ * The value of flag and the situation which is indicatived of by the value.
+ * ETHER_FLAG_OFF (0): Don't use the pause frame (default). 
+ * ETHER_FLAG_ON  (1): Use the pause frame. 
+ */
+#if (ETHER_CHANNEL_MAX == 1)
+static uint8_t pause_frame_enable[ETHER_CHANNEL_MAX] =
+{ ETHER_FLAG_OFF };
+#elif (ETHER_CHANNEL_MAX == 2)
+static uint8_t pause_frame_enable[ETHER_CHANNEL_MAX] =
+{   ETHER_FLAG_OFF, ETHER_FLAG_OFF};
+#endif
+
+/*
+ * The flag indicatives of the state that the interrupt of Link Up/Down occur.
+ * 
+ * Value and state of flag
+ * ETHER_FLAG_OFF (0): It is not possible to communicate. 
+ * ETHER_FLAG_ON  (1): It is possible to communicate. 
+ */
+static uint8_t transfer_enable_flag[ETHER_CHANNEL_MAX];
+
+/*
+ * The flag indicatives of the state that the interrupt of magic packet detection occur.
+ *
+ * Value and state of flag
+ * ETHER_FLAG_OFF (0): The interrupt of the magic packet detection has not been generated. 
+ * ETHER_FLAG_ON  (1): The interrupt of the magic packet detection was generated. 
+ *
+ * If the R_ETHER_LinkProcess function is called, and the interrupt processing of the magic packet detection is done,
+ * this flag becomes ETHER_FLAG_OFF(0). 
+ */
+static uint8_t mpd_flag[ETHER_CHANNEL_MAX];
+
+static uint8_t mac_addr_buf[ETHER_CHANNEL_MAX][6];
+
+/*
+ * The flag indicatives of the state that the interrupt of Link Up/Down occur.
+ * 
+ * Value and state of flag
+ * ETHER_FLAG_OFF         (0) : The Link up/down interrupt has not been generated. 
+ * ETHER_FLAG_ON_LINK_OFF (2) : The Link down interrupt was generated. 
+ * ETHER_FLAG_ON_LINK_ON  (3) : The Link up interrupt was generated. 
+ * 
+ * If the R_ETHER_LinkProcess function is called, and the interrupt processing of Link Up/Down is done,
+ * this flag becomes ETHER_FLAG_OFF(0). 
+ */
+static uint8_t lchng_flag[ETHER_CHANNEL_MAX];
+
+/*
+ * The flag indicatives of the state that enable/disable multicast frame filtering.
+ *
+ * Value and state of flag
+ * ETHER_MC_FILTER_OFF          (0) : Disable multicast frame filtering.
+ * ETHER_MC_FILTER_ON           (1) : Enable multicast frame filtering.
+ *
+ * The frame multicast filtering is software filter. If you want to use Hardware filter,
+ * please use it EPTPC in RX64M/RX71M/RX72M/RX72N.
+ */
+static uint8_t mc_filter_flag[ETHER_CHANNEL_MAX];
+
+/*
+ * The value indicatives of receive count for continuous broadcast frame.
+ */
+static uint32_t bc_filter_count[ETHER_CHANNEL_MAX];
+
+/*
+ * PAUSE Resolution as documented in IEEE 802.3-2008_section2 Annex
+ * 28B, Table 28B-3. The following table codify logic that
+ * determines how the PAUSE is configured for local transmitter
+ * and receiver and partner transmitter and receiver.
+ */
+static const pauseresolution_t pause_resolution[PAUSE_TABLE_ENTRIES] =
+{
+{ PAUSE_MASKC, PAUSE_VAL0, XMIT_PAUSE_OFF, RECV_PAUSE_OFF },
+{ PAUSE_MASKE, PAUSE_VAL4, XMIT_PAUSE_OFF, RECV_PAUSE_OFF },
+{ PAUSE_MASKF, PAUSE_VAL6, XMIT_PAUSE_OFF, RECV_PAUSE_OFF },
+{ PAUSE_MASKF, PAUSE_VAL7, XMIT_PAUSE_ON, RECV_PAUSE_OFF },
+{ PAUSE_MASKE, PAUSE_VAL8, XMIT_PAUSE_OFF, RECV_PAUSE_OFF },
+{ PAUSE_MASKA, PAUSE_VALA, XMIT_PAUSE_ON, RECV_PAUSE_ON },
+{ PAUSE_MASKF, PAUSE_VALC, XMIT_PAUSE_OFF, RECV_PAUSE_OFF },
+{ PAUSE_MASKF, PAUSE_VALD, XMIT_PAUSE_OFF, RECV_PAUSE_ON } };
+
+/*
+ * Receive, transmit descriptors and their buffer.  They are
+ * defined with section pragma directives to easily locate them
+ * on the memory map.
+ */
+R_BSP_ATTRIB_SECTION_CHANGE(B, _RX_DESC, 1)
+static R_BSP_VOLATILE_EVENACCESS descriptor_t rx_descriptors[ETHER_CHANNEL_MAX][ETHER_CFG_EMAC_RX_DESCRIPTORS];
+R_BSP_ATTRIB_SECTION_CHANGE(B, _TX_DESC, 1)
+static R_BSP_VOLATILE_EVENACCESS descriptor_t tx_descriptors[ETHER_CHANNEL_MAX][ETHER_CFG_EMAC_TX_DESCRIPTORS];
+
+/* 
+ * As for Ethernet buffer, the size of total buffer which are use for transmission and the reception is secured.
+ * The total buffer's size which the value is integrated from  EMAC_NUM_BUFFERS (buffer number) and 
+ * ETHER_CFG_BUFSIZE (the size of one buffer).
+ * The ETHER_CFG_BUFSIZE and EMAC_NUM_BUFFERS are defined by macro in the file "r_ether_private.h".
+ * It is sequentially used from the head of the buffer as a receive buffer or a transmission buffer.
+ */
+R_BSP_ATTRIB_SECTION_CHANGE(B, _ETHERNET_BUFFERS, 1)
+static etherbuffer_t ether_buffers[ETHER_CHANNEL_MAX];
+
+R_BSP_ATTRIB_SECTION_CHANGE_END
+
+static uint8_t promiscuous_mode[ETHER_CHANNEL_MAX];
+
+#if (ETHER_CHANNEL_MAX == 1)
+static const ether_control_t ether_ch_0[] =
+{
+/* Ether = ch0, Phy access = ch0 */
+    {   &ETHERC0, &EDMAC0, (volatile uint32_t R_BSP_EVENACCESS_SFR *)&ETHERC0.PIR.LONG, ETHER_CFG_CH0_PHY_ADDRESS, PORT_CONNECT_ET0 } };
+#elif (ETHER_CHANNEL_MAX == 2)
+static const ether_control_t ether_ch_0[]=
+{
+    /* Ether = ch0, Phy access = ch0 */
+    {   &ETHERC0, &EDMAC0, (volatile uint32_t R_BSP_EVENACCESS_SFR *)&ETHERC0.PIR.LONG, ETHER_CFG_CH0_PHY_ADDRESS, PORT_CONNECT_ET0},
+
+    /* Ether = ch0, Phy access = ch1 */
+    {   &ETHERC0, &EDMAC0, (volatile uint32_t R_BSP_EVENACCESS_SFR *)&ETHERC1.PIR.LONG, ETHER_CFG_CH0_PHY_ADDRESS, PORT_CONNECT_ET0_ET1}
+};
+
+static const ether_control_t ether_ch_1[]=
+{
+    /* Ether = ch1, Phy access = ch0 */
+    {   &ETHERC1, &EDMAC1, (volatile uint32_t R_BSP_EVENACCESS_SFR *)&ETHERC0.PIR.LONG, ETHER_CFG_CH1_PHY_ADDRESS, PORT_CONNECT_ET0_ET1},
+
+    /* Ether = ch1, Phy access = ch1 */
+    {   &ETHERC1, &EDMAC1, (volatile uint32_t R_BSP_EVENACCESS_SFR *)&ETHERC1.PIR.LONG, ETHER_CFG_CH1_PHY_ADDRESS, PORT_CONNECT_ET1}
+};
+#endif
+
+/* This table is used to convert it from the channel number for the communication
+ into the channel number for the PHY register access. */
+
+#if (ETHER_CHANNEL_MAX == 1)
+static const uint32_t ether_phy_access[] =
+{
+ETHER_CFG_CH0_PHY_ACCESS };
+#elif (ETHER_CHANNEL_MAX == 2)
+static const uint32_t ether_phy_access[] =
+{
+    ETHER_CFG_CH0_PHY_ACCESS,
+    ETHER_CFG_CH1_PHY_ACCESS
+};
+#endif
+
+static uint8_t etherc_edmac_power_cont[ETHER_PHY_ACCESS_CHANNEL_MAX][ETHER_CHANNEL_MAX];
+
+#if (ETHER_CHANNEL_MAX == 1)
+const ether_ch_control_t g_eth_control_ch[] =
+{
+{ ether_ch_0, ETHER_CFG_CH0_PHY_ACCESS } };
+#elif (ETHER_CHANNEL_MAX == 2)
+const ether_ch_control_t g_eth_control_ch[] =
+{
+    {   ether_ch_0, ETHER_CFG_CH0_PHY_ACCESS},
+    {   ether_ch_1, ETHER_CFG_CH1_PHY_ACCESS}
+};
+#endif
+
+#if (ETHER_CFG_USE_LINKSTA == 0)
+    #if (ETHER_CHANNEL_MAX == 1)
+    /* Previous link status */
+    static int16_t g_pre_link_stat[ETHER_CHANNEL_MAX] = {ETHER_ERR_OTHER};
+    #elif (ETHER_CHANNEL_MAX == 2)
+    /* Previous link status */
+    static int16_t g_pre_link_stat[ETHER_CHANNEL_MAX] = {ETHER_ERR_OTHER, ETHER_ERR_OTHER};
+    #endif
+#endif
+
+/*
+ * Renesas Ethernet API functions
+ */
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_Initial
+ *****************************************************************************************************************/ /**
+ * @brief     This function makes initial settings to the Ethernet FIT module.
+ * @retval    None.
+ * @details   Initializes the memory to be used in order to start Ethernet communication.
+ * @note      This function must be called before calling the R_ETHER_Open_ZC2() function.
+ */
+void R_ETHER_Initial (void)
+{
+    /* Initialize the transmit and receive descriptor */
+    memset((void *)&rx_descriptors, 0x00, sizeof(rx_descriptors));
+    memset((void *)&tx_descriptors, 0x00, sizeof(tx_descriptors));
+
+    /* Initialize the Ether buffer */
+    memset(&ether_buffers, 0x00, sizeof(ether_buffers));
+
+    memset(etherc_edmac_power_cont, 0x00, sizeof(etherc_edmac_power_cont));
+
+    /* Initialize the callback function pointer */
+    cb_func.pcb_func = NULL;
+
+    /* Initialize the interrupt handler pointer */
+    cb_func.pcb_int_hnd = NULL;
+
+    /* Initialize the PMGI callback function pointer */
+    cb_func.pcb_pmgi_hnd = NULL;
+
+    /* Initialize */
+#if (ETHER_CHANNEL_MAX == 1)
+    promiscuous_mode[ETHER_CHANNEL_0] = ETHER_PROMISCUOUS_OFF;
+    mc_filter_flag[ETHER_CHANNEL_0] = ETHER_MC_FILTER_OFF;
+    bc_filter_count[ETHER_CHANNEL_0] = 0;
+    padding_insert_position [ETHER_CHANNEL_0] = 0;
+    padding_insert_size [ETHER_CHANNEL_0] = 0;
+#elif (ETHER_CHANNEL_MAX == 2)
+    promiscuous_mode[ETHER_CHANNEL_0] = ETHER_PROMISCUOUS_OFF;
+    promiscuous_mode[ETHER_CHANNEL_1] = ETHER_PROMISCUOUS_OFF;
+    mc_filter_flag[ETHER_CHANNEL_0] = ETHER_MC_FILTER_OFF;
+    mc_filter_flag[ETHER_CHANNEL_1] = ETHER_MC_FILTER_OFF;
+    bc_filter_count[ETHER_CHANNEL_0] = 0;
+    bc_filter_count[ETHER_CHANNEL_1] = 0;
+    padding_insert_position [ETHER_CHANNEL_0] = 0;
+    padding_insert_position [ETHER_CHANNEL_1] = 0;
+    padding_insert_size [ETHER_CHANNEL_0] = 0;
+    padding_insert_size [ETHER_CHANNEL_1] = 0;
+#endif
+#if (ETHER_CFG_NON_BLOCKING == 1)
+#if (PMGI_CHANNEL_MAX == 1)
+    g_phy_current_param[PMGI_CHANNEL_0].locked.lock = false;
+    g_phy_current_param[PMGI_CHANNEL_0].event = PMGI_IDLE;
+    g_phy_current_param[PMGI_CHANNEL_0].mode = OPEN_ZC2;
+    g_phy_current_param[PMGI_CHANNEL_0].step = STEP0;
+    g_phy_current_param[PMGI_CHANNEL_0].read_data = 0;
+    g_phy_current_param[PMGI_CHANNEL_0].reset_counter = 0;
+#elif (ETHER_CHANNEL_MAX == 2)
+    g_phy_current_param[PMGI_CHANNEL_0].locked.lock = false;
+    g_phy_current_param[PMGI_CHANNEL_0].event = PMGI_IDLE;
+    g_phy_current_param[PMGI_CHANNEL_0].mode = OPEN_ZC2;
+    g_phy_current_param[PMGI_CHANNEL_0].step = STEP0;
+    g_phy_current_param[PMGI_CHANNEL_0].read_data = 0;
+    g_phy_current_param[PMGI_CHANNEL_0].reset_counter = 0;
+    g_phy_current_param[PMGI_CHANNEL_1].locked.lock = false;
+    g_phy_current_param[PMGI_CHANNEL_1].event = PMGI_IDLE;
+    g_phy_current_param[PMGI_CHANNEL_1].mode = OPEN_ZC2;
+    g_phy_current_param[PMGI_CHANNEL_1].step = STEP0;
+    g_phy_current_param[PMGI_CHANNEL_1].read_data = 0;
+    g_phy_current_param[PMGI_CHANNEL_1].reset_counter = 0;
+#endif
+#endif
+
+} /* End of function R_ETHER_Initial() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_Open_ZC2
+ *****************************************************************************************************************/ /**
+ * @brief     When using the ETHER API, this function is used first.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @param[in] mac_addr
+ *             Specifies the MAC address of ETHERC.
+ * @param[in] pause
+ *             Specifies the value set in bit 10 (Pause) in register 4 (auto-negotiation advertisement)
+ *             of the PHY-LSI. The setting ETHER_FLAG_ON is possible only when the user's PHY-LSI supports
+ *             the pause function. This value is passed to the other PHY-LSI during auto-negotiation.
+ *             Flow control is enabled if the auto-negotiation result indicates that both the local PHY-LSI
+ *             and the other PHY-LSI support the pause function.\n
+ *             Specify ETHER_FLAG_ON to convey that the pause function is supported to the other PHY-LSI
+ *             during auto-negotiation, and specify ETHER_FLAG_OFF if the pause function is not supported
+ *             or will not be used even though it is supported.
+ * @retval    ETHER_SUCCESS
+ *            - Processing completed successfully or the PMGI operation start normally when the non-blocking mode
+ *              is enable.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_INVALID_PTR
+ *            - Value of the pointer is NULL or FIT_NO_PTR.
+ * @retval    ETHER_ERR_INVALID_DATA
+ *            - Value of the argument is out of range.
+ * @retval    ETHER_ERR_OTHER
+ *            - PHY-LSI initialization failed when the non-blocking mode is enabled and PMGI callback function is
+ *              not registered .
+ * @retval    ETHER_ERR_LOCKED
+ *            - When PHY access is in progress when non-blocking mode is enabled .
+ * @details   The R_ETHER_Open_ZC2() function resets the ETHERC, EDMAC and PHY-LSI by software, and starts PHY-LSI
+ *            auto-negotiation to enable the link signal change interrupt.\n
+ *            The MAC address is used to initialize the ETHERC MAC address register.\n
+ *            When non-blocking mode is enabled, the processing result of the function is passed as an argument of
+ *            the PMGI callback function.
+ * @note      Either after the R_ETHER_initial() function is called immediately following a power-on reset,
+ *            or after the R_ETHER_Close_ZC2() function was called, applications should only use the other
+ *            API functions after first calling this function and verifying that the return value is ETHER_SUCCESS.
+ */
+ether_return_t R_ETHER_Open_ZC2 (uint32_t channel, const uint8_t mac_addr[], uint8_t pause)
+{
+    volatile bsp_int_err_t bsp_int_err;
+#if (ETHER_CFG_NON_BLOCKING == 0)
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+    ether_return_t ret;
+    int16_t phy_ret;
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc_adr;
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac_adr;
+#else
+    uint16_t pmgi_channel;
+    pmgi_cb_arg_t pmgi_cb_arg;
+#endif
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+    if ((NULL == mac_addr) || (FIT_NO_PTR == mac_addr))
+    {
+        return ETHER_ERR_INVALID_PTR;
+    }
+    if ((ETHER_FLAG_OFF != pause) && (ETHER_FLAG_ON != pause))
+    {
+        return ETHER_ERR_INVALID_DATA;
+    }
+
+#if (ETHER_CFG_NON_BLOCKING == 1)
+    if (NULL == cb_func.pcb_pmgi_hnd)
+    {
+        return ETHER_ERR_OTHER;
+    }
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    if (false == R_BSP_SoftwareLock((BSP_CFG_USER_LOCKING_TYPE *)&g_phy_current_param[pmgi_channel].locked))
+    {
+        return ETHER_ERR_LOCKED;
+    }
+    set_ether_channel(channel);
+#endif
+#if (ETHER_CFG_NON_BLOCKING == 0)
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+    pedmac_adr = pether_ch[phy_access].pedmac;
+#endif
+
+    /* Initialize the flags */
+    transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+    mpd_flag[channel] = ETHER_FLAG_OFF;
+    lchng_flag[channel] = ETHER_FLAG_OFF;
+
+    pause_frame_enable[channel] = pause;
+
+    mac_addr_buf[channel][0] = mac_addr[0];
+    mac_addr_buf[channel][1] = mac_addr[1];
+    mac_addr_buf[channel][2] = mac_addr[2];
+    mac_addr_buf[channel][3] = mac_addr[3];
+    mac_addr_buf[channel][4] = mac_addr[4];
+    mac_addr_buf[channel][5] = mac_addr[5];
+
+#if (defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N))
+    /* Subscribe to r_bsp an interrupt function */
+    if (false == is_entry)
+    {
+        bsp_int_err = R_BSP_InterruptWrite(BSP_INT_SRC_AL1_EDMAC0_EINT0, ether_eint0); /* EINT0 */
+        bsp_int_err = R_BSP_InterruptWrite(BSP_INT_SRC_AL1_EDMAC1_EINT1, ether_eint1); /* EINT1 */
+        is_entry = true;
+    }
+#elif (defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66N))
+    /* Subscribe to r_bsp an interrupt function */
+    if (false == is_entry)
+    {
+        bsp_int_err = R_BSP_InterruptWrite(BSP_INT_SRC_AL1_EDMAC0_EINT0, ether_eint0); /* EINT0 */
+        is_entry = true;
+    }
+#endif
+
+    /* Software reset */
+    ether_reset_mac(channel);
+
+#if (ETHER_CFG_NON_BLOCKING == 0)
+    /* Software reset the PHY */
+    phy_ret = phy_init(channel);
+    if (R_PHY_OK == phy_ret)
+    {
+        phy_start_autonegotiate(channel, pause_frame_enable[channel]);
+
+        /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */
+        petherc_adr->ECSR.LONG = 0x00000037;
+
+        /* Clear all EDMAC status bits */
+        pedmac_adr->EESR.LONG = 0x47FF0F9F;
+
+#if (ETHER_CFG_USE_LINKSTA == 1)
+        /* Enable interrupts of interest only. */
+        petherc_adr->ECSIPR.BIT.LCHNGIP = 1;
+#endif
+
+        pedmac_adr->EESIPR.BIT.ECIIP = 1;
+
+        /* Set Ethernet interrupt level and enable */
+        ether_enable_icu(channel);
+
+        ret = ETHER_SUCCESS;
+    }
+    else
+    {
+        ret = ETHER_ERR_OTHER;
+    }
+
+    return ret;
+#elif (ETHER_CFG_NON_BLOCKING == 1)
+
+    if (R_PHY_ERROR == pmgi_initial(pmgi_channel))
+    {
+        R_BSP_SoftwareUnlock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[pmgi_channel].locked);
+        if ((NULL != cb_func.pcb_pmgi_hnd) && (FIT_NO_FUNC != cb_func.pcb_pmgi_hnd))
+        {
+            pmgi_cb_arg.channel = channel;
+            pmgi_cb_arg.event = PMGI_ERROR;
+            pmgi_cb_arg.mode = OPEN_ZC2;
+            (*cb_func.pcb_pmgi_hnd)((void *)&pmgi_cb_arg);
+        }
+        return ETHER_ERR_OTHER;
+    }
+
+    g_phy_current_param[pmgi_channel].mode = OPEN_ZC2;
+    g_phy_current_param[pmgi_channel].step = STEP0;
+    g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+    pmgi_access(channel, PHY_REG_CONTROL, PHY_CONTROL_RESET, PMGI_WRITE);
+
+    return ETHER_SUCCESS;
+#endif
+
+} /* End of function R_ETHER_Open_ZC2() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_Close_ZC2
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_Close_ZC2() function disables transmit and receive functionality on the ETHERC.
+ *            This function does not put the ETHERC and EDMAC into the module stop state..
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @retval    ETHER_SUCCESS
+ *            - Processing completed successfully.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @details   The R_ETHER_Close_ZC2() function disables transmit and receive functionality on the ETHERC and
+ *            disables Ethernet interrupts. It does not put the ETHERC and EDMAC into the module stop state.\n
+ *            Execute this function to end the Ethernet communication.
+ * @note      None.
+ */
+ether_return_t R_ETHER_Close_ZC2 (uint32_t channel)
+{
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc_adr;
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+    pedmac_adr = pether_ch[phy_access].pedmac;
+
+    /* Disable Ethernet interrupt. */
+    ether_disable_icu(channel);
+
+    petherc_adr->ECSIPR.BIT.LCHNGIP = 0;
+    pedmac_adr->EESIPR.BIT.ECIIP = 0;
+
+    /* Disable TE and RE  */
+    petherc_adr->ECMR.LONG = 0x00000000;
+
+    /* Initialize the flags */
+    transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+    mpd_flag[channel] = ETHER_FLAG_OFF;
+    lchng_flag[channel] = ETHER_FLAG_OFF;
+#if (ETHER_CFG_USE_LINKSTA == 0)
+    g_pre_link_stat[channel] = ETHER_ERR_OTHER;
+#endif
+
+    return ETHER_SUCCESS;
+} /* End of function R_ETHER_Close_ZC2() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_Read_ZC2
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_Read_ZC2() function returns a pointer to the starting address of the buffer storing the
+ *            receive data.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @param[out] **pbuf
+ *             Returns a pointer to the starting address of the buffer storing the receive data.
+ * @retval    A value of 1 or greater
+ *            - Returns the number of bytes received.
+ * @retval    ETHER_NO_DATA
+ *            - A zero value indicates no data is received.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_INVALID_PTR
+ *            - Value of the pointer is NULL or FIT_NO_PTR.
+ * @retval    ETHER_ERR_LINK
+ *            - Auto-negotiation is not completed, and reception is not enabled.
+ * @retval    ETHER_ERR_MPDE
+ *            - As a Magic Packet is being detected, transmission and reception is not enabled.
+ * @retval    ETHER_ERR_MC_FRAME
+ *            - Multicast frame detected when multicast frame filtering is enabled.
+ * @details   The driver's buffer pointer to the starting address of the buffer storing the receive data
+ *            is returned in the parameter pbuf. Returning the pointer allows the operation to be performed with
+ *            zero-copy. Return value shows the number of received bytes. If there is no data available at the time
+ *            of the call, ETHER_NO_DATA is returned. When auto-negotiation is not completed, and reception is not
+ *            enabled, ETHER_ERR_LINK is returned. ETHER_ERR_MPDE is returned when a Magic Packet is being detected.\n
+ *            The EDMAC hardware operates independent of the R_ETHER_Read_ZC2() function and reads data into a buffer
+ *            pointed by the EDMAC receive descriptor. The buffer pointed by the EDMAC receive descriptor is
+ *            statically allocated by the driver.\n
+ *            When multicast frame filtering on the specified channel is enabled by the R_ETHER_Control function,
+ *            the buffer is released immediately when a multicast frame is detected. Also, the value
+ *            ETHER_ERR_MC_FRAME is returned. Note that when hardware-based multicast frame filtering is enabled
+ *            on the RX64M, RX71M, RX72M, RX72N or RX66N, multicast frames are discarded by the hardware and
+ *            detection is not possible.\n
+ *            Frames that generate a receive FIFO overflow, residual-bit frame receive error, long frame receive
+ *            error, short frame receive error, PHY-LSI receive error, or receive frame CRC error are treated
+ *            as receive frame errors. When a receive frame error occurs, the descriptor data is discarded,
+ *            the status is cleared, and reading of data continues.
+ * @note      This function is used in combination with the R_ETHER_Read_ZC2_BufRelease function.
+ *            Always call the R_ETHER_Read_ZC2 function and then the R_ETHER_Read_ZC2_BufRelease function
+ *            in sequence. If the value ETHER_ERR_LINK is returned when this function is called,
+ *            initialize the Ethernet FIT module.
+ */
+int32_t R_ETHER_Read_ZC2 (uint32_t channel, void **pbuf)
+{
+    int32_t num_recvd;
+    int32_t ret;
+    int32_t complete_flag;
+    int32_t ret2;
+#if (1 == ETHER_CFG_EMAC_RX_DESCRIPTORS)
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+#endif
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+    if ((NULL == pbuf) || (FIT_NO_PTR == pbuf))
+    {
+        return ETHER_ERR_INVALID_PTR;
+    }
+
+    /* When the Link up processing is not completed, return error */
+    if (ETHER_FLAG_OFF == transfer_enable_flag[channel])
+    {
+        ret = ETHER_ERR_LINK;
+    }
+
+    /* In case of detection mode of magic packet, return error. */
+    else if (1 == check_mpde_bit())
+    {
+        ret = ETHER_ERR_MPDE;
+    }
+
+    /* When the Link up processing is completed */
+    else
+    {
+        ret = ETHER_NO_DATA;
+        complete_flag = ETHER_ERR_OTHER;
+#if (1 == ETHER_CFG_EMAC_RX_DESCRIPTORS)
+        pether_ch = g_eth_control_ch[channel].pether_control;
+        phy_access = g_eth_control_ch[channel].phy_access;
+        pedmac_adr = pether_ch[phy_access].pedmac;
+#endif
+        /* WAIT_LOOP */
+        while (ETHER_SUCCESS != complete_flag)
+        {
+#if (1 == ETHER_CFG_EMAC_RX_DESCRIPTORS)
+            /* When receive function enable  */
+            if (0x00000000L == pedmac_adr->EDRRR.LONG)
+#else
+            /* When receive data exists. */
+            if (RACT != (papp_rx_desc[channel]->status & RACT))
+#endif
+            {
+                /* Check multicast is detected when multicast frame filter is enabled */
+                if (ETHER_MC_FILTER_ON == mc_filter_flag[channel])
+                {
+                    if (RFS7_RMAF == (papp_rx_desc[channel]->status & RFS7_RMAF))
+                    {
+                        /* The buffer is released at the multicast frame detect.  */
+                        ret2 = R_ETHER_Read_ZC2_BufRelease(channel);
+                        if (ETHER_SUCCESS != ret2)
+                        {
+                            return ret2;
+                        }
+
+                        ret = ETHER_ERR_MC_FRAME;
+                        complete_flag = ETHER_SUCCESS;
+                    }
+                }
+
+                if (ETHER_ERR_MC_FRAME != ret)
+                {
+                    if (RFE == (papp_rx_desc[channel]->status & RFE))
+                    {
+                        /* The buffer is released at the error.  */
+                        ret2 = R_ETHER_Read_ZC2_BufRelease(channel);
+                        if (ETHER_SUCCESS != ret2)
+                        {
+                            return ret2;
+                        }
+                    }
+                    else
+                    {
+                        /**
+                         * Pass the pointer to received data to application.  This is
+                         * zero-copy operation.
+                         */
+                        (*pbuf) = (void *) papp_rx_desc[channel]->buf_p;
+
+                        /* Get bytes received */
+                        num_recvd = papp_rx_desc[channel]->size;
+                        ret = num_recvd;
+                        complete_flag = ETHER_SUCCESS;
+                    }
+                }
+            }
+            else
+            {
+                ret = ETHER_NO_DATA;
+                complete_flag = ETHER_SUCCESS;
+            }
+        }
+    }
+    return ret;
+} /* End of function R_ETHER_Read_ZC2() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_Read_ZC2_BufRelease
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_Read_ZC2_BufRelease() function releases the buffer read by the R_ETHER_Read_ZC2() function.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @retval    ETHER_SUCCESS
+ *            - Processing completed successfully.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_LINK
+ *            - Auto-negotiation is not completed, and reception is not enabled.
+ * @retval    ETHER_ERR_MPDE
+ *            - As a Magic Packet is being detected, transmission and reception is not enabled.
+ * @details   The R_ETHER_Read_ZC2_BufRelease() function releases the buffer read by the R_ETHER_Read_ZC2() function.
+ * @note      Before calling this function, use the R_ETHER_Read_ZC2 function to read data. Call this function after
+ *            a value of 1 or greater is returned.\n
+ *            This function is used in combination with the R_ETHER_Read_ZC2_BufRelease function.
+ *            Always call the R_ETHER_Read_ZC2 function and then the R_ETHER_Read_ZC2_BufRelease function in sequence.
+ *            If the value ETHER_ERR_LINK is returned when this function is called, initialize the Ethernet FIT module.
+ */
+int32_t R_ETHER_Read_ZC2_BufRelease (uint32_t channel)
+{
+    int32_t ret;
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+    uint32_t status;
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+
+    /* When the Link up processing is not completed, return error */
+    if (ETHER_FLAG_OFF == transfer_enable_flag[channel])
+    {
+        ret = ETHER_ERR_LINK;
+    }
+
+    /* In case of detection mode of magic packet, return error. */
+    else if (1 == check_mpde_bit())
+
+    {
+        ret = ETHER_ERR_MPDE;
+    }
+
+    /* When the Link up processing is completed */
+    else
+    {
+#if (1 == ETHER_CFG_EMAC_RX_DESCRIPTORS)
+        pether_ch = g_eth_control_ch[channel].pether_control;
+        phy_access = g_eth_control_ch[channel].phy_access;
+        pedmac_adr = pether_ch[phy_access].pedmac;
+#endif
+        /* When receive data exists */
+#if (1 == ETHER_CFG_EMAC_RX_DESCRIPTORS)
+        if (0x00000000L == pedmac_adr->EDRRR.LONG)
+#else
+        if (RACT != (papp_rx_desc[channel]->status & RACT))
+#endif
+        {
+            /* Move to next descriptor */
+
+            status = RFP1;
+            status |= RFP0;
+            status |= RFE;
+            status |= RFS9_RFOVER;
+            status |= RFS8_RAD;
+            status |= RFS7_RMAF;
+            status |= RFS4_RRF;
+            status |= RFS3_RTLF;
+            status |= RFS2_RTSF;
+            status |= RFS1_PRE;
+            status |= RFS0_CERF;
+
+            papp_rx_desc[channel]->status &= (~status);
+            papp_rx_desc[channel]->status |= RACT;
+            papp_rx_desc[channel] = papp_rx_desc[channel]->next;
+        }
+        pether_ch = g_eth_control_ch[channel].pether_control;
+        phy_access = g_eth_control_ch[channel].phy_access;
+        pedmac_adr = pether_ch[phy_access].pedmac;
+
+        if (0x00000000L == pedmac_adr->EDRRR.LONG)
+        {
+            /* Restart if stopped */
+            pedmac_adr->EDRRR.LONG = 0x00000001L;
+        }
+
+        ret = ETHER_SUCCESS;
+    }
+    return ret;
+} /* End of function R_ETHER_Read_ZC2_BufRelease() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_Write_ZC2_GetBuf
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_Write_ZC2_GetBuf() function returns a pointer to the starting address of
+ *            the transmit data destination.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @param[out] **pbuf
+ *             Returns a pointer to the starting address of the transmit data destination.
+ * @param[out] *pbuf_size
+ *             Returns the maximum size to write to the buffer.
+ * @retval    ETHER_SUCCESS
+ *            - Processing completed successfully.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_INVALID_PTR
+ *            - Value of the pointer is NULL or FIT_NO_PTR.
+ * @retval    ETHER_ERR_LINK
+ *            - Auto-negotiation is not completed, and reception is not enabled.
+ * @retval    ETHER_ERR_MPDE
+ *            - As a Magic Packet is being detected, transmission and reception is not enabled.
+ * @retval    ETHER_ERR_TACT
+ *            - Transmit buffer is not empty.
+ * @details   The R_ETHER_Write_ZC2_GetBuf() function returns the parameter pbuf containing a pointer to
+ *            the starting address of the transmit data destination. The function also returns the maximum size to
+ *            write to the buffer to the parameter pbuf_size. Returning the pointer allows the operation to
+ *            be performed with zero-copy.\n
+ *            Return values indicate if the transmit buffer (pbuf) is writable or not. ETHER_SUCCESS is returned
+ *            when the buffer is writable at the time of the call. When auto-negotiation is not completed,
+ *            and transmission is not enabled, ETHER_ERR_LINK is returned. ETHER_ERR_MPDE is returned when
+ *            a Magic Packet is being detected. ETHER_ERR_TACT is returned when the transmit buffer is not empty.\n
+ *            The EDMAC hardware operates independent of the R_ETHER_Write_ZC2_GetBuf() function and writes data
+ *            stored in a buffer pointed by the EDMAC transmit descriptor. The buffer pointed by the EDMAC
+ *            transmit descriptor is statically allocated by the driver.
+ * @note      This function is used in combination with the R_ETHER_Write_ZC2_SetBuf function.
+ *            Always call the R_ETHER_Write_ZC2_GetBuf function and then the R_ETHER_Write_ZC2_SetBuf function
+ *            in sequence. If the value ETHER_ERR_LINK is returned when this function is called,
+ *            initialize the Ethernet FIT module.
+ */
+ether_return_t R_ETHER_Write_ZC2_GetBuf (uint32_t channel, void **pbuf, uint16_t *pbuf_size)
+{
+    ether_return_t ret;
+#if (1 == ETHER_CFG_EMAC_TX_DESCRIPTORS)
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+#endif
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+    if ((NULL == pbuf) || (FIT_NO_PTR == pbuf))
+    {
+        return ETHER_ERR_INVALID_PTR;
+    }
+    if ((NULL == pbuf_size) || (FIT_NO_PTR == pbuf_size))
+    {
+        return ETHER_ERR_INVALID_PTR;
+    }
+
+    /* When the Link up processing is not completed, return error */
+    if (ETHER_FLAG_OFF == transfer_enable_flag[channel])
+    {
+        ret = ETHER_ERR_LINK;
+    }
+
+    /* In case of detection mode of magic packet, return error. */
+    else if (1 == check_mpde_bit())
+    {
+        ret = ETHER_ERR_MPDE;
+    }
+
+    /* When the Link up processing is completed */
+    else
+    {
+#if (1 == ETHER_CFG_EMAC_TX_DESCRIPTORS)
+        pether_ch = g_eth_control_ch[channel].pether_control;
+        phy_access = g_eth_control_ch[channel].phy_access;
+        pedmac_adr = pether_ch[phy_access].pedmac;
+#endif
+
+        /* All transmit buffers are full */
+#if (1 == ETHER_CFG_EMAC_TX_DESCRIPTORS)
+        if (0x00000000L != pedmac_adr->EDTRR.LONG)
+#else
+        if (TACT == (papp_tx_desc[channel]->status & TACT))
+#endif
+        {
+            ret = ETHER_ERR_TACT;
+        }
+        else
+        {
+            /* Give application another buffer to work with */
+            (*pbuf) = papp_tx_desc[channel]->buf_p;
+            (*pbuf_size) = ETHER_CFG_BUFSIZE;
+            ret = ETHER_SUCCESS;
+        }
+    }
+    return ret;
+} /* End of function R_ETHER_Write_ZC2_GetBuf() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_Write_ZC2_SetBuf
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_Write_ZC2_SetBuf() function enables the EDMAC to transmit the data in the transmit buffer.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @param[in] len
+ *             Specifies the size (60 to 1,514 bytes) which is the Ethernet frame length minus 4 bytes of CRC.
+ * @retval    ETHER_SUCCESS
+ *            - Processing completed successfully.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_INVALID_PTR
+ *            - Value of the pointer is NULL or FIT_NO_PTR.
+ * @retval    ETHER_ERR_LINK
+ *            - Auto-negotiation is not completed, and reception is not enabled.
+ * @retval    ETHER_ERR_MPDE
+ *            - As a Magic Packet is being detected, transmission and reception is not enabled.
+ * @details   Call this function after writing one frame of transmit data is completed.\n
+ *            Set the buffer length to be not less than 60 bytes (64 bytes of the minimum Ethernet frame minus 4 bytes
+ *            of CRC) and not more than 1,514 bytes (1,518 bytes of the maximum Ethernet frame minus 4 bytes of CRC).\n
+ *            To transmit data less than 60 bytes, make sure to pad the data with zero to be 60 bytes.\n
+ *            Return values indicate that the data written in the transmit buffer is enabled to be transmitted.\n
+ *            ETHER_SUCCESS is returned when the data in the transmit buffer is enabled to be transmitted at the time
+ *            of the call. When auto-negotiation is not completed, and transmission is not enabled,
+ *            ETHER_ERR_LINK is returned. ETHER_ERR_MPDE is returned when a Magic Packet is being detected.
+ * @note      1.Call this function after writing one frame of transmit data is completed.\n
+ *            2.To transmit data less than 60 bytes, make sure to pad the data with zero to be 60 bytes.\n
+ *            3.Before calling this function, use the R_ETHER_Write_ZC2_GetBuf function to read data.
+ *              Call this function after ETHER_SUCCESS is returned.\n
+ *            4.This function is used in combination with the R_ETHER_Write_ZC2_GetBuf function.
+ *              Always call the R_ETHER_Write_ZC2_GetBuf function and then the R_ETHER_Write_ZC2_SetBuf
+ *              function in sequence. If the value ETHER_ERR_LINK is returned when this function is called,
+ *              initialize the Ethernet FIT module.
+ */
+ether_return_t R_ETHER_Write_ZC2_SetBuf (uint32_t channel, const uint32_t len)
+{
+    ether_return_t ret;
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+    if ((ETHER_BUFSIZE_MIN > len) || (ETHER_BUFSIZE_MAX < len))
+    {
+        return ETHER_ERR_INVALID_DATA;
+    }
+
+    /* When the Link up processing is not completed, return error */
+    if (ETHER_FLAG_OFF == transfer_enable_flag[channel])
+    {
+        ret = ETHER_ERR_LINK;
+    }
+
+    /* In case of detection mode of magic packet, return error. */
+    else if (1 == check_mpde_bit())
+
+    {
+        ret = ETHER_ERR_MPDE;
+    }
+
+    /* When the Link up processing is completed */
+    else
+    {
+        /* The data of the buffer is made active.  */
+        papp_tx_desc[channel]->bufsize = len;
+        papp_tx_desc[channel]->status &= (~(TFP1 | TFP0));
+        papp_tx_desc[channel]->status |= ((TFP1 | TFP0) | TACT);
+        papp_tx_desc[channel] = papp_tx_desc[channel]->next;
+
+        pether_ch = g_eth_control_ch[channel].pether_control;
+        phy_access = g_eth_control_ch[channel].phy_access;
+        pedmac_adr = pether_ch[phy_access].pedmac;
+
+        if (0x00000000L == pedmac_adr->EDTRR.LONG)
+        {
+            /* Restart if stopped */
+            pedmac_adr->EDTRR.LONG = 0x00000001L;
+        }
+
+        ret = ETHER_SUCCESS;
+    }
+    return ret;
+} /* End of function R_ETHER_Write_ZC2_SetBuf() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_CheckLink_ZC
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_CheckLink_ZC() function checks the status of the physical Ethernet link
+ *            using PHY management interface. Ethernet link is up when the cable is connected to a peer device
+ *            whose PHY is properly initialized.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @retval    ETHER_SUCCESS
+ *            - the link status is link up or the operation starts normally when the non-blocking mode is enabled.
+ * @retval    ETHER_ERR_OTHER
+ *            - the link status is link-down or the non-blocking mode is enabled and the interrupt handler function
+ *              is not registered
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_LOCKED
+ *            - When PHY access is in progress when non-blocking mode is enabled .
+ * @details   The R_ETHER_CheckLink_ZC() function checks the status of the physical Ethernet link
+ *            using PHY management interface. This information (status of Ethernet link) is read from
+ *            the basic status register (register 1) of the PHY-LSI device. If non-blocking mode is disabled,
+ *            ETHER_SUCCESS is returned when the link is up, and ETHER_ERR_OTHER when the link is down.\n
+ *            When non-blocking mode is enabled, the check result is passed as an argument of
+ *            the interrupt handler function after the link status check is completed.
+ * @note      None.
+ */
+ether_return_t R_ETHER_CheckLink_ZC (uint32_t channel)
+{
+#if (ETHER_CFG_NON_BLOCKING == 0)
+    int16_t status;
+#endif
+#if (ETHER_CFG_NON_BLOCKING == 1)
+    uint16_t pmgi_channel;
+    pmgi_cb_arg_t pmgi_cb_arg;
+    uint16_t reg = 0;
+#endif
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+
+#if (ETHER_CFG_NON_BLOCKING == 1)
+    if (NULL == cb_func.pcb_pmgi_hnd)
+    {
+        return ETHER_ERR_OTHER;
+    }
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    if (false == R_BSP_SoftwareLock((BSP_CFG_USER_LOCKING_TYPE *)&g_phy_current_param[pmgi_channel].locked))
+    {
+         return ETHER_ERR_LOCKED;
+    }
+    set_ether_channel(channel);
+
+    if (R_PHY_ERROR == pmgi_initial(pmgi_channel))
+    {
+        R_BSP_SoftwareUnlock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[pmgi_channel].locked);
+        if ((NULL != cb_func.pcb_pmgi_hnd) && (FIT_NO_FUNC != cb_func.pcb_pmgi_hnd))
+        {
+            pmgi_cb_arg.channel = channel;
+            pmgi_cb_arg.event = PMGI_ERROR;
+            pmgi_cb_arg.mode = CHECKLINK_ZC;
+            (*cb_func.pcb_pmgi_hnd)((void *)&pmgi_cb_arg);
+        }
+        return ETHER_ERR_OTHER;
+    }
+
+    g_phy_current_param[pmgi_channel].mode = CHECKLINK_ZC;
+
+    g_phy_current_param[pmgi_channel].step = STEP0;
+    g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+    pmgi_access(channel, PHY_REG_STATUS, reg, PMGI_READ);
+
+    return ETHER_SUCCESS;
+#elif ETHER_CFG_NON_BLOCKING == 0
+    status = phy_get_link_status(channel);
+
+    if (R_PHY_ERROR == status)
+    {
+        /* Link is down */
+        return ETHER_ERR_OTHER;
+    }
+    else
+    {
+        /* Link is up */
+        return ETHER_SUCCESS;
+    }
+#endif
+
+} /* End of function R_ETHER_CheckLink_ZC() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_LinkProcess
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_LinkProcess() function performs link signal change interrupt processing and
+ *            Magic Packet detection interrupt processing.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @retval    None.
+ * @details   Note that link status change detection processing takes place but link signal change interrupt
+ *            processing does not occur when ETHER_CFG_USE_LINKSTA is set to a value of 0.
+ *            When non-blocking mode is enabled, the processing result of the function is passed as an argument of
+ *            the PMGI callback function.
+ *            See Section 3.9 in the application note for more details.
+ * @note      1.If ETHER_CFG_USE_LINKSTA is set to a value of 1, either call this function periodically within the
+ *              normal processing routine. Note that Ethernet transmission and reception may not operate correctly,
+ *              and the Ethernet driver may not enter Magic Packet detection mode correctly, if this function
+ *              is not called.
+ *            2.If ETHER_CFG_USE_LINKSTA is set to a value of 0, either call this function periodically within the
+ *              normal processing routine, or call it from an interrupt function that is processed when a periodically
+ *              occurring interrupt source occurs. Note that Ethernet transmission and reception may
+ *              not operate correctly, and the Ethernet driver may not enter Magic Packet detection mode correctly,
+ *              if this function is not called.
+ *            3.If no callback function was registered with the function R_ETHER_Control(),
+ *              there will be no notification by a callback function.
+ */
+void R_ETHER_LinkProcess (uint32_t channel)
+{
+
+#if (ETHER_CFG_NON_BLOCKING == 0)
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+    int32_t ret;
+#endif
+
+#if (ETHER_CFG_NON_BLOCKING == 1)
+    volatile bsp_int_err_t bsp_int_err;
+    uint16_t pmgi_channel;
+    pmgi_cb_arg_t pmgi_cb_arg;
+    uint16_t reg_data = 0;
+#endif
+    ether_cb_arg_t cb_arg;
+
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return;
+    }
+#if (ETHER_CFG_NON_BLOCKING == 1)
+
+    if (NULL == cb_func.pcb_pmgi_hnd)
+    {
+        return;
+    }
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    if (false == R_BSP_SoftwareLock((BSP_CFG_USER_LOCKING_TYPE *)&g_phy_current_param[pmgi_channel].locked))
+    {
+        R_BSP_NOP();
+        return;
+    }
+
+    set_ether_channel(channel);
+
+    if (R_PHY_ERROR == pmgi_initial(pmgi_channel))
+    {
+        R_BSP_SoftwareUnlock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[pmgi_channel].locked);
+        if ((NULL != cb_func.pcb_pmgi_hnd) && (FIT_NO_FUNC != cb_func.pcb_pmgi_hnd))
+        {
+            pmgi_cb_arg.channel = channel;
+            pmgi_cb_arg.event = PMGI_ERROR;
+            pmgi_cb_arg.mode = LINKPROCESS;
+            (*cb_func.pcb_pmgi_hnd)((void *)&pmgi_cb_arg);
+        }
+        return;
+    }
+#endif
+
+    /* When the magic packet is detected. */
+    if (ETHER_FLAG_ON == mpd_flag[channel])
+    {
+        mpd_flag[channel] = ETHER_FLAG_OFF;
+
+        if ((NULL != cb_func.pcb_func) && (FIT_NO_FUNC != cb_func.pcb_func))
+        {
+            cb_arg.channel = channel;
+            cb_arg.event_id = ETHER_CB_EVENT_ID_WAKEON_LAN;
+            (*cb_func.pcb_func)((void *) &cb_arg);
+        }
+
+        /*
+         * After the close function is called, the open function is called 
+         * to have to set ETHERC to a usual operational mode
+         * to usually communicate after magic packet is detected. 
+         */
+        R_ETHER_Close_ZC2(channel);
+#if (ETHER_CFG_NON_BLOCKING == 1)
+
+        /* Initialize the flags */
+        transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+        mpd_flag[channel] = ETHER_FLAG_OFF;
+        lchng_flag[channel] = ETHER_FLAG_OFF;
+
+    #if (defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N))
+        /* Subscribe to r_bsp an interrupt function */
+        if (false == is_entry)
+        {
+            bsp_int_err = R_BSP_InterruptWrite(BSP_INT_SRC_AL1_EDMAC0_EINT0, ether_eint0); /* EINT0 */
+            bsp_int_err = R_BSP_InterruptWrite(BSP_INT_SRC_AL1_EDMAC1_EINT1, ether_eint1); /* EINT1 */
+            is_entry = true;
+        }
+    #elif (defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66N))
+        /* Subscribe to r_bsp an interrupt function */
+        if (false == is_entry)
+        {
+            bsp_int_err = R_BSP_InterruptWrite(BSP_INT_SRC_AL1_EDMAC0_EINT0, ether_eint0); /* EINT0 */
+            is_entry = true;
+        }
+    #endif
+
+        /* Software reset */
+        ether_reset_mac(channel);
+
+        g_phy_current_param[pmgi_channel].mode = LINKPROCESS_OPEN_ZC2;
+        g_phy_current_param[pmgi_channel].step = STEP0;
+
+        g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+        pmgi_access(channel, PHY_REG_CONTROL, PHY_CONTROL_RESET, PMGI_WRITE);
+        return;
+
+#elif (ETHER_CFG_NON_BLOCKING == 0)
+        R_ETHER_Open_ZC2(channel, mac_addr_buf[channel], pause_frame_enable[channel]);
+#endif
+    }
+
+#if (ETHER_CFG_USE_LINKSTA == 0)
+    #if (ETHER_CFG_NON_BLOCKING == 1)
+        g_phy_current_param[pmgi_channel].mode = LINKPROCESS_CHECKLINK_ZC0;
+        g_phy_current_param[pmgi_channel].step = STEP0;
+
+        pmgi_access(channel, PHY_REG_STATUS, reg_data, PMGI_READ);
+        return ;
+
+    #elif (ETHER_CFG_NON_BLOCKING == 0)
+        ret = R_ETHER_CheckLink_ZC(channel);
+        if (g_pre_link_stat[channel] != ret)
+        {
+            if (ret == ETHER_SUCCESS)
+            {
+                /* The state of the link status in PHY-LSI is confirmed and Link Up/Down is judged. */
+                /* When becoming Link up */
+                lchng_flag[channel] = ETHER_FLAG_ON_LINK_ON;
+            }
+            else
+            {
+                /* When becoming Link down */
+                lchng_flag[channel] = ETHER_FLAG_ON_LINK_OFF;
+            }
+        }
+        g_pre_link_stat[channel] = ret;
+    #endif
+#endif
+
+    /* When the link is up */
+    if (ETHER_FLAG_ON_LINK_ON == lchng_flag[channel])
+    {
+#if (ETHER_CFG_USE_LINKSTA == 1)
+        /* 
+         * The Link Up/Down is confirmed by the Link Status bit of PHY register1, 
+         * because the LINK signal of PHY-LSI is used for LED indicator, and 
+         * isn't used for notifing the Link Up/Down to external device.
+         */
+    #if (ETHER_CFG_NON_BLOCKING == 1)
+        g_phy_current_param[pmgi_channel].mode = LINKPROCESS_CHECKLINK_ZC1;
+        g_phy_current_param[pmgi_channel].step = STEP0;
+
+        pmgi_access(channel, PHY_REG_STATUS, reg_data, PMGI_READ);
+        return ;
+    #elif (ETHER_CFG_NON_BLOCKING == 0)
+        ret = R_ETHER_CheckLink_ZC(channel);
+        if (ETHER_SUCCESS == ret)
+        {
+            /*
+             * The status of the LINK signal became "link-up" even if PHY-LSI did not detect "link-up"
+             * after a reset. To avoid this wrong detection, processing in R_ETHER_LinkProcess has been modified to
+             * clear the flag after link-up is confirmed in R_ETHER_CheckLink_ZC.
+             */
+            lchng_flag[channel] = ETHER_FLAG_OFF;
+
+            /* Initialize the transmit and receive descriptor */
+            memset((void *)&rx_descriptors[channel], 0x00, sizeof(rx_descriptors[channel]));
+            memset((void *)&tx_descriptors[channel], 0x00, sizeof(tx_descriptors[channel]));
+
+            /* Initialize the Ether buffer */
+            memset(&ether_buffers[channel], 0x00, sizeof(ether_buffers[channel]));
+
+            transfer_enable_flag[channel] = ETHER_FLAG_ON;
+            
+            /*
+             * ETHERC and EDMAC are set after ETHERC and EDMAC are reset in software
+             * and sending and receiving is permitted. 
+             */
+            ether_configure_mac(channel, mac_addr_buf[channel], NO_USE_MAGIC_PACKET_DETECT);
+            ret = ether_do_link(channel, NO_USE_MAGIC_PACKET_DETECT);
+            if (ETHER_SUCCESS == ret)
+            {
+                if ((NULL != cb_func.pcb_func) && (FIT_NO_FUNC != cb_func.pcb_func))
+                {
+                    cb_arg.channel = channel;
+                    cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_ON;
+                    (*cb_func.pcb_func)((void *) &cb_arg);
+                }
+            }
+            else
+            {
+                /* When PHY auto-negotiation is not completed */
+                transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+                lchng_flag[channel] = ETHER_FLAG_ON_LINK_ON;
+            }
+        }
+        else
+        {
+            /* no process */
+        }
+    #endif /* (ETHER_CFG_NON_BLOCKING == 1) */
+#elif ((ETHER_CFG_USE_LINKSTA == 0) && (ETHER_CFG_NON_BLOCKING == 0))
+       /*
+        * The status of the LINK signal became "link-up" even if PHY-LSI did not detect "link-up"
+        * after a reset. To avoid this wrong detection, processing in R_ETHER_LinkProcess has been modified to
+        * clear the flag after link-up is confirmed in R_ETHER_CheckLink_ZC.
+        */
+        lchng_flag[channel] = ETHER_FLAG_OFF;
+
+        /* Initialize the transmit and receive descriptor */
+        memset((void *)&rx_descriptors[channel], 0x00, sizeof(rx_descriptors[channel]));
+        memset((void *)&tx_descriptors[channel], 0x00, sizeof(tx_descriptors[channel]));
+
+        /* Initialize the Ether buffer */
+        memset(&ether_buffers[channel], 0x00, sizeof(ether_buffers[channel]));
+
+        transfer_enable_flag[channel] = ETHER_FLAG_ON;
+       
+       /*
+        * ETHERC and EDMAC are set after ETHERC and EDMAC are reset in software
+        * and sending and receiving is permitted. 
+        */
+        ether_configure_mac(channel, mac_addr_buf[channel], NO_USE_MAGIC_PACKET_DETECT);
+        ret = ether_do_link(channel, NO_USE_MAGIC_PACKET_DETECT);
+        if (ETHER_SUCCESS == ret)
+        {
+            if ((NULL != cb_func.pcb_func) && (FIT_NO_FUNC != cb_func.pcb_func))
+            {
+                cb_arg.channel = channel;
+                cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_ON;
+                (*cb_func.pcb_func)((void *) &cb_arg);
+            }
+        }
+        else
+        {
+            /* When PHY auto-negotiation is not completed */
+            transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+            lchng_flag[channel] = ETHER_FLAG_ON_LINK_ON;
+        }
+#endif /* (ETHER_CFG_USE_LINKSTA == 1) */
+    }
+
+    /* When the link is down */
+    else if (ETHER_FLAG_ON_LINK_OFF == lchng_flag[channel])
+    {
+        lchng_flag[channel] = ETHER_FLAG_OFF;
+
+#if (ETHER_CFG_USE_LINKSTA == 1)
+        /* 
+         * The Link Up/Down is confirmed by the Link Status bit of PHY register1, 
+         * because the LINK signal of PHY-LSI is used for LED indicator, and 
+         * isn't used for notifying the Link Up/Down to external device.
+         */
+    #if (ETHER_CFG_NON_BLOCKING == 1)
+        g_phy_current_param[pmgi_channel].mode = LINKPROCESS_CHECKLINK_ZC2;
+        g_phy_current_param[pmgi_channel].step = STEP0;
+
+        pmgi_access(channel, PHY_REG_STATUS, reg_data, PMGI_READ);
+        return ;
+    #elif (ETHER_CFG_NON_BLOCKING == 0)
+        ret = R_ETHER_CheckLink_ZC(channel);
+        if (ETHER_ERR_OTHER == ret)
+        {
+            pether_ch = g_eth_control_ch[channel].pether_control;
+            phy_access = g_eth_control_ch[channel].phy_access;
+            petherc_adr = pether_ch[phy_access].petherc;
+
+            /* Disable receive and transmit. */
+            petherc_adr->ECMR.BIT.RE = 0;
+            petherc_adr->ECMR.BIT.TE = 0;
+
+            transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+
+            if ((NULL != cb_func.pcb_func) && (FIT_NO_FUNC != cb_func.pcb_func))
+            {
+                cb_arg.channel = channel;
+                cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_OFF;
+                (*cb_func.pcb_func)((void *) &cb_arg);
+            }
+        }
+        else
+        {
+            ; /* no operation */
+        }
+    #endif
+#elif ((ETHER_CFG_USE_LINKSTA == 0) && (ETHER_CFG_NON_BLOCKING == 0))
+        pether_ch = g_eth_control_ch[channel].pether_control;
+        phy_access = g_eth_control_ch[channel].phy_access;
+        petherc_adr = pether_ch[phy_access].petherc;
+
+        /* Disable receive and transmit. */
+        petherc_adr->ECMR.BIT.RE = 0;
+        petherc_adr->ECMR.BIT.TE = 0;
+
+        transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+
+        if ((NULL != cb_func.pcb_func) && (FIT_NO_FUNC != cb_func.pcb_func))
+        {
+            cb_arg.channel = channel;
+            cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_OFF;
+            (*cb_func.pcb_func)((void *) &cb_arg);
+        }
+#endif
+    }
+    else
+    {
+#if (ETHER_CFG_NON_BLOCKING == 1)
+        pmgi_close(pmgi_channel);
+        if ((NULL != cb_func.pcb_pmgi_hnd) && (FIT_NO_FUNC != cb_func.pcb_pmgi_hnd))
+        {
+            R_BSP_SoftwareUnlock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[pmgi_channel].locked);
+            pmgi_cb_arg.channel = channel;
+            pmgi_cb_arg.event = PMGI_IDLE;
+            pmgi_cb_arg.mode = LINKPROCESS;
+            (*cb_func.pcb_pmgi_hnd)((void *)&pmgi_cb_arg);
+        }
+#endif
+        /* no operation */
+    }
+} /* End of function R_ETHER_LinkProcess() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_WakeOnLAN
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_WakeOnLAN() function switches the ETHERC setting from normal transmission/reception
+ *            to Magic Packet detection.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @retval    ETHER_SUCCESS
+ *            - Processing completed successfully or the PMGI operation start normally when the non-blocking mode
+ *              is enable.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_LINK
+ *            - Auto-negotiation is not completed, and reception is not enabled.
+ * @retval    ETHER_ERR_OTHER
+ *            - A switch to magic packet detection was performed when the link state was link is down.
+ *              Or the non-blocking mode is enabled and the interrupt handler function is not registered.
+ * @retval    ETHER_ERR_LOCKED
+ *            - When PHY access is in progress when non-blocking mode is enabled.
+ * @details   The R_ETHER_WakeOnLAN() function initializes the ETHERC and EDMAC,
+ *            and then switches the ETHERC to Magic Packet detection.\n
+ *            If non-blocking call is disabled, return values indicate whether the ETHERC has been switched
+ *            to Magic Packet detection or not. When auto-negotiation is not completed,
+ *            and transmission/reception is not enabled, ETHER_ERR_LINK is returned.
+ *            ETHER_ERR_OTHER is returned if the link is down after ETHERC is set to Magic Packet detection.\n
+ *            When non-blocking mode is enabled, the processing result of the function is passed as
+ *            an argument of the PMGI callback function.
+ * @note      None.
+ */
+ether_return_t R_ETHER_WakeOnLAN (uint32_t channel)
+{
+#if (ETHER_CFG_USE_LINKSTA == 1 && ETHER_CFG_NON_BLOCKING == 0)
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+#endif
+    ether_return_t ret;
+
+#if (ETHER_CFG_NON_BLOCKING == 1)
+    uint16_t reg_data = 0;
+    uint16_t pmgi_channel;
+    pmgi_cb_arg_t pmgi_cb_arg;
+#endif
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+
+#if (ETHER_CFG_NON_BLOCKING == 1)
+    if (NULL == cb_func.pcb_pmgi_hnd)
+    {
+        return ETHER_ERR_OTHER;
+    }
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    if (false == R_BSP_SoftwareLock((BSP_CFG_USER_LOCKING_TYPE *)&g_phy_current_param[pmgi_channel].locked))
+    {
+        return ETHER_ERR_LOCKED;
+    }
+
+    set_ether_channel(channel);
+
+    if (R_PHY_ERROR == pmgi_initial(pmgi_channel))
+    {
+        R_BSP_SoftwareUnlock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[pmgi_channel].locked);
+        if ((NULL != cb_func.pcb_pmgi_hnd) && (FIT_NO_FUNC != cb_func.pcb_pmgi_hnd))
+        {
+            pmgi_cb_arg.channel = channel;
+            pmgi_cb_arg.event = PMGI_ERROR;
+            pmgi_cb_arg.mode = WAKEONLAN;
+            (*cb_func.pcb_pmgi_hnd)((void *)&pmgi_cb_arg);
+        }
+        return ETHER_ERR_OTHER;
+    }
+#endif
+
+    /* When the Link up processing is not completed, return error */
+    if (ETHER_FLAG_OFF == transfer_enable_flag[channel])
+    {
+        ret = ETHER_ERR_LINK;
+#if (ETHER_CFG_NON_BLOCKING == 1)
+        pmgi_close(pmgi_channel);
+        if ((NULL != cb_func.pcb_pmgi_hnd) && (FIT_NO_FUNC != cb_func.pcb_pmgi_hnd))
+        {
+            R_BSP_SoftwareUnlock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[pmgi_channel].locked);
+            pmgi_cb_arg.channel = channel;
+            pmgi_cb_arg.event = PMGI_IDLE;
+            pmgi_cb_arg.mode = WAKEONLAN;
+            (*cb_func.pcb_pmgi_hnd)((void *)&pmgi_cb_arg);
+        }
+#endif
+    }
+    /* When the Link up processing is completed */
+    else
+    {
+        /* Change to the magic packet detection mode.  */
+        ether_configure_mac(channel, mac_addr_buf[channel], USE_MAGIC_PACKET_DETECT);
+#if (ETHER_CFG_NON_BLOCKING == 1)
+        g_phy_current_param[pmgi_channel].mode = WAKEONLAN;
+        g_phy_current_param[pmgi_channel].step = STEP0;
+
+        pmgi_access(channel, PHY_REG_STATUS, reg_data, PMGI_READ);
+
+        return ETHER_SUCCESS;
+#elif (ETHER_CFG_NON_BLOCKING == 0)
+        ret = ether_do_link(channel, USE_MAGIC_PACKET_DETECT);
+        if (ETHER_SUCCESS == ret)
+        {
+    #if (ETHER_CFG_USE_LINKSTA == 1)
+            pether_ch = g_eth_control_ch[channel].pether_control;
+            phy_access = g_eth_control_ch[channel].phy_access;
+            petherc_adr = pether_ch[phy_access].petherc;
+
+            /* It is confirmed not to become Link down while changing the setting. */
+            if (ETHER_CFG_LINK_PRESENT == petherc_adr->PSR.BIT.LMON)
+            {
+                ret = ETHER_SUCCESS;
+            }
+            else
+            {
+                ret = ETHER_ERR_OTHER;
+            }
+    #else
+            /* It is confirmed not to become Link down while changing the setting. */
+            ret = R_ETHER_CheckLink_ZC(channel);
+    #endif
+        }
+        else
+        {
+            ret = ETHER_ERR_OTHER;
+        }
+#endif
+    }
+    return ret;
+} /* End of function R_ETHER_WakeOnLAN() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_Read
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_Read() function receives data into the specified receive buffer.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @param[out] *pbuf
+ *             Specifies the receive buffer (to store the receive data).\n
+ *             The maximum write size is 1,514 bytes. When calling this function,
+ *             specify the start address of a array with a capacity of 1,514 bytes.
+ * @retval    A value of 1 or greater
+ *            - Returns the number of bytes received.
+ * @retval    ETHER_NO_DATA
+ *            - A zero value indicates no data is received.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_INVALID_PTR
+ *            - Value of the pointer is NULL or FIT_NO_PTR.
+ * @retval    ETHER_ERR_LINK
+ *            - Auto-negotiation is not completed, and reception is not enabled.
+ * @retval    ETHER_ERR_MPDE
+ *            - As a Magic Packet is being detected, transmission and reception is not enabled.
+ * @retval    ETHER_ERR_MC_FRAME
+ *            - Multicast frame detected when multicast frame filtering is enabled.
+ * @details   This function stores the receive data in the specified receive buffer.\n
+ *            Return values indicate the number of bytes received. If there is no data available at the time
+ *            of the call, ETHER_NO_DATA is returned. When auto-negotiation is not completed,
+ *            and reception is not enabled, ETHER_ERR_LINK is returned. ETHER_ERR_MPDE is returned
+ *            when a Magic Packet is being detected.\n
+ *            When multicast frame filtering on the specified channel is enabled by the R_ETHER_Control function,
+ *            the buffer is released immediately when a multicast frame is detected.
+ *            Also, the value ETHER_ERR_MC_FRAME is returned.
+ *            Note that when hardware-based multicast frame filtering is enabled on the RX64M, RX71M, RX72M,
+ *            RX72N or RX66N, multicast frames are discarded by the hardware and detection is not possible.\n
+ *            Frames that generate a receive FIFO overflow, residual-bit frame receive error,
+ *            long frame receive error, short frame receive error, PHY-LSI receive error, or receive frame
+ *            CRC error are treated as receive frame errors. When a receive frame error occurs,
+ *            the descriptor data is discarded, the status is cleared, and reading of data continues.
+ * @note      1.As this function calls the R_ETHER_Read_ZC2() function and the R_ETHER_Read_ZC2_BufRelease()
+ *              function internally, data is copied between the buffer pointed by the EDMAC receive descriptor
+ *              and the receive buffer specified by the R_ETHER_Read() function. (The maximum write size is
+ *              1,514 bytes, so set aside a space of 1,514 bytes for the specified receive buffer.)\n
+ *            2.Make sure not to use the R_ETHER_Read_ZC2() function and R_ETHER_Read_ZC2_BufRelease()
+ *              function when using the R_ETHER_Read() function.\n
+ *            3.This function uses the standard function memcpy, so string.h is included.\n
+ *            4.If the value ETHER_ERR_LINK is returned when this function is called,
+ *              initialize the Ethernet FIT module.
+ */
+int32_t R_ETHER_Read (uint32_t channel, void *pbuf)
+{
+    int32_t ret;
+    int32_t ret2;
+    uint8_t * pread_buffer_address; /* Buffer location controlled by the Ethernet driver */
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+    if ((NULL == pbuf) || (FIT_NO_PTR == pbuf))
+    {
+        return ETHER_ERR_INVALID_PTR;
+    }
+
+    /* (1) Retrieve the receive buffer location controlled by the  descriptor. */
+    ret = R_ETHER_Read_ZC2(channel, (void **) &pread_buffer_address);
+
+    /* When there is data to receive */
+    if (ret > ETHER_NO_DATA)
+    {
+        /* (2) Copy the data read from the receive buffer which is controlled by the descriptor to
+         the buffer which is specified by the user (up to 1024 bytes). */
+        memcpy(pbuf, pread_buffer_address, (uint32_t )ret);
+
+        /* (3) Read the receive data from the receive buffer controlled by the descriptor,
+         and then release the receive buffer. */
+        ret2 = R_ETHER_Read_ZC2_BufRelease(channel);
+
+        if (ETHER_SUCCESS == ret2) /* When this function is completed successfully */
+        {
+            /* Do Nothing */
+        }
+
+        /* Overwrite the error information */
+        else
+        {
+            ret = ret2;
+        }
+    }
+
+    /* When there is no data to receive */
+    else
+    {
+        /* Do Nothing */
+    }
+    return ret;
+} /* End of function R_ETHER_Read() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_Write
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_Write() function transmits the data from the specified transmit buffer.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @param[in] *pbuf
+ *             Specifies the transmit data (the destination for the transmit data to be written).
+ * @param[in] len
+ *             Specifies the size (60 to 1,514 bytes) which is the Ethernet frame length minus 4 bytes of CRC.
+ * @retval    ETHER_SUCCESS
+ *            - Processing completed successfully.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_INVALID_DATA
+ *            - Value of the argument is out of range.
+ * @retval    ETHER_ERR_INVALID_PTR
+ *            - Value of the pointer is NULL or FIT_NO_PTR.
+ * @retval    ETHER_ERR_LINK
+ *            - Auto-negotiation is not completed, and reception is not enabled.
+ * @retval    ETHER_ERR_MPDE
+ *            - As a Magic Packet is being detected, transmission and reception is not enabled.
+ * @retval    ETHER_ERR_TACT
+ *            - Transmit buffer is not empty.
+ * @details   This function transmits data from the specified transmit buffer.\n
+ *            Set the buffer length to be not less than 60 bytes (64 bytes of the minimum Ethernet frame
+ *            minus 4 bytes of CRC) and not more than 1,514 bytes (1,518 bytes of the maximum Ethernet frame
+ *            minus 4 bytes of CRC).\n
+ *            To transmit data less than 60 bytes, make sure to pad the data with zero to be 60 bytes.\n
+ *            Return values indicate that the data written in the transmit buffer is enabled to be transmitted.\n
+ *            ETHER_SUCCESS is returned when the data in the transmit buffer is enabled to transmit at the time
+ *            of the call. When auto-negotiation is not completed, and transmission is not enabled,
+ *            ETHER_ERR_LINK is returned. ETHER_ERR_MPDE is returned when a Magic Packet is being detected.
+ *            The value ETHER_ERR_TACT is returned if there is no free space in the transmit buffer.
+ * @note      1.To transmit data less than 60 bytes, make sure to pad the data with zero to be 60 bytes.\n
+ *            2.As this function calls the R_ETHER_Write_ZC2_GetBuf() function and
+ *              the R_ETHER_Write_ZC2_SetBuf() function internally, data is copied between the buffer pointed
+ *              by the EDMAC transmit descriptor and the transmit buffer specified by the R_ETHER_Write() function.\n
+ *            3.Make sure not to use the R_ETHER_Write_ZC2_GetBuf() function and R_ETHER_Write_ZC2_SetBuf()
+ *              function when using the R_ETHER_Write() function.\n
+ *            4.This function uses the standard functions memset and memcpy, so string.h is included.\n
+ *            5.If the value ETHER_ERR_LINK is returned when this function is called,
+ *              initialize the Ethernet FIT module.
+ */
+ether_return_t R_ETHER_Write (uint32_t channel, void *pbuf, const uint32_t len)
+{
+    ether_return_t ret;
+    uint8_t * pwrite_buffer_address;
+    uint16_t write_buf_size;
+
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+    if ((NULL == pbuf) || (FIT_NO_PTR == pbuf))
+    {
+        return ETHER_ERR_INVALID_PTR;
+    }
+    if ((ETHER_BUFSIZE_MIN > len) || (ETHER_BUFSIZE_MAX < len))
+    {
+        return ETHER_ERR_INVALID_DATA;
+    }
+
+    /* (1) Retrieve the transmit buffer location controlled by the  descriptor. */
+    ret = R_ETHER_Write_ZC2_GetBuf(channel, (void **) &pwrite_buffer_address, &write_buf_size);
+
+    /* Writing to the transmit buffer (buf) is enabled. */
+    if (ETHER_SUCCESS == ret)
+    {
+        if (write_buf_size < len)
+        {
+            ret = ETHER_ERR_TACT; /* Transmit buffer overflow */
+        }
+        else
+        {
+            /* Write the transmit data to the transmit buffer. */
+
+            /* (2) Write the data to the transmit buffer controlled by the  descriptor. */
+            memcpy(pwrite_buffer_address, pbuf, len);
+
+            /* (3) Enable the EDMAC to transmit data in the transmit buffer. */
+            ret = R_ETHER_Write_ZC2_SetBuf(channel, len);
+
+            /* 
+             * Confirm that the transmission is completed.
+             * Data written in the transmit buffer is transmitted by the EDMAC. Make sure that the
+             * transmission is completed after writing data to the transmit buffer.
+             * If the R_ETHER_Close_ZC2 function is called to stop the Ethernet communication before
+             * verifying that the transmission is completed, the written data written may not be transmitted.
+             */
+            ret = R_ETHER_CheckWrite(channel);
+        }
+    }
+    return ret;
+} /* End of function R_ETHER_Write() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_CheckWrite
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_CheckWrite() function verifies that data transmission has completed.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @retval    ETHER_SUCCESS
+ *            - Processing completed successfully.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @details   The R_ETHER_CheckWrite() function verifies that data was transmitted.\n
+ *            If the transmission completed, ETHER_SUCCESS is returned.
+ * @note      1.This function should be called after transmit data has been written with
+ *              the R_ETHER_Write_ZC2_Setbuf() function.\n
+ *            2.Note that it takes several tens of microseconds for data transmission to actually complete after
+ *              the R_ETHER_Write_ZC2_Setbuf() function is called. Therefore, when using the R_ETHER_Close_ZC2()
+ *              function to shut down the Ethernet module following data transmission, call the R_ETHER_CheckWrite()
+ *              function after calling the R_ETHER_Write_ZC2_Setbuf() function and, after waiting for
+ *              data transmission to finish, call the R_ETHER_Close_ZC2() function. Calling the R_ETHER_Close_ZC2()
+ *              function without calling the R_ETHER_CheckWrite() function can cause data transmission to be
+ *              cut off before it completes.
+ */
+ether_return_t R_ETHER_CheckWrite (uint32_t channel)
+{
+    ether_return_t ret;
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        ret = ETHER_ERR_INVALID_CHAN;
+    }
+    else
+    {
+        pether_ch = g_eth_control_ch[channel].pether_control;
+        phy_access = g_eth_control_ch[channel].phy_access;
+        pedmac_adr = pether_ch[phy_access].pedmac;
+        /* WAIT_LOOP */
+        while (0 != pedmac_adr->EDTRR.BIT.TR)
+        {
+            /* Do Nothing */
+        }
+        ret = ETHER_SUCCESS;
+    }
+    return ret;
+} /* End of function R_ETHER_CheckWrite() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_Control
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_Control() function performs the processing that corresponds to the control code.
+ * @param[in] cmd
+ *             Specifies the control code.
+ * @param[in] control
+ *             Specify the parameters according to the control code.
+ * @retval    ETHER_SUCCESS
+ *            - Processing completed successfully or the PMGI operation start normally when the non-blocking mode
+ *              is enable.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_CHAN_OPEN
+ *            - Indicates the Ethernet cannot be opened because it is being used by another application.
+ * @retval    ETHER_ERR_INVALID_ARG
+ *            - Invalid argument.
+ * @retval    ETHER_ERR_RECV_ENABLE
+ *            - ETHERC receive function enabled.
+ * @details   Performs the processing that corresponds to the control code.
+ *            The value ETHER_ERR_INVALID_ARG is returned if the control code is not supported.\n
+ *            See section 3.14 in application note for more details.
+ * @note      Register callback functions and interrupt handlers before calling the R_ETHER_Open_ZC2() function.
+ *            It may not be possible to detect the first interrupt if the preceding are registered after
+ *            the R_ETHER_Open_ZC2() function is called.\n
+ *            Specify promiscuous mode after setting the control code to CONTROL_POWER_ON and calling this function.
+ *            The intended value will not be stored in the ETHERC mode register if the promiscuous mode setting
+ *            is specified without first setting the control code to CONTROL_POWER_ON and calling this function.\n
+ *            Multicast frame filtering and broadcast frame filtering settings cannot be made while the receive
+ *            functionality of the ETHERC is enabled. Make these settings before calling the R_ETHER_LinkProcess
+ *            function. After the R_ETHER_LinkProcess function is called, the receive functionality is enabled
+ *            when the Ethernet FIT module enters link up status, so calling this function with
+ *            CONTROL_MULTICASTFRAME_FILTER or CONTROL_BROADCASTFRAME_FILTER set as the control code causes
+ *            ETHER_ERR_RECV_ENABLE to be returned, and the settings have no effect.
+ */
+ether_return_t R_ETHER_Control (ether_cmd_t const cmd, ether_param_t const control)
+{
+    ether_return_t ret;
+
+    switch (cmd)
+    {
+        /* Set the callback function pointer */
+        case CONTROL_SET_CALLBACK :
+            ret = ether_set_callback(control);
+        break;
+
+        case CONTROL_SET_PROMISCUOUS_MODE :
+            ret = ether_set_promiscuous_mode(control);
+        break;
+
+        case CONTROL_SET_INT_HANDLER :
+            ret = ether_set_int_handler(control);
+        break;
+
+        case CONTROL_POWER_ON :
+            ret = ether_power_on(control);
+        break;
+
+        case CONTROL_POWER_OFF :
+            ret = ether_power_off(control);
+        break;
+
+        case CONTROL_MULTICASTFRAME_FILTER :
+            ret = ether_set_multicastframe_filter(control);
+        break;
+
+        case CONTROL_BROADCASTFRAME_FILTER :
+            ret = ether_set_broadcastframe_filter(control);
+        break;
+
+        case CONTROL_RECEIVE_DATA_PADDING :
+            ret = ether_receive_data_padding(control);
+        break;
+#if (ETHER_CFG_NON_BLOCKING == 1)
+        case CONTROL_SET_PMGI_CALLBACK :
+            ret = ether_set_pmgi_callback(control);
+        break;
+#endif
+
+        default :
+            ret = ETHER_ERR_INVALID_ARG;
+        break;
+    }
+    return ret;
+} /* End of function R_ETHER_Control() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_WritePHY
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_WritePHY function uses the PHY management interface to write to registers in the PHY-LSI.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @param[in] address
+ *             Specify the address of the PHY-LSI register to be accessed. For details,
+ *             check the data sheet of the PHY-LSI to be used.
+ * @param[in] data
+ *             Specify the data to be written to the PHY-LSI register.
+ *             For details, check the data sheet of the PHY-LSI to be used.
+ * @retval    ETHER_SUCCESS
+ *            - When access is completed normally or when the operation start normally when non-blocking mode is enabled.
+ * @retval    ETHER_ERR_OTHER
+ *            - When non-blocking mode is enabled and no interrupt handler function is registered.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_LOCKED
+ *            - When non-blocking mode is enabled and PHY is being accessed.
+ * @details   The R_ETHER_WritePHY function uses the PHY management interface to write access to registers in the PHY-LSI.
+ *            If non-blocking mode is disabled, ETHER_SUCCESS is returned when write access is successfully completed.\n
+ *            When non-blocking mode is enabled, the callback function is executed after the write access is completed.
+ * @note      None
+ */
+ether_return_t R_ETHER_WritePHY(uint32_t channel, uint16_t address, uint16_t data)
+{
+#if (ETHER_CFG_NON_BLOCKING == 1)
+    uint32_t pmgi_channel;
+#endif
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+
+ #if (ETHER_CFG_NON_BLOCKING == 1)
+    if (NULL == cb_func.pcb_pmgi_hnd)
+    {
+        return ETHER_ERR_OTHER;
+    }
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    if (false == R_BSP_SoftwareLock((BSP_CFG_USER_LOCKING_TYPE *)&g_phy_current_param[pmgi_channel].locked))
+    {
+        return ETHER_ERR_LOCKED;
+    }
+
+    set_ether_channel(channel);
+
+    if (R_PHY_ERROR == pmgi_initial(pmgi_channel))
+    {
+        R_BSP_SoftwareUnlock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[pmgi_channel].locked);
+        return ETHER_ERR_OTHER;
+    }
+
+    g_phy_current_param[pmgi_channel].mode = WRITEPHY;
+    g_phy_current_param[pmgi_channel].step = STEP0;
+
+    pmgi_access(channel, address, data, PMGI_WRITE);
+
+#elif (ETHER_CFG_NON_BLOCKING == 0)
+    phy_write(channel, address, data);
+#endif
+
+    return ETHER_SUCCESS;
+} /* End of function R_ETHER_WritePHY() */
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_ReadPHY
+ *****************************************************************************************************************/ /**
+ * @brief     The R_ETHER_ReadPHY function uses the PHY management interface to access to the registers in the PHY-LSI.
+ * @param[in] channel
+ *             Specifies the ETHERC and EDMAC channel number (0 or 1).
+ *             This value must be specified as 0 on products with only one ETHERC and EDMAC channel.
+ * @param[in] address
+ *             Specify the address of the PHY-LSI register to be accessed. For details,
+ *             check the data sheet of the PHY-LSI to be used.
+ * @param[out] *p_data
+ *             Specify the pointer of the variable to store the register value read from PHY-LSI.
+ *             For details, check the data sheet of the PHY-LSI to be used.
+ * @retval    ETHER_SUCCESS
+ *            - When access is completed normally or when the operation start normally when non-blocking mode is enabled.
+ * @retval    ETHER_ERR_OTHER
+ *            - When non-blocking mode is enabled and no interrupt handler function is registered.
+ * @retval    ETHER_ERR_INVALID_CHAN
+ *            - Nonexistent channel number.
+ * @retval    ETHER_ERR_LOCKED
+ *            - When non-blocking mode is enabled and PHY is being accessed.
+ * @details   When non-blocking mode is disabled, the register value read from the PHY-LSI is stored in
+ *            the argument p_data. Also, ETHER_SUCCESS is returned when the read access is successfully completed.\n
+ *            When non-blocking mode is enabled, the read value is transferred as an argument of the callback function.\n
+ * @note      None
+ */
+ether_return_t R_ETHER_ReadPHY(uint32_t channel, uint16_t address, uint16_t *p_data)
+{
+#if (ETHER_CFG_NON_BLOCKING == 1)
+    uint32_t pmgi_channel;
+#endif
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+
+#if (ETHER_CFG_NON_BLOCKING == 1)
+    if (NULL == cb_func.pcb_pmgi_hnd)
+    {
+        return ETHER_ERR_OTHER;
+    }
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    if (false == R_BSP_SoftwareLock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[pmgi_channel].locked))
+    {
+        return ETHER_ERR_LOCKED;
+    }
+
+    set_ether_channel(channel);
+
+    if (R_PHY_ERROR == pmgi_initial(pmgi_channel))
+    {
+        R_BSP_SoftwareUnlock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[pmgi_channel].locked);
+        return ETHER_ERR_OTHER;
+    }
+
+    g_phy_current_param[pmgi_channel].mode = READPHY;
+    g_phy_current_param[pmgi_channel].step = STEP0;
+
+    pmgi_access(channel, address, *p_data, PMGI_READ);
+
+#elif (ETHER_CFG_NON_BLOCKING == 0)
+    *p_data = phy_read(channel, address);
+#endif
+
+    return ETHER_SUCCESS;
+} /* End of function R_ETHER_ReadPHY() */
+
+/**********************************************************************************************************************
+ * Function Name: R_ETHER_GetVersion
+ *****************************************************************************************************************/ /**
+ * @brief     This function returns the API version.
+ * @return    Version number.
+ * @details   Returns the API version number.
+ * @note      None
+ */
+uint32_t R_ETHER_GetVersion (void)
+{
+    return ((((uint32_t) ETHER_RX_VERSION_MAJOR) << 16) | ((uint32_t) ETHER_RX_VERSION_MINOR));
+} /* End of function R_ETHER_GetVersion() */
+
+/*
+ * Private functions
+ */
+
+/***********************************************************************************************************************
+ * Function Name: ether_reset_mac
+ * Description  : The EDMAC and EtherC are reset through the software reset.
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void ether_reset_mac (uint32_t channel)
+{
+    volatile uint32_t i;
+
+    /* Software reset */
+#if (ETHER_CHANNEL_MAX == 1)
+    if (ETHER_CHANNEL_0 == channel)
+    {
+        EDMAC0.EDMR.BIT.SWR = 1;
+    }
+#elif (ETHER_CHANNEL_MAX == 2)
+    if (ETHER_CHANNEL_0 == channel)
+    {
+        EDMAC0.EDMR.BIT.SWR = 1;
+    }
+    else
+    {
+        EDMAC1.EDMR.BIT.SWR = 1;
+    }
+#endif
+
+    /*
+     * Waiting time until the initialization of ETHERC and EDMAC is completed is 64 cycles
+     * in the clock conversion of an internal bus of EDMAC. 
+     */
+    /* WAIT_LOOP */
+    for (i = 0; i < 0x00000180; i++)
+    {
+        ;
+    }
+
+} /* End of function ether_reset_mac() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_init_descriptors
+ * Description  : The EDMAC descriptors and the driver buffers are initialized.
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void ether_init_descriptors (uint32_t channel)
+{
+    descriptor_t * pdescriptor;
+    uint32_t i;
+
+    /* Initialize the receive descriptors */
+    /* WAIT_LOOP */
+    for (i = 0; i < ETHER_CFG_EMAC_RX_DESCRIPTORS; i++)
+    {
+        pdescriptor = (descriptor_t *) &rx_descriptors[channel][i];
+        pdescriptor->buf_p = (uint8_t *) &(ether_buffers[channel].buffer[i][0]);
+        pdescriptor->bufsize = ETHER_CFG_BUFSIZE;
+        pdescriptor->size = 0;
+        pdescriptor->status = RACT;
+        pdescriptor->next = (descriptor_t *) &rx_descriptors[channel][(i + 1)];
+    }
+
+    /* The last descriptor points back to the start */
+    pdescriptor->status |= RDLE;
+    pdescriptor->next = (descriptor_t *) &rx_descriptors[channel][0];
+
+    /* Initialize application receive descriptor pointer */
+    papp_rx_desc[channel] = (descriptor_t *) &rx_descriptors[channel][0];
+
+    /* Initialize the transmit descriptors */
+    /* WAIT_LOOP */
+    for (i = 0; i < ETHER_CFG_EMAC_TX_DESCRIPTORS; i++)
+    {
+        pdescriptor = (descriptor_t *) &tx_descriptors[channel][i];
+        pdescriptor->buf_p = (uint8_t *) &(ether_buffers[channel].buffer[(ETHER_CFG_EMAC_RX_DESCRIPTORS + i)][0]);
+        pdescriptor->bufsize = 1; /* Set a value equal to or greater than 1. (reference to UMH)
+         When transmitting data, the value of size is set to the function argument
+         R_ETHER_Write_ZC2_SetBuf. */
+        pdescriptor->size = 0; /* Reserved : The write value should be 0. (reference to UMH) */
+        pdescriptor->status = 0;
+        pdescriptor->next = (descriptor_t *) &(tx_descriptors[channel][(i + 1)]);
+    }
+
+    /* The last descriptor points back to the start */
+    pdescriptor->status |= TDLE;
+    pdescriptor->next = (descriptor_t *) &tx_descriptors[channel][0];
+
+    /* Initialize application transmit descriptor pointer */
+    papp_tx_desc[channel] = (descriptor_t *) &tx_descriptors[channel][0];
+} /* End of function ether_init_descriptors() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_config_ethernet
+ * Description  : Configure the Ethernet Controller (EtherC) and the Ethernet
+ *                Direct Memory Access controller (EDMAC).
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ *                mode - 
+ *                   The operational mode is specified. 
+ *                   NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually
+ *                   USE_MAGIC_PACKET_DETECT    (1) - Magic packet detection mode
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void ether_config_ethernet (uint32_t channel, const uint8_t mode)
+{
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc_adr;
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return;
+    }
+
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+    pedmac_adr = pether_ch[phy_access].pedmac;
+
+    /* Magic packet detection mode */
+    if (USE_MAGIC_PACKET_DETECT == mode)
+    {
+#if (ETHER_CFG_USE_LINKSTA == 1)
+        petherc_adr->ECSIPR.LONG = 0x00000006;
+#elif (ETHER_CFG_USE_LINKSTA == 0)
+        petherc_adr->ECSIPR.LONG = 0x00000002;
+#endif
+        pedmac_adr->EESIPR.LONG = 0x00400000;
+    }
+
+    /* Normal mode */
+    else
+    {
+#if (ETHER_CFG_USE_LINKSTA == 1)
+        /* LINK Signal Change Interrupt Enable */
+        petherc_adr->ECSR.BIT.LCHNG = 1;
+        petherc_adr->ECSIPR.BIT.LCHNGIP = 1;
+#endif
+        pedmac_adr->EESIPR.BIT.ECIIP = 1;
+
+        /* Frame receive interrupt and frame transmit end interrupt */
+        pedmac_adr->EESIPR.BIT.FRIP = 1; /* Enable the frame receive interrupt. */
+        pedmac_adr->EESIPR.BIT.TCIP = 1; /* Enable the frame transmit end interrupt. */
+    }
+
+    /* Ethernet length 1514bytes + CRC and intergap is 96-bit time */
+    petherc_adr->RFLR.LONG = 1518;
+    petherc_adr->IPGR.LONG = 0x00000014;
+
+    /* Continuous reception number of Broadcast frame */
+    petherc_adr->BCFRR.LONG = bc_filter_count[channel];
+
+#ifdef __LIT
+    /* Set little endian mode */
+    /* Ethernet length 1514bytes + CRC and intergap is 96-bit time */
+    pedmac_adr->EDMR.BIT.DE = 1;
+#endif
+    /* __LIT */
+
+    /* Initialize Rx descriptor list address */
+    /* Casting the pointer to a uint32_t type is valid because the Renesas Compiler uses 4 bytes per pointer. */
+    pedmac_adr->RDLAR = (void*) papp_rx_desc[channel];
+
+    /* Initialize Tx descriptor list address */
+    /* Casting the pointer to a uint32_t type is valid because the Renesas Compiler uses 4 bytes per pointer. */
+    pedmac_adr->TDLAR = (void*) papp_tx_desc[channel];
+
+    if (ETHER_MC_FILTER_ON == mc_filter_flag[channel])
+    {
+        /* Reflect the EESR.RMAF bit status in the RD0.RFS bit in the receive descriptor */
+        pedmac_adr->TRSCER.LONG = 0x00000000;
+    }
+    else
+    {
+        /* Don't reflect the EESR.RMAF bit status in the RD0.RFS bit in the receive descriptor */
+        pedmac_adr->TRSCER.LONG = 0x00000080;
+    }
+
+    /* Threshold of Tx_FIFO */
+    /* To prevent a transmit underflow, setting the initial value (store and forward modes) is recommended. */
+    pedmac_adr->TFTR.LONG = 0x00000000;
+
+#if (defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66N))
+    /* transmit fifo & receive fifo is 2048 bytes */
+    pedmac_adr->FDR.LONG = 0x00000707;
+#elif (defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N))
+    /* transmit fifo is 2048 bytes, receive fifo is 4096 bytes */
+    pedmac_adr->FDR.LONG = 0x0000070F;
+#endif
+
+    /*  Configure receiving method
+     b0      RNR - Receive Request Bit Reset - Continuous reception of multiple frames is possible.
+     b31:b1  Reserved set to 0
+     */
+    pedmac_adr->RMCR.LONG = 0x00000001;
+
+    /* Insert receive data padding  */
+    pedmac_adr->RPADIR.BIT.PADR = padding_insert_position[channel];
+    pedmac_adr->RPADIR.BIT.PADS = padding_insert_size[channel];
+
+} /* End of function ether_config_ethernet() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_pause_resolution
+ * Description  : Determines PAUSE frame generation and handling. Uses
+ *                the resolution Table 28B-3 of IEEE 802.3-2008.
+ * Arguments    : local_ability -
+ *                    local PAUSE capability (2 least significant bits)
+ *                partner_ability -
+ *                    link partner PAUSE capability (2 least significant bits)
+ *                *ptx_pause -
+ *                    pointer to location to store the result of the table lookup for transmit
+ *                    PAUSE. 1 is enable, 0 is disable.
+ *                *prx_pause -
+ *                    pointer to location to store the result of the table lookup for receive
+ *                    PAUSE. 1 is enable, 0 is disable.
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void ether_pause_resolution (uint16_t local_ability, uint16_t partner_ability, uint16_t *ptx_pause,
+        uint16_t *prx_pause)
+{
+    uint32_t i;
+    uint32_t ability_compare;
+
+    /*
+     * Arrange the bits so that they correspond to the Table 28B-3
+     * of the IEEE 802.3 values.
+     */
+    ability_compare = (uint32_t) (((local_ability & LINK_RES_ABILITY_MASK) << LINK_RES_LOCAL_ABILITY_BITSHIFT)
+            | (partner_ability & LINK_RES_ABILITY_MASK));
+
+    /* Walk through the look up table */
+    /* WAIT_LOOP */
+    for (i = 0; i < PAUSE_TABLE_ENTRIES; i++)
+    {
+        if ((ability_compare & pause_resolution[i].mask) == pause_resolution[i].value)
+        {
+            (*ptx_pause) = pause_resolution[i].transmit;
+            (*prx_pause) = pause_resolution[i].receive;
+            return;
+        }
+    }
+} /* End of function ether_pause_resolution() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_configure_mac
+ * Description  : Software reset is executed, and ETHERC and EDMAC are configured. 
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ *                mac_addr -
+ *                    The MAC address of ETHERC
+ *                mode -
+ *                    The operational mode is specified. 
+ *                    NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually
+ *                    USE_MAGIC_PACKET_DETECT    (1) - Magic packet detection mode
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void ether_configure_mac (uint32_t channel, const uint8_t mac_addr[], const uint8_t mode)
+{
+    uint32_t mac_h;
+    uint32_t mac_l;
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return;
+    }
+
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+
+    /* Software reset */
+    ether_reset_mac(channel);
+
+    /* Set MAC address */
+    mac_h = (((((uint32_t) mac_addr[0] << 24) | ((uint32_t) mac_addr[1] << 16)) | ((uint32_t) mac_addr[2] << 8))
+            | (uint32_t) mac_addr[3]);
+
+    mac_l = (((uint32_t) mac_addr[4] << 8) | (uint32_t) mac_addr[5]);
+
+    petherc_adr->MAHR = mac_h;
+    petherc_adr->MALR.LONG = mac_l;
+
+    /* Initialize receive and transmit descriptors */
+    ether_init_descriptors(channel);
+
+    /* Perform reset of hardware interface configuration */
+    ether_config_ethernet(channel, mode);
+
+} /* End of function ether_configure_mac() */
+
+#if (ETHER_CFG_NON_BLOCKING == 0)
+/***********************************************************************************************************************
+ * Function Name: ether_do_link
+ * Description  : Determines the partner PHY capability through
+ *                auto-negotiation process. The link abilities
+ *                are handled to determine duplex, speed and flow
+ *                control (PAUSE frames).
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ *                mode - 
+ *                    The operational mode is specified. 
+ *                    NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually
+ *                    USE_MAGIC_PACKET_DETECT    (1) - Magic packet detection mode
+ * Return Value : ETHER_SUCCESS -
+ *                    Processing completed successfully
+ *                ETHER_ERR_INVALID_CHAN -
+ *                    Nonexistent channel number
+ *                ETHER_ERR_OTHER -
+ *                    Auto-negotiation of PHY-LSI is not completed or result of Auto-negotiation is abnormal.
+ ***********************************************************************************************************************/
+static ether_return_t ether_do_link (uint32_t channel, const uint8_t mode)
+{
+    ether_return_t ret;
+    uint16_t link_speed_duplex = 0;
+    uint16_t local_pause_bits = 0;
+    uint16_t partner_pause_bits = 0;
+    uint16_t transmit_pause_set = 0;
+    uint16_t receive_pause_set = 0;
+    uint16_t full_duplex = 0;
+    uint16_t link_result = 0;
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc_adr;
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+    pedmac_adr = pether_ch[phy_access].pedmac;
+
+    /* Set the link status */
+    link_result = phy_set_autonegotiate(channel, &link_speed_duplex, &local_pause_bits, &partner_pause_bits);
+
+    if (R_PHY_OK == link_result)
+    {
+        switch (link_speed_duplex)
+        {
+            /* Half duplex link */
+            case PHY_LINK_100H :
+                petherc_adr->ECMR.BIT.DM = 0;
+                petherc_adr->ECMR.BIT.RTM = 1;
+                ret = ETHER_SUCCESS;
+            break;
+
+            case PHY_LINK_10H :
+                petherc_adr->ECMR.BIT.DM = 0;
+                petherc_adr->ECMR.BIT.RTM = 0;
+                ret = ETHER_SUCCESS;
+            break;
+
+                /* Full duplex link */
+            case PHY_LINK_100F :
+                petherc_adr->ECMR.BIT.DM = 1;
+                petherc_adr->ECMR.BIT.RTM = 1;
+                full_duplex = 1;
+                ret = ETHER_SUCCESS;
+            break;
+
+            case PHY_LINK_10F :
+                petherc_adr->ECMR.BIT.DM = 1;
+                petherc_adr->ECMR.BIT.RTM = 0;
+                full_duplex = 1;
+                ret = ETHER_SUCCESS;
+            break;
+
+            default :
+                ret = ETHER_ERR_OTHER;
+            break;
+        }
+
+        /* At the communicate mode usually */
+        if (ETHER_SUCCESS == ret)
+        {
+            if (NO_USE_MAGIC_PACKET_DETECT == mode)
+            {
+
+                /* When pause frame is used */
+                if ((full_duplex) && (ETHER_FLAG_ON == pause_frame_enable[channel]))
+                {
+                    /* Set automatic PAUSE for 512 bit-time */
+                    petherc_adr->APR.LONG = 0x0000FFFF;
+
+                    /* Set unlimited retransmit of PAUSE frames */
+                    petherc_adr->TPAUSER.LONG = 0;
+
+                    /* PAUSE flow control FIFO settings. */
+                    pedmac_adr->FCFTR.LONG = 0x00000000;
+
+                    /* Control of a PAUSE frame whose TIME parameter value is 0 is enabled. */
+                    petherc_adr->ECMR.BIT.ZPF = 1;
+
+                    /**
+                     * Enable PAUSE for full duplex link depending on
+                     * the pause resolution results
+                     */
+                    ether_pause_resolution(local_pause_bits, partner_pause_bits, &transmit_pause_set,
+                            &receive_pause_set);
+
+                    if (XMIT_PAUSE_ON == transmit_pause_set)
+                    {
+                        /* Enable automatic PAUSE frame transmission */
+                        petherc_adr->ECMR.BIT.TXF = 1;
+                    }
+                    else
+                    {
+                        /* Disable automatic PAUSE frame transmission */
+                        petherc_adr->ECMR.BIT.TXF = 0;
+                    }
+
+                    if (RECV_PAUSE_ON == receive_pause_set)
+                    {
+                        /* Enable reception of PAUSE frames */
+                        petherc_adr->ECMR.BIT.RXF = 1;
+                    }
+                    else
+                    {
+                        /* Disable reception of PAUSE frames */
+                        petherc_adr->ECMR.BIT.RXF = 0;
+                    }
+                }
+
+                /* When pause frame is not used */
+                else
+                {
+                    /* Disable PAUSE for half duplex link */
+                    petherc_adr->ECMR.BIT.TXF = 0;
+                    petherc_adr->ECMR.BIT.RXF = 0;
+                }
+
+                /* Set the promiscuous mode bit */
+                petherc_adr->ECMR.BIT.PRM = promiscuous_mode[channel];
+
+                /* Enable receive and transmit. */
+                petherc_adr->ECMR.BIT.RE = 1;
+                petherc_adr->ECMR.BIT.TE = 1;
+
+                /* Enable EDMAC receive */
+                pedmac_adr->EDRRR.LONG = 0x1;
+            }
+
+            /* At the magic packet detection mode */
+            else
+            {
+                /* The magic packet detection is permitted. */
+                petherc_adr->ECMR.BIT.MPDE = 1;
+
+                /* Because data is not transmitted for the magic packet detection waiting, 
+                 only the reception is permitted. */
+                petherc_adr->ECMR.BIT.RE = 1;
+
+                /*
+                 * The reception function of EDMAC keep invalidity 
+                 * because the receive data don't need to be read when the magic packet detection mode.
+                 */
+            }
+        }
+    }
+    else
+    {
+        ret = ETHER_ERR_OTHER;
+    }
+
+    return ret;
+} /* End of function ether_do_link() */
+#endif
+
+/***********************************************************************************************************************
+ * Function Name: ether_set_callback
+ * Description  : Set the callback function
+ * Arguments    : control -
+ *                    Callback function pointer. 
+ *                    If you would rather poll for finish then please input FIT_NO_FUNC for this argument.
+ * Return Value : ETHER_SUCCESS
+ *                    Processing completed successfully
+ ***********************************************************************************************************************/
+static ether_return_t ether_set_callback (ether_param_t const control)
+{
+    void (*pcb_func) (void *);
+
+    pcb_func = control.ether_callback.pcb_func;
+
+    /* Check callback function pointer, of whether or NULL FIT_NO_FUNC */
+    if ((NULL != pcb_func) && (FIT_NO_FUNC != pcb_func))
+    {
+        cb_func.pcb_func = pcb_func; /* Set the callback function */
+    }
+
+    return ETHER_SUCCESS;
+} /* End of function ether_set_callback() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_set_promiscuous_mode
+ * Description  : Set promiscuous mode bit
+ * Arguments    : control -
+ *                    Promiscuous mode bit
+ * Return Value : ETHER_SUCCESS -
+ *                    Processing completed successfully
+ *                ETHER_ERR_INVALID_CHAN - 
+ *                    Nonexistent channel number
+ ***********************************************************************************************************************/
+static ether_return_t ether_set_promiscuous_mode (ether_param_t const control)
+{
+    ether_promiscuous_t * p_arg;
+    uint32_t channel;
+
+    p_arg = control.p_ether_promiscuous;
+    channel = p_arg->channel;
+
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_CHAN;
+    }
+    else
+    {
+        promiscuous_mode[channel] = p_arg->bit;
+    }
+    return ETHER_SUCCESS;
+} /* End of function ether_set_promiscuous_mode() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_set_int_handler
+ * Description  : Set the interrupt handler
+ * Arguments    : control -
+ *                    Interrupt handler pointer.
+ *                    If you would rather poll for finish then please input FIT_NO_FUNC for this argument.
+ * Return Value : ETHER_SUCCESS -
+ *                    Processing completed successfully
+ *                ETHER_ERR_INVALID_ARG -
+ *                    Invalid argument
+ ***********************************************************************************************************************/
+static ether_return_t ether_set_int_handler (ether_param_t const control)
+{
+    void (*pcb_int_hnd) (void *);
+    ether_return_t ret = ETHER_ERR_INVALID_ARG;
+
+    pcb_int_hnd = control.ether_int_hnd.pcb_int_hnd;
+    if (NULL != pcb_int_hnd)
+    {
+        cb_func.pcb_int_hnd = pcb_int_hnd;
+        ret = ETHER_SUCCESS;
+    }
+    return ret;
+} /* End of function ether_set_int_handler() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_power_on
+ * Description  : Turns on power to a ETHER channel.
+ * Arguments    : control -
+ *                    Ethernet channel number
+ * Return Value : ETHER_SUCCESS -
+ *                    Processing completed successfully
+ *                ETHER_ERR_INVALID_CHAN -
+ *                    Nonexistent channel number
+ *                ETHER_ERR_CHAN_OPEN -
+ *                    Indicates the Ethernet cannot be opened because it is being used by another application
+ *                ETHER_ERR_INVALID_ARG -
+ *                    Invalid argument
+ ***********************************************************************************************************************/
+static ether_return_t ether_power_on (ether_param_t const control)
+{
+    uint32_t channel;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+    ether_return_t ret;
+
+    ret = ETHER_ERR_INVALID_ARG;
+    channel = (uint32_t) control.channel;
+
+    if (ETHER_CHANNEL_MAX > channel)
+    {
+        pether_ch = g_eth_control_ch[channel].pether_control;
+        phy_access = g_eth_control_ch[channel].phy_access;
+
+        /* Set port connect */
+        ether_set_phy_mode(pether_ch[phy_access].port_connect);
+
+        /* ETHERC/EDMAC Power on */
+        ret = power_on_control(channel);
+    }
+    return ret;
+} /* End of function ether_power_on() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_power_off
+ * Description  : Turns on power to a ETHER channel.
+ * Arguments    : control -
+ *                    Ethernet channel number
+ * Return Value : ETHER_SUCCESS -
+ *                    Processing completed successfully
+ *                ETHER_ERR_INVALID_ARG -
+ *                    Invalid argument
+ ***********************************************************************************************************************/
+static ether_return_t ether_power_off (ether_param_t const control)
+{
+    uint32_t channel;
+    ether_return_t ret;
+
+    ret = ETHER_ERR_INVALID_ARG;
+    channel = (uint32_t) control.channel;
+
+    if (ETHER_CHANNEL_MAX > channel)
+    {
+        /* ETHERC/EDMAC Power off */
+        power_off_control(channel);
+        ret = ETHER_SUCCESS;
+    }
+    return ret;
+} /* End of function ether_power_off() */
+
+/***********************************************************************************************************************
+ * Function Name: power_on
+ * Description  : Turns on power to a ETHER channel.
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ * Return Value : ETHER_SUCCESS -
+ *                    Processing completed successfully
+ *                ETHER_ERR_INVALID_CHAN -
+ *                    Nonexistent channel number
+ *                ETHER_ERR_CHAN_OPEN -
+ *                    Indicates the Ethernet cannot be opened because it is being used by another application
+ ***********************************************************************************************************************/
+static ether_return_t power_on (uint32_t channel)
+{
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    bsp_int_ctrl_t     int_ctrl;
+#endif
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        /* Should never get here. Valid channel number is checked above. */
+        return ETHER_ERR_INVALID_CHAN;
+    }
+
+#if (ETHER_CHANNEL_MAX == 1)
+    /* Attempt to obtain lock so we know we have exclusive access to ETHER channel. */
+    if (false == R_BSP_HardwareLock((mcu_lock_t) (BSP_LOCK_ETHERC0)))
+    {
+        return ETHER_ERR_CHAN_OPEN;
+    }
+
+    /* Attempt to obtain lock so we know we have exclusive access to EDMAC channel. */
+    if (false == R_BSP_HardwareLock((mcu_lock_t) (BSP_LOCK_EDMAC0)))
+    {
+        /* Release reservation on peripheral. */
+        R_BSP_HardwareUnlock((mcu_lock_t) (BSP_LOCK_ETHERC0));
+        return ETHER_ERR_CHAN_OPEN;
+    }
+#elif (ETHER_CHANNEL_MAX == 2)
+    /* Attempt to obtain lock so we know we have exclusive access to ETHER channel. */
+    if (false == R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_ETHERC0 + channel)))
+    {
+        return ETHER_ERR_CHAN_OPEN;
+    }
+
+    /* Attempt to obtain lock so we know we have exclusive access to EDMAC channel. */
+    if (false == R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_EDMAC0 + channel)))
+    {
+        /* Release reservation on peripheral. */
+        R_BSP_HardwareUnlock((mcu_lock_t)(BSP_LOCK_ETHERC0 + channel));
+        return ETHER_ERR_CHAN_OPEN;
+    }
+#endif
+
+    /* Enable writing to MSTP registers. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR);
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl);
+#endif
+
+    /* Enable selected ETHERC/EDMAC Channel. */
+#if (ETHER_CHANNEL_MAX == 1)
+    if (ETHER_CHANNEL_0 == channel)
+    {
+        MSTP(EDMAC0) = 0;
+    }
+#elif (ETHER_CHANNEL_MAX == 2)
+    if (ETHER_CHANNEL_0 == channel)
+    {
+        MSTP(EDMAC0) = 0;
+    }
+    else
+    {
+        MSTP(EDMAC1) = 0;
+    }
+#endif
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl);
+#endif
+
+    /* Disable writing to MSTP registers. */
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR);
+
+    return ETHER_SUCCESS;
+} /* End of function power_on() */
+
+/***********************************************************************************************************************
+ * Function Name: power_off
+ * Description  : Turns off power to a ETHER channel.
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void power_off (uint32_t channel)
+{
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    bsp_int_ctrl_t    int_ctrl;
+#endif
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        /* Should never get here. Valid channel number is checked above. */
+        return;
+    }
+
+    /* Enable writing to MSTP registers. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR);
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl);
+#endif
+
+    /* Disable selected ETHERC/EDMAC Channel. */
+#if (ETHER_CHANNEL_MAX == 1)
+    if (ETHER_CHANNEL_0 == channel)
+    {
+        MSTP(EDMAC0) = 1;
+    }
+#elif (ETHER_CHANNEL_MAX == 2)
+    if (ETHER_CHANNEL_0 == channel)
+    {
+        MSTP(EDMAC0) = 1;
+    }
+    else
+    {
+        MSTP(EDMAC1) = 1;
+    }
+#endif
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl);
+#endif
+
+    /* Disable writing to MSTP registers. */
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR);
+
+    /* Release reservation on peripheral. */
+#if (ETHER_CHANNEL_MAX == 1)
+    R_BSP_HardwareUnlock((mcu_lock_t) (BSP_LOCK_ETHERC0));
+    R_BSP_HardwareUnlock((mcu_lock_t) (BSP_LOCK_EDMAC0));
+#elif (ETHER_CHANNEL_MAX == 2)
+    R_BSP_HardwareUnlock((mcu_lock_t)(BSP_LOCK_ETHERC0 + channel));
+    R_BSP_HardwareUnlock((mcu_lock_t)(BSP_LOCK_EDMAC0 + channel));
+#endif
+
+} /* End of function power_off() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_set_multicastframe_filter
+ * Description  : set multicast frame filtering function.
+ * Arguments    : control -
+ *                    Ethernet channel number and Multicast Frame filter enable switch
+ * Return Value : ETHER_SUCCESS -
+ *                    Processing completed successfully
+ *                ETHER_ERR_INVALID_ARG -
+ *                    Invalid argument
+ *                ETHER_ERR_RECV_ENABLE -
+ *                    Receive function is enable.
+ ***********************************************************************************************************************/
+static ether_return_t ether_set_multicastframe_filter (ether_param_t const control)
+{
+    ether_multicast_t * p_arg;
+    uint32_t channel;
+    ether_mc_filter_t flag;
+    ether_return_t ret;
+    uint32_t phy_access;
+
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc_adr;
+    const ether_control_t * pether_ch;
+
+    ret = ETHER_ERR_INVALID_ARG;
+    p_arg = control.p_ether_multicast;
+    channel = p_arg->channel;
+    flag = p_arg->flag;
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ret;
+    }
+    if ((ETHER_MC_FILTER_ON != flag) && (ETHER_MC_FILTER_OFF != flag))
+    {
+        return ret;
+    }
+
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+
+    /* Check receive function is enable in ETHERC */
+    if (0 == petherc_adr->ECMR.BIT.RE)
+    {
+        if (ETHER_MC_FILTER_ON == flag)
+        {
+            mc_filter_flag[channel] = ETHER_MC_FILTER_ON;
+        }
+        else
+        {
+            mc_filter_flag[channel] = ETHER_MC_FILTER_OFF;
+        }
+
+        ret = ETHER_SUCCESS;
+    }
+    else
+    {
+        ret = ETHER_ERR_RECV_ENABLE;
+    }
+
+    return ret;
+} /* End of function ether_set_multicastframe_filter() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_set_broadcastframe_filter
+ * Description  : set broadcast frame filtering function.
+ * Arguments    : control -
+ *                    ETHERC channel number and receive count for continuous Broadcast Frame
+ * Return Value : ETHER_SUCCESS -
+ *                    Processing completed successfully
+ *                ETHER_ERR_INVALID_ARG -
+ *                    Invalid argument
+ *                ETHER_ERR_RECV_ENABLE -
+ *                    Receive function is enable.
+ ***********************************************************************************************************************/
+static ether_return_t ether_set_broadcastframe_filter (ether_param_t const control)
+{
+    ether_broadcast_t * p_arg;
+    uint32_t channel;
+    uint32_t counter;
+    ether_return_t ret;
+    uint32_t phy_access;
+
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc_adr;
+    const ether_control_t * pether_ch;
+
+    ret = ETHER_ERR_INVALID_ARG;
+    p_arg = control.p_ether_broadcast;
+    channel = p_arg->channel;
+    counter = p_arg->counter;
+
+    /* Check argument */
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ret;
+    }
+    if (0 != (counter & 0x0FFFF0000))
+    {
+        return ret;
+    }
+
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+
+    /* Check receive function is enable in ETHERC */
+    if (0 == petherc_adr->ECMR.BIT.RE)
+    {
+        bc_filter_count[channel] = counter;
+        ret = ETHER_SUCCESS;
+    }
+    else
+    {
+        ret = ETHER_ERR_RECV_ENABLE;
+    }
+
+    return ret;
+} /* End of function ether_set_broadcastframe_filter() */
+
+/***********************************************************************************************************************
+ * Function Name: power_on_control
+ * Description  : Powers on the channel if the ETHEC channel used and the PHY access channel are different, or if the 
+ *                PHY access channel is powered off.
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ * Return Value : ETHER_SUCCESS -
+ *                    Processing completed successfully
+ *                ETHER_ERR_INVALID_CHAN -
+ *                    Nonexistent channel number
+ *                ETHER_ERR_CHAN_OPEN -
+ *                    Indicates the Ethernet cannot be opened because it is being used by another application
+ *              : ETHER_ERR_OTHER -
+ *                    
+ ***********************************************************************************************************************/
+static ether_return_t power_on_control (uint32_t channel)
+{
+#if (ETHER_CHANNEL_MAX == 1)
+    ether_return_t ret = ETHER_ERR_OTHER;
+
+    etherc_edmac_power_cont[ether_phy_access[channel]][channel] = ETHER_MODULE_USE;
+
+    ret = power_on(channel);
+
+    return ret;
+
+#elif ETHER_CHANNEL_MAX == 2
+    ether_return_t ret = ETHER_ERR_OTHER;
+
+    etherc_edmac_power_cont[ether_phy_access[channel]] [channel] = ETHER_MODULE_USE;
+
+    if (channel != ether_phy_access[channel])
+    {
+        ret = power_on(channel);
+        if (ETHER_SUCCESS != ret)
+        {
+            return ret;
+        }
+    }
+
+    if (!(( ETHER_MODULE_USE == etherc_edmac_power_cont[ether_phy_access[channel]] [ETHER_CHANNEL_0] ) &&
+                    ( ETHER_MODULE_USE == etherc_edmac_power_cont[ether_phy_access[channel]] [ETHER_CHANNEL_1] )))
+    {
+        ret = power_on(ether_phy_access[channel]);
+    }
+
+    return ret;
+
+#endif
+} /* End of function power_on_control() */
+
+/***********************************************************************************************************************
+ * Function Name: power_off_control
+ * Description  : Powers off the channel if the ETHEC channel used and the PHY access channel are different, or if the 
+ *                PHY access channel is powered off.
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void power_off_control (uint32_t channel)
+{
+#if (ETHER_CHANNEL_MAX == 1)
+    etherc_edmac_power_cont[ether_phy_access[channel]][channel] = ETEHR_MODULE_NOT_USE;
+
+    power_off(channel);
+
+#elif (ETHER_CHANNEL_MAX == 2)
+    etherc_edmac_power_cont[ether_phy_access[channel]] [channel] = ETEHR_MODULE_NOT_USE;
+
+    if (channel != ether_phy_access[channel])
+    {
+        power_off(channel);
+    }
+
+    if (( ETEHR_MODULE_NOT_USE == etherc_edmac_power_cont[ether_phy_access[channel]] [ETHER_CHANNEL_0] ) &&
+            ( ETEHR_MODULE_NOT_USE == etherc_edmac_power_cont[ether_phy_access[channel]] [ETHER_CHANNEL_1] ))
+    {
+        power_off(ether_phy_access[channel]);
+    }
+#endif
+} /* End of function power_off_control() */
+
+/***********************************************************************************************************************
+ * Function Name: check_mpde_bit
+ * Description  : 
+ * Arguments    : none
+ * Return Value : 1: Magic Packet detection is enabled.
+ *                0: Magic Packet detection is disabled.
+ ***********************************************************************************************************************/
+static uint8_t check_mpde_bit (void)
+{
+#if (ETHER_CHANNEL_MAX == 1)
+    /* The MPDE bit can be referred to only when ETHERC operates. */
+    if ((ETHER_MODULE_USE == etherc_edmac_power_cont[ETHER_PHY_ACCESS_CHANNEL_0][ETHER_CHANNEL_0])
+            && (1 == ETHERC0.ECMR.BIT.MPDE))
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
+#elif (ETHER_CHANNEL_MAX == 2)
+    /* The MPDE bit can be referred to only when ETHERC0 operates. */
+    if ( ( ((ETHER_MODULE_USE == etherc_edmac_power_cont[ETHER_PHY_ACCESS_CHANNEL_0] [ETHER_CHANNEL_0])
+                            || (ETHER_MODULE_USE == etherc_edmac_power_cont[ETHER_PHY_ACCESS_CHANNEL_1] [ETHER_CHANNEL_0]))
+                    && (1 == ETHERC0.ECMR.BIT.MPDE)
+            )
+
+            /* The MPDE bit can be referred to only when ETHERC1 operates. */
+            || ( ((ETHER_MODULE_USE == etherc_edmac_power_cont[ETHER_PHY_ACCESS_CHANNEL_0] [ETHER_CHANNEL_1])
+                            || (ETHER_MODULE_USE == etherc_edmac_power_cont[ETHER_PHY_ACCESS_CHANNEL_1] [ETHER_CHANNEL_1]))
+                    && (1 == ETHERC1.ECMR.BIT.MPDE)
+            )
+    )
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
+#endif
+} /* End of function check_mpde_bit() */
+
+#if (defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX72M) || \
+       defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N))
+/***********************************************************************************************************************
+ * Function Name: ether_eint0
+ * Description  : EINT0 interrupt processing (A callback function to be called from r_bsp.)
+ * Arguments    : pparam -
+ *                    unused
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void ether_eint0 (void * pparam)
+{
+    volatile uint32_t dummy;
+
+    ether_int_common(ETHER_CHANNEL_0);
+
+    dummy = (uint32_t) pparam;
+} /* End of function ether_eint0() */
+#endif
+
+#if (defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N))
+/***********************************************************************************************************************
+ * Function Name: ether_eint1
+ * Description  : EINT1 interrupt processing (A callback function to be called from r_bsp.)
+ * Arguments    : pparam -
+ *                    unused
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void ether_eint1(void * pparam)
+{
+    volatile uint32_t dummy;
+
+    ether_int_common(ETHER_CHANNEL_1);
+
+    dummy = (uint32_t)pparam;
+} /* End of function ether_eint1() */
+#endif
+
+/***********************************************************************************************************************
+ * Function Name: ether_int_common
+ * Description  : Interrupt handler for Ethernet receive and transmit interrupts.
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ * Return Value : none
+ ***********************************************************************************************************************/
+static void ether_int_common (uint32_t channel)
+{
+    uint32_t status_ecsr;
+    uint32_t status_eesr;
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc_adr;
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac_adr;
+    const ether_control_t * pether_ch;
+    uint32_t phy_access;
+    ether_cb_arg_t cb_arg;
+
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+    pedmac_adr = pether_ch[phy_access].pedmac;
+
+    status_ecsr = petherc_adr->ECSR.LONG;
+    status_eesr = pedmac_adr->EESR.LONG;
+
+    /* Callback : Interrupt handler */
+    if ((NULL != cb_func.pcb_int_hnd) && (FIT_NO_FUNC != cb_func.pcb_int_hnd))
+    {
+        cb_arg.channel = channel;
+        cb_arg.status_ecsr = status_ecsr;
+        cb_arg.status_eesr = status_eesr;
+        (*cb_func.pcb_int_hnd)((void *) &cb_arg);
+    }
+
+    /* When the ETHERC status interrupt is generated */
+    if (status_eesr & EMAC_ECI_INT)
+    {
+#if (ETHER_CFG_USE_LINKSTA == 1)
+        /* When the link signal change interrupt is generated */
+        if (EMAC_LCHNG_INT == (status_ecsr & EMAC_LCHNG_INT))
+        {
+            /* The state of the link signal is confirmed and Link Up/Down is judged. */
+            /* When becoming Link up */
+            if (ETHER_CFG_LINK_PRESENT == petherc_adr->PSR.BIT.LMON)
+            {
+                lchng_flag[channel] = ETHER_FLAG_ON_LINK_ON;
+            }
+
+            /* When Link becomes down */
+            else
+            {
+                lchng_flag[channel] = ETHER_FLAG_ON_LINK_OFF;
+            }
+        }
+#endif
+
+        /* When the Magic Packet detection interrupt is generated */
+        if (EMAC_MPD_INT == (status_ecsr & EMAC_MPD_INT))
+        {
+            mpd_flag[channel] = ETHER_FLAG_ON;
+        }
+
+        /*
+         * Because each bit of the ECSR register is cleared when one is written, 
+         * the value read from the register is written and the bit is cleared. 
+         */
+        /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */
+        petherc_adr->ECSR.LONG = status_ecsr;
+    }
+
+    /*
+     * Because each bit of the EESR register is cleared when one is written, 
+     * the value read from the register is written and the bit is cleared. 
+     */
+    pedmac_adr->EESR.LONG = status_eesr; /* Clear EDMAC status bits */
+
+    /* Whether it is a necessary code is confirmed. */
+
+} /* End of function ether_int_common() */
+
+/***********************************************************************************************************************
+ * Function Name: ether_receive_data_padding
+ * Description  : Save the receive data padding information.
+ * Arguments    : control -
+ *                    Receive data padding information
+ * Return Value : ETHER_SUCCESS -
+ *                    Processing completed successfully
+ *                ETHER_ERR_INVALID_ARG -
+ *                    Invalid argument
+ ***********************************************************************************************************************/
+static ether_return_t ether_receive_data_padding (ether_param_t const control)
+{
+    ether_recv_padding_t *  p_arg;
+    uint32_t                channel;
+    uint8_t                 position;
+    uint8_t                 size;
+
+    p_arg      = control.padding_param;
+    channel     = p_arg->channel;
+    position    = p_arg->position;
+    size        = p_arg->size;
+
+    if (ETHER_CHANNEL_MAX <= channel)
+    {
+        return ETHER_ERR_INVALID_ARG;    // ETHERC channel invalid
+    }
+
+    if (INSERT_POSITION_MAX < position )
+    {
+        return ETHER_ERR_INVALID_ARG;    // Insert position out the range
+    }
+
+    if (INSERT_SIZE_MAX < size )
+    {
+        return ETHER_ERR_INVALID_ARG;    // Insert size beyond the MAX size
+    }
+
+    /* save insert information */
+    padding_insert_position[channel] = position;
+    padding_insert_size[channel] = size;
+
+    return ETHER_SUCCESS;
+} /* End of function ether_receive_data_padding() */
+
+#if (ETHER_CFG_NON_BLOCKING == 1)
+/***********************************************************************************************************************
+ * Function Name: ether_set_pmgi_callback
+ * Description  : Set the callback function
+ * Arguments    : control -
+ *                    Callback function pointer.
+ *                    If you would rather poll for finish then please input FIT_NO_FUNC for this argument.
+ * Return Value : ETHER_SUCCESS
+ *                    Processing completed successfully
+ ***********************************************************************************************************************/
+static ether_return_t ether_set_pmgi_callback(ether_param_t const control)
+{
+    void (*pcb_func) (void *);
+
+    pcb_func = control.pmgi_callback.pcb_pmgi_hnd;
+
+    /* Check callback function pointer, of whether or NULL FIT_NO_FUNC */
+    if ((NULL != pcb_func) && (FIT_NO_FUNC != pcb_func))
+    {
+        cb_func.pcb_pmgi_hnd = pcb_func; /* Set the callback function */
+    }
+
+    return ETHER_SUCCESS;
+} /* End of function ether_set_pmgi_callback() */
+
+/***********************************************************************************************************************
+ * Function Name: get_pmgi_channel
+ * Description  : Calculate the PMGI channel number from used ETHERC channel
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ * Return Value : Used PMGI channel number
+ ***********************************************************************************************************************/
+static uint16_t get_pmgi_channel(uint32_t channel)
+{
+    uint16_t pmgi_channel;
+
+    if (ETHER_CHANNEL_0 == channel)
+    {
+        pmgi_channel = ETHER_CFG_CH0_PHY_ACCESS;
+    }
+    else
+    {
+        pmgi_channel = ETHER_CFG_CH1_PHY_ACCESS;
+    }
+
+    return pmgi_channel;
+} /* End of function get_pmgi_channel() */
+
+/***********************************************************************************************************************
+ * Function Name: set_ether_channel
+ * Description  : Save the ETHERC channel number
+ * Arguments    : channel -
+ *                    ETHERC channel number
+ * Return Value : None
+ ***********************************************************************************************************************/
+static void set_ether_channel(uint32_t channel)
+{
+    if (ETHER_CHANNEL_0 == channel)
+    {
+        g_phy_current_param[ETHER_CFG_CH0_PHY_ACCESS].ether_channel = channel;
+    }
+    else
+    {
+        g_phy_current_param[ETHER_CFG_CH1_PHY_ACCESS].ether_channel = channel;
+    }
+} /* End of function set_ether_channel() */
+
+#if (ETHER_CFG_CH0_PHY_ACCESS == 0) || (ETHER_CFG_CH1_PHY_ACCESS == 0)
+/******************************************************************************
+* Function Name:    ether_pmgi0i_isr
+* Description  :    PMGI0 complete ISR.
+*                   Each ISR calls a common function but passes its channel number.
+* Arguments    :    N/A
+* Return Value :    N/A
+******************************************************************************/
+R_BSP_PRAGMA_STATIC_INTERRUPT(ether_pmgi0i_isr, VECT_PMGI0_PMGI0I)
+R_BSP_ATTRIB_STATIC_INTERRUPT void ether_pmgi0i_isr(void)
+{
+    pmgi_cb_arg_t           cb_arg;
+    pmgi_mode_t             mode;
+    uint32_t                ether_channel;
+    pmgi_step_t             step;
+    pmgi_event_t            event;
+
+    mode            = g_phy_current_param[PMGI_CHANNEL_0].mode;
+    step            = g_phy_current_param[PMGI_CHANNEL_0].step;
+    ether_channel   = g_phy_current_param[PMGI_CHANNEL_0].ether_channel;
+
+    if (PmgiAccessFun_tbl[mode][step].p_func(ether_channel) != ETHER_SUCCESS)
+    {
+        g_phy_current_param[PMGI_CHANNEL_0].event = PMGI_ERROR;
+    }
+
+    event = g_phy_current_param[PMGI_CHANNEL_0].event;
+    if ((PMGI_COMPLETE == event) || (PMGI_ERROR == event))
+    {
+        R_BSP_SoftwareUnlock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[PMGI_CHANNEL_0].locked);
+        if ((NULL != cb_func.pcb_pmgi_hnd) && (FIT_NO_FUNC != cb_func.pcb_pmgi_hnd))
+        {
+            if (PMGI_COMPLETE == event)
+            {
+                cb_arg.event = PMGI_COMPLETE;
+                cb_arg.mode = g_phy_current_param[PMGI_CHANNEL_0].mode;
+            }
+            else
+            {
+                cb_arg.event = PMGI_ERROR;
+                cb_arg.mode = g_phy_current_param[PMGI_CHANNEL_0].mode;
+            }
+            cb_arg.channel = ether_channel;
+            cb_arg.reg_data = g_phy_current_param[PMGI_CHANNEL_0].read_data;
+            /* set PMGI parameters to default */
+            g_phy_current_param[PMGI_CHANNEL_0].event = PMGI_IDLE;
+            g_phy_current_param[PMGI_CHANNEL_0].mode = OPEN_ZC2;
+            g_phy_current_param[PMGI_CHANNEL_0].step = STEP0;
+            pmgi_close(PMGI_CHANNEL_0);
+            (*cb_func.pcb_pmgi_hnd)((void *)&cb_arg);
+        }
+    }
+    else
+    {
+
+    }
+} /* End of function ether_pmgi0i_isr() */
+#endif /* (ETHER_CFG_CH0_PHY_ACCESS == 0) || (ETHER_CFG_CH1_PHY_ACCESS == 0) */
+
+#if (PMGI_CHANNEL_MAX ==2)
+#if (ETHER_CFG_CH0_PHY_ACCESS == 1) || (ETHER_CFG_CH1_PHY_ACCESS == 1)
+/******************************************************************************
+* Function Name:    ether_pmgi1i_isr
+* Description  :    PMGI1 complete ISR.
+*                   Each ISR calls a common function but passes its channel number.
+* Arguments    :    N/A
+* Return Value :    N/A
+******************************************************************************/
+R_BSP_PRAGMA_STATIC_INTERRUPT(ether_pmgi1i_isr, VECT_PMGI1_PMGI1I)
+R_BSP_ATTRIB_STATIC_INTERRUPT void ether_pmgi1i_isr(void)
+{
+    pmgi_cb_arg_t           cb_arg;
+    pmgi_mode_t             mode;
+    uint32_t                ether_channel;
+    pmgi_step_t             step;
+    pmgi_event_t            event;
+
+    mode            = g_phy_current_param[PMGI_CHANNEL_1].mode;
+    step            = g_phy_current_param[PMGI_CHANNEL_1].step;
+    ether_channel   = g_phy_current_param[PMGI_CHANNEL_1].ether_channel;
+
+    if (PmgiAccessFun_tbl[mode][step].p_func(ether_channel) != ETHER_SUCCESS)
+    {
+        g_phy_current_param[PMGI_CHANNEL_1].event = PMGI_ERROR;
+    }
+
+    event = g_phy_current_param[PMGI_CHANNEL_1].event;
+    if ((PMGI_COMPLETE == event) || (PMGI_ERROR == event))
+    {
+        R_BSP_SoftwareUnlock((BSP_CFG_USER_LOCKING_TYPE * )&g_phy_current_param[PMGI_CHANNEL_1].locked);
+        if ((NULL != cb_func.pcb_pmgi_hnd) && (FIT_NO_FUNC != cb_func.pcb_pmgi_hnd))
+        {
+            if (PMGI_COMPLETE == event)
+            {
+                cb_arg.event = PMGI_COMPLETE;
+                cb_arg.mode = g_phy_current_param[PMGI_CHANNEL_1].mode;
+            }
+            else
+            {
+                cb_arg.event = PMGI_ERROR;
+                cb_arg.mode = g_phy_current_param[PMGI_CHANNEL_1].mode;
+            }
+            cb_arg.channel = ether_channel;
+            cb_arg.reg_data = g_phy_current_param[PMGI_CHANNEL_1].read_data;
+            /* set PMGI parameters to default */
+            g_phy_current_param[PMGI_CHANNEL_1].event = PMGI_IDLE;
+            g_phy_current_param[PMGI_CHANNEL_1].mode = OPEN_ZC2;
+            g_phy_current_param[PMGI_CHANNEL_1].step = STEP0;
+            pmgi_close(PMGI_CHANNEL_1);
+            (*cb_func.pcb_pmgi_hnd)((void *)&cb_arg);
+        }
+    }
+    else
+    {
+
+    }
+} /* End of function ether_pmgi1i_isr() */
+#endif /* (ETHER_CFG_CH0_PHY_ACCESS == 1) || (ETHER_CFG_CH1_PHY_ACCESS == 1) */
+#endif
+
+/******************************************************************************
+* Function Name:    pmgi_open_zc2_step0
+* Description  :    Processing after R_ETHER_Open_ZC2'step0 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_open_zc2_step0(uint32_t channel)
+{
+    ether_return_t  ret = ETHER_SUCCESS;
+    uint16_t        pmgi_channel;
+    uint16_t        reg = 0;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    /* set the current parameter of phy */
+    g_phy_current_param[pmgi_channel].step = STEP1;
+    g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+    g_phy_current_param[pmgi_channel].reset_counter = 0;
+
+    pmgi_access(channel, PHY_REG_CONTROL, reg, PMGI_READ);
+
+    return ret;
+} /* End of function pmgi_open_zc2_step0() */
+
+/******************************************************************************
+* Function Name:    pmgi_open_zc2_step1
+* Description  :    Processing after R_ETHER_Open_ZC2'step1 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_open_zc2_step1(uint32_t channel)
+{
+    ether_return_t          ret = ETHER_SUCCESS;
+    uint16_t                pmgi_channel;
+    uint16_t                reg;
+    uint16_t                data = 0;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    reg = pmgi_read_reg(pmgi_channel);
+    if (reg & PHY_CONTROL_RESET)
+    {
+        pmgi_access(channel, PHY_REG_CONTROL, data, PMGI_READ);
+
+        /* set the current parameter of phy */
+        g_phy_current_param[pmgi_channel].reset_counter ++;
+    }
+    else
+    {
+#if ETHER_CFG_USE_PHY_KSZ8041NL == 1
+        g_phy_current_param[pmgi_channel].step = STEP2;
+        g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+        pmgi_access(channel, PHY_REG_PHY_CONTROL_1, data, PMGI_READ);
+
+#elif ETHER_CFG_USE_PHY_KSZ8041NL == 0
+        g_phy_current_param[pmgi_channel].step = STEP4;
+        g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+        if (ETHER_FLAG_OFF == pause_frame_enable[channel])
+        {
+            local_advertise[channel] = ((((PHY_AN_ADVERTISEMENT_100F |
+            PHY_AN_ADVERTISEMENT_100H) |
+            PHY_AN_ADVERTISEMENT_10F) |
+            PHY_AN_ADVERTISEMENT_10H) |
+            PHY_AN_ADVERTISEMENT_SELECTOR);
+        }
+
+        /* When pause frame is used */
+        else
+        {
+            local_advertise[channel] = ((((((PHY_AN_ADVERTISEMENT_ASM_DIR |
+            PHY_AN_ADVERTISEMENT_PAUSE) |
+            PHY_AN_ADVERTISEMENT_100F) |
+            PHY_AN_ADVERTISEMENT_100H) |
+            PHY_AN_ADVERTISEMENT_10F) |
+            PHY_AN_ADVERTISEMENT_10H) |
+            PHY_AN_ADVERTISEMENT_SELECTOR);
+        }
+
+        pmgi_access(channel, PHY_REG_AN_ADVERTISEMENT, local_advertise[channel], PMGI_WRITE);
+
+#endif
+    }
+
+    if (g_phy_current_param[pmgi_channel].reset_counter >= ETHER_CFG_PHY_DELAY_RESET)
+    {
+        ret = ETHER_ERR_OTHER;
+    }
+
+    return ret;
+} /* End of function pmgi_open_zc2_step1() */
+
+#if ETHER_CFG_USE_PHY_KSZ8041NL == 1
+/******************************************************************************
+* Function Name:    pmgi_open_zc2_step2
+* Description  :    Processing after R_ETHER_Open_ZC2'step2 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_open_zc2_step2(uint32_t channel)
+{
+    ether_return_t          ret = ETHER_SUCCESS;
+    uint16_t                pmgi_channel;
+    uint16_t                reg;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    reg = pmgi_read_reg(pmgi_channel);
+    reg &= (~0x8000);
+    reg |= 0x4000;
+
+    /* set the current parameter of phy */
+    g_phy_current_param[pmgi_channel].step = STEP3;
+    g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+    pmgi_access(channel, PHY_REG_PHY_CONTROL_1, reg, PMGI_WRITE);
+
+    return ret;
+} /* End of function pmgi_open_zc2_step2() */
+
+/******************************************************************************
+* Function Name:    pmgi_open_zc2_step3
+* Description  :    Processing after R_ETHER_Open_ZC2'step3 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_open_zc2_step3(uint32_t channel)
+{
+    ether_return_t              ret = ETHER_SUCCESS;
+    uint16_t                    pmgi_channel;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    /* set the current parameter of phy */
+    g_phy_current_param[pmgi_channel].step = STEP4;
+    g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+    if (ETHER_FLAG_OFF == pause_frame_enable[channel])
+    {
+        local_advertise[channel] = ((((PHY_AN_ADVERTISEMENT_100F |
+        PHY_AN_ADVERTISEMENT_100H) |
+        PHY_AN_ADVERTISEMENT_10F) |
+        PHY_AN_ADVERTISEMENT_10H) |
+        PHY_AN_ADVERTISEMENT_SELECTOR);
+    }
+
+    /* When pause frame is used */
+    else
+    {
+        local_advertise[channel] = ((((((PHY_AN_ADVERTISEMENT_ASM_DIR |
+        PHY_AN_ADVERTISEMENT_PAUSE) |
+        PHY_AN_ADVERTISEMENT_100F) |
+        PHY_AN_ADVERTISEMENT_100H) |
+        PHY_AN_ADVERTISEMENT_10F) |
+        PHY_AN_ADVERTISEMENT_10H) |
+        PHY_AN_ADVERTISEMENT_SELECTOR);
+    }
+
+    pmgi_access(channel, PHY_REG_AN_ADVERTISEMENT, local_advertise[channel], PMGI_WRITE);
+
+    return ret;
+} /* End of function pmgi_open_zc2_step3() */
+
+#elif ETHER_CFG_USE_PHY_KSZ8041NL == 0
+static ether_return_t pmgi_open_zc2_step2(uint32_t channel)
+{
+    return ETHER_ERR_OTHER;
+}
+
+static ether_return_t pmgi_open_zc2_step3(uint32_t channel)
+{
+    return ETHER_ERR_OTHER;
+}
+#endif
+
+/******************************************************************************
+* Function Name:    pmgi_open_zc2_step4
+* Description  :    Processing after R_ETHER_Open_ZC2'step4 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_open_zc2_step4(uint32_t channel)
+{
+    ether_return_t          ret = ETHER_SUCCESS;
+    uint16_t                pmgi_channel;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    /* set the current parameter of phy */
+    g_phy_current_param[pmgi_channel].step = STEP5;
+    g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+    pmgi_access(channel, PHY_REG_CONTROL, (PHY_CONTROL_AN_ENABLE |
+            PHY_CONTROL_AN_RESTART), PMGI_WRITE);
+
+    return ret;
+} /* End of function pmgi_open_zc2_step4() */
+
+/******************************************************************************
+* Function Name:    pmgi_open_zc2_step5
+* Description  :    Processing after R_ETHER_Open_ZC2'step5 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_open_zc2_step5(uint32_t channel)
+{
+    ether_return_t          ret = ETHER_SUCCESS;
+    uint16_t                pmgi_channel;
+    uint16_t                data = 0;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    /* set the current parameter of phy */
+    g_phy_current_param[pmgi_channel].step = STEP6;
+    g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+    pmgi_access(channel, PHY_REG_AN_ADVERTISEMENT, data, PMGI_READ);
+
+    return ret;
+} /* End of function pmgi_open_zc2_step5() */
+
+/******************************************************************************
+* Function Name:    pmgi_open_zc2_step6
+* Description  :    Processing after R_ETHER_Open_ZC2'step6 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_open_zc2_step6(uint32_t channel)
+{
+    ether_return_t              ret = ETHER_SUCCESS;
+    uint16_t                    pmgi_channel;
+    uint16_t                    reg;
+    const ether_control_t *     pether_ch;
+    uint32_t                    phy_access;
+
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR *    petherc_adr;
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR *     pedmac_adr;
+
+    pmgi_channel = get_pmgi_channel(channel);
+    reg = pmgi_read_reg(pmgi_channel);
+
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+    pedmac_adr = pether_ch[phy_access].pedmac;
+
+
+    /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */
+    petherc_adr->ECSR.LONG = 0x00000037;
+
+    /* Clear all EDMAC status bits */
+    pedmac_adr->EESR.LONG = 0x47FF0F9F;
+
+#if (ETHER_CFG_USE_LINKSTA == 1)
+    /* Enable interrupts of interest only. */
+    petherc_adr->ECSIPR.BIT.LCHNGIP = 1;
+#endif
+
+    pedmac_adr->EESIPR.BIT.ECIIP = 1;
+
+    /* Set Ethernet interrupt level and enable */
+    ether_enable_icu(channel);
+
+    if (LINKPROCESS_OPEN_ZC2 == g_phy_current_param[pmgi_channel].mode)
+    {
+#if (ETHER_CFG_USE_LINKSTA == 0)
+        /* set the current parameter of phy */
+        g_phy_current_param[pmgi_channel].mode = LINKPROCESS_CHECKLINK_ZC0;
+        g_phy_current_param[pmgi_channel].step = STEP0;
+        g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+        pmgi_access(channel, PHY_REG_STATUS, reg, PMGI_READ);
+
+#elif (ETHER_CFG_USE_LINKSTA == 1)
+        if (ETHER_FLAG_ON_LINK_ON == lchng_flag[channel])
+        {
+            /* set the current parameter of phy */
+            g_phy_current_param[pmgi_channel].mode = LINKPROCESS_CHECKLINK_ZC1;
+            g_phy_current_param[pmgi_channel].step = STEP0;
+            g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+            pmgi_access(channel, PHY_REG_STATUS, reg, PMGI_READ);
+        }
+        else if (ETHER_FLAG_ON_LINK_OFF == lchng_flag[channel])
+        {
+            lchng_flag[channel] = ETHER_FLAG_OFF;
+            /* set the current parameter of phy */
+            g_phy_current_param[pmgi_channel].mode = LINKPROCESS_CHECKLINK_ZC2;
+            g_phy_current_param[pmgi_channel].step = STEP0;
+            g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+            pmgi_access(channel, PHY_REG_STATUS, reg, PMGI_READ);
+        }
+        else
+        {
+            g_phy_current_param[channel].mode = LINKPROCESS;
+            g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+        }
+#endif
+    }
+    else
+    {
+
+        /* PMGI access complete */
+        g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+        g_phy_current_param[pmgi_channel].read_data = reg;
+    }
+
+    return ret;
+} /* End of function pmgi_open_zc2_step6() */
+
+/******************************************************************************
+* Function Name:    pmgi_checklink_zc_step0
+* Description  :    Processing after R_ETHER_CHECKLINK_ZC'step0 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_checklink_zc_step0(uint32_t channel)
+{
+    ether_return_t      ret = ETHER_SUCCESS;
+    uint16_t            pmgi_channel;
+    uint16_t            reg = 0;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    /* set the current parameter of phy */
+    g_phy_current_param[pmgi_channel].step = STEP1;
+    g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+    pmgi_access(channel, PHY_REG_STATUS, reg, PMGI_READ);
+
+    return ret;
+} /* End of function pmgi_checklink_zc_step0() */
+
+/******************************************************************************
+* Function Name:    pmgi_checklink_zc_step1
+* Description  :    Processing after R_ETHER_CHECKLINK_ZC'step1 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_checklink_zc_step1(uint32_t channel)
+{
+    ether_return_t                                      ret = ETHER_SUCCESS;
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR *    petherc_adr;
+    const ether_control_t *                             pether_ch;
+    uint32_t                                            phy_access;
+    ether_cb_arg_t                                      cb_arg;
+    uint16_t                                            pmgi_channel;
+    uint16_t                                            reg;
+#if (ETHER_CFG_USE_LINKSTA == 0)
+    int16_t                                             link_status;
+#endif
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    if ((CHECKLINK_ZC == g_phy_current_param[pmgi_channel].mode))
+    {
+        reg = pmgi_read_reg(pmgi_channel);
+        if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP))
+        {
+            g_phy_current_param[pmgi_channel].read_data = reg;
+            g_phy_current_param[pmgi_channel].event = PMGI_ERROR;
+        }
+        else
+        {
+            /* set the current parameter of phy */
+            g_phy_current_param[pmgi_channel].read_data = reg;
+            g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+        }
+    }
+    else if (LINKPROCESS_CHECKLINK_ZC0 == g_phy_current_param[pmgi_channel].mode)
+    {
+#if (ETHER_CFG_USE_LINKSTA == 0)
+        reg = pmgi_read_reg(pmgi_channel);
+
+        if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP))
+        {
+         link_status = ETHER_ERR_OTHER;
+        }
+        else
+        {
+         link_status = ETHER_SUCCESS;
+        }
+
+        if (g_pre_link_stat[channel] != link_status)
+        {
+            if (ETHER_SUCCESS == (ether_return_t)link_status)
+            {
+                /* The state of the link status in PHY-LSI is confirmed and Link Up/Down is judged. */
+                /* When becoming Link up */
+                lchng_flag[channel] = ETHER_FLAG_ON_LINK_ON;
+            }
+            else
+            {
+                /* When becoming Link down */
+                lchng_flag[channel] = ETHER_FLAG_ON_LINK_OFF;
+            }
+        }
+        g_pre_link_stat[channel] = link_status;
+
+        if (ETHER_FLAG_ON_LINK_ON == lchng_flag[channel])
+        {
+            /*
+            * The status of the LINK signal became "link-up" even if PHY-LSI did not detect "link-up"
+            * after a reset. To avoid this wrong detection, processing in R_ETHER_LinkProcess has been modified to
+            * clear the flag after link-up is confirmed in R_ETHER_CheckLink_ZC.
+            */
+            lchng_flag[channel] = ETHER_FLAG_OFF;
+
+            /* Initialize the transmit and receive descriptor */
+            memset((void *)&rx_descriptors[channel], 0x00, sizeof(rx_descriptors[channel]));
+            memset((void *)&tx_descriptors[channel], 0x00, sizeof(tx_descriptors[channel]));
+
+            /* Initialize the Ether buffer */
+            memset(&ether_buffers[channel], 0x00, sizeof(ether_buffers[channel]));
+
+            transfer_enable_flag[channel] = ETHER_FLAG_ON;
+
+            /*
+            * ETHERC and EDMAC are set after ETHERC and EDMAC are reset in software
+            * and sending and receiving is permitted.
+            */
+            ether_configure_mac(channel, mac_addr_buf[channel], NO_USE_MAGIC_PACKET_DETECT);
+
+            /* set PMGI current parameter */
+            g_phy_current_param[pmgi_channel].mode = LINKPROCESS;
+            g_phy_current_param[pmgi_channel].step = STEP0;
+            g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+            /* PMGI access  */
+            pmgi_access(channel, PHY_REG_STATUS, reg, PMGI_READ);
+
+            return ret;
+        }
+        else if (ETHER_FLAG_ON_LINK_OFF == lchng_flag[channel])
+        {
+            pether_ch = g_eth_control_ch[channel].pether_control;
+            phy_access = g_eth_control_ch[channel].phy_access;
+            petherc_adr = pether_ch[phy_access].petherc;
+
+            /* Disable receive and transmit. */
+            petherc_adr->ECMR.BIT.RE = 0;
+            petherc_adr->ECMR.BIT.TE = 0;
+
+            transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+
+            if ((NULL != cb_func.pcb_func) && (FIT_NO_FUNC != cb_func.pcb_func))
+            {
+                cb_arg.channel = channel;
+                cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_OFF;
+                (*cb_func.pcb_func)((void *) &cb_arg);
+            }
+
+            /* PMGI access complete */
+            g_phy_current_param[pmgi_channel].mode = LINKPROCESS;
+            g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+            g_phy_current_param[pmgi_channel].mode = LINKPROCESS;
+            ret = ETHER_ERR_OTHER;
+            return ret;
+        }
+        else
+        {
+            g_phy_current_param[pmgi_channel].mode = LINKPROCESS;
+            g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+        }
+#elif (ETHER_CFG_USE_LINKSTA == 1)
+        ret = ETHER_ERR_OTHER;
+        g_phy_current_param[pmgi_channel].mode = LINKPROCESS;
+        return ret;
+#endif
+    }
+    else if (LINKPROCESS_CHECKLINK_ZC1 == g_phy_current_param[pmgi_channel].mode)
+    {
+#if (ETHER_CFG_USE_LINKSTA == 0)
+        ret = ETHER_ERR_OTHER;
+        g_phy_current_param[pmgi_channel].mode = LINKPROCESS;
+        return ret;
+#elif (ETHER_CFG_USE_LINKSTA == 1)
+        reg = pmgi_read_reg(pmgi_channel);
+
+        if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP))
+        {
+            R_BSP_NOP();
+
+            /* Link is down */
+            g_phy_current_param[pmgi_channel].mode = LINKPROCESS;
+            ret = ETHER_ERR_OTHER;
+            return ret;
+        }
+        else
+        {
+            /*
+             * The status of the LINK signal became "link-up" even if PHY-LSI did not detect "link-up"
+             * after a reset. To avoid this wrong detection, processing in R_ETHER_LinkProcess has been modified to
+             * clear the flag after link-up is confirmed in R_ETHER_CheckLink_ZC.
+             */
+            lchng_flag[channel] = ETHER_FLAG_OFF;
+
+            /* Initialize the transmit and receive descriptor */
+            memset((void *)&rx_descriptors[channel], 0x00, sizeof(rx_descriptors[channel]));
+            memset((void *)&tx_descriptors[channel], 0x00, sizeof(tx_descriptors[channel]));
+
+            /* Initialize the Ether buffer */
+            memset(&ether_buffers[channel], 0x00, sizeof(ether_buffers[channel]));
+
+            transfer_enable_flag[channel] = ETHER_FLAG_ON;
+
+            /*
+             * ETHERC and EDMAC are set after ETHERC and EDMAC are reset in software
+             * and sending and receiving is permitted.
+             */
+            ether_configure_mac(channel, mac_addr_buf[channel], NO_USE_MAGIC_PACKET_DETECT);
+
+            /* set PMGI current parameters */
+            g_phy_current_param[pmgi_channel].mode = LINKPROCESS;
+            g_phy_current_param[pmgi_channel].step = STEP0;
+            g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+            /* PMGI Read */
+
+            pmgi_access(channel, PHY_REG_STATUS, reg, PMGI_READ);
+
+            return ret;
+        }
+#endif /* (ETHER_CFG_USE_LINKSTA == 0) */
+    }
+    else if (LINKPROCESS_CHECKLINK_ZC2 == g_phy_current_param[pmgi_channel].mode)
+    {
+#if (ETHER_CFG_USE_LINKSTA == 1)
+        reg = pmgi_read_reg(pmgi_channel);
+
+        if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP))
+        {    /* Link is down */
+            pether_ch = g_eth_control_ch[channel].pether_control;
+            phy_access = g_eth_control_ch[channel].phy_access;
+            petherc_adr = pether_ch[phy_access].petherc;
+
+            /* Disable receive and transmit. */
+            petherc_adr->ECMR.BIT.RE = 0;
+            petherc_adr->ECMR.BIT.TE = 0;
+
+            transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+
+            if ((NULL != cb_func.pcb_func) && (FIT_NO_FUNC != cb_func.pcb_func))
+            {
+                cb_arg.channel = channel;
+                cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_OFF;
+                (*cb_func.pcb_func)((void *) &cb_arg);
+            }
+        }
+        else
+        {
+            R_BSP_NOP();
+        }
+
+        g_phy_current_param[pmgi_channel].mode = LINKPROCESS;
+        g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+        return ret;
+#elif (ETHER_CFG_USE_LINKSTA == 0)
+        g_phy_current_param[pmgi_channel].mode = LINKPROCESS;
+        ret = ETHER_ERR_OTHER;
+        return ret;
+#endif
+    }
+    else if (WAKEONLAN_CHECKLINK_ZC == g_phy_current_param[pmgi_channel].mode)
+    {
+        reg = pmgi_read_reg(pmgi_channel);
+        if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP))
+        {
+            g_phy_current_param[pmgi_channel].read_data = reg;
+            g_phy_current_param[pmgi_channel].mode = WAKEONLAN;
+            g_phy_current_param[pmgi_channel].event = PMGI_ERROR;
+        }
+        else
+        {
+            /* set the current parameter of phy */
+            g_phy_current_param[pmgi_channel].read_data = reg;
+            g_phy_current_param[pmgi_channel].mode = WAKEONLAN;
+            g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+        }
+    }
+    else
+    {
+        g_phy_current_param[pmgi_channel].mode = CHECKLINK_ZC;
+        g_phy_current_param[pmgi_channel].event = PMGI_ERROR;
+    }
+
+    return ret;
+} /* End of function pmgi_checklink_zc_step1() */
+
+/******************************************************************************
+* Function Name:    pmgi_linkprocess_step0
+* Description  :    Processing after R_ETHER_LinkProcess'step0 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_linkprocess_step0(uint32_t channel)
+{
+    ether_return_t      ret = ETHER_SUCCESS;
+    uint16_t            pmgi_channel;
+    uint16_t            reg = 0;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    /* set PMGI current parameter */
+    g_phy_current_param[pmgi_channel].step = STEP1;
+    g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+    pmgi_access(channel, PHY_REG_STATUS, reg, PMGI_READ);
+
+    return ret;
+} /* End of function pmgi_linkprocess_step0() */
+
+/******************************************************************************
+* Function Name:    pmgi_linkprocess_step1
+* Description  :    Processing after R_ETHER_LinkProcess'step1 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_linkprocess_step1(uint32_t channel)
+{
+    ether_return_t      ret = ETHER_SUCCESS;
+    uint16_t            pmgi_channel;
+    uint16_t            reg;
+    uint16_t            data = 0;
+
+    g_local_pause_bits[channel] = 0;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    reg = pmgi_read_reg(pmgi_channel);
+
+    if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP))
+    {
+        R_BSP_NOP();
+        ret = ETHER_ERR_OTHER;
+        return ret;
+    }
+    else
+    {
+        /* Establish local pause capability */
+        if (PHY_AN_ADVERTISEMENT_PAUSE == (local_advertise[channel] & PHY_AN_ADVERTISEMENT_PAUSE))
+        {
+            g_local_pause_bits[channel] |= (1 << 1);
+        }
+
+        if (PHY_AN_ADVERTISEMENT_ASM_DIR == (local_advertise[channel] & PHY_AN_ADVERTISEMENT_ASM_DIR))
+        {
+            g_local_pause_bits[channel] |= 1;
+        }
+
+        /* When the auto-negotiation isn't completed, return error */
+        if (PHY_STATUS_AN_COMPLETE != (reg & PHY_STATUS_AN_COMPLETE))
+        {
+            /* When PHY auto-negotiation is not completed */
+            transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+            lchng_flag[channel] = ETHER_FLAG_ON_LINK_ON;
+
+            ret= ETHER_ERR_OTHER;
+            return ret;
+        }
+        else
+        {
+            /* set the current parameter of phy */
+            g_phy_current_param[pmgi_channel].step = STEP2;
+            g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+            pmgi_access(channel, PHY_REG_AN_LINK_PARTNER, data, PMGI_READ);
+        }
+    }
+    return ret;
+} /* End of function pmgi_linkprocess_step1() */
+
+/******************************************************************************
+* Function Name:    pmgi_linkprocess_step2
+* Description  :    Processing after R_ETHER_LinkProcess'step2 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_linkprocess_step2(uint32_t channel)
+{
+    ether_return_t              ret = ETHER_SUCCESS;
+    uint16_t                    link_speed_duplex = 0;
+    uint16_t                    partner_pause_bits = 0;
+    uint16_t                    transmit_pause_set = 0;
+    uint16_t                    receive_pause_set = 0;
+    uint16_t                    full_duplex = 0;
+    uint16_t                    pmgi_channel;
+    uint16_t                    reg;
+    ether_cb_arg_t              cb_arg;
+
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR *    petherc_adr;
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR *     pedmac_adr;
+    const ether_control_t *                             pether_ch;
+    uint32_t                                            phy_access;
+
+    pmgi_channel = get_pmgi_channel(channel);
+    reg = pmgi_read_reg(pmgi_channel);
+
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+    pedmac_adr = pether_ch[phy_access].pedmac;
+
+    /* Establish partner pause capability */
+    if (PHY_AN_LINK_PARTNER_PAUSE == (reg & PHY_AN_LINK_PARTNER_PAUSE))
+    {
+        partner_pause_bits = (1 << 1);
+    }
+
+    if (PHY_AN_LINK_PARTNER_ASM_DIR == (reg & PHY_AN_LINK_PARTNER_ASM_DIR))
+    {
+        partner_pause_bits |= 1;
+    }
+
+    /* Establish the line speed and the duplex */
+    if (PHY_AN_LINK_PARTNER_10H == (reg & PHY_AN_LINK_PARTNER_10H))
+    {
+        link_speed_duplex = PHY_LINK_10H;
+    }
+
+    if (PHY_AN_LINK_PARTNER_10F == (reg & PHY_AN_LINK_PARTNER_10F))
+    {
+        link_speed_duplex = PHY_LINK_10F;
+    }
+    if (PHY_AN_LINK_PARTNER_100H == (reg & PHY_AN_LINK_PARTNER_100H))
+    {
+        link_speed_duplex = PHY_LINK_100H;
+    }
+
+    if (PHY_AN_LINK_PARTNER_100F == (reg & PHY_AN_LINK_PARTNER_100F))
+    {
+        link_speed_duplex = PHY_LINK_100F;
+    }
+
+    switch (link_speed_duplex)
+    {
+        /* Half duplex link */
+        case PHY_LINK_100H :
+            petherc_adr->ECMR.BIT.DM = 0;
+            petherc_adr->ECMR.BIT.RTM = 1;
+            ret = ETHER_SUCCESS;
+        break;
+
+        case PHY_LINK_10H :
+            petherc_adr->ECMR.BIT.DM = 0;
+            petherc_adr->ECMR.BIT.RTM = 0;
+            ret = ETHER_SUCCESS;
+        break;
+
+            /* Full duplex link */
+        case PHY_LINK_100F :
+            petherc_adr->ECMR.BIT.DM = 1;
+            petherc_adr->ECMR.BIT.RTM = 1;
+            full_duplex = 1;
+            ret = ETHER_SUCCESS;
+        break;
+
+        case PHY_LINK_10F :
+            petherc_adr->ECMR.BIT.DM = 1;
+            petherc_adr->ECMR.BIT.RTM = 0;
+            full_duplex = 1;
+            ret = ETHER_SUCCESS;
+        break;
+
+        default :
+            ret = ETHER_ERR_OTHER;
+        break;
+    }
+
+    if (ETHER_SUCCESS == ret)
+    {
+
+        /* When pause frame is used */
+        if ((full_duplex) && (ETHER_FLAG_ON == pause_frame_enable[channel]))
+        {
+            /* Set automatic PAUSE for 512 bit-time */
+            petherc_adr->APR.LONG = 0x0000FFFF;
+
+            /* Set unlimited retransmit of PAUSE frames */
+            petherc_adr->TPAUSER.LONG = 0;
+
+            /* PAUSE flow control FIFO settings. */
+            pedmac_adr->FCFTR.LONG = 0x00000000;
+
+            /* Control of a PAUSE frame whose TIME parameter value is 0 is enabled. */
+            petherc_adr->ECMR.BIT.ZPF = 1;
+
+            /**
+             * Enable PAUSE for full duplex link depending on
+             * the pause resolution results
+             */
+            ether_pause_resolution(g_local_pause_bits[channel], partner_pause_bits, &transmit_pause_set,
+                    &receive_pause_set);
+
+            if (XMIT_PAUSE_ON == transmit_pause_set)
+            {
+                /* Enable automatic PAUSE frame transmission */
+                petherc_adr->ECMR.BIT.TXF = 1;
+            }
+            else
+            {
+                /* Disable automatic PAUSE frame transmission */
+                petherc_adr->ECMR.BIT.TXF = 0;
+            }
+
+            if (RECV_PAUSE_ON == receive_pause_set)
+            {
+                /* Enable reception of PAUSE frames */
+                petherc_adr->ECMR.BIT.RXF = 1;
+            }
+            else
+            {
+                /* Disable reception of PAUSE frames */
+                petherc_adr->ECMR.BIT.RXF = 0;
+            }
+        }
+
+        /* When pause frame is not used */
+        else
+        {
+            /* Disable PAUSE for half duplex link */
+            petherc_adr->ECMR.BIT.TXF = 0;
+            petherc_adr->ECMR.BIT.RXF = 0;
+        }
+
+        /* Set the promiscuous mode bit */
+        petherc_adr->ECMR.BIT.PRM = promiscuous_mode[channel];
+
+        /* Enable receive and transmit. */
+        petherc_adr->ECMR.BIT.RE = 1;
+        petherc_adr->ECMR.BIT.TE = 1;
+
+        /* Enable EDMAC receive */
+        pedmac_adr->EDRRR.LONG = 0x1;
+
+        if ((NULL != cb_func.pcb_func) && (FIT_NO_FUNC != cb_func.pcb_func))
+        {
+            cb_arg.channel = channel;
+            cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_ON;
+            (*cb_func.pcb_func)((void *) &cb_arg);
+        }
+
+        g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+    }
+    else
+    {
+        /* When PHY auto-negotiation is not completed */
+        transfer_enable_flag[channel] = ETHER_FLAG_OFF;
+        lchng_flag[channel] = ETHER_FLAG_ON_LINK_ON;
+
+        g_phy_current_param[pmgi_channel].event = PMGI_ERROR;
+    }
+
+    /* set the current parameter of phy */
+
+    return ret;
+} /* End of function pmgi_linkprocess_step2() */
+
+/******************************************************************************
+* Function Name:    pmgi_wakeonlan_step0
+* Description  :    Processing after R_ETHER_WakeOnLAN'step0 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_wakeonlan_step0(uint32_t channel)
+{
+    ether_return_t      ret = ETHER_SUCCESS;
+    uint16_t            pmgi_channel;
+    uint16_t            reg = 0;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    /* set the current parameter of phy */
+    g_phy_current_param[pmgi_channel].step = STEP1;
+    g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+    pmgi_access(channel, PHY_REG_STATUS, reg, PMGI_READ);
+
+    return ret;
+} /* End of function pmgi_wakeonlan_step0() */
+
+/******************************************************************************
+* Function Name:    pmgi_wakeonlan_step1
+* Description  :    Processing after R_ETHER_WakeOnLAN'step1 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_wakeonlan_step1(uint32_t channel)
+{
+    ether_return_t      ret = ETHER_SUCCESS;
+    uint16_t            pmgi_channel;
+    uint16_t            reg;
+    uint16_t            data = 0;
+
+    g_local_pause_bits[channel] = 0;
+
+    pmgi_channel = get_pmgi_channel(channel);
+
+    reg = pmgi_read_reg(pmgi_channel);
+
+    if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP))
+    {
+        R_BSP_NOP();
+        ret = ETHER_ERR_OTHER;
+    }
+    else
+    {
+        /* Establish local pause capability */
+        if (PHY_AN_ADVERTISEMENT_PAUSE == (local_advertise[channel] & PHY_AN_ADVERTISEMENT_PAUSE))
+        {
+            g_local_pause_bits[channel] |= (1 << 1);
+        }
+
+        if (PHY_AN_ADVERTISEMENT_ASM_DIR == (local_advertise[channel] & PHY_AN_ADVERTISEMENT_ASM_DIR))
+        {
+            g_local_pause_bits[channel] |= 1;
+        }
+
+        /* When the auto-negotiation isn't completed, return error */
+        if (PHY_STATUS_AN_COMPLETE != (reg & PHY_STATUS_AN_COMPLETE))
+        {
+            ret= ETHER_ERR_OTHER;
+        }
+        else
+        {
+            /* set the current parameter of phy */
+            g_phy_current_param[pmgi_channel].step = STEP2;
+            g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+            pmgi_access(channel, PHY_REG_AN_LINK_PARTNER, data, PMGI_READ);
+        }
+    }
+    return ret;
+} /* End of function pmgi_wakeonlan_step1() */
+
+/******************************************************************************
+* Function Name:    pmgi_wakeonlan_step2
+* Description  :    Processing after R_ETHER_WakeOnLAN'step2 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI one step processing successful
+*                   ETHER_ERR_OTHER
+*                       Other error
+******************************************************************************/
+static ether_return_t pmgi_wakeonlan_step2(uint32_t channel)
+{
+    ether_return_t              ret = ETHER_SUCCESS;
+    uint16_t                    link_speed_duplex = 0;
+    uint16_t                    pmgi_channel;
+    uint16_t                    reg;
+
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR *    petherc_adr;
+    const ether_control_t *                             pether_ch;
+    uint32_t                                            phy_access;
+
+    pmgi_channel = get_pmgi_channel(channel);
+    reg = pmgi_read_reg(pmgi_channel);
+
+    pether_ch = g_eth_control_ch[channel].pether_control;
+    phy_access = g_eth_control_ch[channel].phy_access;
+    petherc_adr = pether_ch[phy_access].petherc;
+
+    /* Establish the line speed and the duplex */
+    if (PHY_AN_LINK_PARTNER_10H == (reg & PHY_AN_LINK_PARTNER_10H))
+    {
+        link_speed_duplex = PHY_LINK_10H;
+    }
+
+    if (PHY_AN_LINK_PARTNER_10F == (reg & PHY_AN_LINK_PARTNER_10F))
+    {
+        link_speed_duplex = PHY_LINK_10F;
+    }
+    if (PHY_AN_LINK_PARTNER_100H == (reg & PHY_AN_LINK_PARTNER_100H))
+    {
+        link_speed_duplex = PHY_LINK_100H;
+    }
+
+    if (PHY_AN_LINK_PARTNER_100F == (reg & PHY_AN_LINK_PARTNER_100F))
+    {
+        link_speed_duplex = PHY_LINK_100F;
+    }
+
+    switch (link_speed_duplex)
+    {
+        /* Half duplex link */
+        case PHY_LINK_100H :
+            petherc_adr->ECMR.BIT.DM = 0;
+            petherc_adr->ECMR.BIT.RTM = 1;
+            ret = ETHER_SUCCESS;
+        break;
+
+        case PHY_LINK_10H :
+            petherc_adr->ECMR.BIT.DM = 0;
+            petherc_adr->ECMR.BIT.RTM = 0;
+            ret = ETHER_SUCCESS;
+        break;
+
+            /* Full duplex link */
+        case PHY_LINK_100F :
+            petherc_adr->ECMR.BIT.DM = 1;
+            petherc_adr->ECMR.BIT.RTM = 1;
+            ret = ETHER_SUCCESS;
+        break;
+
+        case PHY_LINK_10F :
+            petherc_adr->ECMR.BIT.DM = 1;
+            petherc_adr->ECMR.BIT.RTM = 0;
+            ret = ETHER_SUCCESS;
+        break;
+
+        default :
+            ret = ETHER_ERR_OTHER;
+        break;
+    }
+
+    if (ETHER_SUCCESS == ret)
+    {
+
+        /* The magic packet detection is permitted. */
+        petherc_adr->ECMR.BIT.MPDE = 1;
+
+        /* Because data is not transmitted for the magic packet detection waiting,
+         only the reception is permitted. */
+        petherc_adr->ECMR.BIT.RE = 1;
+
+        /*
+         * The reception function of EDMAC keep invalidity
+         * because the receive data don't need to be read when the magic packet detection mode.
+         */
+#if (ETHER_CFG_USE_LINKSTA == 1)
+        pether_ch = g_eth_control_ch[channel].pether_control;
+        phy_access = g_eth_control_ch[channel].phy_access;
+        petherc_adr = pether_ch[phy_access].petherc;
+
+        /* It is confirmed not to become Link down while changing the setting. */
+        if (ETHER_CFG_LINK_PRESENT == petherc_adr->PSR.BIT.LMON)
+        {
+            ret = ETHER_SUCCESS;
+            g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+        }
+        else
+        {
+            ret = ETHER_ERR_OTHER;
+            g_phy_current_param[pmgi_channel].event = PMGI_ERROR;
+        }
+#elif (ETHER_CFG_USE_LINKSTA == 0)
+        /* set the current parameter of phy */
+        g_phy_current_param[pmgi_channel].mode = WAKEONLAN_CHECKLINK_ZC;
+        g_phy_current_param[pmgi_channel].step = STEP0;
+        g_phy_current_param[pmgi_channel].event = PMGI_RUNNING;
+
+        pmgi_access(channel, PHY_REG_STATUS, reg, PMGI_READ);
+#endif
+    }
+    else
+    {
+        g_phy_current_param[pmgi_channel].event = PMGI_ERROR;
+    }
+
+    return ret;
+} /* End of function pmgi_wakeonlan_step2() */
+
+/******************************************************************************
+* Function Name:    pmgi_writephy_step0
+* Description  :    Processing after R_ETHER_WritePHY'step0 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI operate successfully
+******************************************************************************/
+static ether_return_t pmgi_writephy_step0(uint32_t channel)
+{
+    ether_return_t      ret = ETHER_SUCCESS;
+    uint16_t            pmgi_channel;
+
+    /* set the current parameter of phy */
+    pmgi_channel = get_pmgi_channel(channel);
+    g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+
+    return ret;
+} /* End of function pmgi_writephy_step0() */
+
+/******************************************************************************
+* Function Name:    pmgi_readphy_step0
+* Description  :    Processing after R_ETHER_ReadPHY'step0 is completed.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_SUCCESS
+*                       PMGI operate successfully
+******************************************************************************/
+static ether_return_t pmgi_readphy_step0(uint32_t channel)
+{
+    ether_return_t      ret = ETHER_SUCCESS;
+    uint16_t pmgi_channel;
+    uint16_t reg_data;
+
+    /* get the PMGI channel */
+    pmgi_channel = get_pmgi_channel(channel);
+
+    /* read the PMGI register */
+    reg_data = pmgi_read_reg(pmgi_channel);
+
+    /* set the current parameter of phy */
+    g_phy_current_param[pmgi_channel].read_data = reg_data;
+    g_phy_current_param[pmgi_channel].event = PMGI_COMPLETE;
+
+    return ret;
+} /* End of function pmgi_readphy_step0() */
+
+/******************************************************************************
+* Function Name:    pmgi_modestep_invalid
+* Description  :    When the parameters of PMGI interrupt process function pointer array
+*                   is error, return ETHER_ERR_INVALID_ARG.
+* Arguments    :    channel -
+*                       ETHERC channel number
+* Return Value :    ETHER_ERR_INVALID_ARG
+*                       The paramters of PMGI interrupt processing function pointer array
+*                       is error.
+******************************************************************************/
+static ether_return_t pmgi_modestep_invalid(uint32_t channel)
+{
+    return ETHER_ERR_INVALID_ARG;
+} /* End of function pmgi_modestep_invalid() */
+#endif /* (ETHER_CFG_NON_BLOCKING == 1) */
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/r_ether_rx_private.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/r_ether_rx_private.h
new file mode 100644
index 00000000..51206f51
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/r_ether_rx_private.h
@@ -0,0 +1,339 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+ * applicable laws, including copyright laws. 
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+ * following link:
+ * http://www.renesas.com/disclaimer 
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.    
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name    : r_ether_rx_private.h
+ * Version      : 1.20
+ * Device       : RX63N/RX65N/RX64M/RX71M/RX72M/RX72N
+ * Tool-Chain   : RX Family C Compiler
+ * H/W Platform : 
+ * Description  : File that defines macro and structure seen only in "r_ether_rx.c" file.
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 22.07.2014 1.00     First Release
+ *         : 16.12.2014 1.01     Added changes for RX71M.
+ *         : 29.01.2015 1.02     Correction of version check.
+ *         : 31.03.2016 1.03     Added changes for RX63N.
+ *         : 01.10.2016 1.04     Added changes for RX65N.
+ *         : 01.10.2017 1.13     Removed BSP version error.
+ *         : 08.01.2018 1.14     Changed setting value check.
+ *         : 20.05.2019 1.16     Added support for GNUC and ICCRX.
+ *                               Fixed coding style.
+ *         : 30.07.2019 1.17     Added changes for RX72M.
+ *         : 22.11.2019 1.20     Added changes for RX72N.
+ *         :                     Added changes for RX66N.
+ *         :                     Deleted support for RX63N.
+  ***********************************************************************************************************************/
+
+/* Guards against multiple inclusion */
+#ifndef R_ETHER_PRIVATE_H
+    #define R_ETHER_PRIVATE_H
+
+/* This checks that the module of the Ethernet is supported to the MCU that has been selected for sure. */
+    #if (defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX72M) || \
+         defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N))
+
+    #else
+        #error "This MCU is not supported by the current r_ether_rx module."
+    #endif
+
+/***********************************************************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+    #include "r_ether_rx_if.h"
+    #include "r_ether_rx_config.h"
+
+/***********************************************************************************************************************
+ Macro definitions
+ ***********************************************************************************************************************/
+
+/* Check the setting values is valid. Please review the setting values in r_ether_rx_config.h if error message is output */
+    #if !((ETHER_CFG_MODE_SEL == 0) || (ETHER_CFG_MODE_SEL == 1))
+        #error "ERROR- ETHER_CFG_MODE_SEL - Ethernet interface select is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_CH0_PHY_ADDRESS >= 0) && (ETHER_CFG_CH0_PHY_ADDRESS <= 31))
+        #error "ERROR- ETHER_CFG_CH0_PHY_ADDRESS - PHY-LSI address is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_CH1_PHY_ADDRESS >= 0) && (ETHER_CFG_CH1_PHY_ADDRESS <= 31))
+        #error "ERROR- ETHER_CFG_CH1_PHY_ADDRESS - PHY-LSI address is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !(ETHER_CFG_EMAC_RX_DESCRIPTORS >= 1)
+        #error "ERROR- ETHER_CFG_EMAC_RX_DESCRIPTORS - Transmission descriptors is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !(ETHER_CFG_EMAC_TX_DESCRIPTORS >= 1)
+        #error "ERROR- ETHER_CFG_EMAC_TX_DESCRIPTORS - Receive descriptors is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_BUFSIZE % 32) == 0)
+        #error "ERROR- ETHER_CFG_BUFSIZE - transmission and receive buffers is not 32-byte aligned in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_CH0_PHY_ACCESS == 0) || (ETHER_CFG_CH0_PHY_ACCESS == 1))
+        #error "ERROR- ETHER_CFG_CH0_PHY_ACCESS - PHY-LSI access channel is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_CH1_PHY_ACCESS == 0) || (ETHER_CFG_CH1_PHY_ACCESS == 1))
+        #error "ERROR- ETHER_CFG_CH1_PHY_ACCESS - PHY-LSI access channel is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !(ETHER_CFG_PHY_MII_WAIT >= 1)
+        #error "ERROR- ETHER_CFG_PHY_MII_WAIT - PHY-LSI access timing is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_LINK_PRESENT == 0) || (ETHER_CFG_LINK_PRESENT == 1))
+        #error "ERROR- ETHER_CFG_LINK_PRESENT - Link signal polarity of PHY-LSI is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_USE_LINKSTA == 0) || (ETHER_CFG_USE_LINKSTA == 1))
+        #error "ERROR- ETHER_CFG_USE_LINKSTA - Use LINKSTA select is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_USE_PHY_KSZ8041NL == 0) || (ETHER_CFG_USE_PHY_KSZ8041NL == 1))
+        #error "ERROR- ETHER_CFG_USE_PHY_KSZ8041NL - use KSZ8041NL is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_NON_BLOCKING == 0) || (ETHER_CFG_NON_BLOCKING == 1))
+        #error "ERROR- ETHER_CFG_NON_BLOCKING - Use Non-Blocking select is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_PMGI_CLOCK >= 97657) && (ETHER_CFG_PMGI_CLOCK <= 60000000) )
+        #error "ERROR- ETHER_CFG_PMGI_CLOCK - PMGI's MDC clock is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_PMGI_ENABLE_PREAMBLE == 0) || (ETHER_CFG_PMGI_ENABLE_PREAMBLE == 1))
+        #error "ERROR- ETHER_CFG_PMGI_ENABLE_PREAMBLE - Preamble Control select is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_PMGI_HOLD_TIME >= 0) && (ETHER_CFG_PMGI_HOLD_TIME <= 7) )
+        #error "ERROR- ETHER_CFG_PMGI_HOLD_TIME - Hold Time Adjustment select is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_PMGI_CAPTURE_TIME >= 0) && (ETHER_CFG_PMGI_CAPTURE_TIME <= 7) )
+        #error "ERROR- ETHER_CFG_PMGI_CAPTURE_TIME - Capture Time Adjustment select is out of range defined in r_ether_rx_config.h."
+    #endif
+
+    #if !((ETHER_CFG_PMGI_INT_PRIORTY >= 0) && (ETHER_CFG_PMGI_INT_PRIORTY <= 15) )
+        #error "ERROR- ETHER_CFG_PMGI_INT_PRIORTY - PMGI interrupt priority level select is out of range defined in r_ether_rx_config.h."
+    #endif
+/*
+ * The total number of EMAC buffers to allocate. The number of
+ * total buffers is simply the sum of the number of transmit and
+ * receive buffers.
+ */
+    #define EMAC_NUM_BUFFERS            (ETHER_CFG_EMAC_RX_DESCRIPTORS + (ETHER_CFG_EMAC_TX_DESCRIPTORS))
+
+/* Definition of the maximum / minimum number of data that can be sent at one time in the Ethernet */
+    #define ETHER_BUFSIZE_MAX           (1514)          /* Maximum number of transmitted data */
+    #define ETHER_BUFSIZE_MIN           (60)            /* Minimum number of transmitted data */
+
+/* Bit definition of interrupt factor of Ethernet interrupt */
+    #define EMAC_LCHNG_INT      (1UL << 2)
+    #define EMAC_MPD_INT        (1UL << 1)
+
+    #define EMAC_RFCOF_INT      (1UL << 24)
+    #define EMAC_ECI_INT        (1UL << 22)
+    #define EMAC_TC_INT         (1UL << 21)
+    #define EMAC_FR_INT         (1UL << 18)
+    #define EMAC_RDE_INT        (1UL << 17)
+    #define EMAC_RFOF_INT       (1UL << 16)
+
+/* Bit definitions of status member of DescriptorS */
+    #define  TACT               (0x80000000)
+    #define  RACT               (0x80000000)
+    #define  TDLE               (0x40000000)
+    #define  RDLE               (0x40000000)
+    #define  TFP1               (0x20000000)
+    #define  RFP1               (0x20000000)
+    #define  TFP0               (0x10000000)
+    #define  RFP0               (0x10000000)
+    #define  TFE                (0x08000000)
+    #define  RFE                (0x08000000)
+
+    #define  RFS9_RFOVER        (0x00000200)
+    #define  RFS8_RAD           (0x00000100)
+    #define  RFS7_RMAF          (0x00000080)
+    #define  RFS4_RRF           (0x00000010)
+    #define  RFS3_RTLF          (0x00000008)
+    #define  RFS2_RTSF          (0x00000004)
+    #define  RFS1_PRE           (0x00000002)
+    #define  RFS0_CERF          (0x00000001)
+
+    #define  TWBI               (0x04000000)
+    #define  TFS8_TAD           (0x00000100)
+    #define  TFS3_CND           (0x00000008)
+    #define  TFS2_DLC           (0x00000004)
+    #define  TFS1_CD            (0x00000002)
+    #define  TFS0_TRO           (0x00000001)
+
+/* Number of entries in PAUSE resolution table */
+    #define PAUSE_TABLE_ENTRIES (8)
+
+/* Local device and link partner PAUSE settings */
+    #define XMIT_PAUSE_OFF      (0) /* The pause frame transmission is prohibited. */
+    #define RECV_PAUSE_OFF      (0) /* The pause frame reception is prohibited.    */
+    #define XMIT_PAUSE_ON       (1) /* The pause frame transmission is permitted.  */
+    #define RECV_PAUSE_ON       (1) /* The pause frame reception is permitted.     */
+
+/* PAUSE link mask and shift values */
+/*
+ * The mask value and shift value which are for that shift the bits form a line and 
+ * for comparing the bit information of PAUSE function which support the local device and 
+ * Link partner with the assorted table(pause_resolution) which enable or disable the PAUSE frame. 
+ */
+    #define LINK_RES_ABILITY_MASK           (3)
+    #define LINK_RES_LOCAL_ABILITY_BITSHIFT (2)
+
+/* Etherc mode */
+    #define NO_USE_MAGIC_PACKET_DETECT  (0)
+    #define USE_MAGIC_PACKET_DETECT     (1)
+
+/* Defines the port connection to be used in the Ether */
+    #define PORT_CONNECT_ET0            (0x01)
+    #define PORT_CONNECT_ET1            (0x02)
+    #define PORT_CONNECT_ET0_ET1        (0x03)
+
+/** PHY access channel */
+    #define ETHER_PHY_ACCESS_CHANNEL_0      (0)
+    #define ETHER_PHY_ACCESS_CHANNEL_1      (1)
+    #define ETHER_PHY_ACCESS_CHANNEL_MAX    (ETHER_CHANNEL_MAX)
+
+/** Ethernet module usage status */
+    #define ETEHR_MODULE_NOT_USE    (0) /* Ethernet module is not used */
+    #define ETHER_MODULE_USE        (1) /* Ethernet module is used */
+
+/***********************************************************************************************************************
+ Typedef definitions
+ ***********************************************************************************************************************/
+/*
+ * EDMAC descriptor as defined in the hardware manual. It is
+ * modified to support little endian CPU mode.
+ */
+R_BSP_PRAGMA_PACK;
+typedef struct DescriptorS
+{
+    R_BSP_EVENACCESS uint32_t           status;
+    #if __LIT
+    /* Little endian */
+    R_BSP_EVENACCESS uint16_t           size;
+    R_BSP_EVENACCESS uint16_t           bufsize;
+    #else
+    /* Big endian */
+    R_BSP_EVENACCESS uint16_t bufsize;
+    R_BSP_EVENACCESS uint16_t size;
+
+    #endif
+    uint8_t            *buf_p;
+    struct DescriptorS *next;
+} descriptor_t;
+
+/*
+ * Ethernet buffer type definition.  
+ */
+typedef struct EtherBufferS
+{
+    uint8_t buffer[EMAC_NUM_BUFFERS][ETHER_CFG_BUFSIZE];
+
+} etherbuffer_t;
+
+/*
+ * PauseMaskE, PauseValE and pause_resolutionS are use to create
+ * PAUSE resolution Table 28B-3 in IEEE 802.3-2008 standard.
+ */
+typedef enum PauseMaskE
+{
+    PAUSE_MASK0,
+    PAUSE_MASK1,
+    PAUSE_MASK2,
+    PAUSE_MASK3,
+    PAUSE_MASK4,
+    PAUSE_MASK5,
+    PAUSE_MASK6,
+    PAUSE_MASK7,
+    PAUSE_MASK8,
+    PAUSE_MASK9,
+    PAUSE_MASKA,
+    PAUSE_MASKB,
+    PAUSE_MASKC,
+    PAUSE_MASKD,
+    PAUSE_MASKE,
+    PAUSE_MASKF
+} pausemask_t;
+
+typedef enum PauseValE
+{
+    PAUSE_VAL0,
+    PAUSE_VAL1,
+    PAUSE_VAL2,
+    PAUSE_VAL3,
+    PAUSE_VAL4,
+    PAUSE_VAL5,
+    PAUSE_VAL6,
+    PAUSE_VAL7,
+    PAUSE_VAL8,
+    PAUSE_VAL9,
+    PAUSE_VALA,
+    PAUSE_VALB,
+    PAUSE_VALC,
+    PAUSE_VALD,
+    PAUSE_VALE,
+    PAUSE_VALF
+} pauseval_t;
+
+typedef struct pause_resolutionS
+{
+    pausemask_t mask;
+    pauseval_t  value;
+    uint8_t     transmit;
+    uint8_t     receive;
+} pauseresolution_t;
+
+typedef struct
+{
+    volatile struct st_etherc R_BSP_EVENACCESS_SFR * petherc; /* ETHERC module */
+    volatile struct st_edmac R_BSP_EVENACCESS_SFR * pedmac; /* EDMAC */
+    volatile uint32_t         R_BSP_EVENACCESS_SFR * preg_pir;
+    uint32_t                  phy_address;
+    uint8_t                   port_connect;
+} ether_control_t;
+
+typedef struct
+{
+    const ether_control_t * pether_control;
+    uint32_t              phy_access;
+} ether_ch_control_t;
+
+R_BSP_PRAGMA_PACKOPTION;
+
+/***********************************************************************************************************************
+ Exported global variables
+ ***********************************************************************************************************************/
+extern const ether_ch_control_t g_eth_control_ch[];
+
+/***********************************************************************************************************************
+ Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+void ether_enable_icu (uint32_t channel);
+void ether_disable_icu (uint32_t channel);
+void ether_set_phy_mode (uint8_t connect);
+
+#endif /* R_ETHER_PRIVATE_H */
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/targets/rx65n/r_ether_setting_rx65n.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/targets/rx65n/r_ether_setting_rx65n.c
new file mode 100644
index 00000000..d895aa94
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_ether_rx/src/targets/rx65n/r_ether_setting_rx65n.c
@@ -0,0 +1,147 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No 
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all 
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, 
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM 
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES 
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS 
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of 
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer 
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.    
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_ether_setting_rx65n.c
+* Version      : 1.20
+* Device       : RX65N
+* Description  : Ethernet module device driver
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 01.10.2016 1.00     First Release
+*         : 01.10.2017 1.13     Removed ether_clear_icu_source function.
+*         :                     Added RX65N-2MB support.
+*         : 22.11.2019 1.20     Added support for atomic control. 
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+#include "r_ether_rx_if.h"
+#include "src/r_ether_rx_private.h"
+
+#if defined(BSP_MCU_RX65N)
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+/* Check the setting values is valid. Please review the setting values in r_ether_rx_config.h if error message is output */
+    #if !((ETHER_CFG_AL1_INT_PRIORTY >= 1) && (ETHER_CFG_AL1_INT_PRIORTY <= 15))
+        #error "ERROR- ETHER_CFG_AL1_INT_PRIORTY - Interrupt priority level is out of range defined in r_ether_rx_config.h."
+    #endif
+
+/***********************************************************************************************************************
+* Function Name: ether_enable_icu
+* Description  :
+* Arguments    : channel -
+*                    Ethernet channel number
+* Return Value : none
+***********************************************************************************************************************/
+void ether_enable_icu(uint32_t channel)
+{
+    volatile uint32_t   dummy;
+    bsp_int_ctrl_t int_ctrl;
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    bsp_int_ctrl_t    ipl_value;
+#endif
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &ipl_value);
+#endif
+    ICU.GENAL1.BIT.EN4 = 1;
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &ipl_value);
+#endif
+    int_ctrl.ipl = ETHER_CFG_AL1_INT_PRIORTY;
+    R_BSP_InterruptControl(BSP_INT_SRC_AL1_EDMAC0_EINT0, BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, &int_ctrl);
+
+    dummy = channel;
+} /* End of function ether_enable_icu() */
+
+/***********************************************************************************************************************
+* Function Name: ether_disable_icu
+* Description  :
+* Arguments    : channel -
+*                    Ethernet channel number
+* Return Value : none
+***********************************************************************************************************************/
+void ether_disable_icu(uint32_t channel)
+{
+    volatile uint32_t   dummy;
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    bsp_int_ctrl_t    int_ctrl;
+#endif
+
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl);
+#endif
+    ICU.GENAL1.BIT.EN4 = 0;
+#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6)
+    R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl);
+#endif
+    R_BSP_InterruptControl(BSP_INT_SRC_AL1_EDMAC0_EINT0, BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, FIT_NO_PTR);
+
+    dummy = channel;
+} /* End of function ether_disable_icu() */
+
+/***********************************************************************************************************************
+* Function Name: ether_set_phy_mode
+* Description  :
+* Arguments    : connect -
+*                    Ethernet channel number
+* Return Value : none
+***********************************************************************************************************************/
+void ether_set_phy_mode(uint8_t connect)
+{
+    if (PORT_CONNECT_ET0 == (connect & PORT_CONNECT_ET0))
+    {
+    #if (ETHER_CFG_MODE_SEL == 0)
+        /* MII */
+        MPC.PFENET.BIT.PHYMODE0 = 1;
+    #elif (ETHER_CFG_MODE_SEL == 1)
+        /* RMII */
+        MPC.PFENET.BIT.PHYMODE0 = 0;
+    #endif
+    }
+
+} /* End of function ether_set_phy_mode() */
+
+#endif  /* defined(BSP_MCU_RX65N) */
+
+/* End of File */
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/Pin.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/Pin.c
new file mode 100644
index 00000000..885c6e59
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/Pin.c
@@ -0,0 +1,143 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : Pin.c
+* Version      : 1.0.2
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements SMC pin code generation.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Pins_Create
+* Description  : This function initializes Smart Configurator pins
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Pins_Create(void)
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+    /* Set ET0_COL pin */
+    MPC.PC7PFS.BYTE = 0x11U;
+    PORTC.PMR.BYTE |= 0x80U;
+
+    /* Set ET0_CRS pin */
+    MPC.P83PFS.BYTE = 0x11U;
+    PORT8.PMR.BYTE |= 0x08U;
+
+    /* Set ET0_ERXD0 pin */
+    MPC.P75PFS.BYTE = 0x11U;
+    PORT7.PMR.BYTE |= 0x20U;
+
+    /* Set ET0_ERXD1 pin */
+    MPC.P74PFS.BYTE = 0x11U;
+    PORT7.PMR.BYTE |= 0x10U;
+
+    /* Set ET0_ERXD2 pin */
+    MPC.PC1PFS.BYTE = 0x11U;
+    PORTC.PMR.BYTE |= 0x02U;
+
+    /* Set ET0_ERXD3 pin */
+    MPC.PC0PFS.BYTE = 0x11U;
+    PORTC.PMR.BYTE |= 0x01U;
+
+    /* Set ET0_ETXD0 pin */
+    MPC.P81PFS.BYTE = 0x11U;
+    PORT8.PMR.BYTE |= 0x02U;
+
+    /* Set ET0_ETXD1 pin */
+    MPC.P82PFS.BYTE = 0x11U;
+    PORT8.PMR.BYTE |= 0x04U;
+
+    /* Set ET0_ETXD2 pin */
+    MPC.PC5PFS.BYTE = 0x11U;
+    PORTC.PMR.BYTE |= 0x20U;
+
+    /* Set ET0_ETXD3 pin */
+    MPC.PC6PFS.BYTE = 0x11U;
+    PORTC.PMR.BYTE |= 0x40U;
+
+    /* Set ET0_LINKSTA pin */
+    MPC.P34PFS.BYTE = 0x11U;
+    PORT3.PMR.BYTE |= 0x10U;
+
+    /* Set ET0_MDC pin */
+    MPC.P72PFS.BYTE = 0x11U;
+    PORT7.PMR.BYTE |= 0x04U;
+
+    /* Set ET0_MDIO pin */
+    MPC.P71PFS.BYTE = 0x11U;
+    PORT7.PMR.BYTE |= 0x02U;
+
+    /* Set ET0_RX_CLK pin */
+    MPC.P76PFS.BYTE = 0x11U;
+    PORT7.PMR.BYTE |= 0x40U;
+
+    /* Set ET0_RX_DV pin */
+    MPC.PC2PFS.BYTE = 0x11U;
+    PORTC.PMR.BYTE |= 0x04U;
+
+    /* Set ET0_RX_ER pin */
+    MPC.P77PFS.BYTE = 0x11U;
+    PORT7.PMR.BYTE |= 0x80U;
+
+    /* Set ET0_TX_CLK pin */
+    MPC.PC4PFS.BYTE = 0x11U;
+    PORTC.PMR.BYTE |= 0x10U;
+
+    /* Set ET0_TX_EN pin */
+    MPC.P80PFS.BYTE = 0x11U;
+    PORT8.PMR.BYTE |= 0x01U;
+
+    /* Set RXD8 pin */
+    MPC.PJ1PFS.BYTE = 0x0AU;
+    PORTJ.PMR.BYTE |= 0x02U;
+
+    /* Set TXD8 pin */
+    PORTJ.PODR.BYTE |= 0x04U;
+    MPC.PJ2PFS.BYTE = 0x0AU;
+    PORTJ.PDR.BYTE |= 0x04U;
+    // PORTJ.PMR.BIT.B2 = 1U; // Please set the PMR bit after TE bit is set to 1.
+
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/Pin.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/Pin.h
new file mode 100644
index 00000000..952c37a1
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/Pin.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : Pin.h
+* Version      : 1.0.2
+* Device(s)    : R5F565NEDxFC
+* Description  : This file implements SMC pin code generation.
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef PIN_H
+#define PIN_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Pins_Create(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/r_ether_rx_pinset.c b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/r_ether_rx_pinset.c
new file mode 100644
index 00000000..99e8d97f
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/r_ether_rx_pinset.c
@@ -0,0 +1,122 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_ether_rx_pinset.c
+* Version      : 1.0.2
+* Device(s)    : R5F565NEDxFC
+* Tool-Chain   : RXC toolchain
+* Description  : Setting of port and mpc registers
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_ether_rx_pinset.h"
+#include "platform.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: R_ETHER_PinSet_ETHERC0_MII
+* Description  : This function initializes pins for r_ether_rx module
+* Arguments    : none
+* Return Value : none
+***********************************************************************************************************************/
+void R_ETHER_PinSet_ETHERC0_MII()
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+    /* Set ET0_TX_CLK pin */
+    MPC.PC4PFS.BYTE = 0x11U;
+    PORTC.PMR.BIT.B4 = 1U;
+
+    /* Set ET0_RX_CLK pin */
+    MPC.P76PFS.BYTE = 0x11U;
+    PORT7.PMR.BIT.B6 = 1U;
+
+    /* Set ET0_TX_EN pin */
+    MPC.P80PFS.BYTE = 0x11U;
+    PORT8.PMR.BIT.B0 = 1U;
+
+    /* Set ET0_ETXD3 pin */
+    MPC.PC6PFS.BYTE = 0x11U;
+    PORTC.PMR.BIT.B6 = 1U;
+
+    /* Set ET0_ETXD2 pin */
+    MPC.PC5PFS.BYTE = 0x11U;
+    PORTC.PMR.BIT.B5 = 1U;
+
+    /* Set ET0_ETXD1 pin */
+    MPC.P82PFS.BYTE = 0x11U;
+    PORT8.PMR.BIT.B2 = 1U;
+
+    /* Set ET0_ETXD0 pin */
+    MPC.P81PFS.BYTE = 0x11U;
+    PORT8.PMR.BIT.B1 = 1U;
+
+    /* Set ET0_RX_DV pin */
+    MPC.PC2PFS.BYTE = 0x11U;
+    PORTC.PMR.BIT.B2 = 1U;
+
+    /* Set ET0_ERXD3 pin */
+    MPC.PC0PFS.BYTE = 0x11U;
+    PORTC.PMR.BIT.B0 = 1U;
+
+    /* Set ET0_ERXD2 pin */
+    MPC.PC1PFS.BYTE = 0x11U;
+    PORTC.PMR.BIT.B1 = 1U;
+
+    /* Set ET0_ERXD1 pin */
+    MPC.P74PFS.BYTE = 0x11U;
+    PORT7.PMR.BIT.B4 = 1U;
+
+    /* Set ET0_ERXD0 pin */
+    MPC.P75PFS.BYTE = 0x11U;
+    PORT7.PMR.BIT.B5 = 1U;
+
+    /* Set ET0_RX_ER pin */
+    MPC.P77PFS.BYTE = 0x11U;
+    PORT7.PMR.BIT.B7 = 1U;
+
+    /* Set ET0_CRS pin */
+    MPC.P83PFS.BYTE = 0x11U;
+    PORT8.PMR.BIT.B3 = 1U;
+
+    /* Set ET0_COL pin */
+    MPC.PC7PFS.BYTE = 0x11U;
+    PORTC.PMR.BIT.B7 = 1U;
+
+    /* Set ET0_MDC pin */
+    MPC.P72PFS.BYTE = 0x11U;
+    PORT7.PMR.BIT.B2 = 1U;
+
+    /* Set ET0_MDIO pin */
+    MPC.P71PFS.BYTE = 0x11U;
+    PORT7.PMR.BIT.B1 = 1U;
+
+    /* Set ET0_LINKSTA pin */
+    MPC.P34PFS.BYTE = 0x11U;
+    PORT3.PMR.BIT.B4 = 1U;
+
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/r_ether_rx_pinset.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/r_ether_rx_pinset.h
new file mode 100644
index 00000000..f300a90d
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/r_ether_rx_pinset.h
@@ -0,0 +1,41 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_ether_rx_pinset.h
+* Version      : 1.0.2
+* Device(s)    : R5F565NEDxFC
+* Tool-Chain   : RXC toolchain
+* Description  : Setting of port and mpc registers
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef R_ETHER_RX_H
+#define R_ETHER_RX_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+
+void R_ETHER_PinSet_ETHERC0_MII();
+
+#endif
diff --git a/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/r_pinset.h b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/r_pinset.h
new file mode 100644
index 00000000..ae73e9f9
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/rx_driver_package/src/smc_gen/r_pincfg/r_pinset.h
@@ -0,0 +1,34 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name    : r_pinset.h.h
+* Version      : 1.0.1
+* Description  : Declares all pin code headers into a single file
+* Creation Date: 2020-12-18
+***********************************************************************************************************************/
+
+#ifndef R_PINSET_H
+#define R_PINSET_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_ether_rx_pinset.h"
+
+#endif /* R_PINSET_H */
diff --git a/Renesas/RSK_RX65N_2MB/lib/threadx/tx_user.h b/Renesas/RSK_RX65N_2MB/lib/threadx/tx_user.h
new file mode 100644
index 00000000..db924875
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/lib/threadx/tx_user.h
@@ -0,0 +1,258 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   User Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_user.h                                           PORTABLE C      */ 
+/*                                                           6.0          */ 
+/*                                                                        */
+/*  AUTHOR                                                                */ 
+/*                                                                        */ 
+/*    William E. Lamie, Microsoft Corporation                             */ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This file contains user defines for configuring ThreadX in specific */ 
+/*    ways. This file will have an effect only if the application and     */ 
+/*    ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */ 
+/*    Note that all the defines in this file may also be made on the      */ 
+/*    command line when building ThreadX library and application objects. */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  05-19-2020     William E. Lamie         Initial Version 6.0           */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_USER_H
+#define TX_USER_H
+
+#define TX_ENABLE_FPU_SUPPORT
+
+/* Define various build options for the ThreadX port.  The application should either make changes
+   here by commenting or un-commenting the conditional compilation defined OR supply the defines 
+   though the compiler's equivalent of the -D option.  
+   
+   For maximum speed, the following should be defined:
+
+        TX_MAX_PRIORITIES                       32  
+        TX_DISABLE_PREEMPTION_THRESHOLD
+        TX_DISABLE_REDUNDANT_CLEARING
+        TX_DISABLE_NOTIFY_CALLBACKS
+        TX_NOT_INTERRUPTABLE
+        TX_TIMER_PROCESS_IN_ISR
+        TX_REACTIVATE_INLINE
+        TX_DISABLE_STACK_FILLING
+        TX_INLINE_THREAD_RESUME_SUSPEND
+   
+   For minimum size, the following should be defined:
+   
+        TX_MAX_PRIORITIES                       32  
+        TX_DISABLE_PREEMPTION_THRESHOLD
+        TX_DISABLE_REDUNDANT_CLEARING
+        TX_DISABLE_NOTIFY_CALLBACKS
+        TX_NOT_INTERRUPTABLE
+        TX_TIMER_PROCESS_IN_ISR
+   
+   Of course, many of these defines reduce functionality and/or change the behavior of the
+   system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR
+   results in faster and smaller code, however, it increases the amount of processing in the ISR.
+   In addition, some services that are available in timers are not available from ISRs and will
+   therefore return an error if this option is used. This may or may not be desirable for a 
+   given application.  */
+
+
+/* Override various options with default values already assigned in tx_port.h. Please also refer
+   to tx_port.h for descriptions on each of these options.  */
+
+/*
+#define TX_MAX_PRIORITIES                       32  
+#define TX_MINIMUM_STACK                        ????         
+#define TX_THREAD_USER_EXTENSION                ????
+#define TX_TIMER_THREAD_STACK_SIZE              ????
+#define TX_TIMER_THREAD_PRIORITY                ????
+*/
+
+/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls 
+   should be processed within the a system timer thread or directly in the timer ISR. 
+   By default, the timer thread is used. When the following is defined, the timer expiration 
+   processing is done directly from the timer ISR, thereby eliminating the timer thread control
+   block, stack, and context switching to activate it.  */
+
+/*
+#define TX_TIMER_PROCESS_IN_ISR
+*/
+
+/* Determine if in-line timer reactivation should be used within the timer expiration processing.
+   By default, this is disabled and a function call is used. When the following is defined,
+   reactivating is performed in-line resulting in faster timer processing but slightly larger
+   code size.  */ 
+
+/*
+#define TX_REACTIVATE_INLINE 
+*/
+
+/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled,
+   which places an 0xEF pattern in each byte of each thread's stack.  This is used by
+   debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature.  */
+
+/*
+#define TX_DISABLE_STACK_FILLING 
+*/
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+/*
+#define TX_ENABLE_STACK_CHECKING
+*/
+
+/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is 
+   enabled. If the application does not use preemption-threshold, it may be disabled to reduce
+   code size and improve performance.  */
+
+/*
+#define TX_DISABLE_PREEMPTION_THRESHOLD
+*/
+
+/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears 
+   the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary
+   clearing of ThreadX global variables.  */
+
+/*
+#define TX_DISABLE_REDUNDANT_CLEARING
+*/
+
+/* Determine if no timer processing is required. This option will help eliminate the timer 
+   processing when not needed. The user will also have to comment out the call to 
+   tx_timer_interrupt, which is typically made from assembly language in 
+   tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR
+   must also be used.  */
+
+/* 
+#define TX_NO_TIMER
+#ifndef TX_TIMER_PROCESS_IN_ISR
+#define TX_TIMER_PROCESS_IN_ISR
+#endif
+*/
+
+/* Determine if the notify callback option should be disabled. By default, notify callbacks are
+   enabled. If the application does not use notify callbacks, they may be disabled to reduce
+   code size and improve performance.  */
+
+/*
+#define TX_DISABLE_NOTIFY_CALLBACKS
+*/
+
+
+/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal 
+   code in-line. This results in a larger image, but improves the performance of the thread 
+   resume and suspend services.  */
+
+/*
+#define TX_INLINE_THREAD_RESUME_SUSPEND
+*/
+
+
+/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code 
+   size and less processing overhead, but increases the interrupt lockout time.  */
+
+/*
+#define TX_NOT_INTERRUPTABLE
+*/
+
+
+/* Determine if the trace event logging code should be enabled. This causes slight increases in 
+   code size and overhead, but provides the ability to generate system trace information which 
+   is available for viewing in TraceX.  */
+
+/*
+#define TX_ENABLE_EVENT_TRACE
+*/
+
+
+/* Determine if block pool performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various block pool performance information. */
+
+/*
+#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if byte pool performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various byte pool performance information. */
+
+/*
+#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if event flags performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various event flags performance information. */
+
+/*
+#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if mutex performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various mutex performance information. */
+
+/*
+#define TX_MUTEX_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if queue performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various queue performance information. */
+
+/*
+#define TX_QUEUE_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if semaphore performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various semaphore performance information. */
+
+/*
+#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if thread performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various thread performance information. */
+
+/*
+#define TX_THREAD_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if timer performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various timer performance information. */
+
+/*
+#define TX_TIMER_ENABLE_PERFORMANCE_INFO
+*/
+
+#endif
+
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+---
+page_type: sample
+description: Connecting a Renensas Starter Kit+ for RX65N-2MB
+languages:
+- c
+products:
+- azure-iot
+- azure-iot-pnp
+- azure-rtos
+- azure-iot-dps
+- azure-iot-hub
+---
+
+# Getting started with the Renensas Starter Kit+ for RX65N-2MB
+
+**Total completion time**: 30 minutes
+
+In this tutorial you use Azure RTOS to connect the Renensas Starter Kit+ for RX65N-2MB (hereafter, the Renesas RX65N) to Azure IoT.  The article is part of the series [Getting Started with Azure RTOS](https://go.microsoft.com/fwlink/p/?linkid=2129824). The series introduces device developers to Azure RTOS, and shows how to connect several device evaluation kits to Azure IoT.
+
+You will complete the following tasks:
+
+* Install a set of embedded development tools for programming the Renesas RX65N in C
+* Build an image and flash it onto the Renesas RX65N
+* Use Azure CLI to create and manage an Azure IoT hub that the Renesas RX65N will securely connect to
+* Use Azure IoT Explorer to view properties, view device telemetry, and call cloud-to-device (c2d) methods
+
+## Prerequisites
+
+* A PC running Microsoft Windows 10
+* If you don't have an Azure subscription, [create one for free](https://azure.microsoft.com/free/?WT.mc_id=A261C142F) before you begin.
+* [Git](https://git-scm.com/downloads) for cloning the repository
+* Hardware
+
+    > * The [Renensas Starter Kit+ for RX65N-2MB](https://www.renesas.com/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rx65n-2mb-starter-kit-plus-renesas-starter-kit-rx65n-2mb) (Renesas RX65N)
+    > * The [Renesas E2 emulator Lite](https://www.renesas.com/software-tool/e2-emulator-lite-rte0t0002lkce00000r)
+    > * 2 * USB 2.0 A male to Mini USB male cable
+    > * The included 5V power supply
+    > * Ethernet cable
+    > * Wired Ethernet access
+
+## Prepare the development environment
+
+To set up your development environment, first you clone a GitHub repo that contains all the assets you need for the tutorial. Then you install a set of programming tools.
+
+### Clone the repo for the tutorial
+
+Clone the following repo to download all sample device code, setup scripts, and offline versions of the documentation. If you previously cloned this repo in another tutorial, you don't need to do it again.
+
+To clone the repo, run the following command:
+
+```shell
+git clone --recursive https://github.com/azure-rtos/getting-started.git
+```
+
+### Install the tools
+
+The cloned repo contains a setup script that installs and configures the required tools. If you installed these tools in another tutorial in the getting started guide, you don't need to do it again.
+
+> Note: The setup script installs the following tools:
+
+> * [GCC](http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.exe): Compile
+> * [CMake](https://cmake.org): Build
+> * [Termite](https://www.compuphase.com/software_termite.htm): Monitor serial port output for connected devices
+> * [Azure CLI](https://docs.microsoft.com/en-us/cli/azure/): Manage Azure resources
+> * [Azure IoT Explorer](https://github.com/Azure/azure-iot-explorer/releases): Cross-platform utility to  monitor and manage Azure IoT resources
+
+To install the tools:
+
+1. From File Explorer, navigate to the following path in the repo and run the setup script named *get-toolchain-rx.bat*:
+
+    > *getting-started\tools\get-toolchain-rx.bat*
+
+    After the installation completes, the Azure IoT Explorer opens automatically. Keep the IoT Explorer open, you'll use it in later steps.
+
+1. Add RX compiler to the Windows Path:
+
+    > *%USERPROFILE%\AppData\Roaming\GCC for Renesas RX 8.3.0.202004-GNURX-ELF\rx-elf\rx-elf\bin*
+
+1. After the installation, open a new console window to recognize the configuration changes made by the setup script. Use this console to complete the remaining programming tasks in the tutorial. You can use Windows CMD, PowerShell, or Git Bash for Windows.
+
+1. Run the following commands to confirm that CMake version 3.14 or later is installed and the RX compiler path is setup correctly:
+
+    ```shell
+    cmake --version
+    rx-elf-gcc
+    ```
+
+To install the remaining tools:
+
+1. Install [Renesas Flash Programmer](https://www.renesas.com/software-tool/renesas-flash-programmer-programming-gui). The Renesas Flash Programmer contains the drivers and tools needed to flash the Renesas RX65N via the Renesas E2 Lite.
+
+### Create an IoT hub
+
+You can use Azure CLI to create an IoT hub that handles events and messaging for your device.
+
+To create an IoT hub:
+
+1. From your console window, run the [az group create](https://docs.microsoft.com/cli/azure/group?view=azure-cli-latest#az-group-create) command to create a resource group. The following command creates a resource group named *MyResourceGroup* in the *centralus* region.
+
+    > Note: You can optionally set an alternate `location`. To see available locations, run [az account list-locations](https://docs.microsoft.com/cli/azure/account?view=azure-cli-latest#az-account-list-locations). For this tutorial we recommend using `centralus` as in the example CLI command. The IoT Plug and Play feature that you use later in the tutorial, is currently only available in three regions, including `centralus`.
+
+    ```shell
+    az group create --name MyResourceGroup --location centralus
+    ```
+
+1. Run the [az iot hub create](https://docs.microsoft.com/cli/azure/iot/hub?view=azure-cli-latest#az-iot-hub-create) command to create an IoT hub. It might take a few minutes to create an IoT hub.
+
+    *YourIotHubName*. Replace this placeholder below with the name you chose for your IoT hub. An IoT hub name must be globally unique in Azure. This placeholder is used in the rest of this tutorial to represent your unique IoT hub name.
+
+    ```shell
+    az iot hub create --resource-group MyResourceGroup --name {YourIoTHubName}
+    ```
+
+1. After the IoT hub is created, view the JSON output in the console, and copy the `hostName` value to use in a later step. The `hostName` value looks like the following example:
+
+    `{Your IoT hub name}.azure-devices.net`
+
+### Register a device
+
+In this section, you create a new device instance and register it with the IoT hub you created. You will use the connection information for the newly registered device to securely connect your physical device in a later section.
+
+To register a device:
+
+1. In your console, run the [az iot hub device-identity create](https://docs.microsoft.com/cli/azure/ext/azure-cli-iot-ext/iot/hub/device-identity?view=azure-cli-latest#ext-azure-cli-iot-ext-az-iot-hub-device-identity-create) command. This creates the simulated device identity.
+
+    *YourIotHubName*. Replace this placeholder below with the name you chose for your IoT hub.
+
+    *MyRenesasDevice*. You can use this name directly for the device in CLI commands in this tutorial. Optionally, use a different name.
+
+    ```shell
+    az iot hub device-identity create --device-id MyRenesasDevice --hub-name {YourIoTHubName}
+    ```
+
+1. After the device is created, view the JSON output in the console, and copy the `deviceId` and `primaryKey` values to use in a later step.
+
+## Prepare the device
+
+Confirm that you have the copied the following values from the JSON output from the previous sections:
+
+> * `hostName`
+> * `deviceId`
+> * `primaryKey`
+
+To connect the Renesas RX65N to Azure, you'll modify a configuration file for Azure IoT settings, rebuild the image, and flash the image to the device.
+
+### Add configuration
+
+1. Open the following file in a text editor:
+
+    > *getting-started\Renesas\RSK_RX65N_2MB\app\azure_config.h*
+
+1. Set the Azure IoT device information constants to the values that you saved after you created Azure resources.
+
+    |Constant name|Value|
+    |-------------|-----|
+    |`IOT_HUB_HOSTNAME` |{*Your Iot hub hostName value*}|
+    |`IOT_HUB_DEVICE_ID` |{*Your deviceID value*}|
+    |`IOT_DEVICE_SAS_KEY` |{*Your primaryKey value*}|
+
+1. Save and close the file.
+
+### Connect the device
+
+> Note: For more details about setting up and getting started with the Renesas RX65N, see [Renesas Starter Kit+ for RX65N-2MB Quick Start](https://www.renesas.com/document/man/e2studio-renesas-starter-kit-rx65n-2mb-quick-start-guide).
+
+1. Complete the following steps using the following image as a reference.
+    
+    ![Renesas RX65N reset, power, ethernet, USB and E1/E2Lite](media/renesas-rx65n.jpg)
+
+1. Using the 5V power supply, connect the **Power Input** on the Rensas RX65N to an electrical outlet.
+
+1. Using the Ethernet cable, connect the  **Ethernet** on the Renesas RX65N to your router.
+
+1. Using the first Mini USB cable, connect the **USB Serial** on the Renesas RX65N to your computer.
+
+1. Using the second Mini USB cable, connect the **E2 Lite USB Serial** on the Renesas E2 Lite to your computer.
+
+1. Using the supplied ribbon cable, connect the **E1/E2Lite** on the Renesas RX65N to the Renesas E2 Lite.
+
+### Build the image
+
+In your console or in File Explorer, run the script *rebuild.bat* at the following path to build the image:
+
+> *getting-started\Renesas\RSK_RX65N_2MB\tools\rebuild.bat*
+
+After the build completes, confirm that a binary file was created in the following path:
+
+> *getting-started\Renesas\RSK_RX65N_2MB\build\app\rx65n_azure_iot.hex*
+
+### Flash the image
+
+1. Launch the *Renesas Flash Programmer* application from the Start menu.
+
+2. Select *New Project...* from the *File* menu, and enter the following settings:
+    * **Microcontroller**: RX65x
+    * **Project Name**: RX65N
+    * **Tool**: E2 emulator Lite
+
+    ![Renesas Flash Programmer, New Project](media/rfp_new.png)
+
+3. Select the *Tool Details* button, and navigate to the *Reset Settings* tab.
+
+4. Select *Reset Pin as Hi-Z* and press the *OK* button.
+
+    ![Renesas Flash Programmer, Reset Settings](media/rfp_reset.png)
+
+5. Press the *Connect* button and when prompted, check the *Auto Authentication* checkbox and then press *OK*.
+
+    ![Renesas Flash Programmer, Authentication](media/rfp_auth.png)
+
+6. Select the *Browse...* button and locate the *rx65n_azure_iot.hex* file created in the previous section.
+
+7. Press *Start* to begin flashing. This process will take approximately 10 seconds.
+
+### Confirm device connection details
+
+You can use the **Termite** utility to monitor communication and confirm that your device is set up correctly.
+> Note: If you have issues getting your device to initialize or connect after flashing, see [Troubleshooting](../../docs/troubleshooting.md).
+
+1. Start **Termite**.
+1. Select **Settings**.
+1. In the **Serial port settings** dialog, check the following settings and update if needed:
+    * **Baud rate**: 115,200
+    * **Port**: The port that your Renesas RX65N is connected to. If there are multiple port options in the dropdown, you can find the correct port to use. Open Windows **Device Manager**, and view **Ports** to identify which port to use.
+    * **Flow control**: DTR/DSR
+
+    ![Termite](media/termite-settings.png)
+1. Select OK.
+1. Press the **Reset** button on the device.
+1. In the **Termite** console, check the following checkpoint values to confirm that the device is initialized and connected to Azure IoT.
+
+    ```output
+    Starting Azure thread
+
+    Initializing DHCP
+    	IP address: 10.0.0.123
+    	Mask: 255.255.255.0
+    	Gateway: 10.0.0.1
+    SUCCESS: DHCP initialized
+
+    Initializing DNS client
+    	DNS address: 10.0.0.1
+    SUCCESS: DNS client initialized
+
+    Initializing SNTP client
+    	SNTP server 0.pool.ntp.org
+    	SNTP IP address: 185.242.56.3
+    	SNTP time update: Nov 16, 2020 23:47:35.385 UTC 
+    SUCCESS: SNTP initialized
+
+    Initializing Azure IoT DPS client
+    	DPS endpoint: global.azure-devices-provisioning.net
+    	DPS ID scope: ***
+    	Registration ID: ***
+    SUCCESS: Azure IoT DPS client initialized
+
+    Initializing Azure IoT Hub client
+    	Hub hostname: ***
+    	Device id: ***
+    	Model id: dtmi:azurertos:devkit:gsg;1
+    Connected to IoTHub
+    SUCCESS: Azure IoT Hub client initialized
+
+    Starting Main loop
+    ```
+
+Keep Termite open to monitor device output in the following steps.
+
+## View device properties
+
+> **Note**: From this point in the tutorial, you can continue these steps, or you can optionally follow the same steps using the IoT Plug and Play preview. IoT Plug and Play provides a standard device model that lets a compatible device advertise its capabilities to an application. This approach simplifies the process of adding, configuring, and interacting with devices. To try IoT Plug and Play with your device, see [Using IoT Plug and Play with Azure RTOS](../../docs/plugandplay.md).
+
+You can use the Azure IoT Explorer to view and manage the properties of your devices. In the following steps, you'll add a connection to your IoT hub in IoT Explorer. With the connection, you can view properties for devices associated with the IoT hub. Optionally, you can perform the same task using Azure CLI.
+
+To add a connection to your IoT hub:
+
+1. In your console window, run the [az iot hub show-connection-string](https://docs.microsoft.com/en-us/cli/azure/iot/hub?view=azure-cli-latest#az-iot-hub-show-connection-string) command to get the connection string for your IoT hub.
+
+    ```shell
+    az iot hub show-connection-string --name {YourIoTHubName}
+    ```
+
+1. Copy the connection string without the surrounding quotation characters.
+1. In Azure IoT Explorer, select **IoT hubs > Add connection**.
+1. Paste the connection string into the **Connection string** box.
+1. Select **Save**.
+
+    ![Azure IoT Explorer connection string](media/azure-iot-explorer-create-connection.png)
+
+If the connection succeeds, the Azure IoT Explorer switches to a **Devices** view and lists your device.
+
+To view device properties using Azure IoT Explorer:
+
+1. Select the link for your device identity. IoT Explorer displays details for the device.
+
+    ![Azure IoT Explorer device identity](media/azure-iot-explorer-device-identity.png)
+
+1. Inspect the properties for your device in the **Device identity** panel.
+1. Optionally, select the **Device twin** panel and inspect additional device properties.
+
+To use Azure CLI to view device properties:
+
+1. Run the [az iot hub device-identity show](https://docs.microsoft.com/en-us/cli/azure/ext/azure-iot/iot/hub/device-identity?view=azure-cli-latest#ext-azure-iot-az-iot-hub-device-identity-show) command.
+
+    ```shell
+    az iot hub device-identity show --device-id MyRenesasDevice --hub-name {YourIoTHubName}
+    ```
+
+1. Inspect the properties for your device in the console output.
+
+## View telemetry
+
+With Azure IoT Explorer, you can view the flow of telemetry from your device to the cloud. Optionally, you can perform the same task using Azure CLI.
+
+To view telemetry in Azure IoT Explorer:
+
+1. In IoT Explorer select **Telemetry**. Confirm that **Use built-in event hub** is set to *Yes*.
+1. Select **Start**.
+1. View the telemetry as the device sends messages to the cloud. 
+
+    ![Azure IoT Explorer device telemetry](media/azure-iot-explorer-device-telemetry.png)
+
+    Note: You can also monitor telemetry from the device by using the Termite terminal.
+
+1. Select **Stop** to end receiving events.
+
+To use Azure CLI to view device telemetry:
+
+1. In your CLI console, run the [az iot hub monitor-events](https://docs.microsoft.com/en-us/cli/azure/ext/azure-iot/iot/hub?view=azure-cli-latest#ext-azure-iot-az-iot-hub-monitor-events) command. Use the names that you created previously in Azure IoT for your device and IoT hub.
+
+    ```shell
+    az iot hub monitor-events --device-id MyRenesasDevice --hub-name {YourIoTHubName}
+    ```
+
+1. View the JSON output in the console.
+
+    ```json
+    {
+        "event": {
+            "origin": "MyRenesasDevice",
+            "payload": "{\"temperature\": 28.5}"
+        }
+    }
+    ```
+
+1. Select CTRL+C to end monitoring.
+
+## Call a direct method on the device
+
+You can also use Azure IoT Explorer to call a direct method that you have implemented on your device. Direct methods have a name, and can optionally have a JSON payload, configurable connection, and method timeout. In this section, you call a method that enables you to turn the LEDs on or off. Optionally, you can perform the same task using Azure CLI.
+
+To call a method in Azure IoT Explorer:
+
+1. Select **Direct method**.
+1. In the **Direct method** panel add the following values for the method name and payload. The payload value *true* indicates to turn the LEDs on.
+    * **Method name**: `setLedState`
+    * **Payload**: `true`
+1. Select **Invoke method**. The four LEDs next to the reset button should turn on.
+
+    ![Azure IoT Explorer invoke method](media/azure-iot-explorer-invoke-method.png)
+1. Change **Payload** to *false*, and again select **Invoke method**. The four LEDs next to the reset button should turn off.
+1. Optionally, you can view the output in Termite to monitor the status of the methods.
+
+To use Azure CLI to call a method:
+
+1. Run the [az iot hub invoke-device-method](https://docs.microsoft.com/en-us/cli/azure/ext/azure-iot/iot/hub?view=azure-cli-latest#ext-azure-iot-az-iot-hub-invoke-device-method) command, and specify the method name and payload. For this method, setting `method-payload` to `true` turns the LEDs on, and setting it to `false` turns them off.
+
+    <!-- Inline code tag and CSS to wrap long code lines. -->
+    <code style="white-space : pre-wrap !important;">
+    az iot hub invoke-device-method --device-id MyRenesasDevice --method-name setLedState --method-payload true --hub-name {YourIoTHubName}
+    </code>
+
+    The CLI console shows the status of your method call on the device, where `204` indicates success.
+
+    ```json
+    {
+      "payload": {},
+      "status": 204
+    }
+    ```
+
+1. Check your device to confirm the LED state.
+
+1. View the Termite terminal to confirm the output messages:
+
+    ```output
+    Received direct method call: setLedState
+        Payload: true
+    LED is turned ON
+    Device twin property sent: {"ledState":true}
+    ```
+
+## Clean up resources
+
+If you no longer need the Azure resources created in this tutorial, you can use the Azure CLI to delete the resource group and all the resources you created for this tutorial. Optionally, you can use Azure IoT Explorer to delete individual resources including devices and IoT hubs.
+
+If you continue to another tutorial in this Getting Started guide, you can keep the resources you've already created and reuse them.
+
+> **Important**: Deleting a resource group is irreversible. The resource group and all the resources contained in it are permanently deleted. Make sure that you do not accidentally delete the wrong resource group or resources.
+
+To delete a resource group by name:
+
+1. Run the [az group delete](https://docs.microsoft.com/cli/azure/group?view=azure-cli-latest#az-group-delete) command. This removes the resource group, the IoT Hub, and the device registration you created.
+
+    ```shell
+    az group delete --name MyResourceGroup
+    ```
+
+1. Run the [az group list](https://docs.microsoft.com/cli/azure/group?view=azure-cli-latest#az-group-list) command to confirm the resource group is deleted.  
+
+    ```shell
+    az group list
+    ```
+
+## Next Steps
+
+In this tutorial you built a custom image that contains Azure RTOS sample code, and then flashed the image to the Renesas RX65N device. You also used the Azure CLI to create Azure resources, connect the Renesas RX65N securely to Azure, view telemetry, and send messages.
+
+* For device developers, the suggested next step is to see the other tutorials in the series [Getting started with Azure RTOS](https://go.microsoft.com/fwlink/p/?linkid=2129824).
+* If you have issues getting your device to initialize or connect after following the steps in this guide, see [Troubleshooting](../../docs/troubleshooting.md).
+* To learn more about how Azure RTOS components are used in the sample code for this tutorial, see [Using Azure RTOS in the Getting Started Guides](../../docs/using-azure-rtos.md).
+    >Note: Azure RTOS provides OEMs with components to secure communication and to create code and data isolation using underlying MCU/MPU hardware protection mechanisms. However, each OEM is ultimately responsible for ensuring that their device meets evolving security requirements.
diff --git a/Renesas/RSK_RX65N_2MB/tools/rebuild.bat b/Renesas/RSK_RX65N_2MB/tools/rebuild.bat
new file mode 100644
index 00000000..763896d4
--- /dev/null
+++ b/Renesas/RSK_RX65N_2MB/tools/rebuild.bat
@@ -0,0 +1,14 @@
+:: Copyright (c) Microsoft Corporation.
+:: Licensed under the MIT License.
+
+@echo off
+
+setlocal
+cd /d %~dp0\..
+
+IF EXIST build (rd /S /Q build)
+
+cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE="../../cmake/renesas-rx-gcc-rx65n.cmake"
+cmake --build build
+
+IF %0 == "%~0" pause
\ No newline at end of file
diff --git a/STMicroelectronics/STM32L4_L4+/CMakeLists.txt b/STMicroelectronics/STM32L4_L4+/CMakeLists.txt
index 99a52bee..cd8e5fe1 100644
--- a/STMicroelectronics/STM32L4_L4+/CMakeLists.txt
+++ b/STMicroelectronics/STM32L4_L4+/CMakeLists.txt
@@ -1,7 +1,7 @@
 # Copyright (c) Microsoft Corporation.
 # Licensed under the MIT License.
 
-cmake_minimum_required(VERSION 3.10 FATAL_ERROR)
+cmake_minimum_required(VERSION 3.13 FATAL_ERROR)
 set(CMAKE_C_STANDARD 99)
 
 set(GSG_BASE_DIR ${CMAKE_SOURCE_DIR}/../..)
diff --git a/STMicroelectronics/STM32L4_L4+/readme.md b/STMicroelectronics/STM32L4_L4+/readme.md
index 99bea610..acbf4061 100644
--- a/STMicroelectronics/STM32L4_L4+/readme.md
+++ b/STMicroelectronics/STM32L4_L4+/readme.md
@@ -363,11 +363,10 @@ To use Azure CLI to call a method:
 1. View the Termite terminal to confirm the output messages:
 
     ```output
-    Received direct method=setLedState, id=1, message=true
+    Received direct method call: setLedState
+        Payload: true
     LED is turned ON
-    Sending device twin update with bool value
-    Sending message {"ledState":true}
-    Direct method=setLedState invoked
+    Device twin property sent: {"ledState":true}
     ```
 
 ## Debugging
diff --git a/cmake/arm-gcc-cortex-toolchain.cmake b/cmake/arm-gcc-cortex-toolchain.cmake
index 61c2b2d5..352289bd 100644
--- a/cmake/arm-gcc-cortex-toolchain.cmake
+++ b/cmake/arm-gcc-cortex-toolchain.cmake
@@ -54,7 +54,7 @@ set(CMAKE_EXE_LINKER_FLAGS "${LD_FLAGS} -fno-common -Wl,--gc-sections,-print-mem
 
 set(CMAKE_C_FLAGS_DEBUG "-O0 -g3")
 set(CMAKE_CXX_ASM_FLAGS_DEBUG "-O0 -g3")
-set(CMAKE_C_ASM_FLAGS_DEBUG "-g3")
+set(CMAKE_ASM_FLAGS_DEBUG "-g3")
 
 set(CMAKE_C_FLAGS_RELEASE "-Os")
 set(CMAKE_CXX_FLAGS_RELEASE "-Os")
diff --git a/cmake/ninja.exe b/cmake/ninja.exe
index 5729a165..95ad42e0 100644
Binary files a/cmake/ninja.exe and b/cmake/ninja.exe differ
diff --git a/cmake/renesas-rx-gcc-rx65n.cmake b/cmake/renesas-rx-gcc-rx65n.cmake
new file mode 100644
index 00000000..a14885d0
--- /dev/null
+++ b/cmake/renesas-rx-gcc-rx65n.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+set(MCPU_FLAGS "-m64bit-doubles -mcpu=rx64m -misa=v2 -mlittle-endian-data")
+
+include(${CMAKE_CURRENT_LIST_DIR}/renesas-rx-gcc-toolchain.cmake)
diff --git a/cmake/renesas-rx-gcc-toolchain.cmake b/cmake/renesas-rx-gcc-toolchain.cmake
new file mode 100644
index 00000000..9b55bacd
--- /dev/null
+++ b/cmake/renesas-rx-gcc-toolchain.cmake
@@ -0,0 +1,61 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+set(CMAKE_SYSTEM_NAME Generic)
+set(CMAKE_SYSTEM_PROCESSOR rx)
+set(TARGET_TRIPLET "rx-elf-")
+
+# do some windows specific logic
+if(WIN32)
+    set(TOOLCHAIN_EXT ".exe")
+else()
+    set(TOOLCHAIN_EXT "")
+endif(WIN32)
+
+# default to Release build
+if(NOT CMAKE_BUILD_TYPE)
+    set(CMAKE_BUILD_TYPE "Debug" CACHE STRING "Choose the type of build, options are: Debug Release." FORCE)
+endif()
+
+find_program(COMPILER_ON_PATH "${TARGET_TRIPLET}gcc${TOOLCHAIN_EXT}")
+
+if(DEFINED ENV{RX_GCC_PATH}) 
+    # use the environment variable first    
+    file(TO_CMAKE_PATH $ENV{RX_GCC_PATH} RX_TOOLCHAIN_PATH)
+    message(STATUS "Using ENV variable RX_GCC_PATH = ${RX_TOOLCHAIN_PATH}")
+elseif(COMPILER_ON_PATH) 
+    # then check on the current path
+    get_filename_component(RX_TOOLCHAIN_PATH ${COMPILER_ON_PATH} DIRECTORY)
+    message(STATUS "Using RX GCC from path = ${RX_TOOLCHAIN_PATH}")
+endif()
+
+# perform compiler test with the static library
+set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
+
+set(CMAKE_C_COMPILER    ${RX_TOOLCHAIN_PATH}/${TARGET_TRIPLET}gcc${TOOLCHAIN_EXT} CACHE STRING "")
+set(CMAKE_CXX_COMPILER  ${RX_TOOLCHAIN_PATH}/${TARGET_TRIPLET}g++${TOOLCHAIN_EXT} CACHE STRING "")
+set(CMAKE_ASM_COMPILER  ${RX_TOOLCHAIN_PATH}/${TARGET_TRIPLET}gcc${TOOLCHAIN_EXT})
+set(CMAKE_LINKER        ${RX_TOOLCHAIN_PATH}/${TARGET_TRIPLET}gcc${TOOLCHAIN_EXT})
+set(CMAKE_SIZE_UTIL     ${RX_TOOLCHAIN_PATH}/${TARGET_TRIPLET}size${TOOLCHAIN_EXT})
+set(CMAKE_OBJCOPY       ${RX_TOOLCHAIN_PATH}/${TARGET_TRIPLET}objcopy${TOOLCHAIN_EXT})
+set(CMAKE_OBJDUMP       ${RX_TOOLCHAIN_PATH}/${TARGET_TRIPLET}objdump${TOOLCHAIN_EXT})
+set(CMAKE_NM_UTIL       ${RX_TOOLCHAIN_PATH}/${TARGET_TRIPLET}nm${TOOLCHAIN_EXT})
+
+set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
+set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
+
+set(CMAKE_COMMON_FLAGS "-ffunction-sections -fdata-sections -fdiagnostics-parseable-fixits -fno-strict-aliasing -fno-builtin -fshort-enums -Wuninitialized -Wdouble-promotion -Werror -Wno-unused-function -Wno-unused-parameter -Wno-incompatible-pointer-types")
+set(CMAKE_C_FLAGS 	"${MCPU_FLAGS} ${VFP_FLAGS} ${CMAKE_COMMON_FLAGS} ${LIBC_INCLUDE}")
+set(CMAKE_CXX_FLAGS "${MCPU_FLAGS} ${VFP_FLAGS} ${CMAKE_COMMON_FLAGS}")
+set(CMAKE_ASM_FLAGS "${MCPU_FLAGS} ${VFP_FLAGS}")
+set(CMAKE_EXE_LINKER_FLAGS "${LD_FLAGS} -fno-common -nostartfiles -Wl,--gc-sections --specs=nano.specs")
+
+set(CMAKE_C_FLAGS_DEBUG "-O0 -g3")
+set(CMAKE_CXX_ASM_FLAGS_DEBUG "-O0 -g3")
+set(CMAKE_ASM_FLAGS_DEBUG "-g3")
+
+set(CMAKE_C_FLAGS_RELEASE "-Os")
+set(CMAKE_CXX_FLAGS_RELEASE "-Os")
+set(CMAKE_ASM_FLAGS_RELEASE "")
diff --git a/cmake/utilities.cmake b/cmake/utilities.cmake
index 44c0a052..b3c3ed7e 100644
--- a/cmake/utilities.cmake
+++ b/cmake/utilities.cmake
@@ -1,13 +1,14 @@
 # Copyright (c) Microsoft Corporation.
 # Licensed under the MIT License.
 
-cmake_minimum_required(VERSION 3.10 FATAL_ERROR)
+cmake_minimum_required(VERSION 3.13 FATAL_ERROR)
 
 # Create the bin output
 function(create_bin_output TARGET)
     add_custom_target(${TARGET}.bin ALL 
         DEPENDS ${TARGET}
-        COMMAND ${CMAKE_OBJCOPY} -Obinary ${TARGET}.elf ${TARGET}.bin)
+        COMMAND ${CMAKE_OBJCOPY} -Obinary ${TARGET}.elf ${TARGET}.bin
+        COMMAND ${CMAKE_OBJCOPY} -Oihex ${TARGET}.elf ${TARGET}.hex)
 endfunction()
 
 # Add custom command to print firmware size in Berkley format
diff --git a/core/lib/netxduo b/core/lib/netxduo
index 158f1dae..300c8787 160000
--- a/core/lib/netxduo
+++ b/core/lib/netxduo
@@ -1 +1 @@
-Subproject commit 158f1daedb3882a2d2117995a2e24cd431b279f4
+Subproject commit 300c8787a8ddb32007560e5244208a1b21afa23e
diff --git a/core/lib/threadx b/core/lib/threadx
index 9b050d00..32e3b3b2 160000
--- a/core/lib/threadx
+++ b/core/lib/threadx
@@ -1 +1 @@
-Subproject commit 9b050d00ed6e138fef2dd9fdcd421298a485d9d1
+Subproject commit 32e3b3b25f4b17ff51ce8a6bad8d9eb32729a0f6
diff --git a/core/src/CMakeLists.txt b/core/src/CMakeLists.txt
index e96345e5..170c75bf 100644
--- a/core/src/CMakeLists.txt
+++ b/core/src/CMakeLists.txt
@@ -16,7 +16,6 @@ set(SOURCES
     azure_iot_cert.c
     azure_iot_ciphersuites.c
     json_utils.c
-    newlib_nano.c
     sntp_client.c
 )
 
@@ -27,6 +26,13 @@ if(NOT DEFINED DISABLE_COMMON_NETWORK)
     )
 endif()
 
+# Allow to disable the common networking component
+if(NOT DEFINED DISABLE_NEWLIB_STUB) 
+    list(APPEND SOURCES
+        newlib_nano.c
+    )
+endif()
+
 add_library(${TARGET} OBJECT
     ${SOURCES}
 )
diff --git a/core/src/newlib_nano.c b/core/src/newlib_nano.c
index 534d36a8..466f4089 100644
--- a/core/src/newlib_nano.c
+++ b/core/src/newlib_nano.c
@@ -1,30 +1,21 @@
 /* Copyright (c) Microsoft Corporation.
    Licensed under the MIT License. */
-   
-#include <stdio.h>
+
 #include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
 
-#include <sys/types.h>
 #include <sys/stat.h>
 
 extern int errno;
 extern int _end;
 
-caddr_t _sbrk(int incr);
-int _close(int file);
-int _fstat(int file, struct stat *st);
-int _isatty(int file);
-int _lseek(int file, int ptr, int dir);
-void _exit(int status);
-void _kill(int pid, int sig);
-int _getpid(void);
-
-caddr_t _sbrk(int incr)
+void* _sbrk(int incr)
 {
     static unsigned char* heap = NULL;
-    unsigned char*        prev_heap;
+    unsigned char* prev_heap;
 
-    if (heap == NULL) 
+    if (heap == NULL)
     {
         heap = (unsigned char*)&_end;
     }
@@ -32,7 +23,7 @@ caddr_t _sbrk(int incr)
 
     heap += incr;
 
-    return (caddr_t)prev_heap;
+    return prev_heap;
 }
 
 int _close(int file)
@@ -40,7 +31,7 @@ int _close(int file)
     return -1;
 }
 
-int _fstat(int file, struct stat *st)
+int _fstat(int file, struct stat* st)
 {
     st->st_mode = S_IFCHR;
     return 0;
@@ -59,7 +50,8 @@ int _lseek(int file, int ptr, int dir)
 void _exit(int status)
 {
     printf("Exiting with status %d.\n", status);
-    while (1);
+    while (1)
+        ;
 }
 
 void _kill(int pid, int sig)
diff --git a/tools/get-toolchain-rx.bat b/tools/get-toolchain-rx.bat
new file mode 100644
index 00000000..ac53cc7b
--- /dev/null
+++ b/tools/get-toolchain-rx.bat
@@ -0,0 +1,8 @@
+:: Copyright (c) Microsoft Corporation.
+:: Licensed under the MIT License.
+
+@echo off
+
+PowerShell.exe -NoProfile -Command "& {Start-Process PowerShell.exe -ArgumentList '-NoProfile -ExecutionPolicy Bypass -File ""%~dpn0.ps1""' -Verb RunAs}"
+
+::pause
diff --git a/tools/get-toolchain-rx.ps1 b/tools/get-toolchain-rx.ps1
new file mode 100644
index 00000000..a09b02b9
--- /dev/null
+++ b/tools/get-toolchain-rx.ps1
@@ -0,0 +1,91 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+[System.Net.ServicePointManager]::SecurityProtocol = [System.Net.SecurityProtocolType]::Tls12;
+
+echo "`nInstalling prerequisites. Please leave the window open until the installation completes."
+
+$gccrx_path = 'http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx'
+$gccrx_file = 'gcc-8.3.0.202004-GNURX-ELF.exe'
+$gccrx_name = 'GCC-RX 8.3.0.20204'
+$gccrx_hash = 'C3340B4915208361A33885505CFB89B69E1607A07F89FBF2A79096182D293978'
+
+$cmake_path = 'https://github.com/Kitware/CMake/releases/download/v3.19.2'
+$cmake_file = 'cmake-3.19.2-win32-x86.msi'
+$cmake_name = 'CMake v3.19.2'
+$cmake_hash = '7ABFEA6278B7BF3F6EB1D3B13F9DF79FD675D274AC88A680831B81DF26C92611'
+
+$termite_path = 'https://www.compuphase.com/software'
+$termite_file = 'termite-3.4.exe'
+$termite_name = 'Termite v3.4'
+$termite_hash = 'CA440B6C7F6EAA812BA5F8BF42AED86E02022CA50A1C72585168C9B671D0FE19'
+
+$azure_cli_path = 'https://azurecliprod.blob.core.windows.net/msi'
+$azure_cli_file = 'azure-cli-2.17.1.msi'
+$azure_cli_name = 'Azure CLI v2.17.1'
+$azure_cli_hash = '414B5DC8030A6E1755650CA4966417735E42D1FCC89FE9D2E41C5720BC88AEA3'
+
+$iot_explorer_path = 'https://github.com/Azure/azure-iot-explorer/releases/download/v0.13.2'
+$iot_explorer_file = 'Azure.IoT.Explorer.preview.0.13.2.msi'
+$iot_explorer_name = 'Azure IoT Explorer v0.13.2'
+$iot_explorer_hash = '6B3931F96EFA7622DB8E123E91FFA395584C75E6AC28D08A37492AE30E212F6F'
+
+echo "`nDownloading packages..."
+
+$wc = New-Object System.Net.WebClient
+$wc.Headers['User-Agent'] = "Mozilla/4.0"
+
+echo "(1/5) $gccrx_name"
+if ( -not (Test-Path "$env:TEMP\$gccrx_file") -Or ((Get-FileHash "$env:TEMP\$gccrx_file").Hash -ne $gccrx_hash))
+{
+    $wc.DownloadFile("$gccrx_path/$gccrx_file", "$env:TEMP\$gccrx_file")
+}
+
+echo "(2/5) $cmake_name"
+if ( -not (Test-Path "$env:TEMP\$cmake_file") -Or ((Get-FileHash "$env:TEMP\$cmake_file").Hash -ne $cmake_hash))
+{
+    $wc.DownloadFile("$cmake_path/$cmake_file", "$env:TEMP\$cmake_file")
+}
+
+echo "(3/5) $termite_name"
+if ( -not (Test-Path "$env:TEMP\$termite_file") -Or ((Get-FileHash "$env:TEMP\$termite_file").Hash -ne $termite_hash))
+{
+    $wc.DownloadFile("$termite_path/$termite_file", "$env:TEMP\$termite_file")
+}
+
+echo "(4/5) $azure_cli_name"
+if ( -not (Test-Path "$env:TEMP\$azure_cli_file") -Or ((Get-FileHash "$env:TEMP\$azure_cli_file").Hash -ne $azure_cli_hash))
+{
+    $wc.DownloadFile("$azure_cli_path/$azure_cli_file", "$env:TEMP\$azure_cli_file")
+}
+
+echo "(5/5) $iot_explorer_name"
+if ( -not (Test-Path "$env:TEMP\$iot_explorer_file") -Or ((Get-FileHash "$env:TEMP\$iot_explorer_file").Hash -ne $iot_explorer_hash))
+{
+    $wc.DownloadFile("$iot_explorer_path/$iot_explorer_file", "$env:TEMP\$iot_explorer_file")
+}
+
+
+echo "`nInstalling packages..."
+
+echo "(1/5) $gccrx_name"
+Start-Process -FilePath "$env:TEMP\$gccrx_file" -ArgumentList "/SILENT" -Wait
+
+echo "(2/5) $cmake_name"
+Start-Process -FilePath "$env:TEMP\$cmake_file" -ArgumentList "ADD_CMAKE_TO_PATH=System /passive" -Wait
+
+echo "(3/5) $termite_name"
+Start-Process -FilePath "$env:TEMP\$termite_file" -ArgumentList "/S" -Wait
+
+echo "(4/5) $azure_cli_name"
+Start-Process -FilePath "$env:TEMP\$azure_cli_file" -ArgumentList "/passive" -Wait
+$env:Path = [System.Environment]::GetEnvironmentVariable("Path", "Machine")
+Start-Process -FilePath "az" -ArgumentList "extension add --name azure-iot" -Wait
+
+echo "(5/5) $iot_explorer_name"
+Start-Process -FilePath "$env:TEMP\$iot_explorer_file" -ArgumentList "/passive" -Wait
+
+echo "`nInstallation complete!"
+
+echo "`nPress any key to continue..."
+Read-Host
diff --git a/tools/get-toolchain.ps1 b/tools/get-toolchain.ps1
index e31c998b..b3ccb496 100644
--- a/tools/get-toolchain.ps1
+++ b/tools/get-toolchain.ps1
@@ -1,18 +1,20 @@
 # Copyright (c) Microsoft Corporation.
 # Licensed under the MIT License.
 
-echo "`nInstalling prerequisites. Please leave the window open until the installation completes."
+[System.Net.ServicePointManager]::SecurityProtocol = [System.Net.SecurityProtocolType]::Tls12;
 
-$cmake_path = 'https://github.com/Kitware/CMake/releases/download/v3.19.2'
-$cmake_file = 'cmake-3.19.2-win32-x86.msi'
-$cmake_name = 'CMake v3.19.2'
-$cmake_hash = '7ABFEA6278B7BF3F6EB1D3B13F9DF79FD675D274AC88A680831B81DF26C92611'
+echo "`nInstalling prerequisites. Please leave the window open until the installation completes."
 
 $gccarm_path = 'https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/'
 $gccarm_file = 'gcc-arm-none-eabi-10-2020-q4-major-win32.exe'
 $gccarm_name = 'GCC-ARM 10-2020-q4-major'
 $gccarm_hash = '9754D95905288AFC787837C3B211A3E502A9EDE8A5F544CFD369C30FEA509CA5'
 
+$cmake_path = 'https://github.com/Kitware/CMake/releases/download/v3.19.2'
+$cmake_file = 'cmake-3.19.2-win32-x86.msi'
+$cmake_name = 'CMake v3.19.2'
+$cmake_hash = '7ABFEA6278B7BF3F6EB1D3B13F9DF79FD675D274AC88A680831B81DF26C92611'
+
 $termite_path = 'https://www.compuphase.com/software'
 $termite_file = 'termite-3.4.exe'
 $termite_name = 'Termite v3.4'
@@ -23,52 +25,55 @@ $azure_cli_file = 'azure-cli-2.17.1.msi'
 $azure_cli_name = 'Azure CLI v2.17.1'
 $azure_cli_hash = '414B5DC8030A6E1755650CA4966417735E42D1FCC89FE9D2E41C5720BC88AEA3'
 
-$iot_explorer_path = 'https://github.com/Azure/azure-iot-explorer/releases/download/v0.13.0'
-$iot_explorer_file = 'Azure.IoT.Explorer.preview.0.13.0.msi'
-$iot_explorer_name = 'Azure IoT Explorer v0.13.0'
-$iot_explorer_hash = 'BF8DF6BC98A3E6F8262DC435779B44E6840C568ADAB8949004546449F2400D1E'
+$iot_explorer_path = 'https://github.com/Azure/azure-iot-explorer/releases/download/v0.13.2'
+$iot_explorer_file = 'Azure.IoT.Explorer.preview.0.13.2.msi'
+$iot_explorer_name = 'Azure IoT Explorer v0.13.2'
+$iot_explorer_hash = '6B3931F96EFA7622DB8E123E91FFA395584C75E6AC28D08A37492AE30E212F6F'
 
 echo "`nDownloading packages..."
 
-echo "(1/5) $cmake_name"
-if ( -not (Test-Path "$env:TEMP\$cmake_file") -Or ((Get-FileHash "$env:TEMP\$cmake_file").Hash -ne $cmake_hash))
+$wc = New-Object System.Net.WebClient
+$wc.Headers['User-Agent'] = "Mozilla/4.0"
+
+echo "(1/5) $gccarm_name"
+if ( -not (Test-Path "$env:TEMP\$gccarm_file") -Or ((Get-FileHash "$env:TEMP\$gccarm_file").Hash -ne $gccarm_hash))
 {
-    (New-Object System.Net.WebClient).DownloadFile("$cmake_path\$cmake_file", "$env:TEMP\$cmake_file")
+    $wc.DownloadFile("$gccarm_path\$gccarm_file", "$env:TEMP\$gccarm_file")
 }
 
-echo "(2/5) $gccarm_name"
-if ( -not (Test-Path "$env:TEMP\$gccarm_file") -Or ((Get-FileHash "$env:TEMP\$gccarm_file").Hash -ne $gccarm_hash))
+echo "(2/5) $cmake_name"
+if ( -not (Test-Path "$env:TEMP\$cmake_file") -Or ((Get-FileHash "$env:TEMP\$cmake_file").Hash -ne $cmake_hash))
 {
-    (New-Object System.Net.WebClient).DownloadFile("$gccarm_path\$gccarm_file", "$env:TEMP\$gccarm_file")
+    $wc.DownloadFile("$cmake_path\$cmake_file", "$env:TEMP\$cmake_file")
 }
 
 echo "(3/5) $termite_name"
 if ( -not (Test-Path "$env:TEMP\$termite_file") -Or ((Get-FileHash "$env:TEMP\$termite_file").Hash -ne $termite_hash))
 {
-    (New-Object System.Net.WebClient).DownloadFile("$termite_path\$termite_file", "$env:TEMP\$termite_file")
+    $wc.DownloadFile("$termite_path\$termite_file", "$env:TEMP\$termite_file")
 }
 
 echo "(4/5) $azure_cli_name"
 if ( -not (Test-Path "$env:TEMP\$azure_cli_file") -Or ((Get-FileHash "$env:TEMP\$azure_cli_file").Hash -ne $azure_cli_hash))
 {
-    (New-Object System.Net.WebClient).DownloadFile("$azure_cli_path\$azure_cli_file", "$env:TEMP\$azure_cli_file")
+    $wc.DownloadFile("$azure_cli_path\$azure_cli_file", "$env:TEMP\$azure_cli_file")
 }
 
 echo "(5/5) $iot_explorer_name"
 if ( -not (Test-Path "$env:TEMP\$iot_explorer_file") -Or ((Get-FileHash "$env:TEMP\$iot_explorer_file").Hash -ne $iot_explorer_hash))
 {
-    (New-Object System.Net.WebClient).DownloadFile("$iot_explorer_path\$iot_explorer_file", "$env:TEMP\$iot_explorer_file")
+    $wc.DownloadFile("$iot_explorer_path\$iot_explorer_file", "$env:TEMP\$iot_explorer_file")
 }
 
 
 echo "`nInstalling packages..."
 
-echo "(1/5) $cmake_name"
-Start-Process -FilePath "$env:TEMP\$cmake_file" -ArgumentList "ADD_CMAKE_TO_PATH=System /passive" -Wait
-
-echo "(2/5) $gccarm_name"
+echo "(1/5) $gccarm_name"
 Start-Process -FilePath "$env:TEMP\$gccarm_file" -ArgumentList "/S /P /R" -Wait
 
+echo "(2/5) $cmake_name"
+Start-Process -FilePath "$env:TEMP\$cmake_file" -ArgumentList "ADD_CMAKE_TO_PATH=System /passive" -Wait
+
 echo "(3/5) $termite_name"
 Start-Process -FilePath "$env:TEMP\$termite_file" -ArgumentList "/S" -Wait