From f1ce504a9f9537939f5ae9a25f3a79e3c2e50ef4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 25 Jan 2022 01:11:19 +0100 Subject: [PATCH 1/2] Added basic ideas for synthesis log files. --- pyEDAA/Reports/Log/Synthesis.py | 36 +++++++++++++++++++++++++++++++++ pyEDAA/Reports/Log/__init__.py | 9 +++++++++ 2 files changed, 45 insertions(+) create mode 100644 pyEDAA/Reports/Log/Synthesis.py create mode 100644 pyEDAA/Reports/Log/__init__.py diff --git a/pyEDAA/Reports/Log/Synthesis.py b/pyEDAA/Reports/Log/Synthesis.py new file mode 100644 index 00000000..52c31130 --- /dev/null +++ b/pyEDAA/Reports/Log/Synthesis.py @@ -0,0 +1,36 @@ +from typing import List + +from pyTooling.Decorators import export +from pyEDAA.ProjectModel import File + +from pyEDAA.Reports.Log import Entry as Log_Entry + + +@export +class SourceCodePosition: + """ + Represents a position in a source code file as a ragged 2 dimensional ``Row``:``Column`` position. + """ + + Row : int #: Row or line in the document + Column : int #: Column in the document + + def __init__(self, row : int, column : int): + self.Row = row + self.Column = column + + def __str__(self): + """Returns a string representation.""" + return "(line: {0}, col: {1})".format(self.Row, self.Column) + + def __repr__(self): + """Returns a string representation in ``row:col`` format.""" + return "{0}:{1})".format(self.Row, self.Column) + + +@export +class Entry(Log_Entry): + _file: File + _position: SourceCodePosition + _codeObject: str + _linkedEntries: List["Entry"] diff --git a/pyEDAA/Reports/Log/__init__.py b/pyEDAA/Reports/Log/__init__.py new file mode 100644 index 00000000..04ea6d03 --- /dev/null +++ b/pyEDAA/Reports/Log/__init__.py @@ -0,0 +1,9 @@ +from pyTooling.Decorators import export + +from pyEDAA.Reports import Severity + + +@export +class Entry: + _severity: Severity + _message: str From 03265b1ad48b40e44b448dd51688fabc32717b81 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 25 Jan 2022 01:12:01 +0100 Subject: [PATCH 2/2] Added example synthesis and implementation log files from Vivado. --- tests/data/Vivado/StopWatch.vdi | 658 ++++++++++++++++++++++++++++++++ tests/data/Vivado/StopWatch.vds | 266 +++++++++++++ 2 files changed, 924 insertions(+) create mode 100644 tests/data/Vivado/StopWatch.vdi create mode 100644 tests/data/Vivado/StopWatch.vds diff --git a/tests/data/Vivado/StopWatch.vdi b/tests/data/Vivado/StopWatch.vdi new file mode 100644 index 00000000..6a43586e --- /dev/null +++ b/tests/data/Vivado/StopWatch.vdi @@ -0,0 +1,658 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Thu Dec 9 12:44:48 2021 +# Process ID: 936 +# Current directory: C:/Training/Solutions/StopWatch/project/StopWatch.runs/impl_StopWatch +# Command line: vivado.exe -log toplevel.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source toplevel.tcl -notrace +# Log file: C:/Training/Solutions/StopWatch/project/StopWatch.runs/impl_StopWatch/toplevel.vdi +# Journal file: C:/Training/Solutions/StopWatch/project/StopWatch.runs/impl_StopWatch\vivado.jou +# Running On: Paebbels-Laptop, OS: Windows, CPU Frequency: 2400 MHz, CPU Physical cores: 8, Host memory: 34073 MB +#----------------------------------------------------------- +source toplevel.tcl -notrace +Command: link_design -top toplevel -part xc7a100tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.488 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2021.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Training/Solutions/StopWatch/xdc/Button.xdc] +Finished Parsing XDC File [C:/Training/Solutions/StopWatch/xdc/Button.xdc] +Parsing XDC File [C:/Training/Solutions/StopWatch/xdc/Clock.xdc] +Finished Parsing XDC File [C:/Training/Solutions/StopWatch/xdc/Clock.xdc] +Parsing XDC File [C:/Training/Solutions/StopWatch/xdc/Display.xdc] +Finished Parsing XDC File [C:/Training/Solutions/StopWatch/xdc/Display.xdc] +Parsing XDC File [C:/Training/Solutions/StopWatch/xdc/Reset.xdc] +Finished Parsing XDC File [C:/Training/Solutions/StopWatch/xdc/Reset.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.488 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:15 . Memory (MB): peak = 1261.488 ; gain = 0.000 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.999 . Memory (MB): peak = 1261.488 ; gain = 0.000 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 15c60762e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1446.242 ; gain = 184.754 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1c60cb46b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1736.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 1 cells and removed 1 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1c60cb46b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1736.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1bc3c427c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1736.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1bc3c427c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1736.844 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 1bc3c427c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1736.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1bc3c427c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1736.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 1 | 1 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1736.844 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1e8485c86 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1736.844 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1e8485c86 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1736.844 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1e8485c86 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1736.844 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1736.844 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1e8485c86 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1736.844 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1736.844 ; gain = 475.355 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1736.844 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Training/Solutions/StopWatch/project/StopWatch.runs/impl_StopWatch/toplevel_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file toplevel_drc_opted.rpt -pb toplevel_drc_opted.pb -rpx toplevel_drc_opted.rpx +Command: report_drc -file toplevel_drc_opted.rpt -pb toplevel_drc_opted.pb -rpx toplevel_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Training/Solutions/StopWatch/project/StopWatch.runs/impl_StopWatch/toplevel_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 141eab3fe + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +CRITICAL WARNING: [Place 30-722] Terminal 'NexysA7_GPIO_Button_Reset_n' has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O +CRITICAL WARNING: [Place 30-722] Terminal 'NexysA7_GPIO_Seg7_Anode_n[4]' has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O +CRITICAL WARNING: [Place 30-722] Terminal 'NexysA7_GPIO_Seg7_Anode_n[5]' has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O +CRITICAL WARNING: [Place 30-722] Terminal 'NexysA7_GPIO_Seg7_Anode_n[6]' has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O +CRITICAL WARNING: [Place 30-722] Terminal 'NexysA7_GPIO_Seg7_Anode_n[7]' has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O +CRITICAL WARNING: [Place 30-722] Terminal 'NexysA7_GPIO_Seg7_Cathode_n[7]' has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a85433d6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.405 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 120fa0983 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.509 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 120fa0983 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.511 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 120fa0983 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.515 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 16473cb92 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.614 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: f81926f9 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.667 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: f81926f9 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.668 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 Physical Synthesis In Placer +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 0 net or LUT. Breaked 0 LUT, combined 0 existing LUT and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 0 | 0 | 0 | 4 | 00:00:00 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.1 Physical Synthesis In Placer | Checksum: 1a5086514 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Phase 2.4 Global Placement Core | Checksum: fe11b632 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Phase 2 Global Placement | Checksum: fe11b632 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 164cb04fa + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 19225f8d6 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 202e3edde + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 20906db97 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 10cf6f244 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 192dbd8e3 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 18cb86c0e + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 18cb86c0e + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 1e63448eb + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=4.676 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 20026beaa + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1775.949 ; gain = 0.000 +INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. +Ending Physical Synthesis Task | Checksum: 1b2c08939 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Phase 4.1.1.1 BUFG Insertion | Checksum: 1e63448eb + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=4.676. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 129152a8c + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Phase 4.1 Post Commit Optimization | Checksum: 129152a8c + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 129152a8c + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 1x1| +|___________|___________________|___________________| +| South| 1x1| 1x1| +|___________|___________________|___________________| +| East| 1x1| 1x1| +|___________|___________________|___________________| +| West| 1x1| 1x1| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 129152a8c + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Phase 4.3 Placer Reporting | Checksum: 129152a8c + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1775.949 ; gain = 0.000 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19c924192 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Ending Placer Task | Checksum: 17fdff7b7 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1775.949 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +60 Infos, 0 Warnings, 6 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1775.949 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Training/Solutions/StopWatch/project/StopWatch.runs/impl_StopWatch/toplevel_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file toplevel_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1775.949 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file toplevel_utilization_placed.rpt -pb toplevel_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file toplevel_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1775.949 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +69 Infos, 0 Warnings, 6 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1782.195 ; gain = 6.246 +INFO: [Common 17-1381] The checkpoint 'C:/Training/Solutions/StopWatch/project/StopWatch.runs/impl_StopWatch/toplevel_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC PLIO-8] Placement Constraints Check for IO constraints: Terminal NexysA7_GPIO_Button_Reset_n has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O. +WARNING: [DRC PLIO-8] Placement Constraints Check for IO constraints: Terminal NexysA7_GPIO_Seg7_Anode_n[4] has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O. +WARNING: [DRC PLIO-8] Placement Constraints Check for IO constraints: Terminal NexysA7_GPIO_Seg7_Anode_n[5] has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O. +WARNING: [DRC PLIO-8] Placement Constraints Check for IO constraints: Terminal NexysA7_GPIO_Seg7_Anode_n[6] has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O. +WARNING: [DRC PLIO-8] Placement Constraints Check for IO constraints: Terminal NexysA7_GPIO_Seg7_Anode_n[7] has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O. +WARNING: [DRC PLIO-8] Placement Constraints Check for IO constraints: Terminal NexysA7_GPIO_Seg7_Cathode_n[7] has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O. +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 6 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: 8c6b32c9 ConstDB: 0 ShapeSum: f374c4ee RouteDB: 0 +Post Restoration Checksum: NetGraph: e7798107 NumContArr: 2c4d5535 Constraints: 0 Timing: 0 +Phase 1 Build RT Design | Checksum: 113c6d63c + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1904.328 ; gain = 113.074 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 113c6d63c + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1904.328 ; gain = 113.074 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: 113c6d63c + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1910.316 ; gain = 119.062 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: 113c6d63c + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1910.316 ; gain = 119.062 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 225a6261b + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1925.797 ; gain = 134.543 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.251 | TNS=0.000 | WHS=-0.195 | THS=-1.991 | + + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 117 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 117 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 1505a157f + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 + +Phase 3 Initial Routing + +Phase 3.1 Global Routing +Phase 3.1 Global Routing | Checksum: 1505a157f + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 +Phase 3 Initial Routing | Checksum: 22237be79 + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.472 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 155128e86 + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 +Phase 4 Rip-up And Reroute | Checksum: 155128e86 + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp + +Phase 5.1.1 Update Timing +Phase 5.1.1 Update Timing | Checksum: 106fc98af + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.551 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.1 Delay CleanUp | Checksum: 106fc98af + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 106fc98af + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 +Phase 5 Delay and Skew Optimization | Checksum: 106fc98af + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 1d07eecd3 + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.551 | TNS=0.000 | WHS=0.156 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 1dc5b7ce0 + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 +Phase 6 Post Hold Fix | Checksum: 1dc5b7ce0 + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.025025 % + Global Horizontal Routing Utilization = 0.0131429 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: 1c1b205d4 + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1c1b205d4 + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 1bfee0fe8 + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=4.551 | TNS=0.000 | WHS=0.156 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 1bfee0fe8 + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 1926.840 ; gain = 135.586 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +84 Infos, 6 Warnings, 6 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 1926.840 ; gain = 144.645 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1936.367 ; gain = 9.527 +INFO: [Common 17-1381] The checkpoint 'C:/Training/Solutions/StopWatch/project/StopWatch.runs/impl_StopWatch/toplevel_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file toplevel_drc_routed.rpt -pb toplevel_drc_routed.pb -rpx toplevel_drc_routed.rpx +Command: report_drc -file toplevel_drc_routed.rpt -pb toplevel_drc_routed.pb -rpx toplevel_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Training/Solutions/StopWatch/project/StopWatch.runs/impl_StopWatch/toplevel_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file toplevel_methodology_drc_routed.rpt -pb toplevel_methodology_drc_routed.pb -rpx toplevel_methodology_drc_routed.rpx +Command: report_methodology -file toplevel_methodology_drc_routed.rpt -pb toplevel_methodology_drc_routed.pb -rpx toplevel_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Training/Solutions/StopWatch/project/StopWatch.runs/impl_StopWatch/toplevel_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file toplevel_power_routed.rpt -pb toplevel_power_summary_routed.pb -rpx toplevel_power_routed.rpx +Command: report_power -file toplevel_power_routed.rpt -pb toplevel_power_summary_routed.pb -rpx toplevel_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +96 Infos, 6 Warnings, 6 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file toplevel_route_status.rpt -pb toplevel_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file toplevel_timing_summary_routed.rpt -pb toplevel_timing_summary_routed.pb -rpx toplevel_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [runtcl-4] Executing : report_incremental_reuse -file toplevel_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file toplevel_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file toplevel_bus_skew_routed.rpt -pb toplevel_bus_skew_routed.pb -rpx toplevel_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force toplevel.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./toplevel.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Common 17-83] Releasing license: Implementation +11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 2404.438 ; gain = 445.016 +INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 12:46:18 2021... diff --git a/tests/data/Vivado/StopWatch.vds b/tests/data/Vivado/StopWatch.vds new file mode 100644 index 00000000..d428b85e --- /dev/null +++ b/tests/data/Vivado/StopWatch.vds @@ -0,0 +1,266 @@ +#----------------------------------------------------------- +# Vivado v2021.2 (64-bit) +# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 +# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 +# Start of session at: Thu Dec 9 12:44:01 2021 +# Process ID: 30416 +# Current directory: C:/Training/Solutions/StopWatch/project/StopWatch.runs/synth_StopWatch +# Command line: vivado.exe -log toplevel.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source toplevel.tcl +# Log file: C:/Training/Solutions/StopWatch/project/StopWatch.runs/synth_StopWatch/toplevel.vds +# Journal file: C:/Training/Solutions/StopWatch/project/StopWatch.runs/synth_StopWatch\vivado.jou +# Running On: Paebbels-Laptop, OS: Windows, CPU Frequency: 2400 MHz, CPU Physical cores: 8, Host memory: 34073 MB +#----------------------------------------------------------- +source toplevel.tcl -notrace +Command: read_checkpoint -auto_incremental -incremental C:/Training/Solutions/StopWatch/project/StopWatch.srcs/utils_1/imports/synth_1/toplevel.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from C:/Training/Solutions/StopWatch/project/StopWatch.srcs/utils_1/imports/synth_1/toplevel.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes +Command: synth_design -top toplevel -part xc7a100tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 10572 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'toplevel' [C:/Training/Solutions/StopWatch/src/toplevel.StopWatch.vhdl:24] +INFO: [Synth 8-638] synthesizing module 'Debouncer' [C:/Training/Solutions/StopWatch/src/Debouncer.vhdl:23] + Parameter CLOCK_FREQ bound to: 64'b0000000000000000000000000000000000000101111101011110000100000000 + Parameter BITS bound to: 2 - type: integer +INFO: [Synth 8-256] done synthesizing module 'Debouncer' (1#1) [C:/Training/Solutions/StopWatch/src/Debouncer.vhdl:23] +INFO: [Synth 8-638] synthesizing module 'Stopwatch' [C:/Training/Solutions/StopWatch/src/StopWatch.vhdl:28] + Parameter CLOCK_FREQ bound to: 64'b0000000000000000000000000000000000000101111101011110000100000000 + Parameter TIMEBASE bound to: 64'b0000000000000000000010010001100001001110011100101010000000000000 + Parameter CONFIG bound to: 128'b00000000000000000000000000010100000000000000000000000000000011000000000000000000000000000001010000000000000000000000000000001100 +INFO: [Synth 8-226] default block is never used [C:/Training/Solutions/StopWatch/src/StopWatch.vhdl:59] +INFO: [Synth 8-638] synthesizing module 'Counter' [C:/Training/Solutions/StopWatch/src/Counter.vhdl:24] + Parameter MODULO bound to: 62 - type: integer + Parameter BITS bound to: 1 - type: integer +INFO: [Synth 8-256] done synthesizing module 'Counter' (2#1) [C:/Training/Solutions/StopWatch/src/Counter.vhdl:24] +INFO: [Synth 8-638] synthesizing module 'Counter__parameterized0' [C:/Training/Solutions/StopWatch/src/Counter.vhdl:24] + Parameter MODULO bound to: 10 - type: integer + Parameter BITS bound to: 4 - type: integer +INFO: [Synth 8-256] done synthesizing module 'Counter__parameterized0' (2#1) [C:/Training/Solutions/StopWatch/src/Counter.vhdl:24] +INFO: [Synth 8-638] synthesizing module 'Counter__parameterized1' [C:/Training/Solutions/StopWatch/src/Counter.vhdl:24] + Parameter MODULO bound to: 6 - type: integer + Parameter BITS bound to: 4 - type: integer +INFO: [Synth 8-256] done synthesizing module 'Counter__parameterized1' (2#1) [C:/Training/Solutions/StopWatch/src/Counter.vhdl:24] +INFO: [Synth 8-256] done synthesizing module 'Stopwatch' (3#1) [C:/Training/Solutions/StopWatch/src/StopWatch.vhdl:28] +INFO: [Synth 8-638] synthesizing module 'seg7_Display' [C:/Training/Solutions/StopWatch/src/seg7_Display.vhdl:27] + Parameter CLOCK_FREQ bound to: 64'b0000000000000000000000000000000000000101111101011110000100000000 + Parameter DIGITS bound to: 4 - type: integer +INFO: [Synth 8-638] synthesizing module 'Counter__parameterized2' [C:/Training/Solutions/StopWatch/src/Counter.vhdl:24] + Parameter MODULO bound to: 100000 - type: integer +INFO: [Synth 8-256] done synthesizing module 'Counter__parameterized2' (3#1) [C:/Training/Solutions/StopWatch/src/Counter.vhdl:24] +INFO: [Synth 8-638] synthesizing module 'Counter__parameterized3' [C:/Training/Solutions/StopWatch/src/Counter.vhdl:24] + Parameter MODULO bound to: 4 - type: integer + Parameter BITS bound to: 2 - type: integer +INFO: [Synth 8-256] done synthesizing module 'Counter__parameterized3' (3#1) [C:/Training/Solutions/StopWatch/src/Counter.vhdl:24] +INFO: [Synth 8-638] synthesizing module 'seg7_Encoder' [C:/Training/Solutions/StopWatch/src/seg7_Encoder.vhdl:17] +INFO: [Synth 8-226] default block is never used [C:/Training/Solutions/StopWatch/src/seg7_Encoder.vhdl:23] +INFO: [Synth 8-256] done synthesizing module 'seg7_Encoder' (4#1) [C:/Training/Solutions/StopWatch/src/seg7_Encoder.vhdl:17] +INFO: [Synth 8-256] done synthesizing module 'seg7_Display' (5#1) [C:/Training/Solutions/StopWatch/src/seg7_Display.vhdl:27] +INFO: [Synth 8-256] done synthesizing module 'toplevel' (6#1) [C:/Training/Solutions/StopWatch/src/toplevel.StopWatch.vhdl:24] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: [Synth 8-802] inferred FSM for state register 'State_reg' in module 'Stopwatch' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + st_reset | 0001 | 00 + st_idle | 0010 | 01 + st_counting | 0100 | 10 + st_pause | 1000 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'State_reg' using encoding 'one-hot' in module 'Stopwatch' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 9 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 + 2 Input 4 Bit Adders := 2 + 2 Input 3 Bit Adders := 2 + 2 Input 2 Bit Adders := 1 ++---Registers : + 9 Bit Registers := 2 + 8 Bit Registers := 2 + 6 Bit Registers := 1 + 4 Bit Registers := 2 + 3 Bit Registers := 2 + 2 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 4 Input 4 Bit Muxes := 2 + 2 Input 4 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 6 + 4 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 5| +|3 |LUT1 | 8| +|4 |LUT2 | 11| +|5 |LUT3 | 13| +|6 |LUT4 | 23| +|7 |LUT5 | 11| +|8 |LUT6 | 14| +|9 |FDRE | 63| +|10 |FDSE | 12| +|11 |IBUF | 3| +|12 |OBUF | 16| ++------+-------+------+ + +Report Instance Areas: ++------+-----------------------+--------------------------+------+ +| |Instance |Module |Cells | ++------+-----------------------+--------------------------+------+ +|1 |top | | 180| +|2 | deb |Debouncer | 44| +|3 | display |seg7_Display | 35| +|4 | cnt1khZ |Counter__parameterized2 | 27| +|5 | cntDigitSelect |Counter__parameterized3 | 8| +|6 | sw |Stopwatch | 69| +|7 | TimeBaseCnt |Counter | 19| +|8 | \genDigits[0].cnt |Counter__parameterized0 | 10| +|9 | \genDigits[1].cnt |Counter__parameterized1 | 7| +|10 | \genDigits[2].cnt |Counter__parameterized0_0 | 10| +|11 | \genDigits[3].cnt |Counter__parameterized1_1 | 16| ++------+-----------------------+--------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1260.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1260.668 ; gain = 0.000 +Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1260.668 ; gain = 0.000 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1260.668 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1260.668 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete, checksum: 66137fa +INFO: [Common 17-83] Releasing license: Synthesis +39 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1260.668 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Training/Solutions/StopWatch/project/StopWatch.runs/synth_StopWatch/toplevel.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file toplevel_utilization_synth.rpt -pb toplevel_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 12:44:40 2021...