diff --git a/scripts/run_rtl_repair_experiment.py b/scripts/run_rtl_repair_experiment.py
index d7aed68..58bfd34 100755
--- a/scripts/run_rtl_repair_experiment.py
+++ b/scripts/run_rtl_repair_experiment.py
@@ -30,7 +30,7 @@
 # the FPGA benchmarks all have testbenches from Verilator which assume a zero init
 _init_fpga = 'zero'
 # the FPGA benchmarks benefit from running with yices2
-_solver_fpga = 'yices2'
+_solver_fpga = 'bitwuzla'
 
 @dataclass
 class ExpConfig: