From 26121bfebc49cc2be96c1dbe04473c9b3691eeb5 Mon Sep 17 00:00:00 2001 From: Greg Burns Date: Tue, 5 Mar 2024 13:19:39 -0800 Subject: [PATCH] Runtime DMA region configuration The non-cached DMA region was hardcoded with size 32K, system.cpp had to be edited to increase this. With this change the non-cached region can be configured solely by changing the size in the linker script. Signed-off-by: Greg Burns --- core/STM32H750IB_flash.lds | 17 ++++++++++++++++- core/STM32H750IB_qspi.lds | 4 ++-- core/STM32H750IB_sram.lds | 4 ++-- src/sys/system.cpp | 34 ++++++++++++++++++++++++++++++++-- 4 files changed, 52 insertions(+), 7 deletions(-) diff --git a/core/STM32H750IB_flash.lds b/core/STM32H750IB_flash.lds index 0756574af..1a183b04a 100644 --- a/core/STM32H750IB_flash.lds +++ b/core/STM32H750IB_flash.lds @@ -10,7 +10,8 @@ MEMORY FLASH (RX) : ORIGIN = 0x08000000, LENGTH = 128K DTCMRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 128K SRAM (RWX) : ORIGIN = 0x24000000, LENGTH = 512K - RAM_D2 (RWX) : ORIGIN = 0x30000000, LENGTH = 288K + RAM_D2_DMA (RWX) : ORIGIN = 0x30000000, LENGTH = 32K + RAM_D2 (RWX) : ORIGIN = ORIGIN(RAM_D2_DMA) + LENGTH(RAM_D2_DMA), LENGTH = 256K - LENGTH(RAM_D2_DMA) RAM_D3 (RWX) : ORIGIN = 0x38000000, LENGTH = 64K BACKUP_SRAM (RWX) : ORIGIN = 0x38800000, LENGTH = 4K ITCMRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 64K @@ -139,6 +140,20 @@ SECTIONS PROVIDE(__dtcmram_bss_end__ = _edtcmram_bss); } > DTCMRAM + .sram1_bss (NOLOAD) : + { + . = ALIGN(4); + _ssram1_bss = .; + + PROVIDE(__sram1_bss_start__ = _sram1_bss); + *(.sram1_bss) + *(.sram1_bss*) + . = ALIGN(4); + _esram1_bss = .; + + PROVIDE(__sram1_bss_end__ = _esram1_bss); + } > RAM_D2_DMA + .sram1_bss (NOLOAD) : { . = ALIGN(4); diff --git a/core/STM32H750IB_qspi.lds b/core/STM32H750IB_qspi.lds index d772e9f32..2188429ec 100644 --- a/core/STM32H750IB_qspi.lds +++ b/core/STM32H750IB_qspi.lds @@ -12,7 +12,7 @@ MEMORY DTCMRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 128K SRAM (RWX) : ORIGIN = 0x24000000, LENGTH = 512K RAM_D2_DMA (RWX) : ORIGIN = 0x30000000, LENGTH = 32K - RAM_D2 (RWX) : ORIGIN = 0x30008000, LENGTH = 256K + RAM_D2 (RWX) : ORIGIN = ORIGIN(RAM_D2_DMA) + LENGTH(RAM_D2_DMA), LENGTH = 256K - LENGTH(RAM_D2_DMA) RAM_D3 (RWX) : ORIGIN = 0x38000000, LENGTH = 64K BACKUP_SRAM (RWX) : ORIGIN = 0x38800000, LENGTH = 4K ITCMRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 64K @@ -268,4 +268,4 @@ SECTIONS libgcc.a ( * ) } -} \ No newline at end of file +} diff --git a/core/STM32H750IB_sram.lds b/core/STM32H750IB_sram.lds index 2e711ec97..01c565542 100644 --- a/core/STM32H750IB_sram.lds +++ b/core/STM32H750IB_sram.lds @@ -11,7 +11,7 @@ MEMORY DTCMRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 128K SRAM (RWX) : ORIGIN = 0x24000000, LENGTH = 512K - 32K RAM_D2_DMA (RWX) : ORIGIN = 0x30000000, LENGTH = 32K - RAM_D2 (RWX) : ORIGIN = 0x30008000, LENGTH = 256K + RAM_D2 (RWX) : ORIGIN = ORIGIN(RAM_D2_DMA) + LENGTH(RAM_D2_DMA), LENGTH = 256K - LENGTH(RAM_D2_DMA) RAM_D3 (RWX) : ORIGIN = 0x38000000, LENGTH = 64K BACKUP_SRAM (RWX) : ORIGIN = 0x38800000, LENGTH = 4K ITCMRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 64K @@ -266,4 +266,4 @@ SECTIONS libgcc.a ( * ) } -} \ No newline at end of file +} diff --git a/src/sys/system.cpp b/src/sys/system.cpp index bdb3fc3f0..5f11c84f9 100644 --- a/src/sys/system.cpp +++ b/src/sys/system.cpp @@ -518,14 +518,44 @@ void System::ConfigureClocks() HAL_PWREx_EnableUSBVoltageDetector(); } +extern "C" +{ + // Non-cacheable RAM D2 address range + extern uint32_t _ssram1_bss, _esram1_bss; +} + +// Map a region size in byte to an appropriate value +static uint8_t MPURegionSize(void* sAddr, void* eAddr) +{ + uint32_t sz = (uint8_t*)eAddr - (uint8_t*)sAddr; + if(sz <= 1 * 1024) + return MPU_REGION_SIZE_1KB; + if(sz <= 2 * 1024) + return MPU_REGION_SIZE_2KB; + if(sz <= 4 * 1024) + return MPU_REGION_SIZE_4KB; + if(sz <= 8 * 1024) + return MPU_REGION_SIZE_8KB; + if(sz <= 16 * 1024) + return MPU_REGION_SIZE_16KB; + if(sz <= 32 * 1024) + return MPU_REGION_SIZE_32KB; + if(sz <= 64 * 1024) + return MPU_REGION_SIZE_64KB; + if(sz <= 128 * 1024) + return MPU_REGION_SIZE_128KB; + else + return MPU_REGION_SIZE_256KB; +} + void System::ConfigureMpu() { MPU_Region_InitTypeDef MPU_InitStruct; HAL_MPU_Disable(); // Configure RAM D2 (SRAM1) as non cacheable MPU_InitStruct.Enable = MPU_REGION_ENABLE; - MPU_InitStruct.BaseAddress = 0x30000000; - MPU_InitStruct.Size = MPU_REGION_SIZE_32KB; + MPU_InitStruct.BaseAddress = (uint32_t)&_ssram1_bss; + MPU_InitStruct.Size = MPURegionSize(&_ssram1_bss, &_esram1_bss); MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;