From c94870156c02e895a3b9b45ee568a02201e30408 Mon Sep 17 00:00:00 2001
From: Elena Frank <elena.frank@protonmail.com>
Date: Fri, 15 Mar 2024 09:36:02 +0100
Subject: [PATCH] fixup! threads: support for riscv (esp32c3 only)

add safety doc comment for `riscv::sched`
---
 src/riot-rs-threads/src/arch/riscv.rs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/riot-rs-threads/src/arch/riscv.rs b/src/riot-rs-threads/src/arch/riscv.rs
index 68aafe0d9..d7982415c 100644
--- a/src/riot-rs-threads/src/arch/riscv.rs
+++ b/src/riot-rs-threads/src/arch/riscv.rs
@@ -111,6 +111,14 @@ fn FROM_CPU_INTR3(trap_frame: &mut TrapFrame) {
     }
 }
 
+/// Probes the runqueue for the next thread and switches context if needed.
+///
+/// # Safety
+///
+/// This method might switch the current register state that is saved in the
+/// `trap_frame`.
+/// It should only be called from inside the trap handler that is responsible for
+/// context switching.
 unsafe fn sched(trap_frame: &mut TrapFrame) {
     unsafe {
         let cs = CriticalSection::new();