bone_fpga_4l_pg3.sch

v 20090830 2
C 39500 39500 0 0 0 EMBEDDEDtitle-bordered-C.sym
[
B 39500 39500 22000 17000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 53900 41000 5 10 0 0 0 0 1
graphical=1
L 57200 40300 57200 39700 15 0 0 0 -1 -1
T 53800 40100 15 8 1 0 0 0 1
FILE:
T 57300 40100 15 8 1 0 0 0 1
REVISION:
T 57300 39800 15 8 1 0 0 0 1
DRAWN BY: 
T 53800 39800 15 8 1 0 0 0 1
PAGE
T 55500 39800 15 8 1 0 0 0 1
OF
T 53800 40400 15 8 1 0 0 0 1
TITLE
B 53700 39700 7600 1400 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 53700 40300 61300 40300 15 0 0 0 -1 -1
L 39700 49500 39500 49500 15 0 0 0 -1 -1
L 39700 47500 39500 47500 15 0 0 0 -1 -1
L 39700 45500 39500 45500 15 0 0 0 -1 -1
L 39700 43500 39500 43500 15 0 0 0 -1 -1
L 39700 41500 39500 41500 15 0 0 0 -1 -1
L 41500 39700 41500 39500 15 0 0 0 -1 -1
L 43500 39700 43500 39500 15 0 0 0 -1 -1
L 45500 39700 45500 39500 15 0 0 0 -1 -1
L 47500 39700 47500 39500 15 0 0 0 -1 -1
L 49500 39700 49500 39500 15 0 0 0 -1 -1
L 51500 39700 51500 39500 15 0 0 0 -1 -1
L 53500 39700 53500 39500 15 0 0 0 -1 -1
L 55500 39700 55500 39500 15 0 0 0 -1 -1
B 39700 39700 21600 16600 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 39600 48500 15 8 1 0 0 4 1
E
T 39600 46500 15 8 1 0 0 4 1
D
T 39600 44500 15 8 1 0 0 4 1
C
T 39600 42500 15 8 1 0 0 4 1
B
T 39600 40500 15 8 1 0 0 4 1
A
T 40500 39600 15 8 1 0 0 4 1
1
T 42500 39600 15 8 1 0 0 4 1
2
T 44500 39600 15 8 1 0 0 4 1
3
T 46500 39600 15 8 1 0 0 4 1
4
T 48500 39600 15 8 1 0 0 4 1
5
T 50500 39600 15 8 1 0 0 4 1
6
T 52500 39600 15 8 1 0 0 4 1
7
T 54500 39600 15 8 1 0 0 4 1
8
L 39700 51500 39500 51500 15 0 0 0 -1 -1
L 39700 53500 39500 53500 15 0 0 0 -1 -1
L 39700 55500 39500 55500 15 0 0 0 -1 -1
T 39600 50500 15 8 1 0 0 4 1
F
T 39600 52500 15 8 1 0 0 4 1
G
T 39600 54500 15 8 1 0 0 4 1
H
T 39600 56000 15 8 1 0 0 4 1
I
L 61500 55500 61300 55500 15 0 0 0 -1 -1
L 61500 53500 61300 53500 15 0 0 0 -1 -1
L 61500 51500 61300 51500 15 0 0 0 -1 -1
L 61500 49500 61300 49500 15 0 0 0 -1 -1
L 61500 47500 61300 47500 15 0 0 0 -1 -1
L 61500 45500 61300 45500 15 0 0 0 -1 -1
L 61500 43500 61300 43500 15 0 0 0 -1 -1
L 61500 41500 61300 41500 15 0 0 0 -1 -1
T 61400 56000 15 8 1 0 0 4 1
I
T 61400 54500 15 8 1 0 0 4 1
H
T 61400 52500 15 8 1 0 0 4 1
G
T 61400 50500 15 8 1 0 0 4 1
F
T 61400 48500 15 8 1 0 0 4 1
E
T 61400 46500 15 8 1 0 0 4 1
D
T 61400 44500 15 8 1 0 0 4 1
C
T 61400 42500 15 8 1 0 0 4 1
B
T 61400 40500 15 8 1 0 0 4 1
A
L 59500 39700 59500 39500 15 0 0 0 -1 -1
L 57500 39700 57500 39500 15 0 0 0 -1 -1
T 60500 39600 15 8 1 0 0 4 1
11
T 58500 39600 15 8 1 0 0 4 1
10
T 56500 39600 15 8 1 0 0 4 1
9
L 41500 56500 41500 56300 15 0 0 0 -1 -1
L 43500 56500 43500 56300 15 0 0 0 -1 -1
L 45500 56500 45500 56300 15 0 0 0 -1 -1
L 47500 56500 47500 56300 15 0 0 0 -1 -1
L 49500 56500 49500 56300 15 0 0 0 -1 -1
L 51500 56500 51500 56300 15 0 0 0 -1 -1
L 53500 56500 53500 56300 15 0 0 0 -1 -1
L 55500 56500 55500 56300 15 0 0 0 -1 -1
L 57500 56500 57500 56300 15 0 0 0 -1 -1
L 59500 56500 59500 56300 15 0 0 0 -1 -1
T 40500 56400 15 8 1 0 0 4 1
1
T 42500 56400 15 8 1 0 0 4 1
2
T 44500 56400 15 8 1 0 0 4 1
3
T 46500 56400 15 8 1 0 0 4 1
4
T 48500 56400 15 8 1 0 0 4 1
5
T 50500 56400 15 8 1 0 0 4 1
6
T 52500 56400 15 8 1 0 0 4 1
7
T 54500 56400 15 8 1 0 0 4 1
8
T 56500 56400 15 8 1 0 0 4 1
9
T 58500 56400 15 8 1 0 0 4 1
10
T 60500 56400 15 8 1 0 0 4 1
11
]
{
T 58300 39800 5 10 1 1 0 0 1
author=Eric Brombaugh
T 54300 40000 5 10 1 1 0 0 1
file=bone_fpga_4l_pg3.sch
}
C 56700 46700 1 180 1 EMBEDDEDoutput-1.sym
[
T 56800 46400 5 10 0 0 180 6 1
device=OUTPUT
L 57400 46700 56900 46700 3 0 0 0 -1 -1
L 57500 46600 57400 46700 3 0 0 0 -1 -1
L 57400 46500 57500 46600 3 0 0 0 -1 -1
L 56900 46500 57400 46500 3 0 0 0 -1 -1
L 56900 46500 56900 46700 3 0 0 0 -1 -1
P 56700 46600 56900 46600 1 0 0
{
T 56950 46650 5 6 0 1 180 6 1
pinnumber=1
T 56950 46650 5 6 0 0 180 6 1
pinseq=1
}
]
{
T 56800 46400 5 10 0 0 180 6 1
device=OUTPUT
T 58700 46700 5 10 1 1 180 0 1
value=FPGA_DONE
T 56700 46700 5 10 0 1 0 6 1
net=FPGA_DONE:1
}
C 47500 53200 1 270 1 EMBEDDEDoutput-1.sym
[
T 47800 53300 5 10 0 0 270 6 1
device=OUTPUT
L 47500 53900 47500 53400 3 0 0 0 -1 -1
L 47600 54000 47500 53900 3 0 0 0 -1 -1
L 47700 53900 47600 54000 3 0 0 0 -1 -1
L 47700 53400 47700 53900 3 0 0 0 -1 -1
L 47700 53400 47500 53400 3 0 0 0 -1 -1
P 47600 53200 47600 53400 1 0 0
{
T 47550 53450 5 6 0 1 270 6 1
pinnumber=1
T 47550 53450 5 6 0 0 270 6 1
pinseq=1
}
]
{
T 47800 53300 5 10 0 0 270 6 1
device=OUTPUT
T 47700 55200 5 10 1 1 90 6 1
value=FPGA_PROG
T 47500 53200 5 10 0 1 90 6 1
net=FPGA_PROG:1
}
C 40500 54000 1 0 0 EMBEDDEDconnector6-1.sym
[
T 40600 56000 8 10 0 1 0 0 1
refdes=CONN?
T 42300 55800 5 10 0 0 0 0 1
device=CONNECTOR_6
B 40500 54000 500 1900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 41900 54200 41000 54200 3 0 0 0 -1 -1
L 41900 54500 41000 54500 3 0 0 0 -1 -1
L 41900 54800 41000 54800 3 0 0 0 -1 -1
L 41900 55100 41000 55100 3 0 0 0 -1 -1
L 41900 55400 41000 55400 3 0 0 0 -1 -1
L 41900 55700 41000 55700 3 0 0 0 -1 -1
P 41900 54500 42200 54500 1 0 1
{
T 40750 54450 5 8 1 1 0 0 1
pinnumber=5
T 40750 54450 5 8 0 0 0 0 1
pinseq=5
T 40750 54450 5 8 0 1 0 0 1
pinlabel=5
T 40750 54450 5 8 0 1 0 0 1
pintype=pas
}
P 41900 55100 42200 55100 1 0 1
{
T 40750 55050 5 8 1 1 0 0 1
pinnumber=3
T 40750 55050 5 8 0 0 0 0 1
pinseq=3
T 40750 55050 5 8 0 1 0 0 1
pinlabel=3
T 40750 55050 5 8 0 1 0 0 1
pintype=pas
}
P 41900 55700 42200 55700 1 0 1
{
T 40750 55650 5 8 1 1 0 0 1
pinnumber=1
T 40750 55650 5 8 0 0 0 0 1
pinseq=1
T 40750 55650 5 8 0 1 0 0 1
pinlabel=1
T 40750 55650 5 8 0 1 0 0 1
pintype=pas
}
P 41900 54200 42200 54200 1 0 1
{
T 40750 54150 5 8 1 1 0 0 1
pinnumber=6
T 40750 54150 5 8 0 0 0 0 1
pinseq=6
T 40750 54150 5 8 0 1 0 0 1
pinlabel=6
T 40750 54150 5 8 0 1 0 0 1
pintype=pas
}
P 41900 54800 42200 54800 1 0 1
{
T 40750 54750 5 8 1 1 0 0 1
pinnumber=4
T 40750 54750 5 8 0 0 0 0 1
pinseq=4
T 40750 54750 5 8 0 1 0 0 1
pinlabel=4
T 40750 54750 5 8 0 1 0 0 1
pintype=pas
}
P 41900 55400 42200 55400 1 0 1
{
T 40750 55350 5 8 1 1 0 0 1
pinnumber=2
T 40750 55350 5 8 0 0 0 0 1
pinseq=2
T 40750 55350 5 8 0 1 0 0 1
pinlabel=2
T 40750 55350 5 8 0 1 0 0 1
pintype=pas
}
]
{
T 42300 55800 5 10 0 0 0 0 1
device=CONNECTOR_6
T 40600 56000 5 10 1 1 0 0 1
refdes=J301
T 40500 54000 5 10 0 1 0 0 1
footprint=JUMPER6
}
T 40200 53700 9 10 1 0 0 0 1
FPGA JTAG
N 43400 55700 45300 55700 4
{
T 43700 55700 5 10 1 1 0 0 1
netname=FPGA_TMS
}
N 54200 50800 54000 50800 4
N 43400 55400 45100 55400 4
{
T 43700 55400 5 10 1 1 0 0 1
netname=FPGA_TDI
}
N 42200 55100 54200 55100 4
{
T 43700 55100 5 10 1 1 0 0 1
netname=FPGA_TDO
}
N 43400 54800 52400 54800 4
{
T 43700 54800 5 10 1 1 0 0 1
netname=FPGA_TCK
}
C 42400 53500 1 0 0 EMBEDDEDgnd-1.sym
[
T 42700 53550 8 10 0 0 0 0 1
net=GND:1
L 42480 53510 42520 53510 3 0 0 0 -1 -1
L 42455 53550 42545 53550 3 0 0 0 -1 -1
L 42400 53600 42600 53600 3 0 0 0 -1 -1
P 42500 53600 42500 53800 1 0 1
{
T 42558 53661 5 4 0 1 0 0 1
pinnumber=1
T 42558 53661 5 4 0 0 0 0 1
pinseq=1
T 42558 53661 5 4 0 1 0 0 1
pinlabel=1
T 42558 53661 5 4 0 1 0 0 1
pintype=pwr
}
]
N 42200 54500 42500 54500 4
N 42500 54500 42500 53800 4
N 54000 46600 56700 46600 4
N 45300 50800 45900 50800 4
C 46800 44200 1 0 0 EMBEDDED3.3V-plus-1.sym
[
T 47100 44200 8 8 0 0 0 0 1
net=+3.3V:1
T 46875 44450 9 8 1 0 0 0 1
+3.3V
L 46850 44400 47150 44400 3 0 0 0 -1 -1
P 47000 44200 47000 44400 1 0 0
{
T 47050 44250 5 6 0 1 0 0 1
pinnumber=1
T 47050 44250 5 6 0 0 0 0 1
pinseq=1
T 47050 44250 5 6 0 1 0 0 1
pinlabel=1
T 47050 44250 5 6 0 1 0 0 1
pintype=pwr
}
]
N 50800 44000 50800 44400 4
N 54000 49600 54200 49600 4
N 47500 44000 51800 44000 4
N 54200 45700 54200 50600 4
N 54000 48400 54200 48400 4
N 54000 47400 54200 47400 4
N 51800 44400 51800 44000 4
C 46200 51800 1 0 0 EMBEDDEDgnd-1.sym
[
T 46500 51850 8 10 0 0 0 0 1
net=GND:1
L 46280 51810 46320 51810 3 0 0 0 -1 -1
L 46255 51850 46345 51850 3 0 0 0 -1 -1
L 46200 51900 46400 51900 3 0 0 0 -1 -1
P 46300 51900 46300 52100 1 0 1
{
T 46358 51961 5 4 0 1 0 0 1
pinnumber=1
T 46358 51961 5 4 0 0 0 0 1
pinseq=1
T 46358 51961 5 4 0 1 0 0 1
pinlabel=1
T 46358 51961 5 4 0 1 0 0 1
pintype=pwr
}
]
N 46300 52600 46300 52100 4
N 51600 52400 51600 52600 4
N 45700 52600 51600 52600 4
N 49400 52400 49400 52600 4
N 50200 52400 50200 52600 4
N 45700 47400 45700 52600 4
N 45900 48200 45700 48200 4
C 56900 45700 1 180 0 EMBEDDEDled-3.sym
[
T 55950 45250 5 10 0 0 180 0 1
numslots=0
T 55950 45150 5 10 0 0 180 0 1
description=Generic LED
L 56500 45200 56450 45225 3 0 0 0 -1 -1
L 56500 45200 56475 45250 3 0 0 0 -1 -1
L 56600 45200 56550 45225 3 0 0 0 -1 -1
L 56600 45200 56575 45250 3 0 0 0 -1 -1
L 56500 45300 56600 45200 3 0 0 0 -1 -1
L 56400 45300 56500 45200 3 0 0 0 -1 -1
T 56450 45150 8 10 0 1 180 0 1
refdes=D?
L 56300 45500 56200 45500 3 0 0 0 -1 -1
L 56700 45500 56600 45500 3 0 0 0 -1 -1
P 56000 45500 56200 45500 1 0 0
{
T 56100 45550 5 8 0 1 0 0 1
pinnumber=2
T 55500 45550 9 8 0 1 0 0 1
pinlabel=ANODE
T 55900 45350 5 8 0 0 0 8 1
pintype=pas
T 55900 45450 5 8 0 0 0 8 1
pinseq=2
}
P 56900 45500 56700 45500 1 0 0
{
T 56700 45550 5 8 0 1 0 0 1
pinnumber=1
T 56100 45050 9 8 0 1 0 0 1
pinlabel=CATHODE
T 56000 44850 5 8 0 0 0 0 1
pintype=pas
T 56300 44750 5 8 0 0 0 0 1
pinseq=1
}
L 56600 45700 56600 45300 3 0 0 0 -1 -1
L 56600 45500 56300 45300 3 0 0 0 -1 -1
T 55950 45050 5 10 0 0 180 0 1
device=LED
L 56300 45700 56600 45500 3 0 0 0 -1 -1
L 56300 45700 56300 45300 3 0 0 0 -1 -1
]
{
T 55950 45050 5 10 0 0 180 0 1
device=LED
T 55950 45750 5 10 1 1 0 0 1
refdes=LED301
T 56900 45700 5 10 0 0 180 0 1
footprint=805_pol
}
C 55300 45600 1 180 0 EMBEDDEDresistor-1.sym
[
T 55300 45600 8 10 0 1 180 0 1
class=DISCRETE
T 55300 45600 8 10 0 1 180 0 1
pins=2
T 55100 45300 8 10 0 1 180 0 1
refdes=R?
L 55099 45400 55150 45500 3 0 0 0 -1 -1
P 55300 45500 55148 45500 1 0 0
{
T 55200 45450 5 8 0 1 180 0 1
pinnumber=1
T 55200 45450 5 8 0 0 180 0 1
pinseq=1
T 55200 45450 5 8 0 1 180 0 1
pinlabel=1
T 55200 45450 5 8 0 1 180 0 1
pintype=pas
}
P 54400 45500 54550 45500 1 0 0
{
T 54500 45450 5 8 0 1 180 0 1
pinnumber=2
T 54500 45450 5 8 0 0 180 0 1
pinseq=2
T 54500 45450 5 8 0 1 180 0 1
pinlabel=2
T 54500 45450 5 8 0 1 180 0 1
pintype=pas
}
L 54600 45600 54550 45500 3 0 0 0 -1 -1
L 54700 45400 54600 45600 3 0 0 0 -1 -1
T 55000 45200 5 10 0 0 180 0 1
device=RESISTOR
L 55000 45600 55100 45400 3 0 0 0 -1 -1
L 54900 45400 55000 45600 3 0 0 0 -1 -1
L 54800 45600 54900 45400 3 0 0 0 -1 -1
L 54700 45400 54800 45600 3 0 0 0 -1 -1
]
{
T 55000 45200 5 10 0 0 180 0 1
device=RESISTOR
T 54900 45700 5 10 1 1 0 0 1
refdes=R301
T 54500 45700 5 10 1 1 0 0 1
value=330
T 55300 45600 5 10 0 0 270 0 1
footprint=0805
}
N 54400 45500 54400 49200 4
N 55700 45500 55700 46600 4
C 54600 50600 1 0 0 EMBEDDED3.3V-plus-1.sym
[
T 54900 50600 8 8 0 0 0 0 1
net=+3.3V:1
T 54675 50850 9 8 1 0 0 0 1
+3.3V
L 54650 50800 54950 50800 3 0 0 0 -1 -1
P 54800 50600 54800 50800 1 0 0
{
T 54850 50650 5 6 0 1 0 0 1
pinnumber=1
T 54850 50650 5 6 0 0 0 0 1
pinseq=1
T 54850 50650 5 6 0 1 0 0 1
pinlabel=1
T 54850 50650 5 6 0 1 0 0 1
pintype=pwr
}
]
N 54800 49200 54800 50600 4
N 54000 46800 54400 46800 4
C 56700 49100 1 180 1 EMBEDDEDoutput-1.sym
[
T 56800 48800 5 10 0 0 180 6 1
device=OUTPUT
L 57400 49100 56900 49100 3 0 0 0 -1 -1
L 57500 49000 57400 49100 3 0 0 0 -1 -1
L 57400 48900 57500 49000 3 0 0 0 -1 -1
L 56900 48900 57400 48900 3 0 0 0 -1 -1
L 56900 48900 56900 49100 3 0 0 0 -1 -1
P 56700 49000 56900 49000 1 0 0
{
T 56950 49050 5 6 0 1 180 6 1
pinnumber=1
T 56950 49050 5 6 0 0 180 6 1
pinseq=1
}
]
{
T 56800 48800 5 10 0 0 180 6 1
device=OUTPUT
T 57400 49300 5 10 1 1 180 0 1
value=VCCINT
T 56700 49100 5 10 0 1 0 6 1
net=VCCINT:1
}
N 47600 44400 47600 44200 4
N 47000 44200 51400 44200 4
N 45900 49400 45700 49400 4
C 45800 53000 1 0 0 EMBEDDED3.3V-plus-1.sym
[
T 46100 53000 8 8 0 0 0 0 1
net=+3.3V:1
T 45875 53250 9 8 1 0 0 0 1
+3.3V
L 45850 53200 46150 53200 3 0 0 0 -1 -1
P 46000 53000 46000 53200 1 0 0
{
T 46050 53050 5 6 0 1 0 0 1
pinnumber=1
T 46050 53050 5 6 0 0 0 0 1
pinseq=1
T 46050 53050 5 6 0 1 0 0 1
pinlabel=1
T 46050 53050 5 6 0 1 0 0 1
pintype=pwr
}
]
N 48400 52400 48400 52800 4
N 45500 52800 51800 52800 4
C 51300 53200 1 270 1 EMBEDDEDoutput-1.sym
[
T 51600 53300 5 10 0 0 270 6 1
device=OUTPUT
L 51300 53900 51300 53400 3 0 0 0 -1 -1
L 51400 54000 51300 53900 3 0 0 0 -1 -1
L 51500 53900 51400 54000 3 0 0 0 -1 -1
L 51500 53400 51500 53900 3 0 0 0 -1 -1
L 51500 53400 51300 53400 3 0 0 0 -1 -1
P 51400 53200 51400 53400 1 0 0
{
T 51350 53450 5 6 0 1 270 6 1
pinnumber=1
T 51350 53450 5 6 0 0 270 6 1
pinseq=1
}
]
{
T 51600 53300 5 10 0 0 270 6 1
device=OUTPUT
T 51500 54700 5 10 1 1 90 6 1
value=VCCINT
T 51300 53200 5 10 0 1 90 6 1
net=VCCINT:1
}
N 51400 52400 51400 53200 4
N 50000 43800 50000 44400 4
N 51400 44200 51400 44400 4
C 47600 53200 1 180 0 EMBEDDEDresistor-1.sym
[
T 47600 53200 8 10 0 1 180 0 1
class=DISCRETE
T 47600 53200 8 10 0 1 180 0 1
pins=2
T 47400 52900 8 10 0 1 180 0 1
refdes=R?
L 47399 53000 47450 53100 3 0 0 0 -1 -1
P 47600 53100 47448 53100 1 0 0
{
T 47500 53050 5 8 0 1 180 0 1
pinnumber=1
T 47500 53050 5 8 0 0 180 0 1
pinseq=1
T 47500 53050 5 8 0 1 180 0 1
pinlabel=1
T 47500 53050 5 8 0 1 180 0 1
pintype=pas
}
P 46700 53100 46850 53100 1 0 0
{
T 46800 53050 5 8 0 1 180 0 1
pinnumber=2
T 46800 53050 5 8 0 0 180 0 1
pinseq=2
T 46800 53050 5 8 0 1 180 0 1
pinlabel=2
T 46800 53050 5 8 0 1 180 0 1
pintype=pas
}
L 46900 53200 46850 53100 3 0 0 0 -1 -1
L 47000 53000 46900 53200 3 0 0 0 -1 -1
T 47300 52800 5 10 0 0 180 0 1
device=RESISTOR
L 47300 53200 47400 53000 3 0 0 0 -1 -1
L 47200 53000 47300 53200 3 0 0 0 -1 -1
L 47100 53200 47200 53000 3 0 0 0 -1 -1
L 47000 53000 47100 53200 3 0 0 0 -1 -1
]
{
T 47300 52800 5 10 0 0 180 0 1
device=RESISTOR
T 47000 53200 5 10 1 1 0 0 1
refdes=R304
T 46600 53200 5 10 1 1 0 0 1
value=4.7k
T 47600 53200 5 10 0 0 270 0 1
footprint=0805
}
N 46700 53100 46700 52800 4
C 53700 44100 1 0 1 EMBEDDEDresistor-1.sym
[
T 53700 44100 8 10 0 1 0 6 1
class=DISCRETE
T 53700 44100 8 10 0 1 0 6 1
pins=2
T 53500 44400 8 10 0 1 0 6 1
refdes=R?
L 53499 44300 53550 44200 3 0 0 0 -1 -1
P 53700 44200 53548 44200 1 0 0
{
T 53600 44250 5 8 0 1 0 6 1
pinnumber=1
T 53600 44250 5 8 0 0 0 6 1
pinseq=1
T 53600 44250 5 8 0 1 0 6 1
pinlabel=1
T 53600 44250 5 8 0 1 0 6 1
pintype=pas
}
P 52800 44200 52950 44200 1 0 0
{
T 52900 44250 5 8 0 1 0 6 1
pinnumber=2
T 52900 44250 5 8 0 0 0 6 1
pinseq=2
T 52900 44250 5 8 0 1 0 6 1
pinlabel=2
T 52900 44250 5 8 0 1 0 6 1
pintype=pas
}
L 53000 44100 52950 44200 3 0 0 0 -1 -1
L 53100 44300 53000 44100 3 0 0 0 -1 -1
T 53400 44500 5 10 0 0 0 6 1
device=RESISTOR
L 53400 44100 53500 44300 3 0 0 0 -1 -1
L 53300 44300 53400 44100 3 0 0 0 -1 -1
L 53200 44100 53300 44300 3 0 0 0 -1 -1
L 53100 44300 53200 44100 3 0 0 0 -1 -1
]
{
T 53400 44500 5 10 0 0 0 6 1
device=RESISTOR
T 53200 44500 5 10 1 1 180 6 1
refdes=R302
T 52800 44500 5 10 1 1 180 6 1
value=4.7k
T 53700 44100 5 10 0 0 90 2 1
footprint=0805
}
C 53500 44700 1 0 0 EMBEDDED3.3V-plus-1.sym
[
T 53800 44700 8 8 0 0 0 0 1
net=+3.3V:1
T 53575 44950 9 8 1 0 0 0 1
+3.3V
L 53550 44900 53850 44900 3 0 0 0 -1 -1
P 53700 44700 53700 44900 1 0 0
{
T 53750 44750 5 6 0 1 0 0 1
pinnumber=1
T 53750 44750 5 6 0 0 0 0 1
pinseq=1
T 53750 44750 5 6 0 1 0 0 1
pinlabel=1
T 53750 44750 5 6 0 1 0 0 1
pintype=pwr
}
]
C 42500 55800 1 180 1 EMBEDDEDresistor-1.sym
[
T 42500 55800 8 10 0 1 180 6 1
class=DISCRETE
T 42500 55800 8 10 0 1 180 6 1
pins=2
T 42700 55500 8 10 0 1 180 6 1
refdes=R?
L 42701 55600 42650 55700 3 0 0 0 -1 -1
P 42500 55700 42652 55700 1 0 0
{
T 42600 55650 5 8 0 1 180 6 1
pinnumber=1
T 42600 55650 5 8 0 0 180 6 1
pinseq=1
T 42600 55650 5 8 0 1 180 6 1
pinlabel=1
T 42600 55650 5 8 0 1 180 6 1
pintype=pas
}
P 43400 55700 43250 55700 1 0 0
{
T 43300 55650 5 8 0 1 180 6 1
pinnumber=2
T 43300 55650 5 8 0 0 180 6 1
pinseq=2
T 43300 55650 5 8 0 1 180 6 1
pinlabel=2
T 43300 55650 5 8 0 1 180 6 1
pintype=pas
}
L 43200 55800 43250 55700 3 0 0 0 -1 -1
L 43100 55600 43200 55800 3 0 0 0 -1 -1
T 42800 55400 5 10 0 0 180 6 1
device=RESISTOR
L 42800 55800 42700 55600 3 0 0 0 -1 -1
L 42900 55600 42800 55800 3 0 0 0 -1 -1
L 43000 55800 42900 55600 3 0 0 0 -1 -1
L 43100 55600 43000 55800 3 0 0 0 -1 -1
]
{
T 42800 55400 5 10 0 0 180 6 1
device=RESISTOR
T 42700 55800 5 10 1 1 0 6 1
refdes=R306
T 43500 55800 5 10 1 1 0 6 1
value=100
T 42500 55800 5 10 0 0 270 2 1
footprint=0805
}
C 42500 55500 1 180 1 EMBEDDEDresistor-1.sym
[
T 42500 55500 8 10 0 1 180 6 1
class=DISCRETE
T 42500 55500 8 10 0 1 180 6 1
pins=2
T 42700 55200 8 10 0 1 180 6 1
refdes=R?
L 42701 55300 42650 55400 3 0 0 0 -1 -1
P 42500 55400 42652 55400 1 0 0
{
T 42600 55350 5 8 0 1 180 6 1
pinnumber=1
T 42600 55350 5 8 0 0 180 6 1
pinseq=1
T 42600 55350 5 8 0 1 180 6 1
pinlabel=1
T 42600 55350 5 8 0 1 180 6 1
pintype=pas
}
P 43400 55400 43250 55400 1 0 0
{
T 43300 55350 5 8 0 1 180 6 1
pinnumber=2
T 43300 55350 5 8 0 0 180 6 1
pinseq=2
T 43300 55350 5 8 0 1 180 6 1
pinlabel=2
T 43300 55350 5 8 0 1 180 6 1
pintype=pas
}
L 43200 55500 43250 55400 3 0 0 0 -1 -1
L 43100 55300 43200 55500 3 0 0 0 -1 -1
T 42800 55100 5 10 0 0 180 6 1
device=RESISTOR
L 42800 55500 42700 55300 3 0 0 0 -1 -1
L 42900 55300 42800 55500 3 0 0 0 -1 -1
L 43000 55500 42900 55300 3 0 0 0 -1 -1
L 43100 55300 43000 55500 3 0 0 0 -1 -1
]
{
T 42800 55100 5 10 0 0 180 6 1
device=RESISTOR
T 42700 55500 5 10 1 1 0 6 1
refdes=R307
T 43500 55500 5 10 1 1 0 6 1
value=100
T 42500 55500 5 10 0 0 270 2 1
footprint=0805
}
C 42500 54900 1 180 1 EMBEDDEDresistor-1.sym
[
T 42500 54900 8 10 0 1 180 6 1
class=DISCRETE
T 42500 54900 8 10 0 1 180 6 1
pins=2
T 42700 54600 8 10 0 1 180 6 1
refdes=R?
L 42701 54700 42650 54800 3 0 0 0 -1 -1
P 42500 54800 42652 54800 1 0 0
{
T 42600 54750 5 8 0 1 180 6 1
pinnumber=1
T 42600 54750 5 8 0 0 180 6 1
pinseq=1
T 42600 54750 5 8 0 1 180 6 1
pinlabel=1
T 42600 54750 5 8 0 1 180 6 1
pintype=pas
}
P 43400 54800 43250 54800 1 0 0
{
T 43300 54750 5 8 0 1 180 6 1
pinnumber=2
T 43300 54750 5 8 0 0 180 6 1
pinseq=2
T 43300 54750 5 8 0 1 180 6 1
pinlabel=2
T 43300 54750 5 8 0 1 180 6 1
pintype=pas
}
L 43200 54900 43250 54800 3 0 0 0 -1 -1
L 43100 54700 43200 54900 3 0 0 0 -1 -1
T 42800 54500 5 10 0 0 180 6 1
device=RESISTOR
L 42800 54900 42700 54700 3 0 0 0 -1 -1
L 42900 54700 42800 54900 3 0 0 0 -1 -1
L 43000 54900 42900 54700 3 0 0 0 -1 -1
L 43100 54700 43000 54900 3 0 0 0 -1 -1
]
{
T 42800 54500 5 10 0 0 180 6 1
device=RESISTOR
T 42700 54900 5 10 1 1 0 6 1
refdes=R308
T 43500 54900 5 10 1 1 0 6 1
value=100
T 42500 54900 5 10 0 0 270 2 1
footprint=0805
}
N 42200 55700 42500 55700 4
N 42500 55400 42200 55400 4
N 42500 54800 42200 54800 4
N 56700 48600 54000 48600 4
T 56800 45700 9 10 1 0 0 0 1
FPGA CFG
C 51900 43800 1 270 0 EMBEDDEDoutput-1.sym
[
T 52200 43700 5 10 0 0 270 0 1
device=OUTPUT
L 51900 43100 51900 43600 3 0 0 0 -1 -1
L 52000 43000 51900 43100 3 0 0 0 -1 -1
L 52100 43100 52000 43000 3 0 0 0 -1 -1
L 52100 43600 52100 43100 3 0 0 0 -1 -1
L 52100 43600 51900 43600 3 0 0 0 -1 -1
P 52000 43800 52000 43600 1 0 0
{
T 51950 43550 5 6 0 1 270 0 1
pinnumber=1
T 51950 43550 5 6 0 0 270 0 1
pinseq=1
}
]
{
T 52200 43700 5 10 0 0 270 0 1
device=OUTPUT
T 52100 42000 5 10 1 1 90 0 1
value=FPGA_INIT
T 51900 43800 5 10 0 1 90 0 1
net=FPGA_INIT:1
}
N 42200 54200 45500 54200 4
N 45500 46600 45500 54200 4
C 45900 44400 1 0 0 EMBEDDEDxc3s200avq100.sym
[
P 47600 52400 47600 51800 1 0 0
{
T 47600 52400 5 10 0 0 270 0 1
pintype=pas
T 47600 51745 5 10 1 1 90 6 1
pinlabel=PROG
T 47550 51895 5 10 1 1 90 0 1
pinnumber=100
T 47600 52400 5 10 0 0 270 0 1
pinseq=100
}
P 47800 52400 47800 51800 1 0 0
{
T 47800 52400 5 10 0 0 270 0 1
pintype=pas
T 47800 51745 5 10 1 1 90 6 1
pinlabel=IO_L06N_0/PUDC_B
T 47750 51895 5 10 1 1 90 0 1
pinnumber=99
T 47800 52400 5 10 0 0 270 0 1
pinseq=99
}
P 48000 52400 48000 51800 1 0 0
{
T 48000 52400 5 10 0 0 270 0 1
pintype=pas
T 48000 51745 5 10 1 1 90 6 1
pinlabel=IO_LO6P_0/VREF_0
T 47950 51895 5 10 1 1 90 0 1
pinnumber=98
T 48000 52400 5 10 0 0 270 0 1
pinseq=98
}
P 48200 52400 48200 51800 1 0 0
{
T 48200 52400 5 10 0 0 270 0 1
pintype=pas
T 48200 51745 5 10 1 1 90 6 1
pinlabel=IP_0
T 48150 51895 5 10 1 1 90 0 1
pinnumber=97
T 48200 52400 5 10 0 0 270 0 1
pinseq=97
}
P 48400 52400 48400 51800 1 0 0
{
T 48400 52400 5 10 0 0 270 0 1
pintype=pas
T 48400 51745 5 10 1 1 90 6 1
pinlabel=VCC_0
T 48350 51895 5 10 1 1 90 0 1
pinnumber=96
T 48400 52400 5 10 0 0 270 0 1
pinseq=96
}
P 48600 52400 48600 51800 1 0 0
{
T 48600 52400 5 10 0 0 270 0 1
pintype=pas
T 48600 51745 5 10 1 1 90 6 1
pinlabel=GND
T 48550 51895 5 10 1 1 90 0 1
pinnumber=95
T 48600 52400 5 10 0 0 270 0 1
pinseq=95
}
P 48800 52400 48800 51800 1 0 0
{
T 48800 52400 5 10 0 0 270 0 1
pintype=pas
T 48800 51745 5 10 1 1 90 6 1
pinlabel=IO_L05N_0
T 48750 51895 5 10 1 1 90 0 1
pinnumber=94
T 48800 52400 5 10 0 0 270 0 1
pinseq=94
}
P 49000 52400 49000 51800 1 0 0
{
T 49000 52400 5 10 0 0 270 0 1
pintype=pas
T 49000 51745 5 10 1 1 90 6 1
pinlabel=IO_L05P_0
T 48950 51895 5 10 1 1 90 0 1
pinnumber=93
T 49000 52400 5 10 0 0 270 0 1
pinseq=93
}
P 49200 52400 49200 51800 1 0 0
{
T 49200 52400 5 10 0 0 270 0 1
pintype=pas
T 49200 51745 5 10 1 1 90 6 1
pinlabel=VCCAUX
T 49150 51895 5 10 1 1 90 0 1
pinnumber=92
T 49200 52400 5 10 0 0 270 0 1
pinseq=92
}
P 49400 52400 49400 51800 1 0 0
{
T 49400 52400 5 10 0 0 270 0 1
pintype=pas
T 49400 51745 5 10 1 1 90 6 1
pinlabel=GND
T 49350 51895 5 10 1 1 90 0 1
pinnumber=91
T 49400 52400 5 10 0 0 270 0 1
pinseq=91
}
P 49600 52400 49600 51800 1 0 0
{
T 49600 52400 5 10 0 0 270 0 1
pintype=pas
T 49600 51745 5 10 1 1 90 6 1
pinlabel=IO_0/GCLK11
T 49550 51895 5 10 1 1 90 0 1
pinnumber=90
T 49600 52400 5 10 0 0 270 0 1
pinseq=90
}
P 49800 52400 49800 51800 1 0 0
{
T 49800 52400 5 10 0 0 270 0 1
pintype=pas
T 49800 51745 5 10 1 1 90 6 1
pinlabel=IO_L04N_0/GCLK9
T 49750 51895 5 10 1 1 90 0 1
pinnumber=89
T 49800 52400 5 10 0 0 270 0 1
pinseq=89
}
P 50000 52400 50000 51800 1 0 0
{
T 50000 52400 5 10 0 0 270 0 1
pintype=pas
T 50000 51745 5 10 1 1 90 6 1
pinlabel=IO_LO4P_0/GCLK8
T 49950 51895 5 10 1 1 90 0 1
pinnumber=88
T 50000 52400 5 10 0 0 270 0 1
pinseq=88
}
P 50200 52400 50200 51800 1 0 0
{
T 50200 52400 5 10 0 0 270 0 1
pintype=pas
T 50200 51745 5 10 1 1 90 6 1
pinlabel=GND
T 50150 51895 5 10 1 1 90 0 1
pinnumber=87
T 50200 52400 5 10 0 0 270 0 1
pinseq=87
}
P 50400 52400 50400 51800 1 0 0
{
T 50400 52400 5 10 0 0 270 0 1
pintype=pas
T 50400 51745 5 10 1 1 90 6 1
pinlabel=IO_LO3N_0/GCLK7
T 50350 51895 5 10 1 1 90 0 1
pinnumber=86
T 50400 52400 5 10 0 0 270 0 1
pinseq=86
}
P 50600 52400 50600 51800 1 0 0
{
T 50600 52400 5 10 0 0 270 0 1
pintype=pas
T 50600 51745 5 10 1 1 90 6 1
pinlabel=IO_L03P_0/GCLK6
T 50550 51895 5 10 1 1 90 0 1
pinnumber=85
T 50600 52400 5 10 0 0 270 0 1
pinseq=85
}
P 50800 52400 50800 51800 1 0 0
{
T 50800 52400 5 10 0 0 270 0 1
pintype=pas
T 50800 51745 5 10 1 1 90 6 1
pinlabel=IO_L02N_0/GCLK5
T 50750 51895 5 10 1 1 90 0 1
pinnumber=84
T 50800 52400 5 10 0 0 270 0 1
pinseq=84
}
P 51000 52400 51000 51800 1 0 0
{
T 51000 52400 5 10 0 0 270 0 1
pintype=pas
T 51000 51745 5 10 1 1 90 6 1
pinlabel=IO_L02P_0/GCLK4
T 50950 51895 5 10 1 1 90 0 1
pinnumber=83
T 51000 52400 5 10 0 0 270 0 1
pinseq=83
}
P 51200 52400 51200 51800 1 0 0
{
T 51200 52400 5 10 0 0 270 0 1
pintype=pas
T 51200 51745 5 10 1 1 90 6 1
pinlabel=IP_0/VREF_0
T 51150 51895 5 10 1 1 90 0 1
pinnumber=82
T 51200 52400 5 10 0 0 270 0 1
pinseq=82
}
P 51400 52400 51400 51800 1 0 0
{
T 51400 52400 5 10 0 0 270 0 1
pintype=pas
T 51400 51745 5 10 1 1 90 6 1
pinlabel=VCCINT
T 51350 51895 5 10 1 1 90 0 1
pinnumber=81
T 51400 52400 5 10 0 0 270 0 1
pinseq=81
}
T 49995 48595 8 10 0 1 0 0 1
refdes=U?
T 49795 48195 8 10 0 1 0 0 1
footprint=VQ100
T 49595 48395 8 10 0 1 0 0 1
device=XC3S200A
L 46500 51400 46900 51800 3 0 0 0 -1 -1
L 46900 51800 53400 51800 3 0 0 0 -1 -1
P 54000 49800 53400 49800 1 0 0
{
T 54000 49800 5 10 0 0 180 0 1
pintype=pas
T 53345 49795 5 10 1 1 0 6 1
pinlabel=IO_L05P_1
T 53495 49845 5 10 1 1 0 0 1
pinnumber=70
T 54000 49800 5 10 0 0 180 0 1
pinseq=70
}
P 54000 49600 53400 49600 1 0 0
{
T 54000 49600 5 10 0 0 180 0 1
pintype=pas
T 53345 49595 5 10 1 1 0 6 1
pinlabel=GND
T 53495 49645 5 10 1 1 0 0 1
pinnumber=69
T 54000 49600 5 10 0 0 180 0 1
pinseq=69
}
P 54000 49400 53400 49400 1 0 0
{
T 54000 49400 5 10 0 0 180 0 1
pintype=pas
T 53345 49395 5 10 1 1 0 6 1
pinlabel=IP_1/VREF_1
T 53495 49445 5 10 1 1 0 0 1
pinnumber=68
T 54000 49400 5 10 0 0 180 0 1
pinseq=68
}
P 54000 49200 53400 49200 1 0 0
{
T 54000 49200 5 10 0 0 180 0 1
pintype=pas
T 53345 49195 5 10 1 1 0 6 1
pinlabel=VCCO_1
T 53495 49245 5 10 1 1 0 0 1
pinnumber=67
T 54000 49200 5 10 0 0 180 0 1
pinseq=67
}
P 54000 49000 53400 49000 1 0 0
{
T 54000 49000 5 10 0 0 180 0 1
pintype=pas
T 53345 48995 5 10 1 1 0 6 1
pinlabel=VCCINT
T 53495 49045 5 10 1 1 0 0 1
pinnumber=66
T 54000 49000 5 10 0 0 180 0 1
pinseq=66
}
P 54000 48800 53400 48800 1 0 0
{
T 54000 48800 5 10 0 0 180 0 1
pintype=pas
T 53345 48795 5 10 1 1 0 6 1
pinlabel=IO_L04N_1/RHCLK7
T 53495 48845 5 10 1 1 0 0 1
pinnumber=65
T 54000 48800 5 10 0 0 180 0 1
pinseq=65
}
P 54000 48600 53400 48600 1 0 0
{
T 54000 48600 5 10 0 0 180 0 1
pintype=pas
T 53345 48595 5 10 1 1 0 6 1
pinlabel=IO_L04P_1/IRDY1/RHCLK6
T 53495 48645 5 10 1 1 0 0 1
pinnumber=64
T 54000 48600 5 10 0 0 180 0 1
pinseq=64
}
P 54000 48400 53400 48400 1 0 0
{
T 54000 48400 5 10 0 0 180 0 1
pintype=pas
T 53345 48395 5 10 1 1 0 6 1
pinlabel=GND
T 53495 48445 5 10 1 1 0 0 1
pinnumber=63
T 54000 48400 5 10 0 0 180 0 1
pinseq=63
}
P 54000 48200 53400 48200 1 0 0
{
T 54000 48200 5 10 0 0 180 0 1
pintype=pas
T 53345 48195 5 10 1 1 0 6 1
pinlabel=IO_L03N_1/TRDY1/RHCLK3
T 53495 48245 5 10 1 1 0 0 1
pinnumber=62
T 54000 48200 5 10 0 0 180 0 1
pinseq=62
}
P 54000 48000 53400 48000 1 0 0
{
T 54000 48000 5 10 0 0 180 0 1
pintype=pas
T 53345 47995 5 10 1 1 0 6 1
pinlabel=IO_L03P_1/RHCLK2
T 53495 48045 5 10 1 1 0 0 1
pinnumber=61
T 54000 48000 5 10 0 0 180 0 1
pinseq=61
}
P 51600 52400 51600 51800 1 0 0
{
T 51600 52400 5 10 0 0 270 0 1
pintype=pas
T 51600 51745 5 10 1 1 90 6 1
pinlabel=GND
T 51550 51895 5 10 1 1 90 0 1
pinnumber=80
T 51600 52400 5 10 0 0 270 0 1
pinseq=80
}
P 51800 52400 51800 51800 1 0 0
{
T 51800 52400 5 10 0 0 270 0 1
pintype=pas
T 51800 51745 5 10 1 1 90 6 1
pinlabel=VCCO_0
T 51750 51895 5 10 1 1 90 0 1
pinnumber=79
T 51800 52400 5 10 0 0 270 0 1
pinseq=79
}
P 52000 52400 52000 51800 1 0 0
{
T 52000 52400 5 10 0 0 270 0 1
pintype=pas
T 52000 51745 5 10 1 1 90 6 1
pinlabel=IO_L01N_0
T 51950 51895 5 10 1 1 90 0 1
pinnumber=78
T 52000 52400 5 10 0 0 270 0 1
pinseq=78
}
P 52200 52400 52200 51800 1 0 0
{
T 52200 52400 5 10 0 0 270 0 1
pintype=pas
T 52200 51745 5 10 1 1 90 6 1
pinlabel=IO_L01P_0/VREF_0
T 52150 51895 5 10 1 1 90 0 1
pinnumber=77
T 52200 52400 5 10 0 0 270 0 1
pinseq=77
}
P 52400 52400 52400 51800 1 0 0
{
T 52400 52400 5 10 0 0 270 0 1
pintype=pas
T 52400 51745 5 10 1 1 90 6 1
pinlabel=TCK
T 52350 51895 5 10 1 1 90 0 1
pinnumber=76
T 52400 52400 5 10 0 0 270 0 1
pinseq=76
}
P 54000 50800 53400 50800 1 0 0
{
T 54000 50800 5 10 0 0 180 0 1
pintype=pas
T 53345 50795 5 10 1 1 0 6 1
pinlabel=TDO
T 53495 50845 5 10 1 1 0 0 1
pinnumber=75
T 54000 50800 5 10 0 0 180 0 1
pinseq=75
}
P 54000 50600 53400 50600 1 0 0
{
T 54000 50600 5 10 0 0 180 0 1
pintype=pas
T 53345 50595 5 10 1 1 0 6 1
pinlabel=GND
T 53495 50645 5 10 1 1 0 0 1
pinnumber=74
T 54000 50600 5 10 0 0 180 0 1
pinseq=74
}
P 54000 50400 53400 50400 1 0 0
{
T 54000 50400 5 10 0 0 180 0 1
pintype=pas
T 53345 50395 5 10 1 1 0 6 1
pinlabel=IO_L06N_1
T 53495 50445 5 10 1 1 0 0 1
pinnumber=73
T 54000 50400 5 10 0 0 180 0 1
pinseq=73
}
P 54000 50200 53400 50200 1 0 0
{
T 54000 50200 5 10 0 0 180 0 1
pintype=pas
T 53345 50195 5 10 1 1 0 6 1
pinlabel=IO_L06P_1
T 53495 50245 5 10 1 1 0 0 1
pinnumber=72
T 54000 50200 5 10 0 0 180 0 1
pinseq=72
}
P 54000 50000 53400 50000 1 0 0
{
T 54000 50000 5 10 0 0 180 0 1
pintype=pas
T 53345 49995 5 10 1 1 0 6 1
pinlabel=IO_L05N_1
T 53495 50045 5 10 1 1 0 0 1
pinnumber=71
T 54000 50000 5 10 0 0 180 0 1
pinseq=71
}
L 53400 51800 53400 45000 3 0 0 0 -1 -1
P 52400 44400 52400 45000 1 0 0
{
T 52400 44400 5 10 0 0 90 0 1
pintype=pas
T 52400 45055 5 10 1 1 90 0 1
pinlabel=IO_L11P_2/D2
T 52350 44905 5 10 1 1 90 6 1
pinnumber=50
T 52400 44400 5 10 0 0 90 0 1
pinseq=50
}
P 52200 44400 52200 45000 1 0 0
{
T 52200 44400 5 10 0 0 90 0 1
pintype=pas
T 52200 45055 5 10 1 1 90 0 1
pinlabel=IO_L10N_2/D3
T 52150 44905 5 10 1 1 90 6 1
pinnumber=49
T 52200 44400 5 10 0 0 90 0 1
pinseq=49
}
P 52000 44400 52000 45000 1 0 0
{
T 52000 44400 5 10 0 0 90 0 1
pintype=pas
T 52000 45055 5 10 1 1 90 0 1
pinlabel=IO_L10P_2/INIT_B
T 51950 44905 5 10 1 1 90 6 1
pinnumber=48
T 52000 44400 5 10 0 0 90 0 1
pinseq=48
}
P 51800 44400 51800 45000 1 0 0
{
T 51800 44400 5 10 0 0 90 0 1
pintype=pas
T 51800 45055 5 10 1 1 90 0 1
pinlabel=GND
T 51750 44905 5 10 1 1 90 6 1
pinnumber=47
T 51800 44400 5 10 0 0 90 0 1
pinseq=47
}
P 51600 44400 51600 45000 1 0 0
{
T 51600 44400 5 10 0 0 90 0 1
pintype=pas
T 51600 45055 5 10 1 1 90 0 1
pinlabel=IO_2/MOSI/CSI_B
T 51550 44905 5 10 1 1 90 6 1
pinnumber=46
T 51600 44400 5 10 0 0 90 0 1
pinseq=46
}
P 51400 44400 51400 45000 1 0 0
{
T 51400 44400 5 10 0 0 90 0 1
pintype=pas
T 51400 45055 5 10 1 1 90 0 1
pinlabel=VCC0_2
T 51350 44905 5 10 1 1 90 6 1
pinnumber=45
T 51400 44400 5 10 0 0 90 0 1
pinseq=45
}
P 51200 44400 51200 45000 1 0 0
{
T 51200 44400 5 10 0 0 90 0 1
pintype=pas
T 51200 45055 5 10 1 1 90 0 1
pinlabel=IO_L09N_2/GCLK1
T 51150 44905 5 10 1 1 90 6 1
pinnumber=44
T 51200 44400 5 10 0 0 90 0 1
pinseq=44
}
P 51000 44400 51000 45000 1 0 0
{
T 51000 44400 5 10 0 0 90 0 1
pintype=pas
T 51000 45055 5 10 1 1 90 0 1
pinlabel=IO_L09P_2/GCLK0
T 50950 44905 5 10 1 1 90 6 1
pinnumber=43
T 51000 44400 5 10 0 0 90 0 1
pinseq=43
}
P 50800 44400 50800 45000 1 0 0
{
T 50800 44400 5 10 0 0 90 0 1
pintype=pas
T 50800 45055 5 10 1 1 90 0 1
pinlabel=GND
T 50750 44905 5 10 1 1 90 6 1
pinnumber=42
T 50800 44400 5 10 0 0 90 0 1
pinseq=42
}
P 50600 44400 50600 45000 1 0 0
{
T 50600 44400 5 10 0 0 90 0 1
pintype=pas
T 50600 45055 5 10 1 1 90 0 1
pinlabel=IO_L08N_2/GCLK15
T 50550 44905 5 10 1 1 90 6 1
pinnumber=41
T 50600 44400 5 10 0 0 90 0 1
pinseq=41
}
P 54000 47800 53400 47800 1 0 0
{
T 54000 47800 5 10 0 0 180 0 1
pintype=pas
T 53345 47795 5 10 1 1 0 6 1
pinlabel=IO_L02N_1/RHCLK1
T 53495 47845 5 10 1 1 0 0 1
pinnumber=60
T 54000 47800 5 10 0 0 180 0 1
pinseq=60
}
P 54000 47600 53400 47600 1 0 0
{
T 54000 47600 5 10 0 0 180 0 1
pintype=pas
T 53345 47595 5 10 1 1 0 6 1
pinlabel=IO_L02P_1/RHCLK0
T 53495 47645 5 10 1 1 0 0 1
pinnumber=59
T 54000 47600 5 10 0 0 180 0 1
pinseq=59
}
P 54000 47400 53400 47400 1 0 0
{
T 54000 47400 5 10 0 0 180 0 1
pintype=pas
T 53345 47395 5 10 1 1 0 6 1
pinlabel=GND
T 53495 47445 5 10 1 1 0 0 1
pinnumber=58
T 54000 47400 5 10 0 0 180 0 1
pinseq=58
}
P 54000 47200 53400 47200 1 0 0
{
T 54000 47200 5 10 0 0 180 0 1
pintype=pas
T 53345 47195 5 10 1 1 0 6 1
pinlabel=IO_L01N_1
T 53495 47245 5 10 1 1 0 0 1
pinnumber=57
T 54000 47200 5 10 0 0 180 0 1
pinseq=57
}
P 54000 47000 53400 47000 1 0 0
{
T 54000 47000 5 10 0 0 180 0 1
pintype=pas
T 53345 46995 5 10 1 1 0 6 1
pinlabel=IO_L01P_1
T 53495 47045 5 10 1 1 0 0 1
pinnumber=56
T 54000 47000 5 10 0 0 180 0 1
pinseq=56
}
P 54000 46800 53400 46800 1 0 0
{
T 54000 46800 5 10 0 0 180 0 1
pintype=pas
T 53345 46795 5 10 1 1 0 6 1
pinlabel=VCCAUX
T 53495 46845 5 10 1 1 0 0 1
pinnumber=55
T 54000 46800 5 10 0 0 180 0 1
pinseq=55
}
P 54000 46600 53400 46600 1 0 0
{
T 54000 46600 5 10 0 0 180 0 1
pintype=pas
T 53345 46595 5 10 1 1 0 6 1
pinlabel=DONE
T 53495 46645 5 10 1 1 0 0 1
pinnumber=54
T 54000 46600 5 10 0 0 180 0 1
pinseq=54
}
P 54000 46400 53400 46400 1 0 0
{
T 54000 46400 5 10 0 0 180 0 1
pintype=pas
T 53345 46395 5 10 1 1 0 6 1
pinlabel=IO_L12N_2/CCLK
T 53495 46445 5 10 1 1 0 0 1
pinnumber=53
T 54000 46400 5 10 0 0 180 0 1
pinseq=53
}
P 54000 46200 53400 46200 1 0 0
{
T 54000 46200 5 10 0 0 180 0 1
pintype=pas
T 53345 46195 5 10 1 1 0 6 1
pinlabel=IO_L11N_2/D1
T 53495 46245 5 10 1 1 0 0 1
pinnumber=52
T 54000 46200 5 10 0 0 180 0 1
pinseq=52
}
P 54000 46000 53400 46000 1 0 0
{
T 54000 46000 5 10 0 0 180 0 1
pintype=pas
T 53345 45995 5 10 1 1 0 6 1
pinlabel=1O_12P_2/D0/DIN/MISO
T 53495 46045 5 10 1 1 0 0 1
pinnumber=51
T 54000 46000 5 10 0 0 180 0 1
pinseq=51
}
L 53400 45000 46500 45000 3 0 0 0 -1 -1
P 48400 44400 48400 45000 1 0 0
{
T 48400 44400 5 10 0 0 90 0 1
pintype=pas
T 48400 45055 5 10 1 1 90 0 1
pinlabel=IO_L04P_2/VS1
T 48350 44905 5 10 1 1 90 6 1
pinnumber=30
T 48400 44400 5 10 0 0 90 0 1
pinseq=30
}
P 48200 44400 48200 45000 1 0 0
{
T 48200 44400 5 10 0 0 90 0 1
pintype=pas
T 48200 45055 5 10 1 1 90 0 1
pinlabel=IO_L03N_2/VS2
T 48150 44905 5 10 1 1 90 6 1
pinnumber=29
T 48200 44400 5 10 0 0 90 0 1
pinseq=29
}
P 48000 44400 48000 45000 1 0 0
{
T 48000 44400 5 10 0 0 90 0 1
pintype=pas
T 48000 45055 5 10 1 1 90 0 1
pinlabel=IO_L03P_2/RDWR_B
T 47950 44905 5 10 1 1 90 6 1
pinnumber=28
T 48000 44400 5 10 0 0 90 0 1
pinseq=28
}
P 47800 44400 47800 45000 1 0 0
{
T 47800 44400 5 10 0 0 90 0 1
pintype=pas
T 47800 45055 5 10 1 1 90 0 1
pinlabel=IO_L02N_2/CSO_B
T 47750 44905 5 10 1 1 90 6 1
pinnumber=27
T 47800 44400 5 10 0 0 90 0 1
pinseq=27
}
P 47600 44400 47600 45000 1 0 0
{
T 47600 44400 5 10 0 0 90 0 1
pintype=pas
T 47600 45055 5 10 1 1 90 0 1
pinlabel=VCCO_2
T 47550 44905 5 10 1 1 90 6 1
pinnumber=26
T 47600 44400 5 10 0 0 90 0 1
pinseq=26
}
P 45900 46000 46500 46000 1 0 0
{
T 45900 46000 5 10 0 0 0 0 1
pintype=pas
T 46555 45995 5 10 1 1 0 0 1
pinlabel=IO_L01N_2/M0
T 46405 46045 5 10 1 1 0 6 1
pinnumber=25
T 45900 46000 5 10 0 0 0 0 1
pinseq=25
}
P 45900 46200 46500 46200 1 0 0
{
T 45900 46200 5 10 0 0 0 0 1
pintype=pas
T 46555 46195 5 10 1 1 0 0 1
pinlabel=IO_L02P_2/M2
T 46405 46245 5 10 1 1 0 6 1
pinnumber=24
T 45900 46200 5 10 0 0 0 0 1
pinseq=24
}
P 45900 46400 46500 46400 1 0 0
{
T 45900 46400 5 10 0 0 0 0 1
pintype=pas
T 46555 46395 5 10 1 1 0 0 1
pinlabel=IO_L01P_2/M1
T 46405 46445 5 10 1 1 0 6 1
pinnumber=23
T 45900 46400 5 10 0 0 0 0 1
pinseq=23
}
P 45900 46600 46500 46600 1 0 0
{
T 45900 46600 5 10 0 0 0 0 1
pintype=pas
T 46555 46595 5 10 1 1 0 0 1
pinlabel=VCCAUX
T 46405 46645 5 10 1 1 0 6 1
pinnumber=22
T 45900 46600 5 10 0 0 0 0 1
pinseq=22
}
P 45900 46800 46500 46800 1 0 0
{
T 45900 46800 5 10 0 0 0 0 1
pintype=pas
T 46555 46795 5 10 1 1 0 0 1
pinlabel=IP_3
T 46405 46845 5 10 1 1 0 6 1
pinnumber=21
T 45900 46800 5 10 0 0 0 0 1
pinseq=21
}
P 50400 44400 50400 45000 1 0 0
{
T 50400 44400 5 10 0 0 90 0 1
pintype=pas
T 50400 45055 5 10 1 1 90 0 1
pinlabel=IO_L08P_2/GCLK14
T 50350 44905 5 10 1 1 90 6 1
pinnumber=40
T 50400 44400 5 10 0 0 90 0 1
pinseq=40
}
P 50200 44400 50200 45000 1 0 0
{
T 50200 44400 5 10 0 0 90 0 1
pintype=pas
T 50200 45055 5 10 1 1 90 0 1
pinlabel=IP_2/VREF_2
T 50150 44905 5 10 1 1 90 6 1
pinnumber=39
T 50200 44400 5 10 0 0 90 0 1
pinseq=39
}
P 50000 44400 50000 45000 1 0 0
{
T 50000 44400 5 10 0 0 90 0 1
pintype=pas
T 50000 45055 5 10 1 1 90 0 1
pinlabel=VCCINT
T 49950 44905 5 10 1 1 90 6 1
pinnumber=38
T 50000 44400 5 10 0 0 90 0 1
pinseq=38
}
P 49800 44400 49800 45000 1 0 0
{
T 49800 44400 5 10 0 0 90 0 1
pintype=pas
T 49800 45055 5 10 1 1 90 0 1
pinlabel=IO_L07N_2/D4
T 49750 44905 5 10 1 1 90 6 1
pinnumber=37
T 49800 44400 5 10 0 0 90 0 1
pinseq=37
}
P 49600 44400 49600 45000 1 0 0
{
T 49600 44400 5 10 0 0 90 0 1
pintype=pas
T 49600 45055 5 10 1 1 90 0 1
pinlabel=IO_L07P_2/D5
T 49550 44905 5 10 1 1 90 6 1
pinnumber=36
T 49600 44400 5 10 0 0 90 0 1
pinseq=36
}
P 49400 44400 49400 45000 1 0 0
{
T 49400 44400 5 10 0 0 90 0 1
pintype=pas
T 49400 45055 5 10 1 1 90 0 1
pinlabel=IO_L06N_2/D6
T 49350 44905 5 10 1 1 90 6 1
pinnumber=35
T 49400 44400 5 10 0 0 90 0 1
pinseq=35
}
P 49200 44400 49200 45000 1 0 0
{
T 49200 44400 5 10 0 0 90 0 1
pintype=pas
T 49200 45055 5 10 1 1 90 0 1
pinlabel=IO_L06P_2/D7
T 49150 44905 5 10 1 1 90 6 1
pinnumber=34
T 49200 44400 5 10 0 0 90 0 1
pinseq=34
}
P 49000 44400 49000 45000 1 0 0
{
T 49000 44400 5 10 0 0 90 0 1
pintype=pas
T 49000 45055 5 10 1 1 90 0 1
pinlabel=IO_L05N_2
T 48950 44905 5 10 1 1 90 6 1
pinnumber=33
T 49000 44400 5 10 0 0 90 0 1
pinseq=33
}
P 48800 44400 48800 45000 1 0 0
{
T 48800 44400 5 10 0 0 90 0 1
pintype=pas
T 48800 45055 5 10 1 1 90 0 1
pinlabel=IO_L05P_2
T 48750 44905 5 10 1 1 90 6 1
pinnumber=32
T 48800 44400 5 10 0 0 90 0 1
pinseq=32
}
P 48600 44400 48600 45000 1 0 0
{
T 48600 44400 5 10 0 0 90 0 1
pintype=pas
T 48600 45055 5 10 1 1 90 0 1
pinlabel=IO_L04N_2/VS0
T 48550 44905 5 10 1 1 90 6 1
pinnumber=31
T 48600 44400 5 10 0 0 90 0 1
pinseq=31
}
L 46500 45000 46500 51400 3 0 0 0 -1 -1
P 45900 49000 46500 49000 1 0 0
{
T 45900 49000 5 10 0 0 0 0 1
pintype=pas
T 46555 48995 5 10 1 1 0 0 1
pinlabel=IO_L03N_3/LHCLK1
T 46405 49045 5 10 1 1 0 6 1
pinnumber=10
T 45900 49000 5 10 0 0 0 0 1
pinseq=10
}
P 45900 49200 46500 49200 1 0 0
{
T 45900 49200 5 10 0 0 0 0 1
pintype=pas
T 46555 49195 5 10 1 1 0 0 1
pinlabel=IO_L03P_3/LHCLK0
T 46405 49245 5 10 1 1 0 6 1
pinnumber=9
T 45900 49200 5 10 0 0 0 0 1
pinseq=9
}
P 45900 49400 46500 49400 1 0 0
{
T 45900 49400 5 10 0 0 0 0 1
pintype=pas
T 46555 49395 5 10 1 1 0 0 1
pinlabel=GND
T 46405 49445 5 10 1 1 0 6 1
pinnumber=8
T 45900 49400 5 10 0 0 0 0 1
pinseq=8
}
P 45900 49600 46500 49600 1 0 0
{
T 45900 49600 5 10 0 0 0 0 1
pintype=pas
T 46555 49595 5 10 1 1 0 0 1
pinlabel=IP_3/VREF_3
T 46405 49645 5 10 1 1 0 6 1
pinnumber=7
T 45900 49600 5 10 0 0 0 0 1
pinseq=7
}
P 45900 49800 46500 49800 1 0 0
{
T 45900 49800 5 10 0 0 0 0 1
pintype=pas
T 46555 49795 5 10 1 1 0 0 1
pinlabel=IO_L02N_3
T 46405 49845 5 10 1 1 0 6 1
pinnumber=6
T 45900 49800 5 10 0 0 0 0 1
pinseq=6
}
P 45900 50000 46500 50000 1 0 0
{
T 45900 50000 5 10 0 0 0 0 1
pintype=pas
T 46555 49995 5 10 1 1 0 0 1
pinlabel=IO_L02P_3
T 46405 50045 5 10 1 1 0 6 1
pinnumber=5
T 45900 50000 5 10 0 0 0 0 1
pinseq=5
}
P 45900 50200 46500 50200 1 0 0
{
T 45900 50200 5 10 0 0 0 0 1
pintype=pas
T 46555 50195 5 10 1 1 0 0 1
pinlabel=IO_L01N_3
T 46405 50245 5 10 1 1 0 6 1
pinnumber=4
T 45900 50200 5 10 0 0 0 0 1
pinseq=4
}
P 45900 50400 46500 50400 1 0 0
{
T 45900 50400 5 10 0 0 0 0 1
pintype=pas
T 46555 50395 5 10 1 1 0 0 1
pinlabel=IO_L01P_3
T 46405 50445 5 10 1 1 0 6 1
pinnumber=3
T 45900 50400 5 10 0 0 0 0 1
pinseq=3
}
P 45900 50600 46500 50600 1 0 0
{
T 45900 50600 5 10 0 0 0 0 1
pintype=pas
T 46555 50595 5 10 1 1 0 0 1
pinlabel=TDI
T 46405 50645 5 10 1 1 0 6 1
pinnumber=2
T 45900 50600 5 10 0 0 0 0 1
pinseq=2
}
P 45900 50800 46500 50800 1 0 0
{
T 45900 50800 5 10 0 0 0 0 1
pintype=pas
T 46555 50795 5 10 1 1 0 0 1
pinlabel=TMS
T 46405 50845 5 10 1 1 0 6 1
pinnumber=1
T 45900 50800 5 10 0 0 0 0 1
pinseq=1
}
P 45900 47000 46500 47000 1 0 0
{
T 45900 47000 5 10 0 0 0 0 1
pintype=pas
T 46555 46995 5 10 1 1 0 0 1
pinlabel=IO_L06N_3
T 46405 47045 5 10 1 1 0 6 1
pinnumber=20
T 45900 47000 5 10 0 0 0 0 1
pinseq=20
}
P 45900 47200 46500 47200 1 0 0
{
T 45900 47200 5 10 0 0 0 0 1
pintype=pas
T 46555 47195 5 10 1 1 0 0 1
pinlabel=IO_L06P_3
T 46405 47245 5 10 1 1 0 6 1
pinnumber=19
T 45900 47200 5 10 0 0 0 0 1
pinseq=19
}
P 45900 47400 46500 47400 1 0 0
{
T 45900 47400 5 10 0 0 0 0 1
pintype=pas
T 46555 47395 5 10 1 1 0 0 1
pinlabel=GND
T 46405 47445 5 10 1 1 0 6 1
pinnumber=18
T 45900 47400 5 10 0 0 0 0 1
pinseq=18
}
P 45900 47600 46500 47600 1 0 0
{
T 45900 47600 5 10 0 0 0 0 1
pintype=pas
T 46555 47595 5 10 1 1 0 0 1
pinlabel=VCCINT
T 46405 47645 5 10 1 1 0 6 1
pinnumber=17
T 45900 47600 5 10 0 0 0 0 1
pinseq=17
}
P 45900 47800 46500 47800 1 0 0
{
T 45900 47800 5 10 0 0 0 0 1
pintype=pas
T 46555 47795 5 10 1 1 0 0 1
pinlabel=IO_L05N_3/LHCLK7
T 46405 47845 5 10 1 1 0 6 1
pinnumber=16
T 45900 47800 5 10 0 0 0 0 1
pinseq=16
}
P 45900 48000 46500 48000 1 0 0
{
T 45900 48000 5 10 0 0 0 0 1
pintype=pas
T 46555 47995 5 10 1 1 0 0 1
pinlabel=IO_L05P_3/TRDY2/LHCLK6
T 46405 48045 5 10 1 1 0 6 1
pinnumber=15
T 45900 48000 5 10 0 0 0 0 1
pinseq=15
}
P 45900 48200 46500 48200 1 0 0
{
T 45900 48200 5 10 0 0 0 0 1
pintype=pas
T 46555 48195 5 10 1 1 0 0 1
pinlabel=GND
T 46405 48245 5 10 1 1 0 6 1
pinnumber=14
T 45900 48200 5 10 0 0 0 0 1
pinseq=14
}
P 45900 48400 46500 48400 1 0 0
{
T 45900 48400 5 10 0 0 0 0 1
pintype=pas
T 46555 48395 5 10 1 1 0 0 1
pinlabel=IO_L04N_3/IRDY2/LHCLK3
T 46405 48445 5 10 1 1 0 6 1
pinnumber=13
T 45900 48400 5 10 0 0 0 0 1
pinseq=12
}
P 45900 48600 46500 48600 1 0 0
{
T 45900 48600 5 10 0 0 0 0 1
pintype=pas
T 46555 48595 5 10 1 1 0 0 1
pinlabel=IO_L04P_3/LHCLK2
T 46405 48645 5 10 1 1 0 6 1
pinnumber=12
T 45900 48600 5 10 0 0 0 0 1
pinseq=12
}
P 45900 48800 46500 48800 1 0 0
{
T 45900 48800 5 10 0 0 0 0 1
pintype=pas
T 46555 48795 5 10 1 1 0 0 1
pinlabel=VCCO_3
T 46405 48845 5 10 1 1 0 6 1
pinnumber=11
T 45900 48800 5 10 0 0 0 0 1
pinseq=11
}
]
{
T 49595 48395 5 10 1 1 0 0 1
device=XC3S200A
T 49795 48195 5 10 1 1 0 0 1
footprint=LQFP100_14
T 49995 48595 5 10 1 1 0 0 1
refdes=U301
}
N 54200 50800 54200 55100 4
N 52400 52400 52400 54800 4
N 45300 50800 45300 55700 4
N 45900 50600 45100 50600 4
N 45100 50600 45100 55400 4
N 45900 47400 45700 47400 4
N 48600 52400 48600 52600 4
N 49200 52400 49200 52800 4
N 51800 52400 51800 52800 4
N 45900 46600 45500 46600 4
N 45900 48800 41600 48800 4
N 46000 53000 46000 52800 4
N 54000 50600 54200 50600 4
N 47600 52400 47600 53200 4
N 52000 43800 52000 44400 4
N 53700 44700 53700 44200 4
N 54000 46000 60300 46000 4
N 54000 46200 58200 46200 4
N 54000 46400 58200 46400 4
N 52400 43700 52400 44400 4
N 49800 43800 49800 44400 4
N 49600 43800 49600 44400 4
N 49400 43800 49400 44400 4
N 49200 43800 49200 44400 4
N 56700 47600 54000 47600 4
N 54000 47800 56700 47800 4
N 56700 48000 54000 48000 4
N 54000 48200 56700 48200 4
N 54000 50400 56700 50400 4
N 54000 50200 56700 50200 4
N 54000 50000 56700 50000 4
N 54000 49800 56700 49800 4
N 50400 52400 50400 53200 4
N 50800 52400 50800 53200 4
N 51000 52400 51000 53200 4
N 50600 52400 50600 53200 4
N 49000 44400 49000 43800 4
N 48800 44400 48800 43800 4
C 40900 44600 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 40000 44800 5 10 0 0 90 0 1
symversion=0.1
T 39800 44800 5 10 0 0 90 0 1
numslots=0
T 39600 44800 5 10 0 0 90 0 1
description=capacitor
T 40400 44800 8 10 0 1 90 0 1
refdes=C?
T 40200 44800 5 10 0 0 90 0 1
device=CAPACITOR
L 40700 45000 40700 44800 3 0 0 0 -1 -1
L 40700 45300 40700 45100 3 0 0 0 -1 -1
L 40500 45100 40900 45100 3 0 0 0 -1 -1
L 40500 45000 40900 45000 3 0 0 0 -1 -1
P 40700 45500 40700 45300 1 0 0
{
T 40650 45350 5 8 0 1 90 0 1
pinnumber=2
T 40750 45350 5 8 0 1 90 2 1
pinseq=2
T 40700 45300 9 8 0 1 90 6 1
pinlabel=2
T 40700 45300 5 8 0 1 90 8 1
pintype=pas
}
P 40700 44600 40700 44800 1 0 0
{
T 40650 44750 5 8 0 1 90 6 1
pinnumber=1
T 40750 44750 5 8 0 1 90 8 1
pinseq=1
T 40700 44800 9 8 0 1 90 0 1
pinlabel=1
T 40700 44800 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 40200 44800 5 10 0 0 90 0 1
device=CAPACITOR
T 40500 45200 5 10 1 1 180 0 1
refdes=C301
T 40000 44800 5 10 0 0 90 0 1
symversion=0.1
T 40000 44800 5 10 1 1 0 0 1
value=0.1uf
T 40900 44600 5 10 0 0 0 0 1
footprint=0603
}
C 40900 43300 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 40000 43500 5 10 0 0 90 0 1
symversion=0.1
T 39800 43500 5 10 0 0 90 0 1
numslots=0
T 39600 43500 5 10 0 0 90 0 1
description=capacitor
T 40400 43500 8 10 0 1 90 0 1
refdes=C?
T 40200 43500 5 10 0 0 90 0 1
device=CAPACITOR
L 40700 43700 40700 43500 3 0 0 0 -1 -1
L 40700 44000 40700 43800 3 0 0 0 -1 -1
L 40500 43800 40900 43800 3 0 0 0 -1 -1
L 40500 43700 40900 43700 3 0 0 0 -1 -1
P 40700 44200 40700 44000 1 0 0
{
T 40650 44050 5 8 0 1 90 0 1
pinnumber=2
T 40750 44050 5 8 0 1 90 2 1
pinseq=2
T 40700 44000 9 8 0 1 90 6 1
pinlabel=2
T 40700 44000 5 8 0 1 90 8 1
pintype=pas
}
P 40700 43300 40700 43500 1 0 0
{
T 40650 43450 5 8 0 1 90 6 1
pinnumber=1
T 40750 43450 5 8 0 1 90 8 1
pinseq=1
T 40700 43500 9 8 0 1 90 0 1
pinlabel=1
T 40700 43500 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 40200 43500 5 10 0 0 90 0 1
device=CAPACITOR
T 40500 43900 5 10 1 1 180 0 1
refdes=C302
T 40000 43500 5 10 0 0 90 0 1
symversion=0.1
T 40000 43500 5 10 1 1 0 0 1
value=0.1uf
T 40900 43300 5 10 0 0 0 0 1
footprint=0603
}
C 42700 43300 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 41800 43500 5 10 0 0 90 0 1
symversion=0.1
T 41600 43500 5 10 0 0 90 0 1
numslots=0
T 41400 43500 5 10 0 0 90 0 1
description=capacitor
T 42200 43500 8 10 0 1 90 0 1
refdes=C?
T 42000 43500 5 10 0 0 90 0 1
device=CAPACITOR
L 42500 43700 42500 43500 3 0 0 0 -1 -1
L 42500 44000 42500 43800 3 0 0 0 -1 -1
L 42300 43800 42700 43800 3 0 0 0 -1 -1
L 42300 43700 42700 43700 3 0 0 0 -1 -1
P 42500 44200 42500 44000 1 0 0
{
T 42450 44050 5 8 0 1 90 0 1
pinnumber=2
T 42550 44050 5 8 0 1 90 2 1
pinseq=2
T 42500 44000 9 8 0 1 90 6 1
pinlabel=2
T 42500 44000 5 8 0 1 90 8 1
pintype=pas
}
P 42500 43300 42500 43500 1 0 0
{
T 42450 43450 5 8 0 1 90 6 1
pinnumber=1
T 42550 43450 5 8 0 1 90 8 1
pinseq=1
T 42500 43500 9 8 0 1 90 0 1
pinlabel=1
T 42500 43500 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 42000 43500 5 10 0 0 90 0 1
device=CAPACITOR
T 42300 43900 5 10 1 1 180 0 1
refdes=C303
T 41800 43500 5 10 0 0 90 0 1
symversion=0.1
T 41800 43500 5 10 1 1 0 0 1
value=0.1uf
T 42700 43300 5 10 0 0 0 0 1
footprint=0603
}
C 41800 44600 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 40900 44800 5 10 0 0 90 0 1
symversion=0.1
T 40700 44800 5 10 0 0 90 0 1
numslots=0
T 40500 44800 5 10 0 0 90 0 1
description=capacitor
T 41300 44800 8 10 0 1 90 0 1
refdes=C?
T 41100 44800 5 10 0 0 90 0 1
device=CAPACITOR
L 41600 45000 41600 44800 3 0 0 0 -1 -1
L 41600 45300 41600 45100 3 0 0 0 -1 -1
L 41400 45100 41800 45100 3 0 0 0 -1 -1
L 41400 45000 41800 45000 3 0 0 0 -1 -1
P 41600 45500 41600 45300 1 0 0
{
T 41550 45350 5 8 0 1 90 0 1
pinnumber=2
T 41650 45350 5 8 0 1 90 2 1
pinseq=2
T 41600 45300 9 8 0 1 90 6 1
pinlabel=2
T 41600 45300 5 8 0 1 90 8 1
pintype=pas
}
P 41600 44600 41600 44800 1 0 0
{
T 41550 44750 5 8 0 1 90 6 1
pinnumber=1
T 41650 44750 5 8 0 1 90 8 1
pinseq=1
T 41600 44800 9 8 0 1 90 0 1
pinlabel=1
T 41600 44800 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 41100 44800 5 10 0 0 90 0 1
device=CAPACITOR
T 41400 45200 5 10 1 1 180 0 1
refdes=C304
T 40900 44800 5 10 0 0 90 0 1
symversion=0.1
T 40900 44800 5 10 1 1 0 0 1
value=0.1uf
T 41800 44600 5 10 0 0 0 0 1
footprint=0603
}
C 42800 44600 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 41900 44800 5 10 0 0 90 0 1
symversion=0.1
T 41700 44800 5 10 0 0 90 0 1
numslots=0
T 41500 44800 5 10 0 0 90 0 1
description=capacitor
T 42300 44800 8 10 0 1 90 0 1
refdes=C?
T 42100 44800 5 10 0 0 90 0 1
device=CAPACITOR
L 42600 45000 42600 44800 3 0 0 0 -1 -1
L 42600 45300 42600 45100 3 0 0 0 -1 -1
L 42400 45100 42800 45100 3 0 0 0 -1 -1
L 42400 45000 42800 45000 3 0 0 0 -1 -1
P 42600 45500 42600 45300 1 0 0
{
T 42550 45350 5 8 0 1 90 0 1
pinnumber=2
T 42650 45350 5 8 0 1 90 2 1
pinseq=2
T 42600 45300 9 8 0 1 90 6 1
pinlabel=2
T 42600 45300 5 8 0 1 90 8 1
pintype=pas
}
P 42600 44600 42600 44800 1 0 0
{
T 42550 44750 5 8 0 1 90 6 1
pinnumber=1
T 42650 44750 5 8 0 1 90 8 1
pinseq=1
T 42600 44800 9 8 0 1 90 0 1
pinlabel=1
T 42600 44800 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 42100 44800 5 10 0 0 90 0 1
device=CAPACITOR
T 42400 45200 5 10 1 1 180 0 1
refdes=C305
T 41900 44800 5 10 0 0 90 0 1
symversion=0.1
T 41900 44800 5 10 1 1 0 0 1
value=0.1uf
T 42800 44600 5 10 0 0 0 0 1
footprint=0603
}
C 41800 43300 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 40900 43500 5 10 0 0 90 0 1
symversion=0.1
T 40700 43500 5 10 0 0 90 0 1
numslots=0
T 40500 43500 5 10 0 0 90 0 1
description=capacitor
T 41300 43500 8 10 0 1 90 0 1
refdes=C?
T 41100 43500 5 10 0 0 90 0 1
device=CAPACITOR
L 41600 43700 41600 43500 3 0 0 0 -1 -1
L 41600 44000 41600 43800 3 0 0 0 -1 -1
L 41400 43800 41800 43800 3 0 0 0 -1 -1
L 41400 43700 41800 43700 3 0 0 0 -1 -1
P 41600 44200 41600 44000 1 0 0
{
T 41550 44050 5 8 0 1 90 0 1
pinnumber=2
T 41650 44050 5 8 0 1 90 2 1
pinseq=2
T 41600 44000 9 8 0 1 90 6 1
pinlabel=2
T 41600 44000 5 8 0 1 90 8 1
pintype=pas
}
P 41600 43300 41600 43500 1 0 0
{
T 41550 43450 5 8 0 1 90 6 1
pinnumber=1
T 41650 43450 5 8 0 1 90 8 1
pinseq=1
T 41600 43500 9 8 0 1 90 0 1
pinlabel=1
T 41600 43500 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 41100 43500 5 10 0 0 90 0 1
device=CAPACITOR
T 41400 43900 5 10 1 1 180 0 1
refdes=C306
T 40900 43500 5 10 0 0 90 0 1
symversion=0.1
T 40900 43500 5 10 1 1 0 0 1
value=0.1uf
T 41800 43300 5 10 0 0 0 0 1
footprint=0603
}
C 42700 42100 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 41800 42300 5 10 0 0 90 0 1
symversion=0.1
T 41600 42300 5 10 0 0 90 0 1
numslots=0
T 41400 42300 5 10 0 0 90 0 1
description=capacitor
T 42200 42300 8 10 0 1 90 0 1
refdes=C?
T 42000 42300 5 10 0 0 90 0 1
device=CAPACITOR
L 42500 42500 42500 42300 3 0 0 0 -1 -1
L 42500 42800 42500 42600 3 0 0 0 -1 -1
L 42300 42600 42700 42600 3 0 0 0 -1 -1
L 42300 42500 42700 42500 3 0 0 0 -1 -1
P 42500 43000 42500 42800 1 0 0
{
T 42450 42850 5 8 0 1 90 0 1
pinnumber=2
T 42550 42850 5 8 0 1 90 2 1
pinseq=2
T 42500 42800 9 8 0 1 90 6 1
pinlabel=2
T 42500 42800 5 8 0 1 90 8 1
pintype=pas
}
P 42500 42100 42500 42300 1 0 0
{
T 42450 42250 5 8 0 1 90 6 1
pinnumber=1
T 42550 42250 5 8 0 1 90 8 1
pinseq=1
T 42500 42300 9 8 0 1 90 0 1
pinlabel=1
T 42500 42300 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 42000 42300 5 10 0 0 90 0 1
device=CAPACITOR
T 42300 42700 5 10 1 1 180 0 1
refdes=C307
T 41800 42300 5 10 0 0 90 0 1
symversion=0.1
T 41800 42300 5 10 1 1 0 0 1
value=0.1uf
T 42700 42100 5 10 0 0 0 0 1
footprint=0603
}
C 41800 42100 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 40900 42300 5 10 0 0 90 0 1
symversion=0.1
T 40700 42300 5 10 0 0 90 0 1
numslots=0
T 40500 42300 5 10 0 0 90 0 1
description=capacitor
T 41300 42300 8 10 0 1 90 0 1
refdes=C?
T 41100 42300 5 10 0 0 90 0 1
device=CAPACITOR
L 41600 42500 41600 42300 3 0 0 0 -1 -1
L 41600 42800 41600 42600 3 0 0 0 -1 -1
L 41400 42600 41800 42600 3 0 0 0 -1 -1
L 41400 42500 41800 42500 3 0 0 0 -1 -1
P 41600 43000 41600 42800 1 0 0
{
T 41550 42850 5 8 0 1 90 0 1
pinnumber=2
T 41650 42850 5 8 0 1 90 2 1
pinseq=2
T 41600 42800 9 8 0 1 90 6 1
pinlabel=2
T 41600 42800 5 8 0 1 90 8 1
pintype=pas
}
P 41600 42100 41600 42300 1 0 0
{
T 41550 42250 5 8 0 1 90 6 1
pinnumber=1
T 41650 42250 5 8 0 1 90 8 1
pinseq=1
T 41600 42300 9 8 0 1 90 0 1
pinlabel=1
T 41600 42300 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 41100 42300 5 10 0 0 90 0 1
device=CAPACITOR
T 41400 42700 5 10 1 1 180 0 1
refdes=C308
T 40900 42300 5 10 0 0 90 0 1
symversion=0.1
T 40900 42300 5 10 1 1 0 0 1
value=0.1uf
T 41800 42100 5 10 0 0 0 0 1
footprint=0603
}
C 40900 42100 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 40000 42300 5 10 0 0 90 0 1
symversion=0.1
T 39800 42300 5 10 0 0 90 0 1
numslots=0
T 39600 42300 5 10 0 0 90 0 1
description=capacitor
T 40400 42300 8 10 0 1 90 0 1
refdes=C?
T 40200 42300 5 10 0 0 90 0 1
device=CAPACITOR
L 40700 42500 40700 42300 3 0 0 0 -1 -1
L 40700 42800 40700 42600 3 0 0 0 -1 -1
L 40500 42600 40900 42600 3 0 0 0 -1 -1
L 40500 42500 40900 42500 3 0 0 0 -1 -1
P 40700 43000 40700 42800 1 0 0
{
T 40650 42850 5 8 0 1 90 0 1
pinnumber=2
T 40750 42850 5 8 0 1 90 2 1
pinseq=2
T 40700 42800 9 8 0 1 90 6 1
pinlabel=2
T 40700 42800 5 8 0 1 90 8 1
pintype=pas
}
P 40700 42100 40700 42300 1 0 0
{
T 40650 42250 5 8 0 1 90 6 1
pinnumber=1
T 40750 42250 5 8 0 1 90 8 1
pinseq=1
T 40700 42300 9 8 0 1 90 0 1
pinlabel=1
T 40700 42300 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 40200 42300 5 10 0 0 90 0 1
device=CAPACITOR
T 40500 42700 5 10 1 1 180 0 1
refdes=C309
T 40000 42300 5 10 0 0 90 0 1
symversion=0.1
T 40000 42300 5 10 1 1 0 0 1
value=0.1uf
T 40900 42100 5 10 0 0 0 0 1
footprint=0603
}
C 43700 42100 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 42800 42300 5 10 0 0 90 0 1
symversion=0.1
T 42600 42300 5 10 0 0 90 0 1
numslots=0
T 42400 42300 5 10 0 0 90 0 1
description=capacitor
T 43200 42300 8 10 0 1 90 0 1
refdes=C?
T 43000 42300 5 10 0 0 90 0 1
device=CAPACITOR
L 43500 42500 43500 42300 3 0 0 0 -1 -1
L 43500 42800 43500 42600 3 0 0 0 -1 -1
L 43300 42600 43700 42600 3 0 0 0 -1 -1
L 43300 42500 43700 42500 3 0 0 0 -1 -1
P 43500 43000 43500 42800 1 0 0
{
T 43450 42850 5 8 0 1 90 0 1
pinnumber=2
T 43550 42850 5 8 0 1 90 2 1
pinseq=2
T 43500 42800 9 8 0 1 90 6 1
pinlabel=2
T 43500 42800 5 8 0 1 90 8 1
pintype=pas
}
P 43500 42100 43500 42300 1 0 0
{
T 43450 42250 5 8 0 1 90 6 1
pinnumber=1
T 43550 42250 5 8 0 1 90 8 1
pinseq=1
T 43500 42300 9 8 0 1 90 0 1
pinlabel=1
T 43500 42300 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 43000 42300 5 10 0 0 90 0 1
device=CAPACITOR
T 43300 42700 5 10 1 1 180 0 1
refdes=C310
T 42800 42300 5 10 0 0 90 0 1
symversion=0.1
T 42800 42300 5 10 1 1 0 0 1
value=0.1uf
T 43700 42100 5 10 0 0 0 0 1
footprint=0603
}
C 43700 43300 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 42800 43500 5 10 0 0 90 0 1
symversion=0.1
T 42600 43500 5 10 0 0 90 0 1
numslots=0
T 42400 43500 5 10 0 0 90 0 1
description=capacitor
T 43200 43500 8 10 0 1 90 0 1
refdes=C?
T 43000 43500 5 10 0 0 90 0 1
device=CAPACITOR
L 43500 43700 43500 43500 3 0 0 0 -1 -1
L 43500 44000 43500 43800 3 0 0 0 -1 -1
L 43300 43800 43700 43800 3 0 0 0 -1 -1
L 43300 43700 43700 43700 3 0 0 0 -1 -1
P 43500 44200 43500 44000 1 0 0
{
T 43450 44050 5 8 0 1 90 0 1
pinnumber=2
T 43550 44050 5 8 0 1 90 2 1
pinseq=2
T 43500 44000 9 8 0 1 90 6 1
pinlabel=2
T 43500 44000 5 8 0 1 90 8 1
pintype=pas
}
P 43500 43300 43500 43500 1 0 0
{
T 43450 43450 5 8 0 1 90 6 1
pinnumber=1
T 43550 43450 5 8 0 1 90 8 1
pinseq=1
T 43500 43500 9 8 0 1 90 0 1
pinlabel=1
T 43500 43500 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 43000 43500 5 10 0 0 90 0 1
device=CAPACITOR
T 43300 43900 5 10 1 1 180 0 1
refdes=C311
T 42800 43500 5 10 0 0 90 0 1
symversion=0.1
T 42800 43500 5 10 1 1 0 0 1
value=0.1uf
T 43700 43300 5 10 0 0 0 0 1
footprint=0603
}
C 43700 44600 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 42800 44800 5 10 0 0 90 0 1
symversion=0.1
T 42600 44800 5 10 0 0 90 0 1
numslots=0
T 42400 44800 5 10 0 0 90 0 1
description=capacitor
T 43200 44800 8 10 0 1 90 0 1
refdes=C?
T 43000 44800 5 10 0 0 90 0 1
device=CAPACITOR
L 43500 45000 43500 44800 3 0 0 0 -1 -1
L 43500 45300 43500 45100 3 0 0 0 -1 -1
L 43300 45100 43700 45100 3 0 0 0 -1 -1
L 43300 45000 43700 45000 3 0 0 0 -1 -1
P 43500 45500 43500 45300 1 0 0
{
T 43450 45350 5 8 0 1 90 0 1
pinnumber=2
T 43550 45350 5 8 0 1 90 2 1
pinseq=2
T 43500 45300 9 8 0 1 90 6 1
pinlabel=2
T 43500 45300 5 8 0 1 90 8 1
pintype=pas
}
P 43500 44600 43500 44800 1 0 0
{
T 43450 44750 5 8 0 1 90 6 1
pinnumber=1
T 43550 44750 5 8 0 1 90 8 1
pinseq=1
T 43500 44800 9 8 0 1 90 0 1
pinlabel=1
T 43500 44800 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 43000 44800 5 10 0 0 90 0 1
device=CAPACITOR
T 43300 45200 5 10 1 1 180 0 1
refdes=C312
T 42800 44800 5 10 0 0 90 0 1
symversion=0.1
T 42800 44800 5 10 1 1 0 0 1
value=0.1uf
T 43700 44600 5 10 0 0 0 0 1
footprint=0603
}
N 40700 43000 44100 43000 4
N 40400 43300 43500 43300 4
N 40400 44600 43500 44600 4
N 40400 42100 43500 42100 4
N 40400 44600 40400 40200 4
C 40300 39900 1 0 0 EMBEDDEDgnd-1.sym
[
T 40600 39950 8 10 0 0 0 0 1
net=GND:1
L 40380 39910 40420 39910 3 0 0 0 -1 -1
L 40355 39950 40445 39950 3 0 0 0 -1 -1
L 40300 40000 40500 40000 3 0 0 0 -1 -1
P 40400 40000 40400 40200 1 0 1
{
T 40458 40061 5 4 0 1 0 0 1
pinnumber=1
T 40458 40061 5 4 0 0 0 0 1
pinseq=1
T 40458 40061 5 4 0 1 0 0 1
pinlabel=1
T 40458 40061 5 4 0 1 0 0 1
pintype=pwr
}
]
N 40700 45500 43700 45500 4
C 43700 45600 1 180 1 EMBEDDEDoutput-1.sym
[
T 43800 45300 5 10 0 0 180 6 1
device=OUTPUT
L 44400 45600 43900 45600 3 0 0 0 -1 -1
L 44500 45500 44400 45600 3 0 0 0 -1 -1
L 44400 45400 44500 45500 3 0 0 0 -1 -1
L 43900 45400 44400 45400 3 0 0 0 -1 -1
L 43900 45400 43900 45600 3 0 0 0 -1 -1
P 43700 45500 43900 45500 1 0 0
{
T 43950 45550 5 6 0 1 180 6 1
pinnumber=1
T 43950 45550 5 6 0 0 180 6 1
pinseq=1
}
]
{
T 43800 45300 5 10 0 0 180 6 1
device=OUTPUT
T 44600 45600 5 10 1 1 180 6 1
value=VCCINT
T 43700 45600 5 10 0 1 0 6 1
net=VCCINT:1
}
C 43900 44200 1 0 0 EMBEDDED3.3V-plus-1.sym
[
T 44200 44200 8 8 0 0 0 0 1
net=+3.3V:1
T 43975 44450 9 8 1 0 0 0 1
+3.3V
L 43950 44400 44250 44400 3 0 0 0 -1 -1
P 44100 44200 44100 44400 1 0 0
{
T 44150 44250 5 6 0 1 0 0 1
pinnumber=1
T 44150 44250 5 6 0 0 0 0 1
pinseq=1
T 44150 44250 5 6 0 1 0 0 1
pinlabel=1
T 44150 44250 5 6 0 1 0 0 1
pintype=pwr
}
]
C 40900 40800 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 40000 41000 5 10 0 0 90 0 1
symversion=0.1
T 39800 41000 5 10 0 0 90 0 1
numslots=0
T 39600 41000 5 10 0 0 90 0 1
description=capacitor
T 40400 41000 8 10 0 1 90 0 1
refdes=C?
T 40200 41000 5 10 0 0 90 0 1
device=CAPACITOR
L 40700 41200 40700 41000 3 0 0 0 -1 -1
L 40700 41500 40700 41300 3 0 0 0 -1 -1
L 40500 41300 40900 41300 3 0 0 0 -1 -1
L 40500 41200 40900 41200 3 0 0 0 -1 -1
P 40700 41700 40700 41500 1 0 0
{
T 40650 41550 5 8 0 1 90 0 1
pinnumber=2
T 40750 41550 5 8 0 1 90 2 1
pinseq=2
T 40700 41500 9 8 0 1 90 6 1
pinlabel=2
T 40700 41500 5 8 0 1 90 8 1
pintype=pas
}
P 40700 40800 40700 41000 1 0 0
{
T 40650 40950 5 8 0 1 90 6 1
pinnumber=1
T 40750 40950 5 8 0 1 90 8 1
pinseq=1
T 40700 41000 9 8 0 1 90 0 1
pinlabel=1
T 40700 41000 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 40200 41000 5 10 0 0 90 0 1
device=CAPACITOR
T 40500 41400 5 10 1 1 180 0 1
refdes=C315
T 40000 41000 5 10 0 0 90 0 1
symversion=0.1
T 40000 41000 5 10 1 1 0 0 1
value=0.1uf
T 40900 40800 5 10 0 0 0 0 1
footprint=0603
}
N 40700 44200 44100 44200 4
N 50000 52400 50000 53200 4
N 49800 53200 49800 52400 4
N 49000 53200 49000 52400 4
N 48800 53200 48800 52400 4
T 54300 40400 9 10 1 0 0 0 1
BeagleBone FPGA board V1.5: FPGA
T 54400 39800 9 10 1 0 0 0 1
3
T 55900 39800 9 10 1 0 0 0 1
3
T 58100 40100 9 10 1 0 0 0 1
-
N 50400 43800 50400 44400 4
N 50600 43800 50600 44400 4
N 52800 44200 52000 44200 4
N 45000 50400 45900 50400 4
N 45000 50200 45900 50200 4
N 45000 50000 45900 50000 4
N 45000 49800 45900 49800 4
N 45000 49200 45900 49200 4
N 45000 49000 45900 49000 4
N 45000 48600 45900 48600 4
N 45000 48400 45900 48400 4
N 45000 48000 45900 48000 4
N 45000 47800 45900 47800 4
N 45000 47200 45900 47200 4
N 45000 47000 45900 47000 4
C 50900 43800 1 270 0 EMBEDDEDoutput-1.sym
[
P 51000 43800 51000 43600 1 0 0
{
T 50950 43550 5 6 0 1 270 0 1
pinnumber=1
T 50950 43550 5 6 0 0 270 0 1
pinseq=1
}
L 51100 43600 50900 43600 3 0 0 0 -1 -1
L 51100 43600 51100 43100 3 0 0 0 -1 -1
L 51100 43100 51000 43000 3 0 0 0 -1 -1
L 51000 43000 50900 43100 3 0 0 0 -1 -1
L 50900 43100 50900 43600 3 0 0 0 -1 -1
T 51200 43700 5 10 0 0 270 0 1
device=OUTPUT
]
{
T 51200 43700 5 10 0 0 270 0 1
device=OUTPUT
T 51100 41800 5 10 1 1 90 0 1
value=FPGA_CLK50
T 50900 43800 5 10 0 1 90 0 1
net=FPGA_CLK50:1
}
N 51000 44400 51000 43800 4
N 47800 41700 47800 44400 4
N 52400 43700 52800 43700 4
N 54000 49000 56700 49000 4
N 56700 48800 54000 48800 4
N 56700 47000 54000 47000 4
N 56700 47200 54000 47200 4
C 47700 53200 1 270 1 EMBEDDEDoutput-1.sym
[
P 47800 53200 47800 53400 1 0 0
{
T 47750 53450 5 6 0 1 270 6 1
pinnumber=1
T 47750 53450 5 6 0 0 270 6 1
pinseq=1
}
L 47900 53400 47700 53400 3 0 0 0 -1 -1
L 47900 53400 47900 53900 3 0 0 0 -1 -1
L 47900 53900 47800 54000 3 0 0 0 -1 -1
L 47800 54000 47700 53900 3 0 0 0 -1 -1
L 47700 53900 47700 53400 3 0 0 0 -1 -1
T 48000 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 48000 53300 5 10 0 0 270 6 1
device=OUTPUT
T 47900 54300 5 10 1 1 90 6 1
value=JA0
T 47700 53200 5 10 0 1 90 6 1
net=JA0:1
}
C 50500 53200 1 270 1 EMBEDDEDoutput-1.sym
[
L 50500 53900 50500 53400 3 0 0 0 -1 -1
L 50600 54000 50500 53900 3 0 0 0 -1 -1
L 50700 53900 50600 54000 3 0 0 0 -1 -1
L 50700 53400 50700 53900 3 0 0 0 -1 -1
L 50700 53400 50500 53400 3 0 0 0 -1 -1
P 50600 53200 50600 53400 1 0 0
{
T 50550 53450 5 6 0 0 270 6 1
pinseq=1
T 50550 53450 5 6 0 1 270 6 1
pinnumber=1
}
T 50800 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 50800 53300 5 10 0 0 270 6 1
device=OUTPUT
T 50700 54300 5 10 1 1 90 6 1
value=JB0
T 50500 53200 5 10 0 1 90 6 1
net=JB0:1
}
C 56700 49700 1 0 0 EMBEDDEDoutput-1.sym
[
L 57400 49700 56900 49700 3 0 0 0 -1 -1
L 57500 49800 57400 49700 3 0 0 0 -1 -1
L 57400 49900 57500 49800 3 0 0 0 -1 -1
L 56900 49900 57400 49900 3 0 0 0 -1 -1
L 56900 49900 56900 49700 3 0 0 0 -1 -1
P 56700 49800 56900 49800 1 0 0
{
T 56950 49750 5 6 0 0 0 0 1
pinseq=1
T 56950 49750 5 6 0 1 0 0 1
pinnumber=1
}
T 56800 50000 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 56800 50000 5 10 0 0 0 0 1
device=OUTPUT
T 57500 49700 5 10 1 1 0 0 1
value=JC0
T 56700 49700 5 10 0 1 180 0 1
net=JC0:1
}
C 56700 50100 1 180 1 EMBEDDEDoutput-1.sym
[
L 57400 50100 56900 50100 3 0 0 0 -1 -1
L 57500 50000 57400 50100 3 0 0 0 -1 -1
L 57400 49900 57500 50000 3 0 0 0 -1 -1
L 56900 49900 57400 49900 3 0 0 0 -1 -1
L 56900 49900 56900 50100 3 0 0 0 -1 -1
P 56700 50000 56900 50000 1 0 0
{
T 56950 50050 5 6 0 0 180 6 1
pinseq=1
T 56950 50050 5 6 0 1 180 6 1
pinnumber=1
}
T 56800 49800 5 10 0 0 180 6 1
device=OUTPUT
]
{
T 56800 49800 5 10 0 0 180 6 1
device=OUTPUT
T 57800 49900 5 10 1 1 0 6 1
value=JB7
T 56700 50100 5 10 0 1 0 6 1
net=JB7:1
}
C 56700 47100 1 0 0 EMBEDDEDoutput-1.sym
[
L 57400 47100 56900 47100 3 0 0 0 -1 -1
L 57500 47200 57400 47100 3 0 0 0 -1 -1
L 57400 47300 57500 47200 3 0 0 0 -1 -1
L 56900 47300 57400 47300 3 0 0 0 -1 -1
L 56900 47300 56900 47100 3 0 0 0 -1 -1
P 56700 47200 56900 47200 1 0 0
{
T 56950 47150 5 6 0 0 0 0 1
pinseq=1
T 56950 47150 5 6 0 1 0 0 1
pinnumber=1
}
T 56800 47400 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 56800 47400 5 10 0 0 0 0 1
device=OUTPUT
T 57500 47100 5 10 1 1 0 0 1
value=JC7
T 56700 47100 5 10 0 1 180 0 1
net=JC7:1
}
C 50300 53200 1 270 1 EMBEDDEDoutput-1.sym
[
T 50600 53300 5 10 0 0 270 6 1
device=OUTPUT
L 50300 53900 50300 53400 3 0 0 0 -1 -1
L 50400 54000 50300 53900 3 0 0 0 -1 -1
L 50500 53900 50400 54000 3 0 0 0 -1 -1
L 50500 53400 50500 53900 3 0 0 0 -1 -1
L 50500 53400 50300 53400 3 0 0 0 -1 -1
P 50400 53200 50400 53400 1 0 0
{
T 50350 53450 5 6 0 1 270 6 1
pinnumber=1
T 50350 53450 5 6 0 0 270 6 1
pinseq=1
}
]
{
T 50600 53300 5 10 0 0 270 6 1
device=OUTPUT
T 50500 54300 5 10 1 1 90 6 1
value=JA7
T 50300 53200 5 10 0 1 90 6 1
net=JA7:1
}
N 49600 52400 49600 53200 4
N 52000 52400 52000 53200 4
N 52200 52400 52200 53200 4
N 48000 53200 48000 52400 4
N 47800 53200 47800 52400 4
C 47400 52500 1 180 0 EMBEDDEDresistor-1.sym
[
L 46800 52300 46900 52500 3 0 0 0 -1 -1
L 46900 52500 47000 52300 3 0 0 0 -1 -1
L 47000 52300 47100 52500 3 0 0 0 -1 -1
L 47100 52500 47200 52300 3 0 0 0 -1 -1
L 46800 52300 46700 52500 3 0 0 0 -1 -1
L 46700 52500 46650 52400 3 0 0 0 -1 -1
P 46500 52400 46650 52400 1 0 0
{
T 46600 52350 5 8 0 1 180 0 1
pinnumber=2
T 46600 52350 5 8 0 0 180 0 1
pinseq=2
T 46600 52350 5 8 0 1 180 0 1
pinlabel=2
T 46600 52350 5 8 0 1 180 0 1
pintype=pas
}
P 47400 52400 47248 52400 1 0 0
{
T 47300 52350 5 8 0 1 180 0 1
pinnumber=1
T 47300 52350 5 8 0 0 180 0 1
pinseq=1
T 47300 52350 5 8 0 1 180 0 1
pinlabel=1
T 47300 52350 5 8 0 1 180 0 1
pintype=pas
}
L 47199 52300 47250 52400 3 0 0 0 -1 -1
T 47100 52100 5 10 0 0 180 0 1
device=RESISTOR
T 47200 52200 8 10 0 1 180 0 1
refdes=R?
T 47400 52500 8 10 0 1 180 0 1
pins=2
T 47400 52500 8 10 0 1 180 0 1
class=DISCRETE
]
{
T 47100 52100 5 10 0 0 180 0 1
device=RESISTOR
T 46900 52100 5 10 1 1 0 0 1
refdes=R305
T 46500 52100 5 10 1 1 0 0 1
value=1k
T 47400 52500 5 10 0 0 270 0 1
footprint=0805
}
N 46500 52400 46300 52400 4
N 47800 52500 47400 52500 4
N 47400 52500 47400 52400 4
N 45000 47600 45900 47600 4
C 48700 53200 1 270 1 EMBEDDEDoutput-1.sym
[
P 48800 53200 48800 53400 1 0 0
{
T 48750 53450 5 6 0 0 270 6 1
pinseq=1
T 48750 53450 5 6 0 1 270 6 1
pinnumber=1
}
L 48900 53400 48700 53400 3 0 0 0 -1 -1
L 48900 53400 48900 53900 3 0 0 0 -1 -1
L 48900 53900 48800 54000 3 0 0 0 -1 -1
L 48800 54000 48700 53900 3 0 0 0 -1 -1
L 48700 53900 48700 53400 3 0 0 0 -1 -1
T 49000 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 49000 53300 5 10 0 0 270 6 1
device=OUTPUT
T 48900 54300 5 10 1 1 90 6 1
value=JA1
T 48700 53200 5 10 0 1 90 6 1
net=JA1:1
}
C 47900 53200 1 270 1 EMBEDDEDoutput-1.sym
[
L 47900 53900 47900 53400 3 0 0 0 -1 -1
L 48000 54000 47900 53900 3 0 0 0 -1 -1
L 48100 53900 48000 54000 3 0 0 0 -1 -1
L 48100 53400 48100 53900 3 0 0 0 -1 -1
L 48100 53400 47900 53400 3 0 0 0 -1 -1
P 48000 53200 48000 53400 1 0 0
{
T 47950 53450 5 6 0 0 270 6 1
pinseq=1
T 47950 53450 5 6 0 1 270 6 1
pinnumber=1
}
T 48200 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 48200 53300 5 10 0 0 270 6 1
device=OUTPUT
T 48100 54300 5 10 1 1 90 6 1
value=JA4
T 47900 53200 5 10 0 1 90 6 1
net=JA4:1
}
C 49900 53200 1 270 1 EMBEDDEDoutput-1.sym
[
P 50000 53200 50000 53400 1 0 0
{
T 49950 53450 5 6 0 0 270 6 1
pinseq=1
T 49950 53450 5 6 0 1 270 6 1
pinnumber=1
}
L 50100 53400 49900 53400 3 0 0 0 -1 -1
L 50100 53400 50100 53900 3 0 0 0 -1 -1
L 50100 53900 50000 54000 3 0 0 0 -1 -1
L 50000 54000 49900 53900 3 0 0 0 -1 -1
L 49900 53900 49900 53400 3 0 0 0 -1 -1
T 50200 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 50200 53300 5 10 0 0 270 6 1
device=OUTPUT
T 50100 54300 5 10 1 1 90 6 1
value=JA3
T 49900 53200 5 10 0 1 90 6 1
net=JA3:1
}
C 48900 53200 1 270 1 EMBEDDEDoutput-1.sym
[
L 48900 53900 48900 53400 3 0 0 0 -1 -1
L 49000 54000 48900 53900 3 0 0 0 -1 -1
L 49100 53900 49000 54000 3 0 0 0 -1 -1
L 49100 53400 49100 53900 3 0 0 0 -1 -1
L 49100 53400 48900 53400 3 0 0 0 -1 -1
P 49000 53200 49000 53400 1 0 0
{
T 48950 53450 5 6 0 1 270 6 1
pinnumber=1
T 48950 53450 5 6 0 0 270 6 1
pinseq=1
}
T 49200 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 49200 53300 5 10 0 0 270 6 1
device=OUTPUT
T 49100 54300 5 10 1 1 90 6 1
value=JA5
T 48900 53200 5 10 0 1 90 6 1
net=JA5:1
}
C 49500 53200 1 270 1 EMBEDDEDoutput-1.sym
[
L 49500 53900 49500 53400 3 0 0 0 -1 -1
L 49600 54000 49500 53900 3 0 0 0 -1 -1
L 49700 53900 49600 54000 3 0 0 0 -1 -1
L 49700 53400 49700 53900 3 0 0 0 -1 -1
L 49700 53400 49500 53400 3 0 0 0 -1 -1
P 49600 53200 49600 53400 1 0 0
{
T 49550 53450 5 6 0 1 270 6 1
pinnumber=1
T 49550 53450 5 6 0 0 270 6 1
pinseq=1
}
T 49800 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 49800 53300 5 10 0 0 270 6 1
device=OUTPUT
T 49700 54300 5 10 1 1 90 6 1
value=JA2
T 49500 53200 5 10 0 1 90 6 1
net=JA2:1
}
C 49700 53200 1 270 1 EMBEDDEDoutput-1.sym
[
L 49700 53900 49700 53400 3 0 0 0 -1 -1
L 49800 54000 49700 53900 3 0 0 0 -1 -1
L 49900 53900 49800 54000 3 0 0 0 -1 -1
L 49900 53400 49900 53900 3 0 0 0 -1 -1
L 49900 53400 49700 53400 3 0 0 0 -1 -1
P 49800 53200 49800 53400 1 0 0
{
T 49750 53450 5 6 0 1 270 6 1
pinnumber=1
T 49750 53450 5 6 0 0 270 6 1
pinseq=1
}
T 50000 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 50000 53300 5 10 0 0 270 6 1
device=OUTPUT
T 49900 54300 5 10 1 1 90 6 1
value=JA6
T 49700 53200 5 10 0 1 90 6 1
net=JA6:1
}
C 50900 53200 1 270 1 EMBEDDEDoutput-1.sym
[
L 50900 53900 50900 53400 3 0 0 0 -1 -1
L 51000 54000 50900 53900 3 0 0 0 -1 -1
L 51100 53900 51000 54000 3 0 0 0 -1 -1
L 51100 53400 51100 53900 3 0 0 0 -1 -1
L 51100 53400 50900 53400 3 0 0 0 -1 -1
P 51000 53200 51000 53400 1 0 0
{
T 50950 53450 5 6 0 1 270 6 1
pinnumber=1
T 50950 53450 5 6 0 0 270 6 1
pinseq=1
}
T 51200 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 51200 53300 5 10 0 0 270 6 1
device=OUTPUT
T 51100 54300 5 10 1 1 90 6 1
value=JB1
T 50900 53200 5 10 0 1 90 6 1
net=JB1:1
}
C 52100 53200 1 270 1 EMBEDDEDoutput-1.sym
[
L 52100 53900 52100 53400 3 0 0 0 -1 -1
L 52200 54000 52100 53900 3 0 0 0 -1 -1
L 52300 53900 52200 54000 3 0 0 0 -1 -1
L 52300 53400 52300 53900 3 0 0 0 -1 -1
L 52300 53400 52100 53400 3 0 0 0 -1 -1
P 52200 53200 52200 53400 1 0 0
{
T 52150 53450 5 6 0 1 270 6 1
pinnumber=1
T 52150 53450 5 6 0 0 270 6 1
pinseq=1
}
T 52400 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 52400 53300 5 10 0 0 270 6 1
device=OUTPUT
T 52300 54300 5 10 1 1 90 6 1
value=JB2
T 52100 53200 5 10 0 1 90 6 1
net=JB2:1
}
C 50700 53200 1 270 1 EMBEDDEDoutput-1.sym
[
L 50700 53900 50700 53400 3 0 0 0 -1 -1
L 50800 54000 50700 53900 3 0 0 0 -1 -1
L 50900 53900 50800 54000 3 0 0 0 -1 -1
L 50900 53400 50900 53900 3 0 0 0 -1 -1
L 50900 53400 50700 53400 3 0 0 0 -1 -1
P 50800 53200 50800 53400 1 0 0
{
T 50750 53450 5 6 0 1 270 6 1
pinnumber=1
T 50750 53450 5 6 0 0 270 6 1
pinseq=1
}
T 51000 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 51000 53300 5 10 0 0 270 6 1
device=OUTPUT
T 50900 54300 5 10 1 1 90 6 1
value=JB4
T 50700 53200 5 10 0 1 90 6 1
net=JB4:1
}
C 51900 53200 1 270 1 EMBEDDEDoutput-1.sym
[
L 51900 53900 51900 53400 3 0 0 0 -1 -1
L 52000 54000 51900 53900 3 0 0 0 -1 -1
L 52100 53900 52000 54000 3 0 0 0 -1 -1
L 52100 53400 52100 53900 3 0 0 0 -1 -1
L 52100 53400 51900 53400 3 0 0 0 -1 -1
P 52000 53200 52000 53400 1 0 0
{
T 51950 53450 5 6 0 1 270 6 1
pinnumber=1
T 51950 53450 5 6 0 0 270 6 1
pinseq=1
}
T 52200 53300 5 10 0 0 270 6 1
device=OUTPUT
]
{
T 52200 53300 5 10 0 0 270 6 1
device=OUTPUT
T 52100 54300 5 10 1 1 90 6 1
value=JB5
T 51900 53200 5 10 0 1 90 6 1
net=JB5:1
}
C 56700 50500 1 180 1 EMBEDDEDoutput-1.sym
[
P 56700 50400 56900 50400 1 0 0
{
T 56950 50450 5 6 0 0 180 6 1
pinseq=1
T 56950 50450 5 6 0 1 180 6 1
pinnumber=1
}
L 56900 50300 56900 50500 3 0 0 0 -1 -1
L 56900 50300 57400 50300 3 0 0 0 -1 -1
L 57400 50300 57500 50400 3 0 0 0 -1 -1
L 57500 50400 57400 50500 3 0 0 0 -1 -1
L 57400 50500 56900 50500 3 0 0 0 -1 -1
T 56800 50200 5 10 0 0 180 6 1
device=OUTPUT
]
{
T 56800 50200 5 10 0 0 180 6 1
device=OUTPUT
T 57800 50300 5 10 1 1 0 6 1
value=JB6
T 56700 50500 5 10 0 1 0 6 1
net=JB6:1
}
C 56700 50300 1 180 1 EMBEDDEDoutput-1.sym
[
P 56700 50200 56900 50200 1 0 0
{
T 56950 50250 5 6 0 0 180 6 1
pinseq=1
T 56950 50250 5 6 0 1 180 6 1
pinnumber=1
}
L 56900 50100 56900 50300 3 0 0 0 -1 -1
L 56900 50100 57400 50100 3 0 0 0 -1 -1
L 57400 50100 57500 50200 3 0 0 0 -1 -1
L 57500 50200 57400 50300 3 0 0 0 -1 -1
L 57400 50300 56900 50300 3 0 0 0 -1 -1
T 56800 50000 5 10 0 0 180 6 1
device=OUTPUT
]
{
T 56800 50000 5 10 0 0 180 6 1
device=OUTPUT
T 57800 50100 5 10 1 1 0 6 1
value=JB3
T 56700 50300 5 10 0 1 0 6 1
net=JB3:1
}
C 56700 48700 1 0 0 EMBEDDEDoutput-1.sym
[
L 57400 48700 56900 48700 3 0 0 0 -1 -1
L 57500 48800 57400 48700 3 0 0 0 -1 -1
L 57400 48900 57500 48800 3 0 0 0 -1 -1
L 56900 48900 57400 48900 3 0 0 0 -1 -1
L 56900 48900 56900 48700 3 0 0 0 -1 -1
P 56700 48800 56900 48800 1 0 0
{
T 56950 48750 5 6 0 1 0 0 1
pinnumber=1
T 56950 48750 5 6 0 0 0 0 1
pinseq=1
}
T 56800 49000 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 56800 49000 5 10 0 0 0 0 1
device=OUTPUT
T 57500 48700 5 10 1 1 0 0 1
value=JC4
T 56700 48700 5 10 0 1 180 0 1
net=JC4:1
}
C 56700 48500 1 0 0 EMBEDDEDoutput-1.sym
[
L 57400 48500 56900 48500 3 0 0 0 -1 -1
L 57500 48600 57400 48500 3 0 0 0 -1 -1
L 57400 48700 57500 48600 3 0 0 0 -1 -1
L 56900 48700 57400 48700 3 0 0 0 -1 -1
L 56900 48700 56900 48500 3 0 0 0 -1 -1
P 56700 48600 56900 48600 1 0 0
{
T 56950 48550 5 6 0 1 0 0 1
pinnumber=1
T 56950 48550 5 6 0 0 0 0 1
pinseq=1
}
T 56800 48800 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 56800 48800 5 10 0 0 0 0 1
device=OUTPUT
T 57500 48500 5 10 1 1 0 0 1
value=JC1
T 56700 48500 5 10 0 1 180 0 1
net=JC1:1
}
C 56700 48100 1 0 0 EMBEDDEDoutput-1.sym
[
L 57400 48100 56900 48100 3 0 0 0 -1 -1
L 57500 48200 57400 48100 3 0 0 0 -1 -1
L 57400 48300 57500 48200 3 0 0 0 -1 -1
L 56900 48300 57400 48300 3 0 0 0 -1 -1
L 56900 48300 56900 48100 3 0 0 0 -1 -1
P 56700 48200 56900 48200 1 0 0
{
T 56950 48150 5 6 0 1 0 0 1
pinnumber=1
T 56950 48150 5 6 0 0 0 0 1
pinseq=1
}
T 56800 48400 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 56800 48400 5 10 0 0 0 0 1
device=OUTPUT
T 57500 48100 5 10 1 1 0 0 1
value=JC5
T 56700 48100 5 10 0 1 180 0 1
net=JC5:1
}
C 56700 47900 1 0 0 EMBEDDEDoutput-1.sym
[
P 56700 48000 56900 48000 1 0 0
{
T 56950 47950 5 6 0 0 0 0 1
pinseq=1
T 56950 47950 5 6 0 1 0 0 1
pinnumber=1
}
L 56900 48100 56900 47900 3 0 0 0 -1 -1
L 56900 48100 57400 48100 3 0 0 0 -1 -1
L 57400 48100 57500 48000 3 0 0 0 -1 -1
L 57500 48000 57400 47900 3 0 0 0 -1 -1
L 57400 47900 56900 47900 3 0 0 0 -1 -1
T 56800 48200 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 56800 48200 5 10 0 0 0 0 1
device=OUTPUT
T 57500 47900 5 10 1 1 0 0 1
value=JC2
T 56700 47900 5 10 0 1 180 0 1
net=JC2:1
}
C 56700 47500 1 0 0 EMBEDDEDoutput-1.sym
[
P 56700 47600 56900 47600 1 0 0
{
T 56950 47550 5 6 0 0 0 0 1
pinseq=1
T 56950 47550 5 6 0 1 0 0 1
pinnumber=1
}
L 56900 47700 56900 47500 3 0 0 0 -1 -1
L 56900 47700 57400 47700 3 0 0 0 -1 -1
L 57400 47700 57500 47600 3 0 0 0 -1 -1
L 57500 47600 57400 47500 3 0 0 0 -1 -1
L 57400 47500 56900 47500 3 0 0 0 -1 -1
T 56800 47800 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 56800 47800 5 10 0 0 0 0 1
device=OUTPUT
T 57500 47500 5 10 1 1 0 0 1
value=JC3
T 56700 47500 5 10 0 1 180 0 1
net=JC3:1
}
C 56700 47700 1 0 0 EMBEDDEDoutput-1.sym
[
L 57400 47700 56900 47700 3 0 0 0 -1 -1
L 57500 47800 57400 47700 3 0 0 0 -1 -1
L 57400 47900 57500 47800 3 0 0 0 -1 -1
L 56900 47900 57400 47900 3 0 0 0 -1 -1
L 56900 47900 56900 47700 3 0 0 0 -1 -1
P 56700 47800 56900 47800 1 0 0
{
T 56950 47750 5 6 0 1 0 0 1
pinnumber=1
T 56950 47750 5 6 0 0 0 0 1
pinseq=1
}
T 56800 48000 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 56800 48000 5 10 0 0 0 0 1
device=OUTPUT
T 57500 47700 5 10 1 1 0 0 1
value=JC6
T 56700 47700 5 10 0 1 180 0 1
net=JC6:1
}
C 45000 47700 1 180 0 EMBEDDEDoutput-1.sym
[
T 44900 47400 5 10 0 0 180 0 1
device=OUTPUT
L 44300 47700 44800 47700 3 0 0 0 -1 -1
L 44200 47600 44300 47700 3 0 0 0 -1 -1
L 44300 47500 44200 47600 3 0 0 0 -1 -1
L 44800 47500 44300 47500 3 0 0 0 -1 -1
L 44800 47500 44800 47700 3 0 0 0 -1 -1
P 45000 47600 44800 47600 1 0 0
{
T 44750 47650 5 6 0 1 180 0 1
pinnumber=1
T 44750 47650 5 6 0 0 180 0 1
pinseq=1
}
]
{
T 44900 47400 5 10 0 0 180 0 1
device=OUTPUT
T 44100 47700 5 10 1 1 180 0 1
value=VCCINT
T 45000 47700 5 10 0 1 0 0 1
net=VCCINT:1
}
C 41800 47900 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 41100 48100 5 10 0 0 90 0 1
device=CAPACITOR
T 41300 48100 8 10 0 1 90 0 1
refdes=C?
T 40500 48100 5 10 0 0 90 0 1
description=capacitor
T 40700 48100 5 10 0 0 90 0 1
numslots=0
T 40900 48100 5 10 0 0 90 0 1
symversion=0.1
P 41600 47900 41600 48100 1 0 0
{
T 41550 48050 5 8 0 1 90 6 1
pinnumber=1
T 41650 48050 5 8 0 1 90 8 1
pinseq=1
T 41600 48100 9 8 0 1 90 0 1
pinlabel=1
T 41600 48100 5 8 0 1 90 2 1
pintype=pas
}
P 41600 48800 41600 48600 1 0 0
{
T 41550 48650 5 8 0 1 90 0 1
pinnumber=2
T 41650 48650 5 8 0 1 90 2 1
pinseq=2
T 41600 48600 9 8 0 1 90 6 1
pinlabel=2
T 41600 48600 5 8 0 1 90 8 1
pintype=pas
}
L 41400 48300 41800 48300 3 0 0 0 -1 -1
L 41400 48400 41800 48400 3 0 0 0 -1 -1
L 41600 48600 41600 48400 3 0 0 0 -1 -1
L 41600 48300 41600 48100 3 0 0 0 -1 -1
]
{
T 41100 48100 5 10 0 0 90 0 1
device=CAPACITOR
T 41300 48500 5 10 1 1 180 0 1
refdes=C314
T 40900 48100 5 10 0 0 90 0 1
symversion=0.1
T 40900 48100 5 10 1 1 0 0 1
value=0.1uf
T 41800 47900 5 10 0 0 0 0 1
footprint=0603
}
C 41500 47600 1 0 0 EMBEDDEDgnd-1.sym
[
T 41800 47650 8 10 0 0 0 0 1
net=GND:1
P 41600 47700 41600 47900 1 0 1
{
T 41658 47761 5 4 0 1 0 0 1
pinnumber=1
T 41658 47761 5 4 0 0 0 0 1
pinseq=1
T 41658 47761 5 4 0 1 0 0 1
pinlabel=1
T 41658 47761 5 4 0 1 0 0 1
pintype=pwr
}
L 41500 47700 41700 47700 3 0 0 0 -1 -1
L 41555 47650 41645 47650 3 0 0 0 -1 -1
L 41580 47610 41620 47610 3 0 0 0 -1 -1
]
N 45900 46400 45700 46400 4
N 45900 46200 45700 46200 4
C 58200 41600 1 0 0 EMBEDDEDm25p20.sym
[
P 59900 42300 60200 42300 1 0 1
{
T 60050 42350 5 10 1 1 0 0 1
pinnumber=8
T 60050 42350 5 10 0 0 0 0 1
pinseq=8
T 59850 42250 5 10 1 1 0 6 1
pinlabel=VDD
T 60050 42350 5 10 0 1 0 0 1
pintype=pas
}
B 58500 41600 1400 900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 59900 42100 60200 42100 1 0 1
{
T 60050 42150 5 10 1 1 0 0 1
pinnumber=7
T 60050 42150 5 10 0 0 0 0 1
pinseq=7
T 59850 42050 5 10 1 1 0 6 1
pinlabel=/HOLD
T 60050 42150 5 10 0 1 0 0 1
pintype=pas
}
P 59900 41900 60200 41900 1 0 1
{
T 60050 41950 5 10 1 1 0 0 1
pinnumber=6
T 60050 41950 5 10 0 0 0 0 1
pinseq=6
T 59850 41850 5 10 1 1 0 6 1
pinlabel=C
T 60050 41950 5 10 0 1 0 0 1
pintype=pas
}
P 58200 42300 58500 42300 1 0 0
{
T 58100 42300 5 10 0 0 0 0 1
pintype=pas
T 58555 42295 5 10 1 1 0 0 1
pinlabel=/S
T 58405 42345 5 10 1 1 0 6 1
pinnumber=1
T 58100 42300 5 10 0 0 0 0 1
pinseq=1
}
P 58200 42100 58500 42100 1 0 0
{
T 58100 42100 5 10 0 0 0 0 1
pintype=pas
T 58555 42095 5 10 1 1 0 0 1
pinlabel=Q
T 58405 42145 5 10 1 1 0 6 1
pinnumber=2
T 58100 42100 5 10 0 0 0 0 1
pinseq=2
}
P 58200 41900 58500 41900 1 0 0
{
T 58100 41900 5 10 0 0 0 0 1
pintype=pas
T 58555 41895 5 10 1 1 0 0 1
pinlabel=/W
T 58405 41945 5 10 1 1 0 6 1
pinnumber=3
T 58100 41900 5 10 0 0 0 0 1
pinseq=3
}
P 58200 41700 58500 41700 1 0 0
{
T 58100 41700 5 10 0 0 0 0 1
pintype=pas
T 58555 41695 5 10 1 1 0 0 1
pinlabel=VSS
T 58405 41745 5 10 1 1 0 6 1
pinnumber=4
T 58100 41700 5 10 0 0 0 0 1
pinseq=4
}
P 60200 41700 59900 41700 1 0 0
{
T 60300 41700 5 10 0 0 0 6 1
pintype=pas
T 59845 41695 5 10 1 1 0 6 1
pinlabel=D
T 60095 41745 5 10 1 1 0 0 1
pinnumber=5
T 60300 41700 5 10 0 0 0 6 1
pinseq=5
}
T 54895 38100 8 10 0 1 0 0 1
device=23K256
T 59200 42600 9 10 1 0 0 0 1
M25P20
T 58395 42900 8 10 0 1 0 0 1
footprint=SOIC-127P-600L1-8N
T 58595 42600 8 10 0 1 0 0 1
refdes=U?
]
{
T 54895 38100 5 10 0 1 0 0 1
device=M25P20-VMN6
T 58395 42900 5 10 0 1 0 0 1
footprint=SOIC-127P-600L1-8N
T 58595 42600 5 10 1 1 0 0 1
refdes=U302
}
N 57800 42100 58200 42100 4
C 58000 41300 1 0 0 EMBEDDEDgnd-1.sym
[
T 58300 41350 8 10 0 0 0 0 1
net=GND:1
L 58080 41310 58120 41310 3 0 0 0 -1 -1
L 58055 41350 58145 41350 3 0 0 0 -1 -1
L 58000 41400 58200 41400 3 0 0 0 -1 -1
P 58100 41400 58100 41600 1 0 1
{
T 58158 41461 5 4 0 1 0 0 1
pinnumber=1
T 58158 41461 5 4 0 0 0 0 1
pinseq=1
T 58158 41461 5 4 0 1 0 0 1
pinlabel=1
T 58158 41461 5 4 0 1 0 0 1
pintype=pwr
}
]
N 58200 41700 58100 41700 4
N 58100 41700 58100 41600 4
C 60200 42700 1 0 0 EMBEDDED3.3V-plus-1.sym
[
T 60275 42950 9 8 1 0 0 0 1
+3.3V
T 60500 42700 8 8 0 0 0 0 1
net=+3.3V:1
P 60400 42700 60400 42900 1 0 0
{
T 60450 42750 5 6 0 1 0 0 1
pinnumber=1
T 60450 42750 5 6 0 0 0 0 1
pinseq=1
T 60450 42750 5 6 0 1 0 0 1
pinlabel=1
T 60450 42750 5 6 0 1 0 0 1
pintype=pwr
}
L 60250 42900 60550 42900 3 0 0 0 -1 -1
]
N 60200 42300 60400 42300 4
N 60400 42100 60400 42700 4
N 60200 42100 60400 42100 4
N 60200 41900 60900 41900 4
N 60900 41900 60900 45600 4
N 57900 45600 60900 45600 4
N 57900 45600 57900 46400 4
N 44100 44200 44100 41700 4
C 58100 43100 1 0 0 EMBEDDEDSN74AUP1T157.sym
[
B 58400 43300 1400 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 59800 43800 60100 43800 1 0 1
{
T 59950 43850 5 10 1 1 0 0 1
pinnumber=6
T 59950 43850 5 10 0 0 0 0 1
pinseq=6
T 59750 43750 5 10 1 1 0 6 1
pinlabel=Y
T 59950 43850 5 10 0 1 0 0 1
pintype=pas
}
P 58100 43800 58400 43800 1 0 0
{
T 58000 43800 5 10 0 0 0 0 1
pintype=pas
T 58455 43795 5 10 1 1 0 0 1
pinlabel=A
T 58305 43845 5 10 1 1 0 6 1
pinnumber=1
T 58000 43800 5 10 0 0 0 0 1
pinseq=1
}
P 58100 43600 58400 43600 1 0 0
{
T 58000 43600 5 10 0 0 0 0 1
pintype=pas
T 58455 43595 5 10 1 1 0 0 1
pinlabel=GND
T 58305 43645 5 10 1 1 0 6 1
pinnumber=2
T 58000 43600 5 10 0 0 0 0 1
pinseq=2
}
P 58100 43400 58400 43400 1 0 0
{
T 58000 43400 5 10 0 0 0 0 1
pintype=pas
T 58455 43395 5 10 1 1 0 0 1
pinlabel=B
T 58305 43445 5 10 1 1 0 6 1
pinnumber=3
T 58000 43400 5 10 0 0 0 0 1
pinseq=3
}
P 60100 43400 59800 43400 1 0 0
{
T 60200 43400 5 10 0 0 180 0 1
pintype=pas
T 59745 43395 5 10 1 1 0 6 1
pinlabel=C
T 59895 43445 5 10 1 1 0 0 1
pinnumber=4
T 60200 43400 5 10 0 0 180 0 1
pinseq=4
}
P 60100 43600 59800 43600 1 0 0
{
T 60200 43600 5 10 0 0 0 6 1
pintype=pas
T 59745 43595 5 10 1 1 0 6 1
pinlabel=VCC
T 59895 43645 5 10 1 1 0 0 1
pinnumber=5
T 60200 43600 5 10 0 0 0 6 1
pinseq=5
}
T 54795 39600 8 10 0 1 0 0 1
device=23K256
T 58400 43100 9 10 1 0 0 0 1
SN74AUP1T157
T 58295 44400 8 10 0 1 0 0 1
footprint=SOIC-127P-600L1-8N
T 58495 44100 8 10 0 1 0 0 1
refdes=U?
]
{
T 54795 39600 5 10 0 1 0 0 1
device=23K256
T 58295 44400 5 10 0 1 0 0 1
footprint=SOT363-65P-240L1-6N__On-Semi_419B-Package
T 58495 44100 5 10 1 1 0 0 1
refdes=U303
}
N 60100 43800 60300 43800 4
N 57600 42300 58200 42300 4
C 41800 40800 1 90 0 EMBEDDEDcapacitor-1.sym
[
L 41600 41200 41600 41000 3 0 0 0 -1 -1
L 41600 41500 41600 41300 3 0 0 0 -1 -1
L 41400 41300 41800 41300 3 0 0 0 -1 -1
L 41400 41200 41800 41200 3 0 0 0 -1 -1
P 41600 41700 41600 41500 1 0 0
{
T 41550 41550 5 8 0 1 90 0 1
pinnumber=2
T 41650 41550 5 8 0 1 90 2 1
pinseq=2
T 41600 41500 9 8 0 1 90 6 1
pinlabel=2
T 41600 41500 5 8 0 1 90 8 1
pintype=pas
}
P 41600 40800 41600 41000 1 0 0
{
T 41550 40950 5 8 0 1 90 6 1
pinnumber=1
T 41650 40950 5 8 0 1 90 8 1
pinseq=1
T 41600 41000 9 8 0 1 90 0 1
pinlabel=1
T 41600 41000 5 8 0 1 90 2 1
pintype=pas
}
T 40900 41000 5 10 0 0 90 0 1
symversion=0.1
T 40700 41000 5 10 0 0 90 0 1
numslots=0
T 40500 41000 5 10 0 0 90 0 1
description=capacitor
T 41300 41000 8 10 0 1 90 0 1
refdes=C?
T 41100 41000 5 10 0 0 90 0 1
device=CAPACITOR
]
{
T 41100 41000 5 10 0 0 90 0 1
device=CAPACITOR
T 41400 41400 5 10 1 1 180 0 1
refdes=C316
T 40900 41000 5 10 0 0 90 0 1
symversion=0.1
T 40900 41000 5 10 1 1 0 0 1
value=0.1uf
T 41800 40800 5 10 0 0 0 0 1
footprint=0603
}
N 40700 41700 44100 41700 4
N 41600 40800 40400 40800 4
C 60400 43600 1 0 0 EMBEDDED3.3V-plus-1.sym
[
L 60450 43800 60750 43800 3 0 0 0 -1 -1
P 60600 43600 60600 43800 1 0 0
{
T 60650 43650 5 6 0 1 0 0 1
pinnumber=1
T 60650 43650 5 6 0 0 0 0 1
pinseq=1
T 60650 43650 5 6 0 1 0 0 1
pinlabel=1
T 60650 43650 5 6 0 1 0 0 1
pintype=pwr
}
T 60700 43600 8 8 0 0 0 0 1
net=+3.3V:1
T 60475 43850 9 8 1 0 0 0 1
+3.3V
]
N 60100 43600 60600 43600 4
C 57900 43000 1 0 0 EMBEDDEDgnd-1.sym
[
P 58000 43100 58000 43300 1 0 1
{
T 58058 43161 5 4 0 1 0 0 1
pinnumber=1
T 58058 43161 5 4 0 0 0 0 1
pinseq=1
T 58058 43161 5 4 0 1 0 0 1
pinlabel=1
T 58058 43161 5 4 0 1 0 0 1
pintype=pwr
}
L 57900 43100 58100 43100 3 0 0 0 -1 -1
L 57955 43050 58045 43050 3 0 0 0 -1 -1
L 57980 43010 58020 43010 3 0 0 0 -1 -1
T 58200 43050 8 10 0 0 0 0 1
net=GND:1
]
N 58100 43600 58000 43600 4
N 58000 43600 58000 43300 4
C 43700 40400 1 0 0 EMBEDDEDSN74AUP1T157.sym
[
B 44000 40600 1400 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 45400 41100 45700 41100 1 0 1
{
T 45550 41150 5 10 1 1 0 0 1
pinnumber=6
T 45550 41150 5 10 0 0 0 0 1
pinseq=6
T 45350 41050 5 10 1 1 0 6 1
pinlabel=Y
T 45550 41150 5 10 0 1 0 0 1
pintype=pas
}
P 43700 41100 44000 41100 1 0 0
{
T 43600 41100 5 10 0 0 0 0 1
pintype=pas
T 44055 41095 5 10 1 1 0 0 1
pinlabel=A
T 43905 41145 5 10 1 1 0 6 1
pinnumber=1
T 43600 41100 5 10 0 0 0 0 1
pinseq=1
}
P 43700 40900 44000 40900 1 0 0
{
T 43600 40900 5 10 0 0 0 0 1
pintype=pas
T 44055 40895 5 10 1 1 0 0 1
pinlabel=GND
T 43905 40945 5 10 1 1 0 6 1
pinnumber=2
T 43600 40900 5 10 0 0 0 0 1
pinseq=2
}
P 43700 40700 44000 40700 1 0 0
{
T 43600 40700 5 10 0 0 0 0 1
pintype=pas
T 44055 40695 5 10 1 1 0 0 1
pinlabel=B
T 43905 40745 5 10 1 1 0 6 1
pinnumber=3
T 43600 40700 5 10 0 0 0 0 1
pinseq=3
}
P 45700 40700 45400 40700 1 0 0
{
T 45800 40700 5 10 0 0 180 0 1
pintype=pas
T 45345 40695 5 10 1 1 0 6 1
pinlabel=C
T 45495 40745 5 10 1 1 0 0 1
pinnumber=4
T 45800 40700 5 10 0 0 180 0 1
pinseq=4
}
P 45700 40900 45400 40900 1 0 0
{
T 45800 40900 5 10 0 0 0 6 1
pintype=pas
T 45345 40895 5 10 1 1 0 6 1
pinlabel=VCC
T 45495 40945 5 10 1 1 0 0 1
pinnumber=5
T 45800 40900 5 10 0 0 0 6 1
pinseq=5
}
T 40395 36900 8 10 0 1 0 0 1
device=23K256
T 44000 40400 9 10 1 0 0 0 1
SN74AUP1T157
T 43895 41700 8 10 0 1 0 0 1
footprint=SOIC-127P-600L1-8N
T 44095 41400 8 10 0 1 0 0 1
refdes=U?
]
{
T 40395 36900 5 10 0 1 0 0 1
device=23K256
T 43895 41700 5 10 0 1 0 0 1
footprint=SOT363-65P-240L1-6N__On-Semi_419B-Package
T 44095 41400 5 10 1 1 0 0 1
refdes=U304
}
C 45900 41200 1 0 0 EMBEDDED3.3V-plus-1.sym
[
P 46100 41200 46100 41400 1 0 0
{
T 46150 41250 5 6 0 1 0 0 1
pinnumber=1
T 46150 41250 5 6 0 0 0 0 1
pinseq=1
T 46150 41250 5 6 0 1 0 0 1
pinlabel=1
T 46150 41250 5 6 0 1 0 0 1
pintype=pwr
}
L 45950 41400 46250 41400 3 0 0 0 -1 -1
T 45975 41450 9 8 1 0 0 0 1
+3.3V
T 46200 41200 8 8 0 0 0 0 1
net=+3.3V:1
]
C 43400 40200 1 0 0 EMBEDDEDgnd-1.sym
[
T 43700 40250 8 10 0 0 0 0 1
net=GND:1
L 43480 40210 43520 40210 3 0 0 0 -1 -1
L 43455 40250 43545 40250 3 0 0 0 -1 -1
L 43400 40300 43600 40300 3 0 0 0 -1 -1
P 43500 40300 43500 40500 1 0 1
{
T 43558 40361 5 4 0 1 0 0 1
pinnumber=1
T 43558 40361 5 4 0 0 0 0 1
pinseq=1
T 43558 40361 5 4 0 1 0 0 1
pinlabel=1
T 43558 40361 5 4 0 1 0 0 1
pintype=pwr
}
]
N 43700 40900 43500 40900 4
N 43500 40500 43500 41100 4
N 45700 40900 46100 40900 4
N 46100 40300 46100 41200 4
N 43700 41100 43500 41100 4
N 43700 40700 43700 40300 4
N 43700 40300 46100 40300 4
T 46200 40500 9 10 1 0 0 0 2
U304 strapped as an inverter:
output low @ reset for SPI Flash cfg
T 58000 44400 9 10 1 0 0 0 2
U303 selects DIN source
- SPI Flash (1)  or OMAP (0)
N 48000 43800 48000 44400 4
N 51600 41200 51600 44400 4
C 57400 42700 1 0 1 EMBEDDEDoutput-1.sym
[
T 57300 43000 5 10 0 0 0 6 1
device=OUTPUT
P 57400 42800 57200 42800 1 0 0
{
T 57150 42750 5 6 0 0 0 6 1
pinseq=1
T 57150 42750 5 6 0 1 0 6 1
pinnumber=1
}
L 57200 42900 57200 42700 3 0 0 0 -1 -1
L 57200 42900 56700 42900 3 0 0 0 -1 -1
L 56700 42900 56600 42800 3 0 0 0 -1 -1
L 56600 42800 56700 42700 3 0 0 0 -1 -1
L 56700 42700 57200 42700 3 0 0 0 -1 -1
]
{
T 57300 43000 5 10 0 0 0 6 1
device=OUTPUT
T 57700 42500 5 10 1 1 0 6 1
value=OMAP_FLASH_DRV_N
T 57400 42700 5 10 0 1 180 6 1
net=OMAP_FLASH_DRV_N:1
}
N 45700 41100 45700 46400 4
N 48600 44400 48600 43800 4
N 48400 44400 48400 43800 4
N 48200 44400 48200 43800 4
N 51200 44400 51200 43800 4
N 52200 44400 52200 43500 4
N 52200 43500 52800 43500 4
N 55300 45500 56000 45500 4
C 57000 45200 1 0 0 EMBEDDEDgnd-1.sym
[
L 57080 45210 57120 45210 3 0 0 0 -1 -1
L 57055 45250 57145 45250 3 0 0 0 -1 -1
L 57000 45300 57200 45300 3 0 0 0 -1 -1
P 57100 45300 57100 45500 1 0 1
{
T 57158 45361 5 4 0 1 0 0 1
pinnumber=1
T 57158 45361 5 4 0 0 0 0 1
pinseq=1
T 57158 45361 5 4 0 1 0 0 1
pinlabel=1
T 57158 45361 5 4 0 1 0 0 1
pintype=pwr
}
T 57300 45250 8 10 0 0 0 0 1
net=GND:1
]
N 56900 45500 57100 45500 4
C 54100 45400 1 0 0 EMBEDDEDgnd-1.sym
[
T 54400 45450 8 10 0 0 0 0 1
net=GND:1
L 54180 45410 54220 45410 3 0 0 0 -1 -1
L 54155 45450 54245 45450 3 0 0 0 -1 -1
L 54100 45500 54300 45500 3 0 0 0 -1 -1
P 54200 45500 54200 45700 1 0 1
{
T 54258 45561 5 4 0 1 0 0 1
pinnumber=1
T 54258 45561 5 4 0 0 0 0 1
pinseq=1
T 54258 45561 5 4 0 1 0 0 1
pinlabel=1
T 54258 45561 5 4 0 1 0 0 1
pintype=pwr
}
]
C 47400 43700 1 0 0 EMBEDDEDgnd-1.sym
[
T 47700 43750 8 10 0 0 0 0 1
net=GND:1
L 47480 43710 47520 43710 3 0 0 0 -1 -1
L 47455 43750 47545 43750 3 0 0 0 -1 -1
L 47400 43800 47600 43800 3 0 0 0 -1 -1
P 47500 43800 47500 44000 1 0 1
{
T 47558 43861 5 4 0 1 0 0 1
pinnumber=1
T 47558 43861 5 4 0 0 0 0 1
pinseq=1
T 47558 43861 5 4 0 1 0 0 1
pinlabel=1
T 47558 43861 5 4 0 1 0 0 1
pintype=pwr
}
]
N 50200 44400 50200 41100 4
C 44900 40100 1 180 0 EMBEDDEDoutput-1.sym
[
P 44900 40000 44700 40000 1 0 0
{
T 44650 40050 5 6 0 1 180 0 1
pinnumber=1
T 44650 40050 5 6 0 0 180 0 1
pinseq=1
}
L 44700 39900 44700 40100 3 0 0 0 -1 -1
L 44700 39900 44200 39900 3 0 0 0 -1 -1
L 44200 39900 44100 40000 3 0 0 0 -1 -1
L 44100 40000 44200 40100 3 0 0 0 -1 -1
L 44200 40100 44700 40100 3 0 0 0 -1 -1
T 44800 39800 5 10 0 0 180 0 1
device=OUTPUT
]
{
T 44800 39800 5 10 0 0 180 0 1
device=OUTPUT
T 42500 39900 5 10 1 1 0 0 1
value=FPGA_SPI_MODE
T 44900 40100 5 10 0 0 0 0 1
net=FPGA_SPI_MODE:1
}
N 45700 40000 45700 40700 4
N 55500 43400 58100 43400 4
N 57800 42100 57800 43800 4
N 57800 43800 58100 43800 4
N 60300 43800 60300 46000 4
N 57400 42800 60100 42800 4
N 60100 42800 60100 43400 4
N 60200 41700 60400 41700 4
N 60400 41700 60400 41200 4
N 60400 41200 51600 41200 4
N 47800 41700 57600 41700 4
N 57600 41700 57600 42300 4
N 55500 43400 55500 49400 4
N 54000 49200 54800 49200 4
N 54000 49400 58200 49400 4
N 44900 40000 45700 40000 4
N 58200 41900 58000 41900 4
N 58000 41900 58000 42600 4
N 58000 42600 60400 42600 4
N 45000 46800 45900 46800 4
C 41400 48900 1 0 0 EMBEDDED3.3V-plus-1.sym
[
T 41475 49150 9 8 1 0 0 0 1
+3.3V
T 41700 48900 8 8 0 0 0 0 1
net=+3.3V:1
P 41600 48900 41600 49100 1 0 0
{
T 41650 48950 5 6 0 1 0 0 1
pinnumber=1
T 41650 48950 5 6 0 0 0 0 1
pinseq=1
T 41650 48950 5 6 0 1 0 0 1
pinlabel=1
T 41650 48950 5 6 0 1 0 0 1
pintype=pwr
}
L 41450 49100 41750 49100 3 0 0 0 -1 -1
]
C 51300 43800 1 90 1 EMBEDDEDoutput-1.sym
[
P 51200 43800 51200 43600 1 0 0
{
T 51250 43550 5 6 0 0 90 6 1
pinseq=1
T 51250 43550 5 6 0 1 90 6 1
pinnumber=1
}
L 51100 43600 51300 43600 3 0 0 0 -1 -1
L 51100 43600 51100 43100 3 0 0 0 -1 -1
L 51100 43100 51200 43000 3 0 0 0 -1 -1
L 51200 43000 51300 43100 3 0 0 0 -1 -1
L 51300 43100 51300 43600 3 0 0 0 -1 -1
T 51000 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 51000 43700 5 10 0 0 90 6 1
device=OUTPUT
T 51300 42900 5 10 1 1 90 6 1
value=CLKOUT2
T 51300 43800 5 10 0 1 270 6 1
net=CLKOUT2:1
}
C 50200 41000 1 0 1 EMBEDDEDoutput-1.sym
[
P 50200 41100 50000 41100 1 0 0
{
T 49950 41050 5 6 0 0 0 6 1
pinseq=1
T 49950 41050 5 6 0 1 0 6 1
pinnumber=1
}
L 50000 41200 50000 41000 3 0 0 0 -1 -1
L 50000 41200 49500 41200 3 0 0 0 -1 -1
L 49500 41200 49400 41100 3 0 0 0 -1 -1
L 49400 41100 49500 41000 3 0 0 0 -1 -1
L 49500 41000 50000 41000 3 0 0 0 -1 -1
T 50100 41300 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 50100 41300 5 10 0 0 0 6 1
device=OUTPUT
T 49300 41000 5 10 1 1 0 6 1
value=SPI0_CS0
T 50200 41000 5 10 0 1 180 6 1
net=SPI0_CS0:1
}
C 58200 46300 1 0 0 EMBEDDEDoutput-1.sym
[
P 58200 46400 58400 46400 1 0 0
{
T 58450 46350 5 6 0 0 0 0 1
pinseq=1
T 58450 46350 5 6 0 1 0 0 1
pinnumber=1
}
L 58400 46500 58400 46300 3 0 0 0 -1 -1
L 58400 46500 58900 46500 3 0 0 0 -1 -1
L 58900 46500 59000 46400 3 0 0 0 -1 -1
L 59000 46400 58900 46300 3 0 0 0 -1 -1
L 58900 46300 58400 46300 3 0 0 0 -1 -1
T 58300 46600 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 58300 46600 5 10 0 0 0 0 1
device=OUTPUT
T 59100 46300 5 10 1 1 0 0 1
value=SPI0_SCLK
T 58200 46300 5 10 0 1 180 0 1
net=SPI0_SCLK:1
}
C 52800 43600 1 0 0 EMBEDDEDoutput-1.sym
[
P 52800 43700 53000 43700 1 0 0
{
T 53050 43650 5 6 0 0 0 0 1
pinseq=1
T 53050 43650 5 6 0 1 0 0 1
pinnumber=1
}
L 53000 43800 53000 43600 3 0 0 0 -1 -1
L 53000 43800 53500 43800 3 0 0 0 -1 -1
L 53500 43800 53600 43700 3 0 0 0 -1 -1
L 53600 43700 53500 43600 3 0 0 0 -1 -1
L 53500 43600 53000 43600 3 0 0 0 -1 -1
T 52900 43900 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 52900 43900 5 10 0 0 0 0 1
device=OUTPUT
T 53700 43600 5 10 1 1 0 0 1
value=LED0
T 52800 43600 5 10 0 1 180 0 1
net=LED0:1
}
C 52800 43400 1 0 0 EMBEDDEDoutput-1.sym
[
L 53500 43400 53000 43400 3 0 0 0 -1 -1
L 53600 43500 53500 43400 3 0 0 0 -1 -1
L 53500 43600 53600 43500 3 0 0 0 -1 -1
L 53000 43600 53500 43600 3 0 0 0 -1 -1
L 53000 43600 53000 43400 3 0 0 0 -1 -1
P 52800 43500 53000 43500 1 0 0
{
T 53050 43450 5 6 0 1 0 0 1
pinnumber=1
T 53050 43450 5 6 0 0 0 0 1
pinseq=1
}
T 52900 43700 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 52900 43700 5 10 0 0 0 0 1
device=OUTPUT
T 53700 43400 5 10 1 1 0 0 1
value=LED1
T 52800 43400 5 10 0 1 180 0 1
net=LED1:1
}
N 41600 48900 41600 48800 4
C 45000 48500 1 0 1 EMBEDDEDoutput-1.sym
[
T 44900 48800 5 10 0 0 0 6 1
device=OUTPUT
L 44300 48500 44800 48500 3 0 0 0 -1 -1
L 44200 48600 44300 48500 3 0 0 0 -1 -1
L 44300 48700 44200 48600 3 0 0 0 -1 -1
L 44800 48700 44300 48700 3 0 0 0 -1 -1
L 44800 48700 44800 48500 3 0 0 0 -1 -1
P 45000 48600 44800 48600 1 0 0
{
T 44750 48550 5 6 0 1 0 6 1
pinnumber=1
T 44750 48550 5 6 0 0 0 6 1
pinseq=1
}
]
{
T 44900 48800 5 10 0 0 0 6 1
device=OUTPUT
T 44100 48500 5 10 1 1 0 6 1
value=GPMC_CSN2
T 45000 48500 5 10 0 1 180 6 1
net=GPMC_CSN2:1
}
C 45000 49100 1 0 1 EMBEDDEDoutput-1.sym
[
T 44900 49400 5 10 0 0 0 6 1
device=OUTPUT
L 44300 49100 44800 49100 3 0 0 0 -1 -1
L 44200 49200 44300 49100 3 0 0 0 -1 -1
L 44300 49300 44200 49200 3 0 0 0 -1 -1
L 44800 49300 44300 49300 3 0 0 0 -1 -1
L 44800 49300 44800 49100 3 0 0 0 -1 -1
P 45000 49200 44800 49200 1 0 0
{
T 44750 49150 5 6 0 1 0 6 1
pinnumber=1
T 44750 49150 5 6 0 0 0 6 1
pinseq=1
}
]
{
T 44900 49400 5 10 0 0 0 6 1
device=OUTPUT
T 44100 49100 5 10 1 1 0 6 1
value=GPMC_AD5
T 45000 49100 5 10 0 1 180 6 1
net=GPMC_AD5:1
}
C 45000 49900 1 0 1 EMBEDDEDoutput-1.sym
[
T 44900 50200 5 10 0 0 0 6 1
device=OUTPUT
L 44300 49900 44800 49900 3 0 0 0 -1 -1
L 44200 50000 44300 49900 3 0 0 0 -1 -1
L 44300 50100 44200 50000 3 0 0 0 -1 -1
L 44800 50100 44300 50100 3 0 0 0 -1 -1
L 44800 50100 44800 49900 3 0 0 0 -1 -1
P 45000 50000 44800 50000 1 0 0
{
T 44750 49950 5 6 0 1 0 6 1
pinnumber=1
T 44750 49950 5 6 0 0 0 6 1
pinseq=1
}
]
{
T 44900 50200 5 10 0 0 0 6 1
device=OUTPUT
T 44100 49900 5 10 1 1 0 6 1
value=GPMC_AD1
T 45000 49900 5 10 0 1 180 6 1
net=GPMC_AD1:1
}
C 45000 50300 1 0 1 EMBEDDEDoutput-1.sym
[
T 44900 50600 5 10 0 0 0 6 1
device=OUTPUT
L 44300 50300 44800 50300 3 0 0 0 -1 -1
L 44200 50400 44300 50300 3 0 0 0 -1 -1
L 44300 50500 44200 50400 3 0 0 0 -1 -1
L 44800 50500 44300 50500 3 0 0 0 -1 -1
L 44800 50500 44800 50300 3 0 0 0 -1 -1
P 45000 50400 44800 50400 1 0 0
{
T 44750 50350 5 6 0 1 0 6 1
pinnumber=1
T 44750 50350 5 6 0 0 0 6 1
pinseq=1
}
]
{
T 44900 50600 5 10 0 0 0 6 1
device=OUTPUT
T 44100 50300 5 10 1 1 0 6 1
value=GPMC_CSN0
T 45000 50300 5 10 0 1 180 6 1
net=GPMC_CSN0:1
}
C 45000 48300 1 0 1 EMBEDDEDoutput-1.sym
[
T 44900 48600 5 10 0 0 0 6 1
device=OUTPUT
L 44300 48300 44800 48300 3 0 0 0 -1 -1
L 44200 48400 44300 48300 3 0 0 0 -1 -1
L 44300 48500 44200 48400 3 0 0 0 -1 -1
L 44800 48500 44300 48500 3 0 0 0 -1 -1
L 44800 48500 44800 48300 3 0 0 0 -1 -1
P 45000 48400 44800 48400 1 0 0
{
T 44750 48350 5 6 0 0 0 6 1
pinseq=1
T 44750 48350 5 6 0 1 0 6 1
pinnumber=1
}
]
{
T 44900 48600 5 10 0 0 0 6 1
device=OUTPUT
T 44100 48300 5 10 1 1 0 6 1
value=GPMC_AD8
T 45000 48300 5 10 0 1 180 6 1
net=GPMC_AD8:1
}
C 45000 48900 1 0 1 EMBEDDEDoutput-1.sym
[
T 44900 49200 5 10 0 0 0 6 1
device=OUTPUT
P 45000 49000 44800 49000 1 0 0
{
T 44750 48950 5 6 0 1 0 6 1
pinnumber=1
T 44750 48950 5 6 0 0 0 6 1
pinseq=1
}
L 44800 49100 44800 48900 3 0 0 0 -1 -1
L 44800 49100 44300 49100 3 0 0 0 -1 -1
L 44300 49100 44200 49000 3 0 0 0 -1 -1
L 44200 49000 44300 48900 3 0 0 0 -1 -1
L 44300 48900 44800 48900 3 0 0 0 -1 -1
]
{
T 44900 49200 5 10 0 0 0 6 1
device=OUTPUT
T 44100 48900 5 10 1 1 0 6 1
value=GPMC_CSN1
T 45000 48900 5 10 0 1 180 6 1
net=GPMC_CSN1:1
}
C 45000 49700 1 0 1 EMBEDDEDoutput-1.sym
[
T 44900 50000 5 10 0 0 0 6 1
device=OUTPUT
P 45000 49800 44800 49800 1 0 0
{
T 44750 49750 5 6 0 1 0 6 1
pinnumber=1
T 44750 49750 5 6 0 0 0 6 1
pinseq=1
}
L 44800 49900 44800 49700 3 0 0 0 -1 -1
L 44800 49900 44300 49900 3 0 0 0 -1 -1
L 44300 49900 44200 49800 3 0 0 0 -1 -1
L 44200 49800 44300 49700 3 0 0 0 -1 -1
L 44300 49700 44800 49700 3 0 0 0 -1 -1
]
{
T 44900 50000 5 10 0 0 0 6 1
device=OUTPUT
T 44100 49700 5 10 1 1 0 6 1
value=GPMC_AD4
T 45000 49700 5 10 0 1 180 6 1
net=GPMC_AD4:1
}
C 45000 50100 1 0 1 EMBEDDEDoutput-1.sym
[
T 44900 50400 5 10 0 0 0 6 1
device=OUTPUT
P 45000 50200 44800 50200 1 0 0
{
T 44750 50150 5 6 0 1 0 6 1
pinnumber=1
T 44750 50150 5 6 0 0 0 6 1
pinseq=1
}
L 44800 50300 44800 50100 3 0 0 0 -1 -1
L 44800 50300 44300 50300 3 0 0 0 -1 -1
L 44300 50300 44200 50200 3 0 0 0 -1 -1
L 44200 50200 44300 50100 3 0 0 0 -1 -1
L 44300 50100 44800 50100 3 0 0 0 -1 -1
]
{
T 44900 50400 5 10 0 0 0 6 1
device=OUTPUT
T 44100 50100 5 10 1 1 0 6 1
value=GPMC_AD0
T 45000 50100 5 10 0 1 180 6 1
net=GPMC_AD0:1
}
C 45000 49500 1 0 1 EMBEDDEDoutput-1.sym
[
P 45000 49600 44800 49600 1 0 0
{
T 44750 49550 5 6 0 0 0 6 1
pinseq=1
T 44750 49550 5 6 0 1 0 6 1
pinnumber=1
}
L 44800 49700 44800 49500 3 0 0 0 -1 -1
L 44800 49700 44300 49700 3 0 0 0 -1 -1
L 44300 49700 44200 49600 3 0 0 0 -1 -1
L 44200 49600 44300 49500 3 0 0 0 -1 -1
L 44300 49500 44800 49500 3 0 0 0 -1 -1
T 44900 49800 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 44900 49800 5 10 0 0 0 6 1
device=OUTPUT
T 44100 49500 5 10 1 1 0 6 1
value=BTN1
T 45000 49500 5 10 0 1 180 6 1
net=BTN1:1
}
N 45000 49600 45900 49600 4
C 50100 43800 1 90 1 EMBEDDEDoutput-1.sym
[
P 50000 43800 50000 43600 1 0 0
{
T 50050 43550 5 6 0 1 90 6 1
pinnumber=1
T 50050 43550 5 6 0 0 90 6 1
pinseq=1
}
L 49900 43600 50100 43600 3 0 0 0 -1 -1
L 49900 43600 49900 43100 3 0 0 0 -1 -1
L 49900 43100 50000 43000 3 0 0 0 -1 -1
L 50000 43000 50100 43100 3 0 0 0 -1 -1
L 50100 43100 50100 43600 3 0 0 0 -1 -1
T 49800 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 49800 43700 5 10 0 0 90 6 1
device=OUTPUT
T 50100 42900 5 10 1 1 90 6 1
value=VCCINT
T 50100 43800 5 10 0 1 270 6 1
net=VCCINT:1
}
C 45000 46700 1 0 1 EMBEDDEDoutput-1.sym
[
P 45000 46800 44800 46800 1 0 0
{
T 44750 46750 5 6 0 1 0 6 1
pinnumber=1
T 44750 46750 5 6 0 0 0 6 1
pinseq=1
}
L 44800 46900 44800 46700 3 0 0 0 -1 -1
L 44800 46900 44300 46900 3 0 0 0 -1 -1
L 44300 46900 44200 46800 3 0 0 0 -1 -1
L 44200 46800 44300 46700 3 0 0 0 -1 -1
L 44300 46700 44800 46700 3 0 0 0 -1 -1
T 44900 47000 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 44900 47000 5 10 0 0 0 6 1
device=OUTPUT
T 44100 46700 5 10 1 1 0 6 1
value=BTN0
T 45000 46700 5 10 0 1 180 6 1
net=BTN0:1
}
C 56700 46900 1 0 0 EMBEDDEDoutput-1.sym
[
T 56800 47200 5 10 0 0 0 0 1
device=OUTPUT
P 56700 47000 56900 47000 1 0 0
{
T 56950 46950 5 6 0 0 0 0 1
pinseq=1
T 56950 46950 5 6 0 1 0 0 1
pinnumber=1
}
L 56900 47100 56900 46900 3 0 0 0 -1 -1
L 56900 47100 57400 47100 3 0 0 0 -1 -1
L 57400 47100 57500 47000 3 0 0 0 -1 -1
L 57500 47000 57400 46900 3 0 0 0 -1 -1
L 57400 46900 56900 46900 3 0 0 0 -1 -1
]
{
T 56800 47200 5 10 0 0 0 0 1
device=OUTPUT
T 57600 46900 5 10 1 1 0 0 1
value=GPMC_BE1N
T 56700 46900 5 10 0 1 180 0 1
net=GPMC_BE1N:1
}
C 50700 43800 1 90 1 EMBEDDEDoutput-1.sym
[
L 50700 43100 50700 43600 3 0 0 0 -1 -1
L 50600 43000 50700 43100 3 0 0 0 -1 -1
L 50500 43100 50600 43000 3 0 0 0 -1 -1
L 50500 43600 50500 43100 3 0 0 0 -1 -1
L 50500 43600 50700 43600 3 0 0 0 -1 -1
P 50600 43800 50600 43600 1 0 0
{
T 50650 43550 5 6 0 1 90 6 1
pinnumber=1
T 50650 43550 5 6 0 0 90 6 1
pinseq=1
}
T 50400 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 50400 43700 5 10 0 0 90 6 1
device=OUTPUT
T 50700 42900 5 10 1 1 90 6 1
value=GPMC_CLK
T 50700 43800 5 10 0 1 270 6 1
net=GPMC_CLK:1
}
C 45000 47900 1 0 1 EMBEDDEDoutput-1.sym
[
L 44300 47900 44800 47900 3 0 0 0 -1 -1
L 44200 48000 44300 47900 3 0 0 0 -1 -1
L 44300 48100 44200 48000 3 0 0 0 -1 -1
L 44800 48100 44300 48100 3 0 0 0 -1 -1
L 44800 48100 44800 47900 3 0 0 0 -1 -1
P 45000 48000 44800 48000 1 0 0
{
T 44750 47950 5 6 0 0 0 6 1
pinseq=1
T 44750 47950 5 6 0 1 0 6 1
pinnumber=1
}
T 44900 48200 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 44900 48200 5 10 0 0 0 6 1
device=OUTPUT
T 44100 47900 5 10 1 1 0 6 1
value=GPMC_AD11
T 45000 47900 5 10 0 1 180 6 1
net=GPMC_AD11:1
}
C 45000 47700 1 0 1 EMBEDDEDoutput-1.sym
[
L 44300 47700 44800 47700 3 0 0 0 -1 -1
L 44200 47800 44300 47700 3 0 0 0 -1 -1
L 44300 47900 44200 47800 3 0 0 0 -1 -1
L 44800 47900 44300 47900 3 0 0 0 -1 -1
L 44800 47900 44800 47700 3 0 0 0 -1 -1
P 45000 47800 44800 47800 1 0 0
{
T 44750 47750 5 6 0 1 0 6 1
pinnumber=1
T 44750 47750 5 6 0 0 0 6 1
pinseq=1
}
T 44900 48000 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 44900 48000 5 10 0 0 0 6 1
device=OUTPUT
T 44100 47700 5 10 1 1 0 6 1
value=GPMC_AD14
T 45000 47700 5 10 0 1 180 6 1
net=GPMC_AD14:1
}
C 45000 47100 1 0 1 EMBEDDEDoutput-1.sym
[
P 45000 47200 44800 47200 1 0 0
{
T 44750 47150 5 6 0 1 0 6 1
pinnumber=1
T 44750 47150 5 6 0 0 0 6 1
pinseq=1
}
L 44800 47300 44800 47100 3 0 0 0 -1 -1
L 44800 47300 44300 47300 3 0 0 0 -1 -1
L 44300 47300 44200 47200 3 0 0 0 -1 -1
L 44200 47200 44300 47100 3 0 0 0 -1 -1
L 44300 47100 44800 47100 3 0 0 0 -1 -1
T 44900 47400 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 44900 47400 5 10 0 0 0 6 1
device=OUTPUT
T 44100 47100 5 10 1 1 0 6 1
value=GPMC_AD15
T 45000 47100 5 10 0 1 180 6 1
net=GPMC_AD15:1
}
C 45000 46900 1 0 1 EMBEDDEDoutput-1.sym
[
L 44300 46900 44800 46900 3 0 0 0 -1 -1
L 44200 47000 44300 46900 3 0 0 0 -1 -1
L 44300 47100 44200 47000 3 0 0 0 -1 -1
L 44800 47100 44300 47100 3 0 0 0 -1 -1
L 44800 47100 44800 46900 3 0 0 0 -1 -1
P 45000 47000 44800 47000 1 0 0
{
T 44750 46950 5 6 0 0 0 6 1
pinseq=1
T 44750 46950 5 6 0 1 0 6 1
pinnumber=1
}
T 44900 47200 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 44900 47200 5 10 0 0 0 6 1
device=OUTPUT
T 44100 46900 5 10 1 1 0 6 1
value=GPMC_AD10
T 45000 46900 5 10 0 1 180 6 1
net=GPMC_AD10:1
}
C 49500 43800 1 90 1 EMBEDDEDoutput-1.sym
[
P 49400 43800 49400 43600 1 0 0
{
T 49450 43550 5 6 0 1 90 6 1
pinnumber=1
T 49450 43550 5 6 0 0 90 6 1
pinseq=1
}
L 49300 43600 49500 43600 3 0 0 0 -1 -1
L 49300 43600 49300 43100 3 0 0 0 -1 -1
L 49300 43100 49400 43000 3 0 0 0 -1 -1
L 49400 43000 49500 43100 3 0 0 0 -1 -1
L 49500 43100 49500 43600 3 0 0 0 -1 -1
T 49200 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 49200 43700 5 10 0 0 90 6 1
device=OUTPUT
T 49500 42900 5 10 1 1 90 6 1
value=GPMC_AD3
T 49500 43800 5 10 0 1 270 6 1
net=GPMC_AD3:1
}
C 49700 43800 1 90 1 EMBEDDEDoutput-1.sym
[
L 49700 43100 49700 43600 3 0 0 0 -1 -1
L 49600 43000 49700 43100 3 0 0 0 -1 -1
L 49500 43100 49600 43000 3 0 0 0 -1 -1
L 49500 43600 49500 43100 3 0 0 0 -1 -1
L 49500 43600 49700 43600 3 0 0 0 -1 -1
P 49600 43800 49600 43600 1 0 0
{
T 49650 43550 5 6 0 1 90 6 1
pinnumber=1
T 49650 43550 5 6 0 0 90 6 1
pinseq=1
}
T 49400 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 49400 43700 5 10 0 0 90 6 1
device=OUTPUT
T 49700 42900 5 10 1 1 90 6 1
value=GPMC_AD2
T 49700 43800 5 10 0 1 270 6 1
net=GPMC_AD2:1
}
C 49100 43800 1 90 1 EMBEDDEDoutput-1.sym
[
L 49100 43100 49100 43600 3 0 0 0 -1 -1
L 49000 43000 49100 43100 3 0 0 0 -1 -1
L 48900 43100 49000 43000 3 0 0 0 -1 -1
L 48900 43600 48900 43100 3 0 0 0 -1 -1
L 48900 43600 49100 43600 3 0 0 0 -1 -1
P 49000 43800 49000 43600 1 0 0
{
T 49050 43550 5 6 0 0 90 6 1
pinseq=1
T 49050 43550 5 6 0 1 90 6 1
pinnumber=1
}
T 48800 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 48800 43700 5 10 0 0 90 6 1
device=OUTPUT
T 49100 42900 5 10 1 1 90 6 1
value=GPMC_OEN
T 49100 43800 5 10 0 1 270 6 1
net=GPMC_OEN:1
}
C 48700 43800 1 90 1 EMBEDDEDoutput-1.sym
[
L 48700 43100 48700 43600 3 0 0 0 -1 -1
L 48600 43000 48700 43100 3 0 0 0 -1 -1
L 48500 43100 48600 43000 3 0 0 0 -1 -1
L 48500 43600 48500 43100 3 0 0 0 -1 -1
L 48500 43600 48700 43600 3 0 0 0 -1 -1
P 48600 43800 48600 43600 1 0 0
{
T 48650 43550 5 6 0 0 90 6 1
pinseq=1
T 48650 43550 5 6 0 1 90 6 1
pinnumber=1
}
T 48400 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 48400 43700 5 10 0 0 90 6 1
device=OUTPUT
T 48700 42900 5 10 1 1 90 6 1
value=GPMC_WEN
T 48700 43800 5 10 0 1 270 6 1
net=GPMC_WEN:1
}
C 49300 43800 1 90 1 EMBEDDEDoutput-1.sym
[
P 49200 43800 49200 43600 1 0 0
{
T 49250 43550 5 6 0 0 90 6 1
pinseq=1
T 49250 43550 5 6 0 1 90 6 1
pinnumber=1
}
L 49100 43600 49300 43600 3 0 0 0 -1 -1
L 49100 43600 49100 43100 3 0 0 0 -1 -1
L 49100 43100 49200 43000 3 0 0 0 -1 -1
L 49200 43000 49300 43100 3 0 0 0 -1 -1
L 49300 43100 49300 43600 3 0 0 0 -1 -1
T 49000 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 49000 43700 5 10 0 0 90 6 1
device=OUTPUT
T 49300 42900 5 10 1 1 90 6 1
value=GPMC_ADVN_ALE
T 49300 43800 5 10 0 1 270 6 1
net=GPMC_ADVN_ALE:1
}
C 48900 43800 1 90 1 EMBEDDEDoutput-1.sym
[
P 48800 43800 48800 43600 1 0 0
{
T 48850 43550 5 6 0 0 90 6 1
pinseq=1
T 48850 43550 5 6 0 1 90 6 1
pinnumber=1
}
L 48700 43600 48900 43600 3 0 0 0 -1 -1
L 48700 43600 48700 43100 3 0 0 0 -1 -1
L 48700 43100 48800 43000 3 0 0 0 -1 -1
L 48800 43000 48900 43100 3 0 0 0 -1 -1
L 48900 43100 48900 43600 3 0 0 0 -1 -1
T 48600 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 48600 43700 5 10 0 0 90 6 1
device=OUTPUT
T 48900 42900 5 10 1 1 90 6 1
value=GPMC_BE0N_CLE
T 48900 43800 5 10 0 1 270 6 1
net=GPMC_BE0N_CLE:1
}
C 48300 43800 1 90 1 EMBEDDEDoutput-1.sym
[
L 48300 43100 48300 43600 3 0 0 0 -1 -1
L 48200 43000 48300 43100 3 0 0 0 -1 -1
L 48100 43100 48200 43000 3 0 0 0 -1 -1
L 48100 43600 48100 43100 3 0 0 0 -1 -1
L 48100 43600 48300 43600 3 0 0 0 -1 -1
P 48200 43800 48200 43600 1 0 0
{
T 48250 43550 5 6 0 0 90 6 1
pinseq=1
T 48250 43550 5 6 0 1 90 6 1
pinnumber=1
}
T 48000 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 48000 43700 5 10 0 0 90 6 1
device=OUTPUT
T 48300 42900 5 10 1 1 90 6 1
value=GPMC_AD12
T 48300 43800 5 10 0 1 270 6 1
net=GPMC_AD12:1
}
C 48500 43800 1 90 1 EMBEDDEDoutput-1.sym
[
L 48500 43100 48500 43600 3 0 0 0 -1 -1
L 48400 43000 48500 43100 3 0 0 0 -1 -1
L 48300 43100 48400 43000 3 0 0 0 -1 -1
L 48300 43600 48300 43100 3 0 0 0 -1 -1
L 48300 43600 48500 43600 3 0 0 0 -1 -1
P 48400 43800 48400 43600 1 0 0
{
T 48450 43550 5 6 0 1 90 6 1
pinnumber=1
T 48450 43550 5 6 0 0 90 6 1
pinseq=1
}
T 48200 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 48200 43700 5 10 0 0 90 6 1
device=OUTPUT
T 48500 42900 5 10 1 1 90 6 1
value=GPMC_AD13
T 48500 43800 5 10 0 1 270 6 1
net=GPMC_AD13:1
}
C 48100 43800 1 90 1 EMBEDDEDoutput-1.sym
[
L 48100 43100 48100 43600 3 0 0 0 -1 -1
L 48000 43000 48100 43100 3 0 0 0 -1 -1
L 47900 43100 48000 43000 3 0 0 0 -1 -1
L 47900 43600 47900 43100 3 0 0 0 -1 -1
L 47900 43600 48100 43600 3 0 0 0 -1 -1
P 48000 43800 48000 43600 1 0 0
{
T 48050 43550 5 6 0 1 90 6 1
pinnumber=1
T 48050 43550 5 6 0 0 90 6 1
pinseq=1
}
T 47800 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 47800 43700 5 10 0 0 90 6 1
device=OUTPUT
T 48100 42900 5 10 1 1 90 6 1
value=GPMC_AD9
T 48100 43800 5 10 0 1 270 6 1
net=GPMC_AD9:1
}
C 49900 43800 1 90 1 EMBEDDEDoutput-1.sym
[
L 49900 43100 49900 43600 3 0 0 0 -1 -1
L 49800 43000 49900 43100 3 0 0 0 -1 -1
L 49700 43100 49800 43000 3 0 0 0 -1 -1
L 49700 43600 49700 43100 3 0 0 0 -1 -1
L 49700 43600 49900 43600 3 0 0 0 -1 -1
P 49800 43800 49800 43600 1 0 0
{
T 49850 43550 5 6 0 1 90 6 1
pinnumber=1
T 49850 43550 5 6 0 0 90 6 1
pinseq=1
}
T 49600 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 49600 43700 5 10 0 0 90 6 1
device=OUTPUT
T 49900 42900 5 10 1 1 90 6 1
value=GPMC_AD7
T 49900 43800 5 10 0 1 270 6 1
net=GPMC_AD7:1
}
C 50500 43800 1 90 1 EMBEDDEDoutput-1.sym
[
L 50500 43100 50500 43600 3 0 0 0 -1 -1
L 50400 43000 50500 43100 3 0 0 0 -1 -1
L 50300 43100 50400 43000 3 0 0 0 -1 -1
L 50300 43600 50300 43100 3 0 0 0 -1 -1
L 50300 43600 50500 43600 3 0 0 0 -1 -1
P 50400 43800 50400 43600 1 0 0
{
T 50450 43550 5 6 0 0 90 6 1
pinseq=1
T 50450 43550 5 6 0 1 90 6 1
pinnumber=1
}
T 50200 43700 5 10 0 0 90 6 1
device=OUTPUT
]
{
T 50200 43700 5 10 0 0 90 6 1
device=OUTPUT
T 50500 42900 5 10 1 1 90 6 1
value=GPMC_AD6
T 50500 43800 5 10 0 1 270 6 1
net=GPMC_AD6:1
}
C 58200 46100 1 0 0 EMBEDDEDoutput-1.sym
[
T 58300 46400 5 10 0 0 0 0 1
device=OUTPUT
P 58200 46200 58400 46200 1 0 0
{
T 58450 46150 5 6 0 1 0 0 1
pinnumber=1
T 58450 46150 5 6 0 0 0 0 1
pinseq=1
}
L 58400 46300 58400 46100 3 0 0 0 -1 -1
L 58400 46300 58900 46300 3 0 0 0 -1 -1
L 58900 46300 59000 46200 3 0 0 0 -1 -1
L 59000 46200 58900 46100 3 0 0 0 -1 -1
L 58900 46100 58400 46100 3 0 0 0 -1 -1
]
{
T 58300 46400 5 10 0 0 0 0 1
device=OUTPUT
T 59100 46100 5 10 1 1 0 0 1
value=SPI0_D0
T 58200 46100 5 10 0 1 180 0 1
net=SPI0_D0:1
}
C 58200 49300 1 0 0 EMBEDDEDoutput-1.sym
[
T 58300 49600 5 10 0 0 0 0 1
device=OUTPUT
P 58200 49400 58400 49400 1 0 0
{
T 58450 49350 5 6 0 1 0 0 1
pinnumber=1
T 58450 49350 5 6 0 0 0 0 1
pinseq=1
}
L 58400 49500 58400 49300 3 0 0 0 -1 -1
L 58400 49500 58900 49500 3 0 0 0 -1 -1
L 58900 49500 59000 49400 3 0 0 0 -1 -1
L 59000 49400 58900 49300 3 0 0 0 -1 -1
L 58900 49300 58400 49300 3 0 0 0 -1 -1
]
{
T 58300 49600 5 10 0 0 0 0 1
device=OUTPUT
T 59100 49300 5 10 1 1 0 0 1
value=SPI0_D1
T 58200 49300 5 10 0 1 180 0 1
net=SPI0_D1:1
}
T 59900 46100 9 10 1 0 0 0 1
(MISO)
T 59900 49300 9 10 1 0 0 0 1
(MOSI)