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Building a vexriscv_smp variant SoC standalone? #687
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Hi, Basicaly, when the cpu configure asked isn't already pre-generated into the pythondata repo, the flow invoke the VexRiscv generation to fill its netlist cache. This is done by running the VexRiscv SBT project, and here the issue seem to be related to some issue between SBT and the java environnement installed. See https://stackoverflow.com/questions/61271015/sbt-fails-with-string-class-is-broken
What give the following to you ? : java --version |
Looks like I was on OpenJDK 14. Switching to OpenJDK 10 which I also had installed and I get a new failure:
The
Maybe I should have used the |
Basicaly, in : Should be VexRiscv repo and SpinalHDL repo (see https://github.com/litex-hub/pythondata-cpu-vexriscv-smp/tree/master/pythondata_cpu_vexriscv_smp/verilog/ext) |
pip install is indeed probably not doing the recursive clone. @daveshah1 can you eventually try with a manual recursive clone of |
I can confirm that the |
Currently looks like https://github.com/litex-hub/pythondata-cpu-vexriscv-smp is generated by hand rather than using the https://github.com/litex-hub/pythondata-auto tool to generate it? |
@mithro Yes, i wasn't aware of the flow, so i copied the none smp one and modified by hand. |
@Dolu1990 -- I had a todo item to fix up |
@Dolu1990 -- Added litex-hub/pythondata-cpu-vexriscv_smp#1 to track getting pythondata-cpu-vexriscv_smp be autogenerated. |
I created litex-hub/pythondata-auto#4 to track adding auto-generation of verilog as part of the pythondata-auto tool. |
@Dolu1990 - I also created litex-hub/pythondata-auto#5 about the README not saying that the repository is generated using the https://github.com/litex-hub/pythondata-auto tool. |
We can probably close this since issues have been created in the specific repositories. |
Running
fails with
Not sure if this is because vexriscv_smp must use linux-on-litex-vexriscv; something is broken in my environment; this is just a vexriscv bug; or litex is calling something wrong?
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