Lacking option to simulate memory correctly for LWD and SWD

[mbelda]

It should be a mecanism to specify the address of memory where the input and the output for each column start. Since this is the way the CGRA works.

With the approach that is used right now, I cannot model having data on the memory and reading it through a LWD. I need to write that data on the inputs file. Even worse, if every column must read the same address, I have to duplicate the data on the input file for each column. (This gets worse with the variable increment for the LWD).

Also, for the SWD I cannot simulate where is really storing the data in the memory. So, I cannot test if I am computing the address correctly. This happens when using the SWD with variable increment, but a fix could be used also for the fixed increment SWD.