diff --git a/esp-hal/Cargo.toml b/esp-hal/Cargo.toml index 8c7b71a3e00..e5482be4757 100644 --- a/esp-hal/Cargo.toml +++ b/esp-hal/Cargo.toml @@ -52,13 +52,13 @@ xtensa-lx = { version = "0.9.0", optional = true } # IMPORTANT: # Each supported device MUST have its PAC included below along with a # corresponding feature. -esp32 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true } -esp32c2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true } -esp32c3 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true } -esp32c6 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true } -esp32h2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true } -esp32s2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true } -esp32s3 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "400b3b3", features = ["critical-section", "rt"], optional = true } +esp32 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true } +esp32c2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true } +esp32c3 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true } +esp32c6 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true } +esp32h2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true } +esp32s2 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true } +esp32s3 = { git = "https://github.com/esp-rs/esp-pacs/", rev = "d7ee5ce", features = ["critical-section", "rt"], optional = true } [target.'cfg(target_arch = "riscv32")'.dependencies] esp-riscv-rt = { version = "0.8.0", path = "../esp-riscv-rt" } diff --git a/esp-hal/src/analog/adc/riscv.rs b/esp-hal/src/analog/adc/riscv.rs index f057cc4a25c..fbac76fa4eb 100644 --- a/esp-hal/src/analog/adc/riscv.rs +++ b/esp-hal/src/analog/adc/riscv.rs @@ -181,12 +181,9 @@ impl RegisterAccess for crate::peripherals::ADC1 { let sar_adc = unsafe { &*APB_SARADC::PTR }; sar_adc.onetime_sample().modify(|_, w| unsafe { - w.saradc1_onetime_sample() - .set_bit() - .saradc_onetime_channel() - .bits(channel) - .saradc_onetime_atten() - .bits(attenuation) + w.saradc1_onetime_sample().set_bit(); + w.onetime_channel().bits(channel); + w.onetime_atten().bits(attenuation) }); } @@ -195,19 +192,19 @@ impl RegisterAccess for crate::peripherals::ADC1 { sar_adc .onetime_sample() - .modify(|_, w| w.saradc_onetime_start().set_bit()); + .modify(|_, w| w.onetime_start().set_bit()); } fn is_done() -> bool { let sar_adc = unsafe { &*APB_SARADC::PTR }; - sar_adc.int_raw().read().apb_saradc1_done().bit() + sar_adc.int_raw().read().adc1_done().bit() } fn read_data() -> u16 { let sar_adc = unsafe { &*APB_SARADC::PTR }; - (sar_adc.sar1data_status().read().apb_saradc1_data().bits() as u16) & 0xfff + (sar_adc.sar1data_status().read().saradc1_data().bits() as u16) & 0xfff } fn reset() { @@ -216,12 +213,12 @@ impl RegisterAccess for crate::peripherals::ADC1 { // Clear ADC1 sampling done interrupt bit sar_adc .int_clr() - .write(|w| w.apb_saradc1_done().clear_bit_by_one()); + .write(|w| w.adc1_done().clear_bit_by_one()); // Disable ADC sampling sar_adc .onetime_sample() - .modify(|_, w| w.saradc_onetime_start().clear_bit()); + .modify(|_, w| w.onetime_start().clear_bit()); } fn set_init_code(data: u16) { @@ -292,12 +289,9 @@ impl RegisterAccess for crate::peripherals::ADC2 { let sar_adc = unsafe { &*APB_SARADC::PTR }; sar_adc.onetime_sample().modify(|_, w| unsafe { - w.saradc2_onetime_sample() - .set_bit() - .saradc_onetime_channel() - .bits(channel) - .saradc_onetime_atten() - .bits(attenuation) + w.saradc2_onetime_sample().set_bit(); + w.onetime_channel().bits(channel); + w.onetime_atten().bits(attenuation) }); } @@ -306,19 +300,19 @@ impl RegisterAccess for crate::peripherals::ADC2 { sar_adc .onetime_sample() - .modify(|_, w| w.saradc_onetime_start().set_bit()); + .modify(|_, w| w.onetime_start().set_bit()); } fn is_done() -> bool { let sar_adc = unsafe { &*APB_SARADC::PTR }; - sar_adc.int_raw().read().apb_saradc2_done().bit() + sar_adc.int_raw().read().adc2_done().bit() } fn read_data() -> u16 { let sar_adc = unsafe { &*APB_SARADC::PTR }; - (sar_adc.sar2data_status().read().apb_saradc2_data().bits() as u16) & 0xfff + (sar_adc.sar2data_status().read().saradc2_data().bits() as u16) & 0xfff } fn reset() { @@ -326,11 +320,11 @@ impl RegisterAccess for crate::peripherals::ADC2 { sar_adc .int_clr() - .write(|w| w.apb_saradc2_done().clear_bit_by_one()); + .write(|w| w.adc2_done().clear_bit_by_one()); sar_adc .onetime_sample() - .modify(|_, w| w.saradc_onetime_start().clear_bit()); + .modify(|_, w| w.onetime_start().clear_bit()); } fn set_init_code(data: u16) { @@ -416,14 +410,10 @@ where PeripheralClockControl::enable(Peripheral::ApbSarAdc); unsafe { &*APB_SARADC::PTR }.ctrl().modify(|_, w| unsafe { - w.saradc_start_force() - .set_bit() - .saradc_start() - .set_bit() - .saradc_sar_clk_gated() - .set_bit() - .saradc_xpd_sar_force() - .bits(0b11) + w.start_force().set_bit(); + w.start().set_bit(); + w.sar_clk_gated().set_bit(); + w.xpd_sar_force().bits(0b11) }); Adc { diff --git a/esp-hal/src/analog/adc/xtensa.rs b/esp-hal/src/analog/adc/xtensa.rs index 020dd4912f1..c31ee154ff6 100644 --- a/esp-hal/src/analog/adc/xtensa.rs +++ b/esp-hal/src/analog/adc/xtensa.rs @@ -238,15 +238,7 @@ impl RegisterAccess for crate::peripherals::ADC1 { let adc = unsafe { &*APB_SARADC::ptr() }; let sensors = unsafe { &*SENS::ptr() }; - cfg_if::cfg_if! { - if #[cfg(esp32s2)] { - adc.int_clr() - .write(|w| w.adc1_done().clear_bit_by_one()); - } else { - adc.int_clr() - .write(|w| w.apb_saradc1_done().clear_bit_by_one()); - } - } + adc.int_clr().write(|w| w.adc1_done().clear_bit_by_one()); sensors .sar_meas1_ctrl2() @@ -294,9 +286,7 @@ impl RegisterAccess for crate::peripherals::ADC2 { .modify(|_, w| w.sar2_rtc_force().set_bit()); let sar_apb = unsafe { &*APB_SARADC::ptr() }; - sar_apb - .arb_ctrl() - .modify(|_, w| w.adc_arb_rtc_force().set_bit()); + sar_apb.arb_ctrl().modify(|_, w| w.rtc_force().set_bit()); } fn set_start_force() { @@ -362,15 +352,7 @@ impl RegisterAccess for crate::peripherals::ADC2 { let adc = unsafe { &*APB_SARADC::ptr() }; let sensors = unsafe { &*SENS::ptr() }; - cfg_if::cfg_if! { - if #[cfg(esp32s2)] { - adc.int_clr() - .write(|w| w.adc2_done().clear_bit_by_one()); - } else { - adc.int_clr() - .write(|w| w.apb_saradc2_done().clear_bit_by_one()); - } - } + adc.int_clr().write(|w| w.adc2_done().clear_bit_by_one()); sensors .sar_meas2_ctrl2()