diff --git a/.cargo/config.toml b/.cargo/config.toml
index 35049cbcb13..9f81e304413 100644
--- a/.cargo/config.toml
+++ b/.cargo/config.toml
@@ -1,2 +1,3 @@
 [alias]
 xtask = "run --package xtask --"
+xfmt = "xtask fmt-packages"
diff --git a/esp-hal/src/aes/mod.rs b/esp-hal/src/aes/mod.rs
index bbf18752534..9615f533cc7 100644
--- a/esp-hal/src/aes/mod.rs
+++ b/esp-hal/src/aes/mod.rs
@@ -250,6 +250,7 @@ pub mod dma {
             WriteBuffer,
         },
         peripherals::AES,
+        Blocking,
     };
 
     const ALIGN_SIZE: usize = core::mem::size_of::<u32>();
@@ -275,7 +276,7 @@ pub mod dma {
         /// The underlying [`Aes`](super::Aes) driver
         pub aes: super::Aes<'d>,
 
-        channel: Channel<'d, <AES as DmaEligible>::Dma, crate::Blocking>,
+        channel: Channel<'d, <AES as DmaEligible>::Dma, Blocking>,
         rx_chain: DescriptorChain,
         tx_chain: DescriptorChain,
     }
@@ -284,12 +285,11 @@ pub mod dma {
         /// Enable DMA for the current instance of the AES driver
         pub fn with_dma<C>(
             self,
-            channel: Channel<'d, C, crate::Blocking>,
+            channel: Channel<'d, C, Blocking>,
             rx_descriptors: &'static mut [DmaDescriptor],
             tx_descriptors: &'static mut [DmaDescriptor],
         ) -> AesDma<'d>
         where
-            Self: Sized,
             C: DmaChannelConvert<<AES as DmaEligible>::Dma>,
         {
             AesDma {
diff --git a/esp-hal/src/dma/gdma.rs b/esp-hal/src/dma/gdma.rs
index 59d19ecdb80..7551193d7d4 100644
--- a/esp-hal/src/dma/gdma.rs
+++ b/esp-hal/src/dma/gdma.rs
@@ -17,7 +17,9 @@
 use crate::{
     dma::*,
     peripheral::PeripheralRef,
+    peripherals::Interrupt,
     system::{Peripheral, PeripheralClockControl},
+    Blocking,
 };
 
 #[doc(hidden)]
@@ -33,6 +35,36 @@ impl crate::private::Sealed for AnyGdmaChannel {}
 impl DmaChannel for AnyGdmaChannel {
     type Rx = ChannelRxImpl<Self>;
     type Tx = ChannelTxImpl<Self>;
+
+    fn async_handler<M: Mode>(ch: &Channel<'_, Self, M>) -> InterruptHandler {
+        match ch.tx.tx_impl.0.number() {
+            0 => DmaChannel0::handler(),
+            #[cfg(not(esp32c2))]
+            1 => DmaChannel1::handler(),
+            #[cfg(not(esp32c2))]
+            2 => DmaChannel2::handler(),
+            #[cfg(esp32s3)]
+            3 => DmaChannel3::handler(),
+            #[cfg(esp32s3)]
+            4 => DmaChannel4::handler(),
+            _ => unreachable!(),
+        }
+    }
+
+    fn interrupts<M: Mode>(ch: &Channel<'_, Self, M>) -> &'static [Interrupt] {
+        match ch.tx.tx_impl.0.number() {
+            0 => DmaChannel0::isrs(),
+            #[cfg(not(esp32c2))]
+            1 => DmaChannel1::isrs(),
+            #[cfg(not(esp32c2))]
+            2 => DmaChannel2::isrs(),
+            #[cfg(esp32s3)]
+            3 => DmaChannel3::isrs(),
+            #[cfg(esp32s3)]
+            4 => DmaChannel4::isrs(),
+            _ => unreachable!(),
+        }
+    }
 }
 
 #[non_exhaustive]
@@ -442,9 +474,27 @@ macro_rules! impl_channel {
 
             impl crate::private::Sealed for [<DmaChannel $num>] {}
 
+            impl [<DmaChannel $num>] {
+                fn handler() -> InterruptHandler {
+                    $async_handler
+                }
+
+                fn isrs() -> &'static [Interrupt] {
+                    &[$(Interrupt::$interrupt),*]
+                }
+            }
+
             impl DmaChannel for [<DmaChannel $num>] {
                 type Rx = ChannelRxImpl<SpecificGdmaChannel<$num>>;
                 type Tx = ChannelTxImpl<SpecificGdmaChannel<$num>>;
+
+                fn async_handler<M: Mode>(_ch: &Channel<'_, Self, M>) -> InterruptHandler {
+                    Self::handler()
+                }
+
+                fn interrupts<M: Mode>(_ch: &Channel<'_, Self, M>,) -> &'static [Interrupt] {
+                    Self::isrs()
+                }
             }
 
             impl DmaChannelConvert<AnyGdmaChannel> for [<DmaChannel $num>] {
@@ -464,64 +514,25 @@ macro_rules! impl_channel {
                 fn get_tx_interrupts() -> impl InterruptAccess<DmaTxInterrupt> {
                     ChannelTxImpl(SpecificGdmaChannel::<$num> {})
                 }
-
-                fn set_isr(handler: $crate::interrupt::InterruptHandler) {
-                    let mut dma = unsafe { crate::peripherals::DMA::steal() };
-                    $(
-                        dma.[< bind_ $interrupt:lower _interrupt >](handler.handler());
-                        $crate::interrupt::enable($crate::peripherals::Interrupt::$interrupt, handler.priority()).unwrap();
-                    )*
-                }
             }
 
-            impl ChannelCreator<$num> {
-                fn do_configure<'a, M: crate::Mode>(
-                    self,
-                    burst_mode: bool,
-                    priority: DmaPriority,
-                ) -> crate::dma::Channel<'a, [<DmaChannel $num>], M> {
+            impl [<DmaChannel $num>] {
+                /// Unsafely constructs a new DMA channel.
+                ///
+                /// # Safety
+                ///
+                /// The caller must ensure that only a single instance is used.
+                pub unsafe fn steal<'a>() -> Channel<'a, Self, Blocking> {
                     let tx_impl = ChannelTxImpl(SpecificGdmaChannel::<$num> {});
-                    tx_impl.set_burst_mode(burst_mode);
-                    tx_impl.set_priority(priority);
-
                     let rx_impl = ChannelRxImpl(SpecificGdmaChannel::<$num> {});
-                    rx_impl.set_burst_mode(burst_mode);
-                    rx_impl.set_priority(priority);
-                    // clear the mem2mem mode to avoid failed DMA if this
-                    // channel was previously used for a mem2mem transfer.
-                    rx_impl.set_mem2mem_mode(false);
-
-                    crate::dma::Channel {
-                        tx: ChannelTx::new(tx_impl, burst_mode),
-                        rx: ChannelRx::new(rx_impl, burst_mode),
-                        phantom: PhantomData,
-                    }
-                }
 
-                /// Configure the channel for use with blocking APIs
-                ///
-                /// Descriptors should be sized as `(CHUNK_SIZE + 4091) / 4092`. I.e., to
-                /// transfer buffers of size `1..=4092`, you need 1 descriptor.
-                pub fn configure<'a>(
-                    self,
-                    burst_mode: bool,
-                    priority: DmaPriority,
-                ) -> crate::dma::Channel<'a, [<DmaChannel $num>], crate::Blocking> {
-                    self.do_configure(burst_mode, priority)
-                }
-
-                /// Configure the channel for use with async APIs
-                ///
-                /// Descriptors should be sized as `(CHUNK_SIZE + 4091) / 4092`. I.e., to
-                /// transfer buffers of size `1..=4092`, you need 1 descriptor.
-                pub fn configure_for_async<'a>(
-                    self,
-                    burst_mode: bool,
-                    priority: DmaPriority,
-                ) -> crate::dma::Channel<'a, [<DmaChannel $num>], $crate::Async> {
-                    let this = self.do_configure(burst_mode, priority);
+                    let mut this = Channel {
+                        tx: ChannelTx::new(tx_impl),
+                        rx: ChannelRx::new(rx_impl),
+                        phantom: PhantomData,
+                    };
 
-                    [<DmaChannel $num>]::set_isr($async_handler);
+                    this.configure(false, DmaPriority::Priority0);
 
                     this
                 }
@@ -617,19 +628,19 @@ crate::impl_dma_eligible! {
 pub struct Dma<'d> {
     _inner: PeripheralRef<'d, crate::peripherals::DMA>,
     /// Channel 0
-    pub channel0: ChannelCreator<0>,
+    pub channel0: Channel<'d, DmaChannel0, Blocking>,
     /// Channel 1
     #[cfg(not(esp32c2))]
-    pub channel1: ChannelCreator<1>,
+    pub channel1: Channel<'d, DmaChannel1, Blocking>,
     /// Channel 2
     #[cfg(not(esp32c2))]
-    pub channel2: ChannelCreator<2>,
+    pub channel2: Channel<'d, DmaChannel2, Blocking>,
     /// Channel 3
     #[cfg(esp32s3)]
-    pub channel3: ChannelCreator<3>,
+    pub channel3: Channel<'d, DmaChannel3, Blocking>,
     /// Channel 4
     #[cfg(esp32s3)]
-    pub channel4: ChannelCreator<4>,
+    pub channel4: Channel<'d, DmaChannel4, Blocking>,
 }
 
 impl<'d> Dma<'d> {
@@ -645,17 +656,19 @@ impl<'d> Dma<'d> {
             .modify(|_, w| w.ahbm_rst_inter().clear_bit());
         dma.misc_conf().modify(|_, w| w.clk_en().set_bit());
 
-        Dma {
-            _inner: dma,
-            channel0: ChannelCreator {},
-            #[cfg(not(esp32c2))]
-            channel1: ChannelCreator {},
-            #[cfg(not(esp32c2))]
-            channel2: ChannelCreator {},
-            #[cfg(esp32s3)]
-            channel3: ChannelCreator {},
-            #[cfg(esp32s3)]
-            channel4: ChannelCreator {},
+        unsafe {
+            Dma {
+                _inner: dma,
+                channel0: DmaChannel0::steal(),
+                #[cfg(not(esp32c2))]
+                channel1: DmaChannel1::steal(),
+                #[cfg(not(esp32c2))]
+                channel2: DmaChannel2::steal(),
+                #[cfg(esp32s3)]
+                channel3: DmaChannel3::steal(),
+                #[cfg(esp32s3)]
+                channel4: DmaChannel4::steal(),
+            }
         }
     }
 }
diff --git a/esp-hal/src/dma/m2m.rs b/esp-hal/src/dma/m2m.rs
index 0e0aee187d1..45468b29f59 100644
--- a/esp-hal/src/dma/m2m.rs
+++ b/esp-hal/src/dma/m2m.rs
@@ -18,6 +18,8 @@ use crate::{
         Tx,
         WriteBuffer,
     },
+    Async,
+    Blocking,
     Mode,
 };
 
@@ -36,19 +38,18 @@ where
     peripheral: DmaPeripheral,
 }
 
-impl<'d, M> Mem2Mem<'d, M>
-where
-    M: Mode,
-{
+impl<'d> Mem2Mem<'d, Blocking> {
     /// Create a new Mem2Mem instance.
-    pub fn new<CH>(
-        channel: Channel<'d, CH, M>,
+    pub fn new<CH, DM>(
+        channel: Channel<'d, CH, DM>,
         peripheral: impl DmaEligible,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
     ) -> Result<Self, DmaError>
     where
         CH: DmaChannelConvert<AnyGdmaChannel>,
+        DM: Mode,
+        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
     {
         unsafe {
             Self::new_unsafe(
@@ -62,8 +63,8 @@ where
     }
 
     /// Create a new Mem2Mem instance with specific chunk size.
-    pub fn new_with_chunk_size<CH>(
-        channel: Channel<'d, CH, M>,
+    pub fn new_with_chunk_size<CH, DM>(
+        channel: Channel<'d, CH, DM>,
         peripheral: impl DmaEligible,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
@@ -71,6 +72,8 @@ where
     ) -> Result<Self, DmaError>
     where
         CH: DmaChannelConvert<AnyGdmaChannel>,
+        DM: Mode,
+        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
     {
         unsafe {
             Self::new_unsafe(
@@ -89,8 +92,8 @@ where
     ///
     /// You must ensure that your not using DMA for the same peripheral and
     /// that your the only one using the DmaPeripheral.
-    pub unsafe fn new_unsafe<CH>(
-        channel: Channel<'d, CH, M>,
+    pub unsafe fn new_unsafe<CH, DM>(
+        channel: Channel<'d, CH, DM>,
         peripheral: DmaPeripheral,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
@@ -98,6 +101,8 @@ where
     ) -> Result<Self, DmaError>
     where
         CH: DmaChannelConvert<AnyGdmaChannel>,
+        DM: Mode,
+        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
     {
         if !(1..=4092).contains(&chunk_size) {
             return Err(DmaError::InvalidChunkSize);
@@ -106,13 +111,28 @@ where
             return Err(DmaError::OutOfDescriptors);
         }
         Ok(Mem2Mem {
-            channel: channel.degrade(),
+            channel: Channel::<_, Blocking>::from(channel).degrade(),
             peripheral,
             rx_chain: DescriptorChain::new_with_chunk_size(rx_descriptors, chunk_size),
             tx_chain: DescriptorChain::new_with_chunk_size(tx_descriptors, chunk_size),
         })
     }
 
+    /// Convert Mem2Mem to an async Mem2Mem.
+    pub fn into_async(self) -> Mem2Mem<'d, Async> {
+        Mem2Mem {
+            channel: self.channel.into_async(),
+            rx_chain: self.rx_chain,
+            tx_chain: self.tx_chain,
+            peripheral: self.peripheral,
+        }
+    }
+}
+
+impl<'d, M> Mem2Mem<'d, M>
+where
+    M: Mode,
+{
     /// Start a memory to memory transfer.
     pub fn start_transfer<'t, TXBUF, RXBUF>(
         &mut self,
diff --git a/esp-hal/src/dma/mod.rs b/esp-hal/src/dma/mod.rs
index c228517e691..ada29ca5109 100644
--- a/esp-hal/src/dma/mod.rs
+++ b/esp-hal/src/dma/mod.rs
@@ -20,7 +20,7 @@
 //! # use esp_hal::dma_buffers;
 //! # use esp_hal::gpio::Io;
 //! # use esp_hal::spi::{master::Spi, SpiMode};
-//! # use esp_hal::dma::{Dma, DmaPriority};
+//! # use esp_hal::dma::Dma;
 //! let dma = Dma::new(peripherals.DMA);
 #![cfg_attr(any(esp32, esp32s2), doc = "let dma_channel = dma.spi2channel;")]
 #![cfg_attr(not(any(esp32, esp32s2)), doc = "let dma_channel = dma.channel0;")]
@@ -39,10 +39,7 @@
 //! .with_mosi(mosi)
 //! .with_miso(miso)
 //! .with_cs(cs)
-//! .with_dma(dma_channel.configure(
-//!     false,
-//!     DmaPriority::Priority0,
-//! ));
+//! .with_dma(dma_channel);
 //! # }
 //! ```
 //! 
@@ -58,6 +55,25 @@
 
 use core::{cmp::min, fmt::Debug, marker::PhantomData, sync::atomic::compiler_fence};
 
+use enumset::{EnumSet, EnumSetType};
+
+pub use self::buffers::*;
+#[cfg(gdma)]
+pub use self::gdma::*;
+#[cfg(gdma)]
+pub use self::m2m::*;
+#[cfg(pdma)]
+pub use self::pdma::*;
+use crate::{
+    interrupt::InterruptHandler,
+    peripherals::Interrupt,
+    soc::is_slice_in_dram,
+    Async,
+    Blocking,
+    Cpu,
+    Mode,
+};
+
 trait Word: crate::private::Sealed {}
 
 macro_rules! impl_word {
@@ -351,17 +367,6 @@ impl DmaDescriptor {
     }
 }
 
-use enumset::{EnumSet, EnumSetType};
-
-pub use self::buffers::*;
-#[cfg(gdma)]
-pub use self::gdma::*;
-#[cfg(gdma)]
-pub use self::m2m::*;
-#[cfg(pdma)]
-pub use self::pdma::*;
-use crate::{interrupt::InterruptHandler, soc::is_slice_in_dram, Mode};
-
 mod buffers;
 #[cfg(gdma)]
 mod gdma;
@@ -1523,21 +1528,24 @@ impl RxCircularState {
 }
 
 /// A description of a DMA Channel.
-pub trait DmaChannel: crate::private::Sealed {
+pub trait DmaChannel: crate::private::Sealed + Sized {
     /// A description of the RX half of a DMA Channel.
     type Rx: RxRegisterAccess + InterruptAccess<DmaRxInterrupt>;
 
     /// A description of the TX half of a DMA Channel.
     type Tx: TxRegisterAccess + InterruptAccess<DmaTxInterrupt>;
+
+    /// Returns the async interrupt handler.
+    fn async_handler<M: Mode>(ch: &Channel<'_, Self, M>) -> InterruptHandler;
+
+    /// Returns the interrupt.
+    fn interrupts<M: Mode>(ch: &Channel<'_, Self, M>) -> &'static [Interrupt];
 }
 
 #[doc(hidden)]
 pub trait DmaChannelExt: DmaChannel {
     fn get_rx_interrupts() -> impl InterruptAccess<DmaRxInterrupt>;
     fn get_tx_interrupts() -> impl InterruptAccess<DmaTxInterrupt>;
-
-    #[doc(hidden)]
-    fn set_isr(handler: InterruptHandler);
 }
 
 #[doc(hidden)]
@@ -1629,9 +1637,14 @@ impl<'a, CH> ChannelRx<'a, CH>
 where
     CH: DmaChannel,
 {
-    fn new(rx_impl: CH::Rx, burst_mode: bool) -> Self {
+    fn new(rx_impl: CH::Rx) -> Self {
+        #[cfg(gdma)]
+        // clear the mem2mem mode to avoid failed DMA if this
+        // channel was previously used for a mem2mem transfer.
+        rx_impl.set_mem2mem_mode(false);
+
         Self {
-            burst_mode,
+            burst_mode: false,
             rx_impl,
             _phantom: PhantomData,
         }
@@ -1649,6 +1662,12 @@ where
             _phantom: PhantomData,
         }
     }
+
+    /// Configure the channel.
+    pub fn configure(&mut self, burst_mode: bool, priority: DmaPriority) {
+        self.burst_mode = burst_mode;
+        self.rx_impl.configure(burst_mode, priority);
+    }
 }
 
 impl<'a, CH> crate::private::Sealed for ChannelRx<'a, CH> where CH: DmaChannel {}
@@ -1845,9 +1864,9 @@ impl<'a, CH> ChannelTx<'a, CH>
 where
     CH: DmaChannel,
 {
-    fn new(tx_impl: CH::Tx, burst_mode: bool) -> Self {
+    fn new(tx_impl: CH::Tx) -> Self {
         Self {
-            burst_mode,
+            burst_mode: false,
             tx_impl,
             _phantom: PhantomData,
         }
@@ -1865,6 +1884,12 @@ where
             _phantom: PhantomData,
         }
     }
+
+    /// Configure the channel.
+    pub fn configure(&mut self, burst_mode: bool, priority: DmaPriority) {
+        self.burst_mode = burst_mode;
+        self.tx_impl.configure(burst_mode, priority);
+    }
 }
 
 impl<'a, CH> crate::private::Sealed for ChannelTx<'a, CH> where CH: DmaChannel {}
@@ -2031,12 +2056,24 @@ pub trait RegisterAccess: crate::private::Sealed {
 pub trait RxRegisterAccess: RegisterAccess {
     #[cfg(gdma)]
     fn set_mem2mem_mode(&self, value: bool);
+
+    /// Configure the channel.
+    fn configure(&self, burst_mode: bool, priority: DmaPriority) {
+        self.set_burst_mode(burst_mode);
+        self.set_priority(priority);
+    }
 }
 
 #[doc(hidden)]
 pub trait TxRegisterAccess: RegisterAccess {
     /// Outlink descriptor address when EOF occurs of Tx channel.
     fn last_dscr_address(&self) -> usize;
+
+    /// Configure the channel.
+    fn configure(&self, burst_mode: bool, priority: DmaPriority) {
+        self.set_burst_mode(burst_mode);
+        self.set_priority(priority);
+    }
 }
 
 #[doc(hidden)]
@@ -2060,19 +2097,19 @@ pub trait InterruptAccess<T: EnumSetType>: crate::private::Sealed {
 }
 
 /// DMA Channel
-pub struct Channel<'d, CH, MODE>
+pub struct Channel<'d, CH, M>
 where
     CH: DmaChannel,
-    MODE: Mode,
+    M: Mode,
 {
     /// RX half of the channel
     pub rx: ChannelRx<'d, CH>,
     /// TX half of the channel
     pub tx: ChannelTx<'d, CH>,
-    phantom: PhantomData<MODE>,
+    pub(crate) phantom: PhantomData<M>,
 }
 
-impl<'d, C> Channel<'d, C, crate::Blocking>
+impl<'d, C> Channel<'d, C, Blocking>
 where
     C: DmaChannel,
 {
@@ -2082,9 +2119,12 @@ where
     /// Interrupts are not enabled at the peripheral level here.
     pub fn set_interrupt_handler(&mut self, handler: InterruptHandler)
     where
-        C: DmaChannelExt,
+        C: DmaChannel,
     {
-        C::set_isr(handler);
+        for interrupt in C::interrupts(self).iter().copied() {
+            unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) };
+            crate::interrupt::enable(interrupt, handler.priority()).unwrap();
+        }
     }
 
     /// Listen for the given interrupts
@@ -2128,6 +2168,55 @@ where
             }
         }
     }
+
+    /// Configure the channel.
+    pub fn configure(&mut self, burst_mode: bool, priority: DmaPriority) {
+        self.tx.configure(burst_mode, priority);
+        self.rx.configure(burst_mode, priority);
+    }
+
+    /// Converts a blocking channel to an async channel.
+    pub fn into_async(mut self) -> Channel<'d, C, Async> {
+        self.set_interrupt_handler(C::async_handler(&self));
+
+        Channel {
+            tx: self.tx,
+            rx: self.rx,
+            phantom: PhantomData,
+        }
+    }
+}
+
+impl<'d, C> Channel<'d, C, Async>
+where
+    C: DmaChannel,
+{
+    /// Converts an async channel to a blocking channel.
+    pub fn into_blocking(self) -> Channel<'d, C, Blocking> {
+        for interrupt in C::interrupts(&self).iter().copied() {
+            crate::interrupt::disable(Cpu::ProCpu, interrupt);
+            #[cfg(multi_core)]
+            crate::interrupt::disable(Cpu::AppCpu, interrupt);
+        }
+
+        Channel {
+            tx: self.tx,
+            rx: self.rx,
+            phantom: PhantomData,
+        }
+    }
+}
+
+impl<'d, C: DmaChannel> From<Channel<'d, C, Blocking>> for Channel<'d, C, Async> {
+    fn from(channel: Channel<'d, C, Blocking>) -> Self {
+        channel.into_async()
+    }
+}
+
+impl<'d, C: DmaChannel> From<Channel<'d, C, Async>> for Channel<'d, C, Blocking> {
+    fn from(channel: Channel<'d, C, Async>) -> Self {
+        channel.into_blocking()
+    }
 }
 
 impl<'d, CH, M: Mode> Channel<'d, CH, M>
@@ -2852,13 +2941,13 @@ pub(crate) mod asynch {
 
         #[cfg(i2s0)]
         #[handler(priority = crate::interrupt::Priority::max())]
-        pub(crate) fn interrupt_handler_i2s0() {
+        pub(crate) fn interrupt_handler_i2s0_dma() {
             handle_interrupt::<I2s0DmaChannel>();
         }
 
         #[cfg(i2s1)]
         #[handler(priority = crate::interrupt::Priority::max())]
-        pub(crate) fn interrupt_handler_i2s1() {
+        pub(crate) fn interrupt_handler_i2s1_dma() {
             handle_interrupt::<I2s1DmaChannel>();
         }
     }
diff --git a/esp-hal/src/dma/pdma.rs b/esp-hal/src/dma/pdma.rs
index de853696aee..3d0c71c6dbb 100644
--- a/esp-hal/src/dma/pdma.rs
+++ b/esp-hal/src/dma/pdma.rs
@@ -16,6 +16,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 use crate::{
     dma::*,
     peripheral::PeripheralRef,
+    peripherals::Interrupt,
     system::{Peripheral, PeripheralClockControl},
 };
 
@@ -324,9 +325,27 @@ macro_rules! ImplSpiChannel {
             #[non_exhaustive]
             pub struct [<Spi $num DmaChannel>] {}
 
+            impl [<Spi $num DmaChannel>] {
+                fn handler() -> InterruptHandler {
+                    super::asynch::interrupt::[< interrupt_handler_spi $num _dma >]
+                }
+
+                fn isrs() -> &'static [Interrupt] {
+                    &[Interrupt::[< SPI $num _DMA >]]
+                }
+            }
+
             impl DmaChannel for [<Spi $num DmaChannel>] {
                 type Rx = SpiDmaRxChannelImpl<Self>;
                 type Tx = SpiDmaTxChannelImpl<Self>;
+
+                fn async_handler<M: Mode>(_ch: &Channel<'_, Self, M>) -> InterruptHandler {
+                    Self::handler()
+                }
+
+                fn interrupts<M: Mode>(_ch: &Channel<'_, Self, M>) -> &'static [Interrupt] {
+                    Self::isrs()
+                }
             }
 
             impl DmaChannelExt for [<Spi $num DmaChannel>] {
@@ -336,14 +355,6 @@ macro_rules! ImplSpiChannel {
                 fn get_tx_interrupts() -> impl InterruptAccess<DmaTxInterrupt> {
                     SpiDmaTxChannelImpl(Self {})
                 }
-
-                fn set_isr(handler: InterruptHandler) {
-                    let interrupt = $crate::peripherals::Interrupt::[< SPI $num _DMA >];
-                    unsafe {
-                        crate::interrupt::bind_interrupt(interrupt, handler.handler());
-                    }
-                    crate::interrupt::enable(interrupt, handler.priority()).unwrap();
-                }
             }
 
             impl PdmaChannel for [<Spi $num DmaChannel>] {
@@ -377,64 +388,23 @@ macro_rules! ImplSpiChannel {
 
             impl $crate::private::Sealed for [<Spi $num DmaChannel>] {}
 
-            #[doc = concat!("Creates a channel for SPI", $num)]
-            #[non_exhaustive]
-            pub struct [<Spi $num DmaChannelCreator>] {}
-
-            impl [<Spi $num DmaChannelCreator>] {
-                fn do_configure<'a, M: $crate::Mode>(
-                    self,
-                    burst_mode: bool,
-                    priority: DmaPriority,
-                ) -> Channel<'a, [<Spi $num DmaChannel>], M> {
-                    #[cfg(esp32)]
-                    {
-                        // (only) on ESP32 we need to configure DPORT for the SPI DMA channels
-                        let dport = unsafe { &*crate::peripherals::DPORT::PTR };
-                        dport
-                            .spi_dma_chan_sel()
-                            .modify(|_, w| unsafe { w.[< spi $num _dma_chan_sel>]().bits($num - 1) });
-                    }
-
-                    let tx_impl = SpiDmaTxChannelImpl([<Spi $num DmaChannel>] {});
-                    tx_impl.set_burst_mode(burst_mode);
-                    tx_impl.set_priority(priority);
-
-                    let rx_impl = SpiDmaRxChannelImpl([<Spi $num DmaChannel>] {});
-                    rx_impl.set_burst_mode(burst_mode);
-                    rx_impl.set_priority(priority);
-
-                    Channel {
-                        tx: ChannelTx::new(tx_impl, burst_mode),
-                        rx: ChannelRx::new(rx_impl, burst_mode),
-                        phantom: PhantomData,
-                    }
-                }
-
-                /// Configure the channel for use with blocking APIs
+            impl [<Spi $num DmaChannel>] {
+                /// Unsafely constructs a new DMA channel.
                 ///
-                /// Descriptors should be sized as `(CHUNK_SIZE + 4091) / 4092`. I.e., to
-                /// transfer buffers of size `1..=4092`, you need 1 descriptor.
-                pub fn configure<'a>(
-                    self,
-                    burst_mode: bool,
-                    priority: DmaPriority,
-                ) -> Channel<'a, [<Spi $num DmaChannel>], $crate::Blocking> {
-                    Self::do_configure(self, burst_mode, priority)
-                }
-
-                /// Configure the channel for use with async APIs
+                /// # Safety
                 ///
-                /// Descriptors should be sized as `(CHUNK_SIZE + 4091) / 4092`. I.e., to
-                /// transfer buffers of size `1..=4092`, you need 1 descriptor.
-                pub fn configure_for_async<'a>(
-                    self,
-                    burst_mode: bool,
-                    priority: DmaPriority,
-                ) -> Channel<'a, [<Spi $num DmaChannel>], $crate::Async> {
-                    let this = Self::do_configure(self, burst_mode, priority);
+                /// The caller must ensure that only a single instance is used.
+                pub unsafe fn steal<'a>() -> Channel<'a, Self, Blocking> {
+                    let tx_impl = SpiDmaTxChannelImpl(Self {});
+                    let rx_impl = SpiDmaRxChannelImpl(Self {});
+
+                    let mut this = Channel {
+                        tx: ChannelTx::new(tx_impl),
+                        rx: ChannelRx::new(rx_impl),
+                        phantom: PhantomData,
+                    };
 
-                    [<Spi $num DmaChannel>]::set_isr(super::asynch::interrupt::[< interrupt_handler_spi $num _dma >]);
+                    this.configure(false, DmaPriority::Priority0);
 
                     this
                 }
@@ -746,9 +716,27 @@ macro_rules! ImplI2sChannel {
 
             impl $crate::private::Sealed for [<I2s $num DmaChannel>] {}
 
+            impl [<I2s $num DmaChannel>] {
+                fn handler() -> InterruptHandler {
+                    super::asynch::interrupt::[< interrupt_handler_i2s $num _dma >]
+                }
+
+                fn isrs() -> &'static [Interrupt] {
+                    &[Interrupt::[< I2S $num >]]
+                }
+            }
+
             impl DmaChannel for [<I2s $num DmaChannel>] {
                 type Rx = I2sDmaRxChannelImpl<Self>;
                 type Tx = I2sDmaTxChannelImpl<Self>;
+
+                fn async_handler<M: Mode>(_ch: &Channel<'_, Self, M>) -> InterruptHandler {
+                    Self::handler()
+                }
+
+                fn interrupts<M: Mode>(_ch: &Channel<'_, Self, M>) -> &'static [Interrupt] {
+                    Self::isrs()
+                }
             }
 
             impl DmaChannelExt for [<I2s $num DmaChannel>] {
@@ -758,14 +746,6 @@ macro_rules! ImplI2sChannel {
                 fn get_tx_interrupts() -> impl InterruptAccess<DmaTxInterrupt> {
                     I2sDmaTxChannelImpl(Self {})
                 }
-
-                fn set_isr(handler: InterruptHandler) {
-                    let interrupt = $crate::peripherals::Interrupt::[< I2S $num >];
-                    unsafe {
-                        crate::interrupt::bind_interrupt(interrupt, handler.handler());
-                    }
-                    crate::interrupt::enable(interrupt, handler.priority()).unwrap();
-                }
             }
 
             impl PdmaChannel for [<I2s $num DmaChannel>] {
@@ -796,54 +776,23 @@ macro_rules! ImplI2sChannel {
                 }
             }
 
-            #[doc = concat!("Creates a channel for I2S", $num)]
-            pub struct [<I2s $num DmaChannelCreator>] {}
-
-            impl [<I2s $num DmaChannelCreator>] {
-                fn do_configure<'a, M: $crate::Mode>(
-                    self,
-                    burst_mode: bool,
-                    priority: DmaPriority,
-                ) -> Channel<'a, [<I2s $num DmaChannel>], M> {
-                    let tx_impl = I2sDmaTxChannelImpl([<I2s $num DmaChannel>] {});
-                    tx_impl.set_burst_mode(burst_mode);
-                    tx_impl.set_priority(priority);
-
-                    let rx_impl = I2sDmaRxChannelImpl([<I2s $num DmaChannel>] {});
-                    rx_impl.set_burst_mode(burst_mode);
-                    rx_impl.set_priority(priority);
-
-                    Channel {
-                        tx: ChannelTx::new(tx_impl, burst_mode),
-                        rx: ChannelRx::new(rx_impl, burst_mode),
-                        phantom: PhantomData,
-                    }
-                }
-
-                /// Configure the channel for use with blocking APIs
+            impl [<I2s $num DmaChannel>] {
+                /// Unsafely constructs a new DMA channel.
                 ///
-                /// Descriptors should be sized as `(CHUNK_SIZE + 4091) / 4092`. I.e., to
-                /// transfer buffers of size `1..=4092`, you need 1 descriptor.
-                pub fn configure<'a>(
-                    self,
-                    burst_mode: bool,
-                    priority: DmaPriority,
-                ) -> Channel<'a, [<I2s $num DmaChannel>], $crate::Blocking> {
-                    Self::do_configure(self, burst_mode, priority)
-                }
-
-                /// Configure the channel for use with async APIs
+                /// # Safety
                 ///
-                /// Descriptors should be sized as `(CHUNK_SIZE + 4091) / 4092`. I.e., to
-                /// transfer buffers of size `1..=4092`, you need 1 descriptor.
-                pub fn configure_for_async<'a>(
-                    self,
-                    burst_mode: bool,
-                    priority: DmaPriority,
-                ) -> Channel<'a, [<I2s $num DmaChannel>], $crate::Async> {
-                    let this = Self::do_configure(self, burst_mode, priority);
+                /// The caller must ensure that only a single instance is used.
+                pub unsafe fn steal<'a>() -> Channel<'a, Self, Blocking> {
+                    let tx_impl = I2sDmaTxChannelImpl(Self {});
+                    let rx_impl = I2sDmaRxChannelImpl(Self {});
+
+                    let mut this = Channel {
+                        tx: ChannelTx::new(tx_impl),
+                        rx: ChannelRx::new(rx_impl),
+                        phantom: PhantomData,
+                    };
 
-                    [<I2s $num DmaChannel>]::set_isr(super::asynch::interrupt::[< interrupt_handler_i2s $num >]);
+                    this.configure(false, DmaPriority::Priority0);
 
                     this
                 }
@@ -874,14 +823,14 @@ crate::impl_dma_eligible!([I2s1DmaChannel] I2S1 => I2s1);
 pub struct Dma<'d> {
     _inner: PeripheralRef<'d, crate::peripherals::DMA>,
     /// DMA channel for SPI2
-    pub spi2channel: Spi2DmaChannelCreator,
+    pub spi2channel: Channel<'d, Spi2DmaChannel, Blocking>,
     /// DMA channel for SPI3
-    pub spi3channel: Spi3DmaChannelCreator,
+    pub spi3channel: Channel<'d, Spi3DmaChannel, Blocking>,
     /// DMA channel for I2S0
-    pub i2s0channel: I2s0DmaChannelCreator,
+    pub i2s0channel: Channel<'d, I2s0DmaChannel, Blocking>,
     /// DMA channel for I2S1
     #[cfg(i2s1)]
-    pub i2s1channel: I2s1DmaChannelCreator,
+    pub i2s1channel: Channel<'d, I2s1DmaChannel, Blocking>,
 }
 
 impl<'d> Dma<'d> {
@@ -891,13 +840,28 @@ impl<'d> Dma<'d> {
     ) -> Dma<'d> {
         PeripheralClockControl::enable(Peripheral::Dma);
 
-        Dma {
-            _inner: dma.into_ref(),
-            spi2channel: Spi2DmaChannelCreator {},
-            spi3channel: Spi3DmaChannelCreator {},
-            i2s0channel: I2s0DmaChannelCreator {},
-            #[cfg(i2s1)]
-            i2s1channel: I2s1DmaChannelCreator {},
+        #[cfg(esp32)]
+        {
+            // (only) on ESP32 we need to configure DPORT for the SPI DMA channels
+            // This assignes the DMA channels to the SPI peripherals, which is more
+            // restrictive than necessary but we currently support the same
+            // number of SPI peripherals as SPI DMA channels so it's not a big
+            // deal.
+            let dport = unsafe { &*crate::peripherals::DPORT::PTR };
+            dport.spi_dma_chan_sel().modify(|_, w| unsafe {
+                w.spi2_dma_chan_sel().bits(1).spi3_dma_chan_sel().bits(2)
+            });
+        }
+
+        unsafe {
+            Dma {
+                _inner: dma.into_ref(),
+                spi2channel: Spi2DmaChannel::steal(),
+                spi3channel: Spi3DmaChannel::steal(),
+                i2s0channel: I2s0DmaChannel::steal(),
+                #[cfg(i2s1)]
+                i2s1channel: I2s1DmaChannel::steal(),
+            }
         }
     }
 }
@@ -924,6 +888,20 @@ impl crate::private::Sealed for AnySpiDmaChannel {}
 impl DmaChannel for AnySpiDmaChannel {
     type Rx = SpiDmaRxChannelImpl<AnySpiDmaChannelInner>;
     type Tx = SpiDmaTxChannelImpl<AnySpiDmaChannelInner>;
+
+    fn async_handler<M: Mode>(ch: &Channel<'_, Self, M>) -> InterruptHandler {
+        match &ch.tx.tx_impl.0 {
+            AnySpiDmaChannelInner::Spi2(_) => Spi2DmaChannel::handler(),
+            AnySpiDmaChannelInner::Spi3(_) => Spi3DmaChannel::handler(),
+        }
+    }
+
+    fn interrupts<M: Mode>(ch: &Channel<'_, Self, M>) -> &'static [Interrupt] {
+        match &ch.tx.tx_impl.0 {
+            AnySpiDmaChannelInner::Spi2(_) => Spi2DmaChannel::isrs(),
+            AnySpiDmaChannelInner::Spi3(_) => Spi3DmaChannel::isrs(),
+        }
+    }
 }
 
 crate::any_enum! {
@@ -960,6 +938,22 @@ impl crate::private::Sealed for AnyI2sDmaChannel {}
 impl DmaChannel for AnyI2sDmaChannel {
     type Rx = I2sDmaRxChannelImpl<AnyI2sDmaChannelInner>;
     type Tx = I2sDmaTxChannelImpl<AnyI2sDmaChannelInner>;
+
+    fn async_handler<M: Mode>(ch: &Channel<'_, Self, M>) -> InterruptHandler {
+        match &ch.tx.tx_impl.0 {
+            AnyI2sDmaChannelInner::I2s0(_) => I2s0DmaChannel::handler(),
+            #[cfg(i2s1)]
+            AnyI2sDmaChannelInner::I2s1(_) => I2s1DmaChannel::handler(),
+        }
+    }
+
+    fn interrupts<M: Mode>(ch: &Channel<'_, Self, M>) -> &'static [Interrupt] {
+        match &ch.tx.tx_impl.0 {
+            AnyI2sDmaChannelInner::I2s0(_) => I2s0DmaChannel::isrs(),
+            #[cfg(i2s1)]
+            AnyI2sDmaChannelInner::I2s1(_) => I2s1DmaChannel::isrs(),
+        }
+    }
 }
 
 crate::any_enum! {
diff --git a/esp-hal/src/i2s.rs b/esp-hal/src/i2s.rs
index 3f69d82dfdf..4efbedded0a 100644
--- a/esp-hal/src/i2s.rs
+++ b/esp-hal/src/i2s.rs
@@ -34,7 +34,7 @@
 //! # use esp_hal::i2s::DataFormat;
 //! # use esp_hal::gpio::Io;
 //! # use esp_hal::dma_buffers;
-//! # use esp_hal::dma::{Dma, DmaPriority};
+//! # use esp_hal::dma::Dma;
 //! # let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 //! let dma = Dma::new(peripherals.DMA);
 #![cfg_attr(any(esp32, esp32s2), doc = "let dma_channel = dma.i2s0channel;")]
@@ -47,10 +47,7 @@
 //!     Standard::Philips,
 //!     DataFormat::Data16Channel16,
 //!     44100.Hz(),
-//!     dma_channel.configure(
-//!         false,
-//!         DmaPriority::Priority0,
-//!     ),
+//!     dma_channel,
 //!     rx_descriptors,
 //!     tx_descriptors,
 //! );
@@ -107,6 +104,8 @@ use crate::{
     interrupt::InterruptHandler,
     peripheral::{Peripheral, PeripheralRef},
     system::PeripheralClockControl,
+    Async,
+    Blocking,
     InterruptConfigurable,
     Mode,
 };
@@ -252,16 +251,16 @@ impl DataFormat {
 }
 
 /// Instance of the I2S peripheral driver
-pub struct I2s<'d, DmaMode, T = AnyI2s>
+pub struct I2s<'d, M, T = AnyI2s>
 where
     T: RegisterAccess,
-    DmaMode: Mode,
+    M: Mode,
 {
     /// Handles the reception (RX) side of the I2S peripheral.
-    pub i2s_rx: RxCreator<'d, DmaMode, T>,
+    pub i2s_rx: RxCreator<'d, M, T>,
     /// Handles the transmission (TX) side of the I2S peripheral.
-    pub i2s_tx: TxCreator<'d, DmaMode, T>,
-    phantom: PhantomData<DmaMode>,
+    pub i2s_tx: TxCreator<'d, M, T>,
+    phantom: PhantomData<M>,
 }
 
 impl<'d, DmaMode, T> I2s<'d, DmaMode, T>
@@ -368,24 +367,23 @@ where
     }
 }
 
-impl<'d, DmaMode> I2s<'d, DmaMode>
-where
-    DmaMode: Mode,
-{
+impl<'d> I2s<'d, Blocking> {
     /// Construct a new I2S peripheral driver instance for the first I2S
     /// peripheral
     #[allow(clippy::too_many_arguments)]
-    pub fn new<CH>(
+    pub fn new<CH, DM>(
         i2s: impl Peripheral<P = impl RegisterAccess> + 'd,
         standard: Standard,
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
-        channel: Channel<'d, CH, DmaMode>,
+        channel: Channel<'d, CH, DM>,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
     ) -> Self
     where
         CH: DmaChannelConvert<<AnyI2s as DmaEligible>::Dma>,
+        DM: Mode,
+        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
     {
         Self::new_typed(
             i2s.map_into(),
@@ -399,25 +397,26 @@ where
     }
 }
 
-impl<'d, DmaMode, T> I2s<'d, DmaMode, T>
+impl<'d, T> I2s<'d, Blocking, T>
 where
     T: RegisterAccess,
-    DmaMode: Mode,
 {
     /// Construct a new I2S peripheral driver instance for the first I2S
     /// peripheral
     #[allow(clippy::too_many_arguments)]
-    pub fn new_typed<CH>(
+    pub fn new_typed<CH, DM>(
         i2s: impl Peripheral<P = T> + 'd,
         standard: Standard,
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
-        channel: Channel<'d, CH, DmaMode>,
+        channel: Channel<'d, CH, DM>,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
     ) -> Self
     where
         CH: DmaChannelConvert<T::Dma>,
+        DM: Mode,
+        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
     {
         crate::into_ref!(i2s);
         Self::new_internal(
@@ -425,12 +424,43 @@ where
             standard,
             data_format,
             sample_rate,
-            channel,
+            channel.into(),
             rx_descriptors,
             tx_descriptors,
         )
     }
 
+    /// Converts the SPI instance into async mode.
+    pub fn into_async(self) -> I2s<'d, Async, T> {
+        let channel = Channel {
+            rx: self.i2s_rx.rx_channel,
+            tx: self.i2s_tx.tx_channel,
+            phantom: PhantomData::<Blocking>,
+        };
+        let channel = channel.into_async();
+        I2s {
+            i2s_rx: RxCreator {
+                i2s: self.i2s_rx.i2s,
+                rx_channel: channel.rx,
+                descriptors: self.i2s_rx.descriptors,
+                phantom: PhantomData,
+            },
+            i2s_tx: TxCreator {
+                i2s: self.i2s_tx.i2s,
+                tx_channel: channel.tx,
+                descriptors: self.i2s_tx.descriptors,
+                phantom: PhantomData,
+            },
+            phantom: PhantomData,
+        }
+    }
+}
+
+impl<'d, M, T> I2s<'d, M, T>
+where
+    T: RegisterAccess,
+    M: Mode,
+{
     /// Configures the I2S peripheral to use a master clock (MCLK) output pin.
     pub fn with_mclk<P: PeripheralOutput>(self, pin: impl Peripheral<P = P> + 'd) -> Self {
         crate::into_mapped_ref!(pin);
@@ -761,15 +791,15 @@ mod private {
         Mode,
     };
 
-    pub struct TxCreator<'d, DmaMode, T>
+    pub struct TxCreator<'d, M, T>
     where
         T: RegisterAccess,
-        DmaMode: Mode,
+        M: Mode,
     {
         pub i2s: PeripheralRef<'d, T>,
         pub tx_channel: ChannelTx<'d, T::Dma>,
         pub descriptors: &'static mut [DmaDescriptor],
-        pub(crate) phantom: PhantomData<DmaMode>,
+        pub(crate) phantom: PhantomData<M>,
     }
 
     impl<'d, DmaMode, T> TxCreator<'d, DmaMode, T>
@@ -820,23 +850,23 @@ mod private {
         }
     }
 
-    pub struct RxCreator<'d, DmaMode, T>
+    pub struct RxCreator<'d, M, T>
     where
         T: RegisterAccess,
-        DmaMode: Mode,
+        M: Mode,
     {
         pub i2s: PeripheralRef<'d, T>,
         pub rx_channel: ChannelRx<'d, T::Dma>,
         pub descriptors: &'static mut [DmaDescriptor],
-        pub(crate) phantom: PhantomData<DmaMode>,
+        pub(crate) phantom: PhantomData<M>,
     }
 
-    impl<'d, DmaMode, T> RxCreator<'d, DmaMode, T>
+    impl<'d, M, T> RxCreator<'d, M, T>
     where
         T: RegisterAccess,
-        DmaMode: Mode,
+        M: Mode,
     {
-        pub fn build(self) -> I2sRx<'d, DmaMode, T> {
+        pub fn build(self) -> I2sRx<'d, M, T> {
             I2sRx {
                 i2s: self.i2s,
                 rx_channel: self.rx_channel,
diff --git a/esp-hal/src/lcd_cam/cam.rs b/esp-hal/src/lcd_cam/cam.rs
index abf7b5d398f..0bd32bcb752 100644
--- a/esp-hal/src/lcd_cam/cam.rs
+++ b/esp-hal/src/lcd_cam/cam.rs
@@ -20,7 +20,7 @@
 //! # use esp_hal::lcd_cam::{cam::{Camera, RxEightBits}, LcdCam};
 //! # use fugit::RateExtU32;
 //! # use esp_hal::dma_rx_stream_buffer;
-//! # use esp_hal::dma::{Dma, DmaPriority};
+//! # use esp_hal::dma::Dma;
 //! # let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 //!
 //! # let dma = Dma::new(peripherals.DMA);
@@ -28,11 +28,6 @@
 //!
 //! # let dma_buf = dma_rx_stream_buffer!(20 * 1000, 1000);
 //!
-//! # let channel = channel.configure(
-//! #     false,
-//! #     DmaPriority::Priority0,
-//! # );
-//!
 //! let mclk_pin = io.pins.gpio15;
 //! let vsync_pin = io.pins.gpio6;
 //! let href_pin = io.pins.gpio7;
diff --git a/esp-hal/src/lcd_cam/lcd/i8080.rs b/esp-hal/src/lcd_cam/lcd/i8080.rs
index 72ab45dea80..6082b259efe 100644
--- a/esp-hal/src/lcd_cam/lcd/i8080.rs
+++ b/esp-hal/src/lcd_cam/lcd/i8080.rs
@@ -18,7 +18,7 @@
 //! # use esp_hal::gpio::Io;
 //! # use esp_hal::lcd_cam::{LcdCam, lcd::i8080::{Config, I8080, TxEightBits}};
 //! # use esp_hal::dma_tx_buffer;
-//! # use esp_hal::dma::{Dma, DmaPriority, DmaTxBuf};
+//! # use esp_hal::dma::{Dma, DmaTxBuf};
 //! # let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 //!
 //! # let dma = Dma::new(peripherals.DMA);
@@ -26,11 +26,6 @@
 //!
 //! # let mut dma_buf = dma_tx_buffer!(32678).unwrap();
 //!
-//! # let channel = channel.configure(
-//! #     false,
-//! #     DmaPriority::Priority0,
-//! # );
-//!
 //! let tx_pins = TxEightBits::new(
 //!     io.pins.gpio9,
 //!     io.pins.gpio46,
diff --git a/esp-hal/src/parl_io.rs b/esp-hal/src/parl_io.rs
index 72394da5e81..259f1c3ca26 100644
--- a/esp-hal/src/parl_io.rs
+++ b/esp-hal/src/parl_io.rs
@@ -54,6 +54,7 @@ use crate::{
     peripheral::{self, Peripheral},
     peripherals::{self, PARL_IO},
     system::PeripheralClockControl,
+    Async,
     Blocking,
     InterruptConfigurable,
     Mode,
@@ -1040,6 +1041,28 @@ where
 }
 
 impl<'d> ParlIoFullDuplex<'d, Blocking> {
+    /// Convert to an async version.
+    pub fn into_async(self) -> ParlIoFullDuplex<'d, Async> {
+        let channel = Channel {
+            tx: self.tx.tx_channel,
+            rx: self.rx.rx_channel,
+            phantom: PhantomData::<Blocking>,
+        };
+        let channel = channel.into_async();
+        ParlIoFullDuplex {
+            tx: TxCreatorFullDuplex {
+                tx_channel: channel.tx,
+                descriptors: self.tx.descriptors,
+                phantom: PhantomData,
+            },
+            rx: RxCreatorFullDuplex {
+                rx_channel: channel.rx,
+                descriptors: self.rx.descriptors,
+                phantom: PhantomData,
+            },
+        }
+    }
+
     /// Sets the interrupt handler, enables it with
     /// [crate::interrupt::Priority::min()]
     ///
@@ -1069,14 +1092,38 @@ impl<'d> ParlIoFullDuplex<'d, Blocking> {
     }
 }
 
-impl<'d> crate::private::Sealed for ParlIoFullDuplex<'d, Blocking> {}
+impl crate::private::Sealed for ParlIoFullDuplex<'_, Blocking> {}
 
-impl<'d> InterruptConfigurable for ParlIoFullDuplex<'d, Blocking> {
+impl InterruptConfigurable for ParlIoFullDuplex<'_, Blocking> {
     fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) {
         ParlIoFullDuplex::set_interrupt_handler(self, handler);
     }
 }
 
+impl<'d> ParlIoFullDuplex<'d, Async> {
+    /// Convert to a blocking version.
+    pub fn into_blocking(self) -> ParlIoFullDuplex<'d, Blocking> {
+        let channel = Channel {
+            tx: self.tx.tx_channel,
+            rx: self.rx.rx_channel,
+            phantom: PhantomData::<Async>,
+        };
+        let channel = channel.into_blocking();
+        ParlIoFullDuplex {
+            tx: TxCreatorFullDuplex {
+                tx_channel: channel.tx,
+                descriptors: self.tx.descriptors,
+                phantom: PhantomData,
+            },
+            rx: RxCreatorFullDuplex {
+                rx_channel: channel.rx,
+                descriptors: self.rx.descriptors,
+                phantom: PhantomData,
+            },
+        }
+    }
+}
+
 /// Parallel IO in half duplex / TX only mode
 pub struct ParlIoTxOnly<'d, DM>
 where
diff --git a/esp-hal/src/spi/master.rs b/esp-hal/src/spi/master.rs
index e3ad29213d5..79c9d6d99be 100644
--- a/esp-hal/src/spi/master.rs
+++ b/esp-hal/src/spi/master.rs
@@ -61,6 +61,8 @@
 //! [`embedded-hal-bus`]: https://docs.rs/embedded-hal-bus/latest/embedded_hal_bus/spi/index.html
 //! [`embassy-embedded-hal`]: https://docs.embassy.dev/embassy-embedded-hal/git/default/shared_bus/index.html
 
+use core::marker::PhantomData;
+
 pub use dma::*;
 #[cfg(gdma)]
 use enumset::EnumSet;
@@ -73,7 +75,16 @@ use procmacros::ram;
 use super::{DmaError, Error, SpiBitOrder, SpiDataMode, SpiMode};
 use crate::{
     clock::Clocks,
-    dma::{DmaChannelConvert, DmaEligible, DmaRxBuffer, DmaTxBuffer, PeripheralMarker, Rx, Tx},
+    dma::{
+        Channel,
+        DmaChannelConvert,
+        DmaEligible,
+        DmaRxBuffer,
+        DmaTxBuffer,
+        PeripheralMarker,
+        Rx,
+        Tx,
+    },
     gpio::{
         interconnect::{OutputConnection, PeripheralOutput},
         InputSignal,
@@ -86,6 +97,8 @@ use crate::{
     private,
     spi::AnySpi,
     system::PeripheralClockControl,
+    Async,
+    Blocking,
     Mode,
 };
 
@@ -423,12 +436,14 @@ impl Address {
 }
 
 /// SPI peripheral driver
-pub struct Spi<'d, T = AnySpi> {
+pub struct Spi<'d, M, T = AnySpi> {
     spi: PeripheralRef<'d, T>,
+    _mode: PhantomData<M>,
 }
 
-impl<'d, T> Spi<'d, T>
+impl<'d, M, T> Spi<'d, M, T>
 where
+    M: Mode,
     T: InstanceDma,
 {
     /// Configures the SPI instance to use DMA with the specified channel.
@@ -436,19 +451,17 @@ where
     /// This method prepares the SPI instance for DMA transfers using SPI
     /// and returns an instance of `SpiDma` that supports DMA
     /// operations.
-    pub fn with_dma<CH, DmaMode>(
-        self,
-        channel: crate::dma::Channel<'d, CH, DmaMode>,
-    ) -> SpiDma<'d, DmaMode, T>
+    pub fn with_dma<CH, DM>(self, channel: Channel<'d, CH, DM>) -> SpiDma<'d, M, T>
     where
         CH: DmaChannelConvert<T::Dma>,
-        DmaMode: Mode,
+        DM: Mode,
+        Channel<'d, CH, M>: From<Channel<'d, CH, DM>>,
     {
-        SpiDma::new(self.spi, channel)
+        SpiDma::new(self.spi, channel.into())
     }
 }
 
-impl<'d, T> Spi<'d, T>
+impl<'d, M, T> Spi<'d, M, T>
 where
     T: Instance,
 {
@@ -484,18 +497,36 @@ where
     }
 }
 
-impl<'d> Spi<'d> {
+impl<'d> Spi<'d, Blocking> {
     /// Constructs an SPI instance in 8bit dataframe mode.
     pub fn new(
         spi: impl Peripheral<P = impl Instance> + 'd,
         frequency: HertzU32,
         mode: SpiMode,
-    ) -> Spi<'d> {
+    ) -> Spi<'d, Blocking> {
         Self::new_typed(spi.map_into(), frequency, mode)
     }
+
+    /// Converts the SPI instance into async mode.
+    pub fn into_async(self) -> Spi<'d, Async> {
+        Spi {
+            spi: self.spi,
+            _mode: PhantomData,
+        }
+    }
 }
 
-impl<'d, T> Spi<'d, T>
+impl<'d> Spi<'d, Async> {
+    /// Converts the SPI instance into blocking mode.
+    pub fn into_blocking(self) -> Spi<'d, Blocking> {
+        Spi {
+            spi: self.spi,
+            _mode: PhantomData,
+        }
+    }
+}
+
+impl<'d, M, T> Spi<'d, M, T>
 where
     T: Instance,
 {
@@ -504,10 +535,13 @@ where
         spi: impl Peripheral<P = T> + 'd,
         frequency: HertzU32,
         mode: SpiMode,
-    ) -> Spi<'d, T> {
+    ) -> Spi<'d, M, T> {
         crate::into_ref!(spi);
 
-        let mut spi = Spi { spi };
+        let mut spi = Spi {
+            spi,
+            _mode: PhantomData,
+        };
         spi.spi.reset_peripheral();
         spi.spi.enable_peripheral();
         spi.spi.setup(frequency);
@@ -616,7 +650,7 @@ where
     }
 }
 
-impl<'d, T> Spi<'d, T>
+impl<'d, M, T> Spi<'d, M, T>
 where
     T: QspiInstance,
 {
@@ -663,7 +697,7 @@ where
     }
 }
 
-impl<T> Spi<'_, T>
+impl<M, T> Spi<'_, M, T>
 where
     T: Instance,
 {
@@ -754,7 +788,7 @@ where
     }
 }
 
-impl<T> embedded_hal_02::spi::FullDuplex<u8> for Spi<'_, T>
+impl<M, T> embedded_hal_02::spi::FullDuplex<u8> for Spi<'_, M, T>
 where
     T: Instance,
 {
@@ -769,7 +803,7 @@ where
     }
 }
 
-impl<T> embedded_hal_02::blocking::spi::Transfer<u8> for Spi<'_, T>
+impl<M, T> embedded_hal_02::blocking::spi::Transfer<u8> for Spi<'_, M, T>
 where
     T: Instance,
 {
@@ -780,7 +814,7 @@ where
     }
 }
 
-impl<T> embedded_hal_02::blocking::spi::Write<u8> for Spi<'_, T>
+impl<M, T> embedded_hal_02::blocking::spi::Write<u8> for Spi<'_, M, T>
 where
     T: Instance,
 {
@@ -812,6 +846,8 @@ mod dma {
             Rx,
             Tx,
         },
+        Async,
+        Blocking,
         InterruptConfigurable,
         Mode,
     };
@@ -836,6 +872,40 @@ mod dma {
         address_buffer: DmaTxBuf,
     }
 
+    impl<'d, T> SpiDma<'d, Blocking, T>
+    where
+        T: InstanceDma,
+    {
+        /// Converts the SPI instance into async mode.
+        pub fn into_async(self) -> SpiDma<'d, Async, T> {
+            SpiDma {
+                spi: self.spi,
+                channel: self.channel.into_async(),
+                tx_transfer_in_progress: self.tx_transfer_in_progress,
+                rx_transfer_in_progress: self.rx_transfer_in_progress,
+                #[cfg(all(esp32, spi_address_workaround))]
+                address_buffer: self.address_buffer,
+            }
+        }
+    }
+
+    impl<'d, T> SpiDma<'d, Async, T>
+    where
+        T: InstanceDma,
+    {
+        /// Converts the SPI instance into async mode.
+        pub fn into_blocking(self) -> SpiDma<'d, Blocking, T> {
+            SpiDma {
+                spi: self.spi,
+                channel: self.channel.into_blocking(),
+                tx_transfer_in_progress: self.tx_transfer_in_progress,
+                rx_transfer_in_progress: self.rx_transfer_in_progress,
+                #[cfg(all(esp32, spi_address_workaround))]
+                address_buffer: self.address_buffer,
+            }
+        }
+    }
+
     #[cfg(all(esp32, spi_address_workaround))]
     unsafe impl<'d, M, T> Send for SpiDma<'d, M, T>
     where
@@ -1181,7 +1251,7 @@ mod dma {
         }
     }
 
-    impl<'d, T, Buf> SpiDmaTransfer<'d, crate::Async, Buf, T>
+    impl<'d, T, Buf> SpiDmaTransfer<'d, Async, Buf, T>
     where
         T: InstanceDma,
     {
@@ -1461,6 +1531,34 @@ mod dma {
         tx_buf: DmaTxBuf,
     }
 
+    impl<'d, T> SpiDmaBus<'d, Blocking, T>
+    where
+        T: InstanceDma,
+    {
+        /// Converts the SPI instance into async mode.
+        pub fn into_async(self) -> SpiDmaBus<'d, Async, T> {
+            SpiDmaBus {
+                spi_dma: self.spi_dma.into_async(),
+                rx_buf: self.rx_buf,
+                tx_buf: self.tx_buf,
+            }
+        }
+    }
+
+    impl<'d, T> SpiDmaBus<'d, Async, T>
+    where
+        T: InstanceDma,
+    {
+        /// Converts the SPI instance into async mode.
+        pub fn into_blocking(self) -> SpiDmaBus<'d, Blocking, T> {
+            SpiDmaBus {
+                spi_dma: self.spi_dma.into_blocking(),
+                rx_buf: self.rx_buf,
+                tx_buf: self.tx_buf,
+            }
+        }
+    }
+
     impl<'d, M, T> SpiDmaBus<'d, M, T>
     where
         T: InstanceDma,
@@ -1704,7 +1802,7 @@ mod dma {
         }
     }
 
-    impl<'d, T> embedded_hal_02::blocking::spi::Transfer<u8> for SpiDmaBus<'d, crate::Blocking, T>
+    impl<'d, T> embedded_hal_02::blocking::spi::Transfer<u8> for SpiDmaBus<'d, Blocking, T>
     where
         T: InstanceDma,
     {
@@ -1716,7 +1814,7 @@ mod dma {
         }
     }
 
-    impl<'d, T> embedded_hal_02::blocking::spi::Write<u8> for SpiDmaBus<'d, crate::Blocking, T>
+    impl<'d, T> embedded_hal_02::blocking::spi::Write<u8> for SpiDmaBus<'d, Blocking, T>
     where
         T: InstanceDma,
     {
@@ -1736,6 +1834,7 @@ mod dma {
         };
 
         use super::*;
+        use crate::Async;
 
         struct DropGuard<I, F: FnOnce(I)> {
             inner: ManuallyDrop<I>,
@@ -1775,7 +1874,7 @@ mod dma {
             }
         }
 
-        impl<'d, T> SpiDmaBus<'d, crate::Async, T>
+        impl<'d, T> SpiDmaBus<'d, Async, T>
         where
             T: InstanceDma,
         {
@@ -1889,7 +1988,7 @@ mod dma {
             }
         }
 
-        impl<'d, T> embedded_hal_async::spi::SpiBus for SpiDmaBus<'d, crate::Async, T>
+        impl<'d, T> embedded_hal_async::spi::SpiBus for SpiDmaBus<'d, Async, T>
         where
             T: InstanceDma,
         {
@@ -1964,11 +2063,11 @@ mod ehal1 {
 
     use super::*;
 
-    impl<T> embedded_hal::spi::ErrorType for Spi<'_, T> {
+    impl<M, T> embedded_hal::spi::ErrorType for Spi<'_, M, T> {
         type Error = Error;
     }
 
-    impl<T> FullDuplex for Spi<'_, T>
+    impl<M, T> FullDuplex for Spi<'_, M, T>
     where
         T: Instance,
     {
@@ -1981,7 +2080,7 @@ mod ehal1 {
         }
     }
 
-    impl<T> SpiBus for Spi<'_, T>
+    impl<M, T> SpiBus for Spi<'_, M, T>
     where
         T: Instance,
     {
diff --git a/esp-hal/src/spi/slave.rs b/esp-hal/src/spi/slave.rs
index 97315ab6f92..2f07fb1c65b 100644
--- a/esp-hal/src/spi/slave.rs
+++ b/esp-hal/src/spi/slave.rs
@@ -15,7 +15,6 @@
 //!
 //! ```rust, no_run
 #![doc = crate::before_snippet!()]
-//! # use esp_hal::dma::DmaPriority;
 //! # use esp_hal::dma_buffers;
 //! # use esp_hal::spi::SpiMode;
 //! # use esp_hal::spi::slave::Spi;
@@ -39,10 +38,7 @@
 //!     cs,
 //!     SpiMode::Mode0,
 //! )
-//! .with_dma(dma_channel.configure(
-//!     false,
-//!     DmaPriority::Priority0,
-//! ), rx_descriptors, tx_descriptors);
+//! .with_dma(dma_channel, rx_descriptors, tx_descriptors);
 //!
 //! let mut receive = rx_buffer;
 //! let mut send = tx_buffer;
@@ -70,6 +66,8 @@
 //!
 //! See [tracking issue](https://github.com/esp-rs/esp-hal/issues/469) for more information.
 
+use core::marker::PhantomData;
+
 use super::{Error, SpiMode};
 use crate::{
     dma::{DescriptorChain, DmaChannelConvert, DmaEligible, PeripheralMarker, Rx, Tx},
@@ -83,6 +81,7 @@ use crate::{
     private,
     spi::AnySpi,
     system::PeripheralClockControl,
+    Blocking,
 };
 
 const MAX_DMA_SIZE: usize = 32768 - 32;
@@ -90,13 +89,14 @@ const MAX_DMA_SIZE: usize = 32768 - 32;
 /// SPI peripheral driver.
 ///
 /// See the [module-level documentation][self] for more details.
-pub struct Spi<'d, T = AnySpi> {
+pub struct Spi<'d, M, T = AnySpi> {
     spi: PeripheralRef<'d, T>,
     #[allow(dead_code)]
     data_mode: SpiMode,
+    _mode: PhantomData<M>,
 }
 
-impl<'d> Spi<'d> {
+impl<'d> Spi<'d, Blocking> {
     /// Constructs an SPI instance in 8bit dataframe mode.
     pub fn new<
         SCK: PeripheralInput,
@@ -110,12 +110,12 @@ impl<'d> Spi<'d> {
         miso: impl Peripheral<P = MISO> + 'd,
         cs: impl Peripheral<P = CS> + 'd,
         mode: SpiMode,
-    ) -> Spi<'d> {
+    ) -> Spi<'d, Blocking> {
         Self::new_typed(spi.map_into(), sclk, mosi, miso, cs, mode)
     }
 }
 
-impl<'d, T> Spi<'d, T>
+impl<'d, M, T> Spi<'d, M, T>
 where
     T: Instance,
 {
@@ -132,7 +132,7 @@ where
         miso: impl Peripheral<P = MISO> + 'd,
         cs: impl Peripheral<P = CS> + 'd,
         mode: SpiMode,
-    ) -> Spi<'d, T> {
+    ) -> Spi<'d, M, T> {
         crate::into_mapped_ref!(sclk, mosi, miso, cs);
 
         let this = Self::new_internal(spi, mode);
@@ -153,12 +153,13 @@ where
         this
     }
 
-    pub(crate) fn new_internal(spi: impl Peripheral<P = T> + 'd, mode: SpiMode) -> Spi<'d, T> {
+    pub(crate) fn new_internal(spi: impl Peripheral<P = T> + 'd, mode: SpiMode) -> Spi<'d, M, T> {
         crate::into_ref!(spi);
 
         let mut spi = Spi {
             spi,
             data_mode: mode,
+            _mode: PhantomData,
         };
 
         PeripheralClockControl::reset(spi.spi.peripheral());
@@ -193,36 +194,38 @@ pub mod dma {
         Mode,
     };
 
-    impl<'d, T> Spi<'d, T>
+    impl<'d, M, T> Spi<'d, M, T>
     where
         T: InstanceDma,
+        M: Mode,
     {
         /// Configures the SPI3 peripheral with the provided DMA channel and
         /// descriptors.
         #[cfg_attr(esp32, doc = "\n\n**Note**: ESP32 only supports Mode 1 and 3.")]
-        pub fn with_dma<CH, DmaMode>(
+        pub fn with_dma<CH, DM>(
             mut self,
-            channel: Channel<'d, CH, DmaMode>,
+            channel: Channel<'d, CH, DM>,
             rx_descriptors: &'static mut [DmaDescriptor],
             tx_descriptors: &'static mut [DmaDescriptor],
-        ) -> SpiDma<'d, DmaMode, T>
+        ) -> SpiDma<'d, M, T>
         where
             CH: DmaChannelConvert<T::Dma>,
-            DmaMode: Mode,
+            DM: Mode,
+            Channel<'d, CH, M>: From<Channel<'d, CH, DM>>,
         {
             self.spi.set_data_mode(self.data_mode, true);
-            SpiDma::new(self.spi, channel, rx_descriptors, tx_descriptors)
+            SpiDma::new(self.spi, channel.into(), rx_descriptors, tx_descriptors)
         }
     }
 
     /// A DMA capable SPI instance.
-    pub struct SpiDma<'d, DmaMode, T = AnySpi>
+    pub struct SpiDma<'d, M, T = AnySpi>
     where
         T: InstanceDma,
-        DmaMode: Mode,
+        M: Mode,
     {
         pub(crate) spi: PeripheralRef<'d, T>,
-        pub(crate) channel: Channel<'d, T::Dma, DmaMode>,
+        pub(crate) channel: Channel<'d, T::Dma, M>,
         rx_chain: DescriptorChain,
         tx_chain: DescriptorChain,
     }
diff --git a/examples/src/bin/dma_extmem2mem.rs b/examples/src/bin/dma_extmem2mem.rs
index 063197a7f6e..4fab1087c77 100644
--- a/examples/src/bin/dma_extmem2mem.rs
+++ b/examples/src/bin/dma_extmem2mem.rs
@@ -11,7 +11,7 @@ use esp_alloc as _;
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority, Mem2Mem},
+    dma::{Dma, Mem2Mem},
     dma_descriptors_chunk_size,
     prelude::*,
 };
@@ -68,11 +68,10 @@ fn main() -> ! {
     let (rx_descriptors, tx_descriptors) = dma_descriptors_chunk_size!(DATA_SIZE, CHUNK_SIZE);
 
     let dma = Dma::new(peripherals.DMA);
-    let channel = dma.channel0.configure(false, DmaPriority::Priority0);
     let dma_peripheral = peripherals.SPI2;
 
     let mut mem2mem = Mem2Mem::new_with_chunk_size(
-        channel,
+        dma.channel0,
         dma_peripheral,
         rx_descriptors,
         tx_descriptors,
diff --git a/examples/src/bin/dma_mem2mem.rs b/examples/src/bin/dma_mem2mem.rs
index 795e158d290..23dda706764 100644
--- a/examples/src/bin/dma_mem2mem.rs
+++ b/examples/src/bin/dma_mem2mem.rs
@@ -9,7 +9,7 @@
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority, Mem2Mem},
+    dma::{Dma, Mem2Mem},
     dma_buffers,
     prelude::*,
 };
@@ -28,14 +28,13 @@ fn main() -> ! {
     let (mut rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DATA_SIZE);
 
     let dma = Dma::new(peripherals.DMA);
-    let channel = dma.channel0.configure(false, DmaPriority::Priority0);
     #[cfg(any(feature = "esp32c2", feature = "esp32c3", feature = "esp32s3"))]
     let dma_peripheral = peripherals.SPI2;
     #[cfg(not(any(feature = "esp32c2", feature = "esp32c3", feature = "esp32s3")))]
     let dma_peripheral = peripherals.MEM2MEM1;
 
     let mut mem2mem =
-        Mem2Mem::new(channel, dma_peripheral, rx_descriptors, tx_descriptors).unwrap();
+        Mem2Mem::new(dma.channel0, dma_peripheral, rx_descriptors, tx_descriptors).unwrap();
 
     for i in 0..core::mem::size_of_val(tx_buffer) {
         tx_buffer[i] = (i % 256) as u8;
diff --git a/examples/src/bin/embassy_i2s_read.rs b/examples/src/bin/embassy_i2s_read.rs
index 17c48383c48..b4c919a465d 100644
--- a/examples/src/bin/embassy_i2s_read.rs
+++ b/examples/src/bin/embassy_i2s_read.rs
@@ -20,7 +20,7 @@
 use embassy_executor::Spawner;
 use esp_backtrace as _;
 use esp_hal::{
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_buffers,
     gpio::Io,
     i2s::{DataFormat, I2s, Standard},
@@ -52,10 +52,11 @@ async fn main(_spawner: Spawner) {
         Standard::Philips,
         DataFormat::Data16Channel16,
         44100u32.Hz(),
-        dma_channel.configure_for_async(false, DmaPriority::Priority0),
+        dma_channel,
         rx_descriptors,
         tx_descriptors,
-    );
+    )
+    .into_async();
 
     #[cfg(not(feature = "esp32"))]
     let i2s = i2s.with_mclk(io.pins.gpio0);
diff --git a/examples/src/bin/embassy_i2s_sound.rs b/examples/src/bin/embassy_i2s_sound.rs
index 50660d81840..203201831b8 100644
--- a/examples/src/bin/embassy_i2s_sound.rs
+++ b/examples/src/bin/embassy_i2s_sound.rs
@@ -34,7 +34,7 @@
 use embassy_executor::Spawner;
 use esp_backtrace as _;
 use esp_hal::{
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_buffers,
     gpio::Io,
     i2s::{DataFormat, I2s, Standard},
@@ -74,10 +74,11 @@ async fn main(_spawner: Spawner) {
         Standard::Philips,
         DataFormat::Data16Channel16,
         44100u32.Hz(),
-        dma_channel.configure_for_async(false, DmaPriority::Priority0),
+        dma_channel,
         rx_descriptors,
         tx_descriptors,
-    );
+    )
+    .into_async();
 
     let i2s_tx = i2s
         .i2s_tx
diff --git a/examples/src/bin/embassy_parl_io_rx.rs b/examples/src/bin/embassy_parl_io_rx.rs
index 83fccaec51d..5fef3168eba 100644
--- a/examples/src/bin/embassy_parl_io_rx.rs
+++ b/examples/src/bin/embassy_parl_io_rx.rs
@@ -14,7 +14,7 @@ use embassy_executor::Spawner;
 use embassy_time::{Duration, Timer};
 use esp_backtrace as _;
 use esp_hal::{
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_buffers,
     gpio::Io,
     parl_io::{no_clk_pin, BitPackOrder, ParlIoRxOnly, RxFourBits},
@@ -36,13 +36,12 @@ async fn main(_spawner: Spawner) {
     let (rx_buffer, rx_descriptors, _, _) = dma_buffers!(32000, 0);
 
     let dma = Dma::new(peripherals.DMA);
-    let dma_channel = dma.channel0;
 
     let mut rx_pins = RxFourBits::new(io.pins.gpio1, io.pins.gpio2, io.pins.gpio3, io.pins.gpio4);
 
     let parl_io = ParlIoRxOnly::new(
         peripherals.PARL_IO,
-        dma_channel.configure_for_async(false, DmaPriority::Priority0),
+        dma.channel0.into_async(),
         rx_descriptors,
         1.MHz(),
     )
diff --git a/examples/src/bin/embassy_parl_io_tx.rs b/examples/src/bin/embassy_parl_io_tx.rs
index 9a1ca372fb3..aabf083357c 100644
--- a/examples/src/bin/embassy_parl_io_tx.rs
+++ b/examples/src/bin/embassy_parl_io_tx.rs
@@ -18,7 +18,7 @@ use embassy_executor::Spawner;
 use embassy_time::{Duration, Timer};
 use esp_backtrace as _;
 use esp_hal::{
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_buffers,
     gpio::Io,
     parl_io::{
@@ -47,7 +47,6 @@ async fn main(_spawner: Spawner) {
     let (_, _, tx_buffer, tx_descriptors) = dma_buffers!(0, 32000);
 
     let dma = Dma::new(peripherals.DMA);
-    let dma_channel = dma.channel0;
 
     let tx_pins = TxFourBits::new(io.pins.gpio1, io.pins.gpio2, io.pins.gpio3, io.pins.gpio4);
 
@@ -55,7 +54,7 @@ async fn main(_spawner: Spawner) {
 
     let parl_io = ParlIoTxOnly::new(
         peripherals.PARL_IO,
-        dma_channel.configure_for_async(false, DmaPriority::Priority0),
+        dma.channel0.into_async(),
         tx_descriptors,
         1.MHz(),
     )
diff --git a/examples/src/bin/embassy_spi.rs b/examples/src/bin/embassy_spi.rs
index 334cd713764..f5162c0b2ad 100644
--- a/examples/src/bin/embassy_spi.rs
+++ b/examples/src/bin/embassy_spi.rs
@@ -63,8 +63,9 @@ async fn main(_spawner: Spawner) {
         .with_mosi(mosi)
         .with_miso(miso)
         .with_cs(cs)
-        .with_dma(dma_channel.configure_for_async(false, DmaPriority::Priority0))
-        .with_buffers(dma_rx_buf, dma_tx_buf);
+        .with_dma(dma_channel)
+        .with_buffers(dma_rx_buf, dma_tx_buf)
+        .into_async();
 
     let send_buffer = [0, 1, 2, 3, 4, 5, 6, 7];
     loop {
diff --git a/examples/src/bin/i2s_read.rs b/examples/src/bin/i2s_read.rs
index 30f45361264..d412525c805 100644
--- a/examples/src/bin/i2s_read.rs
+++ b/examples/src/bin/i2s_read.rs
@@ -18,7 +18,7 @@
 
 use esp_backtrace as _;
 use esp_hal::{
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_buffers,
     gpio::Io,
     i2s::{DataFormat, I2s, Standard},
@@ -49,7 +49,7 @@ fn main() -> ! {
         Standard::Philips,
         DataFormat::Data16Channel16,
         44100.Hz(),
-        dma_channel.configure(false, DmaPriority::Priority0),
+        dma_channel,
         rx_descriptors,
         tx_descriptors,
     );
diff --git a/examples/src/bin/i2s_sound.rs b/examples/src/bin/i2s_sound.rs
index e998928b7d2..de7c90f3b75 100644
--- a/examples/src/bin/i2s_sound.rs
+++ b/examples/src/bin/i2s_sound.rs
@@ -32,7 +32,7 @@
 
 use esp_backtrace as _;
 use esp_hal::{
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_buffers,
     gpio::Io,
     i2s::{DataFormat, I2s, Standard},
@@ -66,7 +66,7 @@ fn main() -> ! {
         Standard::Philips,
         DataFormat::Data16Channel16,
         44100.Hz(),
-        dma_channel.configure(false, DmaPriority::Priority0),
+        dma_channel,
         rx_descriptors,
         tx_descriptors,
     );
diff --git a/examples/src/bin/lcd_cam_ov2640.rs b/examples/src/bin/lcd_cam_ov2640.rs
index cdc6d64c1b2..16cf1c91427 100644
--- a/examples/src/bin/lcd_cam_ov2640.rs
+++ b/examples/src/bin/lcd_cam_ov2640.rs
@@ -26,7 +26,7 @@
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_rx_stream_buffer,
     gpio::Io,
     i2c,
@@ -47,12 +47,9 @@ fn main() -> ! {
     let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 
     let dma = Dma::new(peripherals.DMA);
-    let channel = dma.channel0;
 
     let dma_rx_buf = dma_rx_stream_buffer!(20 * 1000, 1000);
 
-    let channel = channel.configure(false, DmaPriority::Priority0);
-
     let cam_siod = io.pins.gpio4;
     let cam_sioc = io.pins.gpio5;
     let cam_xclk = io.pins.gpio15;
@@ -71,7 +68,7 @@ fn main() -> ! {
     );
 
     let lcd_cam = LcdCam::new(peripherals.LCD_CAM);
-    let camera = Camera::new(lcd_cam.cam, channel.rx, cam_data_pins, 20u32.MHz())
+    let camera = Camera::new(lcd_cam.cam, dma.channel0.rx, cam_data_pins, 20u32.MHz())
         .with_master_clock(cam_xclk)
         .with_pixel_clock(cam_pclk)
         .with_ctrl_pins(cam_vsync, cam_href);
diff --git a/examples/src/bin/lcd_i8080.rs b/examples/src/bin/lcd_i8080.rs
index 2937f427cae..741e1cc47d7 100644
--- a/examples/src/bin/lcd_i8080.rs
+++ b/examples/src/bin/lcd_i8080.rs
@@ -25,7 +25,7 @@
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority, DmaTxBuf},
+    dma::{Dma, DmaTxBuf},
     dma_tx_buffer,
     gpio::{Input, Io, Level, Output, Pull},
     lcd_cam::{
@@ -50,12 +50,9 @@ fn main() -> ! {
     let lcd_te = io.pins.gpio48; // Frame sync
 
     let dma = Dma::new(peripherals.DMA);
-    let channel = dma.channel0;
 
     let dma_tx_buf = dma_tx_buffer!(4000).unwrap();
 
-    let channel = channel.configure(false, DmaPriority::Priority0);
-
     let delay = Delay::new();
 
     let mut backlight = Output::new(lcd_backlight, Level::Low);
@@ -76,7 +73,7 @@ fn main() -> ! {
     let lcd_cam = LcdCam::new(peripherals.LCD_CAM);
     let i8080 = I8080::new(
         lcd_cam.lcd,
-        channel.tx,
+        dma.channel0.tx,
         tx_pins,
         20.MHz(),
         Config::default(),
diff --git a/examples/src/bin/parl_io_rx.rs b/examples/src/bin/parl_io_rx.rs
index 8f66c376ea4..7ff13a96b90 100644
--- a/examples/src/bin/parl_io_rx.rs
+++ b/examples/src/bin/parl_io_rx.rs
@@ -12,7 +12,7 @@
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_buffers,
     gpio::Io,
     parl_io::{no_clk_pin, BitPackOrder, ParlIoRxOnly, RxFourBits},
@@ -33,13 +33,8 @@ fn main() -> ! {
 
     let mut rx_pins = RxFourBits::new(io.pins.gpio1, io.pins.gpio2, io.pins.gpio3, io.pins.gpio4);
 
-    let parl_io = ParlIoRxOnly::new(
-        peripherals.PARL_IO,
-        dma_channel.configure(false, DmaPriority::Priority0),
-        rx_descriptors,
-        1.MHz(),
-    )
-    .unwrap();
+    let parl_io =
+        ParlIoRxOnly::new(peripherals.PARL_IO, dma_channel, rx_descriptors, 1.MHz()).unwrap();
 
     let mut parl_io_rx = parl_io
         .rx
diff --git a/examples/src/bin/parl_io_tx.rs b/examples/src/bin/parl_io_tx.rs
index 0df17ad398e..287e94867d5 100644
--- a/examples/src/bin/parl_io_tx.rs
+++ b/examples/src/bin/parl_io_tx.rs
@@ -16,7 +16,7 @@
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_buffers,
     gpio::Io,
     parl_io::{
@@ -46,13 +46,8 @@ fn main() -> ! {
 
     let mut pin_conf = TxPinConfigWithValidPin::new(tx_pins, io.pins.gpio5);
 
-    let parl_io = ParlIoTxOnly::new(
-        peripherals.PARL_IO,
-        dma_channel.configure(false, DmaPriority::Priority0),
-        tx_descriptors,
-        1.MHz(),
-    )
-    .unwrap();
+    let parl_io =
+        ParlIoTxOnly::new(peripherals.PARL_IO, dma_channel, tx_descriptors, 1.MHz()).unwrap();
 
     let mut clock_pin = ClkOutPin::new(io.pins.gpio6);
 
diff --git a/examples/src/bin/qspi_flash.rs b/examples/src/bin/qspi_flash.rs
index 687b28ba18f..216727ea237 100644
--- a/examples/src/bin/qspi_flash.rs
+++ b/examples/src/bin/qspi_flash.rs
@@ -30,7 +30,7 @@
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
+    dma::{Dma, DmaRxBuf, DmaTxBuf},
     dma_buffers,
     gpio::Io,
     prelude::*,
@@ -86,7 +86,7 @@ fn main() -> ! {
         .with_sio2(sio2)
         .with_sio3(sio3)
         .with_cs(cs)
-        .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
+        .with_dma(dma_channel);
 
     let delay = Delay::new();
 
diff --git a/examples/src/bin/spi_loopback_dma.rs b/examples/src/bin/spi_loopback_dma.rs
index f081478da36..239dfc5f3b6 100644
--- a/examples/src/bin/spi_loopback_dma.rs
+++ b/examples/src/bin/spi_loopback_dma.rs
@@ -21,7 +21,7 @@
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
+    dma::{Dma, DmaRxBuf, DmaTxBuf},
     dma_buffers,
     gpio::Io,
     prelude::*,
@@ -58,7 +58,7 @@ fn main() -> ! {
         .with_mosi(mosi)
         .with_miso(miso)
         .with_cs(cs)
-        .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
+        .with_dma(dma_channel);
 
     let delay = Delay::new();
 
diff --git a/examples/src/bin/spi_loopback_dma_psram.rs b/examples/src/bin/spi_loopback_dma_psram.rs
index 1ae30408518..dd03c696ed7 100644
--- a/examples/src/bin/spi_loopback_dma_psram.rs
+++ b/examples/src/bin/spi_loopback_dma_psram.rs
@@ -25,7 +25,7 @@
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaBufBlkSize, DmaPriority, DmaRxBuf, DmaTxBuf},
+    dma::{Dma, DmaBufBlkSize, DmaRxBuf, DmaTxBuf},
     gpio::Io,
     peripheral::Peripheral,
     prelude::*,
@@ -95,7 +95,7 @@ fn main() -> ! {
         .with_miso(miso)
         .with_mosi(mosi)
         .with_cs(cs)
-        .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
+        .with_dma(dma_channel);
 
     delay.delay_millis(100); // delay to let the above messages display
 
diff --git a/examples/src/bin/spi_slave_dma.rs b/examples/src/bin/spi_slave_dma.rs
index 5352c71db8b..caaee2fb29a 100644
--- a/examples/src/bin/spi_slave_dma.rs
+++ b/examples/src/bin/spi_slave_dma.rs
@@ -32,7 +32,7 @@
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_buffers,
     gpio::{Input, Io, Level, Output, Pull},
     prelude::*,
@@ -75,11 +75,7 @@ fn main() -> ! {
         slave_cs,
         SpiMode::Mode0,
     )
-    .with_dma(
-        dma_channel.configure(false, DmaPriority::Priority0),
-        tx_descriptors,
-        rx_descriptors,
-    );
+    .with_dma(dma_channel, tx_descriptors, rx_descriptors);
 
     let delay = Delay::new();
 
diff --git a/hil-test/tests/aes_dma.rs b/hil-test/tests/aes_dma.rs
index 3fdb98db1ff..e560e041dd3 100644
--- a/hil-test/tests/aes_dma.rs
+++ b/hil-test/tests/aes_dma.rs
@@ -7,7 +7,7 @@
 
 use esp_hal::{
     aes::{dma::CipherMode, Aes, Mode},
-    dma::{Dma, DmaPriority},
+    dma::Dma,
     dma_buffers,
     peripherals::Peripherals,
 };
@@ -32,11 +32,8 @@ mod tests {
 
         let (mut output, rx_descriptors, input, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
 
-        let mut aes = Aes::new(peripherals.AES).with_dma(
-            dma_channel.configure(false, DmaPriority::Priority0),
-            rx_descriptors,
-            tx_descriptors,
-        );
+        let mut aes =
+            Aes::new(peripherals.AES).with_dma(dma_channel, rx_descriptors, tx_descriptors);
 
         let keytext = b"SUp4SeCp@sSw0rd";
         let mut keybuf = [0_u8; 16];
@@ -74,11 +71,8 @@ mod tests {
 
         let (mut output, rx_descriptors, input, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
 
-        let mut aes = Aes::new(peripherals.AES).with_dma(
-            dma_channel.configure(false, DmaPriority::Priority0),
-            rx_descriptors,
-            tx_descriptors,
-        );
+        let mut aes =
+            Aes::new(peripherals.AES).with_dma(dma_channel, rx_descriptors, tx_descriptors);
 
         let keytext = b"SUp4SeCp@sSw0rd";
         let mut keybuf = [0_u8; 16];
@@ -115,11 +109,8 @@ mod tests {
 
         let (mut output, rx_descriptors, input, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
 
-        let mut aes = Aes::new(peripherals.AES).with_dma(
-            dma_channel.configure(false, DmaPriority::Priority0),
-            rx_descriptors,
-            tx_descriptors,
-        );
+        let mut aes =
+            Aes::new(peripherals.AES).with_dma(dma_channel, rx_descriptors, tx_descriptors);
 
         let keytext = b"SUp4SeCp@sSw0rd";
         let mut keybuf = [0_u8; 16];
@@ -157,11 +148,8 @@ mod tests {
 
         let (mut output, rx_descriptors, input, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
 
-        let mut aes = Aes::new(peripherals.AES).with_dma(
-            dma_channel.configure(false, DmaPriority::Priority0),
-            rx_descriptors,
-            tx_descriptors,
-        );
+        let mut aes =
+            Aes::new(peripherals.AES).with_dma(dma_channel, rx_descriptors, tx_descriptors);
 
         let keytext = b"SUp4SeCp@sSw0rd";
         let mut keybuf = [0_u8; 16];
diff --git a/hil-test/tests/dma_mem2mem.rs b/hil-test/tests/dma_mem2mem.rs
index f65873ae6c5..22555bd8b56 100644
--- a/hil-test/tests/dma_mem2mem.rs
+++ b/hil-test/tests/dma_mem2mem.rs
@@ -6,7 +6,7 @@
 #![no_main]
 
 use esp_hal::{
-    dma::{AnyGdmaChannel, Channel, Dma, DmaError, DmaPriority, Mem2Mem},
+    dma::{AnyGdmaChannel, Channel, Dma, DmaError, Mem2Mem},
     dma_buffers,
     dma_buffers_chunk_size,
     dma_descriptors,
@@ -50,9 +50,7 @@ mod tests {
         }
 
         Context {
-            channel: dma_channel
-                .configure(false, DmaPriority::Priority0)
-                .degrade(),
+            channel: dma_channel.degrade(),
             dma_peripheral,
         }
     }
diff --git a/hil-test/tests/embassy_interrupt_spi_dma.rs b/hil-test/tests/embassy_interrupt_spi_dma.rs
index 65499ab4a5b..7663c871bc8 100644
--- a/hil-test/tests/embassy_interrupt_spi_dma.rs
+++ b/hil-test/tests/embassy_interrupt_spi_dma.rs
@@ -9,7 +9,7 @@
 
 use embassy_time::{Duration, Instant, Ticker};
 use esp_hal::{
-    dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
+    dma::{Channel, Dma, DmaRxBuf, DmaTxBuf},
     dma_buffers,
     interrupt::{software::SoftwareInterruptControl, Priority},
     prelude::*,
@@ -19,6 +19,7 @@ use esp_hal::{
     },
     timer::{timg::TimerGroup, AnyTimer},
     Async,
+    Blocking,
 };
 use esp_hal_embassy::InterruptExecutor;
 use hil_test as _;
@@ -81,11 +82,13 @@ mod test {
         let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
         let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
-            .with_dma(dma_channel1.configure_for_async(false, DmaPriority::Priority0))
-            .with_buffers(dma_rx_buf, dma_tx_buf);
+            .with_dma(dma_channel1)
+            .with_buffers(dma_rx_buf, dma_tx_buf)
+            .into_async();
 
         let spi2 = Spi::new(peripherals.SPI3, 100.kHz(), SpiMode::Mode0)
-            .with_dma(dma_channel2.configure_for_async(false, DmaPriority::Priority0));
+            .with_dma(dma_channel2)
+            .into_async();
 
         let sw_ints = SoftwareInterruptControl::new(peripherals.SW_INTERRUPT);
 
@@ -120,9 +123,9 @@ mod test {
 
         cfg_if::cfg_if! {
             if #[cfg(pdma)] {
-                use esp_hal::dma::Spi2DmaChannelCreator as DmaChannelCreator;
+                use esp_hal::dma::Spi2DmaChannel as DmaChannel;
             } else {
-                type DmaChannelCreator = esp_hal::dma::ChannelCreator<0>;
+                type DmaChannel = esp_hal::dma::DmaChannel0;
             }
         }
 
@@ -131,7 +134,7 @@ mod test {
 
         pub struct SpiPeripherals {
             pub spi: SPI2,
-            pub dma_channel: DmaChannelCreator,
+            pub dma_channel: Channel<'static, DmaChannel, Blocking>,
         }
 
         #[embassy_executor::task]
@@ -141,12 +144,9 @@ mod test {
             let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
             let mut spi = Spi::new(peripherals.spi, 100.kHz(), SpiMode::Mode0)
-                .with_dma(
-                    peripherals
-                        .dma_channel
-                        .configure_for_async(false, DmaPriority::Priority0),
-                )
-                .with_buffers(dma_rx_buf, dma_tx_buf);
+                .with_dma(peripherals.dma_channel)
+                .with_buffers(dma_rx_buf, dma_tx_buf)
+                .into_async();
 
             let send_buffer = mk_static!([u8; BUFFER_SIZE], [0u8; BUFFER_SIZE]);
             loop {
diff --git a/hil-test/tests/i2s.rs b/hil-test/tests/i2s.rs
index 2420264edc5..59bfabad5f1 100644
--- a/hil-test/tests/i2s.rs
+++ b/hil-test/tests/i2s.rs
@@ -11,21 +11,22 @@
 
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority},
+    dma::{Channel, Dma},
     dma_buffers,
     gpio::{Io, NoPin},
     i2s::{DataFormat, I2s, I2sTx, Standard},
     peripherals::I2S0,
     prelude::*,
     Async,
+    Blocking,
 };
 use hil_test as _;
 
 cfg_if::cfg_if! {
     if #[cfg(any(esp32, esp32s2))] {
-        type DmaChannel0Creator = esp_hal::dma::I2s0DmaChannelCreator;
+        type DmaChannel0 = esp_hal::dma::I2s0DmaChannel;
     } else {
-        type DmaChannel0Creator = esp_hal::dma::ChannelCreator<0>;
+        type DmaChannel0 = esp_hal::dma::DmaChannel0;
     }
 }
 
@@ -103,7 +104,7 @@ mod tests {
 
     struct Context {
         io: Io,
-        dma_channel: DmaChannel0Creator,
+        dma_channel: Channel<'static, DmaChannel0, Blocking>,
         i2s: I2S0,
     }
 
@@ -142,11 +143,11 @@ mod tests {
             Standard::Philips,
             DataFormat::Data16Channel16,
             16000.Hz(),
-            ctx.dma_channel
-                .configure_for_async(false, DmaPriority::Priority0),
+            ctx.dma_channel,
             rx_descriptors,
             tx_descriptors,
-        );
+        )
+        .into_async();
 
         let (_, dout) = hil_test::common_test_pins!(ctx.io);
 
@@ -197,7 +198,7 @@ mod tests {
             Standard::Philips,
             DataFormat::Data16Channel16,
             16000.Hz(),
-            ctx.dma_channel.configure(false, DmaPriority::Priority0),
+            ctx.dma_channel,
             rx_descriptors,
             tx_descriptors,
         );
diff --git a/hil-test/tests/lcd_cam_i8080.rs b/hil-test/tests/lcd_cam_i8080.rs
index 85d5c8493b5..81d1f5ff1c1 100644
--- a/hil-test/tests/lcd_cam_i8080.rs
+++ b/hil-test/tests/lcd_cam_i8080.rs
@@ -6,7 +6,7 @@
 #![no_main]
 
 use esp_hal::{
-    dma::{Dma, DmaPriority, DmaTxBuf},
+    dma::{Dma, DmaTxBuf},
     dma_buffers,
     gpio::{Io, NoPin},
     lcd_cam::{
@@ -19,13 +19,14 @@ use esp_hal::{
         Pcnt,
     },
     prelude::*,
+    Blocking,
 };
 use hil_test as _;
 
 const DATA_SIZE: usize = 1024 * 10;
 
 struct Context<'d> {
-    lcd_cam: LcdCam<'d, esp_hal::Blocking>,
+    lcd_cam: LcdCam<'d, Blocking>,
     pcnt: Pcnt<'d>,
     io: Io,
     dma: Dma<'d>,
@@ -58,13 +59,11 @@ mod tests {
 
     #[test]
     fn test_i8080_8bit(ctx: Context<'static>) {
-        let channel = ctx.dma.channel0.configure(false, DmaPriority::Priority0);
-
         let pins = TxEightBits::new(NoPin, NoPin, NoPin, NoPin, NoPin, NoPin, NoPin, NoPin);
 
         let i8080 = I8080::new(
             ctx.lcd_cam.lcd,
-            channel.tx,
+            ctx.dma.channel0.tx,
             pins,
             20.MHz(),
             Config::default(),
@@ -76,15 +75,11 @@ mod tests {
 
     #[test]
     fn test_i8080_8bit_async_channel(ctx: Context<'static>) {
-        let channel = ctx
-            .dma
-            .channel0
-            .configure_for_async(false, DmaPriority::Priority0);
         let pins = TxEightBits::new(NoPin, NoPin, NoPin, NoPin, NoPin, NoPin, NoPin, NoPin);
 
         let i8080 = I8080::new(
             ctx.lcd_cam.lcd,
-            channel.tx,
+            ctx.dma.channel0.tx,
             pins,
             20.MHz(),
             Config::default(),
@@ -140,7 +135,6 @@ mod tests {
             .channel0
             .set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
 
-        let channel = ctx.dma.channel0.configure(false, DmaPriority::Priority0);
         let pins = TxEightBits::new(
             unit0_signal,
             unit1_signal,
@@ -154,7 +148,7 @@ mod tests {
 
         let mut i8080 = I8080::new(
             ctx.lcd_cam.lcd,
-            channel.tx,
+            ctx.dma.channel0.tx,
             pins,
             20.MHz(),
             Config::default(),
@@ -257,7 +251,7 @@ mod tests {
             .channel0
             .set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
 
-        let channel = ctx.dma.channel0.configure(false, DmaPriority::Priority0);
+        let channel = ctx.dma.channel0;
         let pins = TxSixteenBits::new(
             NoPin,
             NoPin,
diff --git a/hil-test/tests/lcd_cam_i8080_async.rs b/hil-test/tests/lcd_cam_i8080_async.rs
index c5c36d209d7..e965287ade6 100644
--- a/hil-test/tests/lcd_cam_i8080_async.rs
+++ b/hil-test/tests/lcd_cam_i8080_async.rs
@@ -7,7 +7,7 @@
 #![no_main]
 
 use esp_hal::{
-    dma::{Dma, DmaPriority, DmaTxBuf},
+    dma::{Dma, DmaTxBuf},
     dma_buffers,
     gpio::NoPin,
     lcd_cam::{
@@ -15,13 +15,14 @@ use esp_hal::{
         LcdCam,
     },
     prelude::*,
+    Async,
 };
 use hil_test as _;
 
 const DATA_SIZE: usize = 1024 * 10;
 
 struct Context<'d> {
-    lcd_cam: LcdCam<'d, esp_hal::Async>,
+    lcd_cam: LcdCam<'d, Async>,
     dma: Dma<'d>,
     dma_buf: DmaTxBuf,
 }
@@ -49,12 +50,11 @@ mod tests {
 
     #[test]
     async fn test_i8080_8bit(ctx: Context<'static>) {
-        let channel = ctx.dma.channel0.configure(false, DmaPriority::Priority0);
         let pins = TxEightBits::new(NoPin, NoPin, NoPin, NoPin, NoPin, NoPin, NoPin, NoPin);
 
         let i8080 = I8080::new(
             ctx.lcd_cam.lcd,
-            channel.tx,
+            ctx.dma.channel0.tx,
             pins,
             20.MHz(),
             Config::default(),
@@ -72,15 +72,11 @@ mod tests {
 
     #[test]
     async fn test_i8080_8bit_async_channel(ctx: Context<'static>) {
-        let channel = ctx
-            .dma
-            .channel0
-            .configure_for_async(false, DmaPriority::Priority0);
         let pins = TxEightBits::new(NoPin, NoPin, NoPin, NoPin, NoPin, NoPin, NoPin, NoPin);
 
         let i8080 = I8080::new(
             ctx.lcd_cam.lcd,
-            channel.tx,
+            ctx.dma.channel0.tx,
             pins,
             20.MHz(),
             Config::default(),
diff --git a/hil-test/tests/parl_io_tx.rs b/hil-test/tests/parl_io_tx.rs
index 3bec7b56c86..af66cdd7219 100644
--- a/hil-test/tests/parl_io_tx.rs
+++ b/hil-test/tests/parl_io_tx.rs
@@ -7,7 +7,7 @@
 #[cfg(esp32c6)]
 use esp_hal::parl_io::{TxPinConfigWithValidPin, TxSixteenBits};
 use esp_hal::{
-    dma::{ChannelCreator, Dma, DmaPriority},
+    dma::{Channel, Dma, DmaChannel0},
     gpio::{interconnect::InputSignal, AnyPin, Io, NoPin},
     parl_io::{
         BitPackOrder,
@@ -24,12 +24,13 @@ use esp_hal::{
     },
     peripherals::PARL_IO,
     prelude::*,
+    Blocking,
 };
 use hil_test as _;
 
 struct Context {
     parl_io: PARL_IO,
-    dma_channel: ChannelCreator<0>,
+    dma_channel: Channel<'static, DmaChannel0, Blocking>,
     clock: AnyPin,
     valid: AnyPin,
     clock_loopback: InputSignal,
@@ -87,13 +88,8 @@ mod tests {
         let mut pins = TxPinConfigIncludingValidPin::new(pins);
         let mut clock_pin = ClkOutPin::new(ctx.clock);
 
-        let pio = ParlIoTxOnly::new(
-            ctx.parl_io,
-            ctx.dma_channel.configure(false, DmaPriority::Priority0),
-            tx_descriptors,
-            10.MHz(),
-        )
-        .unwrap();
+        let pio =
+            ParlIoTxOnly::new(ctx.parl_io, ctx.dma_channel, tx_descriptors, 10.MHz()).unwrap();
 
         let mut pio = pio
             .tx
@@ -154,13 +150,8 @@ mod tests {
 
         let mut clock_pin = ClkOutPin::new(ctx.clock);
 
-        let pio = ParlIoTxOnly::new(
-            ctx.parl_io,
-            ctx.dma_channel.configure(false, DmaPriority::Priority0),
-            tx_descriptors,
-            10.MHz(),
-        )
-        .unwrap();
+        let pio =
+            ParlIoTxOnly::new(ctx.parl_io, ctx.dma_channel, tx_descriptors, 10.MHz()).unwrap();
 
         let mut pio = pio
             .tx
diff --git a/hil-test/tests/parl_io_tx_async.rs b/hil-test/tests/parl_io_tx_async.rs
index cdb177a4828..358f791ddc6 100644
--- a/hil-test/tests/parl_io_tx_async.rs
+++ b/hil-test/tests/parl_io_tx_async.rs
@@ -9,7 +9,7 @@
 #[cfg(esp32c6)]
 use esp_hal::parl_io::{TxPinConfigWithValidPin, TxSixteenBits};
 use esp_hal::{
-    dma::{ChannelCreator, Dma, DmaPriority},
+    dma::{Channel, Dma, DmaChannel0},
     gpio::{interconnect::InputSignal, AnyPin, Io, NoPin},
     parl_io::{
         BitPackOrder,
@@ -26,12 +26,13 @@ use esp_hal::{
     },
     peripherals::PARL_IO,
     prelude::*,
+    Async,
 };
 use hil_test as _;
 
 struct Context {
     parl_io: PARL_IO,
-    dma_channel: ChannelCreator<0>,
+    dma_channel: Channel<'static, DmaChannel0, Async>,
     clock: AnyPin,
     valid: AnyPin,
     clock_loopback: InputSignal,
@@ -59,7 +60,7 @@ mod tests {
         let pcnt = Pcnt::new(peripherals.PCNT);
         let pcnt_unit = pcnt.unit0;
         let dma = Dma::new(peripherals.DMA);
-        let dma_channel = dma.channel0;
+        let dma_channel = dma.channel0.into_async();
 
         let parl_io = peripherals.PARL_IO;
 
@@ -89,14 +90,8 @@ mod tests {
         let mut pins = TxPinConfigIncludingValidPin::new(pins);
         let mut clock_pin = ClkOutPin::new(ctx.clock);
 
-        let pio = ParlIoTxOnly::new(
-            ctx.parl_io,
-            ctx.dma_channel
-                .configure_for_async(false, DmaPriority::Priority0),
-            tx_descriptors,
-            10.MHz(),
-        )
-        .unwrap();
+        let pio =
+            ParlIoTxOnly::new(ctx.parl_io, ctx.dma_channel, tx_descriptors, 10.MHz()).unwrap();
 
         let mut pio = pio
             .tx
@@ -156,14 +151,8 @@ mod tests {
 
         let mut clock_pin = ClkOutPin::new(ctx.clock);
 
-        let pio = ParlIoTxOnly::new(
-            ctx.parl_io,
-            ctx.dma_channel
-                .configure_for_async(false, DmaPriority::Priority0),
-            tx_descriptors,
-            10.MHz(),
-        )
-        .unwrap();
+        let pio =
+            ParlIoTxOnly::new(ctx.parl_io, ctx.dma_channel, tx_descriptors, 10.MHz()).unwrap();
 
         let mut pio = pio
             .tx
diff --git a/hil-test/tests/qspi.rs b/hil-test/tests/qspi.rs
index 641098f1a62..3e8065907fb 100644
--- a/hil-test/tests/qspi.rs
+++ b/hil-test/tests/qspi.rs
@@ -8,7 +8,7 @@
 #[cfg(pcnt)]
 use esp_hal::pcnt::{channel::EdgeMode, unit::Unit, Pcnt};
 use esp_hal::{
-    dma::{Channel, Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
+    dma::{Channel, Dma, DmaRxBuf, DmaTxBuf},
     dma_buffers,
     gpio::{AnyPin, Input, Io, Level, Output, Pull},
     prelude::*,
@@ -204,8 +204,6 @@ mod tests {
             }
         }
 
-        let dma_channel = dma_channel.configure(false, DmaPriority::Priority0);
-
         Context {
             spi: peripherals.SPI2,
             #[cfg(pcnt)]
diff --git a/hil-test/tests/spi_full_duplex.rs b/hil-test/tests/spi_full_duplex.rs
index 1af4146fff1..99282f79081 100644
--- a/hil-test/tests/spi_full_duplex.rs
+++ b/hil-test/tests/spi_full_duplex.rs
@@ -12,12 +12,13 @@ use embedded_hal::spi::SpiBus;
 #[cfg(pcnt)]
 use embedded_hal_async::spi::SpiBus as SpiBusAsync;
 use esp_hal::{
-    dma::{Dma, DmaDescriptor, DmaPriority, DmaRxBuf, DmaTxBuf},
+    dma::{Channel, Dma, DmaDescriptor, DmaRxBuf, DmaTxBuf},
     dma_buffers,
     gpio::{Io, Level, NoPin},
     peripheral::Peripheral,
     prelude::*,
     spi::{master::Spi, SpiMode},
+    Blocking,
 };
 #[cfg(pcnt)]
 use esp_hal::{
@@ -28,15 +29,15 @@ use hil_test as _;
 
 cfg_if::cfg_if! {
     if #[cfg(any(esp32, esp32s2))] {
-        type DmaChannelCreator = esp_hal::dma::Spi2DmaChannelCreator;
+        type DmaChannel = esp_hal::dma::Spi2DmaChannel;
     } else {
-        type DmaChannelCreator = esp_hal::dma::ChannelCreator<0>;
+        type DmaChannel = esp_hal::dma::DmaChannel0;
     }
 }
 
 struct Context {
-    spi: Spi<'static>,
-    dma_channel: DmaChannelCreator,
+    spi: Spi<'static, Blocking>,
+    dma_channel: Channel<'static, DmaChannel, Blocking>,
     // Reuse the really large buffer so we don't run out of DRAM with many tests
     rx_buffer: &'static mut [u8],
     rx_descriptors: &'static mut [DmaDescriptor],
@@ -198,9 +199,7 @@ mod tests {
         let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
         let unit = ctx.pcnt_unit;
-        let mut spi = ctx
-            .spi
-            .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
+        let mut spi = ctx.spi.with_dma(ctx.dma_channel);
 
         unit.channel0.set_edge_signal(ctx.pcnt_source);
         unit.channel0
@@ -231,9 +230,7 @@ mod tests {
         let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
         let unit = ctx.pcnt_unit;
-        let mut spi = ctx
-            .spi
-            .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
+        let mut spi = ctx.spi.with_dma(ctx.dma_channel);
 
         unit.channel0.set_edge_signal(ctx.pcnt_source);
         unit.channel0
@@ -268,9 +265,7 @@ mod tests {
             *v = (i % 255) as u8;
         }
 
-        let mut spi = ctx
-            .spi
-            .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
+        let mut spi = ctx.spi.with_dma(ctx.dma_channel);
 
         for i in 0..4 {
             dma_tx_buf.as_mut_slice()[0] = i as u8;
@@ -298,9 +293,7 @@ mod tests {
 
         dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
 
-        let spi = ctx
-            .spi
-            .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
+        let spi = ctx.spi.with_dma(ctx.dma_channel);
         let transfer = spi
             .transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
@@ -329,7 +322,7 @@ mod tests {
 
         let mut spi = ctx
             .spi
-            .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0))
+            .with_dma(ctx.dma_channel)
             .with_buffers(dma_rx_buf, dma_tx_buf);
 
         let tx_buf = [0xde, 0xad, 0xbe, 0xef];
@@ -349,7 +342,7 @@ mod tests {
 
         let mut spi = ctx
             .spi
-            .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0))
+            .with_dma(ctx.dma_channel)
             .with_buffers(dma_rx_buf, dma_tx_buf);
 
         let tx_buf = [0xde, 0xad, 0xbe, 0xef];
@@ -371,7 +364,7 @@ mod tests {
 
         let mut spi = ctx
             .spi
-            .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0))
+            .with_dma(ctx.dma_channel)
             .with_buffers(dma_rx_buf, dma_tx_buf);
 
         let tx_buf = core::array::from_fn(|i| i as _);
@@ -392,11 +385,9 @@ mod tests {
         let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let mut spi = ctx
             .spi
-            .with_dma(
-                ctx.dma_channel
-                    .configure_for_async(false, DmaPriority::Priority0),
-            )
-            .with_buffers(dma_rx_buf, dma_tx_buf);
+            .with_dma(ctx.dma_channel)
+            .with_buffers(dma_rx_buf, dma_tx_buf)
+            .into_async();
 
         ctx.pcnt_unit.channel0.set_edge_signal(ctx.pcnt_source);
         ctx.pcnt_unit
@@ -428,10 +419,8 @@ mod tests {
         let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let mut spi = ctx
             .spi
-            .with_dma(
-                ctx.dma_channel
-                    .configure_for_async(false, DmaPriority::Priority0),
-            )
+            .into_async()
+            .with_dma(ctx.dma_channel)
             .with_buffers(dma_rx_buf, dma_tx_buf);
 
         ctx.pcnt_unit.channel0.set_edge_signal(ctx.pcnt_source);
@@ -463,7 +452,7 @@ mod tests {
             .spi
             .with_mosi(NoPin)
             .with_miso(Level::High)
-            .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
+            .with_dma(ctx.dma_channel);
 
         let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
         let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
@@ -500,9 +489,7 @@ mod tests {
         let dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
         let dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
 
-        let spi = ctx
-            .spi
-            .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
+        let spi = ctx.spi.with_dma(ctx.dma_channel);
 
         let mut transfer = spi
             .transfer(dma_rx_buf, dma_tx_buf)
@@ -523,9 +510,7 @@ mod tests {
         let mut dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
         let mut dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
 
-        let mut spi = ctx
-            .spi
-            .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
+        let mut spi = ctx.spi.with_dma(ctx.dma_channel);
 
         let mut transfer = spi
             .transfer(dma_rx_buf, dma_tx_buf)
@@ -557,10 +542,7 @@ mod tests {
         let dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
         let dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
 
-        let spi = ctx.spi.with_dma(
-            ctx.dma_channel
-                .configure_for_async(false, DmaPriority::Priority0),
-        );
+        let spi = ctx.spi.with_dma(ctx.dma_channel).into_async();
 
         let mut transfer = spi
             .transfer(dma_rx_buf, dma_tx_buf)
diff --git a/hil-test/tests/spi_half_duplex_read.rs b/hil-test/tests/spi_half_duplex_read.rs
index a50fa0dc807..6970c6d485f 100644
--- a/hil-test/tests/spi_half_duplex_read.rs
+++ b/hil-test/tests/spi_half_duplex_read.rs
@@ -6,7 +6,7 @@
 #![no_main]
 
 use esp_hal::{
-    dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
+    dma::{Dma, DmaRxBuf, DmaTxBuf},
     dma_buffers,
     gpio::{Io, Level, Output},
     prelude::*,
@@ -52,7 +52,7 @@ mod tests {
         let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
             .with_sck(sclk)
             .with_miso(miso)
-            .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
+            .with_dma(dma_channel);
 
         Context { spi, miso_mirror }
     }
diff --git a/hil-test/tests/spi_half_duplex_write.rs b/hil-test/tests/spi_half_duplex_write.rs
index a44dda26070..5a2d4f06355 100644
--- a/hil-test/tests/spi_half_duplex_write.rs
+++ b/hil-test/tests/spi_half_duplex_write.rs
@@ -6,7 +6,7 @@
 #![no_main]
 
 use esp_hal::{
-    dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
+    dma::{Dma, DmaRxBuf, DmaTxBuf},
     dma_buffers,
     gpio::{interconnect::InputSignal, Io},
     pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
@@ -55,7 +55,7 @@ mod tests {
         let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
             .with_sck(sclk)
             .with_mosi(mosi)
-            .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
+            .with_dma(dma_channel);
 
         Context {
             spi,
diff --git a/hil-test/tests/spi_half_duplex_write_psram.rs b/hil-test/tests/spi_half_duplex_write_psram.rs
index eea6b6254a6..aefaa31c71c 100644
--- a/hil-test/tests/spi_half_duplex_write_psram.rs
+++ b/hil-test/tests/spi_half_duplex_write_psram.rs
@@ -7,7 +7,7 @@
 use defmt::error;
 use esp_alloc as _;
 use esp_hal::{
-    dma::{Dma, DmaBufBlkSize, DmaPriority, DmaRxBuf, DmaTxBuf},
+    dma::{Dma, DmaBufBlkSize, DmaRxBuf, DmaTxBuf},
     dma_buffers,
     dma_descriptors_chunk_size,
     gpio::{interconnect::InputSignal, Io},
@@ -67,7 +67,7 @@ mod tests {
         let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
             .with_sck(sclk)
             .with_mosi(mosi)
-            .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
+            .with_dma(dma_channel);
 
         Context {
             spi,
diff --git a/hil-test/tests/spi_slave.rs b/hil-test/tests/spi_slave.rs
index f39791b6833..e8bc9f29546 100644
--- a/hil-test/tests/spi_slave.rs
+++ b/hil-test/tests/spi_slave.rs
@@ -9,24 +9,25 @@
 #![no_main]
 
 use esp_hal::{
-    dma::{Dma, DmaPriority},
+    dma::{Channel, Dma},
     dma_buffers,
     gpio::{interconnect::InputSignal, Io, Level, Output},
     spi::{slave::Spi, SpiMode},
+    Blocking,
 };
 use hil_test as _;
 
 cfg_if::cfg_if! {
     if #[cfg(any(esp32, esp32s2))] {
-        type DmaChannelCreator = esp_hal::dma::Spi2DmaChannelCreator;
+        type DmaChannel = esp_hal::dma::Spi2DmaChannel;
     } else {
-        type DmaChannelCreator = esp_hal::dma::ChannelCreator<0>;
+        type DmaChannel = esp_hal::dma::DmaChannel0;
     }
 }
 
 struct Context {
-    spi: Spi<'static>,
-    dma_channel: DmaChannelCreator,
+    spi: Spi<'static, Blocking>,
+    dma_channel: Channel<'static, DmaChannel, Blocking>,
     bitbang_spi: BitbangSpi,
 }
 
@@ -149,11 +150,9 @@ mod tests {
     fn test_basic(mut ctx: Context) {
         const DMA_SIZE: usize = 32;
         let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_SIZE);
-        let mut spi = ctx.spi.with_dma(
-            ctx.dma_channel.configure(false, DmaPriority::Priority0),
-            rx_descriptors,
-            tx_descriptors,
-        );
+        let mut spi = ctx
+            .spi
+            .with_dma(ctx.dma_channel, rx_descriptors, tx_descriptors);
         let slave_send = tx_buffer;
         let slave_receive = rx_buffer;