+ 'd) -> Self { + pub fn new(rtc_cntl: impl Peripheral
+ 'd) -> Self { rtc::init(); rtc::configure_clock(); diff --git a/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs b/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs index e6a7232b9db..5235f1cb8bf 100644 --- a/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs +++ b/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs @@ -3,7 +3,7 @@ use strum::FromRepr; use crate::{ clock::{clocks_ll::regi2c_write_mask, Clock, XtalClock}, - peripherals::{LP_AON, LP_CLKRST, PCR, PMU, TIMG0}, + peripherals::{LP_AON, PCR, PMU, RTC_CNTL, TIMG0}, soc::efuse::{Efuse, WAFER_VERSION_MAJOR, WAFER_VERSION_MINOR}, }; @@ -106,7 +106,7 @@ pub(crate) fn configure_clock() { fn modem_clk_domain_active_state_icg_map_preinit() { unsafe { let pmu = &*PMU::PTR; - let lp_clkrst = &*LP_CLKRST::PTR; + let rtc_cntl = &*RTC_CNTL::PTR; let pcr = &*PCR::PTR; pmu.hp_active_icg_modem @@ -132,7 +132,7 @@ fn modem_clk_domain_active_state_icg_map_preinit() { pmu.imm_sleep_sysclk .write(|w| w.update_dig_icg_switch().set_bit()); - lp_clkrst.fosc_cntl.modify(|_, w| w.fosc_dfreq().bits(100)); + rtc_cntl.fosc_cntl.modify(|_, w| w.fosc_dfreq().bits(100)); regi2c_write_mask( I2C_DIG_REG, I2C_DIG_REG_HOSTID, @@ -141,9 +141,7 @@ fn modem_clk_domain_active_state_icg_map_preinit() { I2C_DIG_REG_SCK_DCAP_LSB, 128, ); - lp_clkrst - .rc32k_cntl - .modify(|_, w| w.rc32k_dfreq().bits(100)); + rtc_cntl.rc32k_cntl.modify(|_, w| w.rc32k_dfreq().bits(100)); // https://github.com/espressif/esp-idf/commit/e3148369f32fdc6de62c35a67f7adb6f4faef4e3#diff-cc84d279f2f3d77fe252aa40a64d4813f271a52b5a4055e876efd012d888e135R810-R815 pcr.ctrl_tick_conf @@ -307,7 +305,7 @@ impl RtcClock { /// Get the RTC_SLOW_CLK source pub(crate) fn get_slow_freq() -> RtcSlowClock { - let lp_clrst = unsafe { &*LP_CLKRST::ptr() }; + let lp_clrst = unsafe { &*RTC_CNTL::ptr() }; let slow_freq = lp_clrst.lp_clk_conf.read().slow_clk_sel().bits(); match slow_freq { @@ -321,12 +319,12 @@ impl RtcClock { fn set_slow_freq(slow_freq: RtcSlowClock) { unsafe { - let lp_clkrst = &*LP_CLKRST::PTR; + let rtc_cntl = &*RTC_CNTL::PTR; - lp_clkrst + rtc_cntl .lp_clk_conf .modify(|_, w| w.slow_clk_sel().bits(slow_freq as u8)); - lp_clkrst.clk_to_hp.modify(|_, w| { + rtc_cntl.clk_to_hp.modify(|_, w| { w.icg_hp_xtal32k() .bit(match slow_freq { RtcSlowClock::RtcSlowClock32kXtal => true, @@ -346,8 +344,8 @@ impl RtcClock { // stage bootloader https://github.com/espressif/esp-idf/blob/master/components/bootloader_support/src/bootloader_clock_init.c#L65-L67 fn set_fast_freq(fast_freq: RtcFastClock) { unsafe { - let lp_clkrst = &*LP_CLKRST::PTR; - lp_clkrst.lp_clk_conf.modify(|_, w| { + let rtc_cntl = &*RTC_CNTL::PTR; + rtc_cntl.lp_clk_conf.modify(|_, w| { w.fast_clk_sel().bit(match fast_freq { RtcFastClock::RtcFastClockRcFast => false, RtcFastClock::RtcFastClockXtalD2 => true, @@ -377,7 +375,7 @@ impl RtcClock { }; } - let lp_clkrst = unsafe { &*LP_CLKRST::ptr() }; + let rtc_cntl = unsafe { &*RTC_CNTL::ptr() }; let pcr = unsafe { &*PCR::ptr() }; let pmu = unsafe { &*PMU::ptr() }; @@ -427,17 +425,17 @@ impl RtcClock { // Only enable if originaly was disabled // If clock is already on, do nothing - let dig_32k_xtal_enabled = lp_clkrst.clk_to_hp.read().icg_hp_xtal32k().bit_is_set(); + let dig_32k_xtal_enabled = rtc_cntl.clk_to_hp.read().icg_hp_xtal32k().bit_is_set(); if cal_clk == RtcCalSel::RtcCal32kXtal && !dig_32k_xtal_enabled { - lp_clkrst + rtc_cntl .clk_to_hp .modify(|_, w| w.icg_hp_xtal32k().set_bit()); } // TODO: very hacky // in ESP-IDF these are not called in this function but the fields are set - lp_clkrst + rtc_cntl .clk_to_hp .modify(|_, w| w.icg_hp_xtal32k().set_bit()); pmu.hp_sleep_lp_ck_power @@ -451,7 +449,7 @@ impl RtcClock { .read() .hp_sleep_xpd_fosc_clk() .bit_is_set(); - let dig_rc_fast_enabled = lp_clkrst.clk_to_hp.read().icg_hp_fosc().bit_is_set(); + let dig_rc_fast_enabled = rtc_cntl.clk_to_hp.read().icg_hp_fosc().bit_is_set(); if cal_clk == RtcCalSel::RtcCalRcFast { if !rc_fast_enabled { @@ -463,7 +461,7 @@ impl RtcClock { } if !dig_rc_fast_enabled { - lp_clkrst.clk_to_hp.modify(|_, w| w.icg_hp_fosc().set_bit()); + rtc_cntl.clk_to_hp.modify(|_, w| w.icg_hp_fosc().set_bit()); unsafe { ets_delay_us(5); } @@ -475,7 +473,7 @@ impl RtcClock { .read() .hp_sleep_xpd_rc32k() .bit_is_set(); - let dig_rc32k_enabled = lp_clkrst.clk_to_hp.read().icg_hp_osc32k().bit_is_set(); + let dig_rc32k_enabled = rtc_cntl.clk_to_hp.read().icg_hp_osc32k().bit_is_set(); if cal_clk == RtcCalSel::RtcCal32kRc { if !rc32k_enabled { @@ -487,7 +485,7 @@ impl RtcClock { } if !dig_rc32k_enabled { - lp_clkrst + rtc_cntl .clk_to_hp .modify(|_, w| w.icg_hp_osc32k().set_bit()); } @@ -593,7 +591,7 @@ impl RtcClock { .modify(|_, w| w.rtc_cali_start().clear_bit()); if cal_clk == RtcCalSel::RtcCal32kXtal && !dig_32k_xtal_enabled { - lp_clkrst + rtc_cntl .clk_to_hp .modify(|_, w| w.icg_hp_xtal32k().clear_bit()); } @@ -608,7 +606,7 @@ impl RtcClock { } if dig_rc_fast_enabled { - lp_clkrst.clk_to_hp.modify(|_, w| w.icg_hp_fosc().set_bit()); + rtc_cntl.clk_to_hp.modify(|_, w| w.icg_hp_fosc().set_bit()); unsafe { ets_delay_us(5); } @@ -624,7 +622,7 @@ impl RtcClock { } } if dig_rc32k_enabled { - lp_clkrst + rtc_cntl .clk_to_hp .modify(|_, w| w.icg_hp_osc32k().set_bit()); } diff --git a/esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs b/esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs index 364efd34387..f41dba6eb0e 100644 --- a/esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs +++ b/esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs @@ -3,7 +3,7 @@ use strum::FromRepr; use crate::{ clock::{clocks_ll::regi2c_write_mask, Clock, XtalClock}, - peripherals::{LP_AON, LP_CLKRST, PCR, PMU, TIMG0}, + peripherals::{LP_AON, PCR, PMU, RTC_CNTL, TIMG0}, }; const I2C_PMU: u8 = 0x6d; @@ -306,8 +306,8 @@ impl RtcClock { fn set_fast_freq(fast_freq: RtcFastClock) { // components/hal/esp32s2/include/hal/clk_tree_ll.h unsafe { - let lp_clkrst = &*LP_CLKRST::PTR; - lp_clkrst.lp_clk_conf.modify(|_, w| { + let rtc_cntl = &*RTC_CNTL::PTR; + rtc_cntl.lp_clk_conf.modify(|_, w| { w.fast_clk_sel().bits(match fast_freq { RtcFastClock::RtcFastClockRcFast => 0b00, RtcFastClock::RtcFastClockXtalD2 => 0b01, @@ -319,12 +319,12 @@ impl RtcClock { fn set_slow_freq(slow_freq: RtcSlowClock) { unsafe { - let lp_clkrst = &*LP_CLKRST::PTR; + let rtc_cntl = &*RTC_CNTL::PTR; - lp_clkrst + rtc_cntl .lp_clk_conf .modify(|_, w| w.slow_clk_sel().bits(slow_freq as u8)); - lp_clkrst.clk_to_hp.modify(|_, w| { + rtc_cntl.clk_to_hp.modify(|_, w| { w.icg_hp_xtal32k() .bit(match slow_freq { RtcSlowClock::RtcSlowClock32kXtal => true, @@ -341,7 +341,7 @@ impl RtcClock { /// Get the RTC_SLOW_CLK source pub(crate) fn get_slow_freq() -> RtcSlowClock { - let lp_clrst = unsafe { &*LP_CLKRST::ptr() }; + let lp_clrst = unsafe { &*RTC_CNTL::ptr() }; let slow_freq = lp_clrst.lp_clk_conf.read().slow_clk_sel().bits(); match slow_freq { @@ -382,7 +382,7 @@ impl RtcClock { }; } - let lp_clkrst = unsafe { &*LP_CLKRST::ptr() }; + let rtc_cntl = unsafe { &*RTC_CNTL::ptr() }; let pcr = unsafe { &*PCR::ptr() }; let pmu = unsafe { &*PMU::ptr() }; @@ -432,17 +432,17 @@ impl RtcClock { // Only enable if originaly was disabled // If clock is already on, do nothing - let dig_32k_xtal_enabled = lp_clkrst.clk_to_hp.read().icg_hp_xtal32k().bit_is_set(); + let dig_32k_xtal_enabled = rtc_cntl.clk_to_hp.read().icg_hp_xtal32k().bit_is_set(); if cal_clk == RtcCalSel::RtcCal32kXtal && !dig_32k_xtal_enabled { - lp_clkrst + rtc_cntl .clk_to_hp .modify(|_, w| w.icg_hp_xtal32k().set_bit()); } // TODO: very hacky // in ESP-IDF these are not called in this function but the fields are set - lp_clkrst + rtc_cntl .clk_to_hp .modify(|_, w| w.icg_hp_xtal32k().set_bit()); pmu.hp_sleep_lp_ck_power @@ -456,7 +456,7 @@ impl RtcClock { .read() .hp_sleep_xpd_fosc_clk() .bit_is_set(); - let dig_rc_fast_enabled = lp_clkrst.clk_to_hp.read().icg_hp_fosc().bit_is_set(); + let dig_rc_fast_enabled = rtc_cntl.clk_to_hp.read().icg_hp_fosc().bit_is_set(); if cal_clk == RtcCalSel::RtcCalRcFast { if !rc_fast_enabled { @@ -468,7 +468,7 @@ impl RtcClock { } if !dig_rc_fast_enabled { - lp_clkrst.clk_to_hp.modify(|_, w| w.icg_hp_fosc().set_bit()); + rtc_cntl.clk_to_hp.modify(|_, w| w.icg_hp_fosc().set_bit()); unsafe { ets_delay_us(5); } @@ -480,7 +480,7 @@ impl RtcClock { .read() .hp_sleep_xpd_rc32k() .bit_is_set(); - let dig_rc32k_enabled = lp_clkrst.clk_to_hp.read().icg_hp_osc32k().bit_is_set(); + let dig_rc32k_enabled = rtc_cntl.clk_to_hp.read().icg_hp_osc32k().bit_is_set(); if cal_clk == RtcCalSel::RtcCal32kRc { if !rc32k_enabled { @@ -492,7 +492,7 @@ impl RtcClock { } if !dig_rc32k_enabled { - lp_clkrst + rtc_cntl .clk_to_hp .modify(|_, w| w.icg_hp_osc32k().set_bit()); } @@ -581,7 +581,7 @@ impl RtcClock { .modify(|_, w| w.rtc_cali_start().clear_bit()); if cal_clk == RtcCalSel::RtcCal32kXtal && !dig_32k_xtal_enabled { - lp_clkrst + rtc_cntl .clk_to_hp .modify(|_, w| w.icg_hp_xtal32k().clear_bit()); } @@ -596,7 +596,7 @@ impl RtcClock { } if dig_rc_fast_enabled { - lp_clkrst.clk_to_hp.modify(|_, w| w.icg_hp_fosc().set_bit()); + rtc_cntl.clk_to_hp.modify(|_, w| w.icg_hp_fosc().set_bit()); unsafe { ets_delay_us(5); } @@ -612,7 +612,7 @@ impl RtcClock { } } if dig_rc32k_enabled { - lp_clkrst + rtc_cntl .clk_to_hp .modify(|_, w| w.icg_hp_osc32k().set_bit()); } diff --git a/esp-hal-common/src/soc/esp32c6/peripherals.rs b/esp-hal-common/src/soc/esp32c6/peripherals.rs index b51aea9c55c..b4987f7c4b8 100644 --- a/esp-hal-common/src/soc/esp32c6/peripherals.rs +++ b/esp-hal-common/src/soc/esp32c6/peripherals.rs @@ -55,7 +55,8 @@ crate::peripherals! { LP_AON <= LP_AON, LP_APM <= LP_APM, LP_APM0 <= LP_APM0, - LP_CLKRST <= LP_CLKRST, + // RTC_CNTL is derived from LP_CLKRST + RTC_CNTL <= LP_CLKRST, LP_I2C0 <= LP_I2C0, LP_I2C_ANA_MST <= LP_I2C_ANA_MST, LP_IO <= LP_IO, diff --git a/esp-hal-common/src/soc/esp32h2/peripherals.rs b/esp-hal-common/src/soc/esp32h2/peripherals.rs index e8efe4a7803..ab5066e9ccd 100644 --- a/esp-hal-common/src/soc/esp32h2/peripherals.rs +++ b/esp-hal-common/src/soc/esp32h2/peripherals.rs @@ -50,7 +50,8 @@ crate::peripherals! { LP_ANA <= LP_ANA, LP_AON <= LP_AON, LP_APM <= LP_APM, - LP_CLKRST <= LP_CLKRST, + // RTC_CNTL is derived from LP_CLKRST + RTC_CNTL <= LP_CLKRST, LP_PERI <= LP_PERI, LP_TIMER <= LP_TIMER, LP_WDT <= LP_WDT, diff --git a/esp32c6-hal/examples/parl_io_rx.rs b/esp32c6-hal/examples/parl_io_rx.rs index 3a53718d39f..3c5019df392 100644 --- a/esp32c6-hal/examples/parl_io_rx.rs +++ b/esp32c6-hal/examples/parl_io_rx.rs @@ -28,7 +28,7 @@ fn main() -> ! { let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); // Disable the watchdog timers. - let mut rtc = Rtc::new(peripherals.LP_CLKRST); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks); let mut wdt0 = timer_group0.wdt; let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks); diff --git a/esp32c6-hal/examples/ram.rs b/esp32c6-hal/examples/ram.rs index f583deb9a87..b83d3eecc3f 100644 --- a/esp32c6-hal/examples/ram.rs +++ b/esp32c6-hal/examples/ram.rs @@ -40,7 +40,7 @@ fn main() -> ! { // The RWDT flash boot protection must be enabled, as it is triggered as part of // the example. - let mut rtc = Rtc::new(peripherals.LP_CLKRST); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); rtc.rwdt.enable(); timer0.start(1u64.secs()); diff --git a/esp32c6-hal/examples/rtc_time.rs b/esp32c6-hal/examples/rtc_time.rs index 906a9897b5b..9fbc075c3f8 100644 --- a/esp32c6-hal/examples/rtc_time.rs +++ b/esp32c6-hal/examples/rtc_time.rs @@ -12,7 +12,7 @@ fn main() -> ! { let system = peripherals.SYSTEM.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let rtc = Rtc::new(peripherals.LP_CLKRST); + let rtc = Rtc::new(peripherals.RTC_CNTL); let mut delay = Delay::new(&clocks); loop { diff --git a/esp32c6-hal/examples/rtc_watchdog.rs b/esp32c6-hal/examples/rtc_watchdog.rs index df422c6dad7..93d58bbe190 100644 --- a/esp32c6-hal/examples/rtc_watchdog.rs +++ b/esp32c6-hal/examples/rtc_watchdog.rs @@ -28,7 +28,7 @@ fn main() -> ! { let system = peripherals.SYSTEM.split(); let _clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let mut rtc = Rtc::new(peripherals.LP_CLKRST); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); rtc.rwdt.start(2000u64.millis()); rtc.rwdt.listen(); diff --git a/esp32c6-hal/examples/spi_slave_dma.rs b/esp32c6-hal/examples/spi_slave_dma.rs index 7b7965b0499..71c4820f212 100644 --- a/esp32c6-hal/examples/spi_slave_dma.rs +++ b/esp32c6-hal/examples/spi_slave_dma.rs @@ -48,7 +48,7 @@ fn main() -> ! { // Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT, // the RTC WDT, and the TIMG WDTs. - let mut rtc = Rtc::new(peripherals.LP_CLKRST); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks); let mut wdt0 = timer_group0.wdt; let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks); diff --git a/esp32c6-hal/src/lib.rs b/esp32c6-hal/src/lib.rs index c42c9a8987b..58adb29be72 100644 --- a/esp32c6-hal/src/lib.rs +++ b/esp32c6-hal/src/lib.rs @@ -81,12 +81,12 @@ pub mod analog { #[export_name = "__post_init"] unsafe fn post_init() { use esp_hal_common::{ - peripherals::{LP_CLKRST, TIMG0, TIMG1}, + peripherals::{RTC_CNTL, TIMG0, TIMG1}, timer::Wdt, }; // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LP_CLKRST::steal()); + let mut rtc = Rtc::new(RTC_CNTL::steal()); rtc.swd.disable(); rtc.rwdt.disable(); diff --git a/esp32h2-hal/examples/parl_io_rx.rs b/esp32h2-hal/examples/parl_io_rx.rs index 44bd02dd615..2ebd9834b16 100644 --- a/esp32h2-hal/examples/parl_io_rx.rs +++ b/esp32h2-hal/examples/parl_io_rx.rs @@ -28,7 +28,7 @@ fn main() -> ! { let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); // Disable the watchdog timers. - let mut rtc = Rtc::new(peripherals.LP_CLKRST); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks); let mut wdt0 = timer_group0.wdt; let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks); diff --git a/esp32h2-hal/examples/ram.rs b/esp32h2-hal/examples/ram.rs index f92b090df67..c17d4af501f 100644 --- a/esp32h2-hal/examples/ram.rs +++ b/esp32h2-hal/examples/ram.rs @@ -40,7 +40,7 @@ fn main() -> ! { // The RWDT flash boot protection must be enabled, as it is triggered as part of // the example. - let mut rtc = Rtc::new(peripherals.LP_CLKRST); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); rtc.rwdt.enable(); timer0.start(1u64.secs()); diff --git a/esp32h2-hal/examples/rtc_time.rs b/esp32h2-hal/examples/rtc_time.rs index f79a7b5510b..f192c81a59e 100644 --- a/esp32h2-hal/examples/rtc_time.rs +++ b/esp32h2-hal/examples/rtc_time.rs @@ -12,7 +12,7 @@ fn main() -> ! { let system = peripherals.SYSTEM.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let rtc = Rtc::new(peripherals.LP_CLKRST); + let rtc = Rtc::new(peripherals.RTC_CNTL); let mut delay = Delay::new(&clocks); loop { diff --git a/esp32h2-hal/examples/rtc_watchdog.rs b/esp32h2-hal/examples/rtc_watchdog.rs index fcb85066e58..1a31fa7ff14 100644 --- a/esp32h2-hal/examples/rtc_watchdog.rs +++ b/esp32h2-hal/examples/rtc_watchdog.rs @@ -28,7 +28,7 @@ fn main() -> ! { let system = peripherals.SYSTEM.split(); let _clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let mut rtc = Rtc::new(peripherals.LP_CLKRST); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); rtc.rwdt.start(2000u64.millis()); rtc.rwdt.listen(); diff --git a/esp32h2-hal/examples/spi_slave_dma.rs b/esp32h2-hal/examples/spi_slave_dma.rs index 088078a856b..cb335c24a51 100644 --- a/esp32h2-hal/examples/spi_slave_dma.rs +++ b/esp32h2-hal/examples/spi_slave_dma.rs @@ -48,7 +48,7 @@ fn main() -> ! { // Disable the watchdog timers. For the ESP32-C6, this includes the Super WDT, // the RTC WDT, and the TIMG WDTs. - let mut rtc = Rtc::new(peripherals.LP_CLKRST); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks); let mut wdt0 = timer_group0.wdt; let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks); diff --git a/esp32h2-hal/src/lib.rs b/esp32h2-hal/src/lib.rs index aba1a361953..722e634a330 100644 --- a/esp32h2-hal/src/lib.rs +++ b/esp32h2-hal/src/lib.rs @@ -81,12 +81,12 @@ pub mod analog { #[export_name = "__post_init"] unsafe fn post_init() { use esp_hal_common::{ - peripherals::{LP_CLKRST, TIMG0, TIMG1}, + peripherals::{RTC_CNTL, TIMG0, TIMG1}, timer::Wdt, }; // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LP_CLKRST::steal()); + let mut rtc = Rtc::new(RTC_CNTL::steal()); rtc.swd.disable(); rtc.rwdt.disable();