diff --git a/esp-hal/src/dma/mod.rs b/esp-hal/src/dma/mod.rs
index 11d53f73b1..447f605142 100644
--- a/esp-hal/src/dma/mod.rs
+++ b/esp-hal/src/dma/mod.rs
@@ -228,7 +228,14 @@ impl Debug for DmaDescriptorFlags {
 #[cfg(feature = "defmt")]
 impl defmt::Format for DmaDescriptorFlags {
     fn format(&self, fmt: defmt::Formatter<'_>) {
-        defmt::write!(fmt, "DmaDescriptorFlags {{ size: {}, length: {}, suc_eof: {}, owner: {} }}", self.size(), self.length(), self.suc_eof(), if self.owner() { "DMA" } else { "CPU" });
+        defmt::write!(
+            fmt,
+            "DmaDescriptorFlags {{ size: {}, length: {}, suc_eof: {}, owner: {} }}",
+            self.size(),
+            self.length(),
+            self.suc_eof(),
+            if self.owner() { "DMA" } else { "CPU" }
+        );
     }
 }
 
@@ -1968,7 +1975,8 @@ where
 /// Holds all the information needed to configure a DMA channel for a transfer.
 pub struct Preparation {
     start: *mut DmaDescriptor,
-    /// block size for PSRAM transfers (TODO: enable burst mode for non external memory?)
+    /// block size for PSRAM transfers (TODO: enable burst mode for non external
+    /// memory?)
     block_size: Option<DmaBufBlkSize>,
     // burst_mode, alignment, check_owner, etc.
 }
@@ -2039,8 +2047,8 @@ pub enum DmaBufBlkSize {
 /// DMA transmit buffer
 ///
 /// This is a contiguous buffer linked together by DMA descriptors of length
-/// 4092 at most. It can only be used for transmitting data to a peripheral's FIFO.
-/// See [DmaRxBuf] for receiving data.
+/// 4092 at most. It can only be used for transmitting data to a peripheral's
+/// FIFO. See [DmaRxBuf] for receiving data.
 #[derive(Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct DmaTxBuf {
@@ -2212,7 +2220,12 @@ impl DmaTxBuffer for DmaTxBuf {
 
         #[cfg(esp32s3)]
         if crate::soc::is_valid_psram_address(self.buffer.as_ptr() as u32) {
-            unsafe {crate::soc::cache_writeback_addr(self.buffer.as_ptr() as u32, self.buffer.len() as u32)};
+            unsafe {
+                crate::soc::cache_writeback_addr(
+                    self.buffer.as_ptr() as u32,
+                    self.buffer.len() as u32,
+                )
+            };
         }
 
         Preparation {
diff --git a/examples/src/bin/spi_loopback_dma_psram.rs b/examples/src/bin/spi_loopback_dma_psram.rs
index fddaf0a464..3c31349ed6 100644
--- a/examples/src/bin/spi_loopback_dma_psram.rs
+++ b/examples/src/bin/spi_loopback_dma_psram.rs
@@ -22,7 +22,7 @@
 use esp_backtrace as _;
 use esp_hal::{
     delay::Delay,
-    dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf, DmaBufBlkSize},
+    dma::{Dma, DmaBufBlkSize, DmaPriority, DmaRxBuf, DmaTxBuf},
     gpio::Io,
     prelude::*,
     spi::{master::Spi, SpiMode},
@@ -47,7 +47,7 @@ macro_rules! dma_alloc_buffer {
 // TODO: the fist transfer fails in some conditions:
 // - if this is <= 8192 when chunk_size is 4032!?!?
 // - varing either DMA_CHUNK_SIZE or DMA_BUFFER_SIZE seems change the behavior
-const DMA_BUFFER_SIZE: usize = 16384; // the first request fails is this is <= 8192 when chunk_size is 4032!?!? 
+const DMA_BUFFER_SIZE: usize = 16384; // the first request fails is this is <= 8192 when chunk_size is 4032!?!?
 const DMA_CHUNK_SIZE: usize = 4032; // size is aligned to 64 bytes
 const DMA_ALIGNMENT: DmaBufBlkSize = DmaBufBlkSize::Size16;
 
@@ -68,12 +68,29 @@ fn main() -> ! {
     let dma = Dma::new(peripherals.DMA);
     let dma_channel = dma.channel0;
 
-    let (_, tx_descriptors) = esp_hal::dma_descriptors_chunk_size!(0, DMA_BUFFER_SIZE, DMA_CHUNK_SIZE);
+    let (_, tx_descriptors) =
+        esp_hal::dma_descriptors_chunk_size!(0, DMA_BUFFER_SIZE, DMA_CHUNK_SIZE);
     let tx_buffer = dma_alloc_buffer!(DMA_BUFFER_SIZE, DMA_ALIGNMENT as usize);
-    info!("TX: {:p} len {} ({} descripters)", tx_buffer.as_ptr(), tx_buffer.len(), tx_descriptors.len());
-    let mut dma_tx_buf = DmaTxBuf::new_with_chunk_size(tx_descriptors, tx_buffer, DMA_CHUNK_SIZE, Some(DMA_ALIGNMENT)).unwrap();
+    info!(
+        "TX: {:p} len {} ({} descripters)",
+        tx_buffer.as_ptr(),
+        tx_buffer.len(),
+        tx_descriptors.len()
+    );
+    let mut dma_tx_buf = DmaTxBuf::new_with_chunk_size(
+        tx_descriptors,
+        tx_buffer,
+        DMA_CHUNK_SIZE,
+        Some(DMA_ALIGNMENT),
+    )
+    .unwrap();
     let (rx_buffer, rx_descriptors, _, _) = esp_hal::dma_buffers!(DMA_BUFFER_SIZE, 0);
-    info!("RX: {:p} len {} ({} descripters)", rx_buffer.as_ptr(), rx_buffer.len(), rx_descriptors.len());
+    info!(
+        "RX: {:p} len {} ({} descripters)",
+        rx_buffer.as_ptr(),
+        rx_buffer.len(),
+        rx_descriptors.len()
+    );
     let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
     let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
         .with_pins(sclk, mosi, miso, cs)
@@ -100,7 +117,12 @@ fn main() -> ! {
         (spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
         for (i, v) in dma_tx_buf.as_mut_slice().iter_mut().enumerate() {
             if dma_rx_buf.as_slice()[i] != *v {
-                error!("Mismatch at index {}: expected {}, got {}", i, *v, dma_rx_buf.as_slice()[i]);
+                error!(
+                    "Mismatch at index {}: expected {}, got {}",
+                    i,
+                    *v,
+                    dma_rx_buf.as_slice()[i]
+                );
                 break;
             }
         }
diff --git a/hil-test/tests/spi_half_duplex_write_psram.rs b/hil-test/tests/spi_half_duplex_write_psram.rs
index 495387c821..0a9dbe86b4 100644
--- a/hil-test/tests/spi_half_duplex_write_psram.rs
+++ b/hil-test/tests/spi_half_duplex_write_psram.rs
@@ -6,7 +6,7 @@
 #![no_main]
 use esp_alloc as _;
 use esp_hal::{
-    dma::{Dma, DmaPriority, DmaTxBuf, DmaBufBlkSize},
+    dma::{Dma, DmaBufBlkSize, DmaPriority, DmaTxBuf},
     dma_descriptors_chunk_size,
     gpio::{interconnect::InputSignal, Io},
     pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
@@ -107,7 +107,9 @@ mod tests {
 
         let (_, descriptors) = dma_descriptors_chunk_size!(0, DMA_BUFFER_SIZE, DMA_CHUNK_SIZE);
         let buffer = dma_alloc_buffer!(DMA_BUFFER_SIZE, DMA_ALIGNMENT as usize);
-        let mut dma_tx_buf = DmaTxBuf::new_with_chunk_size(descriptors, buffer, DMA_CHUNK_SIZE, Some(DMA_ALIGNMENT)).unwrap();
+        let mut dma_tx_buf =
+            DmaTxBuf::new_with_chunk_size(descriptors, buffer, DMA_CHUNK_SIZE, Some(DMA_ALIGNMENT))
+                .unwrap();
 
         let unit = ctx.pcnt_unit;
         let mut spi = ctx.spi;
@@ -153,9 +155,10 @@ mod tests {
     // fn test_spidmabus_writes_are_correctly_by_pcnt(ctx: Context) {
     //     const DMA_BUFFER_SIZE: usize = 64;
 
-    //     let (rx, rxd, buffer, descriptors) = dma_buffers!(1, DMA_BUFFER_SIZE);
-    //     let dma_rx_buf = DmaRxBuf::new(rxd, rx).unwrap();
-    //     let dma_tx_buf = DmaTxBuf::new(descriptors, buffer).unwrap();
+    //     let (rx, rxd, buffer, descriptors) = dma_buffers!(1,
+    // DMA_BUFFER_SIZE);     let dma_rx_buf = DmaRxBuf::new(rxd,
+    // rx).unwrap();     let dma_tx_buf = DmaTxBuf::new(descriptors,
+    // buffer).unwrap();
 
     //     let unit = ctx.pcnt_unit;
     //     let mut spi = ctx.spi.with_buffers(dma_rx_buf, dma_tx_buf);